1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
6 #include <rte_bus_pci.h>
7 #include <rte_ethdev_pci.h>
11 #include "hns3_ethdev.h"
12 #include "hns3_logs.h"
13 #include "hns3_rxtx.h"
14 #include "hns3_intr.h"
15 #include "hns3_regs.h"
19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
22 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
23 #define HNS3_INVALID_PVID 0xFFFF
25 #define HNS3_FILTER_TYPE_VF 0
26 #define HNS3_FILTER_TYPE_PORT 1
27 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
28 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
29 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
30 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
31 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
32 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
33 | HNS3_FILTER_FE_ROCE_EGRESS_B)
34 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
35 | HNS3_FILTER_FE_ROCE_INGRESS_B)
37 /* Reset related Registers */
38 #define HNS3_GLOBAL_RESET_BIT 0
39 #define HNS3_CORE_RESET_BIT 1
40 #define HNS3_IMP_RESET_BIT 2
41 #define HNS3_FUN_RST_ING_B 0
43 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
44 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
45 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U
46 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
48 #define HNS3_RESET_WAIT_MS 100
49 #define HNS3_RESET_WAIT_CNT 200
51 /* FEC mode order defined in HNS3 hardware */
52 #define HNS3_HW_FEC_MODE_NOFEC 0
53 #define HNS3_HW_FEC_MODE_BASER 1
54 #define HNS3_HW_FEC_MODE_RS 2
57 HNS3_VECTOR0_EVENT_RST,
58 HNS3_VECTOR0_EVENT_MBX,
59 HNS3_VECTOR0_EVENT_ERR,
60 HNS3_VECTOR0_EVENT_OTHER,
63 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
64 { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
65 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
66 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
68 { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
69 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
70 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
71 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
73 { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
74 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
75 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
77 { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
78 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
79 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
80 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
82 { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
83 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
84 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
86 { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
87 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
88 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
91 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
93 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
94 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
96 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
98 static int hns3_add_mc_addr(struct hns3_hw *hw,
99 struct rte_ether_addr *mac_addr);
100 static int hns3_remove_mc_addr(struct hns3_hw *hw,
101 struct rte_ether_addr *mac_addr);
102 static int hns3_restore_fec(struct hns3_hw *hw);
103 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
105 void hns3_ether_format_addr(char *buf, uint16_t size,
106 const struct rte_ether_addr *ether_addr)
108 snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
109 ether_addr->addr_bytes[0],
110 ether_addr->addr_bytes[4],
111 ether_addr->addr_bytes[5]);
115 hns3_pf_disable_irq0(struct hns3_hw *hw)
117 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
121 hns3_pf_enable_irq0(struct hns3_hw *hw)
123 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
126 static enum hns3_evt_cause
127 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
129 struct hns3_hw *hw = &hns->hw;
130 uint32_t vector0_int_stats;
131 uint32_t cmdq_src_val;
132 uint32_t hw_err_src_reg;
134 enum hns3_evt_cause ret;
136 /* fetch the events from their corresponding regs */
137 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
138 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
139 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
142 * Assumption: If by any chance reset and mailbox events are reported
143 * together then we will only process reset event and defer the
144 * processing of the mailbox events. Since, we would have not cleared
145 * RX CMDQ event this time we would receive again another interrupt
146 * from H/W just for the mailbox.
148 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
149 rte_atomic16_set(&hw->reset.disable_cmd, 1);
150 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
151 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
153 hw->reset.stats.imp_cnt++;
154 hns3_warn(hw, "IMP reset detected, clear reset status");
156 hns3_schedule_delayed_reset(hns);
157 hns3_warn(hw, "IMP reset detected, don't clear reset status");
160 ret = HNS3_VECTOR0_EVENT_RST;
165 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
166 rte_atomic16_set(&hw->reset.disable_cmd, 1);
167 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
168 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
170 hw->reset.stats.global_cnt++;
171 hns3_warn(hw, "Global reset detected, clear reset status");
173 hns3_schedule_delayed_reset(hns);
174 hns3_warn(hw, "Global reset detected, don't clear reset status");
177 ret = HNS3_VECTOR0_EVENT_RST;
181 /* check for vector0 msix event source */
182 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
183 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
184 val = vector0_int_stats | hw_err_src_reg;
185 ret = HNS3_VECTOR0_EVENT_ERR;
189 /* check for vector0 mailbox(=CMDQ RX) event source */
190 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
191 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
193 ret = HNS3_VECTOR0_EVENT_MBX;
197 if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
198 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
199 vector0_int_stats, cmdq_src_val, hw_err_src_reg);
200 val = vector0_int_stats;
201 ret = HNS3_VECTOR0_EVENT_OTHER;
210 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
212 if (event_type == HNS3_VECTOR0_EVENT_RST)
213 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
214 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
215 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
219 hns3_clear_all_event_cause(struct hns3_hw *hw)
221 uint32_t vector0_int_stats;
222 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
224 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
225 hns3_warn(hw, "Probe during IMP reset interrupt");
227 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
228 hns3_warn(hw, "Probe during Global reset interrupt");
230 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
231 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
232 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
233 BIT(HNS3_VECTOR0_CORERESET_INT_B));
234 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
238 hns3_interrupt_handler(void *param)
240 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
241 struct hns3_adapter *hns = dev->data->dev_private;
242 struct hns3_hw *hw = &hns->hw;
243 enum hns3_evt_cause event_cause;
244 uint32_t clearval = 0;
246 /* Disable interrupt */
247 hns3_pf_disable_irq0(hw);
249 event_cause = hns3_check_event_cause(hns, &clearval);
250 /* vector 0 interrupt is shared with reset and mailbox source events. */
251 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
252 hns3_warn(hw, "Received err interrupt");
253 hns3_handle_msix_error(hns, &hw->reset.request);
254 hns3_handle_ras_error(hns, &hw->reset.request);
255 hns3_schedule_reset(hns);
256 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
257 hns3_warn(hw, "Received reset interrupt");
258 hns3_schedule_reset(hns);
259 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
260 hns3_dev_handle_mbx_msg(hw);
262 hns3_err(hw, "Received unknown event");
264 hns3_clear_event_cause(hw, event_cause, clearval);
265 /* Enable interrupt if it is not cause by reset */
266 hns3_pf_enable_irq0(hw);
270 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
272 #define HNS3_VLAN_ID_OFFSET_STEP 160
273 #define HNS3_VLAN_BYTE_SIZE 8
274 struct hns3_vlan_filter_pf_cfg_cmd *req;
275 struct hns3_hw *hw = &hns->hw;
276 uint8_t vlan_offset_byte_val;
277 struct hns3_cmd_desc desc;
278 uint8_t vlan_offset_byte;
279 uint8_t vlan_offset_base;
282 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
284 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
285 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
287 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
289 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
290 req->vlan_offset = vlan_offset_base;
291 req->vlan_cfg = on ? 0 : 1;
292 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
294 ret = hns3_cmd_send(hw, &desc, 1);
296 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
303 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
305 struct hns3_user_vlan_table *vlan_entry;
306 struct hns3_pf *pf = &hns->pf;
308 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
309 if (vlan_entry->vlan_id == vlan_id) {
310 if (vlan_entry->hd_tbl_status)
311 hns3_set_port_vlan_filter(hns, vlan_id, 0);
312 LIST_REMOVE(vlan_entry, next);
313 rte_free(vlan_entry);
320 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
323 struct hns3_user_vlan_table *vlan_entry;
324 struct hns3_hw *hw = &hns->hw;
325 struct hns3_pf *pf = &hns->pf;
327 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
328 if (vlan_entry->vlan_id == vlan_id)
332 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
333 if (vlan_entry == NULL) {
334 hns3_err(hw, "Failed to malloc hns3 vlan table");
338 vlan_entry->hd_tbl_status = writen_to_tbl;
339 vlan_entry->vlan_id = vlan_id;
341 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
345 hns3_restore_vlan_table(struct hns3_adapter *hns)
347 struct hns3_user_vlan_table *vlan_entry;
348 struct hns3_hw *hw = &hns->hw;
349 struct hns3_pf *pf = &hns->pf;
353 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
354 return hns3_vlan_pvid_configure(hns,
355 hw->port_base_vlan_cfg.pvid, 1);
357 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
358 if (vlan_entry->hd_tbl_status) {
359 vlan_id = vlan_entry->vlan_id;
360 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
370 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
372 struct hns3_hw *hw = &hns->hw;
373 bool writen_to_tbl = false;
377 * When vlan filter is enabled, hardware regards packets without vlan
378 * as packets with vlan 0. So, to receive packets without vlan, vlan id
379 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
381 if (on == 0 && vlan_id == 0)
385 * When port base vlan enabled, we use port base vlan as the vlan
386 * filter condition. In this case, we don't update vlan filter table
387 * when user add new vlan or remove exist vlan, just update the
388 * vlan list. The vlan id in vlan list will be writen in vlan filter
389 * table until port base vlan disabled
391 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
392 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
393 writen_to_tbl = true;
398 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
400 hns3_rm_dev_vlan_table(hns, vlan_id);
406 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
408 struct hns3_adapter *hns = dev->data->dev_private;
409 struct hns3_hw *hw = &hns->hw;
412 rte_spinlock_lock(&hw->lock);
413 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
414 rte_spinlock_unlock(&hw->lock);
419 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
422 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
423 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
424 struct hns3_hw *hw = &hns->hw;
425 struct hns3_cmd_desc desc;
428 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
429 vlan_type != ETH_VLAN_TYPE_OUTER)) {
430 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
434 if (tpid != RTE_ETHER_TYPE_VLAN) {
435 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
439 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
440 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
442 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
443 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
444 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
445 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
446 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
447 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
448 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
449 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
452 ret = hns3_cmd_send(hw, &desc, 1);
454 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
459 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
461 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
462 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
463 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
465 ret = hns3_cmd_send(hw, &desc, 1);
467 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
473 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
476 struct hns3_adapter *hns = dev->data->dev_private;
477 struct hns3_hw *hw = &hns->hw;
480 rte_spinlock_lock(&hw->lock);
481 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
482 rte_spinlock_unlock(&hw->lock);
487 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
488 struct hns3_rx_vtag_cfg *vcfg)
490 struct hns3_vport_vtag_rx_cfg_cmd *req;
491 struct hns3_hw *hw = &hns->hw;
492 struct hns3_cmd_desc desc;
497 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
499 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
500 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
501 vcfg->strip_tag1_en ? 1 : 0);
502 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
503 vcfg->strip_tag2_en ? 1 : 0);
504 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
505 vcfg->vlan1_vlan_prionly ? 1 : 0);
506 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
507 vcfg->vlan2_vlan_prionly ? 1 : 0);
509 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
510 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
511 vcfg->strip_tag1_discard_en ? 1 : 0);
512 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
513 vcfg->strip_tag2_discard_en ? 1 : 0);
515 * In current version VF is not supported when PF is driven by DPDK
516 * driver, just need to configure parameters for PF vport.
518 vport_id = HNS3_PF_FUNC_ID;
519 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
520 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
521 req->vf_bitmap[req->vf_offset] = bitmap;
523 ret = hns3_cmd_send(hw, &desc, 1);
525 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
530 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
531 struct hns3_rx_vtag_cfg *vcfg)
533 struct hns3_pf *pf = &hns->pf;
534 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
538 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
539 struct hns3_tx_vtag_cfg *vcfg)
541 struct hns3_pf *pf = &hns->pf;
542 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
546 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
548 struct hns3_rx_vtag_cfg rxvlan_cfg;
549 struct hns3_hw *hw = &hns->hw;
552 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
553 rxvlan_cfg.strip_tag1_en = false;
554 rxvlan_cfg.strip_tag2_en = enable;
555 rxvlan_cfg.strip_tag2_discard_en = false;
557 rxvlan_cfg.strip_tag1_en = enable;
558 rxvlan_cfg.strip_tag2_en = true;
559 rxvlan_cfg.strip_tag2_discard_en = true;
562 rxvlan_cfg.strip_tag1_discard_en = false;
563 rxvlan_cfg.vlan1_vlan_prionly = false;
564 rxvlan_cfg.vlan2_vlan_prionly = false;
565 rxvlan_cfg.rx_vlan_offload_en = enable;
567 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
569 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
573 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
579 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
580 uint8_t fe_type, bool filter_en, uint8_t vf_id)
582 struct hns3_vlan_filter_ctrl_cmd *req;
583 struct hns3_cmd_desc desc;
586 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
588 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
589 req->vlan_type = vlan_type;
590 req->vlan_fe = filter_en ? fe_type : 0;
593 ret = hns3_cmd_send(hw, &desc, 1);
595 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
601 hns3_vlan_filter_init(struct hns3_adapter *hns)
603 struct hns3_hw *hw = &hns->hw;
606 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
607 HNS3_FILTER_FE_EGRESS, false,
610 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
614 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
615 HNS3_FILTER_FE_INGRESS, false,
618 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
624 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
626 struct hns3_hw *hw = &hns->hw;
629 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
630 HNS3_FILTER_FE_INGRESS, enable,
633 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
634 enable ? "enable" : "disable", ret);
640 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
642 struct hns3_adapter *hns = dev->data->dev_private;
643 struct hns3_hw *hw = &hns->hw;
644 struct rte_eth_rxmode *rxmode;
645 unsigned int tmp_mask;
649 rte_spinlock_lock(&hw->lock);
650 rxmode = &dev->data->dev_conf.rxmode;
651 tmp_mask = (unsigned int)mask;
652 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
653 /* ignore vlan filter configuration during promiscuous mode */
654 if (!dev->data->promiscuous) {
655 /* Enable or disable VLAN filter */
656 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
659 ret = hns3_enable_vlan_filter(hns, enable);
661 rte_spinlock_unlock(&hw->lock);
662 hns3_err(hw, "failed to %s rx filter, ret = %d",
663 enable ? "enable" : "disable", ret);
669 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
670 /* Enable or disable VLAN stripping */
671 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
674 ret = hns3_en_hw_strip_rxvtag(hns, enable);
676 rte_spinlock_unlock(&hw->lock);
677 hns3_err(hw, "failed to %s rx strip, ret = %d",
678 enable ? "enable" : "disable", ret);
683 rte_spinlock_unlock(&hw->lock);
689 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
690 struct hns3_tx_vtag_cfg *vcfg)
692 struct hns3_vport_vtag_tx_cfg_cmd *req;
693 struct hns3_cmd_desc desc;
694 struct hns3_hw *hw = &hns->hw;
699 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
701 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
702 req->def_vlan_tag1 = vcfg->default_tag1;
703 req->def_vlan_tag2 = vcfg->default_tag2;
704 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
705 vcfg->accept_tag1 ? 1 : 0);
706 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
707 vcfg->accept_untag1 ? 1 : 0);
708 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
709 vcfg->accept_tag2 ? 1 : 0);
710 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
711 vcfg->accept_untag2 ? 1 : 0);
712 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
713 vcfg->insert_tag1_en ? 1 : 0);
714 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
715 vcfg->insert_tag2_en ? 1 : 0);
716 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
718 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
719 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
720 vcfg->tag_shift_mode_en ? 1 : 0);
723 * In current version VF is not supported when PF is driven by DPDK
724 * driver, just need to configure parameters for PF vport.
726 vport_id = HNS3_PF_FUNC_ID;
727 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
728 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
729 req->vf_bitmap[req->vf_offset] = bitmap;
731 ret = hns3_cmd_send(hw, &desc, 1);
733 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
739 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
742 struct hns3_hw *hw = &hns->hw;
743 struct hns3_tx_vtag_cfg txvlan_cfg;
746 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
747 txvlan_cfg.accept_tag1 = true;
748 txvlan_cfg.insert_tag1_en = false;
749 txvlan_cfg.default_tag1 = 0;
751 txvlan_cfg.accept_tag1 =
752 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
753 txvlan_cfg.insert_tag1_en = true;
754 txvlan_cfg.default_tag1 = pvid;
757 txvlan_cfg.accept_untag1 = true;
758 txvlan_cfg.accept_tag2 = true;
759 txvlan_cfg.accept_untag2 = true;
760 txvlan_cfg.insert_tag2_en = false;
761 txvlan_cfg.default_tag2 = 0;
762 txvlan_cfg.tag_shift_mode_en = true;
764 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
766 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
771 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
777 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
779 struct hns3_user_vlan_table *vlan_entry;
780 struct hns3_pf *pf = &hns->pf;
782 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
783 if (vlan_entry->hd_tbl_status) {
784 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
785 vlan_entry->hd_tbl_status = false;
790 vlan_entry = LIST_FIRST(&pf->vlan_list);
792 LIST_REMOVE(vlan_entry, next);
793 rte_free(vlan_entry);
794 vlan_entry = LIST_FIRST(&pf->vlan_list);
800 hns3_add_all_vlan_table(struct hns3_adapter *hns)
802 struct hns3_user_vlan_table *vlan_entry;
803 struct hns3_pf *pf = &hns->pf;
805 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
806 if (!vlan_entry->hd_tbl_status) {
807 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
808 vlan_entry->hd_tbl_status = true;
814 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
816 struct hns3_hw *hw = &hns->hw;
819 hns3_rm_all_vlan_table(hns, true);
820 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
821 ret = hns3_set_port_vlan_filter(hns,
822 hw->port_base_vlan_cfg.pvid, 0);
824 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
832 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
833 uint16_t port_base_vlan_state, uint16_t new_pvid)
835 struct hns3_hw *hw = &hns->hw;
839 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
840 old_pvid = hw->port_base_vlan_cfg.pvid;
841 if (old_pvid != HNS3_INVALID_PVID) {
842 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
844 hns3_err(hw, "failed to remove old pvid %u, "
845 "ret = %d", old_pvid, ret);
850 hns3_rm_all_vlan_table(hns, false);
851 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
853 hns3_err(hw, "failed to add new pvid %u, ret = %d",
858 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
860 hns3_err(hw, "failed to remove pvid %u, ret = %d",
865 hns3_add_all_vlan_table(hns);
871 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
873 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
874 struct hns3_rx_vtag_cfg rx_vlan_cfg;
878 rx_strip_en = old_cfg->rx_vlan_offload_en;
880 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
881 rx_vlan_cfg.strip_tag2_en = true;
882 rx_vlan_cfg.strip_tag2_discard_en = true;
884 rx_vlan_cfg.strip_tag1_en = false;
885 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
886 rx_vlan_cfg.strip_tag2_discard_en = false;
888 rx_vlan_cfg.strip_tag1_discard_en = false;
889 rx_vlan_cfg.vlan1_vlan_prionly = false;
890 rx_vlan_cfg.vlan2_vlan_prionly = false;
891 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
893 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
897 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
902 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
904 struct hns3_hw *hw = &hns->hw;
905 uint16_t port_base_vlan_state;
908 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
909 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
910 hns3_warn(hw, "Invalid operation! As current pvid set "
911 "is %u, disable pvid %u is invalid",
912 hw->port_base_vlan_cfg.pvid, pvid);
916 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
917 HNS3_PORT_BASE_VLAN_DISABLE;
918 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
920 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
925 ret = hns3_en_pvid_strip(hns, on);
927 hns3_err(hw, "failed to config rx vlan strip for pvid, "
932 if (pvid == HNS3_INVALID_PVID)
934 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
936 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
942 hw->port_base_vlan_cfg.state = port_base_vlan_state;
943 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
948 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
950 struct hns3_adapter *hns = dev->data->dev_private;
951 struct hns3_hw *hw = &hns->hw;
952 bool pvid_en_state_change;
956 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
957 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
958 RTE_ETHER_MAX_VLAN_ID);
963 * If PVID configuration state change, should refresh the PVID
964 * configuration state in struct hns3_tx_queue/hns3_rx_queue.
966 pvid_state = hw->port_base_vlan_cfg.state;
967 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
968 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
969 pvid_en_state_change = false;
971 pvid_en_state_change = true;
973 rte_spinlock_lock(&hw->lock);
974 ret = hns3_vlan_pvid_configure(hns, pvid, on);
975 rte_spinlock_unlock(&hw->lock);
979 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
980 * need be processed by PMD driver.
982 if (pvid_en_state_change &&
983 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
984 hns3_update_all_queues_pvid_proc_en(hw);
990 hns3_default_vlan_config(struct hns3_adapter *hns)
992 struct hns3_hw *hw = &hns->hw;
996 * When vlan filter is enabled, hardware regards packets without vlan
997 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
998 * table, packets without vlan won't be received. So, add vlan 0 as
1001 ret = hns3_vlan_filter_configure(hns, 0, 1);
1003 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1008 hns3_init_vlan_config(struct hns3_adapter *hns)
1010 struct hns3_hw *hw = &hns->hw;
1014 * This function can be called in the initialization and reset process,
1015 * when in reset process, it means that hardware had been reseted
1016 * successfully and we need to restore the hardware configuration to
1017 * ensure that the hardware configuration remains unchanged before and
1020 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1021 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1022 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1025 ret = hns3_vlan_filter_init(hns);
1027 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1031 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1032 RTE_ETHER_TYPE_VLAN);
1034 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1039 * When in the reinit dev stage of the reset process, the following
1040 * vlan-related configurations may differ from those at initialization,
1041 * we will restore configurations to hardware in hns3_restore_vlan_table
1042 * and hns3_restore_vlan_conf later.
1044 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1045 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1047 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1051 ret = hns3_en_hw_strip_rxvtag(hns, false);
1053 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1059 return hns3_default_vlan_config(hns);
1063 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1065 struct hns3_pf *pf = &hns->pf;
1066 struct hns3_hw *hw = &hns->hw;
1071 if (!hw->data->promiscuous) {
1072 /* restore vlan filter states */
1073 offloads = hw->data->dev_conf.rxmode.offloads;
1074 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1075 ret = hns3_enable_vlan_filter(hns, enable);
1077 hns3_err(hw, "failed to restore vlan rx filter conf, "
1083 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1085 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1089 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1091 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1097 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1099 struct hns3_adapter *hns = dev->data->dev_private;
1100 struct rte_eth_dev_data *data = dev->data;
1101 struct rte_eth_txmode *txmode;
1102 struct hns3_hw *hw = &hns->hw;
1106 txmode = &data->dev_conf.txmode;
1107 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1109 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1110 "configuration is not supported! Ignore these two "
1111 "parameters: hw_vlan_reject_tagged(%u), "
1112 "hw_vlan_reject_untagged(%u)",
1113 txmode->hw_vlan_reject_tagged,
1114 txmode->hw_vlan_reject_untagged);
1116 /* Apply vlan offload setting */
1117 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1118 ret = hns3_vlan_offload_set(dev, mask);
1120 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1126 * If pvid config is not set in rte_eth_conf, driver needn't to set
1127 * VLAN pvid related configuration to hardware.
1129 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1132 /* Apply pvid setting */
1133 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1134 txmode->hw_vlan_insert_pvid);
1136 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1143 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1144 unsigned int tso_mss_max)
1146 struct hns3_cfg_tso_status_cmd *req;
1147 struct hns3_cmd_desc desc;
1150 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1152 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1155 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1157 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1160 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1162 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1164 return hns3_cmd_send(hw, &desc, 1);
1168 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1169 uint16_t *allocated_size, bool is_alloc)
1171 struct hns3_umv_spc_alc_cmd *req;
1172 struct hns3_cmd_desc desc;
1175 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1176 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1177 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1178 req->space_size = rte_cpu_to_le_32(space_size);
1180 ret = hns3_cmd_send(hw, &desc, 1);
1182 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1183 is_alloc ? "allocate" : "free", ret);
1187 if (is_alloc && allocated_size)
1188 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1194 hns3_init_umv_space(struct hns3_hw *hw)
1196 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1197 struct hns3_pf *pf = &hns->pf;
1198 uint16_t allocated_size = 0;
1201 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1206 if (allocated_size < pf->wanted_umv_size)
1207 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1208 pf->wanted_umv_size, allocated_size);
1210 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1211 pf->wanted_umv_size;
1212 pf->used_umv_size = 0;
1217 hns3_uninit_umv_space(struct hns3_hw *hw)
1219 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1220 struct hns3_pf *pf = &hns->pf;
1223 if (pf->max_umv_size == 0)
1226 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1230 pf->max_umv_size = 0;
1236 hns3_is_umv_space_full(struct hns3_hw *hw)
1238 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1239 struct hns3_pf *pf = &hns->pf;
1242 is_full = (pf->used_umv_size >= pf->max_umv_size);
1248 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1250 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1251 struct hns3_pf *pf = &hns->pf;
1254 if (pf->used_umv_size > 0)
1255 pf->used_umv_size--;
1257 pf->used_umv_size++;
1261 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1262 const uint8_t *addr, bool is_mc)
1264 const unsigned char *mac_addr = addr;
1265 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1266 ((uint32_t)mac_addr[2] << 16) |
1267 ((uint32_t)mac_addr[1] << 8) |
1268 (uint32_t)mac_addr[0];
1269 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1271 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1273 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1274 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1275 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1278 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1279 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1283 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1285 enum hns3_mac_vlan_tbl_opcode op)
1288 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1293 if (op == HNS3_MAC_VLAN_ADD) {
1294 if (resp_code == 0 || resp_code == 1) {
1296 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1297 hns3_err(hw, "add mac addr failed for uc_overflow");
1299 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1300 hns3_err(hw, "add mac addr failed for mc_overflow");
1304 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1307 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1308 if (resp_code == 0) {
1310 } else if (resp_code == 1) {
1311 hns3_dbg(hw, "remove mac addr failed for miss");
1315 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1318 } else if (op == HNS3_MAC_VLAN_LKUP) {
1319 if (resp_code == 0) {
1321 } else if (resp_code == 1) {
1322 hns3_dbg(hw, "lookup mac addr failed for miss");
1326 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1331 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1338 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1339 struct hns3_mac_vlan_tbl_entry_cmd *req,
1340 struct hns3_cmd_desc *desc, bool is_mc)
1346 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1348 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1349 memcpy(desc[0].data, req,
1350 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1351 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1353 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1354 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1356 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1358 memcpy(desc[0].data, req,
1359 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1360 ret = hns3_cmd_send(hw, desc, 1);
1363 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1367 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1368 retval = rte_le_to_cpu_16(desc[0].retval);
1370 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1371 HNS3_MAC_VLAN_LKUP);
1375 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1376 struct hns3_mac_vlan_tbl_entry_cmd *req,
1377 struct hns3_cmd_desc *mc_desc)
1384 if (mc_desc == NULL) {
1385 struct hns3_cmd_desc desc;
1387 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1388 memcpy(desc.data, req,
1389 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1390 ret = hns3_cmd_send(hw, &desc, 1);
1391 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1392 retval = rte_le_to_cpu_16(desc.retval);
1394 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1397 hns3_cmd_reuse_desc(&mc_desc[0], false);
1398 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1399 hns3_cmd_reuse_desc(&mc_desc[1], false);
1400 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1401 hns3_cmd_reuse_desc(&mc_desc[2], false);
1402 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1403 memcpy(mc_desc[0].data, req,
1404 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1405 mc_desc[0].retval = 0;
1406 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1407 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1408 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1410 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1415 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1423 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1424 struct hns3_mac_vlan_tbl_entry_cmd *req)
1426 struct hns3_cmd_desc desc;
1431 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1433 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1435 ret = hns3_cmd_send(hw, &desc, 1);
1437 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1440 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1441 retval = rte_le_to_cpu_16(desc.retval);
1443 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1444 HNS3_MAC_VLAN_REMOVE);
1448 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1450 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1451 struct hns3_mac_vlan_tbl_entry_cmd req;
1452 struct hns3_pf *pf = &hns->pf;
1453 struct hns3_cmd_desc desc[3];
1454 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1455 uint16_t egress_port = 0;
1459 /* check if mac addr is valid */
1460 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1461 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1463 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1468 memset(&req, 0, sizeof(req));
1471 * In current version VF is not supported when PF is driven by DPDK
1472 * driver, just need to configure parameters for PF vport.
1474 vf_id = HNS3_PF_FUNC_ID;
1475 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1476 HNS3_MAC_EPORT_VFID_S, vf_id);
1478 req.egress_port = rte_cpu_to_le_16(egress_port);
1480 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1483 * Lookup the mac address in the mac_vlan table, and add
1484 * it if the entry is inexistent. Repeated unicast entry
1485 * is not allowed in the mac vlan table.
1487 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1488 if (ret == -ENOENT) {
1489 if (!hns3_is_umv_space_full(hw)) {
1490 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1492 hns3_update_umv_space(hw, false);
1496 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1501 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1503 /* check if we just hit the duplicate */
1505 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1509 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1516 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1518 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1519 struct rte_ether_addr *addr;
1523 for (i = 0; i < hw->mc_addrs_num; i++) {
1524 addr = &hw->mc_addrs[i];
1525 /* Check if there are duplicate addresses */
1526 if (rte_is_same_ether_addr(addr, mac_addr)) {
1527 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1529 hns3_err(hw, "failed to add mc mac addr, same addrs"
1530 "(%s) is added by the set_mc_mac_addr_list "
1536 ret = hns3_add_mc_addr(hw, mac_addr);
1538 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1540 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1547 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1549 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1552 ret = hns3_remove_mc_addr(hw, mac_addr);
1554 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1556 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1563 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1564 uint32_t idx, __rte_unused uint32_t pool)
1566 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1567 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1570 rte_spinlock_lock(&hw->lock);
1573 * In hns3 network engine adding UC and MC mac address with different
1574 * commands with firmware. We need to determine whether the input
1575 * address is a UC or a MC address to call different commands.
1576 * By the way, it is recommended calling the API function named
1577 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1578 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1579 * may affect the specifications of UC mac addresses.
1581 if (rte_is_multicast_ether_addr(mac_addr))
1582 ret = hns3_add_mc_addr_common(hw, mac_addr);
1584 ret = hns3_add_uc_addr_common(hw, mac_addr);
1587 rte_spinlock_unlock(&hw->lock);
1588 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1590 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1596 hw->mac.default_addr_setted = true;
1597 rte_spinlock_unlock(&hw->lock);
1603 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1605 struct hns3_mac_vlan_tbl_entry_cmd req;
1606 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1609 /* check if mac addr is valid */
1610 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1611 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1613 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1618 memset(&req, 0, sizeof(req));
1619 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1620 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1621 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1622 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1625 hns3_update_umv_space(hw, true);
1631 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1633 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1634 /* index will be checked by upper level rte interface */
1635 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1636 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1639 rte_spinlock_lock(&hw->lock);
1641 if (rte_is_multicast_ether_addr(mac_addr))
1642 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1644 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1645 rte_spinlock_unlock(&hw->lock);
1647 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1649 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1655 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1656 struct rte_ether_addr *mac_addr)
1658 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1659 struct rte_ether_addr *oaddr;
1660 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1661 bool default_addr_setted;
1662 bool rm_succes = false;
1666 * It has been guaranteed that input parameter named mac_addr is valid
1667 * address in the rte layer of DPDK framework.
1669 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1670 default_addr_setted = hw->mac.default_addr_setted;
1671 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1674 rte_spinlock_lock(&hw->lock);
1675 if (default_addr_setted) {
1676 ret = hns3_remove_uc_addr_common(hw, oaddr);
1678 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1680 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1687 ret = hns3_add_uc_addr_common(hw, mac_addr);
1689 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1691 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1692 goto err_add_uc_addr;
1695 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1697 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1698 goto err_pause_addr_cfg;
1701 rte_ether_addr_copy(mac_addr,
1702 (struct rte_ether_addr *)hw->mac.mac_addr);
1703 hw->mac.default_addr_setted = true;
1704 rte_spinlock_unlock(&hw->lock);
1709 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1711 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1714 "Failed to roll back to del setted mac addr(%s): %d",
1720 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1722 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1725 "Failed to restore old uc mac addr(%s): %d",
1727 hw->mac.default_addr_setted = false;
1730 rte_spinlock_unlock(&hw->lock);
1736 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1738 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1739 struct hns3_hw *hw = &hns->hw;
1740 struct rte_ether_addr *addr;
1745 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1746 addr = &hw->data->mac_addrs[i];
1747 if (rte_is_zero_ether_addr(addr))
1749 if (rte_is_multicast_ether_addr(addr))
1750 ret = del ? hns3_remove_mc_addr(hw, addr) :
1751 hns3_add_mc_addr(hw, addr);
1753 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1754 hns3_add_uc_addr_common(hw, addr);
1758 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1760 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1761 "ret = %d.", del ? "remove" : "restore",
1769 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1771 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1775 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1776 word_num = vfid / 32;
1777 bit_num = vfid % 32;
1779 desc[1].data[word_num] &=
1780 rte_cpu_to_le_32(~(1UL << bit_num));
1782 desc[1].data[word_num] |=
1783 rte_cpu_to_le_32(1UL << bit_num);
1785 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1786 bit_num = vfid % 32;
1788 desc[2].data[word_num] &=
1789 rte_cpu_to_le_32(~(1UL << bit_num));
1791 desc[2].data[word_num] |=
1792 rte_cpu_to_le_32(1UL << bit_num);
1797 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1799 struct hns3_mac_vlan_tbl_entry_cmd req;
1800 struct hns3_cmd_desc desc[3];
1801 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1805 /* Check if mac addr is valid */
1806 if (!rte_is_multicast_ether_addr(mac_addr)) {
1807 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1809 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1814 memset(&req, 0, sizeof(req));
1815 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1816 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1817 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1819 /* This mac addr do not exist, add new entry for it */
1820 memset(desc[0].data, 0, sizeof(desc[0].data));
1821 memset(desc[1].data, 0, sizeof(desc[0].data));
1822 memset(desc[2].data, 0, sizeof(desc[0].data));
1826 * In current version VF is not supported when PF is driven by DPDK
1827 * driver, just need to configure parameters for PF vport.
1829 vf_id = HNS3_PF_FUNC_ID;
1830 hns3_update_desc_vfid(desc, vf_id, false);
1831 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1834 hns3_err(hw, "mc mac vlan table is full");
1835 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1837 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1844 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1846 struct hns3_mac_vlan_tbl_entry_cmd req;
1847 struct hns3_cmd_desc desc[3];
1848 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1852 /* Check if mac addr is valid */
1853 if (!rte_is_multicast_ether_addr(mac_addr)) {
1854 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1856 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1861 memset(&req, 0, sizeof(req));
1862 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1863 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1864 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1867 * This mac addr exist, remove this handle's VFID for it.
1868 * In current version VF is not supported when PF is driven by
1869 * DPDK driver, just need to configure parameters for PF vport.
1871 vf_id = HNS3_PF_FUNC_ID;
1872 hns3_update_desc_vfid(desc, vf_id, true);
1874 /* All the vfid is zero, so need to delete this entry */
1875 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1876 } else if (ret == -ENOENT) {
1877 /* This mac addr doesn't exist. */
1882 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1884 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1891 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1892 struct rte_ether_addr *mc_addr_set,
1893 uint32_t nb_mc_addr)
1895 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1896 struct rte_ether_addr *addr;
1900 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1901 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1902 "invalid. valid range: 0~%d",
1903 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1907 /* Check if input mac addresses are valid */
1908 for (i = 0; i < nb_mc_addr; i++) {
1909 addr = &mc_addr_set[i];
1910 if (!rte_is_multicast_ether_addr(addr)) {
1911 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1914 "failed to set mc mac addr, addr(%s) invalid.",
1919 /* Check if there are duplicate addresses */
1920 for (j = i + 1; j < nb_mc_addr; j++) {
1921 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1922 hns3_ether_format_addr(mac_str,
1923 RTE_ETHER_ADDR_FMT_SIZE,
1925 hns3_err(hw, "failed to set mc mac addr, "
1926 "addrs invalid. two same addrs(%s).",
1933 * Check if there are duplicate addresses between mac_addrs
1936 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1937 if (rte_is_same_ether_addr(addr,
1938 &hw->data->mac_addrs[j])) {
1939 hns3_ether_format_addr(mac_str,
1940 RTE_ETHER_ADDR_FMT_SIZE,
1942 hns3_err(hw, "failed to set mc mac addr, "
1943 "addrs invalid. addrs(%s) has already "
1944 "configured in mac_addr add API",
1955 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1956 struct rte_ether_addr *mc_addr_set,
1958 struct rte_ether_addr *reserved_addr_list,
1959 int *reserved_addr_num,
1960 struct rte_ether_addr *add_addr_list,
1962 struct rte_ether_addr *rm_addr_list,
1965 struct rte_ether_addr *addr;
1966 int current_addr_num;
1967 int reserved_num = 0;
1975 /* Calculate the mc mac address list that should be removed */
1976 current_addr_num = hw->mc_addrs_num;
1977 for (i = 0; i < current_addr_num; i++) {
1978 addr = &hw->mc_addrs[i];
1980 for (j = 0; j < mc_addr_num; j++) {
1981 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1988 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1991 rte_ether_addr_copy(addr,
1992 &reserved_addr_list[reserved_num]);
1997 /* Calculate the mc mac address list that should be added */
1998 for (i = 0; i < mc_addr_num; i++) {
1999 addr = &mc_addr_set[i];
2001 for (j = 0; j < current_addr_num; j++) {
2002 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2009 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2014 /* Reorder the mc mac address list maintained by driver */
2015 for (i = 0; i < reserved_num; i++)
2016 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2018 for (i = 0; i < rm_num; i++) {
2019 num = reserved_num + i;
2020 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2023 *reserved_addr_num = reserved_num;
2024 *add_addr_num = add_num;
2025 *rm_addr_num = rm_num;
2029 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2030 struct rte_ether_addr *mc_addr_set,
2031 uint32_t nb_mc_addr)
2033 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2034 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2035 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2036 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2037 struct rte_ether_addr *addr;
2038 int reserved_addr_num;
2046 /* Check if input parameters are valid */
2047 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2051 rte_spinlock_lock(&hw->lock);
2054 * Calculate the mc mac address lists those should be removed and be
2055 * added, Reorder the mc mac address list maintained by driver.
2057 mc_addr_num = (int)nb_mc_addr;
2058 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2059 reserved_addr_list, &reserved_addr_num,
2060 add_addr_list, &add_addr_num,
2061 rm_addr_list, &rm_addr_num);
2063 /* Remove mc mac addresses */
2064 for (i = 0; i < rm_addr_num; i++) {
2065 num = rm_addr_num - i - 1;
2066 addr = &rm_addr_list[num];
2067 ret = hns3_remove_mc_addr(hw, addr);
2069 rte_spinlock_unlock(&hw->lock);
2075 /* Add mc mac addresses */
2076 for (i = 0; i < add_addr_num; i++) {
2077 addr = &add_addr_list[i];
2078 ret = hns3_add_mc_addr(hw, addr);
2080 rte_spinlock_unlock(&hw->lock);
2084 num = reserved_addr_num + i;
2085 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2088 rte_spinlock_unlock(&hw->lock);
2094 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2096 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2097 struct hns3_hw *hw = &hns->hw;
2098 struct rte_ether_addr *addr;
2103 for (i = 0; i < hw->mc_addrs_num; i++) {
2104 addr = &hw->mc_addrs[i];
2105 if (!rte_is_multicast_ether_addr(addr))
2108 ret = hns3_remove_mc_addr(hw, addr);
2110 ret = hns3_add_mc_addr(hw, addr);
2113 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2115 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2116 del ? "Remove" : "Restore", mac_str, ret);
2123 hns3_check_mq_mode(struct rte_eth_dev *dev)
2125 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2126 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2127 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2128 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2129 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2130 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2135 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2136 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2138 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2139 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2140 "rx_mq_mode = %d", rx_mq_mode);
2144 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2145 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2146 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2147 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2148 rx_mq_mode, tx_mq_mode);
2152 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2153 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2154 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2155 dcb_rx_conf->nb_tcs, pf->tc_max);
2159 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2160 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2161 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2162 "nb_tcs(%d) != %d or %d in rx direction.",
2163 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2167 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2168 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2169 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2173 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2174 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2175 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2176 "is not equal to one in tx direction.",
2177 i, dcb_rx_conf->dcb_tc[i]);
2180 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2181 max_tc = dcb_rx_conf->dcb_tc[i];
2184 num_tc = max_tc + 1;
2185 if (num_tc > dcb_rx_conf->nb_tcs) {
2186 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2187 num_tc, dcb_rx_conf->nb_tcs);
2196 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2198 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200 if (!hns3_dev_dcb_supported(hw)) {
2201 hns3_err(hw, "this port does not support dcb configurations.");
2205 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2206 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2210 /* Check multiple queue mode */
2211 return hns3_check_mq_mode(dev);
2215 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2216 enum hns3_ring_type queue_type, uint16_t queue_id)
2218 struct hns3_cmd_desc desc;
2219 struct hns3_ctrl_vector_chain_cmd *req =
2220 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2221 enum hns3_cmd_status status;
2222 enum hns3_opcode_type op;
2223 uint16_t tqp_type_and_id = 0;
2228 op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2229 hns3_cmd_setup_basic_desc(&desc, op, false);
2230 req->int_vector_id = vector_id;
2232 if (queue_type == HNS3_RING_TYPE_RX)
2233 gl = HNS3_RING_GL_RX;
2235 gl = HNS3_RING_GL_TX;
2239 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2241 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2242 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2244 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2245 req->int_cause_num = 1;
2246 op_str = mmap ? "Map" : "Unmap";
2247 status = hns3_cmd_send(hw, &desc, 1);
2249 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2250 op_str, queue_id, req->int_vector_id, status);
2258 hns3_init_ring_with_vector(struct hns3_hw *hw)
2265 * In hns3 network engine, vector 0 is always the misc interrupt of this
2266 * function, vector 1~N can be used respectively for the queues of the
2267 * function. Tx and Rx queues with the same number share the interrupt
2268 * vector. In the initialization clearing the all hardware mapping
2269 * relationship configurations between queues and interrupt vectors is
2270 * needed, so some error caused by the residual configurations, such as
2271 * the unexpected Tx interrupt, can be avoid.
2273 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2274 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2275 vec = vec - 1; /* the last interrupt is reserved */
2276 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2277 for (i = 0; i < hw->intr_tqps_num; i++) {
2279 * Set gap limiter/rate limiter/quanity limiter algorithm
2280 * configuration for interrupt coalesce of queue's interrupt.
2282 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2283 HNS3_TQP_INTR_GL_DEFAULT);
2284 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2285 HNS3_TQP_INTR_GL_DEFAULT);
2286 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2288 * QL(quantity limiter) is not used currently, just set 0 to
2291 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2293 ret = hns3_bind_ring_with_vector(hw, vec, false,
2294 HNS3_RING_TYPE_TX, i);
2296 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2297 "vector: %u, ret=%d", i, vec, ret);
2301 ret = hns3_bind_ring_with_vector(hw, vec, false,
2302 HNS3_RING_TYPE_RX, i);
2304 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2305 "vector: %u, ret=%d", i, vec, ret);
2314 hns3_dev_configure(struct rte_eth_dev *dev)
2316 struct hns3_adapter *hns = dev->data->dev_private;
2317 struct rte_eth_conf *conf = &dev->data->dev_conf;
2318 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2319 struct hns3_hw *hw = &hns->hw;
2320 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2321 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2322 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2323 struct rte_eth_rss_conf rss_conf;
2328 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2331 * Some versions of hardware network engine does not support
2332 * individually enable/disable/reset the Tx or Rx queue. These devices
2333 * must enable/disable/reset Tx and Rx queues at the same time. When the
2334 * numbers of Tx queues allocated by upper applications are not equal to
2335 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2336 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2337 * work as usual. But these fake queues are imperceptible, and can not
2338 * be used by upper applications.
2340 if (!hns3_dev_indep_txrx_supported(hw)) {
2341 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2343 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2349 hw->adapter_state = HNS3_NIC_CONFIGURING;
2350 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2351 hns3_err(hw, "setting link speed/duplex not supported");
2356 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2357 ret = hns3_check_dcb_cfg(dev);
2362 /* When RSS is not configured, redirect the packet queue 0 */
2363 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2364 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2365 rss_conf = conf->rx_adv_conf.rss_conf;
2366 hw->rss_dis_flag = false;
2367 if (rss_conf.rss_key == NULL) {
2368 rss_conf.rss_key = rss_cfg->key;
2369 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2372 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2378 * If jumbo frames are enabled, MTU needs to be refreshed
2379 * according to the maximum RX packet length.
2381 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2383 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2384 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2385 * can safely assign to "uint16_t" type variable.
2387 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2388 ret = hns3_dev_mtu_set(dev, mtu);
2391 dev->data->mtu = mtu;
2394 ret = hns3_dev_configure_vlan(dev);
2398 /* config hardware GRO */
2399 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2400 ret = hns3_config_gro(hw, gro_en);
2404 hns->rx_simple_allowed = true;
2405 hns->rx_vec_allowed = true;
2406 hns->tx_simple_allowed = true;
2407 hns->tx_vec_allowed = true;
2409 hns3_init_rx_ptype_tble(dev);
2410 hw->adapter_state = HNS3_NIC_CONFIGURED;
2415 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2416 hw->adapter_state = HNS3_NIC_INITIALIZED;
2422 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2424 struct hns3_config_max_frm_size_cmd *req;
2425 struct hns3_cmd_desc desc;
2427 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2429 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2430 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2431 req->min_frm_size = RTE_ETHER_MIN_LEN;
2433 return hns3_cmd_send(hw, &desc, 1);
2437 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2441 ret = hns3_set_mac_mtu(hw, mps);
2443 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2447 ret = hns3_buffer_alloc(hw);
2449 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2455 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2457 struct hns3_adapter *hns = dev->data->dev_private;
2458 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2459 struct hns3_hw *hw = &hns->hw;
2460 bool is_jumbo_frame;
2463 if (dev->data->dev_started) {
2464 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2465 "before configuration", dev->data->port_id);
2469 rte_spinlock_lock(&hw->lock);
2470 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2471 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2474 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2475 * assign to "uint16_t" type variable.
2477 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2479 rte_spinlock_unlock(&hw->lock);
2480 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2481 dev->data->port_id, mtu, ret);
2484 hns->pf.mps = (uint16_t)frame_size;
2486 dev->data->dev_conf.rxmode.offloads |=
2487 DEV_RX_OFFLOAD_JUMBO_FRAME;
2489 dev->data->dev_conf.rxmode.offloads &=
2490 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2491 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2492 rte_spinlock_unlock(&hw->lock);
2498 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2500 struct hns3_adapter *hns = eth_dev->data->dev_private;
2501 struct hns3_hw *hw = &hns->hw;
2502 uint16_t queue_num = hw->tqps_num;
2505 * In interrupt mode, 'max_rx_queues' is set based on the number of
2506 * MSI-X interrupt resources of the hardware.
2508 if (hw->data->dev_conf.intr_conf.rxq == 1)
2509 queue_num = hw->intr_tqps_num;
2511 info->max_rx_queues = queue_num;
2512 info->max_tx_queues = hw->tqps_num;
2513 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2514 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2515 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2516 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2517 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2518 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2519 DEV_RX_OFFLOAD_TCP_CKSUM |
2520 DEV_RX_OFFLOAD_UDP_CKSUM |
2521 DEV_RX_OFFLOAD_SCTP_CKSUM |
2522 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2523 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2524 DEV_RX_OFFLOAD_KEEP_CRC |
2525 DEV_RX_OFFLOAD_SCATTER |
2526 DEV_RX_OFFLOAD_VLAN_STRIP |
2527 DEV_RX_OFFLOAD_VLAN_FILTER |
2528 DEV_RX_OFFLOAD_JUMBO_FRAME |
2529 DEV_RX_OFFLOAD_RSS_HASH |
2530 DEV_RX_OFFLOAD_TCP_LRO);
2531 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2532 DEV_TX_OFFLOAD_IPV4_CKSUM |
2533 DEV_TX_OFFLOAD_TCP_CKSUM |
2534 DEV_TX_OFFLOAD_UDP_CKSUM |
2535 DEV_TX_OFFLOAD_SCTP_CKSUM |
2536 DEV_TX_OFFLOAD_MULTI_SEGS |
2537 DEV_TX_OFFLOAD_TCP_TSO |
2538 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2539 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2540 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2541 DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2542 hns3_txvlan_cap_get(hw));
2544 if (hns3_dev_indep_txrx_supported(hw))
2545 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2546 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2548 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2549 .nb_max = HNS3_MAX_RING_DESC,
2550 .nb_min = HNS3_MIN_RING_DESC,
2551 .nb_align = HNS3_ALIGN_RING_DESC,
2554 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2555 .nb_max = HNS3_MAX_RING_DESC,
2556 .nb_min = HNS3_MIN_RING_DESC,
2557 .nb_align = HNS3_ALIGN_RING_DESC,
2558 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2559 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2562 info->default_rxconf = (struct rte_eth_rxconf) {
2563 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2565 * If there are no available Rx buffer descriptors, incoming
2566 * packets are always dropped by hardware based on hns3 network
2572 info->default_txconf = (struct rte_eth_txconf) {
2573 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2577 info->vmdq_queue_num = 0;
2579 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2580 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2581 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2583 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2584 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2585 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2586 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2587 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2588 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2594 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2597 struct hns3_adapter *hns = eth_dev->data->dev_private;
2598 struct hns3_hw *hw = &hns->hw;
2599 uint32_t version = hw->fw_version;
2602 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2603 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2604 HNS3_FW_VERSION_BYTE3_S),
2605 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2606 HNS3_FW_VERSION_BYTE2_S),
2607 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2608 HNS3_FW_VERSION_BYTE1_S),
2609 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2610 HNS3_FW_VERSION_BYTE0_S));
2611 ret += 1; /* add the size of '\0' */
2612 if (fw_size < (uint32_t)ret)
2619 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2620 __rte_unused int wait_to_complete)
2622 struct hns3_adapter *hns = eth_dev->data->dev_private;
2623 struct hns3_hw *hw = &hns->hw;
2624 struct hns3_mac *mac = &hw->mac;
2625 struct rte_eth_link new_link;
2627 if (!hns3_is_reset_pending(hns)) {
2628 hns3_update_speed_duplex(eth_dev);
2629 hns3_update_link_status(hw);
2632 memset(&new_link, 0, sizeof(new_link));
2633 switch (mac->link_speed) {
2634 case ETH_SPEED_NUM_10M:
2635 case ETH_SPEED_NUM_100M:
2636 case ETH_SPEED_NUM_1G:
2637 case ETH_SPEED_NUM_10G:
2638 case ETH_SPEED_NUM_25G:
2639 case ETH_SPEED_NUM_40G:
2640 case ETH_SPEED_NUM_50G:
2641 case ETH_SPEED_NUM_100G:
2642 case ETH_SPEED_NUM_200G:
2643 new_link.link_speed = mac->link_speed;
2646 new_link.link_speed = ETH_SPEED_NUM_100M;
2650 new_link.link_duplex = mac->link_duplex;
2651 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2652 new_link.link_autoneg =
2653 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2655 return rte_eth_linkstatus_set(eth_dev, &new_link);
2659 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2661 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2662 struct hns3_pf *pf = &hns->pf;
2664 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2667 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2673 hns3_query_function_status(struct hns3_hw *hw)
2675 #define HNS3_QUERY_MAX_CNT 10
2676 #define HNS3_QUERY_SLEEP_MSCOEND 1
2677 struct hns3_func_status_cmd *req;
2678 struct hns3_cmd_desc desc;
2682 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2683 req = (struct hns3_func_status_cmd *)desc.data;
2686 ret = hns3_cmd_send(hw, &desc, 1);
2688 PMD_INIT_LOG(ERR, "query function status failed %d",
2693 /* Check pf reset is done */
2697 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2698 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2700 return hns3_parse_func_status(hw, req);
2704 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2706 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2707 struct hns3_pf *pf = &hns->pf;
2709 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2711 * The total_tqps_num obtained from firmware is maximum tqp
2712 * numbers of this port, which should be used for PF and VFs.
2713 * There is no need for pf to have so many tqp numbers in
2714 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2715 * coming from config file, is assigned to maximum queue number
2716 * for the PF of this port by user. So users can modify the
2717 * maximum queue number of PF according to their own application
2718 * scenarios, which is more flexible to use. In addition, many
2719 * memories can be saved due to allocating queue statistics
2720 * room according to the actual number of queues required. The
2721 * maximum queue number of PF for network engine with
2722 * revision_id greater than 0x30 is assigned by config file.
2724 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2725 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2726 "must be greater than 0.",
2727 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2731 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2732 hw->total_tqps_num);
2735 * Due to the limitation on the number of PF interrupts
2736 * available, the maximum queue number assigned to PF on
2737 * the network engine with revision_id 0x21 is 64.
2739 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2740 HNS3_MAX_TQP_NUM_HIP08_PF);
2747 hns3_query_pf_resource(struct hns3_hw *hw)
2749 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2750 struct hns3_pf *pf = &hns->pf;
2751 struct hns3_pf_res_cmd *req;
2752 struct hns3_cmd_desc desc;
2755 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2756 ret = hns3_cmd_send(hw, &desc, 1);
2758 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2762 req = (struct hns3_pf_res_cmd *)desc.data;
2763 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2764 rte_le_to_cpu_16(req->ext_tqp_num);
2765 ret = hns3_get_pf_max_tqp_num(hw);
2769 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2770 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2772 if (req->tx_buf_size)
2774 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2776 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2778 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2780 if (req->dv_buf_size)
2782 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2784 pf->dv_buf_size = HNS3_DEFAULT_DV;
2786 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2789 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2790 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2796 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2798 struct hns3_cfg_param_cmd *req;
2799 uint64_t mac_addr_tmp_high;
2800 uint8_t ext_rss_size_max;
2801 uint64_t mac_addr_tmp;
2804 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2806 /* get the configuration */
2807 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2808 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2809 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2810 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2811 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2812 HNS3_CFG_TQP_DESC_N_M,
2813 HNS3_CFG_TQP_DESC_N_S);
2815 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2816 HNS3_CFG_PHY_ADDR_M,
2817 HNS3_CFG_PHY_ADDR_S);
2818 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2819 HNS3_CFG_MEDIA_TP_M,
2820 HNS3_CFG_MEDIA_TP_S);
2821 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2822 HNS3_CFG_RX_BUF_LEN_M,
2823 HNS3_CFG_RX_BUF_LEN_S);
2824 /* get mac address */
2825 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2826 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2827 HNS3_CFG_MAC_ADDR_H_M,
2828 HNS3_CFG_MAC_ADDR_H_S);
2830 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2832 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2833 HNS3_CFG_DEFAULT_SPEED_M,
2834 HNS3_CFG_DEFAULT_SPEED_S);
2835 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2836 HNS3_CFG_RSS_SIZE_M,
2837 HNS3_CFG_RSS_SIZE_S);
2839 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2840 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2842 req = (struct hns3_cfg_param_cmd *)desc[1].data;
2843 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2845 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2846 HNS3_CFG_SPEED_ABILITY_M,
2847 HNS3_CFG_SPEED_ABILITY_S);
2848 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2849 HNS3_CFG_UMV_TBL_SPACE_M,
2850 HNS3_CFG_UMV_TBL_SPACE_S);
2851 if (!cfg->umv_space)
2852 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2854 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2855 HNS3_CFG_EXT_RSS_SIZE_M,
2856 HNS3_CFG_EXT_RSS_SIZE_S);
2859 * Field ext_rss_size_max obtained from firmware will be more flexible
2860 * for future changes and expansions, which is an exponent of 2, instead
2861 * of reading out directly. If this field is not zero, hns3 PF PMD
2862 * driver uses it as rss_size_max under one TC. Device, whose revision
2863 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2864 * maximum number of queues supported under a TC through this field.
2866 if (ext_rss_size_max)
2867 cfg->rss_size_max = 1U << ext_rss_size_max;
2870 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2871 * @hw: pointer to struct hns3_hw
2872 * @hcfg: the config structure to be getted
2875 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2877 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2878 struct hns3_cfg_param_cmd *req;
2883 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2885 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2886 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2888 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2889 i * HNS3_CFG_RD_LEN_BYTES);
2890 /* Len should be divided by 4 when send to hardware */
2891 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2892 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2893 req->offset = rte_cpu_to_le_32(offset);
2896 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2898 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2902 hns3_parse_cfg(hcfg, desc);
2908 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2910 switch (speed_cmd) {
2911 case HNS3_CFG_SPEED_10M:
2912 *speed = ETH_SPEED_NUM_10M;
2914 case HNS3_CFG_SPEED_100M:
2915 *speed = ETH_SPEED_NUM_100M;
2917 case HNS3_CFG_SPEED_1G:
2918 *speed = ETH_SPEED_NUM_1G;
2920 case HNS3_CFG_SPEED_10G:
2921 *speed = ETH_SPEED_NUM_10G;
2923 case HNS3_CFG_SPEED_25G:
2924 *speed = ETH_SPEED_NUM_25G;
2926 case HNS3_CFG_SPEED_40G:
2927 *speed = ETH_SPEED_NUM_40G;
2929 case HNS3_CFG_SPEED_50G:
2930 *speed = ETH_SPEED_NUM_50G;
2932 case HNS3_CFG_SPEED_100G:
2933 *speed = ETH_SPEED_NUM_100G;
2935 case HNS3_CFG_SPEED_200G:
2936 *speed = ETH_SPEED_NUM_200G;
2946 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2948 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2949 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2950 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2951 hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2952 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2956 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2958 struct hns3_dev_specs_0_cmd *req0;
2960 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2962 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2963 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2964 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2965 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2966 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
2970 hns3_query_dev_specifications(struct hns3_hw *hw)
2972 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2976 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2977 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2979 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2981 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2983 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2987 hns3_parse_dev_specifications(hw, desc);
2993 hns3_get_capability(struct hns3_hw *hw)
2995 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2996 struct rte_pci_device *pci_dev;
2997 struct hns3_pf *pf = &hns->pf;
2998 struct rte_eth_dev *eth_dev;
3003 eth_dev = &rte_eth_devices[hw->data->port_id];
3004 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3005 device_id = pci_dev->id.device_id;
3007 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3008 device_id == HNS3_DEV_ID_50GE_RDMA ||
3009 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3010 device_id == HNS3_DEV_ID_200G_RDMA)
3011 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3013 /* Get PCI revision id */
3014 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3015 HNS3_PCI_REVISION_ID);
3016 if (ret != HNS3_PCI_REVISION_ID_LEN) {
3017 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3021 hw->revision = revision;
3023 if (revision < PCI_REVISION_ID_HIP09_A) {
3024 hns3_set_default_dev_specifications(hw);
3025 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3026 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3027 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3028 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3029 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3030 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3031 hw->rss_info.ipv6_sctp_offload_supported = false;
3035 ret = hns3_query_dev_specifications(hw);
3038 "failed to query dev specifications, ret = %d",
3043 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3044 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3045 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3046 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3047 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3048 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3049 hw->rss_info.ipv6_sctp_offload_supported = true;
3055 hns3_get_board_configuration(struct hns3_hw *hw)
3057 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3058 struct hns3_pf *pf = &hns->pf;
3059 struct hns3_cfg cfg;
3062 ret = hns3_get_board_cfg(hw, &cfg);
3064 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3068 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
3069 !hns3_dev_copper_supported(hw)) {
3070 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
3074 hw->mac.media_type = cfg.media_type;
3075 hw->rss_size_max = cfg.rss_size_max;
3076 hw->rss_dis_flag = false;
3077 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3078 hw->mac.phy_addr = cfg.phy_addr;
3079 hw->mac.default_addr_setted = false;
3080 hw->num_tx_desc = cfg.tqp_desc_num;
3081 hw->num_rx_desc = cfg.tqp_desc_num;
3082 hw->dcb_info.num_pg = 1;
3083 hw->dcb_info.hw_pfc_map = 0;
3085 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3087 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3088 cfg.default_speed, ret);
3092 pf->tc_max = cfg.tc_num;
3093 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3094 PMD_INIT_LOG(WARNING,
3095 "Get TC num(%u) from flash, set TC num to 1",
3100 /* Dev does not support DCB */
3101 if (!hns3_dev_dcb_supported(hw)) {
3105 pf->pfc_max = pf->tc_max;
3107 hw->dcb_info.num_tc = 1;
3108 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3109 hw->tqps_num / hw->dcb_info.num_tc);
3110 hns3_set_bit(hw->hw_tc_map, 0, 1);
3111 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3113 pf->wanted_umv_size = cfg.umv_space;
3119 hns3_get_configuration(struct hns3_hw *hw)
3123 ret = hns3_query_function_status(hw);
3125 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3129 /* Get device capability */
3130 ret = hns3_get_capability(hw);
3132 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3136 /* Get pf resource */
3137 ret = hns3_query_pf_resource(hw);
3139 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3143 ret = hns3_get_board_configuration(hw);
3145 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3149 ret = hns3_query_dev_fec_info(hw);
3152 "failed to query FEC information, ret = %d", ret);
3158 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3159 uint16_t tqp_vid, bool is_pf)
3161 struct hns3_tqp_map_cmd *req;
3162 struct hns3_cmd_desc desc;
3165 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3167 req = (struct hns3_tqp_map_cmd *)desc.data;
3168 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3169 req->tqp_vf = func_id;
3170 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3172 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3173 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3175 ret = hns3_cmd_send(hw, &desc, 1);
3177 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3183 hns3_map_tqp(struct hns3_hw *hw)
3189 * In current version, VF is not supported when PF is driven by DPDK
3190 * driver, so we assign total tqps_num tqps allocated to this port
3193 for (i = 0; i < hw->total_tqps_num; i++) {
3194 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3203 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3205 struct hns3_config_mac_speed_dup_cmd *req;
3206 struct hns3_cmd_desc desc;
3209 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3211 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3213 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3216 case ETH_SPEED_NUM_10M:
3217 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3218 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3220 case ETH_SPEED_NUM_100M:
3221 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3222 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3224 case ETH_SPEED_NUM_1G:
3225 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3226 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3228 case ETH_SPEED_NUM_10G:
3229 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3230 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3232 case ETH_SPEED_NUM_25G:
3233 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3234 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3236 case ETH_SPEED_NUM_40G:
3237 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3238 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3240 case ETH_SPEED_NUM_50G:
3241 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3242 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3244 case ETH_SPEED_NUM_100G:
3245 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3246 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3248 case ETH_SPEED_NUM_200G:
3249 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3250 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3253 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3257 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3259 ret = hns3_cmd_send(hw, &desc, 1);
3261 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3267 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3269 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3270 struct hns3_pf *pf = &hns->pf;
3271 struct hns3_priv_buf *priv;
3272 uint32_t i, total_size;
3274 total_size = pf->pkt_buf_size;
3276 /* alloc tx buffer for all enabled tc */
3277 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3278 priv = &buf_alloc->priv_buf[i];
3280 if (hw->hw_tc_map & BIT(i)) {
3281 if (total_size < pf->tx_buf_size)
3284 priv->tx_buf_size = pf->tx_buf_size;
3286 priv->tx_buf_size = 0;
3288 total_size -= priv->tx_buf_size;
3295 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3297 /* TX buffer size is unit by 128 byte */
3298 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3299 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3300 struct hns3_tx_buff_alloc_cmd *req;
3301 struct hns3_cmd_desc desc;
3306 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3308 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3309 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3310 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3312 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3313 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3314 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3317 ret = hns3_cmd_send(hw, &desc, 1);
3319 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3325 hns3_get_tc_num(struct hns3_hw *hw)
3330 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3331 if (hw->hw_tc_map & BIT(i))
3337 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3339 struct hns3_priv_buf *priv;
3340 uint32_t rx_priv = 0;
3343 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3344 priv = &buf_alloc->priv_buf[i];
3346 rx_priv += priv->buf_size;
3352 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3354 uint32_t total_tx_size = 0;
3357 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3358 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3360 return total_tx_size;
3363 /* Get the number of pfc enabled TCs, which have private buffer */
3365 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3367 struct hns3_priv_buf *priv;
3371 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3372 priv = &buf_alloc->priv_buf[i];
3373 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3380 /* Get the number of pfc disabled TCs, which have private buffer */
3382 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3383 struct hns3_pkt_buf_alloc *buf_alloc)
3385 struct hns3_priv_buf *priv;
3389 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3390 priv = &buf_alloc->priv_buf[i];
3391 if (hw->hw_tc_map & BIT(i) &&
3392 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3400 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3403 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3404 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3405 struct hns3_pf *pf = &hns->pf;
3406 uint32_t shared_buf, aligned_mps;
3411 tc_num = hns3_get_tc_num(hw);
3412 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3414 if (hns3_dev_dcb_supported(hw))
3415 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3418 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3421 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3422 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3423 HNS3_BUF_SIZE_UNIT);
3425 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3426 if (rx_all < rx_priv + shared_std)
3429 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3430 buf_alloc->s_buf.buf_size = shared_buf;
3431 if (hns3_dev_dcb_supported(hw)) {
3432 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3433 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3434 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3435 HNS3_BUF_SIZE_UNIT);
3437 buf_alloc->s_buf.self.high =
3438 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3439 buf_alloc->s_buf.self.low = aligned_mps;
3442 if (hns3_dev_dcb_supported(hw)) {
3443 hi_thrd = shared_buf - pf->dv_buf_size;
3445 if (tc_num <= NEED_RESERVE_TC_NUM)
3446 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3450 hi_thrd = hi_thrd / tc_num;
3452 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3453 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3454 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3456 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3457 lo_thrd = aligned_mps;
3460 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3461 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3462 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3469 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3470 struct hns3_pkt_buf_alloc *buf_alloc)
3472 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3473 struct hns3_pf *pf = &hns->pf;
3474 struct hns3_priv_buf *priv;
3475 uint32_t aligned_mps;
3479 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3480 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3482 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3483 priv = &buf_alloc->priv_buf[i];
3490 if (!(hw->hw_tc_map & BIT(i)))
3494 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3495 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3496 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3497 HNS3_BUF_SIZE_UNIT);
3500 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3504 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3507 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3511 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3512 struct hns3_pkt_buf_alloc *buf_alloc)
3514 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3515 struct hns3_pf *pf = &hns->pf;
3516 struct hns3_priv_buf *priv;
3517 int no_pfc_priv_num;
3522 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3523 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3525 /* let the last to be cleared first */
3526 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3527 priv = &buf_alloc->priv_buf[i];
3528 mask = BIT((uint8_t)i);
3530 if (hw->hw_tc_map & mask &&
3531 !(hw->dcb_info.hw_pfc_map & mask)) {
3532 /* Clear the no pfc TC private buffer */
3540 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3541 no_pfc_priv_num == 0)
3545 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3549 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3550 struct hns3_pkt_buf_alloc *buf_alloc)
3552 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3553 struct hns3_pf *pf = &hns->pf;
3554 struct hns3_priv_buf *priv;
3560 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3561 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3563 /* let the last to be cleared first */
3564 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3565 priv = &buf_alloc->priv_buf[i];
3566 mask = BIT((uint8_t)i);
3567 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3568 /* Reduce the number of pfc TC with private buffer */
3575 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3580 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3584 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3585 struct hns3_pkt_buf_alloc *buf_alloc)
3587 #define COMPENSATE_BUFFER 0x3C00
3588 #define COMPENSATE_HALF_MPS_NUM 5
3589 #define PRIV_WL_GAP 0x1800
3590 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3591 struct hns3_pf *pf = &hns->pf;
3592 uint32_t tc_num = hns3_get_tc_num(hw);
3593 uint32_t half_mps = pf->mps >> 1;
3594 struct hns3_priv_buf *priv;
3595 uint32_t min_rx_priv;
3599 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3601 rx_priv = rx_priv / tc_num;
3603 if (tc_num <= NEED_RESERVE_TC_NUM)
3604 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3607 * Minimum value of private buffer in rx direction (min_rx_priv) is
3608 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3609 * buffer if rx_priv is greater than min_rx_priv.
3611 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3612 COMPENSATE_HALF_MPS_NUM * half_mps;
3613 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3614 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3616 if (rx_priv < min_rx_priv)
3619 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3620 priv = &buf_alloc->priv_buf[i];
3626 if (!(hw->hw_tc_map & BIT(i)))
3630 priv->buf_size = rx_priv;
3631 priv->wl.high = rx_priv - pf->dv_buf_size;
3632 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3635 buf_alloc->s_buf.buf_size = 0;
3641 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3642 * @hw: pointer to struct hns3_hw
3643 * @buf_alloc: pointer to buffer calculation data
3644 * @return: 0: calculate sucessful, negative: fail
3647 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3649 /* When DCB is not supported, rx private buffer is not allocated. */
3650 if (!hns3_dev_dcb_supported(hw)) {
3651 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3652 struct hns3_pf *pf = &hns->pf;
3653 uint32_t rx_all = pf->pkt_buf_size;
3655 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3656 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3663 * Try to allocate privated packet buffer for all TCs without share
3666 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3670 * Try to allocate privated packet buffer for all TCs with share
3673 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3677 * For different application scenes, the enabled port number, TC number
3678 * and no_drop TC number are different. In order to obtain the better
3679 * performance, software could allocate the buffer size and configure
3680 * the waterline by tring to decrease the private buffer size according
3681 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3684 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3687 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3690 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3697 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3699 struct hns3_rx_priv_buff_cmd *req;
3700 struct hns3_cmd_desc desc;
3705 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3706 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3708 /* Alloc private buffer TCs */
3709 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3710 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3713 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3714 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3717 buf_size = buf_alloc->s_buf.buf_size;
3718 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3719 (1 << HNS3_TC0_PRI_BUF_EN_B));
3721 ret = hns3_cmd_send(hw, &desc, 1);
3723 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3729 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3731 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3732 struct hns3_rx_priv_wl_buf *req;
3733 struct hns3_priv_buf *priv;
3734 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3738 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3739 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3741 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3743 /* The first descriptor set the NEXT bit to 1 */
3745 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3747 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3749 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3750 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3752 priv = &buf_alloc->priv_buf[idx];
3753 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3755 req->tc_wl[j].high |=
3756 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3757 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3759 req->tc_wl[j].low |=
3760 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3764 /* Send 2 descriptor at one time */
3765 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3767 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3773 hns3_common_thrd_config(struct hns3_hw *hw,
3774 struct hns3_pkt_buf_alloc *buf_alloc)
3776 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3777 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3778 struct hns3_rx_com_thrd *req;
3779 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3780 struct hns3_tc_thrd *tc;
3785 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3786 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3788 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3790 /* The first descriptor set the NEXT bit to 1 */
3792 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3794 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3796 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3797 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3798 tc = &s_buf->tc_thrd[tc_idx];
3800 req->com_thrd[j].high =
3801 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3802 req->com_thrd[j].high |=
3803 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3804 req->com_thrd[j].low =
3805 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3806 req->com_thrd[j].low |=
3807 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3811 /* Send 2 descriptors at one time */
3812 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3814 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3820 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3822 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3823 struct hns3_rx_com_wl *req;
3824 struct hns3_cmd_desc desc;
3827 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3829 req = (struct hns3_rx_com_wl *)desc.data;
3830 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3831 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3833 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3834 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3836 ret = hns3_cmd_send(hw, &desc, 1);
3838 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3844 hns3_buffer_alloc(struct hns3_hw *hw)
3846 struct hns3_pkt_buf_alloc pkt_buf;
3849 memset(&pkt_buf, 0, sizeof(pkt_buf));
3850 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3853 "could not calc tx buffer size for all TCs %d",
3858 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3860 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3864 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3867 "could not calc rx priv buffer size for all TCs %d",
3872 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3874 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3878 if (hns3_dev_dcb_supported(hw)) {
3879 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3882 "could not configure rx private waterline %d",
3887 ret = hns3_common_thrd_config(hw, &pkt_buf);
3890 "could not configure common threshold %d",
3896 ret = hns3_common_wl_config(hw, &pkt_buf);
3898 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3905 hns3_mac_init(struct hns3_hw *hw)
3907 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3908 struct hns3_mac *mac = &hw->mac;
3909 struct hns3_pf *pf = &hns->pf;
3912 pf->support_sfp_query = true;
3913 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3914 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3916 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3920 mac->link_status = ETH_LINK_DOWN;
3922 return hns3_config_mtu(hw, pf->mps);
3926 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3928 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
3929 #define HNS3_ETHERTYPE_ALREADY_ADD 1
3930 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
3931 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
3936 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
3941 switch (resp_code) {
3942 case HNS3_ETHERTYPE_SUCCESS_ADD:
3943 case HNS3_ETHERTYPE_ALREADY_ADD:
3946 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3948 "add mac ethertype failed for manager table overflow.");
3949 return_status = -EIO;
3951 case HNS3_ETHERTYPE_KEY_CONFLICT:
3952 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3953 return_status = -EIO;
3957 "add mac ethertype failed for undefined, code=%u.",
3959 return_status = -EIO;
3963 return return_status;
3967 hns3_add_mgr_tbl(struct hns3_hw *hw,
3968 const struct hns3_mac_mgr_tbl_entry_cmd *req)
3970 struct hns3_cmd_desc desc;
3975 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3976 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3978 ret = hns3_cmd_send(hw, &desc, 1);
3981 "add mac ethertype failed for cmd_send, ret =%d.",
3986 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3987 retval = rte_le_to_cpu_16(desc.retval);
3989 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3993 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3994 int *table_item_num)
3996 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3999 * In current version, we add one item in management table as below:
4000 * 0x0180C200000E -- LLDP MC address
4003 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4004 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4005 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4006 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4007 tbl->i_port_bitmap = 0x1;
4008 *table_item_num = 1;
4012 hns3_init_mgr_tbl(struct hns3_hw *hw)
4014 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
4015 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4020 memset(mgr_table, 0, sizeof(mgr_table));
4021 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4022 for (i = 0; i < table_item_num; i++) {
4023 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4025 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4035 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4036 bool en_mc, bool en_bc, int vport_id)
4041 memset(param, 0, sizeof(struct hns3_promisc_param));
4043 param->enable = HNS3_PROMISC_EN_UC;
4045 param->enable |= HNS3_PROMISC_EN_MC;
4047 param->enable |= HNS3_PROMISC_EN_BC;
4048 param->vf_id = vport_id;
4052 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4054 struct hns3_promisc_cfg_cmd *req;
4055 struct hns3_cmd_desc desc;
4058 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4060 req = (struct hns3_promisc_cfg_cmd *)desc.data;
4061 req->vf_id = param->vf_id;
4062 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4063 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4065 ret = hns3_cmd_send(hw, &desc, 1);
4067 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4073 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4075 struct hns3_promisc_param param;
4076 bool en_bc_pmc = true;
4080 * In current version VF is not supported when PF is driven by DPDK
4081 * driver, just need to configure parameters for PF vport.
4083 vf_id = HNS3_PF_FUNC_ID;
4085 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4086 return hns3_cmd_set_promisc_mode(hw, ¶m);
4090 hns3_promisc_init(struct hns3_hw *hw)
4092 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4093 struct hns3_pf *pf = &hns->pf;
4094 struct hns3_promisc_param param;
4098 ret = hns3_set_promisc_mode(hw, false, false);
4100 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4105 * In current version VFs are not supported when PF is driven by DPDK
4106 * driver. After PF has been taken over by DPDK, the original VF will
4107 * be invalid. So, there is a possibility of entry residues. It should
4108 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4111 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4112 hns3_promisc_param_init(¶m, false, false, false, func_id);
4113 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4115 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4116 " ret = %d", func_id, ret);
4125 hns3_promisc_uninit(struct hns3_hw *hw)
4127 struct hns3_promisc_param param;
4131 func_id = HNS3_PF_FUNC_ID;
4134 * In current version VFs are not supported when PF is driven by
4135 * DPDK driver, and VFs' promisc mode status has been cleared during
4136 * init and their status will not change. So just clear PF's promisc
4137 * mode status during uninit.
4139 hns3_promisc_param_init(¶m, false, false, false, func_id);
4140 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4142 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4143 " uninit, ret = %d", ret);
4147 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4149 bool allmulti = dev->data->all_multicast ? true : false;
4150 struct hns3_adapter *hns = dev->data->dev_private;
4151 struct hns3_hw *hw = &hns->hw;
4156 rte_spinlock_lock(&hw->lock);
4157 ret = hns3_set_promisc_mode(hw, true, true);
4159 rte_spinlock_unlock(&hw->lock);
4160 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4166 * When promiscuous mode was enabled, disable the vlan filter to let
4167 * all packets coming in in the receiving direction.
4169 offloads = dev->data->dev_conf.rxmode.offloads;
4170 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4171 ret = hns3_enable_vlan_filter(hns, false);
4173 hns3_err(hw, "failed to enable promiscuous mode due to "
4174 "failure to disable vlan filter, ret = %d",
4176 err = hns3_set_promisc_mode(hw, false, allmulti);
4178 hns3_err(hw, "failed to restore promiscuous "
4179 "status after disable vlan filter "
4180 "failed during enabling promiscuous "
4181 "mode, ret = %d", ret);
4185 rte_spinlock_unlock(&hw->lock);
4191 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4193 bool allmulti = dev->data->all_multicast ? true : false;
4194 struct hns3_adapter *hns = dev->data->dev_private;
4195 struct hns3_hw *hw = &hns->hw;
4200 /* If now in all_multicast mode, must remain in all_multicast mode. */
4201 rte_spinlock_lock(&hw->lock);
4202 ret = hns3_set_promisc_mode(hw, false, allmulti);
4204 rte_spinlock_unlock(&hw->lock);
4205 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4209 /* when promiscuous mode was disabled, restore the vlan filter status */
4210 offloads = dev->data->dev_conf.rxmode.offloads;
4211 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4212 ret = hns3_enable_vlan_filter(hns, true);
4214 hns3_err(hw, "failed to disable promiscuous mode due to"
4215 " failure to restore vlan filter, ret = %d",
4217 err = hns3_set_promisc_mode(hw, true, true);
4219 hns3_err(hw, "failed to restore promiscuous "
4220 "status after enabling vlan filter "
4221 "failed during disabling promiscuous "
4222 "mode, ret = %d", ret);
4225 rte_spinlock_unlock(&hw->lock);
4231 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4233 struct hns3_adapter *hns = dev->data->dev_private;
4234 struct hns3_hw *hw = &hns->hw;
4237 if (dev->data->promiscuous)
4240 rte_spinlock_lock(&hw->lock);
4241 ret = hns3_set_promisc_mode(hw, false, true);
4242 rte_spinlock_unlock(&hw->lock);
4244 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4251 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4253 struct hns3_adapter *hns = dev->data->dev_private;
4254 struct hns3_hw *hw = &hns->hw;
4257 /* If now in promiscuous mode, must remain in all_multicast mode. */
4258 if (dev->data->promiscuous)
4261 rte_spinlock_lock(&hw->lock);
4262 ret = hns3_set_promisc_mode(hw, false, false);
4263 rte_spinlock_unlock(&hw->lock);
4265 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4272 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4274 struct hns3_hw *hw = &hns->hw;
4275 bool allmulti = hw->data->all_multicast ? true : false;
4278 if (hw->data->promiscuous) {
4279 ret = hns3_set_promisc_mode(hw, true, true);
4281 hns3_err(hw, "failed to restore promiscuous mode, "
4286 ret = hns3_set_promisc_mode(hw, false, allmulti);
4288 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4294 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4296 struct hns3_sfp_speed_cmd *resp;
4297 struct hns3_cmd_desc desc;
4300 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4301 resp = (struct hns3_sfp_speed_cmd *)desc.data;
4302 ret = hns3_cmd_send(hw, &desc, 1);
4303 if (ret == -EOPNOTSUPP) {
4304 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4307 hns3_err(hw, "get sfp speed failed %d", ret);
4311 *speed = resp->sfp_speed;
4317 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4319 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4320 duplex = ETH_LINK_FULL_DUPLEX;
4326 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4328 struct hns3_mac *mac = &hw->mac;
4329 uint32_t cur_speed = mac->link_speed;
4332 duplex = hns3_check_speed_dup(duplex, speed);
4333 if (mac->link_speed == speed && mac->link_duplex == duplex)
4336 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4340 mac->link_speed = speed;
4341 ret = hns3_dcb_port_shaper_cfg(hw);
4343 hns3_err(hw, "failed to configure port shaper, ret = %d.", ret);
4344 mac->link_speed = cur_speed;
4348 mac->link_duplex = duplex;
4354 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4356 struct hns3_adapter *hns = eth_dev->data->dev_private;
4357 struct hns3_hw *hw = &hns->hw;
4358 struct hns3_pf *pf = &hns->pf;
4362 /* If IMP do not support get SFP/qSFP speed, return directly */
4363 if (!pf->support_sfp_query)
4366 ret = hns3_get_sfp_speed(hw, &speed);
4367 if (ret == -EOPNOTSUPP) {
4368 pf->support_sfp_query = false;
4373 if (speed == ETH_SPEED_NUM_NONE)
4374 return 0; /* do nothing if no SFP */
4376 /* Config full duplex for SFP */
4377 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4381 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4383 struct hns3_config_mac_mode_cmd *req;
4384 struct hns3_cmd_desc desc;
4385 uint32_t loop_en = 0;
4389 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4391 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4394 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4395 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4396 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4397 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4398 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4399 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4400 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4401 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4402 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4403 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4406 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4407 * when receiving frames. Otherwise, CRC will be stripped.
4409 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4410 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4412 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4413 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4414 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4415 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4416 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4418 ret = hns3_cmd_send(hw, &desc, 1);
4420 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4426 hns3_get_mac_link_status(struct hns3_hw *hw)
4428 struct hns3_link_status_cmd *req;
4429 struct hns3_cmd_desc desc;
4433 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4434 ret = hns3_cmd_send(hw, &desc, 1);
4436 hns3_err(hw, "get link status cmd failed %d", ret);
4437 return ETH_LINK_DOWN;
4440 req = (struct hns3_link_status_cmd *)desc.data;
4441 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4443 return !!link_status;
4447 hns3_update_link_status(struct hns3_hw *hw)
4451 state = hns3_get_mac_link_status(hw);
4452 if (state != hw->mac.link_status) {
4453 hw->mac.link_status = state;
4454 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4459 hns3_service_handler(void *param)
4461 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4462 struct hns3_adapter *hns = eth_dev->data->dev_private;
4463 struct hns3_hw *hw = &hns->hw;
4465 if (!hns3_is_reset_pending(hns)) {
4466 hns3_update_speed_duplex(eth_dev);
4467 hns3_update_link_status(hw);
4469 hns3_warn(hw, "Cancel the query when reset is pending");
4471 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4475 hns3_init_hardware(struct hns3_adapter *hns)
4477 struct hns3_hw *hw = &hns->hw;
4480 ret = hns3_map_tqp(hw);
4482 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4486 ret = hns3_init_umv_space(hw);
4488 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4492 ret = hns3_mac_init(hw);
4494 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4498 ret = hns3_init_mgr_tbl(hw);
4500 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4504 ret = hns3_promisc_init(hw);
4506 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4511 ret = hns3_init_vlan_config(hns);
4513 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4517 ret = hns3_dcb_init(hw);
4519 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4523 ret = hns3_init_fd_config(hns);
4525 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4529 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4531 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4535 ret = hns3_config_gro(hw, false);
4537 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4542 * In the initialization clearing the all hardware mapping relationship
4543 * configurations between queues and interrupt vectors is needed, so
4544 * some error caused by the residual configurations, such as the
4545 * unexpected interrupt, can be avoid.
4547 ret = hns3_init_ring_with_vector(hw);
4549 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4556 hns3_uninit_umv_space(hw);
4561 hns3_clear_hw(struct hns3_hw *hw)
4563 struct hns3_cmd_desc desc;
4566 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4568 ret = hns3_cmd_send(hw, &desc, 1);
4569 if (ret && ret != -EOPNOTSUPP)
4576 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4581 * The new firmware support report more hardware error types by
4582 * msix mode. These errors are defined as RAS errors in hardware
4583 * and belong to a different type from the MSI-x errors processed
4584 * by the network driver.
4586 * Network driver should open the new error report on initialition
4588 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4589 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4590 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4594 hns3_init_pf(struct rte_eth_dev *eth_dev)
4596 struct rte_device *dev = eth_dev->device;
4597 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4598 struct hns3_adapter *hns = eth_dev->data->dev_private;
4599 struct hns3_hw *hw = &hns->hw;
4602 PMD_INIT_FUNC_TRACE();
4604 /* Get hardware io base address from pcie BAR2 IO space */
4605 hw->io_base = pci_dev->mem_resource[2].addr;
4607 /* Firmware command queue initialize */
4608 ret = hns3_cmd_init_queue(hw);
4610 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4611 goto err_cmd_init_queue;
4614 hns3_clear_all_event_cause(hw);
4616 /* Firmware command initialize */
4617 ret = hns3_cmd_init(hw);
4619 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4624 * To ensure that the hardware environment is clean during
4625 * initialization, the driver actively clear the hardware environment
4626 * during initialization, including PF and corresponding VFs' vlan, mac,
4627 * flow table configurations, etc.
4629 ret = hns3_clear_hw(hw);
4631 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4635 hns3_config_all_msix_error(hw, true);
4637 ret = rte_intr_callback_register(&pci_dev->intr_handle,
4638 hns3_interrupt_handler,
4641 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4642 goto err_intr_callback_register;
4645 /* Enable interrupt */
4646 rte_intr_enable(&pci_dev->intr_handle);
4647 hns3_pf_enable_irq0(hw);
4649 /* Get configuration */
4650 ret = hns3_get_configuration(hw);
4652 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4653 goto err_get_config;
4656 ret = hns3_tqp_stats_init(hw);
4658 goto err_get_config;
4660 ret = hns3_init_hardware(hns);
4662 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4666 /* Initialize flow director filter list & hash */
4667 ret = hns3_fdir_filter_init(hns);
4669 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4673 hns3_set_default_rss_args(hw);
4675 ret = hns3_enable_hw_error_intr(hns, true);
4677 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4679 goto err_enable_intr;
4685 hns3_fdir_filter_uninit(hns);
4687 hns3_uninit_umv_space(hw);
4689 hns3_tqp_stats_uninit(hw);
4691 hns3_pf_disable_irq0(hw);
4692 rte_intr_disable(&pci_dev->intr_handle);
4693 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4695 err_intr_callback_register:
4697 hns3_cmd_uninit(hw);
4698 hns3_cmd_destroy_queue(hw);
4706 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4708 struct hns3_adapter *hns = eth_dev->data->dev_private;
4709 struct rte_device *dev = eth_dev->device;
4710 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4711 struct hns3_hw *hw = &hns->hw;
4713 PMD_INIT_FUNC_TRACE();
4715 hns3_enable_hw_error_intr(hns, false);
4716 hns3_rss_uninit(hns);
4717 (void)hns3_config_gro(hw, false);
4718 hns3_promisc_uninit(hw);
4719 hns3_fdir_filter_uninit(hns);
4720 hns3_uninit_umv_space(hw);
4721 hns3_tqp_stats_uninit(hw);
4722 hns3_pf_disable_irq0(hw);
4723 rte_intr_disable(&pci_dev->intr_handle);
4724 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4726 hns3_config_all_msix_error(hw, false);
4727 hns3_cmd_uninit(hw);
4728 hns3_cmd_destroy_queue(hw);
4733 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4735 struct hns3_hw *hw = &hns->hw;
4738 ret = hns3_dcb_cfg_update(hns);
4742 ret = hns3_init_queues(hns, reset_queue);
4744 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
4748 ret = hns3_cfg_mac_mode(hw, true);
4750 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
4751 goto err_config_mac_mode;
4755 err_config_mac_mode:
4756 hns3_dev_release_mbufs(hns);
4758 * Here is exception handling, hns3_reset_all_tqps will have the
4759 * corresponding error message if it is handled incorrectly, so it is
4760 * not necessary to check hns3_reset_all_tqps return value, here keep
4761 * ret as the error code causing the exception.
4763 (void)hns3_reset_all_tqps(hns);
4768 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4770 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4771 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4772 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4773 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4774 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4775 uint32_t intr_vector;
4779 if (dev->data->dev_conf.intr_conf.rxq == 0)
4782 /* disable uio/vfio intr/eventfd mapping */
4783 rte_intr_disable(intr_handle);
4785 /* check and configure queue intr-vector mapping */
4786 if (rte_intr_cap_multiple(intr_handle) ||
4787 !RTE_ETH_DEV_SRIOV(dev).active) {
4788 intr_vector = hw->used_rx_queues;
4789 /* creates event fd for each intr vector when MSIX is used */
4790 if (rte_intr_efd_enable(intr_handle, intr_vector))
4793 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4794 intr_handle->intr_vec =
4795 rte_zmalloc("intr_vec",
4796 hw->used_rx_queues * sizeof(int), 0);
4797 if (intr_handle->intr_vec == NULL) {
4798 hns3_err(hw, "Failed to allocate %u rx_queues"
4799 " intr_vec", hw->used_rx_queues);
4801 goto alloc_intr_vec_error;
4805 if (rte_intr_allow_others(intr_handle)) {
4806 vec = RTE_INTR_VEC_RXTX_OFFSET;
4807 base = RTE_INTR_VEC_RXTX_OFFSET;
4809 if (rte_intr_dp_is_en(intr_handle)) {
4810 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4811 ret = hns3_bind_ring_with_vector(hw, vec, true,
4815 goto bind_vector_error;
4816 intr_handle->intr_vec[q_id] = vec;
4817 if (vec < base + intr_handle->nb_efd - 1)
4821 rte_intr_enable(intr_handle);
4825 rte_intr_efd_disable(intr_handle);
4826 if (intr_handle->intr_vec) {
4827 free(intr_handle->intr_vec);
4828 intr_handle->intr_vec = NULL;
4831 alloc_intr_vec_error:
4832 rte_intr_efd_disable(intr_handle);
4837 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4839 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4840 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4841 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4845 if (dev->data->dev_conf.intr_conf.rxq == 0)
4848 if (rte_intr_dp_is_en(intr_handle)) {
4849 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4850 ret = hns3_bind_ring_with_vector(hw,
4851 intr_handle->intr_vec[q_id], true,
4852 HNS3_RING_TYPE_RX, q_id);
4862 hns3_restore_filter(struct rte_eth_dev *dev)
4864 hns3_restore_rss_filter(dev);
4868 hns3_dev_start(struct rte_eth_dev *dev)
4870 struct hns3_adapter *hns = dev->data->dev_private;
4871 struct hns3_hw *hw = &hns->hw;
4874 PMD_INIT_FUNC_TRACE();
4875 if (rte_atomic16_read(&hw->reset.resetting))
4878 rte_spinlock_lock(&hw->lock);
4879 hw->adapter_state = HNS3_NIC_STARTING;
4881 ret = hns3_do_start(hns, true);
4883 hw->adapter_state = HNS3_NIC_CONFIGURED;
4884 rte_spinlock_unlock(&hw->lock);
4887 ret = hns3_map_rx_interrupt(dev);
4889 hw->adapter_state = HNS3_NIC_CONFIGURED;
4890 rte_spinlock_unlock(&hw->lock);
4895 * There are three register used to control the status of a TQP
4896 * (contains a pair of Tx queue and Rx queue) in the new version network
4897 * engine. One is used to control the enabling of Tx queue, the other is
4898 * used to control the enabling of Rx queue, and the last is the master
4899 * switch used to control the enabling of the tqp. The Tx register and
4900 * TQP register must be enabled at the same time to enable a Tx queue.
4901 * The same applies to the Rx queue. For the older network engine, this
4902 * function only refresh the enabled flag, and it is used to update the
4903 * status of queue in the dpdk framework.
4905 ret = hns3_start_all_txqs(dev);
4907 hw->adapter_state = HNS3_NIC_CONFIGURED;
4908 rte_spinlock_unlock(&hw->lock);
4912 ret = hns3_start_all_rxqs(dev);
4914 hns3_stop_all_txqs(dev);
4915 hw->adapter_state = HNS3_NIC_CONFIGURED;
4916 rte_spinlock_unlock(&hw->lock);
4920 hw->adapter_state = HNS3_NIC_STARTED;
4921 rte_spinlock_unlock(&hw->lock);
4923 hns3_rx_scattered_calc(dev);
4924 hns3_set_rxtx_function(dev);
4925 hns3_mp_req_start_rxtx(dev);
4926 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4928 hns3_restore_filter(dev);
4930 /* Enable interrupt of all rx queues before enabling queues */
4931 hns3_dev_all_rx_queue_intr_enable(hw, true);
4934 * After finished the initialization, enable tqps to receive/transmit
4935 * packets and refresh all queue status.
4937 hns3_start_tqps(hw);
4939 hns3_info(hw, "hns3 dev start successful!");
4944 hns3_do_stop(struct hns3_adapter *hns)
4946 struct hns3_hw *hw = &hns->hw;
4949 ret = hns3_cfg_mac_mode(hw, false);
4952 hw->mac.link_status = ETH_LINK_DOWN;
4954 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4955 hns3_configure_all_mac_addr(hns, true);
4956 ret = hns3_reset_all_tqps(hns);
4958 hns3_err(hw, "failed to reset all queues ret = %d.",
4963 hw->mac.default_addr_setted = false;
4968 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4970 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4971 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4972 struct hns3_adapter *hns = dev->data->dev_private;
4973 struct hns3_hw *hw = &hns->hw;
4974 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4975 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4978 if (dev->data->dev_conf.intr_conf.rxq == 0)
4981 /* unmap the ring with vector */
4982 if (rte_intr_allow_others(intr_handle)) {
4983 vec = RTE_INTR_VEC_RXTX_OFFSET;
4984 base = RTE_INTR_VEC_RXTX_OFFSET;
4986 if (rte_intr_dp_is_en(intr_handle)) {
4987 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4988 (void)hns3_bind_ring_with_vector(hw, vec, false,
4991 if (vec < base + intr_handle->nb_efd - 1)
4995 /* Clean datapath event and queue/vec mapping */
4996 rte_intr_efd_disable(intr_handle);
4997 if (intr_handle->intr_vec) {
4998 rte_free(intr_handle->intr_vec);
4999 intr_handle->intr_vec = NULL;
5004 hns3_dev_stop(struct rte_eth_dev *dev)
5006 struct hns3_adapter *hns = dev->data->dev_private;
5007 struct hns3_hw *hw = &hns->hw;
5009 PMD_INIT_FUNC_TRACE();
5010 dev->data->dev_started = 0;
5012 hw->adapter_state = HNS3_NIC_STOPPING;
5013 hns3_set_rxtx_function(dev);
5015 /* Disable datapath on secondary process. */
5016 hns3_mp_req_stop_rxtx(dev);
5017 /* Prevent crashes when queues are still in use. */
5018 rte_delay_ms(hw->tqps_num);
5020 rte_spinlock_lock(&hw->lock);
5021 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
5024 hns3_unmap_rx_interrupt(dev);
5025 hns3_dev_release_mbufs(hns);
5026 hw->adapter_state = HNS3_NIC_CONFIGURED;
5028 hns3_rx_scattered_reset(dev);
5029 rte_eal_alarm_cancel(hns3_service_handler, dev);
5030 rte_spinlock_unlock(&hw->lock);
5036 hns3_dev_close(struct rte_eth_dev *eth_dev)
5038 struct hns3_adapter *hns = eth_dev->data->dev_private;
5039 struct hns3_hw *hw = &hns->hw;
5042 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5043 rte_free(eth_dev->process_private);
5044 eth_dev->process_private = NULL;
5048 if (hw->adapter_state == HNS3_NIC_STARTED)
5049 ret = hns3_dev_stop(eth_dev);
5051 hw->adapter_state = HNS3_NIC_CLOSING;
5052 hns3_reset_abort(hns);
5053 hw->adapter_state = HNS3_NIC_CLOSED;
5055 hns3_configure_all_mc_mac_addr(hns, true);
5056 hns3_remove_all_vlan_table(hns);
5057 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5058 hns3_uninit_pf(eth_dev);
5059 hns3_free_all_queues(eth_dev);
5060 rte_free(hw->reset.wait_data);
5061 rte_free(eth_dev->process_private);
5062 eth_dev->process_private = NULL;
5063 hns3_mp_uninit_primary();
5064 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5070 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5072 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5073 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5075 fc_conf->pause_time = pf->pause_time;
5077 /* return fc current mode */
5078 switch (hw->current_mode) {
5080 fc_conf->mode = RTE_FC_FULL;
5082 case HNS3_FC_TX_PAUSE:
5083 fc_conf->mode = RTE_FC_TX_PAUSE;
5085 case HNS3_FC_RX_PAUSE:
5086 fc_conf->mode = RTE_FC_RX_PAUSE;
5090 fc_conf->mode = RTE_FC_NONE;
5098 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5102 hw->requested_mode = HNS3_FC_NONE;
5104 case RTE_FC_RX_PAUSE:
5105 hw->requested_mode = HNS3_FC_RX_PAUSE;
5107 case RTE_FC_TX_PAUSE:
5108 hw->requested_mode = HNS3_FC_TX_PAUSE;
5111 hw->requested_mode = HNS3_FC_FULL;
5114 hw->requested_mode = HNS3_FC_NONE;
5115 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5116 "configured to RTE_FC_NONE", mode);
5122 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5124 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5125 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5128 if (fc_conf->high_water || fc_conf->low_water ||
5129 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5130 hns3_err(hw, "Unsupported flow control settings specified, "
5131 "high_water(%u), low_water(%u), send_xon(%u) and "
5132 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5133 fc_conf->high_water, fc_conf->low_water,
5134 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5137 if (fc_conf->autoneg) {
5138 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5141 if (!fc_conf->pause_time) {
5142 hns3_err(hw, "Invalid pause time %u setting.",
5143 fc_conf->pause_time);
5147 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5148 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5149 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5150 "current_fc_status = %d", hw->current_fc_status);
5154 hns3_get_fc_mode(hw, fc_conf->mode);
5155 if (hw->requested_mode == hw->current_mode &&
5156 pf->pause_time == fc_conf->pause_time)
5159 rte_spinlock_lock(&hw->lock);
5160 ret = hns3_fc_enable(dev, fc_conf);
5161 rte_spinlock_unlock(&hw->lock);
5167 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5168 struct rte_eth_pfc_conf *pfc_conf)
5170 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5171 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5175 if (!hns3_dev_dcb_supported(hw)) {
5176 hns3_err(hw, "This port does not support dcb configurations.");
5180 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5181 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5182 hns3_err(hw, "Unsupported flow control settings specified, "
5183 "high_water(%u), low_water(%u), send_xon(%u) and "
5184 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5185 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5186 pfc_conf->fc.send_xon,
5187 pfc_conf->fc.mac_ctrl_frame_fwd);
5190 if (pfc_conf->fc.autoneg) {
5191 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5194 if (pfc_conf->fc.pause_time == 0) {
5195 hns3_err(hw, "Invalid pause time %u setting.",
5196 pfc_conf->fc.pause_time);
5200 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5201 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5202 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5203 "current_fc_status = %d", hw->current_fc_status);
5207 priority = pfc_conf->priority;
5208 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5209 if (hw->dcb_info.pfc_en & BIT(priority) &&
5210 hw->requested_mode == hw->current_mode &&
5211 pfc_conf->fc.pause_time == pf->pause_time)
5214 rte_spinlock_lock(&hw->lock);
5215 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5216 rte_spinlock_unlock(&hw->lock);
5222 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5224 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5225 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5226 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5229 rte_spinlock_lock(&hw->lock);
5230 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5231 dcb_info->nb_tcs = pf->local_max_tc;
5233 dcb_info->nb_tcs = 1;
5235 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5236 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5237 for (i = 0; i < dcb_info->nb_tcs; i++)
5238 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5240 for (i = 0; i < hw->num_tc; i++) {
5241 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5242 dcb_info->tc_queue.tc_txq[0][i].base =
5243 hw->tc_queue[i].tqp_offset;
5244 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5245 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5246 hw->tc_queue[i].tqp_count;
5248 rte_spinlock_unlock(&hw->lock);
5254 hns3_reinit_dev(struct hns3_adapter *hns)
5256 struct hns3_hw *hw = &hns->hw;
5259 ret = hns3_cmd_init(hw);
5261 hns3_err(hw, "Failed to init cmd: %d", ret);
5265 ret = hns3_reset_all_tqps(hns);
5267 hns3_err(hw, "Failed to reset all queues: %d", ret);
5271 ret = hns3_init_hardware(hns);
5273 hns3_err(hw, "Failed to init hardware: %d", ret);
5277 ret = hns3_enable_hw_error_intr(hns, true);
5279 hns3_err(hw, "fail to enable hw error interrupts: %d",
5283 hns3_info(hw, "Reset done, driver initialization finished.");
5289 is_pf_reset_done(struct hns3_hw *hw)
5291 uint32_t val, reg, reg_bit;
5293 switch (hw->reset.level) {
5294 case HNS3_IMP_RESET:
5295 reg = HNS3_GLOBAL_RESET_REG;
5296 reg_bit = HNS3_IMP_RESET_BIT;
5298 case HNS3_GLOBAL_RESET:
5299 reg = HNS3_GLOBAL_RESET_REG;
5300 reg_bit = HNS3_GLOBAL_RESET_BIT;
5302 case HNS3_FUNC_RESET:
5303 reg = HNS3_FUN_RST_ING;
5304 reg_bit = HNS3_FUN_RST_ING_B;
5306 case HNS3_FLR_RESET:
5308 hns3_err(hw, "Wait for unsupported reset level: %d",
5312 val = hns3_read_dev(hw, reg);
5313 if (hns3_get_bit(val, reg_bit))
5320 hns3_is_reset_pending(struct hns3_adapter *hns)
5322 struct hns3_hw *hw = &hns->hw;
5323 enum hns3_reset_level reset;
5325 hns3_check_event_cause(hns, NULL);
5326 reset = hns3_get_reset_level(hns, &hw->reset.pending);
5327 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5328 hns3_warn(hw, "High level reset %d is pending", reset);
5331 reset = hns3_get_reset_level(hns, &hw->reset.request);
5332 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5333 hns3_warn(hw, "High level reset %d is request", reset);
5340 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5342 struct hns3_hw *hw = &hns->hw;
5343 struct hns3_wait_data *wait_data = hw->reset.wait_data;
5346 if (wait_data->result == HNS3_WAIT_SUCCESS)
5348 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5349 gettimeofday(&tv, NULL);
5350 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5351 tv.tv_sec, tv.tv_usec);
5353 } else if (wait_data->result == HNS3_WAIT_REQUEST)
5356 wait_data->hns = hns;
5357 wait_data->check_completion = is_pf_reset_done;
5358 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5359 HNS3_RESET_WAIT_MS + get_timeofday_ms();
5360 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5361 wait_data->count = HNS3_RESET_WAIT_CNT;
5362 wait_data->result = HNS3_WAIT_REQUEST;
5363 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5368 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5370 struct hns3_cmd_desc desc;
5371 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5373 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5374 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5375 req->fun_reset_vfid = func_id;
5377 return hns3_cmd_send(hw, &desc, 1);
5381 hns3_imp_reset_cmd(struct hns3_hw *hw)
5383 struct hns3_cmd_desc desc;
5385 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5386 desc.data[0] = 0xeedd;
5388 return hns3_cmd_send(hw, &desc, 1);
5392 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5394 struct hns3_hw *hw = &hns->hw;
5398 gettimeofday(&tv, NULL);
5399 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5400 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5401 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5402 tv.tv_sec, tv.tv_usec);
5406 switch (reset_level) {
5407 case HNS3_IMP_RESET:
5408 hns3_imp_reset_cmd(hw);
5409 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5410 tv.tv_sec, tv.tv_usec);
5412 case HNS3_GLOBAL_RESET:
5413 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5414 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5415 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5416 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5417 tv.tv_sec, tv.tv_usec);
5419 case HNS3_FUNC_RESET:
5420 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5421 tv.tv_sec, tv.tv_usec);
5422 /* schedule again to check later */
5423 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5424 hns3_schedule_reset(hns);
5427 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5430 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5433 static enum hns3_reset_level
5434 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5436 struct hns3_hw *hw = &hns->hw;
5437 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5439 /* Return the highest priority reset level amongst all */
5440 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5441 reset_level = HNS3_IMP_RESET;
5442 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5443 reset_level = HNS3_GLOBAL_RESET;
5444 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5445 reset_level = HNS3_FUNC_RESET;
5446 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5447 reset_level = HNS3_FLR_RESET;
5449 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5450 return HNS3_NONE_RESET;
5456 hns3_record_imp_error(struct hns3_adapter *hns)
5458 struct hns3_hw *hw = &hns->hw;
5461 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5462 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5463 hns3_warn(hw, "Detected IMP RD poison!");
5464 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5465 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5466 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5469 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5470 hns3_warn(hw, "Detected IMP CMDQ error!");
5471 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5472 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5473 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5478 hns3_prepare_reset(struct hns3_adapter *hns)
5480 struct hns3_hw *hw = &hns->hw;
5484 switch (hw->reset.level) {
5485 case HNS3_FUNC_RESET:
5486 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5491 * After performaning pf reset, it is not necessary to do the
5492 * mailbox handling or send any command to firmware, because
5493 * any mailbox handling or command to firmware is only valid
5494 * after hns3_cmd_init is called.
5496 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5497 hw->reset.stats.request_cnt++;
5499 case HNS3_IMP_RESET:
5500 hns3_record_imp_error(hns);
5501 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5502 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5503 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5512 hns3_set_rst_done(struct hns3_hw *hw)
5514 struct hns3_pf_rst_done_cmd *req;
5515 struct hns3_cmd_desc desc;
5517 req = (struct hns3_pf_rst_done_cmd *)desc.data;
5518 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5519 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5520 return hns3_cmd_send(hw, &desc, 1);
5524 hns3_stop_service(struct hns3_adapter *hns)
5526 struct hns3_hw *hw = &hns->hw;
5527 struct rte_eth_dev *eth_dev;
5529 eth_dev = &rte_eth_devices[hw->data->port_id];
5530 if (hw->adapter_state == HNS3_NIC_STARTED)
5531 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5532 hw->mac.link_status = ETH_LINK_DOWN;
5534 hns3_set_rxtx_function(eth_dev);
5536 /* Disable datapath on secondary process. */
5537 hns3_mp_req_stop_rxtx(eth_dev);
5538 rte_delay_ms(hw->tqps_num);
5540 rte_spinlock_lock(&hw->lock);
5541 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5542 hw->adapter_state == HNS3_NIC_STOPPING) {
5543 hns3_enable_all_queues(hw, false);
5545 hw->reset.mbuf_deferred_free = true;
5547 hw->reset.mbuf_deferred_free = false;
5550 * It is cumbersome for hardware to pick-and-choose entries for deletion
5551 * from table space. Hence, for function reset software intervention is
5552 * required to delete the entries
5554 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5555 hns3_configure_all_mc_mac_addr(hns, true);
5556 rte_spinlock_unlock(&hw->lock);
5562 hns3_start_service(struct hns3_adapter *hns)
5564 struct hns3_hw *hw = &hns->hw;
5565 struct rte_eth_dev *eth_dev;
5567 if (hw->reset.level == HNS3_IMP_RESET ||
5568 hw->reset.level == HNS3_GLOBAL_RESET)
5569 hns3_set_rst_done(hw);
5570 eth_dev = &rte_eth_devices[hw->data->port_id];
5571 hns3_set_rxtx_function(eth_dev);
5572 hns3_mp_req_start_rxtx(eth_dev);
5573 if (hw->adapter_state == HNS3_NIC_STARTED) {
5574 hns3_service_handler(eth_dev);
5576 /* Enable interrupt of all rx queues before enabling queues */
5577 hns3_dev_all_rx_queue_intr_enable(hw, true);
5579 * Enable state of each rxq and txq will be recovered after
5580 * reset, so we need to restore them before enable all tqps;
5582 hns3_restore_tqp_enable_state(hw);
5584 * When finished the initialization, enable queues to receive
5585 * and transmit packets.
5587 hns3_enable_all_queues(hw, true);
5594 hns3_restore_conf(struct hns3_adapter *hns)
5596 struct hns3_hw *hw = &hns->hw;
5599 ret = hns3_configure_all_mac_addr(hns, false);
5603 ret = hns3_configure_all_mc_mac_addr(hns, false);
5607 ret = hns3_dev_promisc_restore(hns);
5611 ret = hns3_restore_vlan_table(hns);
5615 ret = hns3_restore_vlan_conf(hns);
5619 ret = hns3_restore_all_fdir_filter(hns);
5623 ret = hns3_restore_rx_interrupt(hw);
5627 ret = hns3_restore_gro_conf(hw);
5631 ret = hns3_restore_fec(hw);
5635 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5636 ret = hns3_do_start(hns, false);
5639 hns3_info(hw, "hns3 dev restart successful!");
5640 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5641 hw->adapter_state = HNS3_NIC_CONFIGURED;
5645 hns3_configure_all_mc_mac_addr(hns, true);
5647 hns3_configure_all_mac_addr(hns, true);
5652 hns3_reset_service(void *param)
5654 struct hns3_adapter *hns = (struct hns3_adapter *)param;
5655 struct hns3_hw *hw = &hns->hw;
5656 enum hns3_reset_level reset_level;
5657 struct timeval tv_delta;
5658 struct timeval tv_start;
5664 * The interrupt is not triggered within the delay time.
5665 * The interrupt may have been lost. It is necessary to handle
5666 * the interrupt to recover from the error.
5668 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5669 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5670 hns3_err(hw, "Handling interrupts in delayed tasks");
5671 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5672 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5673 if (reset_level == HNS3_NONE_RESET) {
5674 hns3_err(hw, "No reset level is set, try IMP reset");
5675 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5678 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5681 * Check if there is any ongoing reset in the hardware. This status can
5682 * be checked from reset_pending. If there is then, we need to wait for
5683 * hardware to complete reset.
5684 * a. If we are able to figure out in reasonable time that hardware
5685 * has fully resetted then, we can proceed with driver, client
5687 * b. else, we can come back later to check this status so re-sched
5690 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5691 if (reset_level != HNS3_NONE_RESET) {
5692 gettimeofday(&tv_start, NULL);
5693 ret = hns3_reset_process(hns, reset_level);
5694 gettimeofday(&tv, NULL);
5695 timersub(&tv, &tv_start, &tv_delta);
5696 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5697 tv_delta.tv_usec / USEC_PER_MSEC;
5698 if (msec > HNS3_RESET_PROCESS_MS)
5699 hns3_err(hw, "%d handle long time delta %" PRIx64
5700 " ms time=%ld.%.6ld",
5701 hw->reset.level, msec,
5702 tv.tv_sec, tv.tv_usec);
5707 /* Check if we got any *new* reset requests to be honored */
5708 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5709 if (reset_level != HNS3_NONE_RESET)
5710 hns3_msix_process(hns, reset_level);
5714 hns3_get_speed_capa_num(uint16_t device_id)
5718 switch (device_id) {
5719 case HNS3_DEV_ID_25GE:
5720 case HNS3_DEV_ID_25GE_RDMA:
5723 case HNS3_DEV_ID_100G_RDMA_MACSEC:
5724 case HNS3_DEV_ID_200G_RDMA:
5736 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
5739 switch (device_id) {
5740 case HNS3_DEV_ID_25GE:
5742 case HNS3_DEV_ID_25GE_RDMA:
5743 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
5744 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
5746 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
5747 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
5748 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
5750 case HNS3_DEV_ID_100G_RDMA_MACSEC:
5751 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
5752 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
5754 case HNS3_DEV_ID_200G_RDMA:
5755 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
5756 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
5766 hns3_fec_get_capability(struct rte_eth_dev *dev,
5767 struct rte_eth_fec_capa *speed_fec_capa,
5770 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5771 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5772 uint16_t device_id = pci_dev->id.device_id;
5773 unsigned int capa_num;
5776 capa_num = hns3_get_speed_capa_num(device_id);
5777 if (capa_num == 0) {
5778 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
5783 if (speed_fec_capa == NULL || num < capa_num)
5786 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
5794 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
5796 struct hns3_config_fec_cmd *req;
5797 struct hns3_cmd_desc desc;
5801 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
5802 * in device of link speed
5805 if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
5810 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
5811 req = (struct hns3_config_fec_cmd *)desc.data;
5812 ret = hns3_cmd_send(hw, &desc, 1);
5814 hns3_err(hw, "get current fec auto state failed, ret = %d",
5819 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
5824 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
5826 #define QUERY_ACTIVE_SPEED 1
5827 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5828 struct hns3_sfp_speed_cmd *resp;
5829 uint32_t tmp_fec_capa;
5831 struct hns3_cmd_desc desc;
5835 * If link is down and AUTO is enabled, AUTO is returned, otherwise,
5836 * configured FEC mode is returned.
5837 * If link is up, current FEC mode is returned.
5839 if (hw->mac.link_status == ETH_LINK_DOWN) {
5840 ret = get_current_fec_auto_state(hw, &auto_state);
5844 if (auto_state == 0x1) {
5845 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
5850 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
5851 resp = (struct hns3_sfp_speed_cmd *)desc.data;
5852 resp->query_type = QUERY_ACTIVE_SPEED;
5854 ret = hns3_cmd_send(hw, &desc, 1);
5855 if (ret == -EOPNOTSUPP) {
5856 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
5859 hns3_err(hw, "get FEC failed, ret = %d", ret);
5864 * FEC mode order defined in hns3 hardware is inconsistend with
5865 * that defined in the ethdev library. So the sequence needs
5868 switch (resp->active_fec) {
5869 case HNS3_HW_FEC_MODE_NOFEC:
5870 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5872 case HNS3_HW_FEC_MODE_BASER:
5873 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
5875 case HNS3_HW_FEC_MODE_RS:
5876 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
5879 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5883 *fec_capa = tmp_fec_capa;
5888 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
5890 struct hns3_config_fec_cmd *req;
5891 struct hns3_cmd_desc desc;
5894 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
5896 req = (struct hns3_config_fec_cmd *)desc.data;
5898 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
5899 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5900 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
5902 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
5903 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5904 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
5906 case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
5907 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5908 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
5910 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
5911 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
5916 ret = hns3_cmd_send(hw, &desc, 1);
5918 hns3_err(hw, "set fec mode failed, ret = %d", ret);
5924 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
5926 struct hns3_mac *mac = &hw->mac;
5929 switch (mac->link_speed) {
5930 case ETH_SPEED_NUM_10G:
5931 cur_capa = fec_capa[1].capa;
5933 case ETH_SPEED_NUM_25G:
5934 case ETH_SPEED_NUM_100G:
5935 case ETH_SPEED_NUM_200G:
5936 cur_capa = fec_capa[0].capa;
5947 is_fec_mode_one_bit_set(uint32_t mode)
5952 for (i = 0; i < sizeof(mode); i++)
5953 if (mode >> i & 0x1)
5956 return cnt == 1 ? true : false;
5960 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
5962 #define FEC_CAPA_NUM 2
5963 struct hns3_adapter *hns = dev->data->dev_private;
5964 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
5965 struct hns3_pf *pf = &hns->pf;
5967 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
5969 uint32_t num = FEC_CAPA_NUM;
5972 ret = hns3_fec_get_capability(dev, fec_capa, num);
5976 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
5977 if (!is_fec_mode_one_bit_set(mode))
5978 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
5979 "FEC mode should be only one bit set", mode);
5982 * Check whether the configured mode is within the FEC capability.
5983 * If not, the configured mode will not be supported.
5985 cur_capa = get_current_speed_fec_cap(hw, fec_capa);
5986 if (!(cur_capa & mode)) {
5987 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
5991 ret = hns3_set_fec_hw(hw, mode);
5995 pf->fec_mode = mode;
6000 hns3_restore_fec(struct hns3_hw *hw)
6002 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6003 struct hns3_pf *pf = &hns->pf;
6004 uint32_t mode = pf->fec_mode;
6007 ret = hns3_set_fec_hw(hw, mode);
6009 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6016 hns3_query_dev_fec_info(struct hns3_hw *hw)
6018 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6019 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6020 struct rte_eth_dev *eth_dev = hns->eth_dev;
6023 ret = hns3_fec_get(eth_dev, &pf->fec_mode);
6025 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6030 static const struct eth_dev_ops hns3_eth_dev_ops = {
6031 .dev_configure = hns3_dev_configure,
6032 .dev_start = hns3_dev_start,
6033 .dev_stop = hns3_dev_stop,
6034 .dev_close = hns3_dev_close,
6035 .promiscuous_enable = hns3_dev_promiscuous_enable,
6036 .promiscuous_disable = hns3_dev_promiscuous_disable,
6037 .allmulticast_enable = hns3_dev_allmulticast_enable,
6038 .allmulticast_disable = hns3_dev_allmulticast_disable,
6039 .mtu_set = hns3_dev_mtu_set,
6040 .stats_get = hns3_stats_get,
6041 .stats_reset = hns3_stats_reset,
6042 .xstats_get = hns3_dev_xstats_get,
6043 .xstats_get_names = hns3_dev_xstats_get_names,
6044 .xstats_reset = hns3_dev_xstats_reset,
6045 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
6046 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6047 .dev_infos_get = hns3_dev_infos_get,
6048 .fw_version_get = hns3_fw_version_get,
6049 .rx_queue_setup = hns3_rx_queue_setup,
6050 .tx_queue_setup = hns3_tx_queue_setup,
6051 .rx_queue_release = hns3_dev_rx_queue_release,
6052 .tx_queue_release = hns3_dev_tx_queue_release,
6053 .rx_queue_start = hns3_dev_rx_queue_start,
6054 .rx_queue_stop = hns3_dev_rx_queue_stop,
6055 .tx_queue_start = hns3_dev_tx_queue_start,
6056 .tx_queue_stop = hns3_dev_tx_queue_stop,
6057 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
6058 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
6059 .rxq_info_get = hns3_rxq_info_get,
6060 .txq_info_get = hns3_txq_info_get,
6061 .rx_burst_mode_get = hns3_rx_burst_mode_get,
6062 .tx_burst_mode_get = hns3_tx_burst_mode_get,
6063 .flow_ctrl_get = hns3_flow_ctrl_get,
6064 .flow_ctrl_set = hns3_flow_ctrl_set,
6065 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6066 .mac_addr_add = hns3_add_mac_addr,
6067 .mac_addr_remove = hns3_remove_mac_addr,
6068 .mac_addr_set = hns3_set_default_mac_addr,
6069 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
6070 .link_update = hns3_dev_link_update,
6071 .rss_hash_update = hns3_dev_rss_hash_update,
6072 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
6073 .reta_update = hns3_dev_rss_reta_update,
6074 .reta_query = hns3_dev_rss_reta_query,
6075 .filter_ctrl = hns3_dev_filter_ctrl,
6076 .vlan_filter_set = hns3_vlan_filter_set,
6077 .vlan_tpid_set = hns3_vlan_tpid_set,
6078 .vlan_offload_set = hns3_vlan_offload_set,
6079 .vlan_pvid_set = hns3_vlan_pvid_set,
6080 .get_reg = hns3_get_regs,
6081 .get_dcb_info = hns3_get_dcb_info,
6082 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6083 .fec_get_capability = hns3_fec_get_capability,
6084 .fec_get = hns3_fec_get,
6085 .fec_set = hns3_fec_set,
6088 static const struct hns3_reset_ops hns3_reset_ops = {
6089 .reset_service = hns3_reset_service,
6090 .stop_service = hns3_stop_service,
6091 .prepare_reset = hns3_prepare_reset,
6092 .wait_hardware_ready = hns3_wait_hardware_ready,
6093 .reinit_dev = hns3_reinit_dev,
6094 .restore_conf = hns3_restore_conf,
6095 .start_service = hns3_start_service,
6099 hns3_dev_init(struct rte_eth_dev *eth_dev)
6101 struct hns3_adapter *hns = eth_dev->data->dev_private;
6102 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6103 struct rte_ether_addr *eth_addr;
6104 struct hns3_hw *hw = &hns->hw;
6107 PMD_INIT_FUNC_TRACE();
6109 hns->eth_dev = eth_dev;
6111 eth_dev->process_private = (struct hns3_process_private *)
6112 rte_zmalloc_socket("hns3_filter_list",
6113 sizeof(struct hns3_process_private),
6114 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6115 if (eth_dev->process_private == NULL) {
6116 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6119 /* initialize flow filter lists */
6120 hns3_filterlist_init(eth_dev);
6122 hns3_set_rxtx_function(eth_dev);
6123 eth_dev->dev_ops = &hns3_eth_dev_ops;
6124 eth_dev->rx_queue_count = hns3_rx_queue_count;
6125 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6126 ret = hns3_mp_init_secondary();
6128 PMD_INIT_LOG(ERR, "Failed to init for secondary "
6129 "process, ret = %d", ret);
6130 goto err_mp_init_secondary;
6133 hw->secondary_cnt++;
6137 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6139 ret = hns3_mp_init_primary();
6142 "Failed to init for primary process, ret = %d",
6144 goto err_mp_init_primary;
6147 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6149 hw->data = eth_dev->data;
6152 * Set default max packet size according to the mtu
6153 * default vale in DPDK frame.
6155 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6157 ret = hns3_reset_init(hw);
6159 goto err_init_reset;
6160 hw->reset.ops = &hns3_reset_ops;
6162 ret = hns3_init_pf(eth_dev);
6164 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6168 /* Allocate memory for storing MAC addresses */
6169 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6170 sizeof(struct rte_ether_addr) *
6171 HNS3_UC_MACADDR_NUM, 0);
6172 if (eth_dev->data->mac_addrs == NULL) {
6173 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6174 "to store MAC addresses",
6175 sizeof(struct rte_ether_addr) *
6176 HNS3_UC_MACADDR_NUM);
6178 goto err_rte_zmalloc;
6181 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6182 if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6183 rte_eth_random_addr(hw->mac.mac_addr);
6184 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6185 (struct rte_ether_addr *)hw->mac.mac_addr);
6186 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6187 "unicast address, using random MAC address %s",
6190 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6191 ð_dev->data->mac_addrs[0]);
6193 hw->adapter_state = HNS3_NIC_INITIALIZED;
6195 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
6196 hns3_err(hw, "Reschedule reset service after dev_init");
6197 hns3_schedule_reset(hns);
6199 /* IMP will wait ready flag before reset */
6200 hns3_notify_reset_ready(hw, false);
6203 hns3_info(hw, "hns3 dev initialization successful!");
6207 hns3_uninit_pf(eth_dev);
6210 rte_free(hw->reset.wait_data);
6213 hns3_mp_uninit_primary();
6215 err_mp_init_primary:
6216 err_mp_init_secondary:
6217 eth_dev->dev_ops = NULL;
6218 eth_dev->rx_pkt_burst = NULL;
6219 eth_dev->tx_pkt_burst = NULL;
6220 eth_dev->tx_pkt_prepare = NULL;
6221 rte_free(eth_dev->process_private);
6222 eth_dev->process_private = NULL;
6227 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6229 struct hns3_adapter *hns = eth_dev->data->dev_private;
6230 struct hns3_hw *hw = &hns->hw;
6232 PMD_INIT_FUNC_TRACE();
6234 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6237 if (hw->adapter_state < HNS3_NIC_CLOSING)
6238 hns3_dev_close(eth_dev);
6240 hw->adapter_state = HNS3_NIC_REMOVED;
6245 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6246 struct rte_pci_device *pci_dev)
6248 return rte_eth_dev_pci_generic_probe(pci_dev,
6249 sizeof(struct hns3_adapter),
6254 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6256 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6259 static const struct rte_pci_id pci_id_hns3_map[] = {
6260 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6261 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6262 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6263 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6264 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6265 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6266 { .vendor_id = 0, }, /* sentinel */
6269 static struct rte_pci_driver rte_hns3_pmd = {
6270 .id_table = pci_id_hns3_map,
6271 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6272 .probe = eth_hns3_pci_probe,
6273 .remove = eth_hns3_pci_remove,
6276 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6277 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6278 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6279 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6280 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);