drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_INVLID_PVID                0xFFFF
  39
  40 #define HNS3_FILTER_TYPE_VF             0
  41 #define HNS3_FILTER_TYPE_PORT           1
  42 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  43 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  44 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  45 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  46 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  47 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  48                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  49 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  51
  52 /* Reset related Registers */
  53 #define HNS3_GLOBAL_RESET_BIT           0
  54 #define HNS3_CORE_RESET_BIT             1
  55 #define HNS3_IMP_RESET_BIT              2
  56 #define HNS3_FUN_RST_ING_B              0
  57
  58 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  59
  60 #define HNS3_RESET_WAIT_MS      100
  61 #define HNS3_RESET_WAIT_CNT     200
  62
  63 enum hns3_evt_cause {
  64         HNS3_VECTOR0_EVENT_RST,
  65         HNS3_VECTOR0_EVENT_MBX,
  66         HNS3_VECTOR0_EVENT_ERR,
  67         HNS3_VECTOR0_EVENT_OTHER,
  68 };
  69
  70 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  71                                                  uint64_t *levels);
  72 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  73 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  74                                     int on);
  75 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  76
  77 static int hns3_add_mc_addr(struct hns3_hw *hw,
  78                             struct rte_ether_addr *mac_addr);
  79 static int hns3_remove_mc_addr(struct hns3_hw *hw,
  80                             struct rte_ether_addr *mac_addr);
  81
  82 static void
  83 hns3_pf_disable_irq0(struct hns3_hw *hw)
  84 {
  85         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  86 }
  87
  88 static void
  89 hns3_pf_enable_irq0(struct hns3_hw *hw)
  90 {
  91         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  92 }
  93
  94 static enum hns3_evt_cause
  95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  96 {
  97         struct hns3_hw *hw = &hns->hw;
  98         uint32_t vector0_int_stats;
  99         uint32_t cmdq_src_val;
 100         uint32_t val;
 101         enum hns3_evt_cause ret;
 102
 103         /* fetch the events from their corresponding regs */
 104         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 105         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 106
 107         /*
 108          * Assumption: If by any chance reset and mailbox events are reported
 109          * together then we will only process reset event and defer the
 110          * processing of the mailbox events. Since, we would have not cleared
 111          * RX CMDQ event this time we would receive again another interrupt
 112          * from H/W just for the mailbox.
 113          */
 114         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 115                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 116                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 117                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 118                 if (clearval) {
 119                         hw->reset.stats.imp_cnt++;
 120                         hns3_warn(hw, "IMP reset detected, clear reset status");
 121                 } else {
 122                         hns3_schedule_delayed_reset(hns);
 123                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 124                 }
 125
 126                 ret = HNS3_VECTOR0_EVENT_RST;
 127                 goto out;
 128         }
 129
 130         /* Global reset */
 131         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 132                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 133                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 134                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 135                 if (clearval) {
 136                         hw->reset.stats.global_cnt++;
 137                         hns3_warn(hw, "Global reset detected, clear reset status");
 138                 } else {
 139                         hns3_schedule_delayed_reset(hns);
 140                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 141                 }
 142
 143                 ret = HNS3_VECTOR0_EVENT_RST;
 144                 goto out;
 145         }
 146
 147         /* check for vector0 msix event source */
 148         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 149                 val = vector0_int_stats;
 150                 ret = HNS3_VECTOR0_EVENT_ERR;
 151                 goto out;
 152         }
 153
 154         /* check for vector0 mailbox(=CMDQ RX) event source */
 155         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 156                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 157                 val = cmdq_src_val;
 158                 ret = HNS3_VECTOR0_EVENT_MBX;
 159                 goto out;
 160         }
 161
 162         if (clearval && (vector0_int_stats || cmdq_src_val))
 163                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 164                           vector0_int_stats, cmdq_src_val);
 165         val = vector0_int_stats;
 166         ret = HNS3_VECTOR0_EVENT_OTHER;
 167 out:
 168
 169         if (clearval)
 170                 *clearval = val;
 171         return ret;
 172 }
 173
 174 static void
 175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 176 {
 177         if (event_type == HNS3_VECTOR0_EVENT_RST)
 178                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 179         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 180                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 181 }
 182
 183 static void
 184 hns3_clear_all_event_cause(struct hns3_hw *hw)
 185 {
 186         uint32_t vector0_int_stats;
 187         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 188
 189         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 190                 hns3_warn(hw, "Probe during IMP reset interrupt");
 191
 192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 193                 hns3_warn(hw, "Probe during Global reset interrupt");
 194
 195         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 196                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 197                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 198                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 199         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 200 }
 201
 202 static void
 203 hns3_interrupt_handler(void *param)
 204 {
 205         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 206         struct hns3_adapter *hns = dev->data->dev_private;
 207         struct hns3_hw *hw = &hns->hw;
 208         enum hns3_evt_cause event_cause;
 209         uint32_t clearval = 0;
 210
 211         /* Disable interrupt */
 212         hns3_pf_disable_irq0(hw);
 213
 214         event_cause = hns3_check_event_cause(hns, &clearval);
 215
 216         /* vector 0 interrupt is shared with reset and mailbox source events. */
 217         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 218                 hns3_handle_msix_error(hns, &hw->reset.request);
 219                 hns3_schedule_reset(hns);
 220         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 221                 hns3_schedule_reset(hns);
 222         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 223                 hns3_dev_handle_mbx_msg(hw);
 224         else
 225                 hns3_err(hw, "Received unknown event");
 226
 227         hns3_clear_event_cause(hw, event_cause, clearval);
 228         /* Enable interrupt if it is not cause by reset */
 229         hns3_pf_enable_irq0(hw);
 230 }
 231
 232 static int
 233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 234 {
 235 #define HNS3_VLAN_ID_OFFSET_STEP        160
 236 #define HNS3_VLAN_BYTE_SIZE             8
 237         struct hns3_vlan_filter_pf_cfg_cmd *req;
 238         struct hns3_hw *hw = &hns->hw;
 239         uint8_t vlan_offset_byte_val;
 240         struct hns3_cmd_desc desc;
 241         uint8_t vlan_offset_byte;
 242         uint8_t vlan_offset_base;
 243         int ret;
 244
 245         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 246
 247         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 248         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 249                            HNS3_VLAN_BYTE_SIZE;
 250         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 251
 252         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 253         req->vlan_offset = vlan_offset_base;
 254         req->vlan_cfg = on ? 0 : 1;
 255         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 256
 257         ret = hns3_cmd_send(hw, &desc, 1);
 258         if (ret)
 259                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 260                          vlan_id, ret);
 261
 262         return ret;
 263 }
 264
 265 static void
 266 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 267 {
 268         struct hns3_user_vlan_table *vlan_entry;
 269         struct hns3_pf *pf = &hns->pf;
 270
 271         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 272                 if (vlan_entry->vlan_id == vlan_id) {
 273                         if (vlan_entry->hd_tbl_status)
 274                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 275                         LIST_REMOVE(vlan_entry, next);
 276                         rte_free(vlan_entry);
 277                         break;
 278                 }
 279         }
 280 }
 281
 282 static void
 283 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 284                         bool writen_to_tbl)
 285 {
 286         struct hns3_user_vlan_table *vlan_entry;
 287         struct hns3_hw *hw = &hns->hw;
 288         struct hns3_pf *pf = &hns->pf;
 289
 290         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 291                 if (vlan_entry->vlan_id == vlan_id)
 292                         return;
 293         }
 294
 295         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 296         if (vlan_entry == NULL) {
 297                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 298                 return;
 299         }
 300
 301         vlan_entry->hd_tbl_status = writen_to_tbl;
 302         vlan_entry->vlan_id = vlan_id;
 303
 304         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 305 }
 306
 307 static int
 308 hns3_restore_vlan_table(struct hns3_adapter *hns)
 309 {
 310         struct hns3_user_vlan_table *vlan_entry;
 311         struct hns3_hw *hw = &hns->hw;
 312         struct hns3_pf *pf = &hns->pf;
 313         uint16_t vlan_id;
 314         int ret = 0;
 315
 316         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 317                 return hns3_vlan_pvid_configure(hns,
 318                                                 hw->port_base_vlan_cfg.pvid, 1);
 319
 320         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 321                 if (vlan_entry->hd_tbl_status) {
 322                         vlan_id = vlan_entry->vlan_id;
 323                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 324                         if (ret)
 325                                 break;
 326                 }
 327         }
 328
 329         return ret;
 330 }
 331
 332 static int
 333 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 334 {
 335         struct hns3_hw *hw = &hns->hw;
 336         bool writen_to_tbl = false;
 337         int ret = 0;
 338
 339         /*
 340          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 341          * for normal packet, deleting vlan id 0 is not allowed.
 342          */
 343         if (on == 0 && vlan_id == 0)
 344                 return 0;
 345
 346         /*
 347          * When port base vlan enabled, we use port base vlan as the vlan
 348          * filter condition. In this case, we don't update vlan filter table
 349          * when user add new vlan or remove exist vlan, just update the
 350          * vlan list. The vlan id in vlan list will be writen in vlan filter
 351          * table until port base vlan disabled
 352          */
 353         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 354                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 355                 writen_to_tbl = true;
 356         }
 357
 358         if (ret == 0 && vlan_id) {
 359                 if (on)
 360                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 361                 else
 362                         hns3_rm_dev_vlan_table(hns, vlan_id);
 363         }
 364         return ret;
 365 }
 366
 367 static int
 368 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 369 {
 370         struct hns3_adapter *hns = dev->data->dev_private;
 371         struct hns3_hw *hw = &hns->hw;
 372         int ret;
 373
 374         rte_spinlock_lock(&hw->lock);
 375         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 376         rte_spinlock_unlock(&hw->lock);
 377         return ret;
 378 }
 379
 380 static int
 381 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 382                          uint16_t tpid)
 383 {
 384         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 385         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 386         struct hns3_hw *hw = &hns->hw;
 387         struct hns3_cmd_desc desc;
 388         int ret;
 389
 390         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 391              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 392                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 393                 return -EINVAL;
 394         }
 395
 396         if (tpid != RTE_ETHER_TYPE_VLAN) {
 397                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 398                 return -EINVAL;
 399         }
 400
 401         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 402         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 403
 404         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 405                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 406                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 407         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 408                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 409                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 411                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 412         }
 413
 414         ret = hns3_cmd_send(hw, &desc, 1);
 415         if (ret) {
 416                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 417                          ret);
 418                 return ret;
 419         }
 420
 421         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 422
 423         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 424         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 425         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 426
 427         ret = hns3_cmd_send(hw, &desc, 1);
 428         if (ret)
 429                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 430                          ret);
 431         return ret;
 432 }
 433
 434 static int
 435 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 436                    uint16_t tpid)
 437 {
 438         struct hns3_adapter *hns = dev->data->dev_private;
 439         struct hns3_hw *hw = &hns->hw;
 440         int ret;
 441
 442         rte_spinlock_lock(&hw->lock);
 443         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 444         rte_spinlock_unlock(&hw->lock);
 445         return ret;
 446 }
 447
 448 static int
 449 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 450                              struct hns3_rx_vtag_cfg *vcfg)
 451 {
 452         struct hns3_vport_vtag_rx_cfg_cmd *req;
 453         struct hns3_hw *hw = &hns->hw;
 454         struct hns3_cmd_desc desc;
 455         uint16_t vport_id;
 456         uint8_t bitmap;
 457         int ret;
 458
 459         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 460
 461         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 462         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 463                      vcfg->strip_tag1_en ? 1 : 0);
 464         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 465                      vcfg->strip_tag2_en ? 1 : 0);
 466         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 467                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 468         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 469                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 470
 471         /*
 472          * In current version VF is not supported when PF is driven by DPDK
 473          * driver, just need to configure parameters for PF vport.
 474          */
 475         vport_id = HNS3_PF_FUNC_ID;
 476         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 477         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 478         req->vf_bitmap[req->vf_offset] = bitmap;
 479
 480         ret = hns3_cmd_send(hw, &desc, 1);
 481         if (ret)
 482                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 483         return ret;
 484 }
 485
 486 static void
 487 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 488                            struct hns3_rx_vtag_cfg *vcfg)
 489 {
 490         struct hns3_pf *pf = &hns->pf;
 491         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 492 }
 493
 494 static void
 495 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 496                            struct hns3_tx_vtag_cfg *vcfg)
 497 {
 498         struct hns3_pf *pf = &hns->pf;
 499         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 500 }
 501
 502 static int
 503 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 504 {
 505         struct hns3_rx_vtag_cfg rxvlan_cfg;
 506         struct hns3_hw *hw = &hns->hw;
 507         int ret;
 508
 509         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 510                 rxvlan_cfg.strip_tag1_en = false;
 511                 rxvlan_cfg.strip_tag2_en = enable;
 512         } else {
 513                 rxvlan_cfg.strip_tag1_en = enable;
 514                 rxvlan_cfg.strip_tag2_en = true;
 515         }
 516
 517         rxvlan_cfg.vlan1_vlan_prionly = false;
 518         rxvlan_cfg.vlan2_vlan_prionly = false;
 519         rxvlan_cfg.rx_vlan_offload_en = enable;
 520
 521         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 522         if (ret) {
 523                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 524                 return ret;
 525         }
 526
 527         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 528
 529         return ret;
 530 }
 531
 532 static int
 533 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 534                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 535 {
 536         struct hns3_vlan_filter_ctrl_cmd *req;
 537         struct hns3_cmd_desc desc;
 538         int ret;
 539
 540         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 541
 542         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 543         req->vlan_type = vlan_type;
 544         req->vlan_fe = filter_en ? fe_type : 0;
 545         req->vf_id = vf_id;
 546
 547         ret = hns3_cmd_send(hw, &desc, 1);
 548         if (ret)
 549                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 550
 551         return ret;
 552 }
 553
 554 static int
 555 hns3_vlan_filter_init(struct hns3_adapter *hns)
 556 {
 557         struct hns3_hw *hw = &hns->hw;
 558         int ret;
 559
 560         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 561                                         HNS3_FILTER_FE_EGRESS, false,
 562                                         HNS3_PF_FUNC_ID);
 563         if (ret) {
 564                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 565                 return ret;
 566         }
 567
 568         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 569                                         HNS3_FILTER_FE_INGRESS, false,
 570                                         HNS3_PF_FUNC_ID);
 571         if (ret)
 572                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 573
 574         return ret;
 575 }
 576
 577 static int
 578 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 579 {
 580         struct hns3_hw *hw = &hns->hw;
 581         int ret;
 582
 583         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 584                                         HNS3_FILTER_FE_INGRESS, enable,
 585                                         HNS3_PF_FUNC_ID);
 586         if (ret)
 587                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 588                          enable ? "enable" : "disable", ret);
 589
 590         return ret;
 591 }
 592
 593 static int
 594 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 595 {
 596         struct hns3_adapter *hns = dev->data->dev_private;
 597         struct hns3_hw *hw = &hns->hw;
 598         struct rte_eth_rxmode *rxmode;
 599         unsigned int tmp_mask;
 600         bool enable;
 601         int ret = 0;
 602
 603         rte_spinlock_lock(&hw->lock);
 604         rxmode = &dev->data->dev_conf.rxmode;
 605         tmp_mask = (unsigned int)mask;
 606         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 607                 /* ignore vlan filter configuration during promiscuous mode */
 608                 if (!dev->data->promiscuous) {
 609                         /* Enable or disable VLAN filter */
 610                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 611                                  true : false;
 612
 613                         ret = hns3_enable_vlan_filter(hns, enable);
 614                         if (ret) {
 615                                 rte_spinlock_unlock(&hw->lock);
 616                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 617                                          enable ? "enable" : "disable", ret);
 618                                 return ret;
 619                         }
 620                 }
 621         }
 622
 623         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 624                 /* Enable or disable VLAN stripping */
 625                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 626                     true : false;
 627
 628                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 629                 if (ret) {
 630                         rte_spinlock_unlock(&hw->lock);
 631                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 632                                  enable ? "enable" : "disable", ret);
 633                         return ret;
 634                 }
 635         }
 636
 637         rte_spinlock_unlock(&hw->lock);
 638
 639         return ret;
 640 }
 641
 642 static int
 643 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 644                              struct hns3_tx_vtag_cfg *vcfg)
 645 {
 646         struct hns3_vport_vtag_tx_cfg_cmd *req;
 647         struct hns3_cmd_desc desc;
 648         struct hns3_hw *hw = &hns->hw;
 649         uint16_t vport_id;
 650         uint8_t bitmap;
 651         int ret;
 652
 653         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 654
 655         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 656         req->def_vlan_tag1 = vcfg->default_tag1;
 657         req->def_vlan_tag2 = vcfg->default_tag2;
 658         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 659                      vcfg->accept_tag1 ? 1 : 0);
 660         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 661                      vcfg->accept_untag1 ? 1 : 0);
 662         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 663                      vcfg->accept_tag2 ? 1 : 0);
 664         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 665                      vcfg->accept_untag2 ? 1 : 0);
 666         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 667                      vcfg->insert_tag1_en ? 1 : 0);
 668         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 669                      vcfg->insert_tag2_en ? 1 : 0);
 670         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 671
 672         /*
 673          * In current version VF is not supported when PF is driven by DPDK
 674          * driver, just need to configure parameters for PF vport.
 675          */
 676         vport_id = HNS3_PF_FUNC_ID;
 677         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 678         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 679         req->vf_bitmap[req->vf_offset] = bitmap;
 680
 681         ret = hns3_cmd_send(hw, &desc, 1);
 682         if (ret)
 683                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 684
 685         return ret;
 686 }
 687
 688 static int
 689 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 690                      uint16_t pvid)
 691 {
 692         struct hns3_hw *hw = &hns->hw;
 693         struct hns3_tx_vtag_cfg txvlan_cfg;
 694         int ret;
 695
 696         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 697                 txvlan_cfg.accept_tag1 = true;
 698                 txvlan_cfg.insert_tag1_en = false;
 699                 txvlan_cfg.default_tag1 = 0;
 700         } else {
 701                 txvlan_cfg.accept_tag1 = false;
 702                 txvlan_cfg.insert_tag1_en = true;
 703                 txvlan_cfg.default_tag1 = pvid;
 704         }
 705
 706         txvlan_cfg.accept_untag1 = true;
 707         txvlan_cfg.accept_tag2 = true;
 708         txvlan_cfg.accept_untag2 = true;
 709         txvlan_cfg.insert_tag2_en = false;
 710         txvlan_cfg.default_tag2 = 0;
 711
 712         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 713         if (ret) {
 714                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 715                          ret);
 716                 return ret;
 717         }
 718
 719         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 720         return ret;
 721 }
 722
 723 static void
 724 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 725 {
 726         struct hns3_hw *hw = &hns->hw;
 727
 728         hw->port_base_vlan_cfg.state = on ?
 729             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 730
 731         hw->port_base_vlan_cfg.pvid = pvid;
 732 }
 733
 734 static void
 735 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 736 {
 737         struct hns3_user_vlan_table *vlan_entry;
 738         struct hns3_pf *pf = &hns->pf;
 739
 740         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 741                 if (vlan_entry->hd_tbl_status)
 742                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 743
 744                 vlan_entry->hd_tbl_status = false;
 745         }
 746
 747         if (is_del_list) {
 748                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 749                 while (vlan_entry) {
 750                         LIST_REMOVE(vlan_entry, next);
 751                         rte_free(vlan_entry);
 752                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 753                 }
 754         }
 755 }
 756
 757 static void
 758 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 759 {
 760         struct hns3_user_vlan_table *vlan_entry;
 761         struct hns3_pf *pf = &hns->pf;
 762
 763         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 764                 if (!vlan_entry->hd_tbl_status)
 765                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 766
 767                 vlan_entry->hd_tbl_status = true;
 768         }
 769 }
 770
 771 static void
 772 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 773 {
 774         struct hns3_hw *hw = &hns->hw;
 775         int ret;
 776
 777         hns3_rm_all_vlan_table(hns, true);
 778         if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 779                 ret = hns3_set_port_vlan_filter(hns,
 780                                                 hw->port_base_vlan_cfg.pvid, 0);
 781                 if (ret) {
 782                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 783                                  ret);
 784                         return;
 785                 }
 786         }
 787 }
 788
 789 static int
 790 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 791                                 uint16_t port_base_vlan_state,
 792                                 uint16_t new_pvid, uint16_t old_pvid)
 793 {
 794         struct hns3_hw *hw = &hns->hw;
 795         int ret = 0;
 796
 797         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 798                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 799                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 800                         if (ret) {
 801                                 hns3_err(hw,
 802                                          "Failed to clear clear old pvid filter, ret =%d",
 803                                          ret);
 804                                 return ret;
 805                         }
 806                 }
 807
 808                 hns3_rm_all_vlan_table(hns, false);
 809                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 810         }
 811
 812         if (new_pvid != 0) {
 813                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 814                 if (ret) {
 815                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 816                                  ret);
 817                         return ret;
 818                 }
 819         }
 820
 821         if (new_pvid == hw->port_base_vlan_cfg.pvid)
 822                 hns3_add_all_vlan_table(hns);
 823
 824         return ret;
 825 }
 826
 827 static int
 828 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 829 {
 830         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 831         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 832         bool rx_strip_en;
 833         int ret;
 834
 835         rx_strip_en = old_cfg->rx_vlan_offload_en ? true : false;
 836         if (on) {
 837                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 838                 rx_vlan_cfg.strip_tag2_en = true;
 839         } else {
 840                 rx_vlan_cfg.strip_tag1_en = false;
 841                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 842         }
 843         rx_vlan_cfg.vlan1_vlan_prionly = false;
 844         rx_vlan_cfg.vlan2_vlan_prionly = false;
 845         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 846
 847         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 848         if (ret)
 849                 return ret;
 850
 851         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 852         return ret;
 853 }
 854
 855 static int
 856 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 857 {
 858         struct hns3_hw *hw = &hns->hw;
 859         uint16_t port_base_vlan_state;
 860         uint16_t old_pvid;
 861         int ret;
 862
 863         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 864                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 865                         hns3_warn(hw, "Invalid operation! As current pvid set "
 866                                   "is %u, disable pvid %u is invalid",
 867                                   hw->port_base_vlan_cfg.pvid, pvid);
 868                 return 0;
 869         }
 870
 871         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 872                                     HNS3_PORT_BASE_VLAN_DISABLE;
 873         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 874         if (ret) {
 875                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 876                          ret);
 877                 return ret;
 878         }
 879
 880         ret = hns3_en_pvid_strip(hns, on);
 881         if (ret) {
 882                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 883                          "ret = %d", ret);
 884                 return ret;
 885         }
 886
 887         if (pvid == HNS3_INVLID_PVID)
 888                 goto out;
 889         old_pvid = hw->port_base_vlan_cfg.pvid;
 890         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 891                                               old_pvid);
 892         if (ret) {
 893                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 894                          ret);
 895                 return ret;
 896         }
 897
 898 out:
 899         hns3_store_port_base_vlan_info(hns, pvid, on);
 900         return ret;
 901 }
 902
 903 static int
 904 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 905 {
 906         struct hns3_adapter *hns = dev->data->dev_private;
 907         struct hns3_hw *hw = &hns->hw;
 908         bool pvid_en_state_change;
 909         uint16_t pvid_state;
 910         int ret;
 911
 912         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 913                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 914                          RTE_ETHER_MAX_VLAN_ID);
 915                 return -EINVAL;
 916         }
 917
 918         /*
 919          * If PVID configuration state change, should refresh the PVID
 920          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
 921          */
 922         pvid_state = hw->port_base_vlan_cfg.state;
 923         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
 924             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
 925                 pvid_en_state_change = false;
 926         else
 927                 pvid_en_state_change = true;
 928
 929         rte_spinlock_lock(&hw->lock);
 930         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 931         rte_spinlock_unlock(&hw->lock);
 932         if (ret)
 933                 return ret;
 934
 935         if (pvid_en_state_change)
 936                 hns3_update_all_queues_pvid_state(hw);
 937
 938         return 0;
 939 }
 940
 941 static void
 942 init_port_base_vlan_info(struct hns3_hw *hw)
 943 {
 944         hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 945         hw->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 946 }
 947
 948 static int
 949 hns3_default_vlan_config(struct hns3_adapter *hns)
 950 {
 951         struct hns3_hw *hw = &hns->hw;
 952         int ret;
 953
 954         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 955         if (ret)
 956                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 957         return ret;
 958 }
 959
 960 static int
 961 hns3_init_vlan_config(struct hns3_adapter *hns)
 962 {
 963         struct hns3_hw *hw = &hns->hw;
 964         int ret;
 965
 966         /*
 967          * This function can be called in the initialization and reset process,
 968          * when in reset process, it means that hardware had been reseted
 969          * successfully and we need to restore the hardware configuration to
 970          * ensure that the hardware configuration remains unchanged before and
 971          * after reset.
 972          */
 973         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 974                 init_port_base_vlan_info(hw);
 975
 976         ret = hns3_vlan_filter_init(hns);
 977         if (ret) {
 978                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 979                 return ret;
 980         }
 981
 982         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 983                                        RTE_ETHER_TYPE_VLAN);
 984         if (ret) {
 985                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 986                 return ret;
 987         }
 988
 989         /*
 990          * When in the reinit dev stage of the reset process, the following
 991          * vlan-related configurations may differ from those at initialization,
 992          * we will restore configurations to hardware in hns3_restore_vlan_table
 993          * and hns3_restore_vlan_conf later.
 994          */
 995         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 996                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 997                 if (ret) {
 998                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 999                         return ret;
1000                 }
1001
1002                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1003                 if (ret) {
1004                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1005                                  ret);
1006                         return ret;
1007                 }
1008         }
1009
1010         return hns3_default_vlan_config(hns);
1011 }
1012
1013 static int
1014 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1015 {
1016         struct hns3_pf *pf = &hns->pf;
1017         struct hns3_hw *hw = &hns->hw;
1018         uint64_t offloads;
1019         bool enable;
1020         int ret;
1021
1022         if (!hw->data->promiscuous) {
1023                 /* restore vlan filter states */
1024                 offloads = hw->data->dev_conf.rxmode.offloads;
1025                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1026                 ret = hns3_enable_vlan_filter(hns, enable);
1027                 if (ret) {
1028                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1029                                  "ret = %d", ret);
1030                         return ret;
1031                 }
1032         }
1033
1034         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1035         if (ret) {
1036                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1037                 return ret;
1038         }
1039
1040         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1041         if (ret)
1042                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1043
1044         return ret;
1045 }
1046
1047 static int
1048 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1049 {
1050         struct hns3_adapter *hns = dev->data->dev_private;
1051         struct rte_eth_dev_data *data = dev->data;
1052         struct rte_eth_txmode *txmode;
1053         struct hns3_hw *hw = &hns->hw;
1054         int mask;
1055         int ret;
1056
1057         txmode = &data->dev_conf.txmode;
1058         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1059                 hns3_warn(hw,
1060                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1061                           "configuration is not supported! Ignore these two "
1062                           "parameters: hw_vlan_reject_tagged(%d), "
1063                           "hw_vlan_reject_untagged(%d)",
1064                           txmode->hw_vlan_reject_tagged,
1065                           txmode->hw_vlan_reject_untagged);
1066
1067         /* Apply vlan offload setting */
1068         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1069         ret = hns3_vlan_offload_set(dev, mask);
1070         if (ret) {
1071                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1072                          ret);
1073                 return ret;
1074         }
1075
1076         /*
1077          * If pvid config is not set in rte_eth_conf, driver needn't to set
1078          * VLAN pvid related configuration to hardware.
1079          */
1080         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1081                 return 0;
1082
1083         /* Apply pvid setting */
1084         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1085                                  txmode->hw_vlan_insert_pvid);
1086         if (ret)
1087                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1088                          txmode->pvid, ret);
1089
1090         return ret;
1091 }
1092
1093 static int
1094 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1095                 unsigned int tso_mss_max)
1096 {
1097         struct hns3_cfg_tso_status_cmd *req;
1098         struct hns3_cmd_desc desc;
1099         uint16_t tso_mss;
1100
1101         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1102
1103         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1104
1105         tso_mss = 0;
1106         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1107                        tso_mss_min);
1108         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1109
1110         tso_mss = 0;
1111         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1112                        tso_mss_max);
1113         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1114
1115         return hns3_cmd_send(hw, &desc, 1);
1116 }
1117
1118 static int
1119 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1120                    uint16_t *allocated_size, bool is_alloc)
1121 {
1122         struct hns3_umv_spc_alc_cmd *req;
1123         struct hns3_cmd_desc desc;
1124         int ret;
1125
1126         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1127         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1128         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1129         req->space_size = rte_cpu_to_le_32(space_size);
1130
1131         ret = hns3_cmd_send(hw, &desc, 1);
1132         if (ret) {
1133                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1134                              is_alloc ? "allocate" : "free", ret);
1135                 return ret;
1136         }
1137
1138         if (is_alloc && allocated_size)
1139                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1140
1141         return 0;
1142 }
1143
1144 static int
1145 hns3_init_umv_space(struct hns3_hw *hw)
1146 {
1147         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1148         struct hns3_pf *pf = &hns->pf;
1149         uint16_t allocated_size = 0;
1150         int ret;
1151
1152         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1153                                  true);
1154         if (ret)
1155                 return ret;
1156
1157         if (allocated_size < pf->wanted_umv_size)
1158                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1159                              pf->wanted_umv_size, allocated_size);
1160
1161         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1162                                                 pf->wanted_umv_size;
1163         pf->used_umv_size = 0;
1164         return 0;
1165 }
1166
1167 static int
1168 hns3_uninit_umv_space(struct hns3_hw *hw)
1169 {
1170         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1171         struct hns3_pf *pf = &hns->pf;
1172         int ret;
1173
1174         if (pf->max_umv_size == 0)
1175                 return 0;
1176
1177         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1178         if (ret)
1179                 return ret;
1180
1181         pf->max_umv_size = 0;
1182
1183         return 0;
1184 }
1185
1186 static bool
1187 hns3_is_umv_space_full(struct hns3_hw *hw)
1188 {
1189         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1190         struct hns3_pf *pf = &hns->pf;
1191         bool is_full;
1192
1193         is_full = (pf->used_umv_size >= pf->max_umv_size);
1194
1195         return is_full;
1196 }
1197
1198 static void
1199 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1200 {
1201         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1202         struct hns3_pf *pf = &hns->pf;
1203
1204         if (is_free) {
1205                 if (pf->used_umv_size > 0)
1206                         pf->used_umv_size--;
1207         } else
1208                 pf->used_umv_size++;
1209 }
1210
1211 static void
1212 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1213                       const uint8_t *addr, bool is_mc)
1214 {
1215         const unsigned char *mac_addr = addr;
1216         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1217                             ((uint32_t)mac_addr[2] << 16) |
1218                             ((uint32_t)mac_addr[1] << 8) |
1219                             (uint32_t)mac_addr[0];
1220         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1221
1222         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1223         if (is_mc) {
1224                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1225                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1226                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1227         }
1228
1229         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1230         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1231 }
1232
1233 static int
1234 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1235                              uint8_t resp_code,
1236                              enum hns3_mac_vlan_tbl_opcode op)
1237 {
1238         if (cmdq_resp) {
1239                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1240                          cmdq_resp);
1241                 return -EIO;
1242         }
1243
1244         if (op == HNS3_MAC_VLAN_ADD) {
1245                 if (resp_code == 0 || resp_code == 1) {
1246                         return 0;
1247                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1248                         hns3_err(hw, "add mac addr failed for uc_overflow");
1249                         return -ENOSPC;
1250                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1251                         hns3_err(hw, "add mac addr failed for mc_overflow");
1252                         return -ENOSPC;
1253                 }
1254
1255                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1256                          resp_code);
1257                 return -EIO;
1258         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1259                 if (resp_code == 0) {
1260                         return 0;
1261                 } else if (resp_code == 1) {
1262                         hns3_dbg(hw, "remove mac addr failed for miss");
1263                         return -ENOENT;
1264                 }
1265
1266                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1267                          resp_code);
1268                 return -EIO;
1269         } else if (op == HNS3_MAC_VLAN_LKUP) {
1270                 if (resp_code == 0) {
1271                         return 0;
1272                 } else if (resp_code == 1) {
1273                         hns3_dbg(hw, "lookup mac addr failed for miss");
1274                         return -ENOENT;
1275                 }
1276
1277                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1278                          resp_code);
1279                 return -EIO;
1280         }
1281
1282         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1283                  op);
1284
1285         return -EINVAL;
1286 }
1287
1288 static int
1289 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1290                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1291                          struct hns3_cmd_desc *desc, bool is_mc)
1292 {
1293         uint8_t resp_code;
1294         uint16_t retval;
1295         int ret;
1296
1297         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1298         if (is_mc) {
1299                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1300                 memcpy(desc[0].data, req,
1301                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1302                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1303                                           true);
1304                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1305                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1306                                           true);
1307                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1308         } else {
1309                 memcpy(desc[0].data, req,
1310                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1311                 ret = hns3_cmd_send(hw, desc, 1);
1312         }
1313         if (ret) {
1314                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1315                          ret);
1316                 return ret;
1317         }
1318         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1319         retval = rte_le_to_cpu_16(desc[0].retval);
1320
1321         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1322                                             HNS3_MAC_VLAN_LKUP);
1323 }
1324
1325 static int
1326 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1327                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1328                       struct hns3_cmd_desc *mc_desc)
1329 {
1330         uint8_t resp_code;
1331         uint16_t retval;
1332         int cfg_status;
1333         int ret;
1334
1335         if (mc_desc == NULL) {
1336                 struct hns3_cmd_desc desc;
1337
1338                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1339                 memcpy(desc.data, req,
1340                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1341                 ret = hns3_cmd_send(hw, &desc, 1);
1342                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1343                 retval = rte_le_to_cpu_16(desc.retval);
1344
1345                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1346                                                           HNS3_MAC_VLAN_ADD);
1347         } else {
1348                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1349                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1350                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1351                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1352                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1353                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1354                 memcpy(mc_desc[0].data, req,
1355                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1356                 mc_desc[0].retval = 0;
1357                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1358                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1359                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1360
1361                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1362                                                           HNS3_MAC_VLAN_ADD);
1363         }
1364
1365         if (ret) {
1366                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1367                 return ret;
1368         }
1369
1370         return cfg_status;
1371 }
1372
1373 static int
1374 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1375                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1376 {
1377         struct hns3_cmd_desc desc;
1378         uint8_t resp_code;
1379         uint16_t retval;
1380         int ret;
1381
1382         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1383
1384         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1385
1386         ret = hns3_cmd_send(hw, &desc, 1);
1387         if (ret) {
1388                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1389                 return ret;
1390         }
1391         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1392         retval = rte_le_to_cpu_16(desc.retval);
1393
1394         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1395                                             HNS3_MAC_VLAN_REMOVE);
1396 }
1397
1398 static int
1399 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1400 {
1401         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1402         struct hns3_mac_vlan_tbl_entry_cmd req;
1403         struct hns3_pf *pf = &hns->pf;
1404         struct hns3_cmd_desc desc;
1405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1406         uint16_t egress_port = 0;
1407         uint8_t vf_id;
1408         int ret;
1409
1410         /* check if mac addr is valid */
1411         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1412                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1413                                       mac_addr);
1414                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1415                          mac_str);
1416                 return -EINVAL;
1417         }
1418
1419         memset(&req, 0, sizeof(req));
1420
1421         /*
1422          * In current version VF is not supported when PF is driven by DPDK
1423          * driver, just need to configure parameters for PF vport.
1424          */
1425         vf_id = HNS3_PF_FUNC_ID;
1426         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1427                        HNS3_MAC_EPORT_VFID_S, vf_id);
1428
1429         req.egress_port = rte_cpu_to_le_16(egress_port);
1430
1431         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1432
1433         /*
1434          * Lookup the mac address in the mac_vlan table, and add
1435          * it if the entry is inexistent. Repeated unicast entry
1436          * is not allowed in the mac vlan table.
1437          */
1438         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1439         if (ret == -ENOENT) {
1440                 if (!hns3_is_umv_space_full(hw)) {
1441                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1442                         if (!ret)
1443                                 hns3_update_umv_space(hw, false);
1444                         return ret;
1445                 }
1446
1447                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1448
1449                 return -ENOSPC;
1450         }
1451
1452         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1453
1454         /* check if we just hit the duplicate */
1455         if (ret == 0) {
1456                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1457                 return 0;
1458         }
1459
1460         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1461                  mac_str);
1462
1463         return ret;
1464 }
1465
1466 static int
1467 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1468 {
1469         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1470         struct rte_ether_addr *addr;
1471         int ret;
1472         int i;
1473
1474         for (i = 0; i < hw->mc_addrs_num; i++) {
1475                 addr = &hw->mc_addrs[i];
1476                 /* Check if there are duplicate addresses */
1477                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1478                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1479                                               addr);
1480                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1481                                  "(%s) is added by the set_mc_mac_addr_list "
1482                                  "API", mac_str);
1483                         return -EINVAL;
1484                 }
1485         }
1486
1487         ret = hns3_add_mc_addr(hw, mac_addr);
1488         if (ret) {
1489                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1490                                       mac_addr);
1491                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1492                          mac_str, ret);
1493         }
1494         return ret;
1495 }
1496
1497 static int
1498 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1499 {
1500         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1501         int ret;
1502
1503         ret = hns3_remove_mc_addr(hw, mac_addr);
1504         if (ret) {
1505                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1506                                       mac_addr);
1507                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1508                          mac_str, ret);
1509         }
1510         return ret;
1511 }
1512
1513 static int
1514 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1515                   uint32_t idx, __rte_unused uint32_t pool)
1516 {
1517         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1519         int ret;
1520
1521         rte_spinlock_lock(&hw->lock);
1522
1523         /*
1524          * In hns3 network engine adding UC and MC mac address with different
1525          * commands with firmware. We need to determine whether the input
1526          * address is a UC or a MC address to call different commands.
1527          * By the way, it is recommended calling the API function named
1528          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1529          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1530          * may affect the specifications of UC mac addresses.
1531          */
1532         if (rte_is_multicast_ether_addr(mac_addr))
1533                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1534         else
1535                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1536
1537         if (ret) {
1538                 rte_spinlock_unlock(&hw->lock);
1539                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1540                                       mac_addr);
1541                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1542                          ret);
1543                 return ret;
1544         }
1545
1546         if (idx == 0)
1547                 hw->mac.default_addr_setted = true;
1548         rte_spinlock_unlock(&hw->lock);
1549
1550         return ret;
1551 }
1552
1553 static int
1554 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1555 {
1556         struct hns3_mac_vlan_tbl_entry_cmd req;
1557         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1558         int ret;
1559
1560         /* check if mac addr is valid */
1561         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1562                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1563                                       mac_addr);
1564                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1565                          mac_str);
1566                 return -EINVAL;
1567         }
1568
1569         memset(&req, 0, sizeof(req));
1570         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1571         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1572         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1573         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1574                 return 0;
1575         else if (ret == 0)
1576                 hns3_update_umv_space(hw, true);
1577
1578         return ret;
1579 }
1580
1581 static void
1582 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1583 {
1584         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585         /* index will be checked by upper level rte interface */
1586         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1587         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1588         int ret;
1589
1590         rte_spinlock_lock(&hw->lock);
1591
1592         if (rte_is_multicast_ether_addr(mac_addr))
1593                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1594         else
1595                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1596         rte_spinlock_unlock(&hw->lock);
1597         if (ret) {
1598                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1599                                       mac_addr);
1600                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1601                          ret);
1602         }
1603 }
1604
1605 static int
1606 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1607                           struct rte_ether_addr *mac_addr)
1608 {
1609         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1610         struct rte_ether_addr *oaddr;
1611         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1612         bool default_addr_setted;
1613         bool rm_succes = false;
1614         int ret, ret_val;
1615
1616         /*
1617          * It has been guaranteed that input parameter named mac_addr is valid
1618          * address in the rte layer of DPDK framework.
1619          */
1620         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1621         default_addr_setted = hw->mac.default_addr_setted;
1622         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1623                 return 0;
1624
1625         rte_spinlock_lock(&hw->lock);
1626         if (default_addr_setted) {
1627                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1628                 if (ret) {
1629                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1630                                               oaddr);
1631                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1632                                   mac_str, ret);
1633                         rm_succes = false;
1634                 } else
1635                         rm_succes = true;
1636         }
1637
1638         ret = hns3_add_uc_addr_common(hw, mac_addr);
1639         if (ret) {
1640                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1641                                       mac_addr);
1642                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1643                 goto err_add_uc_addr;
1644         }
1645
1646         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1647         if (ret) {
1648                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1649                 goto err_pause_addr_cfg;
1650         }
1651
1652         rte_ether_addr_copy(mac_addr,
1653                             (struct rte_ether_addr *)hw->mac.mac_addr);
1654         hw->mac.default_addr_setted = true;
1655         rte_spinlock_unlock(&hw->lock);
1656
1657         return 0;
1658
1659 err_pause_addr_cfg:
1660         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1661         if (ret_val) {
1662                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1663                                       mac_addr);
1664                 hns3_warn(hw,
1665                           "Failed to roll back to del setted mac addr(%s): %d",
1666                           mac_str, ret_val);
1667         }
1668
1669 err_add_uc_addr:
1670         if (rm_succes) {
1671                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1672                 if (ret_val) {
1673                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1674                                               oaddr);
1675                         hns3_warn(hw,
1676                                   "Failed to restore old uc mac addr(%s): %d",
1677                                   mac_str, ret_val);
1678                         hw->mac.default_addr_setted = false;
1679                 }
1680         }
1681         rte_spinlock_unlock(&hw->lock);
1682
1683         return ret;
1684 }
1685
1686 static int
1687 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1688 {
1689         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1690         struct hns3_hw *hw = &hns->hw;
1691         struct rte_ether_addr *addr;
1692         int err = 0;
1693         int ret;
1694         int i;
1695
1696         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1697                 addr = &hw->data->mac_addrs[i];
1698                 if (rte_is_zero_ether_addr(addr))
1699                         continue;
1700                 if (rte_is_multicast_ether_addr(addr))
1701                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1702                               hns3_add_mc_addr(hw, addr);
1703                 else
1704                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1705                               hns3_add_uc_addr_common(hw, addr);
1706
1707                 if (ret) {
1708                         err = ret;
1709                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1710                                               addr);
1711                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1712                                  "ret = %d.", del ? "remove" : "restore",
1713                                  mac_str, i, ret);
1714                 }
1715         }
1716         return err;
1717 }
1718
1719 static void
1720 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1721 {
1722 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1723         uint8_t word_num;
1724         uint8_t bit_num;
1725
1726         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1727                 word_num = vfid / 32;
1728                 bit_num = vfid % 32;
1729                 if (clr)
1730                         desc[1].data[word_num] &=
1731                             rte_cpu_to_le_32(~(1UL << bit_num));
1732                 else
1733                         desc[1].data[word_num] |=
1734                             rte_cpu_to_le_32(1UL << bit_num);
1735         } else {
1736                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1737                 bit_num = vfid % 32;
1738                 if (clr)
1739                         desc[2].data[word_num] &=
1740                             rte_cpu_to_le_32(~(1UL << bit_num));
1741                 else
1742                         desc[2].data[word_num] |=
1743                             rte_cpu_to_le_32(1UL << bit_num);
1744         }
1745 }
1746
1747 static int
1748 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1749 {
1750         struct hns3_mac_vlan_tbl_entry_cmd req;
1751         struct hns3_cmd_desc desc[3];
1752         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1753         uint8_t vf_id;
1754         int ret;
1755
1756         /* Check if mac addr is valid */
1757         if (!rte_is_multicast_ether_addr(mac_addr)) {
1758                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1759                                       mac_addr);
1760                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1761                          mac_str);
1762                 return -EINVAL;
1763         }
1764
1765         memset(&req, 0, sizeof(req));
1766         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1767         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1768         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1769         if (ret) {
1770                 /* This mac addr do not exist, add new entry for it */
1771                 memset(desc[0].data, 0, sizeof(desc[0].data));
1772                 memset(desc[1].data, 0, sizeof(desc[0].data));
1773                 memset(desc[2].data, 0, sizeof(desc[0].data));
1774         }
1775
1776         /*
1777          * In current version VF is not supported when PF is driven by DPDK
1778          * driver, just need to configure parameters for PF vport.
1779          */
1780         vf_id = HNS3_PF_FUNC_ID;
1781         hns3_update_desc_vfid(desc, vf_id, false);
1782         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1783         if (ret) {
1784                 if (ret == -ENOSPC)
1785                         hns3_err(hw, "mc mac vlan table is full");
1786                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1787                                       mac_addr);
1788                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1789         }
1790
1791         return ret;
1792 }
1793
1794 static int
1795 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1796 {
1797         struct hns3_mac_vlan_tbl_entry_cmd req;
1798         struct hns3_cmd_desc desc[3];
1799         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1800         uint8_t vf_id;
1801         int ret;
1802
1803         /* Check if mac addr is valid */
1804         if (!rte_is_multicast_ether_addr(mac_addr)) {
1805                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1806                                       mac_addr);
1807                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1808                          mac_str);
1809                 return -EINVAL;
1810         }
1811
1812         memset(&req, 0, sizeof(req));
1813         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1814         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1815         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1816         if (ret == 0) {
1817                 /*
1818                  * This mac addr exist, remove this handle's VFID for it.
1819                  * In current version VF is not supported when PF is driven by
1820                  * DPDK driver, just need to configure parameters for PF vport.
1821                  */
1822                 vf_id = HNS3_PF_FUNC_ID;
1823                 hns3_update_desc_vfid(desc, vf_id, true);
1824
1825                 /* All the vfid is zero, so need to delete this entry */
1826                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1827         } else if (ret == -ENOENT) {
1828                 /* This mac addr doesn't exist. */
1829                 return 0;
1830         }
1831
1832         if (ret) {
1833                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1834                                       mac_addr);
1835                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1836         }
1837
1838         return ret;
1839 }
1840
1841 static int
1842 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1843                            struct rte_ether_addr *mc_addr_set,
1844                            uint32_t nb_mc_addr)
1845 {
1846         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1847         struct rte_ether_addr *addr;
1848         uint32_t i;
1849         uint32_t j;
1850
1851         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1852                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1853                          "invalid. valid range: 0~%d",
1854                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1855                 return -EINVAL;
1856         }
1857
1858         /* Check if input mac addresses are valid */
1859         for (i = 0; i < nb_mc_addr; i++) {
1860                 addr = &mc_addr_set[i];
1861                 if (!rte_is_multicast_ether_addr(addr)) {
1862                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1863                                               addr);
1864                         hns3_err(hw,
1865                                  "failed to set mc mac addr, addr(%s) invalid.",
1866                                  mac_str);
1867                         return -EINVAL;
1868                 }
1869
1870                 /* Check if there are duplicate addresses */
1871                 for (j = i + 1; j < nb_mc_addr; j++) {
1872                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1873                                 rte_ether_format_addr(mac_str,
1874                                                       RTE_ETHER_ADDR_FMT_SIZE,
1875                                                       addr);
1876                                 hns3_err(hw, "failed to set mc mac addr, "
1877                                          "addrs invalid. two same addrs(%s).",
1878                                          mac_str);
1879                                 return -EINVAL;
1880                         }
1881                 }
1882
1883                 /*
1884                  * Check if there are duplicate addresses between mac_addrs
1885                  * and mc_addr_set
1886                  */
1887                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1888                         if (rte_is_same_ether_addr(addr,
1889                                                    &hw->data->mac_addrs[j])) {
1890                                 rte_ether_format_addr(mac_str,
1891                                                       RTE_ETHER_ADDR_FMT_SIZE,
1892                                                       addr);
1893                                 hns3_err(hw, "failed to set mc mac addr, "
1894                                          "addrs invalid. addrs(%s) has already "
1895                                          "configured in mac_addr add API",
1896                                          mac_str);
1897                                 return -EINVAL;
1898                         }
1899                 }
1900         }
1901
1902         return 0;
1903 }
1904
1905 static void
1906 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1907                            struct rte_ether_addr *mc_addr_set,
1908                            int mc_addr_num,
1909                            struct rte_ether_addr *reserved_addr_list,
1910                            int *reserved_addr_num,
1911                            struct rte_ether_addr *add_addr_list,
1912                            int *add_addr_num,
1913                            struct rte_ether_addr *rm_addr_list,
1914                            int *rm_addr_num)
1915 {
1916         struct rte_ether_addr *addr;
1917         int current_addr_num;
1918         int reserved_num = 0;
1919         int add_num = 0;
1920         int rm_num = 0;
1921         int num;
1922         int i;
1923         int j;
1924         bool same_addr;
1925
1926         /* Calculate the mc mac address list that should be removed */
1927         current_addr_num = hw->mc_addrs_num;
1928         for (i = 0; i < current_addr_num; i++) {
1929                 addr = &hw->mc_addrs[i];
1930                 same_addr = false;
1931                 for (j = 0; j < mc_addr_num; j++) {
1932                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1933                                 same_addr = true;
1934                                 break;
1935                         }
1936                 }
1937
1938                 if (!same_addr) {
1939                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1940                         rm_num++;
1941                 } else {
1942                         rte_ether_addr_copy(addr,
1943                                             &reserved_addr_list[reserved_num]);
1944                         reserved_num++;
1945                 }
1946         }
1947
1948         /* Calculate the mc mac address list that should be added */
1949         for (i = 0; i < mc_addr_num; i++) {
1950                 addr = &mc_addr_set[i];
1951                 same_addr = false;
1952                 for (j = 0; j < current_addr_num; j++) {
1953                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1954                                 same_addr = true;
1955                                 break;
1956                         }
1957                 }
1958
1959                 if (!same_addr) {
1960                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1961                         add_num++;
1962                 }
1963         }
1964
1965         /* Reorder the mc mac address list maintained by driver */
1966         for (i = 0; i < reserved_num; i++)
1967                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1968
1969         for (i = 0; i < rm_num; i++) {
1970                 num = reserved_num + i;
1971                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1972         }
1973
1974         *reserved_addr_num = reserved_num;
1975         *add_addr_num = add_num;
1976         *rm_addr_num = rm_num;
1977 }
1978
1979 static int
1980 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1981                           struct rte_ether_addr *mc_addr_set,
1982                           uint32_t nb_mc_addr)
1983 {
1984         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1986         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1987         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1988         struct rte_ether_addr *addr;
1989         int reserved_addr_num;
1990         int add_addr_num;
1991         int rm_addr_num;
1992         int mc_addr_num;
1993         int num;
1994         int ret;
1995         int i;
1996
1997         /* Check if input parameters are valid */
1998         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1999         if (ret)
2000                 return ret;
2001
2002         rte_spinlock_lock(&hw->lock);
2003
2004         /*
2005          * Calculate the mc mac address lists those should be removed and be
2006          * added, Reorder the mc mac address list maintained by driver.
2007          */
2008         mc_addr_num = (int)nb_mc_addr;
2009         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2010                                    reserved_addr_list, &reserved_addr_num,
2011                                    add_addr_list, &add_addr_num,
2012                                    rm_addr_list, &rm_addr_num);
2013
2014         /* Remove mc mac addresses */
2015         for (i = 0; i < rm_addr_num; i++) {
2016                 num = rm_addr_num - i - 1;
2017                 addr = &rm_addr_list[num];
2018                 ret = hns3_remove_mc_addr(hw, addr);
2019                 if (ret) {
2020                         rte_spinlock_unlock(&hw->lock);
2021                         return ret;
2022                 }
2023                 hw->mc_addrs_num--;
2024         }
2025
2026         /* Add mc mac addresses */
2027         for (i = 0; i < add_addr_num; i++) {
2028                 addr = &add_addr_list[i];
2029                 ret = hns3_add_mc_addr(hw, addr);
2030                 if (ret) {
2031                         rte_spinlock_unlock(&hw->lock);
2032                         return ret;
2033                 }
2034
2035                 num = reserved_addr_num + i;
2036                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2037                 hw->mc_addrs_num++;
2038         }
2039         rte_spinlock_unlock(&hw->lock);
2040
2041         return 0;
2042 }
2043
2044 static int
2045 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2046 {
2047         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2048         struct hns3_hw *hw = &hns->hw;
2049         struct rte_ether_addr *addr;
2050         int err = 0;
2051         int ret;
2052         int i;
2053
2054         for (i = 0; i < hw->mc_addrs_num; i++) {
2055                 addr = &hw->mc_addrs[i];
2056                 if (!rte_is_multicast_ether_addr(addr))
2057                         continue;
2058                 if (del)
2059                         ret = hns3_remove_mc_addr(hw, addr);
2060                 else
2061                         ret = hns3_add_mc_addr(hw, addr);
2062                 if (ret) {
2063                         err = ret;
2064                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2065                                               addr);
2066                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2067                                  del ? "Remove" : "Restore", mac_str, ret);
2068                 }
2069         }
2070         return err;
2071 }
2072
2073 static int
2074 hns3_check_mq_mode(struct rte_eth_dev *dev)
2075 {
2076         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2077         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2078         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2080         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2081         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2082         uint8_t num_tc;
2083         int max_tc = 0;
2084         int i;
2085
2086         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2087         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2088
2089         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2090                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2091                          "rx_mq_mode = %d", rx_mq_mode);
2092                 return -EINVAL;
2093         }
2094
2095         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2096             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2097                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2098                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2099                          rx_mq_mode, tx_mq_mode);
2100                 return -EINVAL;
2101         }
2102
2103         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2104                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2105                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2106                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2107                         return -EINVAL;
2108                 }
2109
2110                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2111                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2112                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2113                                  "nb_tcs(%d) != %d or %d in rx direction.",
2114                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2115                         return -EINVAL;
2116                 }
2117
2118                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2119                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2120                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2121                         return -EINVAL;
2122                 }
2123
2124                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2125                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2126                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2127                                          "is not equal to one in tx direction.",
2128                                          i, dcb_rx_conf->dcb_tc[i]);
2129                                 return -EINVAL;
2130                         }
2131                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2132                                 max_tc = dcb_rx_conf->dcb_tc[i];
2133                 }
2134
2135                 num_tc = max_tc + 1;
2136                 if (num_tc > dcb_rx_conf->nb_tcs) {
2137                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2138                                  num_tc, dcb_rx_conf->nb_tcs);
2139                         return -EINVAL;
2140                 }
2141         }
2142
2143         return 0;
2144 }
2145
2146 static int
2147 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2148 {
2149         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150
2151         if (!hns3_dev_dcb_supported(hw)) {
2152                 hns3_err(hw, "this port does not support dcb configurations.");
2153                 return -EOPNOTSUPP;
2154         }
2155
2156         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2157                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2158                 return -EOPNOTSUPP;
2159         }
2160
2161         /* Check multiple queue mode */
2162         return hns3_check_mq_mode(dev);
2163 }
2164
2165 static int
2166 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2167                            enum hns3_ring_type queue_type, uint16_t queue_id)
2168 {
2169         struct hns3_cmd_desc desc;
2170         struct hns3_ctrl_vector_chain_cmd *req =
2171                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2172         enum hns3_cmd_status status;
2173         enum hns3_opcode_type op;
2174         uint16_t tqp_type_and_id = 0;
2175         const char *op_str;
2176         uint16_t type;
2177         uint16_t gl;
2178
2179         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2180         hns3_cmd_setup_basic_desc(&desc, op, false);
2181         req->int_vector_id = vector_id;
2182
2183         if (queue_type == HNS3_RING_TYPE_RX)
2184                 gl = HNS3_RING_GL_RX;
2185         else
2186                 gl = HNS3_RING_GL_TX;
2187
2188         type = queue_type;
2189
2190         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2191                        type);
2192         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2193         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2194                        gl);
2195         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2196         req->int_cause_num = 1;
2197         op_str = mmap ? "Map" : "Unmap";
2198         status = hns3_cmd_send(hw, &desc, 1);
2199         if (status) {
2200                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2201                          op_str, queue_id, req->int_vector_id, status);
2202                 return status;
2203         }
2204
2205         return 0;
2206 }
2207
2208 static int
2209 hns3_init_ring_with_vector(struct hns3_hw *hw)
2210 {
2211         uint8_t vec;
2212         int ret;
2213         int i;
2214
2215         /*
2216          * In hns3 network engine, vector 0 is always the misc interrupt of this
2217          * function, vector 1~N can be used respectively for the queues of the
2218          * function. Tx and Rx queues with the same number share the interrupt
2219          * vector. In the initialization clearing the all hardware mapping
2220          * relationship configurations between queues and interrupt vectors is
2221          * needed, so some error caused by the residual configurations, such as
2222          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2223          * constraints in hns3 hardware engine, we have to implement clearing
2224          * the mapping relationship configurations by binding all queues to the
2225          * last interrupt vector and reserving the last interrupt vector. This
2226          * method results in a decrease of the maximum queues when upper
2227          * applications call the rte_eth_dev_configure API function to enable
2228          * Rx interrupt.
2229          */
2230         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2231         /* vec - 1: the last interrupt is reserved */
2232         hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;
2233         for (i = 0; i < hw->intr_tqps_num; i++) {
2234                 /*
2235                  * Set gap limiter and rate limiter configuration of queue's
2236                  * interrupt.
2237                  */
2238                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2239                                        HNS3_TQP_INTR_GL_DEFAULT);
2240                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2241                                        HNS3_TQP_INTR_GL_DEFAULT);
2242                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2243
2244                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2245                                                  HNS3_RING_TYPE_TX, i);
2246                 if (ret) {
2247                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2248                                           "vector: %d, ret=%d", i, vec, ret);
2249                         return ret;
2250                 }
2251
2252                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2253                                                  HNS3_RING_TYPE_RX, i);
2254                 if (ret) {
2255                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2256                                           "vector: %d, ret=%d", i, vec, ret);
2257                         return ret;
2258                 }
2259         }
2260
2261         return 0;
2262 }
2263
2264 static int
2265 hns3_dev_configure(struct rte_eth_dev *dev)
2266 {
2267         struct hns3_adapter *hns = dev->data->dev_private;
2268         struct rte_eth_conf *conf = &dev->data->dev_conf;
2269         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2270         struct hns3_hw *hw = &hns->hw;
2271         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2272         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2273         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2274         struct rte_eth_rss_conf rss_conf;
2275         uint16_t mtu;
2276         bool gro_en;
2277         int ret;
2278
2279         /*
2280          * Hardware does not support individually enable/disable/reset the Tx or
2281          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2282          * and Rx queues at the same time. When the numbers of Tx queues
2283          * allocated by upper applications are not equal to the numbers of Rx
2284          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2285          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2286          * these fake queues are imperceptible, and can not be used by upper
2287          * applications.
2288          */
2289         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2290         if (ret) {
2291                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2292                 return ret;
2293         }
2294
2295         hw->adapter_state = HNS3_NIC_CONFIGURING;
2296         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2297                 hns3_err(hw, "setting link speed/duplex not supported");
2298                 ret = -EINVAL;
2299                 goto cfg_err;
2300         }
2301
2302         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2303                 ret = hns3_check_dcb_cfg(dev);
2304                 if (ret)
2305                         goto cfg_err;
2306         }
2307
2308         /* When RSS is not configured, redirect the packet queue 0 */
2309         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2310                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2311                 rss_conf = conf->rx_adv_conf.rss_conf;
2312                 if (rss_conf.rss_key == NULL) {
2313                         rss_conf.rss_key = rss_cfg->key;
2314                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2315                 }
2316
2317                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2318                 if (ret)
2319                         goto cfg_err;
2320         }
2321
2322         /*
2323          * If jumbo frames are enabled, MTU needs to be refreshed
2324          * according to the maximum RX packet length.
2325          */
2326         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2327                 /*
2328                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2329                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2330                  * can safely assign to "uint16_t" type variable.
2331                  */
2332                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2333                 ret = hns3_dev_mtu_set(dev, mtu);
2334                 if (ret)
2335                         goto cfg_err;
2336                 dev->data->mtu = mtu;
2337         }
2338
2339         ret = hns3_dev_configure_vlan(dev);
2340         if (ret)
2341                 goto cfg_err;
2342
2343         /* config hardware GRO */
2344         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2345         ret = hns3_config_gro(hw, gro_en);
2346         if (ret)
2347                 goto cfg_err;
2348
2349         hw->adapter_state = HNS3_NIC_CONFIGURED;
2350
2351         return 0;
2352
2353 cfg_err:
2354         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2355         hw->adapter_state = HNS3_NIC_INITIALIZED;
2356
2357         return ret;
2358 }
2359
2360 static int
2361 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2362 {
2363         struct hns3_config_max_frm_size_cmd *req;
2364         struct hns3_cmd_desc desc;
2365
2366         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2367
2368         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2369         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2370         req->min_frm_size = RTE_ETHER_MIN_LEN;
2371
2372         return hns3_cmd_send(hw, &desc, 1);
2373 }
2374
2375 static int
2376 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2377 {
2378         int ret;
2379
2380         ret = hns3_set_mac_mtu(hw, mps);
2381         if (ret) {
2382                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2383                 return ret;
2384         }
2385
2386         ret = hns3_buffer_alloc(hw);
2387         if (ret)
2388                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2389
2390         return ret;
2391 }
2392
2393 static int
2394 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2395 {
2396         struct hns3_adapter *hns = dev->data->dev_private;
2397         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2398         struct hns3_hw *hw = &hns->hw;
2399         bool is_jumbo_frame;
2400         int ret;
2401
2402         if (dev->data->dev_started) {
2403                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2404                          "before configuration", dev->data->port_id);
2405                 return -EBUSY;
2406         }
2407
2408         rte_spinlock_lock(&hw->lock);
2409         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2410         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2411
2412         /*
2413          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2414          * assign to "uint16_t" type variable.
2415          */
2416         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2417         if (ret) {
2418                 rte_spinlock_unlock(&hw->lock);
2419                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2420                          dev->data->port_id, mtu, ret);
2421                 return ret;
2422         }
2423         hns->pf.mps = (uint16_t)frame_size;
2424         if (is_jumbo_frame)
2425                 dev->data->dev_conf.rxmode.offloads |=
2426                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2427         else
2428                 dev->data->dev_conf.rxmode.offloads &=
2429                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2430         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2431         rte_spinlock_unlock(&hw->lock);
2432
2433         return 0;
2434 }
2435
2436 static int
2437 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2438 {
2439         struct hns3_adapter *hns = eth_dev->data->dev_private;
2440         struct hns3_hw *hw = &hns->hw;
2441         uint16_t queue_num = hw->tqps_num;
2442
2443         /*
2444          * In interrupt mode, 'max_rx_queues' is set based on the number of
2445          * MSI-X interrupt resources of the hardware.
2446          */
2447         if (hw->data->dev_conf.intr_conf.rxq == 1)
2448                 queue_num = hw->intr_tqps_num;
2449
2450         info->max_rx_queues = queue_num;
2451         info->max_tx_queues = hw->tqps_num;
2452         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2453         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2454         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2455         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2456         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2457         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2458                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2459                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2460                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2461                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2462                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2463                                  DEV_RX_OFFLOAD_KEEP_CRC |
2464                                  DEV_RX_OFFLOAD_SCATTER |
2465                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2466                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2467                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2468                                  DEV_RX_OFFLOAD_RSS_HASH |
2469                                  DEV_RX_OFFLOAD_TCP_LRO);
2470         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2471         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2472                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2473                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2474                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2475                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2476                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2477                                  DEV_TX_OFFLOAD_TCP_TSO |
2478                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2479                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2480                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2481                                  info->tx_queue_offload_capa |
2482                                  hns3_txvlan_cap_get(hw));
2483
2484         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2485                 .nb_max = HNS3_MAX_RING_DESC,
2486                 .nb_min = HNS3_MIN_RING_DESC,
2487                 .nb_align = HNS3_ALIGN_RING_DESC,
2488         };
2489
2490         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2491                 .nb_max = HNS3_MAX_RING_DESC,
2492                 .nb_min = HNS3_MIN_RING_DESC,
2493                 .nb_align = HNS3_ALIGN_RING_DESC,
2494                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2495                 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT,
2496         };
2497
2498         info->vmdq_queue_num = 0;
2499
2500         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2501         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2502         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2503
2504         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2505         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2506         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2507         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2508         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2509         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2510
2511         return 0;
2512 }
2513
2514 static int
2515 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2516                     size_t fw_size)
2517 {
2518         struct hns3_adapter *hns = eth_dev->data->dev_private;
2519         struct hns3_hw *hw = &hns->hw;
2520         uint32_t version = hw->fw_version;
2521         int ret;
2522
2523         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2524                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2525                                       HNS3_FW_VERSION_BYTE3_S),
2526                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2527                                       HNS3_FW_VERSION_BYTE2_S),
2528                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2529                                       HNS3_FW_VERSION_BYTE1_S),
2530                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2531                                       HNS3_FW_VERSION_BYTE0_S));
2532         ret += 1; /* add the size of '\0' */
2533         if (fw_size < (uint32_t)ret)
2534                 return ret;
2535         else
2536                 return 0;
2537 }
2538
2539 static int
2540 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2541                      __rte_unused int wait_to_complete)
2542 {
2543         struct hns3_adapter *hns = eth_dev->data->dev_private;
2544         struct hns3_hw *hw = &hns->hw;
2545         struct hns3_mac *mac = &hw->mac;
2546         struct rte_eth_link new_link;
2547
2548         if (!hns3_is_reset_pending(hns)) {
2549                 hns3_update_speed_duplex(eth_dev);
2550                 hns3_update_link_status(hw);
2551         }
2552
2553         memset(&new_link, 0, sizeof(new_link));
2554         switch (mac->link_speed) {
2555         case ETH_SPEED_NUM_10M:
2556         case ETH_SPEED_NUM_100M:
2557         case ETH_SPEED_NUM_1G:
2558         case ETH_SPEED_NUM_10G:
2559         case ETH_SPEED_NUM_25G:
2560         case ETH_SPEED_NUM_40G:
2561         case ETH_SPEED_NUM_50G:
2562         case ETH_SPEED_NUM_100G:
2563         case ETH_SPEED_NUM_200G:
2564                 new_link.link_speed = mac->link_speed;
2565                 break;
2566         default:
2567                 new_link.link_speed = ETH_SPEED_NUM_100M;
2568                 break;
2569         }
2570
2571         new_link.link_duplex = mac->link_duplex;
2572         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2573         new_link.link_autoneg =
2574             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2575
2576         return rte_eth_linkstatus_set(eth_dev, &new_link);
2577 }
2578
2579 static int
2580 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2581 {
2582         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2583         struct hns3_pf *pf = &hns->pf;
2584
2585         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2586                 return -EINVAL;
2587
2588         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2589
2590         return 0;
2591 }
2592
2593 static int
2594 hns3_query_function_status(struct hns3_hw *hw)
2595 {
2596 #define HNS3_QUERY_MAX_CNT              10
2597 #define HNS3_QUERY_SLEEP_MSCOEND        1
2598         struct hns3_func_status_cmd *req;
2599         struct hns3_cmd_desc desc;
2600         int timeout = 0;
2601         int ret;
2602
2603         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2604         req = (struct hns3_func_status_cmd *)desc.data;
2605
2606         do {
2607                 ret = hns3_cmd_send(hw, &desc, 1);
2608                 if (ret) {
2609                         PMD_INIT_LOG(ERR, "query function status failed %d",
2610                                      ret);
2611                         return ret;
2612                 }
2613
2614                 /* Check pf reset is done */
2615                 if (req->pf_state)
2616                         break;
2617
2618                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2619         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2620
2621         return hns3_parse_func_status(hw, req);
2622 }
2623
2624 static int
2625 hns3_query_pf_resource(struct hns3_hw *hw)
2626 {
2627         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2628         struct hns3_pf *pf = &hns->pf;
2629         struct hns3_pf_res_cmd *req;
2630         struct hns3_cmd_desc desc;
2631         int ret;
2632
2633         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2634         ret = hns3_cmd_send(hw, &desc, 1);
2635         if (ret) {
2636                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2637                 return ret;
2638         }
2639
2640         req = (struct hns3_pf_res_cmd *)desc.data;
2641         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2642         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2643         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2644         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2645
2646         if (req->tx_buf_size)
2647                 pf->tx_buf_size =
2648                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2649         else
2650                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2651
2652         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2653
2654         if (req->dv_buf_size)
2655                 pf->dv_buf_size =
2656                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2657         else
2658                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2659
2660         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2661
2662         hw->num_msi =
2663             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2664                            HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2665
2666         return 0;
2667 }
2668
2669 static void
2670 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2671 {
2672         struct hns3_cfg_param_cmd *req;
2673         uint64_t mac_addr_tmp_high;
2674         uint64_t mac_addr_tmp;
2675         uint32_t i;
2676
2677         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2678
2679         /* get the configuration */
2680         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2681                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2682         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2683                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2684         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2685                                            HNS3_CFG_TQP_DESC_N_M,
2686                                            HNS3_CFG_TQP_DESC_N_S);
2687
2688         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2689                                        HNS3_CFG_PHY_ADDR_M,
2690                                        HNS3_CFG_PHY_ADDR_S);
2691         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2692                                          HNS3_CFG_MEDIA_TP_M,
2693                                          HNS3_CFG_MEDIA_TP_S);
2694         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2695                                          HNS3_CFG_RX_BUF_LEN_M,
2696                                          HNS3_CFG_RX_BUF_LEN_S);
2697         /* get mac address */
2698         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2699         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2700                                            HNS3_CFG_MAC_ADDR_H_M,
2701                                            HNS3_CFG_MAC_ADDR_H_S);
2702
2703         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2704
2705         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2706                                             HNS3_CFG_DEFAULT_SPEED_M,
2707                                             HNS3_CFG_DEFAULT_SPEED_S);
2708         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2709                                            HNS3_CFG_RSS_SIZE_M,
2710                                            HNS3_CFG_RSS_SIZE_S);
2711
2712         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2713                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2714
2715         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2716         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2717
2718         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2719                                             HNS3_CFG_SPEED_ABILITY_M,
2720                                             HNS3_CFG_SPEED_ABILITY_S);
2721         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2722                                         HNS3_CFG_UMV_TBL_SPACE_M,
2723                                         HNS3_CFG_UMV_TBL_SPACE_S);
2724         if (!cfg->umv_space)
2725                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2726 }
2727
2728 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2729  * @hw: pointer to struct hns3_hw
2730  * @hcfg: the config structure to be getted
2731  */
2732 static int
2733 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2734 {
2735         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2736         struct hns3_cfg_param_cmd *req;
2737         uint32_t offset;
2738         uint32_t i;
2739         int ret;
2740
2741         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2742                 offset = 0;
2743                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2744                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2745                                           true);
2746                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2747                                i * HNS3_CFG_RD_LEN_BYTES);
2748                 /* Len should be divided by 4 when send to hardware */
2749                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2750                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2751                 req->offset = rte_cpu_to_le_32(offset);
2752         }
2753
2754         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2755         if (ret) {
2756                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2757                 return ret;
2758         }
2759
2760         hns3_parse_cfg(hcfg, desc);
2761
2762         return 0;
2763 }
2764
2765 static int
2766 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2767 {
2768         switch (speed_cmd) {
2769         case HNS3_CFG_SPEED_10M:
2770                 *speed = ETH_SPEED_NUM_10M;
2771                 break;
2772         case HNS3_CFG_SPEED_100M:
2773                 *speed = ETH_SPEED_NUM_100M;
2774                 break;
2775         case HNS3_CFG_SPEED_1G:
2776                 *speed = ETH_SPEED_NUM_1G;
2777                 break;
2778         case HNS3_CFG_SPEED_10G:
2779                 *speed = ETH_SPEED_NUM_10G;
2780                 break;
2781         case HNS3_CFG_SPEED_25G:
2782                 *speed = ETH_SPEED_NUM_25G;
2783                 break;
2784         case HNS3_CFG_SPEED_40G:
2785                 *speed = ETH_SPEED_NUM_40G;
2786                 break;
2787         case HNS3_CFG_SPEED_50G:
2788                 *speed = ETH_SPEED_NUM_50G;
2789                 break;
2790         case HNS3_CFG_SPEED_100G:
2791                 *speed = ETH_SPEED_NUM_100G;
2792                 break;
2793         case HNS3_CFG_SPEED_200G:
2794                 *speed = ETH_SPEED_NUM_200G;
2795                 break;
2796         default:
2797                 return -EINVAL;
2798         }
2799
2800         return 0;
2801 }
2802
2803 static int
2804 hns3_get_capability(struct hns3_hw *hw)
2805 {
2806         struct rte_pci_device *pci_dev;
2807         struct rte_eth_dev *eth_dev;
2808         uint16_t device_id;
2809         uint8_t revision;
2810         int ret;
2811
2812         eth_dev = &rte_eth_devices[hw->data->port_id];
2813         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2814         device_id = pci_dev->id.device_id;
2815
2816         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
2817             device_id == HNS3_DEV_ID_50GE_RDMA ||
2818             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
2819             device_id == HNS3_DEV_ID_200G_RDMA)
2820                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
2821
2822         /* Get PCI revision id */
2823         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
2824                                   HNS3_PCI_REVISION_ID);
2825         if (ret != HNS3_PCI_REVISION_ID_LEN) {
2826                 PMD_INIT_LOG(ERR, "failed to read pci revision id: %d", ret);
2827                 return -EIO;
2828         }
2829         hw->revision = revision;
2830
2831         if (revision >= PCI_REVISION_ID_HIP09_A)
2832                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_COPPER_B, 1);
2833
2834         return 0;
2835 }
2836
2837 static int
2838 hns3_get_board_configuration(struct hns3_hw *hw)
2839 {
2840         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2841         struct hns3_pf *pf = &hns->pf;
2842         struct hns3_cfg cfg;
2843         int ret;
2844
2845         ret = hns3_get_board_cfg(hw, &cfg);
2846         if (ret) {
2847                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2848                 return ret;
2849         }
2850
2851         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
2852             !hns3_dev_copper_supported(hw)) {
2853                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2854                 return -EOPNOTSUPP;
2855         }
2856
2857         hw->mac.media_type = cfg.media_type;
2858         hw->rss_size_max = cfg.rss_size_max;
2859         hw->rss_dis_flag = false;
2860         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2861         hw->mac.phy_addr = cfg.phy_addr;
2862         hw->mac.default_addr_setted = false;
2863         hw->num_tx_desc = cfg.tqp_desc_num;
2864         hw->num_rx_desc = cfg.tqp_desc_num;
2865         hw->dcb_info.num_pg = 1;
2866         hw->dcb_info.hw_pfc_map = 0;
2867
2868         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2869         if (ret) {
2870                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2871                              cfg.default_speed, ret);
2872                 return ret;
2873         }
2874
2875         pf->tc_max = cfg.tc_num;
2876         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2877                 PMD_INIT_LOG(WARNING,
2878                              "Get TC num(%u) from flash, set TC num to 1",
2879                              pf->tc_max);
2880                 pf->tc_max = 1;
2881         }
2882
2883         /* Dev does not support DCB */
2884         if (!hns3_dev_dcb_supported(hw)) {
2885                 pf->tc_max = 1;
2886                 pf->pfc_max = 0;
2887         } else
2888                 pf->pfc_max = pf->tc_max;
2889
2890         hw->dcb_info.num_tc = 1;
2891         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2892                                      hw->tqps_num / hw->dcb_info.num_tc);
2893         hns3_set_bit(hw->hw_tc_map, 0, 1);
2894         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2895
2896         pf->wanted_umv_size = cfg.umv_space;
2897
2898         return ret;
2899 }
2900
2901 static int
2902 hns3_get_configuration(struct hns3_hw *hw)
2903 {
2904         int ret;
2905
2906         ret = hns3_query_function_status(hw);
2907         if (ret) {
2908                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2909                 return ret;
2910         }
2911
2912         /* Get device capability */
2913         ret = hns3_get_capability(hw);
2914         if (ret) {
2915                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
2916                 return ret;
2917         }
2918
2919         /* Get pf resource */
2920         ret = hns3_query_pf_resource(hw);
2921         if (ret) {
2922                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2923                 return ret;
2924         }
2925
2926         ret = hns3_get_board_configuration(hw);
2927         if (ret)
2928                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2929
2930         return ret;
2931 }
2932
2933 static int
2934 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2935                       uint16_t tqp_vid, bool is_pf)
2936 {
2937         struct hns3_tqp_map_cmd *req;
2938         struct hns3_cmd_desc desc;
2939         int ret;
2940
2941         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2942
2943         req = (struct hns3_tqp_map_cmd *)desc.data;
2944         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2945         req->tqp_vf = func_id;
2946         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2947         if (!is_pf)
2948                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2949         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2950
2951         ret = hns3_cmd_send(hw, &desc, 1);
2952         if (ret)
2953                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2954
2955         return ret;
2956 }
2957
2958 static int
2959 hns3_map_tqp(struct hns3_hw *hw)
2960 {
2961         uint16_t tqps_num = hw->total_tqps_num;
2962         uint16_t func_id;
2963         uint16_t tqp_id;
2964         bool is_pf;
2965         int num;
2966         int ret;
2967         int i;
2968
2969         /*
2970          * In current version VF is not supported when PF is driven by DPDK
2971          * driver, so we allocate tqps to PF as much as possible.
2972          */
2973         tqp_id = 0;
2974         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2975         for (func_id = HNS3_PF_FUNC_ID; func_id < num; func_id++) {
2976                 is_pf = func_id == HNS3_PF_FUNC_ID ? true : false;
2977                 for (i = 0;
2978                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2979                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2980                                                     is_pf);
2981                         if (ret)
2982                                 return ret;
2983                 }
2984         }
2985
2986         return 0;
2987 }
2988
2989 static int
2990 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2991 {
2992         struct hns3_config_mac_speed_dup_cmd *req;
2993         struct hns3_cmd_desc desc;
2994         int ret;
2995
2996         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2997
2998         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2999
3000         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3001
3002         switch (speed) {
3003         case ETH_SPEED_NUM_10M:
3004                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3005                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3006                 break;
3007         case ETH_SPEED_NUM_100M:
3008                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3009                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3010                 break;
3011         case ETH_SPEED_NUM_1G:
3012                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3013                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3014                 break;
3015         case ETH_SPEED_NUM_10G:
3016                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3017                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3018                 break;
3019         case ETH_SPEED_NUM_25G:
3020                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3021                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3022                 break;
3023         case ETH_SPEED_NUM_40G:
3024                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3025                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3026                 break;
3027         case ETH_SPEED_NUM_50G:
3028                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3029                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3030                 break;
3031         case ETH_SPEED_NUM_100G:
3032                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3033                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3034                 break;
3035         case ETH_SPEED_NUM_200G:
3036                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3037                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3038                 break;
3039         default:
3040                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3041                 return -EINVAL;
3042         }
3043
3044         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3045
3046         ret = hns3_cmd_send(hw, &desc, 1);
3047         if (ret)
3048                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3049
3050         return ret;
3051 }
3052
3053 static int
3054 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3055 {
3056         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3057         struct hns3_pf *pf = &hns->pf;
3058         struct hns3_priv_buf *priv;
3059         uint32_t i, total_size;
3060
3061         total_size = pf->pkt_buf_size;
3062
3063         /* alloc tx buffer for all enabled tc */
3064         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3065                 priv = &buf_alloc->priv_buf[i];
3066
3067                 if (hw->hw_tc_map & BIT(i)) {
3068                         if (total_size < pf->tx_buf_size)
3069                                 return -ENOMEM;
3070
3071                         priv->tx_buf_size = pf->tx_buf_size;
3072                 } else
3073                         priv->tx_buf_size = 0;
3074
3075                 total_size -= priv->tx_buf_size;
3076         }
3077
3078         return 0;
3079 }
3080
3081 static int
3082 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3083 {
3084 /* TX buffer size is unit by 128 byte */
3085 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3086 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3087         struct hns3_tx_buff_alloc_cmd *req;
3088         struct hns3_cmd_desc desc;
3089         uint32_t buf_size;
3090         uint32_t i;
3091         int ret;
3092
3093         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3094
3095         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3096         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3097                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3098
3099                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3100                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3101                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3102         }
3103
3104         ret = hns3_cmd_send(hw, &desc, 1);
3105         if (ret)
3106                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3107
3108         return ret;
3109 }
3110
3111 static int
3112 hns3_get_tc_num(struct hns3_hw *hw)
3113 {
3114         int cnt = 0;
3115         uint8_t i;
3116
3117         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3118                 if (hw->hw_tc_map & BIT(i))
3119                         cnt++;
3120         return cnt;
3121 }
3122
3123 static uint32_t
3124 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3125 {
3126         struct hns3_priv_buf *priv;
3127         uint32_t rx_priv = 0;
3128         int i;
3129
3130         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3131                 priv = &buf_alloc->priv_buf[i];
3132                 if (priv->enable)
3133                         rx_priv += priv->buf_size;
3134         }
3135         return rx_priv;
3136 }
3137
3138 static uint32_t
3139 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3140 {
3141         uint32_t total_tx_size = 0;
3142         uint32_t i;
3143
3144         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3145                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3146
3147         return total_tx_size;
3148 }
3149
3150 /* Get the number of pfc enabled TCs, which have private buffer */
3151 static int
3152 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3153 {
3154         struct hns3_priv_buf *priv;
3155         int cnt = 0;
3156         uint8_t i;
3157
3158         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3159                 priv = &buf_alloc->priv_buf[i];
3160                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3161                         cnt++;
3162         }
3163
3164         return cnt;
3165 }
3166
3167 /* Get the number of pfc disabled TCs, which have private buffer */
3168 static int
3169 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3170                          struct hns3_pkt_buf_alloc *buf_alloc)
3171 {
3172         struct hns3_priv_buf *priv;
3173         int cnt = 0;
3174         uint8_t i;
3175
3176         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3177                 priv = &buf_alloc->priv_buf[i];
3178                 if (hw->hw_tc_map & BIT(i) &&
3179                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3180                         cnt++;
3181         }
3182
3183         return cnt;
3184 }
3185
3186 static bool
3187 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3188                   uint32_t rx_all)
3189 {
3190         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3191         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3192         struct hns3_pf *pf = &hns->pf;
3193         uint32_t shared_buf, aligned_mps;
3194         uint32_t rx_priv;
3195         uint8_t tc_num;
3196         uint8_t i;
3197
3198         tc_num = hns3_get_tc_num(hw);
3199         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3200
3201         if (hns3_dev_dcb_supported(hw))
3202                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3203                                         pf->dv_buf_size;
3204         else
3205                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3206                                         + pf->dv_buf_size;
3207
3208         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3209         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3210                              HNS3_BUF_SIZE_UNIT);
3211
3212         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3213         if (rx_all < rx_priv + shared_std)
3214                 return false;
3215
3216         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3217         buf_alloc->s_buf.buf_size = shared_buf;
3218         if (hns3_dev_dcb_supported(hw)) {
3219                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3220                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3221                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3222                                   HNS3_BUF_SIZE_UNIT);
3223         } else {
3224                 buf_alloc->s_buf.self.high =
3225                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3226                 buf_alloc->s_buf.self.low = aligned_mps;
3227         }
3228
3229         if (hns3_dev_dcb_supported(hw)) {
3230                 hi_thrd = shared_buf - pf->dv_buf_size;
3231
3232                 if (tc_num <= NEED_RESERVE_TC_NUM)
3233                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3234                                         / BUF_MAX_PERCENT;
3235
3236                 if (tc_num)
3237                         hi_thrd = hi_thrd / tc_num;
3238
3239                 hi_thrd = max_t(uint32_t, hi_thrd,
3240                                 HNS3_BUF_MUL_BY * aligned_mps);
3241                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3242                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3243         } else {
3244                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3245                 lo_thrd = aligned_mps;
3246         }
3247
3248         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3249                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3250                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3251         }
3252
3253         return true;
3254 }
3255
3256 static bool
3257 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3258                      struct hns3_pkt_buf_alloc *buf_alloc)
3259 {
3260         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3261         struct hns3_pf *pf = &hns->pf;
3262         struct hns3_priv_buf *priv;
3263         uint32_t aligned_mps;
3264         uint32_t rx_all;
3265         uint8_t i;
3266
3267         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3268         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3269
3270         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3271                 priv = &buf_alloc->priv_buf[i];
3272
3273                 priv->enable = 0;
3274                 priv->wl.low = 0;
3275                 priv->wl.high = 0;
3276                 priv->buf_size = 0;
3277
3278                 if (!(hw->hw_tc_map & BIT(i)))
3279                         continue;
3280
3281                 priv->enable = 1;
3282                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3283                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3284                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3285                                                 HNS3_BUF_SIZE_UNIT);
3286                 } else {
3287                         priv->wl.low = 0;
3288                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3289                                         aligned_mps;
3290                 }
3291
3292                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3293         }
3294
3295         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3296 }
3297
3298 static bool
3299 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3300                              struct hns3_pkt_buf_alloc *buf_alloc)
3301 {
3302         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3303         struct hns3_pf *pf = &hns->pf;
3304         struct hns3_priv_buf *priv;
3305         int no_pfc_priv_num;
3306         uint32_t rx_all;
3307         uint8_t mask;
3308         int i;
3309
3310         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3311         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3312
3313         /* let the last to be cleared first */
3314         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3315                 priv = &buf_alloc->priv_buf[i];
3316                 mask = BIT((uint8_t)i);
3317
3318                 if (hw->hw_tc_map & mask &&
3319                     !(hw->dcb_info.hw_pfc_map & mask)) {
3320                         /* Clear the no pfc TC private buffer */
3321                         priv->wl.low = 0;
3322                         priv->wl.high = 0;
3323                         priv->buf_size = 0;
3324                         priv->enable = 0;
3325                         no_pfc_priv_num--;
3326                 }
3327
3328                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3329                     no_pfc_priv_num == 0)
3330                         break;
3331         }
3332
3333         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3334 }
3335
3336 static bool
3337 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3338                            struct hns3_pkt_buf_alloc *buf_alloc)
3339 {
3340         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3341         struct hns3_pf *pf = &hns->pf;
3342         struct hns3_priv_buf *priv;
3343         uint32_t rx_all;
3344         int pfc_priv_num;
3345         uint8_t mask;
3346         int i;
3347
3348         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3349         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3350
3351         /* let the last to be cleared first */
3352         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3353                 priv = &buf_alloc->priv_buf[i];
3354                 mask = BIT((uint8_t)i);
3355
3356                 if (hw->hw_tc_map & mask &&
3357                     hw->dcb_info.hw_pfc_map & mask) {
3358                         /* Reduce the number of pfc TC with private buffer */
3359                         priv->wl.low = 0;
3360                         priv->enable = 0;
3361                         priv->wl.high = 0;
3362                         priv->buf_size = 0;
3363                         pfc_priv_num--;
3364                 }
3365                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3366                     pfc_priv_num == 0)
3367                         break;
3368         }
3369
3370         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3371 }
3372
3373 static bool
3374 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3375                           struct hns3_pkt_buf_alloc *buf_alloc)
3376 {
3377 #define COMPENSATE_BUFFER       0x3C00
3378 #define COMPENSATE_HALF_MPS_NUM 5
3379 #define PRIV_WL_GAP             0x1800
3380         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3381         struct hns3_pf *pf = &hns->pf;
3382         uint32_t tc_num = hns3_get_tc_num(hw);
3383         uint32_t half_mps = pf->mps >> 1;
3384         struct hns3_priv_buf *priv;
3385         uint32_t min_rx_priv;
3386         uint32_t rx_priv;
3387         uint8_t i;
3388
3389         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3390         if (tc_num)
3391                 rx_priv = rx_priv / tc_num;
3392
3393         if (tc_num <= NEED_RESERVE_TC_NUM)
3394                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3395
3396         /*
3397          * Minimum value of private buffer in rx direction (min_rx_priv) is
3398          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3399          * buffer if rx_priv is greater than min_rx_priv.
3400          */
3401         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3402                         COMPENSATE_HALF_MPS_NUM * half_mps;
3403         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3404         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3405
3406         if (rx_priv < min_rx_priv)
3407                 return false;
3408
3409         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3410                 priv = &buf_alloc->priv_buf[i];
3411
3412                 priv->enable = 0;
3413                 priv->wl.low = 0;
3414                 priv->wl.high = 0;
3415                 priv->buf_size = 0;
3416
3417                 if (!(hw->hw_tc_map & BIT(i)))
3418                         continue;
3419
3420                 priv->enable = 1;
3421                 priv->buf_size = rx_priv;
3422                 priv->wl.high = rx_priv - pf->dv_buf_size;
3423                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3424         }
3425
3426         buf_alloc->s_buf.buf_size = 0;
3427
3428         return true;
3429 }
3430
3431 /*
3432  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3433  * @hw: pointer to struct hns3_hw
3434  * @buf_alloc: pointer to buffer calculation data
3435  * @return: 0: calculate sucessful, negative: fail
3436  */
3437 static int
3438 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3439 {
3440         /* When DCB is not supported, rx private buffer is not allocated. */
3441         if (!hns3_dev_dcb_supported(hw)) {
3442                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3443                 struct hns3_pf *pf = &hns->pf;
3444                 uint32_t rx_all = pf->pkt_buf_size;
3445
3446                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3447                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3448                         return -ENOMEM;
3449
3450                 return 0;
3451         }
3452
3453         /*
3454          * Try to allocate privated packet buffer for all TCs without share
3455          * buffer.
3456          */
3457         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3458                 return 0;
3459
3460         /*
3461          * Try to allocate privated packet buffer for all TCs with share
3462          * buffer.
3463          */
3464         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3465                 return 0;
3466
3467         /*
3468          * For different application scenes, the enabled port number, TC number
3469          * and no_drop TC number are different. In order to obtain the better
3470          * performance, software could allocate the buffer size and configure
3471          * the waterline by tring to decrease the private buffer size according
3472          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3473          * enabled tc.
3474          */
3475         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3476                 return 0;
3477
3478         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3479                 return 0;
3480
3481         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3482                 return 0;
3483
3484         return -ENOMEM;
3485 }
3486
3487 static int
3488 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3489 {
3490         struct hns3_rx_priv_buff_cmd *req;
3491         struct hns3_cmd_desc desc;
3492         uint32_t buf_size;
3493         int ret;
3494         int i;
3495
3496         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3497         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3498
3499         /* Alloc private buffer TCs */
3500         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3501                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3502
3503                 req->buf_num[i] =
3504                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3505                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3506         }
3507
3508         buf_size = buf_alloc->s_buf.buf_size;
3509         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3510                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3511
3512         ret = hns3_cmd_send(hw, &desc, 1);
3513         if (ret)
3514                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3515
3516         return ret;
3517 }
3518
3519 static int
3520 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3521 {
3522 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3523         struct hns3_rx_priv_wl_buf *req;
3524         struct hns3_priv_buf *priv;
3525         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3526         int i, j;
3527         int ret;
3528
3529         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3530                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3531                                           false);
3532                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3533
3534                 /* The first descriptor set the NEXT bit to 1 */
3535                 if (i == 0)
3536                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3537                 else
3538                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3539
3540                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3541                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3542
3543                         priv = &buf_alloc->priv_buf[idx];
3544                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3545                                                         HNS3_BUF_UNIT_S);
3546                         req->tc_wl[j].high |=
3547                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3548                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3549                                                         HNS3_BUF_UNIT_S);
3550                         req->tc_wl[j].low |=
3551                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3552                 }
3553         }
3554
3555         /* Send 2 descriptor at one time */
3556         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3557         if (ret)
3558                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3559                              ret);
3560         return ret;
3561 }
3562
3563 static int
3564 hns3_common_thrd_config(struct hns3_hw *hw,
3565                         struct hns3_pkt_buf_alloc *buf_alloc)
3566 {
3567 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3568         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3569         struct hns3_rx_com_thrd *req;
3570         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3571         struct hns3_tc_thrd *tc;
3572         int tc_idx;
3573         int i, j;
3574         int ret;
3575
3576         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3577                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3578                                           false);
3579                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3580
3581                 /* The first descriptor set the NEXT bit to 1 */
3582                 if (i == 0)
3583                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3584                 else
3585                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3586
3587                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3588                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3589                         tc = &s_buf->tc_thrd[tc_idx];
3590
3591                         req->com_thrd[j].high =
3592                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3593                         req->com_thrd[j].high |=
3594                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3595                         req->com_thrd[j].low =
3596                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3597                         req->com_thrd[j].low |=
3598                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3599                 }
3600         }
3601
3602         /* Send 2 descriptors at one time */
3603         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3604         if (ret)
3605                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3606
3607         return ret;
3608 }
3609
3610 static int
3611 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3612 {
3613         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3614         struct hns3_rx_com_wl *req;
3615         struct hns3_cmd_desc desc;
3616         int ret;
3617
3618         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3619
3620         req = (struct hns3_rx_com_wl *)desc.data;
3621         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3622         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3623
3624         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3625         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3626
3627         ret = hns3_cmd_send(hw, &desc, 1);
3628         if (ret)
3629                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3630
3631         return ret;
3632 }
3633
3634 int
3635 hns3_buffer_alloc(struct hns3_hw *hw)
3636 {
3637         struct hns3_pkt_buf_alloc pkt_buf;
3638         int ret;
3639
3640         memset(&pkt_buf, 0, sizeof(pkt_buf));
3641         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3642         if (ret) {
3643                 PMD_INIT_LOG(ERR,
3644                              "could not calc tx buffer size for all TCs %d",
3645                              ret);
3646                 return ret;
3647         }
3648
3649         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3650         if (ret) {
3651                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3652                 return ret;
3653         }
3654
3655         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3656         if (ret) {
3657                 PMD_INIT_LOG(ERR,
3658                              "could not calc rx priv buffer size for all TCs %d",
3659                              ret);
3660                 return ret;
3661         }
3662
3663         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3664         if (ret) {
3665                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3666                 return ret;
3667         }
3668
3669         if (hns3_dev_dcb_supported(hw)) {
3670                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3671                 if (ret) {
3672                         PMD_INIT_LOG(ERR,
3673                                      "could not configure rx private waterline %d",
3674                                      ret);
3675                         return ret;
3676                 }
3677
3678                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3679                 if (ret) {
3680                         PMD_INIT_LOG(ERR,
3681                                      "could not configure common threshold %d",
3682                                      ret);
3683                         return ret;
3684                 }
3685         }
3686
3687         ret = hns3_common_wl_config(hw, &pkt_buf);
3688         if (ret)
3689                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3690                              ret);
3691
3692         return ret;
3693 }
3694
3695 static int
3696 hns3_mac_init(struct hns3_hw *hw)
3697 {
3698         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3699         struct hns3_mac *mac = &hw->mac;
3700         struct hns3_pf *pf = &hns->pf;
3701         int ret;
3702
3703         pf->support_sfp_query = true;
3704         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3705         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3706         if (ret) {
3707                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3708                 return ret;
3709         }
3710
3711         mac->link_status = ETH_LINK_DOWN;
3712
3713         return hns3_config_mtu(hw, pf->mps);
3714 }
3715
3716 static int
3717 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3718 {
3719 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3720 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3721 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3722 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3723         int return_status;
3724
3725         if (cmdq_resp) {
3726                 PMD_INIT_LOG(ERR,
3727                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3728                              cmdq_resp);
3729                 return -EIO;
3730         }
3731
3732         switch (resp_code) {
3733         case HNS3_ETHERTYPE_SUCCESS_ADD:
3734         case HNS3_ETHERTYPE_ALREADY_ADD:
3735                 return_status = 0;
3736                 break;
3737         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3738                 PMD_INIT_LOG(ERR,
3739                              "add mac ethertype failed for manager table overflow.");
3740                 return_status = -EIO;
3741                 break;
3742         case HNS3_ETHERTYPE_KEY_CONFLICT:
3743                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3744                 return_status = -EIO;
3745                 break;
3746         default:
3747                 PMD_INIT_LOG(ERR,
3748                              "add mac ethertype failed for undefined, code=%d.",
3749                              resp_code);
3750                 return_status = -EIO;
3751                 break;
3752         }
3753
3754         return return_status;
3755 }
3756
3757 static int
3758 hns3_add_mgr_tbl(struct hns3_hw *hw,
3759                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3760 {
3761         struct hns3_cmd_desc desc;
3762         uint8_t resp_code;
3763         uint16_t retval;
3764         int ret;
3765
3766         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3767         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3768
3769         ret = hns3_cmd_send(hw, &desc, 1);
3770         if (ret) {
3771                 PMD_INIT_LOG(ERR,
3772                              "add mac ethertype failed for cmd_send, ret =%d.",
3773                              ret);
3774                 return ret;
3775         }
3776
3777         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3778         retval = rte_le_to_cpu_16(desc.retval);
3779
3780         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3781 }
3782
3783 static void
3784 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3785                      int *table_item_num)
3786 {
3787         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3788
3789         /*
3790          * In current version, we add one item in management table as below:
3791          * 0x0180C200000E -- LLDP MC address
3792          */
3793         tbl = mgr_table;
3794         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3795         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3796         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3797         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3798         tbl->i_port_bitmap = 0x1;
3799         *table_item_num = 1;
3800 }
3801
3802 static int
3803 hns3_init_mgr_tbl(struct hns3_hw *hw)
3804 {
3805 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3806         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3807         int table_item_num;
3808         int ret;
3809         int i;
3810
3811         memset(mgr_table, 0, sizeof(mgr_table));
3812         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3813         for (i = 0; i < table_item_num; i++) {
3814                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3815                 if (ret) {
3816                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3817                                      ret);
3818                         return ret;
3819                 }
3820         }
3821
3822         return 0;
3823 }
3824
3825 static void
3826 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3827                         bool en_mc, bool en_bc, int vport_id)
3828 {
3829         if (!param)
3830                 return;
3831
3832         memset(param, 0, sizeof(struct hns3_promisc_param));
3833         if (en_uc)
3834                 param->enable = HNS3_PROMISC_EN_UC;
3835         if (en_mc)
3836                 param->enable |= HNS3_PROMISC_EN_MC;
3837         if (en_bc)
3838                 param->enable |= HNS3_PROMISC_EN_BC;
3839         param->vf_id = vport_id;
3840 }
3841
3842 static int
3843 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3844 {
3845         struct hns3_promisc_cfg_cmd *req;
3846         struct hns3_cmd_desc desc;
3847         int ret;
3848
3849         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3850
3851         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3852         req->vf_id = param->vf_id;
3853         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3854             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3855
3856         ret = hns3_cmd_send(hw, &desc, 1);
3857         if (ret)
3858                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3859
3860         return ret;
3861 }
3862
3863 static int
3864 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3865 {
3866         struct hns3_promisc_param param;
3867         bool en_bc_pmc = true;
3868         uint8_t vf_id;
3869
3870         /*
3871          * In current version VF is not supported when PF is driven by DPDK
3872          * driver, just need to configure parameters for PF vport.
3873          */
3874         vf_id = HNS3_PF_FUNC_ID;
3875
3876         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3877         return hns3_cmd_set_promisc_mode(hw, &param);
3878 }
3879
3880 static int
3881 hns3_promisc_init(struct hns3_hw *hw)
3882 {
3883         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3884         struct hns3_pf *pf = &hns->pf;
3885         struct hns3_promisc_param param;
3886         uint16_t func_id;
3887         int ret;
3888
3889         ret = hns3_set_promisc_mode(hw, false, false);
3890         if (ret) {
3891                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
3892                 return ret;
3893         }
3894
3895         /*
3896          * In current version VFs are not supported when PF is driven by DPDK
3897          * driver. After PF has been taken over by DPDK, the original VF will
3898          * be invalid. So, there is a possibility of entry residues. It should
3899          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
3900          * during init.
3901          */
3902         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
3903                 hns3_promisc_param_init(&param, false, false, false, func_id);
3904                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3905                 if (ret) {
3906                         PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode,"
3907                                         " ret = %d", func_id, ret);
3908                         return ret;
3909                 }
3910         }
3911
3912         return 0;
3913 }
3914
3915 static void
3916 hns3_promisc_uninit(struct hns3_hw *hw)
3917 {
3918         struct hns3_promisc_param param;
3919         uint16_t func_id;
3920         int ret;
3921
3922         func_id = HNS3_PF_FUNC_ID;
3923
3924         /*
3925          * In current version VFs are not supported when PF is driven by
3926          * DPDK driver, and VFs' promisc mode status has been cleared during
3927          * init and their status will not change. So just clear PF's promisc
3928          * mode status during uninit.
3929          */
3930         hns3_promisc_param_init(&param, false, false, false, func_id);
3931         ret = hns3_cmd_set_promisc_mode(hw, &param);
3932         if (ret)
3933                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
3934                                 " uninit, ret = %d", ret);
3935 }
3936
3937 static int
3938 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3939 {
3940         bool allmulti = dev->data->all_multicast ? true : false;
3941         struct hns3_adapter *hns = dev->data->dev_private;
3942         struct hns3_hw *hw = &hns->hw;
3943         uint64_t offloads;
3944         int err;
3945         int ret;
3946
3947         rte_spinlock_lock(&hw->lock);
3948         ret = hns3_set_promisc_mode(hw, true, true);
3949         if (ret) {
3950                 rte_spinlock_unlock(&hw->lock);
3951                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
3952                          ret);
3953                 return ret;
3954         }
3955
3956         /*
3957          * When promiscuous mode was enabled, disable the vlan filter to let
3958          * all packets coming in in the receiving direction.
3959          */
3960         offloads = dev->data->dev_conf.rxmode.offloads;
3961         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3962                 ret = hns3_enable_vlan_filter(hns, false);
3963                 if (ret) {
3964                         hns3_err(hw, "failed to enable promiscuous mode due to "
3965                                      "failure to disable vlan filter, ret = %d",
3966                                  ret);
3967                         err = hns3_set_promisc_mode(hw, false, allmulti);
3968                         if (err)
3969                                 hns3_err(hw, "failed to restore promiscuous "
3970                                          "status after disable vlan filter "
3971                                          "failed during enabling promiscuous "
3972                                          "mode, ret = %d", ret);
3973                 }
3974         }
3975
3976         rte_spinlock_unlock(&hw->lock);
3977
3978         return ret;
3979 }
3980
3981 static int
3982 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3983 {
3984         bool allmulti = dev->data->all_multicast ? true : false;
3985         struct hns3_adapter *hns = dev->data->dev_private;
3986         struct hns3_hw *hw = &hns->hw;
3987         uint64_t offloads;
3988         int err;
3989         int ret;
3990
3991         /* If now in all_multicast mode, must remain in all_multicast mode. */
3992         rte_spinlock_lock(&hw->lock);
3993         ret = hns3_set_promisc_mode(hw, false, allmulti);
3994         if (ret) {
3995                 rte_spinlock_unlock(&hw->lock);
3996                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
3997                          ret);
3998                 return ret;
3999         }
4000         /* when promiscuous mode was disabled, restore the vlan filter status */
4001         offloads = dev->data->dev_conf.rxmode.offloads;
4002         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4003                 ret = hns3_enable_vlan_filter(hns, true);
4004                 if (ret) {
4005                         hns3_err(hw, "failed to disable promiscuous mode due to"
4006                                  " failure to restore vlan filter, ret = %d",
4007                                  ret);
4008                         err = hns3_set_promisc_mode(hw, true, true);
4009                         if (err)
4010                                 hns3_err(hw, "failed to restore promiscuous "
4011                                          "status after enabling vlan filter "
4012                                          "failed during disabling promiscuous "
4013                                          "mode, ret = %d", ret);
4014                 }
4015         }
4016         rte_spinlock_unlock(&hw->lock);
4017
4018         return ret;
4019 }
4020
4021 static int
4022 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4023 {
4024         struct hns3_adapter *hns = dev->data->dev_private;
4025         struct hns3_hw *hw = &hns->hw;
4026         int ret;
4027
4028         if (dev->data->promiscuous)
4029                 return 0;
4030
4031         rte_spinlock_lock(&hw->lock);
4032         ret = hns3_set_promisc_mode(hw, false, true);
4033         rte_spinlock_unlock(&hw->lock);
4034         if (ret)
4035                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4036                          ret);
4037
4038         return ret;
4039 }
4040
4041 static int
4042 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4043 {
4044         struct hns3_adapter *hns = dev->data->dev_private;
4045         struct hns3_hw *hw = &hns->hw;
4046         int ret;
4047
4048         /* If now in promiscuous mode, must remain in all_multicast mode. */
4049         if (dev->data->promiscuous)
4050                 return 0;
4051
4052         rte_spinlock_lock(&hw->lock);
4053         ret = hns3_set_promisc_mode(hw, false, false);
4054         rte_spinlock_unlock(&hw->lock);
4055         if (ret)
4056                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4057                          ret);
4058
4059         return ret;
4060 }
4061
4062 static int
4063 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4064 {
4065         struct hns3_hw *hw = &hns->hw;
4066         bool allmulti = hw->data->all_multicast ? true : false;
4067         int ret;
4068
4069         if (hw->data->promiscuous) {
4070                 ret = hns3_set_promisc_mode(hw, true, true);
4071                 if (ret)
4072                         hns3_err(hw, "failed to restore promiscuous mode, "
4073                                  "ret = %d", ret);
4074                 return ret;
4075         }
4076
4077         ret = hns3_set_promisc_mode(hw, false, allmulti);
4078         if (ret)
4079                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4080                          ret);
4081         return ret;
4082 }
4083
4084 static int
4085 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4086 {
4087         struct hns3_sfp_speed_cmd *resp;
4088         struct hns3_cmd_desc desc;
4089         int ret;
4090
4091         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4092         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4093         ret = hns3_cmd_send(hw, &desc, 1);
4094         if (ret == -EOPNOTSUPP) {
4095                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4096                 return ret;
4097         } else if (ret) {
4098                 hns3_err(hw, "get sfp speed failed %d", ret);
4099                 return ret;
4100         }
4101
4102         *speed = resp->sfp_speed;
4103
4104         return 0;
4105 }
4106
4107 static uint8_t
4108 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4109 {
4110         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4111                 duplex = ETH_LINK_FULL_DUPLEX;
4112
4113         return duplex;
4114 }
4115
4116 static int
4117 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4118 {
4119         struct hns3_mac *mac = &hw->mac;
4120         int ret;
4121
4122         duplex = hns3_check_speed_dup(duplex, speed);
4123         if (mac->link_speed == speed && mac->link_duplex == duplex)
4124                 return 0;
4125
4126         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4127         if (ret)
4128                 return ret;
4129
4130         mac->link_speed = speed;
4131         mac->link_duplex = duplex;
4132
4133         return 0;
4134 }
4135
4136 static int
4137 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4138 {
4139         struct hns3_adapter *hns = eth_dev->data->dev_private;
4140         struct hns3_hw *hw = &hns->hw;
4141         struct hns3_pf *pf = &hns->pf;
4142         uint32_t speed;
4143         int ret;
4144
4145         /* If IMP do not support get SFP/qSFP speed, return directly */
4146         if (!pf->support_sfp_query)
4147                 return 0;
4148
4149         ret = hns3_get_sfp_speed(hw, &speed);
4150         if (ret == -EOPNOTSUPP) {
4151                 pf->support_sfp_query = false;
4152                 return ret;
4153         } else if (ret)
4154                 return ret;
4155
4156         if (speed == ETH_SPEED_NUM_NONE)
4157                 return 0; /* do nothing if no SFP */
4158
4159         /* Config full duplex for SFP */
4160         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4161 }
4162
4163 static int
4164 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4165 {
4166         struct hns3_config_mac_mode_cmd *req;
4167         struct hns3_cmd_desc desc;
4168         uint32_t loop_en = 0;
4169         uint8_t val = 0;
4170         int ret;
4171
4172         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4173
4174         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4175         if (enable)
4176                 val = 1;
4177         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4178         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4179         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4180         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4181         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4182         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4183         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4184         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4185         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4186         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4187
4188         /*
4189          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4190          * when receiving frames. Otherwise, CRC will be stripped.
4191          */
4192         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4193                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4194         else
4195                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4196         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4197         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4198         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4199         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4200
4201         ret = hns3_cmd_send(hw, &desc, 1);
4202         if (ret)
4203                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4204
4205         return ret;
4206 }
4207
4208 static int
4209 hns3_get_mac_link_status(struct hns3_hw *hw)
4210 {
4211         struct hns3_link_status_cmd *req;
4212         struct hns3_cmd_desc desc;
4213         int link_status;
4214         int ret;
4215
4216         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4217         ret = hns3_cmd_send(hw, &desc, 1);
4218         if (ret) {
4219                 hns3_err(hw, "get link status cmd failed %d", ret);
4220                 return ETH_LINK_DOWN;
4221         }
4222
4223         req = (struct hns3_link_status_cmd *)desc.data;
4224         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4225
4226         return !!link_status;
4227 }
4228
4229 void
4230 hns3_update_link_status(struct hns3_hw *hw)
4231 {
4232         int state;
4233
4234         state = hns3_get_mac_link_status(hw);
4235         if (state != hw->mac.link_status) {
4236                 hw->mac.link_status = state;
4237                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4238         }
4239 }
4240
4241 static void
4242 hns3_service_handler(void *param)
4243 {
4244         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4245         struct hns3_adapter *hns = eth_dev->data->dev_private;
4246         struct hns3_hw *hw = &hns->hw;
4247
4248         if (!hns3_is_reset_pending(hns)) {
4249                 hns3_update_speed_duplex(eth_dev);
4250                 hns3_update_link_status(hw);
4251         } else
4252                 hns3_warn(hw, "Cancel the query when reset is pending");
4253
4254         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4255 }
4256
4257 static int
4258 hns3_init_hardware(struct hns3_adapter *hns)
4259 {
4260         struct hns3_hw *hw = &hns->hw;
4261         int ret;
4262
4263         ret = hns3_map_tqp(hw);
4264         if (ret) {
4265                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4266                 return ret;
4267         }
4268
4269         ret = hns3_init_umv_space(hw);
4270         if (ret) {
4271                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4272                 return ret;
4273         }
4274
4275         ret = hns3_mac_init(hw);
4276         if (ret) {
4277                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4278                 goto err_mac_init;
4279         }
4280
4281         ret = hns3_init_mgr_tbl(hw);
4282         if (ret) {
4283                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4284                 goto err_mac_init;
4285         }
4286
4287         ret = hns3_promisc_init(hw);
4288         if (ret) {
4289                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4290                              ret);
4291                 goto err_mac_init;
4292         }
4293
4294         ret = hns3_init_vlan_config(hns);
4295         if (ret) {
4296                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4297                 goto err_mac_init;
4298         }
4299
4300         ret = hns3_dcb_init(hw);
4301         if (ret) {
4302                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4303                 goto err_mac_init;
4304         }
4305
4306         ret = hns3_init_fd_config(hns);
4307         if (ret) {
4308                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4309                 goto err_mac_init;
4310         }
4311
4312         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4313         if (ret) {
4314                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4315                 goto err_mac_init;
4316         }
4317
4318         ret = hns3_config_gro(hw, false);
4319         if (ret) {
4320                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4321                 goto err_mac_init;
4322         }
4323
4324         /*
4325          * In the initialization clearing the all hardware mapping relationship
4326          * configurations between queues and interrupt vectors is needed, so
4327          * some error caused by the residual configurations, such as the
4328          * unexpected interrupt, can be avoid.
4329          */
4330         ret = hns3_init_ring_with_vector(hw);
4331         if (ret) {
4332                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4333                 goto err_mac_init;
4334         }
4335
4336         return 0;
4337
4338 err_mac_init:
4339         hns3_uninit_umv_space(hw);
4340         return ret;
4341 }
4342
4343 static int
4344 hns3_clear_hw(struct hns3_hw *hw)
4345 {
4346         struct hns3_cmd_desc desc;
4347         int ret;
4348
4349         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4350
4351         ret = hns3_cmd_send(hw, &desc, 1);
4352         if (ret && ret != -EOPNOTSUPP)
4353                 return ret;
4354
4355         return 0;
4356 }
4357
4358 static int
4359 hns3_init_pf(struct rte_eth_dev *eth_dev)
4360 {
4361         struct rte_device *dev = eth_dev->device;
4362         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4363         struct hns3_adapter *hns = eth_dev->data->dev_private;
4364         struct hns3_hw *hw = &hns->hw;
4365         int ret;
4366
4367         PMD_INIT_FUNC_TRACE();
4368
4369         /* Get hardware io base address from pcie BAR2 IO space */
4370         hw->io_base = pci_dev->mem_resource[2].addr;
4371
4372         /* Firmware command queue initialize */
4373         ret = hns3_cmd_init_queue(hw);
4374         if (ret) {
4375                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4376                 goto err_cmd_init_queue;
4377         }
4378
4379         hns3_clear_all_event_cause(hw);
4380
4381         /* Firmware command initialize */
4382         ret = hns3_cmd_init(hw);
4383         if (ret) {
4384                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4385                 goto err_cmd_init;
4386         }
4387
4388         /*
4389          * To ensure that the hardware environment is clean during
4390          * initialization, the driver actively clear the hardware environment
4391          * during initialization, including PF and corresponding VFs' vlan, mac,
4392          * flow table configurations, etc.
4393          */
4394         ret = hns3_clear_hw(hw);
4395         if (ret) {
4396                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4397                 goto err_cmd_init;
4398         }
4399
4400         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4401                                          hns3_interrupt_handler,
4402                                          eth_dev);
4403         if (ret) {
4404                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4405                 goto err_intr_callback_register;
4406         }
4407
4408         /* Enable interrupt */
4409         rte_intr_enable(&pci_dev->intr_handle);
4410         hns3_pf_enable_irq0(hw);
4411
4412         /* Get configuration */
4413         ret = hns3_get_configuration(hw);
4414         if (ret) {
4415                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4416                 goto err_get_config;
4417         }
4418
4419         ret = hns3_init_hardware(hns);
4420         if (ret) {
4421                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4422                 goto err_get_config;
4423         }
4424
4425         /* Initialize flow director filter list & hash */
4426         ret = hns3_fdir_filter_init(hns);
4427         if (ret) {
4428                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4429                 goto err_hw_init;
4430         }
4431
4432         hns3_set_default_rss_args(hw);
4433
4434         ret = hns3_enable_hw_error_intr(hns, true);
4435         if (ret) {
4436                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4437                              ret);
4438                 goto err_fdir;
4439         }
4440
4441         return 0;
4442
4443 err_fdir:
4444         hns3_fdir_filter_uninit(hns);
4445 err_hw_init:
4446         hns3_uninit_umv_space(hw);
4447
4448 err_get_config:
4449         hns3_pf_disable_irq0(hw);
4450         rte_intr_disable(&pci_dev->intr_handle);
4451         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4452                              eth_dev);
4453 err_intr_callback_register:
4454 err_cmd_init:
4455         hns3_cmd_uninit(hw);
4456         hns3_cmd_destroy_queue(hw);
4457 err_cmd_init_queue:
4458         hw->io_base = NULL;
4459
4460         return ret;
4461 }
4462
4463 static void
4464 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4465 {
4466         struct hns3_adapter *hns = eth_dev->data->dev_private;
4467         struct rte_device *dev = eth_dev->device;
4468         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4469         struct hns3_hw *hw = &hns->hw;
4470
4471         PMD_INIT_FUNC_TRACE();
4472
4473         hns3_enable_hw_error_intr(hns, false);
4474         hns3_rss_uninit(hns);
4475         (void)hns3_config_gro(hw, false);
4476         hns3_promisc_uninit(hw);
4477         hns3_fdir_filter_uninit(hns);
4478         hns3_uninit_umv_space(hw);
4479         hns3_pf_disable_irq0(hw);
4480         rte_intr_disable(&pci_dev->intr_handle);
4481         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4482                              eth_dev);
4483         hns3_cmd_uninit(hw);
4484         hns3_cmd_destroy_queue(hw);
4485         hw->io_base = NULL;
4486 }
4487
4488 static int
4489 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4490 {
4491         struct hns3_hw *hw = &hns->hw;
4492         int ret;
4493
4494         ret = hns3_dcb_cfg_update(hns);
4495         if (ret)
4496                 return ret;
4497
4498         /* Enable queues */
4499         ret = hns3_start_queues(hns, reset_queue);
4500         if (ret) {
4501                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4502                 return ret;
4503         }
4504
4505         /* Enable MAC */
4506         ret = hns3_cfg_mac_mode(hw, true);
4507         if (ret) {
4508                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4509                 goto err_config_mac_mode;
4510         }
4511         return 0;
4512
4513 err_config_mac_mode:
4514         hns3_stop_queues(hns, true);
4515         return ret;
4516 }
4517
4518 static int
4519 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4520 {
4521         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4522         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4523         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4524         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4525         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4526         uint32_t intr_vector;
4527         uint16_t q_id;
4528         int ret;
4529
4530         if (dev->data->dev_conf.intr_conf.rxq == 0)
4531                 return 0;
4532
4533         /* disable uio/vfio intr/eventfd mapping */
4534         rte_intr_disable(intr_handle);
4535
4536         /* check and configure queue intr-vector mapping */
4537         if (rte_intr_cap_multiple(intr_handle) ||
4538             !RTE_ETH_DEV_SRIOV(dev).active) {
4539                 intr_vector = hw->used_rx_queues;
4540                 /* creates event fd for each intr vector when MSIX is used */
4541                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4542                         return -EINVAL;
4543         }
4544         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4545                 intr_handle->intr_vec =
4546                         rte_zmalloc("intr_vec",
4547                                     hw->used_rx_queues * sizeof(int), 0);
4548                 if (intr_handle->intr_vec == NULL) {
4549                         hns3_err(hw, "Failed to allocate %d rx_queues"
4550                                      " intr_vec", hw->used_rx_queues);
4551                         ret = -ENOMEM;
4552                         goto alloc_intr_vec_error;
4553                 }
4554         }
4555
4556         if (rte_intr_allow_others(intr_handle)) {
4557                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4558                 base = RTE_INTR_VEC_RXTX_OFFSET;
4559         }
4560         if (rte_intr_dp_is_en(intr_handle)) {
4561                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4562                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4563                                                          HNS3_RING_TYPE_RX,
4564                                                          q_id);
4565                         if (ret)
4566                                 goto bind_vector_error;
4567                         intr_handle->intr_vec[q_id] = vec;
4568                         if (vec < base + intr_handle->nb_efd - 1)
4569                                 vec++;
4570                 }
4571         }
4572         rte_intr_enable(intr_handle);
4573         return 0;
4574
4575 bind_vector_error:
4576         rte_intr_efd_disable(intr_handle);
4577         if (intr_handle->intr_vec) {
4578                 free(intr_handle->intr_vec);
4579                 intr_handle->intr_vec = NULL;
4580         }
4581         return ret;
4582 alloc_intr_vec_error:
4583         rte_intr_efd_disable(intr_handle);
4584         return ret;
4585 }
4586
4587 static int
4588 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4589 {
4590         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4591         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4592         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4593         uint16_t q_id;
4594         int ret;
4595
4596         if (dev->data->dev_conf.intr_conf.rxq == 0)
4597                 return 0;
4598
4599         if (rte_intr_dp_is_en(intr_handle)) {
4600                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4601                         ret = hns3_bind_ring_with_vector(hw,
4602                                         intr_handle->intr_vec[q_id], true,
4603                                         HNS3_RING_TYPE_RX, q_id);
4604                         if (ret)
4605                                 return ret;
4606                 }
4607         }
4608
4609         return 0;
4610 }
4611
4612 static void
4613 hns3_restore_filter(struct rte_eth_dev *dev)
4614 {
4615         hns3_restore_rss_filter(dev);
4616 }
4617
4618 static int
4619 hns3_dev_start(struct rte_eth_dev *dev)
4620 {
4621         struct hns3_adapter *hns = dev->data->dev_private;
4622         struct hns3_hw *hw = &hns->hw;
4623         int ret;
4624
4625         PMD_INIT_FUNC_TRACE();
4626         if (rte_atomic16_read(&hw->reset.resetting))
4627                 return -EBUSY;
4628
4629         rte_spinlock_lock(&hw->lock);
4630         hw->adapter_state = HNS3_NIC_STARTING;
4631
4632         ret = hns3_do_start(hns, true);
4633         if (ret) {
4634                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4635                 rte_spinlock_unlock(&hw->lock);
4636                 return ret;
4637         }
4638         ret = hns3_map_rx_interrupt(dev);
4639         if (ret) {
4640                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4641                 rte_spinlock_unlock(&hw->lock);
4642                 return ret;
4643         }
4644
4645         hw->adapter_state = HNS3_NIC_STARTED;
4646         rte_spinlock_unlock(&hw->lock);
4647
4648         hns3_set_rxtx_function(dev);
4649         hns3_mp_req_start_rxtx(dev);
4650         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4651
4652         hns3_restore_filter(dev);
4653
4654         /* Enable interrupt of all rx queues before enabling queues */
4655         hns3_dev_all_rx_queue_intr_enable(hw, true);
4656         /*
4657          * When finished the initialization, enable queues to receive/transmit
4658          * packets.
4659          */
4660         hns3_enable_all_queues(hw, true);
4661
4662         hns3_info(hw, "hns3 dev start successful!");
4663         return 0;
4664 }
4665
4666 static int
4667 hns3_do_stop(struct hns3_adapter *hns)
4668 {
4669         struct hns3_hw *hw = &hns->hw;
4670         bool reset_queue;
4671         int ret;
4672
4673         ret = hns3_cfg_mac_mode(hw, false);
4674         if (ret)
4675                 return ret;
4676         hw->mac.link_status = ETH_LINK_DOWN;
4677
4678         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4679                 hns3_configure_all_mac_addr(hns, true);
4680                 reset_queue = true;
4681         } else
4682                 reset_queue = false;
4683         hw->mac.default_addr_setted = false;
4684         return hns3_stop_queues(hns, reset_queue);
4685 }
4686
4687 static void
4688 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4689 {
4690         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4691         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4692         struct hns3_adapter *hns = dev->data->dev_private;
4693         struct hns3_hw *hw = &hns->hw;
4694         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4695         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4696         uint16_t q_id;
4697
4698         if (dev->data->dev_conf.intr_conf.rxq == 0)
4699                 return;
4700
4701         /* unmap the ring with vector */
4702         if (rte_intr_allow_others(intr_handle)) {
4703                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4704                 base = RTE_INTR_VEC_RXTX_OFFSET;
4705         }
4706         if (rte_intr_dp_is_en(intr_handle)) {
4707                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4708                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4709                                                          HNS3_RING_TYPE_RX,
4710                                                          q_id);
4711                         if (vec < base + intr_handle->nb_efd - 1)
4712                                 vec++;
4713                 }
4714         }
4715         /* Clean datapath event and queue/vec mapping */
4716         rte_intr_efd_disable(intr_handle);
4717         if (intr_handle->intr_vec) {
4718                 rte_free(intr_handle->intr_vec);
4719                 intr_handle->intr_vec = NULL;
4720         }
4721 }
4722
4723 static void
4724 hns3_dev_stop(struct rte_eth_dev *dev)
4725 {
4726         struct hns3_adapter *hns = dev->data->dev_private;
4727         struct hns3_hw *hw = &hns->hw;
4728
4729         PMD_INIT_FUNC_TRACE();
4730
4731         hw->adapter_state = HNS3_NIC_STOPPING;
4732         hns3_set_rxtx_function(dev);
4733         rte_wmb();
4734         /* Disable datapath on secondary process. */
4735         hns3_mp_req_stop_rxtx(dev);
4736         /* Prevent crashes when queues are still in use. */
4737         rte_delay_ms(hw->tqps_num);
4738
4739         rte_spinlock_lock(&hw->lock);
4740         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4741                 hns3_do_stop(hns);
4742                 hns3_unmap_rx_interrupt(dev);
4743                 hns3_dev_release_mbufs(hns);
4744                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4745         }
4746         rte_eal_alarm_cancel(hns3_service_handler, dev);
4747         rte_spinlock_unlock(&hw->lock);
4748 }
4749
4750 static void
4751 hns3_dev_close(struct rte_eth_dev *eth_dev)
4752 {
4753         struct hns3_adapter *hns = eth_dev->data->dev_private;
4754         struct hns3_hw *hw = &hns->hw;
4755
4756         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4757                 rte_free(eth_dev->process_private);
4758                 eth_dev->process_private = NULL;
4759                 return;
4760         }
4761
4762         if (hw->adapter_state == HNS3_NIC_STARTED)
4763                 hns3_dev_stop(eth_dev);
4764
4765         hw->adapter_state = HNS3_NIC_CLOSING;
4766         hns3_reset_abort(hns);
4767         hw->adapter_state = HNS3_NIC_CLOSED;
4768
4769         hns3_configure_all_mc_mac_addr(hns, true);
4770         hns3_remove_all_vlan_table(hns);
4771         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4772         hns3_uninit_pf(eth_dev);
4773         hns3_free_all_queues(eth_dev);
4774         rte_free(hw->reset.wait_data);
4775         rte_free(eth_dev->process_private);
4776         eth_dev->process_private = NULL;
4777         hns3_mp_uninit_primary();
4778         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4779 }
4780
4781 static int
4782 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4783 {
4784         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4785         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4786
4787         fc_conf->pause_time = pf->pause_time;
4788
4789         /* return fc current mode */
4790         switch (hw->current_mode) {
4791         case HNS3_FC_FULL:
4792                 fc_conf->mode = RTE_FC_FULL;
4793                 break;
4794         case HNS3_FC_TX_PAUSE:
4795                 fc_conf->mode = RTE_FC_TX_PAUSE;
4796                 break;
4797         case HNS3_FC_RX_PAUSE:
4798                 fc_conf->mode = RTE_FC_RX_PAUSE;
4799                 break;
4800         case HNS3_FC_NONE:
4801         default:
4802                 fc_conf->mode = RTE_FC_NONE;
4803                 break;
4804         }
4805
4806         return 0;
4807 }
4808
4809 static void
4810 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4811 {
4812         switch (mode) {
4813         case RTE_FC_NONE:
4814                 hw->requested_mode = HNS3_FC_NONE;
4815                 break;
4816         case RTE_FC_RX_PAUSE:
4817                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4818                 break;
4819         case RTE_FC_TX_PAUSE:
4820                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4821                 break;
4822         case RTE_FC_FULL:
4823                 hw->requested_mode = HNS3_FC_FULL;
4824                 break;
4825         default:
4826                 hw->requested_mode = HNS3_FC_NONE;
4827                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4828                           "configured to RTE_FC_NONE", mode);
4829                 break;
4830         }
4831 }
4832
4833 static int
4834 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4835 {
4836         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4837         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4838         int ret;
4839
4840         if (fc_conf->high_water || fc_conf->low_water ||
4841             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4842                 hns3_err(hw, "Unsupported flow control settings specified, "
4843                          "high_water(%u), low_water(%u), send_xon(%u) and "
4844                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4845                          fc_conf->high_water, fc_conf->low_water,
4846                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4847                 return -EINVAL;
4848         }
4849         if (fc_conf->autoneg) {
4850                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4851                 return -EINVAL;
4852         }
4853         if (!fc_conf->pause_time) {
4854                 hns3_err(hw, "Invalid pause time %d setting.",
4855                          fc_conf->pause_time);
4856                 return -EINVAL;
4857         }
4858
4859         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4860             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4861                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4862                          "current_fc_status = %d", hw->current_fc_status);
4863                 return -EOPNOTSUPP;
4864         }
4865
4866         hns3_get_fc_mode(hw, fc_conf->mode);
4867         if (hw->requested_mode == hw->current_mode &&
4868             pf->pause_time == fc_conf->pause_time)
4869                 return 0;
4870
4871         rte_spinlock_lock(&hw->lock);
4872         ret = hns3_fc_enable(dev, fc_conf);
4873         rte_spinlock_unlock(&hw->lock);
4874
4875         return ret;
4876 }
4877
4878 static int
4879 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4880                             struct rte_eth_pfc_conf *pfc_conf)
4881 {
4882         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4883         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4884         uint8_t priority;
4885         int ret;
4886
4887         if (!hns3_dev_dcb_supported(hw)) {
4888                 hns3_err(hw, "This port does not support dcb configurations.");
4889                 return -EOPNOTSUPP;
4890         }
4891
4892         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4893             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4894                 hns3_err(hw, "Unsupported flow control settings specified, "
4895                          "high_water(%u), low_water(%u), send_xon(%u) and "
4896                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4897                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4898                          pfc_conf->fc.send_xon,
4899                          pfc_conf->fc.mac_ctrl_frame_fwd);
4900                 return -EINVAL;
4901         }
4902         if (pfc_conf->fc.autoneg) {
4903                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4904                 return -EINVAL;
4905         }
4906         if (pfc_conf->fc.pause_time == 0) {
4907                 hns3_err(hw, "Invalid pause time %d setting.",
4908                          pfc_conf->fc.pause_time);
4909                 return -EINVAL;
4910         }
4911
4912         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4913             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4914                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4915                              "current_fc_status = %d", hw->current_fc_status);
4916                 return -EOPNOTSUPP;
4917         }
4918
4919         priority = pfc_conf->priority;
4920         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4921         if (hw->dcb_info.pfc_en & BIT(priority) &&
4922             hw->requested_mode == hw->current_mode &&
4923             pfc_conf->fc.pause_time == pf->pause_time)
4924                 return 0;
4925
4926         rte_spinlock_lock(&hw->lock);
4927         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4928         rte_spinlock_unlock(&hw->lock);
4929
4930         return ret;
4931 }
4932
4933 static int
4934 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4935 {
4936         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4937         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4938         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4939         int i;
4940
4941         rte_spinlock_lock(&hw->lock);
4942         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4943                 dcb_info->nb_tcs = pf->local_max_tc;
4944         else
4945                 dcb_info->nb_tcs = 1;
4946
4947         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4948                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4949         for (i = 0; i < dcb_info->nb_tcs; i++)
4950                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4951
4952         for (i = 0; i < hw->num_tc; i++) {
4953                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4954                 dcb_info->tc_queue.tc_txq[0][i].base =
4955                                                 hw->tc_queue[i].tqp_offset;
4956                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4957                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4958                                                 hw->tc_queue[i].tqp_count;
4959         }
4960         rte_spinlock_unlock(&hw->lock);
4961
4962         return 0;
4963 }
4964
4965 static int
4966 hns3_reinit_dev(struct hns3_adapter *hns)
4967 {
4968         struct hns3_hw *hw = &hns->hw;
4969         int ret;
4970
4971         ret = hns3_cmd_init(hw);
4972         if (ret) {
4973                 hns3_err(hw, "Failed to init cmd: %d", ret);
4974                 return ret;
4975         }
4976
4977         ret = hns3_reset_all_queues(hns);
4978         if (ret) {
4979                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4980                 return ret;
4981         }
4982
4983         ret = hns3_init_hardware(hns);
4984         if (ret) {
4985                 hns3_err(hw, "Failed to init hardware: %d", ret);
4986                 return ret;
4987         }
4988
4989         ret = hns3_enable_hw_error_intr(hns, true);
4990         if (ret) {
4991                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4992                              ret);
4993                 return ret;
4994         }
4995         hns3_info(hw, "Reset done, driver initialization finished.");
4996
4997         return 0;
4998 }
4999
5000 static bool
5001 is_pf_reset_done(struct hns3_hw *hw)
5002 {
5003         uint32_t val, reg, reg_bit;
5004
5005         switch (hw->reset.level) {
5006         case HNS3_IMP_RESET:
5007                 reg = HNS3_GLOBAL_RESET_REG;
5008                 reg_bit = HNS3_IMP_RESET_BIT;
5009                 break;
5010         case HNS3_GLOBAL_RESET:
5011                 reg = HNS3_GLOBAL_RESET_REG;
5012                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5013                 break;
5014         case HNS3_FUNC_RESET:
5015                 reg = HNS3_FUN_RST_ING;
5016                 reg_bit = HNS3_FUN_RST_ING_B;
5017                 break;
5018         case HNS3_FLR_RESET:
5019         default:
5020                 hns3_err(hw, "Wait for unsupported reset level: %d",
5021                          hw->reset.level);
5022                 return true;
5023         }
5024         val = hns3_read_dev(hw, reg);
5025         if (hns3_get_bit(val, reg_bit))
5026                 return false;
5027         else
5028                 return true;
5029 }
5030
5031 bool
5032 hns3_is_reset_pending(struct hns3_adapter *hns)
5033 {
5034         struct hns3_hw *hw = &hns->hw;
5035         enum hns3_reset_level reset;
5036
5037         hns3_check_event_cause(hns, NULL);
5038         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5039         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5040                 hns3_warn(hw, "High level reset %d is pending", reset);
5041                 return true;
5042         }
5043         reset = hns3_get_reset_level(hns, &hw->reset.request);
5044         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5045                 hns3_warn(hw, "High level reset %d is request", reset);
5046                 return true;
5047         }
5048         return false;
5049 }
5050
5051 static int
5052 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5053 {
5054         struct hns3_hw *hw = &hns->hw;
5055         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5056         struct timeval tv;
5057
5058         if (wait_data->result == HNS3_WAIT_SUCCESS)
5059                 return 0;
5060         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5061                 gettimeofday(&tv, NULL);
5062                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5063                           tv.tv_sec, tv.tv_usec);
5064                 return -ETIME;
5065         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5066                 return -EAGAIN;
5067
5068         wait_data->hns = hns;
5069         wait_data->check_completion = is_pf_reset_done;
5070         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5071                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5072         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5073         wait_data->count = HNS3_RESET_WAIT_CNT;
5074         wait_data->result = HNS3_WAIT_REQUEST;
5075         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5076         return -EAGAIN;
5077 }
5078
5079 static int
5080 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5081 {
5082         struct hns3_cmd_desc desc;
5083         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5084
5085         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5086         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5087         req->fun_reset_vfid = func_id;
5088
5089         return hns3_cmd_send(hw, &desc, 1);
5090 }
5091
5092 static int
5093 hns3_imp_reset_cmd(struct hns3_hw *hw)
5094 {
5095         struct hns3_cmd_desc desc;
5096
5097         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5098         desc.data[0] = 0xeedd;
5099
5100         return hns3_cmd_send(hw, &desc, 1);
5101 }
5102
5103 static void
5104 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5105 {
5106         struct hns3_hw *hw = &hns->hw;
5107         struct timeval tv;
5108         uint32_t val;
5109
5110         gettimeofday(&tv, NULL);
5111         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5112             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5113                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5114                           tv.tv_sec, tv.tv_usec);
5115                 return;
5116         }
5117
5118         switch (reset_level) {
5119         case HNS3_IMP_RESET:
5120                 hns3_imp_reset_cmd(hw);
5121                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5122                           tv.tv_sec, tv.tv_usec);
5123                 break;
5124         case HNS3_GLOBAL_RESET:
5125                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5126                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5127                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5128                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5129                           tv.tv_sec, tv.tv_usec);
5130                 break;
5131         case HNS3_FUNC_RESET:
5132                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5133                           tv.tv_sec, tv.tv_usec);
5134                 /* schedule again to check later */
5135                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5136                 hns3_schedule_reset(hns);
5137                 break;
5138         default:
5139                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5140                 return;
5141         }
5142         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5143 }
5144
5145 static enum hns3_reset_level
5146 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5147 {
5148         struct hns3_hw *hw = &hns->hw;
5149         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5150
5151         /* Return the highest priority reset level amongst all */
5152         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5153                 reset_level = HNS3_IMP_RESET;
5154         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5155                 reset_level = HNS3_GLOBAL_RESET;
5156         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5157                 reset_level = HNS3_FUNC_RESET;
5158         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5159                 reset_level = HNS3_FLR_RESET;
5160
5161         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5162                 return HNS3_NONE_RESET;
5163
5164         return reset_level;
5165 }
5166
5167 static int
5168 hns3_prepare_reset(struct hns3_adapter *hns)
5169 {
5170         struct hns3_hw *hw = &hns->hw;
5171         uint32_t reg_val;
5172         int ret;
5173
5174         switch (hw->reset.level) {
5175         case HNS3_FUNC_RESET:
5176                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5177                 if (ret)
5178                         return ret;
5179
5180                 /*
5181                  * After performaning pf reset, it is not necessary to do the
5182                  * mailbox handling or send any command to firmware, because
5183                  * any mailbox handling or command to firmware is only valid
5184                  * after hns3_cmd_init is called.
5185                  */
5186                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5187                 hw->reset.stats.request_cnt++;
5188                 break;
5189         case HNS3_IMP_RESET:
5190                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5191                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5192                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5193                 break;
5194         default:
5195                 break;
5196         }
5197         return 0;
5198 }
5199
5200 static int
5201 hns3_set_rst_done(struct hns3_hw *hw)
5202 {
5203         struct hns3_pf_rst_done_cmd *req;
5204         struct hns3_cmd_desc desc;
5205
5206         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5207         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5208         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5209         return hns3_cmd_send(hw, &desc, 1);
5210 }
5211
5212 static int
5213 hns3_stop_service(struct hns3_adapter *hns)
5214 {
5215         struct hns3_hw *hw = &hns->hw;
5216         struct rte_eth_dev *eth_dev;
5217
5218         eth_dev = &rte_eth_devices[hw->data->port_id];
5219         if (hw->adapter_state == HNS3_NIC_STARTED)
5220                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5221         hw->mac.link_status = ETH_LINK_DOWN;
5222
5223         hns3_set_rxtx_function(eth_dev);
5224         rte_wmb();
5225         /* Disable datapath on secondary process. */
5226         hns3_mp_req_stop_rxtx(eth_dev);
5227         rte_delay_ms(hw->tqps_num);
5228
5229         rte_spinlock_lock(&hw->lock);
5230         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5231             hw->adapter_state == HNS3_NIC_STOPPING) {
5232                 hns3_do_stop(hns);
5233                 hw->reset.mbuf_deferred_free = true;
5234         } else
5235                 hw->reset.mbuf_deferred_free = false;
5236
5237         /*
5238          * It is cumbersome for hardware to pick-and-choose entries for deletion
5239          * from table space. Hence, for function reset software intervention is
5240          * required to delete the entries
5241          */
5242         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5243                 hns3_configure_all_mc_mac_addr(hns, true);
5244         rte_spinlock_unlock(&hw->lock);
5245
5246         return 0;
5247 }
5248
5249 static int
5250 hns3_start_service(struct hns3_adapter *hns)
5251 {
5252         struct hns3_hw *hw = &hns->hw;
5253         struct rte_eth_dev *eth_dev;
5254
5255         if (hw->reset.level == HNS3_IMP_RESET ||
5256             hw->reset.level == HNS3_GLOBAL_RESET)
5257                 hns3_set_rst_done(hw);
5258         eth_dev = &rte_eth_devices[hw->data->port_id];
5259         hns3_set_rxtx_function(eth_dev);
5260         hns3_mp_req_start_rxtx(eth_dev);
5261         if (hw->adapter_state == HNS3_NIC_STARTED) {
5262                 hns3_service_handler(eth_dev);
5263
5264                 /* Enable interrupt of all rx queues before enabling queues */
5265                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5266                 /*
5267                  * When finished the initialization, enable queues to receive
5268                  * and transmit packets.
5269                  */
5270                 hns3_enable_all_queues(hw, true);
5271         }
5272
5273         return 0;
5274 }
5275
5276 static int
5277 hns3_restore_conf(struct hns3_adapter *hns)
5278 {
5279         struct hns3_hw *hw = &hns->hw;
5280         int ret;
5281
5282         ret = hns3_configure_all_mac_addr(hns, false);
5283         if (ret)
5284                 return ret;
5285
5286         ret = hns3_configure_all_mc_mac_addr(hns, false);
5287         if (ret)
5288                 goto err_mc_mac;
5289
5290         ret = hns3_dev_promisc_restore(hns);
5291         if (ret)
5292                 goto err_promisc;
5293
5294         ret = hns3_restore_vlan_table(hns);
5295         if (ret)
5296                 goto err_promisc;
5297
5298         ret = hns3_restore_vlan_conf(hns);
5299         if (ret)
5300                 goto err_promisc;
5301
5302         ret = hns3_restore_all_fdir_filter(hns);
5303         if (ret)
5304                 goto err_promisc;
5305
5306         ret = hns3_restore_rx_interrupt(hw);
5307         if (ret)
5308                 goto err_promisc;
5309
5310         ret = hns3_restore_gro_conf(hw);
5311         if (ret)
5312                 goto err_promisc;
5313
5314         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5315                 ret = hns3_do_start(hns, false);
5316                 if (ret)
5317                         goto err_promisc;
5318                 hns3_info(hw, "hns3 dev restart successful!");
5319         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5320                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5321         return 0;
5322
5323 err_promisc:
5324         hns3_configure_all_mc_mac_addr(hns, true);
5325 err_mc_mac:
5326         hns3_configure_all_mac_addr(hns, true);
5327         return ret;
5328 }
5329
5330 static void
5331 hns3_reset_service(void *param)
5332 {
5333         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5334         struct hns3_hw *hw = &hns->hw;
5335         enum hns3_reset_level reset_level;
5336         struct timeval tv_delta;
5337         struct timeval tv_start;
5338         struct timeval tv;
5339         uint64_t msec;
5340         int ret;
5341
5342         /*
5343          * The interrupt is not triggered within the delay time.
5344          * The interrupt may have been lost. It is necessary to handle
5345          * the interrupt to recover from the error.
5346          */
5347         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5348                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5349                 hns3_err(hw, "Handling interrupts in delayed tasks");
5350                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5351                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5352                 if (reset_level == HNS3_NONE_RESET) {
5353                         hns3_err(hw, "No reset level is set, try IMP reset");
5354                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5355                 }
5356         }
5357         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5358
5359         /*
5360          * Check if there is any ongoing reset in the hardware. This status can
5361          * be checked from reset_pending. If there is then, we need to wait for
5362          * hardware to complete reset.
5363          *    a. If we are able to figure out in reasonable time that hardware
5364          *       has fully resetted then, we can proceed with driver, client
5365          *       reset.
5366          *    b. else, we can come back later to check this status so re-sched
5367          *       now.
5368          */
5369         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5370         if (reset_level != HNS3_NONE_RESET) {
5371                 gettimeofday(&tv_start, NULL);
5372                 ret = hns3_reset_process(hns, reset_level);
5373                 gettimeofday(&tv, NULL);
5374                 timersub(&tv, &tv_start, &tv_delta);
5375                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5376                        tv_delta.tv_usec / USEC_PER_MSEC;
5377                 if (msec > HNS3_RESET_PROCESS_MS)
5378                         hns3_err(hw, "%d handle long time delta %" PRIx64
5379                                      " ms time=%ld.%.6ld",
5380                                  hw->reset.level, msec,
5381                                  tv.tv_sec, tv.tv_usec);
5382                 if (ret == -EAGAIN)
5383                         return;
5384         }
5385
5386         /* Check if we got any *new* reset requests to be honored */
5387         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5388         if (reset_level != HNS3_NONE_RESET)
5389                 hns3_msix_process(hns, reset_level);
5390 }
5391
5392 static const struct eth_dev_ops hns3_eth_dev_ops = {
5393         .dev_start          = hns3_dev_start,
5394         .dev_stop           = hns3_dev_stop,
5395         .dev_close          = hns3_dev_close,
5396         .promiscuous_enable = hns3_dev_promiscuous_enable,
5397         .promiscuous_disable = hns3_dev_promiscuous_disable,
5398         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5399         .allmulticast_disable = hns3_dev_allmulticast_disable,
5400         .mtu_set            = hns3_dev_mtu_set,
5401         .stats_get          = hns3_stats_get,
5402         .stats_reset        = hns3_stats_reset,
5403         .xstats_get         = hns3_dev_xstats_get,
5404         .xstats_get_names   = hns3_dev_xstats_get_names,
5405         .xstats_reset       = hns3_dev_xstats_reset,
5406         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5407         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5408         .dev_infos_get          = hns3_dev_infos_get,
5409         .fw_version_get         = hns3_fw_version_get,
5410         .rx_queue_setup         = hns3_rx_queue_setup,
5411         .tx_queue_setup         = hns3_tx_queue_setup,
5412         .rx_queue_release       = hns3_dev_rx_queue_release,
5413         .tx_queue_release       = hns3_dev_tx_queue_release,
5414         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5415         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5416         .dev_configure          = hns3_dev_configure,
5417         .flow_ctrl_get          = hns3_flow_ctrl_get,
5418         .flow_ctrl_set          = hns3_flow_ctrl_set,
5419         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5420         .mac_addr_add           = hns3_add_mac_addr,
5421         .mac_addr_remove        = hns3_remove_mac_addr,
5422         .mac_addr_set           = hns3_set_default_mac_addr,
5423         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5424         .link_update            = hns3_dev_link_update,
5425         .rss_hash_update        = hns3_dev_rss_hash_update,
5426         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5427         .reta_update            = hns3_dev_rss_reta_update,
5428         .reta_query             = hns3_dev_rss_reta_query,
5429         .filter_ctrl            = hns3_dev_filter_ctrl,
5430         .vlan_filter_set        = hns3_vlan_filter_set,
5431         .vlan_tpid_set          = hns3_vlan_tpid_set,
5432         .vlan_offload_set       = hns3_vlan_offload_set,
5433         .vlan_pvid_set          = hns3_vlan_pvid_set,
5434         .get_reg                = hns3_get_regs,
5435         .get_dcb_info           = hns3_get_dcb_info,
5436         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5437 };
5438
5439 static const struct hns3_reset_ops hns3_reset_ops = {
5440         .reset_service       = hns3_reset_service,
5441         .stop_service        = hns3_stop_service,
5442         .prepare_reset       = hns3_prepare_reset,
5443         .wait_hardware_ready = hns3_wait_hardware_ready,
5444         .reinit_dev          = hns3_reinit_dev,
5445         .restore_conf        = hns3_restore_conf,
5446         .start_service       = hns3_start_service,
5447 };
5448
5449 static int
5450 hns3_dev_init(struct rte_eth_dev *eth_dev)
5451 {
5452         struct hns3_adapter *hns = eth_dev->data->dev_private;
5453         struct hns3_hw *hw = &hns->hw;
5454         int ret;
5455
5456         PMD_INIT_FUNC_TRACE();
5457
5458         eth_dev->process_private = (struct hns3_process_private *)
5459             rte_zmalloc_socket("hns3_filter_list",
5460                                sizeof(struct hns3_process_private),
5461                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5462         if (eth_dev->process_private == NULL) {
5463                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5464                 return -ENOMEM;
5465         }
5466         /* initialize flow filter lists */
5467         hns3_filterlist_init(eth_dev);
5468
5469         hns3_set_rxtx_function(eth_dev);
5470         eth_dev->dev_ops = &hns3_eth_dev_ops;
5471         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5472                 ret = hns3_mp_init_secondary();
5473                 if (ret) {
5474                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
5475                                      "process, ret = %d", ret);
5476                         goto err_mp_init_secondary;
5477                 }
5478
5479                 hw->secondary_cnt++;
5480                 return 0;
5481         }
5482
5483         ret = hns3_mp_init_primary();
5484         if (ret) {
5485                 PMD_INIT_LOG(ERR,
5486                              "Failed to init for primary process, ret = %d",
5487                              ret);
5488                 goto err_mp_init_primary;
5489         }
5490
5491         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5492         hns->is_vf = false;
5493         hw->data = eth_dev->data;
5494
5495         /*
5496          * Set default max packet size according to the mtu
5497          * default vale in DPDK frame.
5498          */
5499         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5500
5501         ret = hns3_reset_init(hw);
5502         if (ret)
5503                 goto err_init_reset;
5504         hw->reset.ops = &hns3_reset_ops;
5505
5506         ret = hns3_init_pf(eth_dev);
5507         if (ret) {
5508                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5509                 goto err_init_pf;
5510         }
5511
5512         /* Allocate memory for storing MAC addresses */
5513         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5514                                                sizeof(struct rte_ether_addr) *
5515                                                HNS3_UC_MACADDR_NUM, 0);
5516         if (eth_dev->data->mac_addrs == NULL) {
5517                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5518                              "to store MAC addresses",
5519                              sizeof(struct rte_ether_addr) *
5520                              HNS3_UC_MACADDR_NUM);
5521                 ret = -ENOMEM;
5522                 goto err_rte_zmalloc;
5523         }
5524
5525         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5526                             &eth_dev->data->mac_addrs[0]);
5527
5528         hw->adapter_state = HNS3_NIC_INITIALIZED;
5529         /*
5530          * Pass the information to the rte_eth_dev_close() that it should also
5531          * release the private port resources.
5532          */
5533         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5534
5535         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5536                 hns3_err(hw, "Reschedule reset service after dev_init");
5537                 hns3_schedule_reset(hns);
5538         } else {
5539                 /* IMP will wait ready flag before reset */
5540                 hns3_notify_reset_ready(hw, false);
5541         }
5542
5543         hns3_info(hw, "hns3 dev initialization successful!");
5544         return 0;
5545
5546 err_rte_zmalloc:
5547         hns3_uninit_pf(eth_dev);
5548
5549 err_init_pf:
5550         rte_free(hw->reset.wait_data);
5551
5552 err_init_reset:
5553         hns3_mp_uninit_primary();
5554
5555 err_mp_init_primary:
5556 err_mp_init_secondary:
5557         eth_dev->dev_ops = NULL;
5558         eth_dev->rx_pkt_burst = NULL;
5559         eth_dev->tx_pkt_burst = NULL;
5560         eth_dev->tx_pkt_prepare = NULL;
5561         rte_free(eth_dev->process_private);
5562         eth_dev->process_private = NULL;
5563         return ret;
5564 }
5565
5566 static int
5567 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5568 {
5569         struct hns3_adapter *hns = eth_dev->data->dev_private;
5570         struct hns3_hw *hw = &hns->hw;
5571
5572         PMD_INIT_FUNC_TRACE();
5573
5574         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5575                 return -EPERM;
5576
5577         eth_dev->dev_ops = NULL;
5578         eth_dev->rx_pkt_burst = NULL;
5579         eth_dev->tx_pkt_burst = NULL;
5580         eth_dev->tx_pkt_prepare = NULL;
5581         if (hw->adapter_state < HNS3_NIC_CLOSING)
5582                 hns3_dev_close(eth_dev);
5583
5584         hw->adapter_state = HNS3_NIC_REMOVED;
5585         return 0;
5586 }
5587
5588 static int
5589 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5590                    struct rte_pci_device *pci_dev)
5591 {
5592         return rte_eth_dev_pci_generic_probe(pci_dev,
5593                                              sizeof(struct hns3_adapter),
5594                                              hns3_dev_init);
5595 }
5596
5597 static int
5598 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5599 {
5600         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5601 }
5602
5603 static const struct rte_pci_id pci_id_hns3_map[] = {
5604         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5605         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5606         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5607         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5608         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5609         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
5610         { .vendor_id = 0, /* sentinel */ },
5611 };
5612
5613 static struct rte_pci_driver rte_hns3_pmd = {
5614         .id_table = pci_id_hns3_map,
5615         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5616         .probe = eth_hns3_pci_probe,
5617         .remove = eth_hns3_pci_remove,
5618 };
5619
5620 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5621 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5622 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5623 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
5624 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);