drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static void
  83 hns3_pf_disable_irq0(struct hns3_hw *hw)
  84 {
  85         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  86 }
  87
  88 static void
  89 hns3_pf_enable_irq0(struct hns3_hw *hw)
  90 {
  91         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  92 }
  93
  94 static enum hns3_evt_cause
  95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  96 {
  97         struct hns3_hw *hw = &hns->hw;
  98         uint32_t vector0_int_stats;
  99         uint32_t cmdq_src_val;
 100         uint32_t val;
 101         enum hns3_evt_cause ret;
 102
 103         /* fetch the events from their corresponding regs */
 104         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 105         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 106
 107         /*
 108          * Assumption: If by any chance reset and mailbox events are reported
 109          * together then we will only process reset event and defer the
 110          * processing of the mailbox events. Since, we would have not cleared
 111          * RX CMDQ event this time we would receive again another interrupt
 112          * from H/W just for the mailbox.
 113          */
 114         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 115                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 116                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 117                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 118                 if (clearval) {
 119                         hw->reset.stats.imp_cnt++;
 120                         hns3_warn(hw, "IMP reset detected, clear reset status");
 121                 } else {
 122                         hns3_schedule_delayed_reset(hns);
 123                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 124                 }
 125
 126                 ret = HNS3_VECTOR0_EVENT_RST;
 127                 goto out;
 128         }
 129
 130         /* Global reset */
 131         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 132                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 133                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 134                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 135                 if (clearval) {
 136                         hw->reset.stats.global_cnt++;
 137                         hns3_warn(hw, "Global reset detected, clear reset status");
 138                 } else {
 139                         hns3_schedule_delayed_reset(hns);
 140                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 141                 }
 142
 143                 ret = HNS3_VECTOR0_EVENT_RST;
 144                 goto out;
 145         }
 146
 147         /* check for vector0 msix event source */
 148         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 149                 val = vector0_int_stats;
 150                 ret = HNS3_VECTOR0_EVENT_ERR;
 151                 goto out;
 152         }
 153
 154         /* check for vector0 mailbox(=CMDQ RX) event source */
 155         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 156                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 157                 val = cmdq_src_val;
 158                 ret = HNS3_VECTOR0_EVENT_MBX;
 159                 goto out;
 160         }
 161
 162         if (clearval && (vector0_int_stats || cmdq_src_val))
 163                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 164                           vector0_int_stats, cmdq_src_val);
 165         val = vector0_int_stats;
 166         ret = HNS3_VECTOR0_EVENT_OTHER;
 167 out:
 168
 169         if (clearval)
 170                 *clearval = val;
 171         return ret;
 172 }
 173
 174 static void
 175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 176 {
 177         if (event_type == HNS3_VECTOR0_EVENT_RST)
 178                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 179         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 180                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 181 }
 182
 183 static void
 184 hns3_clear_all_event_cause(struct hns3_hw *hw)
 185 {
 186         uint32_t vector0_int_stats;
 187         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 188
 189         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 190                 hns3_warn(hw, "Probe during IMP reset interrupt");
 191
 192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 193                 hns3_warn(hw, "Probe during Global reset interrupt");
 194
 195         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 196                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 197                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 198                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 199         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 200 }
 201
 202 static void
 203 hns3_interrupt_handler(void *param)
 204 {
 205         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 206         struct hns3_adapter *hns = dev->data->dev_private;
 207         struct hns3_hw *hw = &hns->hw;
 208         enum hns3_evt_cause event_cause;
 209         uint32_t clearval = 0;
 210
 211         /* Disable interrupt */
 212         hns3_pf_disable_irq0(hw);
 213
 214         event_cause = hns3_check_event_cause(hns, &clearval);
 215
 216         /* vector 0 interrupt is shared with reset and mailbox source events. */
 217         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 218                 hns3_handle_msix_error(hns, &hw->reset.request);
 219                 hns3_schedule_reset(hns);
 220         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 221                 hns3_schedule_reset(hns);
 222         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 223                 hns3_dev_handle_mbx_msg(hw);
 224         else
 225                 hns3_err(hw, "Received unknown event");
 226
 227         hns3_clear_event_cause(hw, event_cause, clearval);
 228         /* Enable interrupt if it is not cause by reset */
 229         hns3_pf_enable_irq0(hw);
 230 }
 231
 232 static int
 233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 234 {
 235 #define HNS3_VLAN_ID_OFFSET_STEP        160
 236 #define HNS3_VLAN_BYTE_SIZE             8
 237         struct hns3_vlan_filter_pf_cfg_cmd *req;
 238         struct hns3_hw *hw = &hns->hw;
 239         uint8_t vlan_offset_byte_val;
 240         struct hns3_cmd_desc desc;
 241         uint8_t vlan_offset_byte;
 242         uint8_t vlan_offset_base;
 243         int ret;
 244
 245         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 246
 247         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 248         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 249                            HNS3_VLAN_BYTE_SIZE;
 250         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 251
 252         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 253         req->vlan_offset = vlan_offset_base;
 254         req->vlan_cfg = on ? 0 : 1;
 255         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 256
 257         ret = hns3_cmd_send(hw, &desc, 1);
 258         if (ret)
 259                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 260                          vlan_id, ret);
 261
 262         return ret;
 263 }
 264
 265 static void
 266 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 267 {
 268         struct hns3_user_vlan_table *vlan_entry;
 269         struct hns3_pf *pf = &hns->pf;
 270
 271         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 272                 if (vlan_entry->vlan_id == vlan_id) {
 273                         if (vlan_entry->hd_tbl_status)
 274                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 275                         LIST_REMOVE(vlan_entry, next);
 276                         rte_free(vlan_entry);
 277                         break;
 278                 }
 279         }
 280 }
 281
 282 static void
 283 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 284                         bool writen_to_tbl)
 285 {
 286         struct hns3_user_vlan_table *vlan_entry;
 287         struct hns3_hw *hw = &hns->hw;
 288         struct hns3_pf *pf = &hns->pf;
 289
 290         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 291                 if (vlan_entry->vlan_id == vlan_id)
 292                         return;
 293         }
 294
 295         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 296         if (vlan_entry == NULL) {
 297                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 298                 return;
 299         }
 300
 301         vlan_entry->hd_tbl_status = writen_to_tbl;
 302         vlan_entry->vlan_id = vlan_id;
 303
 304         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 305 }
 306
 307 static int
 308 hns3_restore_vlan_table(struct hns3_adapter *hns)
 309 {
 310         struct hns3_user_vlan_table *vlan_entry;
 311         struct hns3_pf *pf = &hns->pf;
 312         uint16_t vlan_id;
 313         int ret = 0;
 314
 315         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) {
 316                 ret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid,
 317                                                1);
 318                 return ret;
 319         }
 320
 321         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 322                 if (vlan_entry->hd_tbl_status) {
 323                         vlan_id = vlan_entry->vlan_id;
 324                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 325                         if (ret)
 326                                 break;
 327                 }
 328         }
 329
 330         return ret;
 331 }
 332
 333 static int
 334 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 335 {
 336         struct hns3_pf *pf = &hns->pf;
 337         bool writen_to_tbl = false;
 338         int ret = 0;
 339
 340         /*
 341          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 342          * for normal packet, deleting vlan id 0 is not allowed.
 343          */
 344         if (on == 0 && vlan_id == 0)
 345                 return 0;
 346
 347         /*
 348          * When port base vlan enabled, we use port base vlan as the vlan
 349          * filter condition. In this case, we don't update vlan filter table
 350          * when user add new vlan or remove exist vlan, just update the
 351          * vlan list. The vlan id in vlan list will be writen in vlan filter
 352          * table until port base vlan disabled
 353          */
 354         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 355                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 356                 writen_to_tbl = true;
 357         }
 358
 359         if (ret == 0 && vlan_id) {
 360                 if (on)
 361                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 362                 else
 363                         hns3_rm_dev_vlan_table(hns, vlan_id);
 364         }
 365         return ret;
 366 }
 367
 368 static int
 369 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 370 {
 371         struct hns3_adapter *hns = dev->data->dev_private;
 372         struct hns3_hw *hw = &hns->hw;
 373         int ret;
 374
 375         rte_spinlock_lock(&hw->lock);
 376         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 377         rte_spinlock_unlock(&hw->lock);
 378         return ret;
 379 }
 380
 381 static int
 382 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 383                          uint16_t tpid)
 384 {
 385         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 386         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 387         struct hns3_hw *hw = &hns->hw;
 388         struct hns3_cmd_desc desc;
 389         int ret;
 390
 391         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 392              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 393                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 394                 return -EINVAL;
 395         }
 396
 397         if (tpid != RTE_ETHER_TYPE_VLAN) {
 398                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 399                 return -EINVAL;
 400         }
 401
 402         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 403         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 404
 405         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 406                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 407                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 408         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 409                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 412                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 413         }
 414
 415         ret = hns3_cmd_send(hw, &desc, 1);
 416         if (ret) {
 417                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 418                          ret);
 419                 return ret;
 420         }
 421
 422         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 423
 424         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 425         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 426         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 427
 428         ret = hns3_cmd_send(hw, &desc, 1);
 429         if (ret)
 430                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 431                          ret);
 432         return ret;
 433 }
 434
 435 static int
 436 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 437                    uint16_t tpid)
 438 {
 439         struct hns3_adapter *hns = dev->data->dev_private;
 440         struct hns3_hw *hw = &hns->hw;
 441         int ret;
 442
 443         rte_spinlock_lock(&hw->lock);
 444         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 445         rte_spinlock_unlock(&hw->lock);
 446         return ret;
 447 }
 448
 449 static int
 450 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 451                              struct hns3_rx_vtag_cfg *vcfg)
 452 {
 453         struct hns3_vport_vtag_rx_cfg_cmd *req;
 454         struct hns3_hw *hw = &hns->hw;
 455         struct hns3_cmd_desc desc;
 456         uint16_t vport_id;
 457         uint8_t bitmap;
 458         int ret;
 459
 460         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 461
 462         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 463         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 464                      vcfg->strip_tag1_en ? 1 : 0);
 465         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 466                      vcfg->strip_tag2_en ? 1 : 0);
 467         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 468                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 469         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 470                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 471
 472         /*
 473          * In current version VF is not supported when PF is driven by DPDK
 474          * driver, the PF-related vf_id is 0, just need to configure parameters
 475          * for vport_id 0.
 476          */
 477         vport_id = 0;
 478         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 479         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 480         req->vf_bitmap[req->vf_offset] = bitmap;
 481
 482         ret = hns3_cmd_send(hw, &desc, 1);
 483         if (ret)
 484                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 485         return ret;
 486 }
 487
 488 static void
 489 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 490                            struct hns3_rx_vtag_cfg *vcfg)
 491 {
 492         struct hns3_pf *pf = &hns->pf;
 493         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 494 }
 495
 496 static void
 497 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 498                            struct hns3_tx_vtag_cfg *vcfg)
 499 {
 500         struct hns3_pf *pf = &hns->pf;
 501         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 502 }
 503
 504 static int
 505 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 506 {
 507         struct hns3_rx_vtag_cfg rxvlan_cfg;
 508         struct hns3_pf *pf = &hns->pf;
 509         struct hns3_hw *hw = &hns->hw;
 510         int ret;
 511
 512         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 513                 rxvlan_cfg.strip_tag1_en = false;
 514                 rxvlan_cfg.strip_tag2_en = enable;
 515         } else {
 516                 rxvlan_cfg.strip_tag1_en = enable;
 517                 rxvlan_cfg.strip_tag2_en = true;
 518         }
 519
 520         rxvlan_cfg.vlan1_vlan_prionly = false;
 521         rxvlan_cfg.vlan2_vlan_prionly = false;
 522         rxvlan_cfg.rx_vlan_offload_en = enable;
 523
 524         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 525         if (ret) {
 526                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 527                 return ret;
 528         }
 529
 530         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 531
 532         return ret;
 533 }
 534
 535 static int
 536 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 537                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 538 {
 539         struct hns3_vlan_filter_ctrl_cmd *req;
 540         struct hns3_cmd_desc desc;
 541         int ret;
 542
 543         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 544
 545         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 546         req->vlan_type = vlan_type;
 547         req->vlan_fe = filter_en ? fe_type : 0;
 548         req->vf_id = vf_id;
 549
 550         ret = hns3_cmd_send(hw, &desc, 1);
 551         if (ret)
 552                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 553
 554         return ret;
 555 }
 556
 557 static int
 558 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 559 {
 560         struct hns3_hw *hw = &hns->hw;
 561         int ret;
 562
 563         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 564                                         HNS3_FILTER_FE_EGRESS, false, 0);
 565         if (ret) {
 566                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 567                 return ret;
 568         }
 569
 570         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 571                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 572         if (ret)
 573                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 574
 575         return ret;
 576 }
 577
 578 static int
 579 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 580 {
 581         struct hns3_adapter *hns = dev->data->dev_private;
 582         struct hns3_hw *hw = &hns->hw;
 583         struct rte_eth_rxmode *rxmode;
 584         unsigned int tmp_mask;
 585         bool enable;
 586         int ret = 0;
 587
 588         rte_spinlock_lock(&hw->lock);
 589         rxmode = &dev->data->dev_conf.rxmode;
 590         tmp_mask = (unsigned int)mask;
 591         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 592                 /* Enable or disable VLAN stripping */
 593                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 594                     true : false;
 595
 596                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 597                 if (ret) {
 598                         rte_spinlock_unlock(&hw->lock);
 599                         hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
 600                         return ret;
 601                 }
 602         }
 603
 604         rte_spinlock_unlock(&hw->lock);
 605
 606         return ret;
 607 }
 608
 609 static int
 610 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 611                              struct hns3_tx_vtag_cfg *vcfg)
 612 {
 613         struct hns3_vport_vtag_tx_cfg_cmd *req;
 614         struct hns3_cmd_desc desc;
 615         struct hns3_hw *hw = &hns->hw;
 616         uint16_t vport_id;
 617         uint8_t bitmap;
 618         int ret;
 619
 620         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 621
 622         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 623         req->def_vlan_tag1 = vcfg->default_tag1;
 624         req->def_vlan_tag2 = vcfg->default_tag2;
 625         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 626                      vcfg->accept_tag1 ? 1 : 0);
 627         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 628                      vcfg->accept_untag1 ? 1 : 0);
 629         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 630                      vcfg->accept_tag2 ? 1 : 0);
 631         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 632                      vcfg->accept_untag2 ? 1 : 0);
 633         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 634                      vcfg->insert_tag1_en ? 1 : 0);
 635         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 636                      vcfg->insert_tag2_en ? 1 : 0);
 637         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 638
 639         /*
 640          * In current version VF is not supported when PF is driven by DPDK
 641          * driver, the PF-related vf_id is 0, just need to configure parameters
 642          * for vport_id 0.
 643          */
 644         vport_id = 0;
 645         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 646         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 647         req->vf_bitmap[req->vf_offset] = bitmap;
 648
 649         ret = hns3_cmd_send(hw, &desc, 1);
 650         if (ret)
 651                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 652
 653         return ret;
 654 }
 655
 656 static int
 657 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 658                      uint16_t pvid)
 659 {
 660         struct hns3_hw *hw = &hns->hw;
 661         struct hns3_tx_vtag_cfg txvlan_cfg;
 662         int ret;
 663
 664         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 665                 txvlan_cfg.accept_tag1 = true;
 666                 txvlan_cfg.insert_tag1_en = false;
 667                 txvlan_cfg.default_tag1 = 0;
 668         } else {
 669                 txvlan_cfg.accept_tag1 = false;
 670                 txvlan_cfg.insert_tag1_en = true;
 671                 txvlan_cfg.default_tag1 = pvid;
 672         }
 673
 674         txvlan_cfg.accept_untag1 = true;
 675         txvlan_cfg.accept_tag2 = true;
 676         txvlan_cfg.accept_untag2 = true;
 677         txvlan_cfg.insert_tag2_en = false;
 678         txvlan_cfg.default_tag2 = 0;
 679
 680         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 681         if (ret) {
 682                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 683                          ret);
 684                 return ret;
 685         }
 686
 687         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 688         return ret;
 689 }
 690
 691 static void
 692 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 693 {
 694         struct hns3_pf *pf = &hns->pf;
 695
 696         pf->port_base_vlan_cfg.state = on ?
 697             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 698
 699         pf->port_base_vlan_cfg.pvid = pvid;
 700 }
 701
 702 static void
 703 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 704 {
 705         struct hns3_user_vlan_table *vlan_entry;
 706         struct hns3_pf *pf = &hns->pf;
 707
 708         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 709                 if (vlan_entry->hd_tbl_status)
 710                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 711
 712                 vlan_entry->hd_tbl_status = false;
 713         }
 714
 715         if (is_del_list) {
 716                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 717                 while (vlan_entry) {
 718                         LIST_REMOVE(vlan_entry, next);
 719                         rte_free(vlan_entry);
 720                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 721                 }
 722         }
 723 }
 724
 725 static void
 726 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 727 {
 728         struct hns3_user_vlan_table *vlan_entry;
 729         struct hns3_pf *pf = &hns->pf;
 730
 731         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 732                 if (!vlan_entry->hd_tbl_status)
 733                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 734
 735                 vlan_entry->hd_tbl_status = true;
 736         }
 737 }
 738
 739 static void
 740 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 741 {
 742         struct hns3_hw *hw = &hns->hw;
 743         struct hns3_pf *pf = &hns->pf;
 744         int ret;
 745
 746         hns3_rm_all_vlan_table(hns, true);
 747         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 748                 ret = hns3_set_port_vlan_filter(hns,
 749                                                 pf->port_base_vlan_cfg.pvid, 0);
 750                 if (ret) {
 751                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 752                                  ret);
 753                         return;
 754                 }
 755         }
 756 }
 757
 758 static int
 759 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 760                                 uint16_t port_base_vlan_state,
 761                                 uint16_t new_pvid, uint16_t old_pvid)
 762 {
 763         struct hns3_pf *pf = &hns->pf;
 764         struct hns3_hw *hw = &hns->hw;
 765         int ret = 0;
 766
 767         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 768                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 769                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 770                         if (ret) {
 771                                 hns3_err(hw,
 772                                          "Failed to clear clear old pvid filter, ret =%d",
 773                                          ret);
 774                                 return ret;
 775                         }
 776                 }
 777
 778                 hns3_rm_all_vlan_table(hns, false);
 779                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 780         }
 781
 782         if (new_pvid != 0) {
 783                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 784                 if (ret) {
 785                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 786                                  ret);
 787                         return ret;
 788                 }
 789         }
 790
 791         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 792                 hns3_add_all_vlan_table(hns);
 793
 794         return ret;
 795 }
 796
 797 static int
 798 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 799 {
 800         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 801         struct hns3_hw *hw = &hns->hw;
 802         bool rx_strip_en;
 803         int ret;
 804
 805         rx_strip_en = on ? true : false;
 806         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 807         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 808         rx_vlan_cfg.vlan1_vlan_prionly = false;
 809         rx_vlan_cfg.vlan2_vlan_prionly = false;
 810         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 811
 812         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 813         if (ret) {
 814                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 815                 return ret;
 816         }
 817
 818         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 819         return ret;
 820 }
 821
 822 static int
 823 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 824 {
 825         struct hns3_pf *pf = &hns->pf;
 826         struct hns3_hw *hw = &hns->hw;
 827         uint16_t port_base_vlan_state;
 828         uint16_t old_pvid;
 829         int ret;
 830
 831         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 832                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 833                         hns3_warn(hw, "Invalid operation! As current pvid set "
 834                                   "is %u, disable pvid %u is invalid",
 835                                   pf->port_base_vlan_cfg.pvid, pvid);
 836                 return 0;
 837         }
 838
 839         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 840                                     HNS3_PORT_BASE_VLAN_DISABLE;
 841         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 842         if (ret) {
 843                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 844                 return ret;
 845         }
 846
 847         ret = hns3_en_rx_strip_all(hns, on);
 848         if (ret) {
 849                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 850                 return ret;
 851         }
 852
 853         if (pvid == HNS3_INVLID_PVID)
 854                 goto out;
 855         old_pvid = pf->port_base_vlan_cfg.pvid;
 856         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 857                                               old_pvid);
 858         if (ret) {
 859                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 860                          ret);
 861                 return ret;
 862         }
 863
 864 out:
 865         hns3_store_port_base_vlan_info(hns, pvid, on);
 866         return ret;
 867 }
 868
 869 static int
 870 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 871 {
 872         struct hns3_adapter *hns = dev->data->dev_private;
 873         struct hns3_hw *hw = &hns->hw;
 874         int ret;
 875
 876         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 877                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 878                          RTE_ETHER_MAX_VLAN_ID);
 879                 return -EINVAL;
 880         }
 881
 882         rte_spinlock_lock(&hw->lock);
 883         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 884         rte_spinlock_unlock(&hw->lock);
 885         return ret;
 886 }
 887
 888 static void
 889 init_port_base_vlan_info(struct hns3_hw *hw)
 890 {
 891         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 892         struct hns3_pf *pf = &hns->pf;
 893
 894         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 895         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 896 }
 897
 898 static int
 899 hns3_default_vlan_config(struct hns3_adapter *hns)
 900 {
 901         struct hns3_hw *hw = &hns->hw;
 902         int ret;
 903
 904         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 905         if (ret)
 906                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 907         return ret;
 908 }
 909
 910 static int
 911 hns3_init_vlan_config(struct hns3_adapter *hns)
 912 {
 913         struct hns3_hw *hw = &hns->hw;
 914         int ret;
 915
 916         /*
 917          * This function can be called in the initialization and reset process,
 918          * when in reset process, it means that hardware had been reseted
 919          * successfully and we need to restore the hardware configuration to
 920          * ensure that the hardware configuration remains unchanged before and
 921          * after reset.
 922          */
 923         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 924                 init_port_base_vlan_info(hw);
 925
 926         ret = hns3_enable_vlan_filter(hns, true);
 927         if (ret) {
 928                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 929                 return ret;
 930         }
 931
 932         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 933                                        RTE_ETHER_TYPE_VLAN);
 934         if (ret) {
 935                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 936                 return ret;
 937         }
 938
 939         /*
 940          * When in the reinit dev stage of the reset process, the following
 941          * vlan-related configurations may differ from those at initialization,
 942          * we will restore configurations to hardware in hns3_restore_vlan_table
 943          * and hns3_restore_vlan_conf later.
 944          */
 945         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 946                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 947                 if (ret) {
 948                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 949                         return ret;
 950                 }
 951
 952                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 953                 if (ret) {
 954                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 955                                  ret);
 956                         return ret;
 957                 }
 958         }
 959
 960         return hns3_default_vlan_config(hns);
 961 }
 962
 963 static int
 964 hns3_restore_vlan_conf(struct hns3_adapter *hns)
 965 {
 966         struct hns3_pf *pf = &hns->pf;
 967         struct hns3_hw *hw = &hns->hw;
 968         int ret;
 969
 970         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
 971         if (ret) {
 972                 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
 973                 return ret;
 974         }
 975
 976         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
 977         if (ret)
 978                 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
 979
 980         return ret;
 981 }
 982
 983 static int
 984 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
 985 {
 986         struct hns3_adapter *hns = dev->data->dev_private;
 987         struct rte_eth_dev_data *data = dev->data;
 988         struct rte_eth_txmode *txmode;
 989         struct hns3_hw *hw = &hns->hw;
 990         int ret;
 991
 992         txmode = &data->dev_conf.txmode;
 993         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
 994                 hns3_warn(hw,
 995                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
 996                           "configuration is not supported! Ignore these two "
 997                           "parameters: hw_vlan_reject_tagged(%d), "
 998                           "hw_vlan_reject_untagged(%d)",
 999                           txmode->hw_vlan_reject_tagged,
1000                           txmode->hw_vlan_reject_untagged);
1001
1002         /* Apply vlan offload setting */
1003         ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1004         if (ret) {
1005                 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
1006                 return ret;
1007         }
1008
1009         /* Apply pvid setting */
1010         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1011                                  txmode->hw_vlan_insert_pvid);
1012         if (ret)
1013                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
1014                          txmode->pvid, ret);
1015
1016         return ret;
1017 }
1018
1019 static int
1020 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1021                 unsigned int tso_mss_max)
1022 {
1023         struct hns3_cfg_tso_status_cmd *req;
1024         struct hns3_cmd_desc desc;
1025         uint16_t tso_mss;
1026
1027         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1028
1029         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1030
1031         tso_mss = 0;
1032         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1033                        tso_mss_min);
1034         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1035
1036         tso_mss = 0;
1037         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1038                        tso_mss_max);
1039         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1040
1041         return hns3_cmd_send(hw, &desc, 1);
1042 }
1043
1044 int
1045 hns3_config_gro(struct hns3_hw *hw, bool en)
1046 {
1047         struct hns3_cfg_gro_status_cmd *req;
1048         struct hns3_cmd_desc desc;
1049         int ret;
1050
1051         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1052         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1053
1054         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1055
1056         ret = hns3_cmd_send(hw, &desc, 1);
1057         if (ret)
1058                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1059
1060         return ret;
1061 }
1062
1063 static int
1064 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1065                    uint16_t *allocated_size, bool is_alloc)
1066 {
1067         struct hns3_umv_spc_alc_cmd *req;
1068         struct hns3_cmd_desc desc;
1069         int ret;
1070
1071         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1072         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1073         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1074         req->space_size = rte_cpu_to_le_32(space_size);
1075
1076         ret = hns3_cmd_send(hw, &desc, 1);
1077         if (ret) {
1078                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1079                              is_alloc ? "allocate" : "free", ret);
1080                 return ret;
1081         }
1082
1083         if (is_alloc && allocated_size)
1084                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1085
1086         return 0;
1087 }
1088
1089 static int
1090 hns3_init_umv_space(struct hns3_hw *hw)
1091 {
1092         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1093         struct hns3_pf *pf = &hns->pf;
1094         uint16_t allocated_size = 0;
1095         int ret;
1096
1097         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1098                                  true);
1099         if (ret)
1100                 return ret;
1101
1102         if (allocated_size < pf->wanted_umv_size)
1103                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1104                              pf->wanted_umv_size, allocated_size);
1105
1106         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1107                                                 pf->wanted_umv_size;
1108         pf->used_umv_size = 0;
1109         return 0;
1110 }
1111
1112 static int
1113 hns3_uninit_umv_space(struct hns3_hw *hw)
1114 {
1115         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1116         struct hns3_pf *pf = &hns->pf;
1117         int ret;
1118
1119         if (pf->max_umv_size == 0)
1120                 return 0;
1121
1122         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1123         if (ret)
1124                 return ret;
1125
1126         pf->max_umv_size = 0;
1127
1128         return 0;
1129 }
1130
1131 static bool
1132 hns3_is_umv_space_full(struct hns3_hw *hw)
1133 {
1134         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1135         struct hns3_pf *pf = &hns->pf;
1136         bool is_full;
1137
1138         is_full = (pf->used_umv_size >= pf->max_umv_size);
1139
1140         return is_full;
1141 }
1142
1143 static void
1144 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1145 {
1146         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1147         struct hns3_pf *pf = &hns->pf;
1148
1149         if (is_free) {
1150                 if (pf->used_umv_size > 0)
1151                         pf->used_umv_size--;
1152         } else
1153                 pf->used_umv_size++;
1154 }
1155
1156 static void
1157 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1158                       const uint8_t *addr, bool is_mc)
1159 {
1160         const unsigned char *mac_addr = addr;
1161         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1162                             ((uint32_t)mac_addr[2] << 16) |
1163                             ((uint32_t)mac_addr[1] << 8) |
1164                             (uint32_t)mac_addr[0];
1165         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1166
1167         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1168         if (is_mc) {
1169                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1170                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1171                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1172         }
1173
1174         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1175         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1176 }
1177
1178 static int
1179 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1180                              uint8_t resp_code,
1181                              enum hns3_mac_vlan_tbl_opcode op)
1182 {
1183         if (cmdq_resp) {
1184                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1185                          cmdq_resp);
1186                 return -EIO;
1187         }
1188
1189         if (op == HNS3_MAC_VLAN_ADD) {
1190                 if (resp_code == 0 || resp_code == 1) {
1191                         return 0;
1192                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1193                         hns3_err(hw, "add mac addr failed for uc_overflow");
1194                         return -ENOSPC;
1195                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1196                         hns3_err(hw, "add mac addr failed for mc_overflow");
1197                         return -ENOSPC;
1198                 }
1199
1200                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1201                          resp_code);
1202                 return -EIO;
1203         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1204                 if (resp_code == 0) {
1205                         return 0;
1206                 } else if (resp_code == 1) {
1207                         hns3_dbg(hw, "remove mac addr failed for miss");
1208                         return -ENOENT;
1209                 }
1210
1211                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1212                          resp_code);
1213                 return -EIO;
1214         } else if (op == HNS3_MAC_VLAN_LKUP) {
1215                 if (resp_code == 0) {
1216                         return 0;
1217                 } else if (resp_code == 1) {
1218                         hns3_dbg(hw, "lookup mac addr failed for miss");
1219                         return -ENOENT;
1220                 }
1221
1222                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1223                          resp_code);
1224                 return -EIO;
1225         }
1226
1227         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1228                  op);
1229
1230         return -EINVAL;
1231 }
1232
1233 static int
1234 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1235                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1236                          struct hns3_cmd_desc *desc, bool is_mc)
1237 {
1238         uint8_t resp_code;
1239         uint16_t retval;
1240         int ret;
1241
1242         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1243         if (is_mc) {
1244                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1245                 memcpy(desc[0].data, req,
1246                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1247                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1248                                           true);
1249                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1250                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1251                                           true);
1252                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1253         } else {
1254                 memcpy(desc[0].data, req,
1255                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1256                 ret = hns3_cmd_send(hw, desc, 1);
1257         }
1258         if (ret) {
1259                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1260                          ret);
1261                 return ret;
1262         }
1263         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1264         retval = rte_le_to_cpu_16(desc[0].retval);
1265
1266         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1267                                             HNS3_MAC_VLAN_LKUP);
1268 }
1269
1270 static int
1271 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1272                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1273                       struct hns3_cmd_desc *mc_desc)
1274 {
1275         uint8_t resp_code;
1276         uint16_t retval;
1277         int cfg_status;
1278         int ret;
1279
1280         if (mc_desc == NULL) {
1281                 struct hns3_cmd_desc desc;
1282
1283                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1284                 memcpy(desc.data, req,
1285                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1286                 ret = hns3_cmd_send(hw, &desc, 1);
1287                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1288                 retval = rte_le_to_cpu_16(desc.retval);
1289
1290                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1291                                                           HNS3_MAC_VLAN_ADD);
1292         } else {
1293                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1294                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1295                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1296                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1297                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1298                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1299                 memcpy(mc_desc[0].data, req,
1300                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1301                 mc_desc[0].retval = 0;
1302                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1303                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1304                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1305
1306                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1307                                                           HNS3_MAC_VLAN_ADD);
1308         }
1309
1310         if (ret) {
1311                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1312                 return ret;
1313         }
1314
1315         return cfg_status;
1316 }
1317
1318 static int
1319 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1320                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1321 {
1322         struct hns3_cmd_desc desc;
1323         uint8_t resp_code;
1324         uint16_t retval;
1325         int ret;
1326
1327         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1328
1329         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1330
1331         ret = hns3_cmd_send(hw, &desc, 1);
1332         if (ret) {
1333                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1334                 return ret;
1335         }
1336         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1337         retval = rte_le_to_cpu_16(desc.retval);
1338
1339         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1340                                             HNS3_MAC_VLAN_REMOVE);
1341 }
1342
1343 static int
1344 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1345 {
1346         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1347         struct hns3_mac_vlan_tbl_entry_cmd req;
1348         struct hns3_pf *pf = &hns->pf;
1349         struct hns3_cmd_desc desc;
1350         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1351         uint16_t egress_port = 0;
1352         uint8_t vf_id;
1353         int ret;
1354
1355         /* check if mac addr is valid */
1356         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1357                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1358                                       mac_addr);
1359                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1360                          mac_str);
1361                 return -EINVAL;
1362         }
1363
1364         memset(&req, 0, sizeof(req));
1365
1366         /*
1367          * In current version VF is not supported when PF is driven by DPDK
1368          * driver, the PF-related vf_id is 0, just need to configure parameters
1369          * for vf_id 0.
1370          */
1371         vf_id = 0;
1372         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1373                        HNS3_MAC_EPORT_VFID_S, vf_id);
1374
1375         req.egress_port = rte_cpu_to_le_16(egress_port);
1376
1377         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1378
1379         /*
1380          * Lookup the mac address in the mac_vlan table, and add
1381          * it if the entry is inexistent. Repeated unicast entry
1382          * is not allowed in the mac vlan table.
1383          */
1384         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1385         if (ret == -ENOENT) {
1386                 if (!hns3_is_umv_space_full(hw)) {
1387                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1388                         if (!ret)
1389                                 hns3_update_umv_space(hw, false);
1390                         return ret;
1391                 }
1392
1393                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1394
1395                 return -ENOSPC;
1396         }
1397
1398         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1399
1400         /* check if we just hit the duplicate */
1401         if (ret == 0) {
1402                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1403                 return 0;
1404         }
1405
1406         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1407                  mac_str);
1408
1409         return ret;
1410 }
1411
1412 static int
1413 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1414                   uint32_t idx, __rte_unused uint32_t pool)
1415 {
1416         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1418         int ret;
1419
1420         rte_spinlock_lock(&hw->lock);
1421         ret = hns3_add_uc_addr_common(hw, mac_addr);
1422         if (ret) {
1423                 rte_spinlock_unlock(&hw->lock);
1424                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1425                                       mac_addr);
1426                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1427                 return ret;
1428         }
1429
1430         if (idx == 0)
1431                 hw->mac.default_addr_setted = true;
1432         rte_spinlock_unlock(&hw->lock);
1433
1434         return ret;
1435 }
1436
1437 static int
1438 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1439 {
1440         struct hns3_mac_vlan_tbl_entry_cmd req;
1441         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1442         int ret;
1443
1444         /* check if mac addr is valid */
1445         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1446                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1447                                       mac_addr);
1448                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1449                          mac_str);
1450                 return -EINVAL;
1451         }
1452
1453         memset(&req, 0, sizeof(req));
1454         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1455         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1456         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1457         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1458                 return 0;
1459         else if (ret == 0)
1460                 hns3_update_umv_space(hw, true);
1461
1462         return ret;
1463 }
1464
1465 static void
1466 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1467 {
1468         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1469         /* index will be checked by upper level rte interface */
1470         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1471         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1472         int ret;
1473
1474         rte_spinlock_lock(&hw->lock);
1475         ret = hns3_remove_uc_addr_common(hw, mac_addr);
1476         if (ret) {
1477                 rte_spinlock_unlock(&hw->lock);
1478                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1479                                       mac_addr);
1480                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1481                 return;
1482         }
1483
1484         rte_spinlock_unlock(&hw->lock);
1485 }
1486
1487 static int
1488 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1489                           struct rte_ether_addr *mac_addr)
1490 {
1491         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1492         struct rte_ether_addr *oaddr;
1493         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1494         bool default_addr_setted;
1495         bool rm_succes = false;
1496         int ret, ret_val;
1497
1498         /*
1499          * It has been guaranteed that input parameter named mac_addr is valid
1500          * address in the rte layer of DPDK framework.
1501          */
1502         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1503         default_addr_setted = hw->mac.default_addr_setted;
1504         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1505                 return 0;
1506
1507         rte_spinlock_lock(&hw->lock);
1508         if (default_addr_setted) {
1509                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1510                 if (ret) {
1511                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1512                                               oaddr);
1513                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1514                                   mac_str, ret);
1515                         rm_succes = false;
1516                 } else
1517                         rm_succes = true;
1518         }
1519
1520         ret = hns3_add_uc_addr_common(hw, mac_addr);
1521         if (ret) {
1522                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1523                                       mac_addr);
1524                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1525                 goto err_add_uc_addr;
1526         }
1527
1528         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1529         if (ret) {
1530                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1531                 goto err_pause_addr_cfg;
1532         }
1533
1534         rte_ether_addr_copy(mac_addr,
1535                             (struct rte_ether_addr *)hw->mac.mac_addr);
1536         hw->mac.default_addr_setted = true;
1537         rte_spinlock_unlock(&hw->lock);
1538
1539         return 0;
1540
1541 err_pause_addr_cfg:
1542         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1543         if (ret_val) {
1544                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1545                                       mac_addr);
1546                 hns3_warn(hw,
1547                           "Failed to roll back to del setted mac addr(%s): %d",
1548                           mac_str, ret_val);
1549         }
1550
1551 err_add_uc_addr:
1552         if (rm_succes) {
1553                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1554                 if (ret_val) {
1555                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1556                                               oaddr);
1557                         hns3_warn(hw,
1558                                   "Failed to restore old uc mac addr(%s): %d",
1559                                   mac_str, ret_val);
1560                         hw->mac.default_addr_setted = false;
1561                 }
1562         }
1563         rte_spinlock_unlock(&hw->lock);
1564
1565         return ret;
1566 }
1567
1568 static int
1569 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1570 {
1571         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1572         struct hns3_hw *hw = &hns->hw;
1573         struct rte_ether_addr *addr;
1574         int err = 0;
1575         int ret;
1576         int i;
1577
1578         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1579                 addr = &hw->data->mac_addrs[i];
1580                 if (!rte_is_valid_assigned_ether_addr(addr))
1581                         continue;
1582                 if (del)
1583                         ret = hns3_remove_uc_addr_common(hw, addr);
1584                 else
1585                         ret = hns3_add_uc_addr_common(hw, addr);
1586                 if (ret) {
1587                         err = ret;
1588                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1589                                               addr);
1590                         hns3_dbg(hw,
1591                                  "Failed to %s mac addr(%s). ret:%d i:%d",
1592                                  del ? "remove" : "restore", mac_str, ret, i);
1593                 }
1594         }
1595         return err;
1596 }
1597
1598 static void
1599 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1600 {
1601 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1602         uint8_t word_num;
1603         uint8_t bit_num;
1604
1605         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1606                 word_num = vfid / 32;
1607                 bit_num = vfid % 32;
1608                 if (clr)
1609                         desc[1].data[word_num] &=
1610                             rte_cpu_to_le_32(~(1UL << bit_num));
1611                 else
1612                         desc[1].data[word_num] |=
1613                             rte_cpu_to_le_32(1UL << bit_num);
1614         } else {
1615                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1616                 bit_num = vfid % 32;
1617                 if (clr)
1618                         desc[2].data[word_num] &=
1619                             rte_cpu_to_le_32(~(1UL << bit_num));
1620                 else
1621                         desc[2].data[word_num] |=
1622                             rte_cpu_to_le_32(1UL << bit_num);
1623         }
1624 }
1625
1626 static int
1627 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1628 {
1629         struct hns3_mac_vlan_tbl_entry_cmd req;
1630         struct hns3_cmd_desc desc[3];
1631         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1632         uint8_t vf_id;
1633         int ret;
1634
1635         /* Check if mac addr is valid */
1636         if (!rte_is_multicast_ether_addr(mac_addr)) {
1637                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1638                                       mac_addr);
1639                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1640                          mac_str);
1641                 return -EINVAL;
1642         }
1643
1644         memset(&req, 0, sizeof(req));
1645         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1646         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1647         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1648         if (ret) {
1649                 /* This mac addr do not exist, add new entry for it */
1650                 memset(desc[0].data, 0, sizeof(desc[0].data));
1651                 memset(desc[1].data, 0, sizeof(desc[0].data));
1652                 memset(desc[2].data, 0, sizeof(desc[0].data));
1653         }
1654
1655         /*
1656          * In current version VF is not supported when PF is driven by DPDK
1657          * driver, the PF-related vf_id is 0, just need to configure parameters
1658          * for vf_id 0.
1659          */
1660         vf_id = 0;
1661         hns3_update_desc_vfid(desc, vf_id, false);
1662         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1663         if (ret) {
1664                 if (ret == -ENOSPC)
1665                         hns3_err(hw, "mc mac vlan table is full");
1666                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1667                                       mac_addr);
1668                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1669         }
1670
1671         return ret;
1672 }
1673
1674 static int
1675 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1676 {
1677         struct hns3_mac_vlan_tbl_entry_cmd req;
1678         struct hns3_cmd_desc desc[3];
1679         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1680         uint8_t vf_id;
1681         int ret;
1682
1683         /* Check if mac addr is valid */
1684         if (!rte_is_multicast_ether_addr(mac_addr)) {
1685                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1686                                       mac_addr);
1687                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1688                          mac_str);
1689                 return -EINVAL;
1690         }
1691
1692         memset(&req, 0, sizeof(req));
1693         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1694         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1695         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1696         if (ret == 0) {
1697                 /*
1698                  * This mac addr exist, remove this handle's VFID for it.
1699                  * In current version VF is not supported when PF is driven by
1700                  * DPDK driver, the PF-related vf_id is 0, just need to
1701                  * configure parameters for vf_id 0.
1702                  */
1703                 vf_id = 0;
1704                 hns3_update_desc_vfid(desc, vf_id, true);
1705
1706                 /* All the vfid is zero, so need to delete this entry */
1707                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1708         } else if (ret == -ENOENT) {
1709                 /* This mac addr doesn't exist. */
1710                 return 0;
1711         }
1712
1713         if (ret) {
1714                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1715                                       mac_addr);
1716                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1717         }
1718
1719         return ret;
1720 }
1721
1722 static int
1723 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1724                            struct rte_ether_addr *mc_addr_set,
1725                            uint32_t nb_mc_addr)
1726 {
1727         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1728         struct rte_ether_addr *addr;
1729         uint32_t i;
1730         uint32_t j;
1731
1732         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1733                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1734                          "invalid. valid range: 0~%d",
1735                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1736                 return -EINVAL;
1737         }
1738
1739         /* Check if input mac addresses are valid */
1740         for (i = 0; i < nb_mc_addr; i++) {
1741                 addr = &mc_addr_set[i];
1742                 if (!rte_is_multicast_ether_addr(addr)) {
1743                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1744                                               addr);
1745                         hns3_err(hw,
1746                                  "Failed to set mc mac addr, addr(%s) invalid.",
1747                                  mac_str);
1748                         return -EINVAL;
1749                 }
1750
1751                 /* Check if there are duplicate addresses */
1752                 for (j = i + 1; j < nb_mc_addr; j++) {
1753                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1754                                 rte_ether_format_addr(mac_str,
1755                                                       RTE_ETHER_ADDR_FMT_SIZE,
1756                                                       addr);
1757                                 hns3_err(hw, "Failed to set mc mac addr, "
1758                                          "addrs invalid. two same addrs(%s).",
1759                                          mac_str);
1760                                 return -EINVAL;
1761                         }
1762                 }
1763         }
1764
1765         return 0;
1766 }
1767
1768 static void
1769 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1770                            struct rte_ether_addr *mc_addr_set,
1771                            int mc_addr_num,
1772                            struct rte_ether_addr *reserved_addr_list,
1773                            int *reserved_addr_num,
1774                            struct rte_ether_addr *add_addr_list,
1775                            int *add_addr_num,
1776                            struct rte_ether_addr *rm_addr_list,
1777                            int *rm_addr_num)
1778 {
1779         struct rte_ether_addr *addr;
1780         int current_addr_num;
1781         int reserved_num = 0;
1782         int add_num = 0;
1783         int rm_num = 0;
1784         int num;
1785         int i;
1786         int j;
1787         bool same_addr;
1788
1789         /* Calculate the mc mac address list that should be removed */
1790         current_addr_num = hw->mc_addrs_num;
1791         for (i = 0; i < current_addr_num; i++) {
1792                 addr = &hw->mc_addrs[i];
1793                 same_addr = false;
1794                 for (j = 0; j < mc_addr_num; j++) {
1795                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1796                                 same_addr = true;
1797                                 break;
1798                         }
1799                 }
1800
1801                 if (!same_addr) {
1802                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1803                         rm_num++;
1804                 } else {
1805                         rte_ether_addr_copy(addr,
1806                                             &reserved_addr_list[reserved_num]);
1807                         reserved_num++;
1808                 }
1809         }
1810
1811         /* Calculate the mc mac address list that should be added */
1812         for (i = 0; i < mc_addr_num; i++) {
1813                 addr = &mc_addr_set[i];
1814                 same_addr = false;
1815                 for (j = 0; j < current_addr_num; j++) {
1816                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1817                                 same_addr = true;
1818                                 break;
1819                         }
1820                 }
1821
1822                 if (!same_addr) {
1823                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1824                         add_num++;
1825                 }
1826         }
1827
1828         /* Reorder the mc mac address list maintained by driver */
1829         for (i = 0; i < reserved_num; i++)
1830                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1831
1832         for (i = 0; i < rm_num; i++) {
1833                 num = reserved_num + i;
1834                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1835         }
1836
1837         *reserved_addr_num = reserved_num;
1838         *add_addr_num = add_num;
1839         *rm_addr_num = rm_num;
1840 }
1841
1842 static int
1843 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1844                           struct rte_ether_addr *mc_addr_set,
1845                           uint32_t nb_mc_addr)
1846 {
1847         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1848         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1849         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1850         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1851         struct rte_ether_addr *addr;
1852         int reserved_addr_num;
1853         int add_addr_num;
1854         int rm_addr_num;
1855         int mc_addr_num;
1856         int num;
1857         int ret;
1858         int i;
1859
1860         /* Check if input parameters are valid */
1861         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1862         if (ret)
1863                 return ret;
1864
1865         rte_spinlock_lock(&hw->lock);
1866
1867         /*
1868          * Calculate the mc mac address lists those should be removed and be
1869          * added, Reorder the mc mac address list maintained by driver.
1870          */
1871         mc_addr_num = (int)nb_mc_addr;
1872         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1873                                    reserved_addr_list, &reserved_addr_num,
1874                                    add_addr_list, &add_addr_num,
1875                                    rm_addr_list, &rm_addr_num);
1876
1877         /* Remove mc mac addresses */
1878         for (i = 0; i < rm_addr_num; i++) {
1879                 num = rm_addr_num - i - 1;
1880                 addr = &rm_addr_list[num];
1881                 ret = hns3_remove_mc_addr(hw, addr);
1882                 if (ret) {
1883                         rte_spinlock_unlock(&hw->lock);
1884                         return ret;
1885                 }
1886                 hw->mc_addrs_num--;
1887         }
1888
1889         /* Add mc mac addresses */
1890         for (i = 0; i < add_addr_num; i++) {
1891                 addr = &add_addr_list[i];
1892                 ret = hns3_add_mc_addr(hw, addr);
1893                 if (ret) {
1894                         rte_spinlock_unlock(&hw->lock);
1895                         return ret;
1896                 }
1897
1898                 num = reserved_addr_num + i;
1899                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1900                 hw->mc_addrs_num++;
1901         }
1902         rte_spinlock_unlock(&hw->lock);
1903
1904         return 0;
1905 }
1906
1907 static int
1908 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1909 {
1910         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1911         struct hns3_hw *hw = &hns->hw;
1912         struct rte_ether_addr *addr;
1913         int err = 0;
1914         int ret;
1915         int i;
1916
1917         for (i = 0; i < hw->mc_addrs_num; i++) {
1918                 addr = &hw->mc_addrs[i];
1919                 if (!rte_is_multicast_ether_addr(addr))
1920                         continue;
1921                 if (del)
1922                         ret = hns3_remove_mc_addr(hw, addr);
1923                 else
1924                         ret = hns3_add_mc_addr(hw, addr);
1925                 if (ret) {
1926                         err = ret;
1927                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1928                                               addr);
1929                         hns3_dbg(hw, "%s mc mac addr: %s failed",
1930                                  del ? "Remove" : "Restore", mac_str);
1931                 }
1932         }
1933         return err;
1934 }
1935
1936 static int
1937 hns3_check_mq_mode(struct rte_eth_dev *dev)
1938 {
1939         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1940         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1941         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1943         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1944         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1945         uint8_t num_tc;
1946         int max_tc = 0;
1947         int i;
1948
1949         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1950         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1951
1952         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1953                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
1954                          "rx_mq_mode = %d", rx_mq_mode);
1955                 return -EINVAL;
1956         }
1957
1958         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
1959             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1960                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
1961                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
1962                          rx_mq_mode, tx_mq_mode);
1963                 return -EINVAL;
1964         }
1965
1966         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
1967                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1968                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1969                                  dcb_rx_conf->nb_tcs, pf->tc_max);
1970                         return -EINVAL;
1971                 }
1972
1973                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1974                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1975                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
1976                                  "nb_tcs(%d) != %d or %d in rx direction.",
1977                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1978                         return -EINVAL;
1979                 }
1980
1981                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1982                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1983                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1984                         return -EINVAL;
1985                 }
1986
1987                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1988                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1989                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
1990                                          "is not equal to one in tx direction.",
1991                                          i, dcb_rx_conf->dcb_tc[i]);
1992                                 return -EINVAL;
1993                         }
1994                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
1995                                 max_tc = dcb_rx_conf->dcb_tc[i];
1996                 }
1997
1998                 num_tc = max_tc + 1;
1999                 if (num_tc > dcb_rx_conf->nb_tcs) {
2000                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2001                                  num_tc, dcb_rx_conf->nb_tcs);
2002                         return -EINVAL;
2003                 }
2004         }
2005
2006         return 0;
2007 }
2008
2009 static int
2010 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2011 {
2012         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2013
2014         if (!hns3_dev_dcb_supported(hw)) {
2015                 hns3_err(hw, "this port does not support dcb configurations.");
2016                 return -EOPNOTSUPP;
2017         }
2018
2019         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2020                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2021                 return -EOPNOTSUPP;
2022         }
2023
2024         /* Check multiple queue mode */
2025         return hns3_check_mq_mode(dev);
2026 }
2027
2028 static int
2029 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2030                            enum hns3_ring_type queue_type, uint16_t queue_id)
2031 {
2032         struct hns3_cmd_desc desc;
2033         struct hns3_ctrl_vector_chain_cmd *req =
2034                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2035         enum hns3_cmd_status status;
2036         enum hns3_opcode_type op;
2037         uint16_t tqp_type_and_id = 0;
2038         const char *op_str;
2039         uint16_t type;
2040         uint16_t gl;
2041
2042         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2043         hns3_cmd_setup_basic_desc(&desc, op, false);
2044         req->int_vector_id = vector_id;
2045
2046         if (queue_type == HNS3_RING_TYPE_RX)
2047                 gl = HNS3_RING_GL_RX;
2048         else
2049                 gl = HNS3_RING_GL_TX;
2050
2051         type = queue_type;
2052
2053         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2054                        type);
2055         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2056         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2057                        gl);
2058         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2059         req->int_cause_num = 1;
2060         op_str = mmap ? "Map" : "Unmap";
2061         status = hns3_cmd_send(hw, &desc, 1);
2062         if (status) {
2063                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2064                          op_str, queue_id, req->int_vector_id, status);
2065                 return status;
2066         }
2067
2068         return 0;
2069 }
2070
2071 static int
2072 hns3_init_ring_with_vector(struct hns3_hw *hw)
2073 {
2074         uint8_t vec;
2075         int ret;
2076         int i;
2077
2078         /*
2079          * In hns3 network engine, vector 0 is always the misc interrupt of this
2080          * function, vector 1~N can be used respectively for the queues of the
2081          * function. Tx and Rx queues with the same number share the interrupt
2082          * vector. In the initialization clearing the all hardware mapping
2083          * relationship configurations between queues and interrupt vectors is
2084          * needed, so some error caused by the residual configurations, such as
2085          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2086          * constraints in hns3 hardware engine, we have to implement clearing
2087          * the mapping relationship configurations by binding all queues to the
2088          * last interrupt vector and reserving the last interrupt vector. This
2089          * method results in a decrease of the maximum queues when upper
2090          * applications call the rte_eth_dev_configure API function to enable
2091          * Rx interrupt.
2092          */
2093         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2094         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
2095         for (i = 0; i < hw->intr_tqps_num; i++) {
2096                 /*
2097                  * Set gap limiter and rate limiter configuration of queue's
2098                  * interrupt.
2099                  */
2100                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2101                                        HNS3_TQP_INTR_GL_DEFAULT);
2102                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2103                                        HNS3_TQP_INTR_GL_DEFAULT);
2104                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2105
2106                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2107                                                  HNS3_RING_TYPE_TX, i);
2108                 if (ret) {
2109                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2110                                           "vector: %d, ret=%d", i, vec, ret);
2111                         return ret;
2112                 }
2113
2114                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2115                                                  HNS3_RING_TYPE_RX, i);
2116                 if (ret) {
2117                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2118                                           "vector: %d, ret=%d", i, vec, ret);
2119                         return ret;
2120                 }
2121         }
2122
2123         return 0;
2124 }
2125
2126 static int
2127 hns3_dev_configure(struct rte_eth_dev *dev)
2128 {
2129         struct hns3_adapter *hns = dev->data->dev_private;
2130         struct rte_eth_conf *conf = &dev->data->dev_conf;
2131         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2132         struct hns3_hw *hw = &hns->hw;
2133         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2134         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2135         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2136         struct rte_eth_rss_conf rss_conf;
2137         uint16_t mtu;
2138         int ret;
2139
2140         /*
2141          * Hardware does not support individually enable/disable/reset the Tx or
2142          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2143          * and Rx queues at the same time. When the numbers of Tx queues
2144          * allocated by upper applications are not equal to the numbers of Rx
2145          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2146          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2147          * these fake queues are imperceptible, and can not be used by upper
2148          * applications.
2149          */
2150         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2151         if (ret) {
2152                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2153                 return ret;
2154         }
2155
2156         hw->adapter_state = HNS3_NIC_CONFIGURING;
2157         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2158                 hns3_err(hw, "setting link speed/duplex not supported");
2159                 ret = -EINVAL;
2160                 goto cfg_err;
2161         }
2162
2163         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2164                 ret = hns3_check_dcb_cfg(dev);
2165                 if (ret)
2166                         goto cfg_err;
2167         }
2168
2169         /* When RSS is not configured, redirect the packet queue 0 */
2170         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2171                 rss_conf = conf->rx_adv_conf.rss_conf;
2172                 if (rss_conf.rss_key == NULL) {
2173                         rss_conf.rss_key = rss_cfg->key;
2174                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2175                 }
2176
2177                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2178                 if (ret)
2179                         goto cfg_err;
2180         }
2181
2182         /*
2183          * If jumbo frames are enabled, MTU needs to be refreshed
2184          * according to the maximum RX packet length.
2185          */
2186         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2187                 /*
2188                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2189                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2190                  * can safely assign to "uint16_t" type variable.
2191                  */
2192                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2193                 ret = hns3_dev_mtu_set(dev, mtu);
2194                 if (ret)
2195                         goto cfg_err;
2196                 dev->data->mtu = mtu;
2197         }
2198
2199         ret = hns3_dev_configure_vlan(dev);
2200         if (ret)
2201                 goto cfg_err;
2202
2203         hw->adapter_state = HNS3_NIC_CONFIGURED;
2204
2205         return 0;
2206
2207 cfg_err:
2208         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2209         hw->adapter_state = HNS3_NIC_INITIALIZED;
2210
2211         return ret;
2212 }
2213
2214 static int
2215 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2216 {
2217         struct hns3_config_max_frm_size_cmd *req;
2218         struct hns3_cmd_desc desc;
2219
2220         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2221
2222         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2223         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2224         req->min_frm_size = RTE_ETHER_MIN_LEN;
2225
2226         return hns3_cmd_send(hw, &desc, 1);
2227 }
2228
2229 static int
2230 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2231 {
2232         int ret;
2233
2234         ret = hns3_set_mac_mtu(hw, mps);
2235         if (ret) {
2236                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2237                 return ret;
2238         }
2239
2240         ret = hns3_buffer_alloc(hw);
2241         if (ret) {
2242                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2243                 return ret;
2244         }
2245
2246         return 0;
2247 }
2248
2249 static int
2250 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2251 {
2252         struct hns3_adapter *hns = dev->data->dev_private;
2253         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2254         struct hns3_hw *hw = &hns->hw;
2255         bool is_jumbo_frame;
2256         int ret;
2257
2258         if (dev->data->dev_started) {
2259                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2260                          "before configuration", dev->data->port_id);
2261                 return -EBUSY;
2262         }
2263
2264         rte_spinlock_lock(&hw->lock);
2265         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2266         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2267
2268         /*
2269          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2270          * assign to "uint16_t" type variable.
2271          */
2272         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2273         if (ret) {
2274                 rte_spinlock_unlock(&hw->lock);
2275                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2276                          dev->data->port_id, mtu, ret);
2277                 return ret;
2278         }
2279         hns->pf.mps = (uint16_t)frame_size;
2280         if (is_jumbo_frame)
2281                 dev->data->dev_conf.rxmode.offloads |=
2282                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2283         else
2284                 dev->data->dev_conf.rxmode.offloads &=
2285                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2286         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2287         rte_spinlock_unlock(&hw->lock);
2288
2289         return 0;
2290 }
2291
2292 static int
2293 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2294 {
2295         struct hns3_adapter *hns = eth_dev->data->dev_private;
2296         struct hns3_hw *hw = &hns->hw;
2297         uint16_t queue_num = hw->tqps_num;
2298
2299         /*
2300          * In interrupt mode, 'max_rx_queues' is set based on the number of
2301          * MSI-X interrupt resources of the hardware.
2302          */
2303         if (hw->data->dev_conf.intr_conf.rxq == 1)
2304                 queue_num = hw->intr_tqps_num;
2305
2306         info->max_rx_queues = queue_num;
2307         info->max_tx_queues = hw->tqps_num;
2308         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2309         info->min_rx_bufsize = hw->rx_buf_len;
2310         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2311         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2312         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2313                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2314                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2315                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2316                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2317                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2318                                  DEV_RX_OFFLOAD_KEEP_CRC |
2319                                  DEV_RX_OFFLOAD_SCATTER |
2320                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2321                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2322                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2323                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2324                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
2325         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2326         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2327                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2328                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2329                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2330                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2331                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2332                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2333                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2334                                  DEV_TX_OFFLOAD_TCP_TSO |
2335                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2336                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2337                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2338                                  info->tx_queue_offload_capa);
2339
2340         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2341                 .nb_max = HNS3_MAX_RING_DESC,
2342                 .nb_min = HNS3_MIN_RING_DESC,
2343                 .nb_align = HNS3_ALIGN_RING_DESC,
2344         };
2345
2346         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2347                 .nb_max = HNS3_MAX_RING_DESC,
2348                 .nb_min = HNS3_MIN_RING_DESC,
2349                 .nb_align = HNS3_ALIGN_RING_DESC,
2350         };
2351
2352         info->vmdq_queue_num = 0;
2353
2354         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2355         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2356         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2357
2358         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2359         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2360         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2361         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2362         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2363         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2364
2365         return 0;
2366 }
2367
2368 static int
2369 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2370                     size_t fw_size)
2371 {
2372         struct hns3_adapter *hns = eth_dev->data->dev_private;
2373         struct hns3_hw *hw = &hns->hw;
2374         int ret;
2375
2376         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2377         ret += 1; /* add the size of '\0' */
2378         if (fw_size < (uint32_t)ret)
2379                 return ret;
2380         else
2381                 return 0;
2382 }
2383
2384 static int
2385 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2386                      __rte_unused int wait_to_complete)
2387 {
2388         struct hns3_adapter *hns = eth_dev->data->dev_private;
2389         struct hns3_hw *hw = &hns->hw;
2390         struct hns3_mac *mac = &hw->mac;
2391         struct rte_eth_link new_link;
2392
2393         if (!hns3_is_reset_pending(hns)) {
2394                 hns3_update_speed_duplex(eth_dev);
2395                 hns3_update_link_status(hw);
2396         }
2397
2398         memset(&new_link, 0, sizeof(new_link));
2399         switch (mac->link_speed) {
2400         case ETH_SPEED_NUM_10M:
2401         case ETH_SPEED_NUM_100M:
2402         case ETH_SPEED_NUM_1G:
2403         case ETH_SPEED_NUM_10G:
2404         case ETH_SPEED_NUM_25G:
2405         case ETH_SPEED_NUM_40G:
2406         case ETH_SPEED_NUM_50G:
2407         case ETH_SPEED_NUM_100G:
2408                 new_link.link_speed = mac->link_speed;
2409                 break;
2410         default:
2411                 new_link.link_speed = ETH_SPEED_NUM_100M;
2412                 break;
2413         }
2414
2415         new_link.link_duplex = mac->link_duplex;
2416         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2417         new_link.link_autoneg =
2418             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2419
2420         return rte_eth_linkstatus_set(eth_dev, &new_link);
2421 }
2422
2423 static int
2424 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2425 {
2426         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2427         struct hns3_pf *pf = &hns->pf;
2428
2429         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2430                 return -EINVAL;
2431
2432         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2433
2434         return 0;
2435 }
2436
2437 static int
2438 hns3_query_function_status(struct hns3_hw *hw)
2439 {
2440 #define HNS3_QUERY_MAX_CNT              10
2441 #define HNS3_QUERY_SLEEP_MSCOEND        1
2442         struct hns3_func_status_cmd *req;
2443         struct hns3_cmd_desc desc;
2444         int timeout = 0;
2445         int ret;
2446
2447         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2448         req = (struct hns3_func_status_cmd *)desc.data;
2449
2450         do {
2451                 ret = hns3_cmd_send(hw, &desc, 1);
2452                 if (ret) {
2453                         PMD_INIT_LOG(ERR, "query function status failed %d",
2454                                      ret);
2455                         return ret;
2456                 }
2457
2458                 /* Check pf reset is done */
2459                 if (req->pf_state)
2460                         break;
2461
2462                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2463         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2464
2465         return hns3_parse_func_status(hw, req);
2466 }
2467
2468 static int
2469 hns3_query_pf_resource(struct hns3_hw *hw)
2470 {
2471         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2472         struct hns3_pf *pf = &hns->pf;
2473         struct hns3_pf_res_cmd *req;
2474         struct hns3_cmd_desc desc;
2475         uint16_t num_msi;
2476         int ret;
2477
2478         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2479         ret = hns3_cmd_send(hw, &desc, 1);
2480         if (ret) {
2481                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2482                 return ret;
2483         }
2484
2485         req = (struct hns3_pf_res_cmd *)desc.data;
2486         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2487         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2488         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2489         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2490
2491         if (req->tx_buf_size)
2492                 pf->tx_buf_size =
2493                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2494         else
2495                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2496
2497         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2498
2499         if (req->dv_buf_size)
2500                 pf->dv_buf_size =
2501                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2502         else
2503                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2504
2505         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2506
2507         num_msi = hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2508                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2509         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
2510
2511         return 0;
2512 }
2513
2514 static void
2515 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2516 {
2517         struct hns3_cfg_param_cmd *req;
2518         uint64_t mac_addr_tmp_high;
2519         uint64_t mac_addr_tmp;
2520         uint32_t i;
2521
2522         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2523
2524         /* get the configuration */
2525         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2526                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2527         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2528                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2529         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2530                                            HNS3_CFG_TQP_DESC_N_M,
2531                                            HNS3_CFG_TQP_DESC_N_S);
2532
2533         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2534                                        HNS3_CFG_PHY_ADDR_M,
2535                                        HNS3_CFG_PHY_ADDR_S);
2536         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2537                                          HNS3_CFG_MEDIA_TP_M,
2538                                          HNS3_CFG_MEDIA_TP_S);
2539         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2540                                          HNS3_CFG_RX_BUF_LEN_M,
2541                                          HNS3_CFG_RX_BUF_LEN_S);
2542         /* get mac address */
2543         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2544         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2545                                            HNS3_CFG_MAC_ADDR_H_M,
2546                                            HNS3_CFG_MAC_ADDR_H_S);
2547
2548         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2549
2550         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2551                                             HNS3_CFG_DEFAULT_SPEED_M,
2552                                             HNS3_CFG_DEFAULT_SPEED_S);
2553         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2554                                            HNS3_CFG_RSS_SIZE_M,
2555                                            HNS3_CFG_RSS_SIZE_S);
2556
2557         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2558                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2559
2560         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2561         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2562
2563         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2564                                             HNS3_CFG_SPEED_ABILITY_M,
2565                                             HNS3_CFG_SPEED_ABILITY_S);
2566         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2567                                         HNS3_CFG_UMV_TBL_SPACE_M,
2568                                         HNS3_CFG_UMV_TBL_SPACE_S);
2569         if (!cfg->umv_space)
2570                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2571 }
2572
2573 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2574  * @hw: pointer to struct hns3_hw
2575  * @hcfg: the config structure to be getted
2576  */
2577 static int
2578 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2579 {
2580         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2581         struct hns3_cfg_param_cmd *req;
2582         uint32_t offset;
2583         uint32_t i;
2584         int ret;
2585
2586         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2587                 offset = 0;
2588                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2589                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2590                                           true);
2591                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2592                                i * HNS3_CFG_RD_LEN_BYTES);
2593                 /* Len should be divided by 4 when send to hardware */
2594                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2595                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2596                 req->offset = rte_cpu_to_le_32(offset);
2597         }
2598
2599         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2600         if (ret) {
2601                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2602                 return ret;
2603         }
2604
2605         hns3_parse_cfg(hcfg, desc);
2606
2607         return 0;
2608 }
2609
2610 static int
2611 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2612 {
2613         switch (speed_cmd) {
2614         case HNS3_CFG_SPEED_10M:
2615                 *speed = ETH_SPEED_NUM_10M;
2616                 break;
2617         case HNS3_CFG_SPEED_100M:
2618                 *speed = ETH_SPEED_NUM_100M;
2619                 break;
2620         case HNS3_CFG_SPEED_1G:
2621                 *speed = ETH_SPEED_NUM_1G;
2622                 break;
2623         case HNS3_CFG_SPEED_10G:
2624                 *speed = ETH_SPEED_NUM_10G;
2625                 break;
2626         case HNS3_CFG_SPEED_25G:
2627                 *speed = ETH_SPEED_NUM_25G;
2628                 break;
2629         case HNS3_CFG_SPEED_40G:
2630                 *speed = ETH_SPEED_NUM_40G;
2631                 break;
2632         case HNS3_CFG_SPEED_50G:
2633                 *speed = ETH_SPEED_NUM_50G;
2634                 break;
2635         case HNS3_CFG_SPEED_100G:
2636                 *speed = ETH_SPEED_NUM_100G;
2637                 break;
2638         default:
2639                 return -EINVAL;
2640         }
2641
2642         return 0;
2643 }
2644
2645 static int
2646 hns3_get_board_configuration(struct hns3_hw *hw)
2647 {
2648         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2649         struct hns3_pf *pf = &hns->pf;
2650         struct hns3_cfg cfg;
2651         int ret;
2652
2653         ret = hns3_get_board_cfg(hw, &cfg);
2654         if (ret) {
2655                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2656                 return ret;
2657         }
2658
2659         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2660                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2661                 return -EOPNOTSUPP;
2662         }
2663
2664         hw->mac.media_type = cfg.media_type;
2665         hw->rss_size_max = cfg.rss_size_max;
2666         hw->rss_dis_flag = false;
2667         hw->rx_buf_len = cfg.rx_buf_len;
2668         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2669         hw->mac.phy_addr = cfg.phy_addr;
2670         hw->mac.default_addr_setted = false;
2671         hw->num_tx_desc = cfg.tqp_desc_num;
2672         hw->num_rx_desc = cfg.tqp_desc_num;
2673         hw->dcb_info.num_pg = 1;
2674         hw->dcb_info.hw_pfc_map = 0;
2675
2676         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2677         if (ret) {
2678                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2679                              cfg.default_speed, ret);
2680                 return ret;
2681         }
2682
2683         pf->tc_max = cfg.tc_num;
2684         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2685                 PMD_INIT_LOG(WARNING,
2686                              "Get TC num(%u) from flash, set TC num to 1",
2687                              pf->tc_max);
2688                 pf->tc_max = 1;
2689         }
2690
2691         /* Dev does not support DCB */
2692         if (!hns3_dev_dcb_supported(hw)) {
2693                 pf->tc_max = 1;
2694                 pf->pfc_max = 0;
2695         } else
2696                 pf->pfc_max = pf->tc_max;
2697
2698         hw->dcb_info.num_tc = 1;
2699         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2700                                      hw->tqps_num / hw->dcb_info.num_tc);
2701         hns3_set_bit(hw->hw_tc_map, 0, 1);
2702         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2703
2704         pf->wanted_umv_size = cfg.umv_space;
2705
2706         return ret;
2707 }
2708
2709 static int
2710 hns3_get_configuration(struct hns3_hw *hw)
2711 {
2712         int ret;
2713
2714         ret = hns3_query_function_status(hw);
2715         if (ret) {
2716                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2717                 return ret;
2718         }
2719
2720         /* Get pf resource */
2721         ret = hns3_query_pf_resource(hw);
2722         if (ret) {
2723                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2724                 return ret;
2725         }
2726
2727         ret = hns3_get_board_configuration(hw);
2728         if (ret) {
2729                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2730                 return ret;
2731         }
2732
2733         return 0;
2734 }
2735
2736 static int
2737 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2738                       uint16_t tqp_vid, bool is_pf)
2739 {
2740         struct hns3_tqp_map_cmd *req;
2741         struct hns3_cmd_desc desc;
2742         int ret;
2743
2744         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2745
2746         req = (struct hns3_tqp_map_cmd *)desc.data;
2747         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2748         req->tqp_vf = func_id;
2749         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2750         if (!is_pf)
2751                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2752         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2753
2754         ret = hns3_cmd_send(hw, &desc, 1);
2755         if (ret)
2756                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2757
2758         return ret;
2759 }
2760
2761 static int
2762 hns3_map_tqp(struct hns3_hw *hw)
2763 {
2764         uint16_t tqps_num = hw->total_tqps_num;
2765         uint16_t func_id;
2766         uint16_t tqp_id;
2767         bool is_pf;
2768         int num;
2769         int ret;
2770         int i;
2771
2772         /*
2773          * In current version VF is not supported when PF is driven by DPDK
2774          * driver, so we allocate tqps to PF as much as possible.
2775          */
2776         tqp_id = 0;
2777         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2778         for (func_id = 0; func_id < num; func_id++) {
2779                 is_pf = func_id == 0 ? true : false;
2780                 for (i = 0;
2781                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2782                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2783                                                     is_pf);
2784                         if (ret)
2785                                 return ret;
2786                 }
2787         }
2788
2789         return 0;
2790 }
2791
2792 static int
2793 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2794 {
2795         struct hns3_config_mac_speed_dup_cmd *req;
2796         struct hns3_cmd_desc desc;
2797         int ret;
2798
2799         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2800
2801         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2802
2803         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2804
2805         switch (speed) {
2806         case ETH_SPEED_NUM_10M:
2807                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2808                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2809                 break;
2810         case ETH_SPEED_NUM_100M:
2811                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2812                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2813                 break;
2814         case ETH_SPEED_NUM_1G:
2815                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2816                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2817                 break;
2818         case ETH_SPEED_NUM_10G:
2819                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2820                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2821                 break;
2822         case ETH_SPEED_NUM_25G:
2823                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2824                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2825                 break;
2826         case ETH_SPEED_NUM_40G:
2827                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2828                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2829                 break;
2830         case ETH_SPEED_NUM_50G:
2831                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2832                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2833                 break;
2834         case ETH_SPEED_NUM_100G:
2835                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2836                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2837                 break;
2838         default:
2839                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2840                 return -EINVAL;
2841         }
2842
2843         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2844
2845         ret = hns3_cmd_send(hw, &desc, 1);
2846         if (ret)
2847                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2848
2849         return ret;
2850 }
2851
2852 static int
2853 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2854 {
2855         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2856         struct hns3_pf *pf = &hns->pf;
2857         struct hns3_priv_buf *priv;
2858         uint32_t i, total_size;
2859
2860         total_size = pf->pkt_buf_size;
2861
2862         /* alloc tx buffer for all enabled tc */
2863         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2864                 priv = &buf_alloc->priv_buf[i];
2865
2866                 if (hw->hw_tc_map & BIT(i)) {
2867                         if (total_size < pf->tx_buf_size)
2868                                 return -ENOMEM;
2869
2870                         priv->tx_buf_size = pf->tx_buf_size;
2871                 } else
2872                         priv->tx_buf_size = 0;
2873
2874                 total_size -= priv->tx_buf_size;
2875         }
2876
2877         return 0;
2878 }
2879
2880 static int
2881 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2882 {
2883 /* TX buffer size is unit by 128 byte */
2884 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
2885 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
2886         struct hns3_tx_buff_alloc_cmd *req;
2887         struct hns3_cmd_desc desc;
2888         uint32_t buf_size;
2889         uint32_t i;
2890         int ret;
2891
2892         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2893
2894         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2895         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2896                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2897
2898                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2899                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2900                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2901         }
2902
2903         ret = hns3_cmd_send(hw, &desc, 1);
2904         if (ret)
2905                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2906
2907         return ret;
2908 }
2909
2910 static int
2911 hns3_get_tc_num(struct hns3_hw *hw)
2912 {
2913         int cnt = 0;
2914         uint8_t i;
2915
2916         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2917                 if (hw->hw_tc_map & BIT(i))
2918                         cnt++;
2919         return cnt;
2920 }
2921
2922 static uint32_t
2923 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2924 {
2925         struct hns3_priv_buf *priv;
2926         uint32_t rx_priv = 0;
2927         int i;
2928
2929         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2930                 priv = &buf_alloc->priv_buf[i];
2931                 if (priv->enable)
2932                         rx_priv += priv->buf_size;
2933         }
2934         return rx_priv;
2935 }
2936
2937 static uint32_t
2938 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2939 {
2940         uint32_t total_tx_size = 0;
2941         uint32_t i;
2942
2943         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2944                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2945
2946         return total_tx_size;
2947 }
2948
2949 /* Get the number of pfc enabled TCs, which have private buffer */
2950 static int
2951 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2952 {
2953         struct hns3_priv_buf *priv;
2954         int cnt = 0;
2955         uint8_t i;
2956
2957         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2958                 priv = &buf_alloc->priv_buf[i];
2959                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2960                         cnt++;
2961         }
2962
2963         return cnt;
2964 }
2965
2966 /* Get the number of pfc disabled TCs, which have private buffer */
2967 static int
2968 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2969                          struct hns3_pkt_buf_alloc *buf_alloc)
2970 {
2971         struct hns3_priv_buf *priv;
2972         int cnt = 0;
2973         uint8_t i;
2974
2975         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2976                 priv = &buf_alloc->priv_buf[i];
2977                 if (hw->hw_tc_map & BIT(i) &&
2978                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2979                         cnt++;
2980         }
2981
2982         return cnt;
2983 }
2984
2985 static bool
2986 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2987                   uint32_t rx_all)
2988 {
2989         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2990         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2991         struct hns3_pf *pf = &hns->pf;
2992         uint32_t shared_buf, aligned_mps;
2993         uint32_t rx_priv;
2994         uint8_t tc_num;
2995         uint8_t i;
2996
2997         tc_num = hns3_get_tc_num(hw);
2998         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2999
3000         if (hns3_dev_dcb_supported(hw))
3001                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3002                                         pf->dv_buf_size;
3003         else
3004                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3005                                         + pf->dv_buf_size;
3006
3007         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3008         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3009                              HNS3_BUF_SIZE_UNIT);
3010
3011         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3012         if (rx_all < rx_priv + shared_std)
3013                 return false;
3014
3015         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3016         buf_alloc->s_buf.buf_size = shared_buf;
3017         if (hns3_dev_dcb_supported(hw)) {
3018                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3019                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3020                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3021                                   HNS3_BUF_SIZE_UNIT);
3022         } else {
3023                 buf_alloc->s_buf.self.high =
3024                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3025                 buf_alloc->s_buf.self.low = aligned_mps;
3026         }
3027
3028         if (hns3_dev_dcb_supported(hw)) {
3029                 hi_thrd = shared_buf - pf->dv_buf_size;
3030
3031                 if (tc_num <= NEED_RESERVE_TC_NUM)
3032                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3033                                         / BUF_MAX_PERCENT;
3034
3035                 if (tc_num)
3036                         hi_thrd = hi_thrd / tc_num;
3037
3038                 hi_thrd = max_t(uint32_t, hi_thrd,
3039                                 HNS3_BUF_MUL_BY * aligned_mps);
3040                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3041                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3042         } else {
3043                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3044                 lo_thrd = aligned_mps;
3045         }
3046
3047         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3048                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3049                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3050         }
3051
3052         return true;
3053 }
3054
3055 static bool
3056 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3057                      struct hns3_pkt_buf_alloc *buf_alloc)
3058 {
3059         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3060         struct hns3_pf *pf = &hns->pf;
3061         struct hns3_priv_buf *priv;
3062         uint32_t aligned_mps;
3063         uint32_t rx_all;
3064         uint8_t i;
3065
3066         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3067         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3068
3069         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3070                 priv = &buf_alloc->priv_buf[i];
3071
3072                 priv->enable = 0;
3073                 priv->wl.low = 0;
3074                 priv->wl.high = 0;
3075                 priv->buf_size = 0;
3076
3077                 if (!(hw->hw_tc_map & BIT(i)))
3078                         continue;
3079
3080                 priv->enable = 1;
3081                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3082                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3083                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3084                                                 HNS3_BUF_SIZE_UNIT);
3085                 } else {
3086                         priv->wl.low = 0;
3087                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3088                                         aligned_mps;
3089                 }
3090
3091                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3092         }
3093
3094         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3095 }
3096
3097 static bool
3098 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3099                              struct hns3_pkt_buf_alloc *buf_alloc)
3100 {
3101         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3102         struct hns3_pf *pf = &hns->pf;
3103         struct hns3_priv_buf *priv;
3104         int no_pfc_priv_num;
3105         uint32_t rx_all;
3106         uint8_t mask;
3107         int i;
3108
3109         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3110         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3111
3112         /* let the last to be cleared first */
3113         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3114                 priv = &buf_alloc->priv_buf[i];
3115                 mask = BIT((uint8_t)i);
3116
3117                 if (hw->hw_tc_map & mask &&
3118                     !(hw->dcb_info.hw_pfc_map & mask)) {
3119                         /* Clear the no pfc TC private buffer */
3120                         priv->wl.low = 0;
3121                         priv->wl.high = 0;
3122                         priv->buf_size = 0;
3123                         priv->enable = 0;
3124                         no_pfc_priv_num--;
3125                 }
3126
3127                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3128                     no_pfc_priv_num == 0)
3129                         break;
3130         }
3131
3132         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3133 }
3134
3135 static bool
3136 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3137                            struct hns3_pkt_buf_alloc *buf_alloc)
3138 {
3139         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3140         struct hns3_pf *pf = &hns->pf;
3141         struct hns3_priv_buf *priv;
3142         uint32_t rx_all;
3143         int pfc_priv_num;
3144         uint8_t mask;
3145         int i;
3146
3147         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3148         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3149
3150         /* let the last to be cleared first */
3151         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3152                 priv = &buf_alloc->priv_buf[i];
3153                 mask = BIT((uint8_t)i);
3154
3155                 if (hw->hw_tc_map & mask &&
3156                     hw->dcb_info.hw_pfc_map & mask) {
3157                         /* Reduce the number of pfc TC with private buffer */
3158                         priv->wl.low = 0;
3159                         priv->enable = 0;
3160                         priv->wl.high = 0;
3161                         priv->buf_size = 0;
3162                         pfc_priv_num--;
3163                 }
3164                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3165                     pfc_priv_num == 0)
3166                         break;
3167         }
3168
3169         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3170 }
3171
3172 static bool
3173 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3174                           struct hns3_pkt_buf_alloc *buf_alloc)
3175 {
3176 #define COMPENSATE_BUFFER       0x3C00
3177 #define COMPENSATE_HALF_MPS_NUM 5
3178 #define PRIV_WL_GAP             0x1800
3179         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3180         struct hns3_pf *pf = &hns->pf;
3181         uint32_t tc_num = hns3_get_tc_num(hw);
3182         uint32_t half_mps = pf->mps >> 1;
3183         struct hns3_priv_buf *priv;
3184         uint32_t min_rx_priv;
3185         uint32_t rx_priv;
3186         uint8_t i;
3187
3188         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3189         if (tc_num)
3190                 rx_priv = rx_priv / tc_num;
3191
3192         if (tc_num <= NEED_RESERVE_TC_NUM)
3193                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3194
3195         /*
3196          * Minimum value of private buffer in rx direction (min_rx_priv) is
3197          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3198          * buffer if rx_priv is greater than min_rx_priv.
3199          */
3200         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3201                         COMPENSATE_HALF_MPS_NUM * half_mps;
3202         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3203         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3204
3205         if (rx_priv < min_rx_priv)
3206                 return false;
3207
3208         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3209                 priv = &buf_alloc->priv_buf[i];
3210
3211                 priv->enable = 0;
3212                 priv->wl.low = 0;
3213                 priv->wl.high = 0;
3214                 priv->buf_size = 0;
3215
3216                 if (!(hw->hw_tc_map & BIT(i)))
3217                         continue;
3218
3219                 priv->enable = 1;
3220                 priv->buf_size = rx_priv;
3221                 priv->wl.high = rx_priv - pf->dv_buf_size;
3222                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3223         }
3224
3225         buf_alloc->s_buf.buf_size = 0;
3226
3227         return true;
3228 }
3229
3230 /*
3231  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3232  * @hw: pointer to struct hns3_hw
3233  * @buf_alloc: pointer to buffer calculation data
3234  * @return: 0: calculate sucessful, negative: fail
3235  */
3236 static int
3237 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3238 {
3239         /* When DCB is not supported, rx private buffer is not allocated. */
3240         if (!hns3_dev_dcb_supported(hw)) {
3241                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3242                 struct hns3_pf *pf = &hns->pf;
3243                 uint32_t rx_all = pf->pkt_buf_size;
3244
3245                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3246                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3247                         return -ENOMEM;
3248
3249                 return 0;
3250         }
3251
3252         /*
3253          * Try to allocate privated packet buffer for all TCs without share
3254          * buffer.
3255          */
3256         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3257                 return 0;
3258
3259         /*
3260          * Try to allocate privated packet buffer for all TCs with share
3261          * buffer.
3262          */
3263         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3264                 return 0;
3265
3266         /*
3267          * For different application scenes, the enabled port number, TC number
3268          * and no_drop TC number are different. In order to obtain the better
3269          * performance, software could allocate the buffer size and configure
3270          * the waterline by tring to decrease the private buffer size according
3271          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3272          * enabled tc.
3273          */
3274         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3275                 return 0;
3276
3277         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3278                 return 0;
3279
3280         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3281                 return 0;
3282
3283         return -ENOMEM;
3284 }
3285
3286 static int
3287 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3288 {
3289         struct hns3_rx_priv_buff_cmd *req;
3290         struct hns3_cmd_desc desc;
3291         uint32_t buf_size;
3292         int ret;
3293         int i;
3294
3295         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3296         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3297
3298         /* Alloc private buffer TCs */
3299         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3300                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3301
3302                 req->buf_num[i] =
3303                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3304                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3305         }
3306
3307         buf_size = buf_alloc->s_buf.buf_size;
3308         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3309                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3310
3311         ret = hns3_cmd_send(hw, &desc, 1);
3312         if (ret)
3313                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3314
3315         return ret;
3316 }
3317
3318 static int
3319 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3320 {
3321 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3322         struct hns3_rx_priv_wl_buf *req;
3323         struct hns3_priv_buf *priv;
3324         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3325         int i, j;
3326         int ret;
3327
3328         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3329                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3330                                           false);
3331                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3332
3333                 /* The first descriptor set the NEXT bit to 1 */
3334                 if (i == 0)
3335                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3336                 else
3337                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3338
3339                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3340                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3341
3342                         priv = &buf_alloc->priv_buf[idx];
3343                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3344                                                         HNS3_BUF_UNIT_S);
3345                         req->tc_wl[j].high |=
3346                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3347                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3348                                                         HNS3_BUF_UNIT_S);
3349                         req->tc_wl[j].low |=
3350                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3351                 }
3352         }
3353
3354         /* Send 2 descriptor at one time */
3355         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3356         if (ret)
3357                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3358                              ret);
3359         return ret;
3360 }
3361
3362 static int
3363 hns3_common_thrd_config(struct hns3_hw *hw,
3364                         struct hns3_pkt_buf_alloc *buf_alloc)
3365 {
3366 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3367         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3368         struct hns3_rx_com_thrd *req;
3369         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3370         struct hns3_tc_thrd *tc;
3371         int tc_idx;
3372         int i, j;
3373         int ret;
3374
3375         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3376                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3377                                           false);
3378                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3379
3380                 /* The first descriptor set the NEXT bit to 1 */
3381                 if (i == 0)
3382                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3383                 else
3384                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3385
3386                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3387                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3388                         tc = &s_buf->tc_thrd[tc_idx];
3389
3390                         req->com_thrd[j].high =
3391                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3392                         req->com_thrd[j].high |=
3393                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3394                         req->com_thrd[j].low =
3395                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3396                         req->com_thrd[j].low |=
3397                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3398                 }
3399         }
3400
3401         /* Send 2 descriptors at one time */
3402         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3403         if (ret)
3404                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3405
3406         return ret;
3407 }
3408
3409 static int
3410 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3411 {
3412         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3413         struct hns3_rx_com_wl *req;
3414         struct hns3_cmd_desc desc;
3415         int ret;
3416
3417         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3418
3419         req = (struct hns3_rx_com_wl *)desc.data;
3420         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3421         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3422
3423         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3424         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3425
3426         ret = hns3_cmd_send(hw, &desc, 1);
3427         if (ret)
3428                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3429
3430         return ret;
3431 }
3432
3433 int
3434 hns3_buffer_alloc(struct hns3_hw *hw)
3435 {
3436         struct hns3_pkt_buf_alloc pkt_buf;
3437         int ret;
3438
3439         memset(&pkt_buf, 0, sizeof(pkt_buf));
3440         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3441         if (ret) {
3442                 PMD_INIT_LOG(ERR,
3443                              "could not calc tx buffer size for all TCs %d",
3444                              ret);
3445                 return ret;
3446         }
3447
3448         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3449         if (ret) {
3450                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3451                 return ret;
3452         }
3453
3454         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3455         if (ret) {
3456                 PMD_INIT_LOG(ERR,
3457                              "could not calc rx priv buffer size for all TCs %d",
3458                              ret);
3459                 return ret;
3460         }
3461
3462         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3463         if (ret) {
3464                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3465                 return ret;
3466         }
3467
3468         if (hns3_dev_dcb_supported(hw)) {
3469                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3470                 if (ret) {
3471                         PMD_INIT_LOG(ERR,
3472                                      "could not configure rx private waterline %d",
3473                                      ret);
3474                         return ret;
3475                 }
3476
3477                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3478                 if (ret) {
3479                         PMD_INIT_LOG(ERR,
3480                                      "could not configure common threshold %d",
3481                                      ret);
3482                         return ret;
3483                 }
3484         }
3485
3486         ret = hns3_common_wl_config(hw, &pkt_buf);
3487         if (ret)
3488                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3489                              ret);
3490
3491         return ret;
3492 }
3493
3494 static int
3495 hns3_mac_init(struct hns3_hw *hw)
3496 {
3497         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3498         struct hns3_mac *mac = &hw->mac;
3499         struct hns3_pf *pf = &hns->pf;
3500         int ret;
3501
3502         pf->support_sfp_query = true;
3503         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3504         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3505         if (ret) {
3506                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3507                 return ret;
3508         }
3509
3510         mac->link_status = ETH_LINK_DOWN;
3511
3512         return hns3_config_mtu(hw, pf->mps);
3513 }
3514
3515 static int
3516 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3517 {
3518 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3519 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3520 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3521 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3522         int return_status;
3523
3524         if (cmdq_resp) {
3525                 PMD_INIT_LOG(ERR,
3526                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3527                              cmdq_resp);
3528                 return -EIO;
3529         }
3530
3531         switch (resp_code) {
3532         case HNS3_ETHERTYPE_SUCCESS_ADD:
3533         case HNS3_ETHERTYPE_ALREADY_ADD:
3534                 return_status = 0;
3535                 break;
3536         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3537                 PMD_INIT_LOG(ERR,
3538                              "add mac ethertype failed for manager table overflow.");
3539                 return_status = -EIO;
3540                 break;
3541         case HNS3_ETHERTYPE_KEY_CONFLICT:
3542                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3543                 return_status = -EIO;
3544                 break;
3545         default:
3546                 PMD_INIT_LOG(ERR,
3547                              "add mac ethertype failed for undefined, code=%d.",
3548                              resp_code);
3549                 return_status = -EIO;
3550         }
3551
3552         return return_status;
3553 }
3554
3555 static int
3556 hns3_add_mgr_tbl(struct hns3_hw *hw,
3557                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3558 {
3559         struct hns3_cmd_desc desc;
3560         uint8_t resp_code;
3561         uint16_t retval;
3562         int ret;
3563
3564         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3565         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3566
3567         ret = hns3_cmd_send(hw, &desc, 1);
3568         if (ret) {
3569                 PMD_INIT_LOG(ERR,
3570                              "add mac ethertype failed for cmd_send, ret =%d.",
3571                              ret);
3572                 return ret;
3573         }
3574
3575         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3576         retval = rte_le_to_cpu_16(desc.retval);
3577
3578         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3579 }
3580
3581 static void
3582 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3583                      int *table_item_num)
3584 {
3585         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3586
3587         /*
3588          * In current version, we add one item in management table as below:
3589          * 0x0180C200000E -- LLDP MC address
3590          */
3591         tbl = mgr_table;
3592         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3593         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3594         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3595         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3596         tbl->i_port_bitmap = 0x1;
3597         *table_item_num = 1;
3598 }
3599
3600 static int
3601 hns3_init_mgr_tbl(struct hns3_hw *hw)
3602 {
3603 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3604         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3605         int table_item_num;
3606         int ret;
3607         int i;
3608
3609         memset(mgr_table, 0, sizeof(mgr_table));
3610         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3611         for (i = 0; i < table_item_num; i++) {
3612                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3613                 if (ret) {
3614                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3615                                      ret);
3616                         return ret;
3617                 }
3618         }
3619
3620         return 0;
3621 }
3622
3623 static void
3624 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3625                         bool en_mc, bool en_bc, int vport_id)
3626 {
3627         if (!param)
3628                 return;
3629
3630         memset(param, 0, sizeof(struct hns3_promisc_param));
3631         if (en_uc)
3632                 param->enable = HNS3_PROMISC_EN_UC;
3633         if (en_mc)
3634                 param->enable |= HNS3_PROMISC_EN_MC;
3635         if (en_bc)
3636                 param->enable |= HNS3_PROMISC_EN_BC;
3637         param->vf_id = vport_id;
3638 }
3639
3640 static int
3641 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3642 {
3643         struct hns3_promisc_cfg_cmd *req;
3644         struct hns3_cmd_desc desc;
3645         int ret;
3646
3647         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3648
3649         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3650         req->vf_id = param->vf_id;
3651         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3652             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3653
3654         ret = hns3_cmd_send(hw, &desc, 1);
3655         if (ret)
3656                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3657
3658         return ret;
3659 }
3660
3661 static int
3662 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3663 {
3664         struct hns3_promisc_param param;
3665         bool en_bc_pmc = true;
3666         uint8_t vf_id;
3667         int ret;
3668
3669         /*
3670          * In current version VF is not supported when PF is driven by DPDK
3671          * driver, the PF-related vf_id is 0, just need to configure parameters
3672          * for vf_id 0.
3673          */
3674         vf_id = 0;
3675
3676         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3677         ret = hns3_cmd_set_promisc_mode(hw, &param);
3678         if (ret)
3679                 return ret;
3680
3681         return 0;
3682 }
3683
3684 static int
3685 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3686 {
3687         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3688         struct hns3_pf *pf = &hns->pf;
3689         struct hns3_promisc_param param;
3690         uint16_t func_id;
3691         int ret;
3692
3693         /* func_id 0 is denoted PF, the VFs start from 1 */
3694         for (func_id = 1; func_id < pf->func_num; func_id++) {
3695                 hns3_promisc_param_init(&param, false, false, false, func_id);
3696                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3697                 if (ret)
3698                         return ret;
3699         }
3700
3701         return 0;
3702 }
3703
3704 static int
3705 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3706 {
3707         struct hns3_adapter *hns = dev->data->dev_private;
3708         struct hns3_hw *hw = &hns->hw;
3709         int ret;
3710
3711         rte_spinlock_lock(&hw->lock);
3712         ret = hns3_set_promisc_mode(hw, true, true);
3713         rte_spinlock_unlock(&hw->lock);
3714         if (ret)
3715                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
3716                          ret);
3717
3718         return ret;
3719 }
3720
3721 static int
3722 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3723 {
3724         bool allmulti = dev->data->all_multicast ? true : false;
3725         struct hns3_adapter *hns = dev->data->dev_private;
3726         struct hns3_hw *hw = &hns->hw;
3727         int ret;
3728
3729         /* If now in all_multicast mode, must remain in all_multicast mode. */
3730         rte_spinlock_lock(&hw->lock);
3731         ret = hns3_set_promisc_mode(hw, false, allmulti);
3732         rte_spinlock_unlock(&hw->lock);
3733         if (ret)
3734                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
3735                          ret);
3736
3737         return ret;
3738 }
3739
3740 static int
3741 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3742 {
3743         struct hns3_adapter *hns = dev->data->dev_private;
3744         struct hns3_hw *hw = &hns->hw;
3745         int ret;
3746
3747         if (dev->data->promiscuous)
3748                 return 0;
3749
3750         rte_spinlock_lock(&hw->lock);
3751         ret = hns3_set_promisc_mode(hw, false, true);
3752         rte_spinlock_unlock(&hw->lock);
3753         if (ret)
3754                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
3755                          ret);
3756
3757         return ret;
3758 }
3759
3760 static int
3761 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3762 {
3763         struct hns3_adapter *hns = dev->data->dev_private;
3764         struct hns3_hw *hw = &hns->hw;
3765         int ret;
3766
3767         /* If now in promiscuous mode, must remain in all_multicast mode. */
3768         if (dev->data->promiscuous)
3769                 return 0;
3770
3771         rte_spinlock_lock(&hw->lock);
3772         ret = hns3_set_promisc_mode(hw, false, false);
3773         rte_spinlock_unlock(&hw->lock);
3774         if (ret)
3775                 hns3_err(hw, "Failed to disable allmulticast mode, ret =  %d",
3776                          ret);
3777
3778         return ret;
3779 }
3780
3781 static int
3782 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3783 {
3784         struct hns3_hw *hw = &hns->hw;
3785         bool allmulti = hw->data->all_multicast ? true : false;
3786
3787         if (hw->data->promiscuous)
3788                 return hns3_set_promisc_mode(hw, true, true);
3789
3790         return hns3_set_promisc_mode(hw, false, allmulti);
3791 }
3792
3793 static int
3794 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3795 {
3796         struct hns3_sfp_speed_cmd *resp;
3797         struct hns3_cmd_desc desc;
3798         int ret;
3799
3800         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3801         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3802         ret = hns3_cmd_send(hw, &desc, 1);
3803         if (ret == -EOPNOTSUPP) {
3804                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3805                 return ret;
3806         } else if (ret) {
3807                 hns3_err(hw, "get sfp speed failed %d", ret);
3808                 return ret;
3809         }
3810
3811         *speed = resp->sfp_speed;
3812
3813         return 0;
3814 }
3815
3816 static uint8_t
3817 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3818 {
3819         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3820                 duplex = ETH_LINK_FULL_DUPLEX;
3821
3822         return duplex;
3823 }
3824
3825 static int
3826 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3827 {
3828         struct hns3_mac *mac = &hw->mac;
3829         int ret;
3830
3831         duplex = hns3_check_speed_dup(duplex, speed);
3832         if (mac->link_speed == speed && mac->link_duplex == duplex)
3833                 return 0;
3834
3835         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3836         if (ret)
3837                 return ret;
3838
3839         mac->link_speed = speed;
3840         mac->link_duplex = duplex;
3841
3842         return 0;
3843 }
3844
3845 static int
3846 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3847 {
3848         struct hns3_adapter *hns = eth_dev->data->dev_private;
3849         struct hns3_hw *hw = &hns->hw;
3850         struct hns3_pf *pf = &hns->pf;
3851         uint32_t speed;
3852         int ret;
3853
3854         /* If IMP do not support get SFP/qSFP speed, return directly */
3855         if (!pf->support_sfp_query)
3856                 return 0;
3857
3858         ret = hns3_get_sfp_speed(hw, &speed);
3859         if (ret == -EOPNOTSUPP) {
3860                 pf->support_sfp_query = false;
3861                 return ret;
3862         } else if (ret)
3863                 return ret;
3864
3865         if (speed == ETH_SPEED_NUM_NONE)
3866                 return 0; /* do nothing if no SFP */
3867
3868         /* Config full duplex for SFP */
3869         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3870 }
3871
3872 static int
3873 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3874 {
3875         struct hns3_config_mac_mode_cmd *req;
3876         struct hns3_cmd_desc desc;
3877         uint32_t loop_en = 0;
3878         uint8_t val = 0;
3879         int ret;
3880
3881         req = (struct hns3_config_mac_mode_cmd *)desc.data;
3882
3883         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3884         if (enable)
3885                 val = 1;
3886         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3887         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3888         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3889         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3890         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3891         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3892         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3893         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3894         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3895         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3896         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3897         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3898         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3899         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3900         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3901
3902         ret = hns3_cmd_send(hw, &desc, 1);
3903         if (ret)
3904                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3905
3906         return ret;
3907 }
3908
3909 static int
3910 hns3_get_mac_link_status(struct hns3_hw *hw)
3911 {
3912         struct hns3_link_status_cmd *req;
3913         struct hns3_cmd_desc desc;
3914         int link_status;
3915         int ret;
3916
3917         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3918         ret = hns3_cmd_send(hw, &desc, 1);
3919         if (ret) {
3920                 hns3_err(hw, "get link status cmd failed %d", ret);
3921                 return ETH_LINK_DOWN;
3922         }
3923
3924         req = (struct hns3_link_status_cmd *)desc.data;
3925         link_status = req->status & HNS3_LINK_STATUS_UP_M;
3926
3927         return !!link_status;
3928 }
3929
3930 void
3931 hns3_update_link_status(struct hns3_hw *hw)
3932 {
3933         int state;
3934
3935         state = hns3_get_mac_link_status(hw);
3936         if (state != hw->mac.link_status) {
3937                 hw->mac.link_status = state;
3938                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
3939         }
3940 }
3941
3942 static void
3943 hns3_service_handler(void *param)
3944 {
3945         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3946         struct hns3_adapter *hns = eth_dev->data->dev_private;
3947         struct hns3_hw *hw = &hns->hw;
3948
3949         if (!hns3_is_reset_pending(hns)) {
3950                 hns3_update_speed_duplex(eth_dev);
3951                 hns3_update_link_status(hw);
3952         } else
3953                 hns3_warn(hw, "Cancel the query when reset is pending");
3954
3955         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3956 }
3957
3958 static int
3959 hns3_init_hardware(struct hns3_adapter *hns)
3960 {
3961         struct hns3_hw *hw = &hns->hw;
3962         int ret;
3963
3964         ret = hns3_map_tqp(hw);
3965         if (ret) {
3966                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3967                 return ret;
3968         }
3969
3970         ret = hns3_init_umv_space(hw);
3971         if (ret) {
3972                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3973                 return ret;
3974         }
3975
3976         ret = hns3_mac_init(hw);
3977         if (ret) {
3978                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3979                 goto err_mac_init;
3980         }
3981
3982         ret = hns3_init_mgr_tbl(hw);
3983         if (ret) {
3984                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3985                 goto err_mac_init;
3986         }
3987
3988         ret = hns3_set_promisc_mode(hw, false, false);
3989         if (ret) {
3990                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3991                 goto err_mac_init;
3992         }
3993
3994         ret = hns3_clear_all_vfs_promisc_mode(hw);
3995         if (ret) {
3996                 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
3997                              ret);
3998                 goto err_mac_init;
3999         }
4000
4001         ret = hns3_init_vlan_config(hns);
4002         if (ret) {
4003                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4004                 goto err_mac_init;
4005         }
4006
4007         ret = hns3_dcb_init(hw);
4008         if (ret) {
4009                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4010                 goto err_mac_init;
4011         }
4012
4013         ret = hns3_init_fd_config(hns);
4014         if (ret) {
4015                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4016                 goto err_mac_init;
4017         }
4018
4019         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4020         if (ret) {
4021                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4022                 goto err_mac_init;
4023         }
4024
4025         ret = hns3_config_gro(hw, false);
4026         if (ret) {
4027                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4028                 goto err_mac_init;
4029         }
4030         return 0;
4031
4032 err_mac_init:
4033         hns3_uninit_umv_space(hw);
4034         return ret;
4035 }
4036
4037 static int
4038 hns3_init_pf(struct rte_eth_dev *eth_dev)
4039 {
4040         struct rte_device *dev = eth_dev->device;
4041         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4042         struct hns3_adapter *hns = eth_dev->data->dev_private;
4043         struct hns3_hw *hw = &hns->hw;
4044         int ret;
4045
4046         PMD_INIT_FUNC_TRACE();
4047
4048         /* Get hardware io base address from pcie BAR2 IO space */
4049         hw->io_base = pci_dev->mem_resource[2].addr;
4050
4051         /* Firmware command queue initialize */
4052         ret = hns3_cmd_init_queue(hw);
4053         if (ret) {
4054                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4055                 goto err_cmd_init_queue;
4056         }
4057
4058         hns3_clear_all_event_cause(hw);
4059
4060         /* Firmware command initialize */
4061         ret = hns3_cmd_init(hw);
4062         if (ret) {
4063                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4064                 goto err_cmd_init;
4065         }
4066
4067         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4068                                          hns3_interrupt_handler,
4069                                          eth_dev);
4070         if (ret) {
4071                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4072                 goto err_intr_callback_register;
4073         }
4074
4075         /* Enable interrupt */
4076         rte_intr_enable(&pci_dev->intr_handle);
4077         hns3_pf_enable_irq0(hw);
4078
4079         /* Get configuration */
4080         ret = hns3_get_configuration(hw);
4081         if (ret) {
4082                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4083                 goto err_get_config;
4084         }
4085
4086         ret = hns3_init_hardware(hns);
4087         if (ret) {
4088                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4089                 goto err_get_config;
4090         }
4091
4092         /* Initialize flow director filter list & hash */
4093         ret = hns3_fdir_filter_init(hns);
4094         if (ret) {
4095                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4096                 goto err_hw_init;
4097         }
4098
4099         hns3_set_default_rss_args(hw);
4100
4101         ret = hns3_enable_hw_error_intr(hns, true);
4102         if (ret) {
4103                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4104                              ret);
4105                 goto err_fdir;
4106         }
4107
4108         /*
4109          * In the initialization clearing the all hardware mapping relationship
4110          * configurations between queues and interrupt vectors is needed, so
4111          * some error caused by the residual configurations, such as the
4112          * unexpected interrupt, can be avoid.
4113          */
4114         ret = hns3_init_ring_with_vector(hw);
4115         if (ret)
4116                 goto err_fdir;
4117
4118         return 0;
4119
4120 err_fdir:
4121         hns3_fdir_filter_uninit(hns);
4122 err_hw_init:
4123         hns3_uninit_umv_space(hw);
4124
4125 err_get_config:
4126         hns3_pf_disable_irq0(hw);
4127         rte_intr_disable(&pci_dev->intr_handle);
4128         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4129                              eth_dev);
4130 err_intr_callback_register:
4131 err_cmd_init:
4132         hns3_cmd_uninit(hw);
4133         hns3_cmd_destroy_queue(hw);
4134 err_cmd_init_queue:
4135         hw->io_base = NULL;
4136
4137         return ret;
4138 }
4139
4140 static void
4141 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4142 {
4143         struct hns3_adapter *hns = eth_dev->data->dev_private;
4144         struct rte_device *dev = eth_dev->device;
4145         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4146         struct hns3_hw *hw = &hns->hw;
4147
4148         PMD_INIT_FUNC_TRACE();
4149
4150         hns3_enable_hw_error_intr(hns, false);
4151         hns3_rss_uninit(hns);
4152         hns3_fdir_filter_uninit(hns);
4153         hns3_uninit_umv_space(hw);
4154         hns3_pf_disable_irq0(hw);
4155         rte_intr_disable(&pci_dev->intr_handle);
4156         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4157                              eth_dev);
4158         hns3_cmd_uninit(hw);
4159         hns3_cmd_destroy_queue(hw);
4160         hw->io_base = NULL;
4161 }
4162
4163 static int
4164 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4165 {
4166         struct hns3_hw *hw = &hns->hw;
4167         int ret;
4168
4169         ret = hns3_dcb_cfg_update(hns);
4170         if (ret)
4171                 return ret;
4172
4173         /* Enable queues */
4174         ret = hns3_start_queues(hns, reset_queue);
4175         if (ret) {
4176                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4177                 return ret;
4178         }
4179
4180         /* Enable MAC */
4181         ret = hns3_cfg_mac_mode(hw, true);
4182         if (ret) {
4183                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4184                 goto err_config_mac_mode;
4185         }
4186         return 0;
4187
4188 err_config_mac_mode:
4189         hns3_stop_queues(hns, true);
4190         return ret;
4191 }
4192
4193 static int
4194 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4195 {
4196         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4197         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4198         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4199         uint32_t intr_vector;
4200         uint8_t base = 0;
4201         uint8_t vec = 0;
4202         uint16_t q_id;
4203         int ret;
4204
4205         if (dev->data->dev_conf.intr_conf.rxq == 0)
4206                 return 0;
4207
4208         /* disable uio/vfio intr/eventfd mapping */
4209         rte_intr_disable(intr_handle);
4210
4211         /* check and configure queue intr-vector mapping */
4212         if (rte_intr_cap_multiple(intr_handle) ||
4213             !RTE_ETH_DEV_SRIOV(dev).active) {
4214                 intr_vector = hw->used_rx_queues;
4215                 /* creates event fd for each intr vector when MSIX is used */
4216                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4217                         return -EINVAL;
4218         }
4219         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4220                 intr_handle->intr_vec =
4221                         rte_zmalloc("intr_vec",
4222                                     hw->used_rx_queues * sizeof(int), 0);
4223                 if (intr_handle->intr_vec == NULL) {
4224                         hns3_err(hw, "Failed to allocate %d rx_queues"
4225                                      " intr_vec", hw->used_rx_queues);
4226                         ret = -ENOMEM;
4227                         goto alloc_intr_vec_error;
4228                 }
4229         }
4230
4231         if (rte_intr_allow_others(intr_handle)) {
4232                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4233                 base = RTE_INTR_VEC_RXTX_OFFSET;
4234         }
4235         if (rte_intr_dp_is_en(intr_handle)) {
4236                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4237                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4238                                                          HNS3_RING_TYPE_RX,
4239                                                          q_id);
4240                         if (ret)
4241                                 goto bind_vector_error;
4242                         intr_handle->intr_vec[q_id] = vec;
4243                         if (vec < base + intr_handle->nb_efd - 1)
4244                                 vec++;
4245                 }
4246         }
4247         rte_intr_enable(intr_handle);
4248         return 0;
4249
4250 bind_vector_error:
4251         rte_intr_efd_disable(intr_handle);
4252         if (intr_handle->intr_vec) {
4253                 free(intr_handle->intr_vec);
4254                 intr_handle->intr_vec = NULL;
4255         }
4256         return ret;
4257 alloc_intr_vec_error:
4258         rte_intr_efd_disable(intr_handle);
4259         return ret;
4260 }
4261
4262 static void
4263 hns3_restore_filter(struct rte_eth_dev *dev)
4264 {
4265         hns3_restore_rss_filter(dev);
4266 }
4267
4268 static int
4269 hns3_dev_start(struct rte_eth_dev *dev)
4270 {
4271         struct hns3_adapter *hns = dev->data->dev_private;
4272         struct hns3_hw *hw = &hns->hw;
4273         int ret;
4274
4275         PMD_INIT_FUNC_TRACE();
4276         if (rte_atomic16_read(&hw->reset.resetting))
4277                 return -EBUSY;
4278
4279         rte_spinlock_lock(&hw->lock);
4280         hw->adapter_state = HNS3_NIC_STARTING;
4281
4282         ret = hns3_do_start(hns, true);
4283         if (ret) {
4284                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4285                 rte_spinlock_unlock(&hw->lock);
4286                 return ret;
4287         }
4288
4289         hw->adapter_state = HNS3_NIC_STARTED;
4290         rte_spinlock_unlock(&hw->lock);
4291
4292         ret = hns3_map_rx_interrupt(dev);
4293         if (ret)
4294                 return ret;
4295         hns3_set_rxtx_function(dev);
4296         hns3_mp_req_start_rxtx(dev);
4297         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4298
4299         hns3_restore_filter(dev);
4300
4301         hns3_info(hw, "hns3 dev start successful!");
4302         return 0;
4303 }
4304
4305 static int
4306 hns3_do_stop(struct hns3_adapter *hns)
4307 {
4308         struct hns3_hw *hw = &hns->hw;
4309         bool reset_queue;
4310         int ret;
4311
4312         ret = hns3_cfg_mac_mode(hw, false);
4313         if (ret)
4314                 return ret;
4315         hw->mac.link_status = ETH_LINK_DOWN;
4316
4317         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4318                 hns3_configure_all_mac_addr(hns, true);
4319                 reset_queue = true;
4320         } else
4321                 reset_queue = false;
4322         hw->mac.default_addr_setted = false;
4323         return hns3_stop_queues(hns, reset_queue);
4324 }
4325
4326 static void
4327 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4328 {
4329         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4330         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4331         struct hns3_adapter *hns = dev->data->dev_private;
4332         struct hns3_hw *hw = &hns->hw;
4333         uint8_t base = 0;
4334         uint8_t vec = 0;
4335         uint16_t q_id;
4336
4337         if (dev->data->dev_conf.intr_conf.rxq == 0)
4338                 return;
4339
4340         /* unmap the ring with vector */
4341         if (rte_intr_allow_others(intr_handle)) {
4342                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4343                 base = RTE_INTR_VEC_RXTX_OFFSET;
4344         }
4345         if (rte_intr_dp_is_en(intr_handle)) {
4346                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4347                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4348                                                          HNS3_RING_TYPE_RX,
4349                                                          q_id);
4350                         if (vec < base + intr_handle->nb_efd - 1)
4351                                 vec++;
4352                 }
4353         }
4354         /* Clean datapath event and queue/vec mapping */
4355         rte_intr_efd_disable(intr_handle);
4356         if (intr_handle->intr_vec) {
4357                 rte_free(intr_handle->intr_vec);
4358                 intr_handle->intr_vec = NULL;
4359         }
4360 }
4361
4362 static void
4363 hns3_dev_stop(struct rte_eth_dev *dev)
4364 {
4365         struct hns3_adapter *hns = dev->data->dev_private;
4366         struct hns3_hw *hw = &hns->hw;
4367
4368         PMD_INIT_FUNC_TRACE();
4369
4370         hw->adapter_state = HNS3_NIC_STOPPING;
4371         hns3_set_rxtx_function(dev);
4372         rte_wmb();
4373         /* Disable datapath on secondary process. */
4374         hns3_mp_req_stop_rxtx(dev);
4375         /* Prevent crashes when queues are still in use. */
4376         rte_delay_ms(hw->tqps_num);
4377
4378         rte_spinlock_lock(&hw->lock);
4379         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4380                 hns3_do_stop(hns);
4381                 hns3_dev_release_mbufs(hns);
4382                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4383         }
4384         rte_eal_alarm_cancel(hns3_service_handler, dev);
4385         rte_spinlock_unlock(&hw->lock);
4386         hns3_unmap_rx_interrupt(dev);
4387 }
4388
4389 static void
4390 hns3_dev_close(struct rte_eth_dev *eth_dev)
4391 {
4392         struct hns3_adapter *hns = eth_dev->data->dev_private;
4393         struct hns3_hw *hw = &hns->hw;
4394
4395         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4396                 rte_free(eth_dev->process_private);
4397                 eth_dev->process_private = NULL;
4398                 return;
4399         }
4400
4401         if (hw->adapter_state == HNS3_NIC_STARTED)
4402                 hns3_dev_stop(eth_dev);
4403
4404         hw->adapter_state = HNS3_NIC_CLOSING;
4405         hns3_reset_abort(hns);
4406         hw->adapter_state = HNS3_NIC_CLOSED;
4407
4408         hns3_configure_all_mc_mac_addr(hns, true);
4409         hns3_remove_all_vlan_table(hns);
4410         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4411         hns3_uninit_pf(eth_dev);
4412         hns3_free_all_queues(eth_dev);
4413         rte_free(hw->reset.wait_data);
4414         rte_free(eth_dev->process_private);
4415         eth_dev->process_private = NULL;
4416         hns3_mp_uninit_primary();
4417         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4418 }
4419
4420 static int
4421 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4422 {
4423         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4424         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4425
4426         fc_conf->pause_time = pf->pause_time;
4427
4428         /* return fc current mode */
4429         switch (hw->current_mode) {
4430         case HNS3_FC_FULL:
4431                 fc_conf->mode = RTE_FC_FULL;
4432                 break;
4433         case HNS3_FC_TX_PAUSE:
4434                 fc_conf->mode = RTE_FC_TX_PAUSE;
4435                 break;
4436         case HNS3_FC_RX_PAUSE:
4437                 fc_conf->mode = RTE_FC_RX_PAUSE;
4438                 break;
4439         case HNS3_FC_NONE:
4440         default:
4441                 fc_conf->mode = RTE_FC_NONE;
4442                 break;
4443         }
4444
4445         return 0;
4446 }
4447
4448 static void
4449 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4450 {
4451         switch (mode) {
4452         case RTE_FC_NONE:
4453                 hw->requested_mode = HNS3_FC_NONE;
4454                 break;
4455         case RTE_FC_RX_PAUSE:
4456                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4457                 break;
4458         case RTE_FC_TX_PAUSE:
4459                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4460                 break;
4461         case RTE_FC_FULL:
4462                 hw->requested_mode = HNS3_FC_FULL;
4463                 break;
4464         default:
4465                 hw->requested_mode = HNS3_FC_NONE;
4466                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4467                           "configured to RTE_FC_NONE", mode);
4468                 break;
4469         }
4470 }
4471
4472 static int
4473 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4474 {
4475         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4476         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4477         int ret;
4478
4479         if (fc_conf->high_water || fc_conf->low_water ||
4480             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4481                 hns3_err(hw, "Unsupported flow control settings specified, "
4482                          "high_water(%u), low_water(%u), send_xon(%u) and "
4483                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4484                          fc_conf->high_water, fc_conf->low_water,
4485                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4486                 return -EINVAL;
4487         }
4488         if (fc_conf->autoneg) {
4489                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4490                 return -EINVAL;
4491         }
4492         if (!fc_conf->pause_time) {
4493                 hns3_err(hw, "Invalid pause time %d setting.",
4494                          fc_conf->pause_time);
4495                 return -EINVAL;
4496         }
4497
4498         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4499             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4500                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4501                          "current_fc_status = %d", hw->current_fc_status);
4502                 return -EOPNOTSUPP;
4503         }
4504
4505         hns3_get_fc_mode(hw, fc_conf->mode);
4506         if (hw->requested_mode == hw->current_mode &&
4507             pf->pause_time == fc_conf->pause_time)
4508                 return 0;
4509
4510         rte_spinlock_lock(&hw->lock);
4511         ret = hns3_fc_enable(dev, fc_conf);
4512         rte_spinlock_unlock(&hw->lock);
4513
4514         return ret;
4515 }
4516
4517 static int
4518 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4519                             struct rte_eth_pfc_conf *pfc_conf)
4520 {
4521         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4522         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4523         uint8_t priority;
4524         int ret;
4525
4526         if (!hns3_dev_dcb_supported(hw)) {
4527                 hns3_err(hw, "This port does not support dcb configurations.");
4528                 return -EOPNOTSUPP;
4529         }
4530
4531         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4532             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4533                 hns3_err(hw, "Unsupported flow control settings specified, "
4534                          "high_water(%u), low_water(%u), send_xon(%u) and "
4535                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4536                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4537                          pfc_conf->fc.send_xon,
4538                          pfc_conf->fc.mac_ctrl_frame_fwd);
4539                 return -EINVAL;
4540         }
4541         if (pfc_conf->fc.autoneg) {
4542                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4543                 return -EINVAL;
4544         }
4545         if (pfc_conf->fc.pause_time == 0) {
4546                 hns3_err(hw, "Invalid pause time %d setting.",
4547                          pfc_conf->fc.pause_time);
4548                 return -EINVAL;
4549         }
4550
4551         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4552             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4553                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4554                              "current_fc_status = %d", hw->current_fc_status);
4555                 return -EOPNOTSUPP;
4556         }
4557
4558         priority = pfc_conf->priority;
4559         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4560         if (hw->dcb_info.pfc_en & BIT(priority) &&
4561             hw->requested_mode == hw->current_mode &&
4562             pfc_conf->fc.pause_time == pf->pause_time)
4563                 return 0;
4564
4565         rte_spinlock_lock(&hw->lock);
4566         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4567         rte_spinlock_unlock(&hw->lock);
4568
4569         return ret;
4570 }
4571
4572 static int
4573 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4574 {
4575         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4576         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4577         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4578         int i;
4579
4580         rte_spinlock_lock(&hw->lock);
4581         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4582                 dcb_info->nb_tcs = pf->local_max_tc;
4583         else
4584                 dcb_info->nb_tcs = 1;
4585
4586         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4587                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4588         for (i = 0; i < dcb_info->nb_tcs; i++)
4589                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4590
4591         for (i = 0; i < hw->num_tc; i++) {
4592                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4593                 dcb_info->tc_queue.tc_txq[0][i].base =
4594                                                 hw->tc_queue[i].tqp_offset;
4595                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4596                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4597                                                 hw->tc_queue[i].tqp_count;
4598         }
4599         rte_spinlock_unlock(&hw->lock);
4600
4601         return 0;
4602 }
4603
4604 static int
4605 hns3_reinit_dev(struct hns3_adapter *hns)
4606 {
4607         struct hns3_hw *hw = &hns->hw;
4608         int ret;
4609
4610         ret = hns3_cmd_init(hw);
4611         if (ret) {
4612                 hns3_err(hw, "Failed to init cmd: %d", ret);
4613                 return ret;
4614         }
4615
4616         ret = hns3_reset_all_queues(hns);
4617         if (ret) {
4618                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4619                 return ret;
4620         }
4621
4622         ret = hns3_init_hardware(hns);
4623         if (ret) {
4624                 hns3_err(hw, "Failed to init hardware: %d", ret);
4625                 return ret;
4626         }
4627
4628         ret = hns3_enable_hw_error_intr(hns, true);
4629         if (ret) {
4630                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4631                              ret);
4632                 return ret;
4633         }
4634         hns3_info(hw, "Reset done, driver initialization finished.");
4635
4636         return 0;
4637 }
4638
4639 static bool
4640 is_pf_reset_done(struct hns3_hw *hw)
4641 {
4642         uint32_t val, reg, reg_bit;
4643
4644         switch (hw->reset.level) {
4645         case HNS3_IMP_RESET:
4646                 reg = HNS3_GLOBAL_RESET_REG;
4647                 reg_bit = HNS3_IMP_RESET_BIT;
4648                 break;
4649         case HNS3_GLOBAL_RESET:
4650                 reg = HNS3_GLOBAL_RESET_REG;
4651                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4652                 break;
4653         case HNS3_FUNC_RESET:
4654                 reg = HNS3_FUN_RST_ING;
4655                 reg_bit = HNS3_FUN_RST_ING_B;
4656                 break;
4657         case HNS3_FLR_RESET:
4658         default:
4659                 hns3_err(hw, "Wait for unsupported reset level: %d",
4660                          hw->reset.level);
4661                 return true;
4662         }
4663         val = hns3_read_dev(hw, reg);
4664         if (hns3_get_bit(val, reg_bit))
4665                 return false;
4666         else
4667                 return true;
4668 }
4669
4670 bool
4671 hns3_is_reset_pending(struct hns3_adapter *hns)
4672 {
4673         struct hns3_hw *hw = &hns->hw;
4674         enum hns3_reset_level reset;
4675
4676         hns3_check_event_cause(hns, NULL);
4677         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4678         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4679                 hns3_warn(hw, "High level reset %d is pending", reset);
4680                 return true;
4681         }
4682         reset = hns3_get_reset_level(hns, &hw->reset.request);
4683         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4684                 hns3_warn(hw, "High level reset %d is request", reset);
4685                 return true;
4686         }
4687         return false;
4688 }
4689
4690 static int
4691 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4692 {
4693         struct hns3_hw *hw = &hns->hw;
4694         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4695         struct timeval tv;
4696
4697         if (wait_data->result == HNS3_WAIT_SUCCESS)
4698                 return 0;
4699         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4700                 gettimeofday(&tv, NULL);
4701                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4702                           tv.tv_sec, tv.tv_usec);
4703                 return -ETIME;
4704         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4705                 return -EAGAIN;
4706
4707         wait_data->hns = hns;
4708         wait_data->check_completion = is_pf_reset_done;
4709         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4710                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4711         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4712         wait_data->count = HNS3_RESET_WAIT_CNT;
4713         wait_data->result = HNS3_WAIT_REQUEST;
4714         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4715         return -EAGAIN;
4716 }
4717
4718 static int
4719 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4720 {
4721         struct hns3_cmd_desc desc;
4722         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4723
4724         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4725         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4726         req->fun_reset_vfid = func_id;
4727
4728         return hns3_cmd_send(hw, &desc, 1);
4729 }
4730
4731 static int
4732 hns3_imp_reset_cmd(struct hns3_hw *hw)
4733 {
4734         struct hns3_cmd_desc desc;
4735
4736         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4737         desc.data[0] = 0xeedd;
4738
4739         return hns3_cmd_send(hw, &desc, 1);
4740 }
4741
4742 static void
4743 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4744 {
4745         struct hns3_hw *hw = &hns->hw;
4746         struct timeval tv;
4747         uint32_t val;
4748
4749         gettimeofday(&tv, NULL);
4750         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4751             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4752                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4753                           tv.tv_sec, tv.tv_usec);
4754                 return;
4755         }
4756
4757         switch (reset_level) {
4758         case HNS3_IMP_RESET:
4759                 hns3_imp_reset_cmd(hw);
4760                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4761                           tv.tv_sec, tv.tv_usec);
4762                 break;
4763         case HNS3_GLOBAL_RESET:
4764                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4765                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4766                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4767                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4768                           tv.tv_sec, tv.tv_usec);
4769                 break;
4770         case HNS3_FUNC_RESET:
4771                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4772                           tv.tv_sec, tv.tv_usec);
4773                 /* schedule again to check later */
4774                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4775                 hns3_schedule_reset(hns);
4776                 break;
4777         default:
4778                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4779                 return;
4780         }
4781         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4782 }
4783
4784 static enum hns3_reset_level
4785 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4786 {
4787         struct hns3_hw *hw = &hns->hw;
4788         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4789
4790         /* Return the highest priority reset level amongst all */
4791         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4792                 reset_level = HNS3_IMP_RESET;
4793         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4794                 reset_level = HNS3_GLOBAL_RESET;
4795         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4796                 reset_level = HNS3_FUNC_RESET;
4797         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4798                 reset_level = HNS3_FLR_RESET;
4799
4800         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4801                 return HNS3_NONE_RESET;
4802
4803         return reset_level;
4804 }
4805
4806 static int
4807 hns3_prepare_reset(struct hns3_adapter *hns)
4808 {
4809         struct hns3_hw *hw = &hns->hw;
4810         uint32_t reg_val;
4811         int ret;
4812
4813         switch (hw->reset.level) {
4814         case HNS3_FUNC_RESET:
4815                 ret = hns3_func_reset_cmd(hw, 0);
4816                 if (ret)
4817                         return ret;
4818
4819                 /*
4820                  * After performaning pf reset, it is not necessary to do the
4821                  * mailbox handling or send any command to firmware, because
4822                  * any mailbox handling or command to firmware is only valid
4823                  * after hns3_cmd_init is called.
4824                  */
4825                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4826                 hw->reset.stats.request_cnt++;
4827                 break;
4828         case HNS3_IMP_RESET:
4829                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4830                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4831                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4832                 break;
4833         default:
4834                 break;
4835         }
4836         return 0;
4837 }
4838
4839 static int
4840 hns3_set_rst_done(struct hns3_hw *hw)
4841 {
4842         struct hns3_pf_rst_done_cmd *req;
4843         struct hns3_cmd_desc desc;
4844
4845         req = (struct hns3_pf_rst_done_cmd *)desc.data;
4846         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4847         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4848         return hns3_cmd_send(hw, &desc, 1);
4849 }
4850
4851 static int
4852 hns3_stop_service(struct hns3_adapter *hns)
4853 {
4854         struct hns3_hw *hw = &hns->hw;
4855         struct rte_eth_dev *eth_dev;
4856
4857         eth_dev = &rte_eth_devices[hw->data->port_id];
4858         if (hw->adapter_state == HNS3_NIC_STARTED)
4859                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4860         hw->mac.link_status = ETH_LINK_DOWN;
4861
4862         hns3_set_rxtx_function(eth_dev);
4863         rte_wmb();
4864         /* Disable datapath on secondary process. */
4865         hns3_mp_req_stop_rxtx(eth_dev);
4866         rte_delay_ms(hw->tqps_num);
4867
4868         rte_spinlock_lock(&hw->lock);
4869         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4870             hw->adapter_state == HNS3_NIC_STOPPING) {
4871                 hns3_do_stop(hns);
4872                 hw->reset.mbuf_deferred_free = true;
4873         } else
4874                 hw->reset.mbuf_deferred_free = false;
4875
4876         /*
4877          * It is cumbersome for hardware to pick-and-choose entries for deletion
4878          * from table space. Hence, for function reset software intervention is
4879          * required to delete the entries
4880          */
4881         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
4882                 hns3_configure_all_mc_mac_addr(hns, true);
4883         rte_spinlock_unlock(&hw->lock);
4884
4885         return 0;
4886 }
4887
4888 static int
4889 hns3_start_service(struct hns3_adapter *hns)
4890 {
4891         struct hns3_hw *hw = &hns->hw;
4892         struct rte_eth_dev *eth_dev;
4893
4894         if (hw->reset.level == HNS3_IMP_RESET ||
4895             hw->reset.level == HNS3_GLOBAL_RESET)
4896                 hns3_set_rst_done(hw);
4897         eth_dev = &rte_eth_devices[hw->data->port_id];
4898         hns3_set_rxtx_function(eth_dev);
4899         hns3_mp_req_start_rxtx(eth_dev);
4900         if (hw->adapter_state == HNS3_NIC_STARTED)
4901                 hns3_service_handler(eth_dev);
4902
4903         return 0;
4904 }
4905
4906 static int
4907 hns3_restore_conf(struct hns3_adapter *hns)
4908 {
4909         struct hns3_hw *hw = &hns->hw;
4910         int ret;
4911
4912         ret = hns3_configure_all_mac_addr(hns, false);
4913         if (ret)
4914                 return ret;
4915
4916         ret = hns3_configure_all_mc_mac_addr(hns, false);
4917         if (ret)
4918                 goto err_mc_mac;
4919
4920         ret = hns3_dev_promisc_restore(hns);
4921         if (ret)
4922                 goto err_promisc;
4923
4924         ret = hns3_restore_vlan_table(hns);
4925         if (ret)
4926                 goto err_promisc;
4927
4928         ret = hns3_restore_vlan_conf(hns);
4929         if (ret)
4930                 goto err_promisc;
4931
4932         ret = hns3_restore_all_fdir_filter(hns);
4933         if (ret)
4934                 goto err_promisc;
4935
4936         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
4937                 ret = hns3_do_start(hns, false);
4938                 if (ret)
4939                         goto err_promisc;
4940                 hns3_info(hw, "hns3 dev restart successful!");
4941         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
4942                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4943         return 0;
4944
4945 err_promisc:
4946         hns3_configure_all_mc_mac_addr(hns, true);
4947 err_mc_mac:
4948         hns3_configure_all_mac_addr(hns, true);
4949         return ret;
4950 }
4951
4952 static void
4953 hns3_reset_service(void *param)
4954 {
4955         struct hns3_adapter *hns = (struct hns3_adapter *)param;
4956         struct hns3_hw *hw = &hns->hw;
4957         enum hns3_reset_level reset_level;
4958         struct timeval tv_delta;
4959         struct timeval tv_start;
4960         struct timeval tv;
4961         uint64_t msec;
4962         int ret;
4963
4964         /*
4965          * The interrupt is not triggered within the delay time.
4966          * The interrupt may have been lost. It is necessary to handle
4967          * the interrupt to recover from the error.
4968          */
4969         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
4970                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
4971                 hns3_err(hw, "Handling interrupts in delayed tasks");
4972                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
4973                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4974                 if (reset_level == HNS3_NONE_RESET) {
4975                         hns3_err(hw, "No reset level is set, try IMP reset");
4976                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
4977                 }
4978         }
4979         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
4980
4981         /*
4982          * Check if there is any ongoing reset in the hardware. This status can
4983          * be checked from reset_pending. If there is then, we need to wait for
4984          * hardware to complete reset.
4985          *    a. If we are able to figure out in reasonable time that hardware
4986          *       has fully resetted then, we can proceed with driver, client
4987          *       reset.
4988          *    b. else, we can come back later to check this status so re-sched
4989          *       now.
4990          */
4991         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4992         if (reset_level != HNS3_NONE_RESET) {
4993                 gettimeofday(&tv_start, NULL);
4994                 ret = hns3_reset_process(hns, reset_level);
4995                 gettimeofday(&tv, NULL);
4996                 timersub(&tv, &tv_start, &tv_delta);
4997                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
4998                        tv_delta.tv_usec / USEC_PER_MSEC;
4999                 if (msec > HNS3_RESET_PROCESS_MS)
5000                         hns3_err(hw, "%d handle long time delta %" PRIx64
5001                                      " ms time=%ld.%.6ld",
5002                                  hw->reset.level, msec,
5003                                  tv.tv_sec, tv.tv_usec);
5004                 if (ret == -EAGAIN)
5005                         return;
5006         }
5007
5008         /* Check if we got any *new* reset requests to be honored */
5009         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5010         if (reset_level != HNS3_NONE_RESET)
5011                 hns3_msix_process(hns, reset_level);
5012 }
5013
5014 static const struct eth_dev_ops hns3_eth_dev_ops = {
5015         .dev_start          = hns3_dev_start,
5016         .dev_stop           = hns3_dev_stop,
5017         .dev_close          = hns3_dev_close,
5018         .promiscuous_enable = hns3_dev_promiscuous_enable,
5019         .promiscuous_disable = hns3_dev_promiscuous_disable,
5020         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5021         .allmulticast_disable = hns3_dev_allmulticast_disable,
5022         .mtu_set            = hns3_dev_mtu_set,
5023         .stats_get          = hns3_stats_get,
5024         .stats_reset        = hns3_stats_reset,
5025         .xstats_get         = hns3_dev_xstats_get,
5026         .xstats_get_names   = hns3_dev_xstats_get_names,
5027         .xstats_reset       = hns3_dev_xstats_reset,
5028         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5029         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5030         .dev_infos_get          = hns3_dev_infos_get,
5031         .fw_version_get         = hns3_fw_version_get,
5032         .rx_queue_setup         = hns3_rx_queue_setup,
5033         .tx_queue_setup         = hns3_tx_queue_setup,
5034         .rx_queue_release       = hns3_dev_rx_queue_release,
5035         .tx_queue_release       = hns3_dev_tx_queue_release,
5036         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5037         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5038         .dev_configure          = hns3_dev_configure,
5039         .flow_ctrl_get          = hns3_flow_ctrl_get,
5040         .flow_ctrl_set          = hns3_flow_ctrl_set,
5041         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5042         .mac_addr_add           = hns3_add_mac_addr,
5043         .mac_addr_remove        = hns3_remove_mac_addr,
5044         .mac_addr_set           = hns3_set_default_mac_addr,
5045         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5046         .link_update            = hns3_dev_link_update,
5047         .rss_hash_update        = hns3_dev_rss_hash_update,
5048         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5049         .reta_update            = hns3_dev_rss_reta_update,
5050         .reta_query             = hns3_dev_rss_reta_query,
5051         .filter_ctrl            = hns3_dev_filter_ctrl,
5052         .vlan_filter_set        = hns3_vlan_filter_set,
5053         .vlan_tpid_set          = hns3_vlan_tpid_set,
5054         .vlan_offload_set       = hns3_vlan_offload_set,
5055         .vlan_pvid_set          = hns3_vlan_pvid_set,
5056         .get_reg                = hns3_get_regs,
5057         .get_dcb_info           = hns3_get_dcb_info,
5058         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5059 };
5060
5061 static const struct hns3_reset_ops hns3_reset_ops = {
5062         .reset_service       = hns3_reset_service,
5063         .stop_service        = hns3_stop_service,
5064         .prepare_reset       = hns3_prepare_reset,
5065         .wait_hardware_ready = hns3_wait_hardware_ready,
5066         .reinit_dev          = hns3_reinit_dev,
5067         .restore_conf        = hns3_restore_conf,
5068         .start_service       = hns3_start_service,
5069 };
5070
5071 static int
5072 hns3_dev_init(struct rte_eth_dev *eth_dev)
5073 {
5074         struct rte_device *dev = eth_dev->device;
5075         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5076         struct hns3_adapter *hns = eth_dev->data->dev_private;
5077         struct hns3_hw *hw = &hns->hw;
5078         uint16_t device_id = pci_dev->id.device_id;
5079         int ret;
5080
5081         PMD_INIT_FUNC_TRACE();
5082         eth_dev->process_private = (struct hns3_process_private *)
5083             rte_zmalloc_socket("hns3_filter_list",
5084                                sizeof(struct hns3_process_private),
5085                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5086         if (eth_dev->process_private == NULL) {
5087                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5088                 return -ENOMEM;
5089         }
5090         /* initialize flow filter lists */
5091         hns3_filterlist_init(eth_dev);
5092
5093         hns3_set_rxtx_function(eth_dev);
5094         eth_dev->dev_ops = &hns3_eth_dev_ops;
5095         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5096                 hns3_mp_init_secondary();
5097                 hw->secondary_cnt++;
5098                 return 0;
5099         }
5100
5101         hns3_mp_init_primary();
5102         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5103
5104         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5105             device_id == HNS3_DEV_ID_50GE_RDMA ||
5106             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5107                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5108
5109         hns->is_vf = false;
5110         hw->data = eth_dev->data;
5111
5112         /*
5113          * Set default max packet size according to the mtu
5114          * default vale in DPDK frame.
5115          */
5116         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5117
5118         ret = hns3_reset_init(hw);
5119         if (ret)
5120                 goto err_init_reset;
5121         hw->reset.ops = &hns3_reset_ops;
5122
5123         ret = hns3_init_pf(eth_dev);
5124         if (ret) {
5125                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5126                 goto err_init_pf;
5127         }
5128
5129         /* Allocate memory for storing MAC addresses */
5130         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5131                                                sizeof(struct rte_ether_addr) *
5132                                                HNS3_UC_MACADDR_NUM, 0);
5133         if (eth_dev->data->mac_addrs == NULL) {
5134                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5135                              "to store MAC addresses",
5136                              sizeof(struct rte_ether_addr) *
5137                              HNS3_UC_MACADDR_NUM);
5138                 ret = -ENOMEM;
5139                 goto err_rte_zmalloc;
5140         }
5141
5142         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5143                             &eth_dev->data->mac_addrs[0]);
5144
5145         hw->adapter_state = HNS3_NIC_INITIALIZED;
5146         /*
5147          * Pass the information to the rte_eth_dev_close() that it should also
5148          * release the private port resources.
5149          */
5150         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5151
5152         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5153                 hns3_err(hw, "Reschedule reset service after dev_init");
5154                 hns3_schedule_reset(hns);
5155         } else {
5156                 /* IMP will wait ready flag before reset */
5157                 hns3_notify_reset_ready(hw, false);
5158         }
5159
5160         hns3_info(hw, "hns3 dev initialization successful!");
5161         return 0;
5162
5163 err_rte_zmalloc:
5164         hns3_uninit_pf(eth_dev);
5165
5166 err_init_pf:
5167         rte_free(hw->reset.wait_data);
5168 err_init_reset:
5169         eth_dev->dev_ops = NULL;
5170         eth_dev->rx_pkt_burst = NULL;
5171         eth_dev->tx_pkt_burst = NULL;
5172         eth_dev->tx_pkt_prepare = NULL;
5173         rte_free(eth_dev->process_private);
5174         eth_dev->process_private = NULL;
5175         return ret;
5176 }
5177
5178 static int
5179 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5180 {
5181         struct hns3_adapter *hns = eth_dev->data->dev_private;
5182         struct hns3_hw *hw = &hns->hw;
5183
5184         PMD_INIT_FUNC_TRACE();
5185
5186         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5187                 return -EPERM;
5188
5189         eth_dev->dev_ops = NULL;
5190         eth_dev->rx_pkt_burst = NULL;
5191         eth_dev->tx_pkt_burst = NULL;
5192         eth_dev->tx_pkt_prepare = NULL;
5193         if (hw->adapter_state < HNS3_NIC_CLOSING)
5194                 hns3_dev_close(eth_dev);
5195
5196         hw->adapter_state = HNS3_NIC_REMOVED;
5197         return 0;
5198 }
5199
5200 static int
5201 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5202                    struct rte_pci_device *pci_dev)
5203 {
5204         return rte_eth_dev_pci_generic_probe(pci_dev,
5205                                              sizeof(struct hns3_adapter),
5206                                              hns3_dev_init);
5207 }
5208
5209 static int
5210 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5211 {
5212         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5213 }
5214
5215 static const struct rte_pci_id pci_id_hns3_map[] = {
5216         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5217         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5218         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5219         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5220         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5221         { .vendor_id = 0, /* sentinel */ },
5222 };
5223
5224 static struct rte_pci_driver rte_hns3_pmd = {
5225         .id_table = pci_id_hns3_map,
5226         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5227         .probe = eth_hns3_pci_probe,
5228         .remove = eth_hns3_pci_remove,
5229 };
5230
5231 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5232 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5233 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5234
5235 RTE_INIT(hns3_init_log)
5236 {
5237         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5238         if (hns3_logtype_init >= 0)
5239                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5240         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5241         if (hns3_logtype_driver >= 0)
5242                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5243 }