1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
12 #include <rte_atomic.h>
13 #include <rte_bus_pci.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_interrupts.h>
26 #include "hns3_ethdev.h"
27 #include "hns3_logs.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_intr.h"
30 #include "hns3_regs.h"
34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
37 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
38 #define HNS3_PORT_BASE_VLAN_DISABLE 0
39 #define HNS3_PORT_BASE_VLAN_ENABLE 1
40 #define HNS3_INVLID_PVID 0xFFFF
42 #define HNS3_FILTER_TYPE_VF 0
43 #define HNS3_FILTER_TYPE_PORT 1
44 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
45 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
46 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
47 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
48 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
49 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
50 | HNS3_FILTER_FE_ROCE_EGRESS_B)
51 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
52 | HNS3_FILTER_FE_ROCE_INGRESS_B)
54 /* Reset related Registers */
55 #define HNS3_GLOBAL_RESET_BIT 0
56 #define HNS3_CORE_RESET_BIT 1
57 #define HNS3_IMP_RESET_BIT 2
58 #define HNS3_FUN_RST_ING_B 0
60 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
62 #define HNS3_RESET_WAIT_MS 100
63 #define HNS3_RESET_WAIT_CNT 200
65 int hns3_logtype_init;
66 int hns3_logtype_driver;
69 HNS3_VECTOR0_EVENT_RST,
70 HNS3_VECTOR0_EVENT_MBX,
71 HNS3_VECTOR0_EVENT_ERR,
72 HNS3_VECTOR0_EVENT_OTHER,
75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
83 hns3_pf_disable_irq0(struct hns3_hw *hw)
85 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
89 hns3_pf_enable_irq0(struct hns3_hw *hw)
91 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
94 static enum hns3_evt_cause
95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
97 struct hns3_hw *hw = &hns->hw;
98 uint32_t vector0_int_stats;
99 uint32_t cmdq_src_val;
101 enum hns3_evt_cause ret;
103 /* fetch the events from their corresponding regs */
104 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
105 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
108 * Assumption: If by any chance reset and mailbox events are reported
109 * together then we will only process reset event and defer the
110 * processing of the mailbox events. Since, we would have not cleared
111 * RX CMDQ event this time we would receive again another interrupt
112 * from H/W just for the mailbox.
114 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
115 rte_atomic16_set(&hw->reset.disable_cmd, 1);
116 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
117 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
119 hw->reset.stats.imp_cnt++;
120 hns3_warn(hw, "IMP reset detected, clear reset status");
122 hns3_schedule_delayed_reset(hns);
123 hns3_warn(hw, "IMP reset detected, don't clear reset status");
126 ret = HNS3_VECTOR0_EVENT_RST;
131 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
132 rte_atomic16_set(&hw->reset.disable_cmd, 1);
133 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
134 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
136 hw->reset.stats.global_cnt++;
137 hns3_warn(hw, "Global reset detected, clear reset status");
139 hns3_schedule_delayed_reset(hns);
140 hns3_warn(hw, "Global reset detected, don't clear reset status");
143 ret = HNS3_VECTOR0_EVENT_RST;
147 /* check for vector0 msix event source */
148 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
149 val = vector0_int_stats;
150 ret = HNS3_VECTOR0_EVENT_ERR;
154 /* check for vector0 mailbox(=CMDQ RX) event source */
155 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
156 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
158 ret = HNS3_VECTOR0_EVENT_MBX;
162 if (clearval && (vector0_int_stats || cmdq_src_val))
163 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
164 vector0_int_stats, cmdq_src_val);
165 val = vector0_int_stats;
166 ret = HNS3_VECTOR0_EVENT_OTHER;
175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
177 if (event_type == HNS3_VECTOR0_EVENT_RST)
178 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
179 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
180 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
184 hns3_clear_all_event_cause(struct hns3_hw *hw)
186 uint32_t vector0_int_stats;
187 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
189 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
190 hns3_warn(hw, "Probe during IMP reset interrupt");
192 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
193 hns3_warn(hw, "Probe during Global reset interrupt");
195 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
196 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
197 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
198 BIT(HNS3_VECTOR0_CORERESET_INT_B));
199 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
203 hns3_interrupt_handler(void *param)
205 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
206 struct hns3_adapter *hns = dev->data->dev_private;
207 struct hns3_hw *hw = &hns->hw;
208 enum hns3_evt_cause event_cause;
209 uint32_t clearval = 0;
211 /* Disable interrupt */
212 hns3_pf_disable_irq0(hw);
214 event_cause = hns3_check_event_cause(hns, &clearval);
216 /* vector 0 interrupt is shared with reset and mailbox source events. */
217 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
218 hns3_handle_msix_error(hns, &hw->reset.request);
219 hns3_schedule_reset(hns);
220 } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
221 hns3_schedule_reset(hns);
222 else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
223 hns3_dev_handle_mbx_msg(hw);
225 hns3_err(hw, "Received unknown event");
227 hns3_clear_event_cause(hw, event_cause, clearval);
228 /* Enable interrupt if it is not cause by reset */
229 hns3_pf_enable_irq0(hw);
233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
235 #define HNS3_VLAN_ID_OFFSET_STEP 160
236 #define HNS3_VLAN_BYTE_SIZE 8
237 struct hns3_vlan_filter_pf_cfg_cmd *req;
238 struct hns3_hw *hw = &hns->hw;
239 uint8_t vlan_offset_byte_val;
240 struct hns3_cmd_desc desc;
241 uint8_t vlan_offset_byte;
242 uint8_t vlan_offset_base;
245 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
247 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
248 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
250 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
252 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
253 req->vlan_offset = vlan_offset_base;
254 req->vlan_cfg = on ? 0 : 1;
255 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
257 ret = hns3_cmd_send(hw, &desc, 1);
259 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
266 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
268 struct hns3_user_vlan_table *vlan_entry;
269 struct hns3_pf *pf = &hns->pf;
271 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
272 if (vlan_entry->vlan_id == vlan_id) {
273 if (vlan_entry->hd_tbl_status)
274 hns3_set_port_vlan_filter(hns, vlan_id, 0);
275 LIST_REMOVE(vlan_entry, next);
276 rte_free(vlan_entry);
283 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
286 struct hns3_user_vlan_table *vlan_entry;
287 struct hns3_hw *hw = &hns->hw;
288 struct hns3_pf *pf = &hns->pf;
290 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
291 if (vlan_entry->vlan_id == vlan_id)
295 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
296 if (vlan_entry == NULL) {
297 hns3_err(hw, "Failed to malloc hns3 vlan table");
301 vlan_entry->hd_tbl_status = writen_to_tbl;
302 vlan_entry->vlan_id = vlan_id;
304 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
308 hns3_restore_vlan_table(struct hns3_adapter *hns)
310 struct hns3_user_vlan_table *vlan_entry;
311 struct hns3_pf *pf = &hns->pf;
315 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) {
316 ret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid,
321 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
322 if (vlan_entry->hd_tbl_status) {
323 vlan_id = vlan_entry->vlan_id;
324 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
334 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
336 struct hns3_pf *pf = &hns->pf;
337 bool writen_to_tbl = false;
341 * When vlan filter is enabled, hardware regards vlan id 0 as the entry
342 * for normal packet, deleting vlan id 0 is not allowed.
344 if (on == 0 && vlan_id == 0)
348 * When port base vlan enabled, we use port base vlan as the vlan
349 * filter condition. In this case, we don't update vlan filter table
350 * when user add new vlan or remove exist vlan, just update the
351 * vlan list. The vlan id in vlan list will be writen in vlan filter
352 * table until port base vlan disabled
354 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
355 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
356 writen_to_tbl = true;
359 if (ret == 0 && vlan_id) {
361 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
363 hns3_rm_dev_vlan_table(hns, vlan_id);
369 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
371 struct hns3_adapter *hns = dev->data->dev_private;
372 struct hns3_hw *hw = &hns->hw;
375 rte_spinlock_lock(&hw->lock);
376 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
377 rte_spinlock_unlock(&hw->lock);
382 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
385 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
386 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
387 struct hns3_hw *hw = &hns->hw;
388 struct hns3_cmd_desc desc;
391 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
392 vlan_type != ETH_VLAN_TYPE_OUTER)) {
393 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
397 if (tpid != RTE_ETHER_TYPE_VLAN) {
398 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
402 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
403 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
405 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
406 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
407 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
408 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
409 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
410 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
411 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
412 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
415 ret = hns3_cmd_send(hw, &desc, 1);
417 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
422 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
424 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
425 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
426 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
428 ret = hns3_cmd_send(hw, &desc, 1);
430 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
436 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
439 struct hns3_adapter *hns = dev->data->dev_private;
440 struct hns3_hw *hw = &hns->hw;
443 rte_spinlock_lock(&hw->lock);
444 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
445 rte_spinlock_unlock(&hw->lock);
450 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
451 struct hns3_rx_vtag_cfg *vcfg)
453 struct hns3_vport_vtag_rx_cfg_cmd *req;
454 struct hns3_hw *hw = &hns->hw;
455 struct hns3_cmd_desc desc;
460 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
462 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
463 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
464 vcfg->strip_tag1_en ? 1 : 0);
465 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
466 vcfg->strip_tag2_en ? 1 : 0);
467 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
468 vcfg->vlan1_vlan_prionly ? 1 : 0);
469 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
470 vcfg->vlan2_vlan_prionly ? 1 : 0);
473 * In current version VF is not supported when PF is driven by DPDK
474 * driver, the PF-related vf_id is 0, just need to configure parameters
478 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
479 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
480 req->vf_bitmap[req->vf_offset] = bitmap;
482 ret = hns3_cmd_send(hw, &desc, 1);
484 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
489 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
490 struct hns3_rx_vtag_cfg *vcfg)
492 struct hns3_pf *pf = &hns->pf;
493 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
497 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
498 struct hns3_tx_vtag_cfg *vcfg)
500 struct hns3_pf *pf = &hns->pf;
501 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
505 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
507 struct hns3_rx_vtag_cfg rxvlan_cfg;
508 struct hns3_pf *pf = &hns->pf;
509 struct hns3_hw *hw = &hns->hw;
512 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
513 rxvlan_cfg.strip_tag1_en = false;
514 rxvlan_cfg.strip_tag2_en = enable;
516 rxvlan_cfg.strip_tag1_en = enable;
517 rxvlan_cfg.strip_tag2_en = true;
520 rxvlan_cfg.vlan1_vlan_prionly = false;
521 rxvlan_cfg.vlan2_vlan_prionly = false;
522 rxvlan_cfg.rx_vlan_offload_en = enable;
524 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
526 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
530 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
536 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
537 uint8_t fe_type, bool filter_en, uint8_t vf_id)
539 struct hns3_vlan_filter_ctrl_cmd *req;
540 struct hns3_cmd_desc desc;
543 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
545 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
546 req->vlan_type = vlan_type;
547 req->vlan_fe = filter_en ? fe_type : 0;
550 ret = hns3_cmd_send(hw, &desc, 1);
552 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
558 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
560 struct hns3_hw *hw = &hns->hw;
563 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
564 HNS3_FILTER_FE_EGRESS, false, 0);
566 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
570 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
571 HNS3_FILTER_FE_INGRESS, enable, 0);
573 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
579 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
581 struct hns3_adapter *hns = dev->data->dev_private;
582 struct hns3_hw *hw = &hns->hw;
583 struct rte_eth_rxmode *rxmode;
584 unsigned int tmp_mask;
588 rte_spinlock_lock(&hw->lock);
589 rxmode = &dev->data->dev_conf.rxmode;
590 tmp_mask = (unsigned int)mask;
591 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
592 /* Enable or disable VLAN stripping */
593 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
596 ret = hns3_en_hw_strip_rxvtag(hns, enable);
598 rte_spinlock_unlock(&hw->lock);
599 hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
604 rte_spinlock_unlock(&hw->lock);
610 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
611 struct hns3_tx_vtag_cfg *vcfg)
613 struct hns3_vport_vtag_tx_cfg_cmd *req;
614 struct hns3_cmd_desc desc;
615 struct hns3_hw *hw = &hns->hw;
620 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
622 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
623 req->def_vlan_tag1 = vcfg->default_tag1;
624 req->def_vlan_tag2 = vcfg->default_tag2;
625 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
626 vcfg->accept_tag1 ? 1 : 0);
627 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
628 vcfg->accept_untag1 ? 1 : 0);
629 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
630 vcfg->accept_tag2 ? 1 : 0);
631 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
632 vcfg->accept_untag2 ? 1 : 0);
633 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
634 vcfg->insert_tag1_en ? 1 : 0);
635 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
636 vcfg->insert_tag2_en ? 1 : 0);
637 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
640 * In current version VF is not supported when PF is driven by DPDK
641 * driver, the PF-related vf_id is 0, just need to configure parameters
645 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
646 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
647 req->vf_bitmap[req->vf_offset] = bitmap;
649 ret = hns3_cmd_send(hw, &desc, 1);
651 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
657 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
660 struct hns3_hw *hw = &hns->hw;
661 struct hns3_tx_vtag_cfg txvlan_cfg;
664 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
665 txvlan_cfg.accept_tag1 = true;
666 txvlan_cfg.insert_tag1_en = false;
667 txvlan_cfg.default_tag1 = 0;
669 txvlan_cfg.accept_tag1 = false;
670 txvlan_cfg.insert_tag1_en = true;
671 txvlan_cfg.default_tag1 = pvid;
674 txvlan_cfg.accept_untag1 = true;
675 txvlan_cfg.accept_tag2 = true;
676 txvlan_cfg.accept_untag2 = true;
677 txvlan_cfg.insert_tag2_en = false;
678 txvlan_cfg.default_tag2 = 0;
680 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
682 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
687 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
692 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
694 struct hns3_pf *pf = &hns->pf;
696 pf->port_base_vlan_cfg.state = on ?
697 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
699 pf->port_base_vlan_cfg.pvid = pvid;
703 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
705 struct hns3_user_vlan_table *vlan_entry;
706 struct hns3_pf *pf = &hns->pf;
708 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
709 if (vlan_entry->hd_tbl_status)
710 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
712 vlan_entry->hd_tbl_status = false;
716 vlan_entry = LIST_FIRST(&pf->vlan_list);
718 LIST_REMOVE(vlan_entry, next);
719 rte_free(vlan_entry);
720 vlan_entry = LIST_FIRST(&pf->vlan_list);
726 hns3_add_all_vlan_table(struct hns3_adapter *hns)
728 struct hns3_user_vlan_table *vlan_entry;
729 struct hns3_pf *pf = &hns->pf;
731 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
732 if (!vlan_entry->hd_tbl_status)
733 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
735 vlan_entry->hd_tbl_status = true;
740 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
742 struct hns3_hw *hw = &hns->hw;
743 struct hns3_pf *pf = &hns->pf;
746 hns3_rm_all_vlan_table(hns, true);
747 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
748 ret = hns3_set_port_vlan_filter(hns,
749 pf->port_base_vlan_cfg.pvid, 0);
751 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
759 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
760 uint16_t port_base_vlan_state,
761 uint16_t new_pvid, uint16_t old_pvid)
763 struct hns3_pf *pf = &hns->pf;
764 struct hns3_hw *hw = &hns->hw;
767 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
768 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
769 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
772 "Failed to clear clear old pvid filter, ret =%d",
778 hns3_rm_all_vlan_table(hns, false);
779 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
783 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
785 hns3_err(hw, "Failed to set port vlan filter, ret =%d",
791 if (new_pvid == pf->port_base_vlan_cfg.pvid)
792 hns3_add_all_vlan_table(hns);
798 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
800 struct hns3_rx_vtag_cfg rx_vlan_cfg;
801 struct hns3_hw *hw = &hns->hw;
805 rx_strip_en = on ? true : false;
806 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
807 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
808 rx_vlan_cfg.vlan1_vlan_prionly = false;
809 rx_vlan_cfg.vlan2_vlan_prionly = false;
810 rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
812 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
814 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
818 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
823 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
825 struct hns3_pf *pf = &hns->pf;
826 struct hns3_hw *hw = &hns->hw;
827 uint16_t port_base_vlan_state;
831 if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
832 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
833 hns3_warn(hw, "Invalid operation! As current pvid set "
834 "is %u, disable pvid %u is invalid",
835 pf->port_base_vlan_cfg.pvid, pvid);
839 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
840 HNS3_PORT_BASE_VLAN_DISABLE;
841 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
843 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
847 ret = hns3_en_rx_strip_all(hns, on);
849 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
853 if (pvid == HNS3_INVLID_PVID)
855 old_pvid = pf->port_base_vlan_cfg.pvid;
856 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
859 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
865 hns3_store_port_base_vlan_info(hns, pvid, on);
870 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
872 struct hns3_adapter *hns = dev->data->dev_private;
873 struct hns3_hw *hw = &hns->hw;
876 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
877 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
878 RTE_ETHER_MAX_VLAN_ID);
882 rte_spinlock_lock(&hw->lock);
883 ret = hns3_vlan_pvid_configure(hns, pvid, on);
884 rte_spinlock_unlock(&hw->lock);
889 init_port_base_vlan_info(struct hns3_hw *hw)
891 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
892 struct hns3_pf *pf = &hns->pf;
894 pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
895 pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
899 hns3_default_vlan_config(struct hns3_adapter *hns)
901 struct hns3_hw *hw = &hns->hw;
904 ret = hns3_set_port_vlan_filter(hns, 0, 1);
906 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
911 hns3_init_vlan_config(struct hns3_adapter *hns)
913 struct hns3_hw *hw = &hns->hw;
917 * This function can be called in the initialization and reset process,
918 * when in reset process, it means that hardware had been reseted
919 * successfully and we need to restore the hardware configuration to
920 * ensure that the hardware configuration remains unchanged before and
923 if (rte_atomic16_read(&hw->reset.resetting) == 0)
924 init_port_base_vlan_info(hw);
926 ret = hns3_enable_vlan_filter(hns, true);
928 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
932 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
933 RTE_ETHER_TYPE_VLAN);
935 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
940 * When in the reinit dev stage of the reset process, the following
941 * vlan-related configurations may differ from those at initialization,
942 * we will restore configurations to hardware in hns3_restore_vlan_table
943 * and hns3_restore_vlan_conf later.
945 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
946 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
948 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
952 ret = hns3_en_hw_strip_rxvtag(hns, false);
954 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
960 return hns3_default_vlan_config(hns);
964 hns3_restore_vlan_conf(struct hns3_adapter *hns)
966 struct hns3_pf *pf = &hns->pf;
967 struct hns3_hw *hw = &hns->hw;
970 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
972 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
976 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
978 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
984 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
986 struct hns3_adapter *hns = dev->data->dev_private;
987 struct rte_eth_dev_data *data = dev->data;
988 struct rte_eth_txmode *txmode;
989 struct hns3_hw *hw = &hns->hw;
992 txmode = &data->dev_conf.txmode;
993 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
995 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
996 "configuration is not supported! Ignore these two "
997 "parameters: hw_vlan_reject_tagged(%d), "
998 "hw_vlan_reject_untagged(%d)",
999 txmode->hw_vlan_reject_tagged,
1000 txmode->hw_vlan_reject_untagged);
1002 /* Apply vlan offload setting */
1003 ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1005 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
1009 /* Apply pvid setting */
1010 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1011 txmode->hw_vlan_insert_pvid);
1013 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
1020 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1021 unsigned int tso_mss_max)
1023 struct hns3_cfg_tso_status_cmd *req;
1024 struct hns3_cmd_desc desc;
1027 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1029 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1032 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1034 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1037 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1039 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1041 return hns3_cmd_send(hw, &desc, 1);
1045 hns3_config_gro(struct hns3_hw *hw, bool en)
1047 struct hns3_cfg_gro_status_cmd *req;
1048 struct hns3_cmd_desc desc;
1051 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1052 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1054 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1056 ret = hns3_cmd_send(hw, &desc, 1);
1058 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1064 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1065 uint16_t *allocated_size, bool is_alloc)
1067 struct hns3_umv_spc_alc_cmd *req;
1068 struct hns3_cmd_desc desc;
1071 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1072 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1073 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1074 req->space_size = rte_cpu_to_le_32(space_size);
1076 ret = hns3_cmd_send(hw, &desc, 1);
1078 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1079 is_alloc ? "allocate" : "free", ret);
1083 if (is_alloc && allocated_size)
1084 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1090 hns3_init_umv_space(struct hns3_hw *hw)
1092 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1093 struct hns3_pf *pf = &hns->pf;
1094 uint16_t allocated_size = 0;
1097 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1102 if (allocated_size < pf->wanted_umv_size)
1103 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1104 pf->wanted_umv_size, allocated_size);
1106 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1107 pf->wanted_umv_size;
1108 pf->used_umv_size = 0;
1113 hns3_uninit_umv_space(struct hns3_hw *hw)
1115 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1116 struct hns3_pf *pf = &hns->pf;
1119 if (pf->max_umv_size == 0)
1122 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1126 pf->max_umv_size = 0;
1132 hns3_is_umv_space_full(struct hns3_hw *hw)
1134 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1135 struct hns3_pf *pf = &hns->pf;
1138 is_full = (pf->used_umv_size >= pf->max_umv_size);
1144 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1146 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1147 struct hns3_pf *pf = &hns->pf;
1150 if (pf->used_umv_size > 0)
1151 pf->used_umv_size--;
1153 pf->used_umv_size++;
1157 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1158 const uint8_t *addr, bool is_mc)
1160 const unsigned char *mac_addr = addr;
1161 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1162 ((uint32_t)mac_addr[2] << 16) |
1163 ((uint32_t)mac_addr[1] << 8) |
1164 (uint32_t)mac_addr[0];
1165 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1167 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1169 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1170 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1171 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1174 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1175 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1179 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1181 enum hns3_mac_vlan_tbl_opcode op)
1184 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1189 if (op == HNS3_MAC_VLAN_ADD) {
1190 if (resp_code == 0 || resp_code == 1) {
1192 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1193 hns3_err(hw, "add mac addr failed for uc_overflow");
1195 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1196 hns3_err(hw, "add mac addr failed for mc_overflow");
1200 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1203 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1204 if (resp_code == 0) {
1206 } else if (resp_code == 1) {
1207 hns3_dbg(hw, "remove mac addr failed for miss");
1211 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1214 } else if (op == HNS3_MAC_VLAN_LKUP) {
1215 if (resp_code == 0) {
1217 } else if (resp_code == 1) {
1218 hns3_dbg(hw, "lookup mac addr failed for miss");
1222 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1227 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1234 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1235 struct hns3_mac_vlan_tbl_entry_cmd *req,
1236 struct hns3_cmd_desc *desc, bool is_mc)
1242 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1244 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1245 memcpy(desc[0].data, req,
1246 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1247 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1249 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1250 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1252 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1254 memcpy(desc[0].data, req,
1255 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1256 ret = hns3_cmd_send(hw, desc, 1);
1259 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1263 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1264 retval = rte_le_to_cpu_16(desc[0].retval);
1266 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1267 HNS3_MAC_VLAN_LKUP);
1271 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1272 struct hns3_mac_vlan_tbl_entry_cmd *req,
1273 struct hns3_cmd_desc *mc_desc)
1280 if (mc_desc == NULL) {
1281 struct hns3_cmd_desc desc;
1283 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1284 memcpy(desc.data, req,
1285 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1286 ret = hns3_cmd_send(hw, &desc, 1);
1287 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1288 retval = rte_le_to_cpu_16(desc.retval);
1290 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1293 hns3_cmd_reuse_desc(&mc_desc[0], false);
1294 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1295 hns3_cmd_reuse_desc(&mc_desc[1], false);
1296 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1297 hns3_cmd_reuse_desc(&mc_desc[2], false);
1298 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1299 memcpy(mc_desc[0].data, req,
1300 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1301 mc_desc[0].retval = 0;
1302 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1303 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1304 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1306 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1311 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1319 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1320 struct hns3_mac_vlan_tbl_entry_cmd *req)
1322 struct hns3_cmd_desc desc;
1327 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1329 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1331 ret = hns3_cmd_send(hw, &desc, 1);
1333 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1336 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1337 retval = rte_le_to_cpu_16(desc.retval);
1339 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1340 HNS3_MAC_VLAN_REMOVE);
1344 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1346 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1347 struct hns3_mac_vlan_tbl_entry_cmd req;
1348 struct hns3_pf *pf = &hns->pf;
1349 struct hns3_cmd_desc desc;
1350 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1351 uint16_t egress_port = 0;
1355 /* check if mac addr is valid */
1356 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1357 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1359 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1364 memset(&req, 0, sizeof(req));
1367 * In current version VF is not supported when PF is driven by DPDK
1368 * driver, the PF-related vf_id is 0, just need to configure parameters
1372 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1373 HNS3_MAC_EPORT_VFID_S, vf_id);
1375 req.egress_port = rte_cpu_to_le_16(egress_port);
1377 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1380 * Lookup the mac address in the mac_vlan table, and add
1381 * it if the entry is inexistent. Repeated unicast entry
1382 * is not allowed in the mac vlan table.
1384 ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1385 if (ret == -ENOENT) {
1386 if (!hns3_is_umv_space_full(hw)) {
1387 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1389 hns3_update_umv_space(hw, false);
1393 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1398 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1400 /* check if we just hit the duplicate */
1402 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1406 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1413 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1414 uint32_t idx, __rte_unused uint32_t pool)
1416 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1420 rte_spinlock_lock(&hw->lock);
1421 ret = hns3_add_uc_addr_common(hw, mac_addr);
1423 rte_spinlock_unlock(&hw->lock);
1424 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1426 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1431 hw->mac.default_addr_setted = true;
1432 rte_spinlock_unlock(&hw->lock);
1438 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1440 struct hns3_mac_vlan_tbl_entry_cmd req;
1441 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1444 /* check if mac addr is valid */
1445 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1446 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1448 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1453 memset(&req, 0, sizeof(req));
1454 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1455 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1456 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1457 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1460 hns3_update_umv_space(hw, true);
1466 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1468 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1469 /* index will be checked by upper level rte interface */
1470 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1471 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1474 rte_spinlock_lock(&hw->lock);
1475 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1477 rte_spinlock_unlock(&hw->lock);
1478 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1480 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1484 rte_spinlock_unlock(&hw->lock);
1488 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1489 struct rte_ether_addr *mac_addr)
1491 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1492 struct rte_ether_addr *oaddr;
1493 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1494 bool default_addr_setted;
1495 bool rm_succes = false;
1499 * It has been guaranteed that input parameter named mac_addr is valid
1500 * address in the rte layer of DPDK framework.
1502 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1503 default_addr_setted = hw->mac.default_addr_setted;
1504 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1507 rte_spinlock_lock(&hw->lock);
1508 if (default_addr_setted) {
1509 ret = hns3_remove_uc_addr_common(hw, oaddr);
1511 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1513 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1520 ret = hns3_add_uc_addr_common(hw, mac_addr);
1522 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1524 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1525 goto err_add_uc_addr;
1528 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1530 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1531 goto err_pause_addr_cfg;
1534 rte_ether_addr_copy(mac_addr,
1535 (struct rte_ether_addr *)hw->mac.mac_addr);
1536 hw->mac.default_addr_setted = true;
1537 rte_spinlock_unlock(&hw->lock);
1542 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1544 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1547 "Failed to roll back to del setted mac addr(%s): %d",
1553 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1555 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1558 "Failed to restore old uc mac addr(%s): %d",
1560 hw->mac.default_addr_setted = false;
1563 rte_spinlock_unlock(&hw->lock);
1569 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1571 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1572 struct hns3_hw *hw = &hns->hw;
1573 struct rte_ether_addr *addr;
1578 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1579 addr = &hw->data->mac_addrs[i];
1580 if (!rte_is_valid_assigned_ether_addr(addr))
1583 ret = hns3_remove_uc_addr_common(hw, addr);
1585 ret = hns3_add_uc_addr_common(hw, addr);
1588 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1591 "Failed to %s mac addr(%s). ret:%d i:%d",
1592 del ? "remove" : "restore", mac_str, ret, i);
1599 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1601 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1605 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1606 word_num = vfid / 32;
1607 bit_num = vfid % 32;
1609 desc[1].data[word_num] &=
1610 rte_cpu_to_le_32(~(1UL << bit_num));
1612 desc[1].data[word_num] |=
1613 rte_cpu_to_le_32(1UL << bit_num);
1615 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1616 bit_num = vfid % 32;
1618 desc[2].data[word_num] &=
1619 rte_cpu_to_le_32(~(1UL << bit_num));
1621 desc[2].data[word_num] |=
1622 rte_cpu_to_le_32(1UL << bit_num);
1627 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1629 struct hns3_mac_vlan_tbl_entry_cmd req;
1630 struct hns3_cmd_desc desc[3];
1631 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1635 /* Check if mac addr is valid */
1636 if (!rte_is_multicast_ether_addr(mac_addr)) {
1637 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1639 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1644 memset(&req, 0, sizeof(req));
1645 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1646 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1647 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1649 /* This mac addr do not exist, add new entry for it */
1650 memset(desc[0].data, 0, sizeof(desc[0].data));
1651 memset(desc[1].data, 0, sizeof(desc[0].data));
1652 memset(desc[2].data, 0, sizeof(desc[0].data));
1656 * In current version VF is not supported when PF is driven by DPDK
1657 * driver, the PF-related vf_id is 0, just need to configure parameters
1661 hns3_update_desc_vfid(desc, vf_id, false);
1662 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1665 hns3_err(hw, "mc mac vlan table is full");
1666 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1668 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1675 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1677 struct hns3_mac_vlan_tbl_entry_cmd req;
1678 struct hns3_cmd_desc desc[3];
1679 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1683 /* Check if mac addr is valid */
1684 if (!rte_is_multicast_ether_addr(mac_addr)) {
1685 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1687 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1692 memset(&req, 0, sizeof(req));
1693 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1694 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1695 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1698 * This mac addr exist, remove this handle's VFID for it.
1699 * In current version VF is not supported when PF is driven by
1700 * DPDK driver, the PF-related vf_id is 0, just need to
1701 * configure parameters for vf_id 0.
1704 hns3_update_desc_vfid(desc, vf_id, true);
1706 /* All the vfid is zero, so need to delete this entry */
1707 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1708 } else if (ret == -ENOENT) {
1709 /* This mac addr doesn't exist. */
1714 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1716 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1723 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1724 struct rte_ether_addr *mc_addr_set,
1725 uint32_t nb_mc_addr)
1727 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1728 struct rte_ether_addr *addr;
1732 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1733 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1734 "invalid. valid range: 0~%d",
1735 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1739 /* Check if input mac addresses are valid */
1740 for (i = 0; i < nb_mc_addr; i++) {
1741 addr = &mc_addr_set[i];
1742 if (!rte_is_multicast_ether_addr(addr)) {
1743 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1746 "Failed to set mc mac addr, addr(%s) invalid.",
1751 /* Check if there are duplicate addresses */
1752 for (j = i + 1; j < nb_mc_addr; j++) {
1753 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1754 rte_ether_format_addr(mac_str,
1755 RTE_ETHER_ADDR_FMT_SIZE,
1757 hns3_err(hw, "Failed to set mc mac addr, "
1758 "addrs invalid. two same addrs(%s).",
1769 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1770 struct rte_ether_addr *mc_addr_set,
1772 struct rte_ether_addr *reserved_addr_list,
1773 int *reserved_addr_num,
1774 struct rte_ether_addr *add_addr_list,
1776 struct rte_ether_addr *rm_addr_list,
1779 struct rte_ether_addr *addr;
1780 int current_addr_num;
1781 int reserved_num = 0;
1789 /* Calculate the mc mac address list that should be removed */
1790 current_addr_num = hw->mc_addrs_num;
1791 for (i = 0; i < current_addr_num; i++) {
1792 addr = &hw->mc_addrs[i];
1794 for (j = 0; j < mc_addr_num; j++) {
1795 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1802 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1805 rte_ether_addr_copy(addr,
1806 &reserved_addr_list[reserved_num]);
1811 /* Calculate the mc mac address list that should be added */
1812 for (i = 0; i < mc_addr_num; i++) {
1813 addr = &mc_addr_set[i];
1815 for (j = 0; j < current_addr_num; j++) {
1816 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1823 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1828 /* Reorder the mc mac address list maintained by driver */
1829 for (i = 0; i < reserved_num; i++)
1830 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1832 for (i = 0; i < rm_num; i++) {
1833 num = reserved_num + i;
1834 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1837 *reserved_addr_num = reserved_num;
1838 *add_addr_num = add_num;
1839 *rm_addr_num = rm_num;
1843 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1844 struct rte_ether_addr *mc_addr_set,
1845 uint32_t nb_mc_addr)
1847 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1848 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1849 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1850 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1851 struct rte_ether_addr *addr;
1852 int reserved_addr_num;
1860 /* Check if input parameters are valid */
1861 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1865 rte_spinlock_lock(&hw->lock);
1868 * Calculate the mc mac address lists those should be removed and be
1869 * added, Reorder the mc mac address list maintained by driver.
1871 mc_addr_num = (int)nb_mc_addr;
1872 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1873 reserved_addr_list, &reserved_addr_num,
1874 add_addr_list, &add_addr_num,
1875 rm_addr_list, &rm_addr_num);
1877 /* Remove mc mac addresses */
1878 for (i = 0; i < rm_addr_num; i++) {
1879 num = rm_addr_num - i - 1;
1880 addr = &rm_addr_list[num];
1881 ret = hns3_remove_mc_addr(hw, addr);
1883 rte_spinlock_unlock(&hw->lock);
1889 /* Add mc mac addresses */
1890 for (i = 0; i < add_addr_num; i++) {
1891 addr = &add_addr_list[i];
1892 ret = hns3_add_mc_addr(hw, addr);
1894 rte_spinlock_unlock(&hw->lock);
1898 num = reserved_addr_num + i;
1899 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1902 rte_spinlock_unlock(&hw->lock);
1908 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1910 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1911 struct hns3_hw *hw = &hns->hw;
1912 struct rte_ether_addr *addr;
1917 for (i = 0; i < hw->mc_addrs_num; i++) {
1918 addr = &hw->mc_addrs[i];
1919 if (!rte_is_multicast_ether_addr(addr))
1922 ret = hns3_remove_mc_addr(hw, addr);
1924 ret = hns3_add_mc_addr(hw, addr);
1927 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1929 hns3_dbg(hw, "%s mc mac addr: %s failed",
1930 del ? "Remove" : "Restore", mac_str);
1937 hns3_check_mq_mode(struct rte_eth_dev *dev)
1939 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1940 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1941 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1943 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1944 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1949 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1950 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1952 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1953 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
1954 "rx_mq_mode = %d", rx_mq_mode);
1958 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
1959 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1960 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
1961 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
1962 rx_mq_mode, tx_mq_mode);
1966 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
1967 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1968 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1969 dcb_rx_conf->nb_tcs, pf->tc_max);
1973 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1974 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1975 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
1976 "nb_tcs(%d) != %d or %d in rx direction.",
1977 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1981 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1982 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1983 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1987 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1988 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1989 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
1990 "is not equal to one in tx direction.",
1991 i, dcb_rx_conf->dcb_tc[i]);
1994 if (dcb_rx_conf->dcb_tc[i] > max_tc)
1995 max_tc = dcb_rx_conf->dcb_tc[i];
1998 num_tc = max_tc + 1;
1999 if (num_tc > dcb_rx_conf->nb_tcs) {
2000 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2001 num_tc, dcb_rx_conf->nb_tcs);
2010 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2012 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2014 if (!hns3_dev_dcb_supported(hw)) {
2015 hns3_err(hw, "this port does not support dcb configurations.");
2019 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2020 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2024 /* Check multiple queue mode */
2025 return hns3_check_mq_mode(dev);
2029 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2030 enum hns3_ring_type queue_type, uint16_t queue_id)
2032 struct hns3_cmd_desc desc;
2033 struct hns3_ctrl_vector_chain_cmd *req =
2034 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2035 enum hns3_cmd_status status;
2036 enum hns3_opcode_type op;
2037 uint16_t tqp_type_and_id = 0;
2042 op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2043 hns3_cmd_setup_basic_desc(&desc, op, false);
2044 req->int_vector_id = vector_id;
2046 if (queue_type == HNS3_RING_TYPE_RX)
2047 gl = HNS3_RING_GL_RX;
2049 gl = HNS3_RING_GL_TX;
2053 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2055 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2056 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2058 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2059 req->int_cause_num = 1;
2060 op_str = mmap ? "Map" : "Unmap";
2061 status = hns3_cmd_send(hw, &desc, 1);
2063 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2064 op_str, queue_id, req->int_vector_id, status);
2072 hns3_init_ring_with_vector(struct hns3_hw *hw)
2079 * In hns3 network engine, vector 0 is always the misc interrupt of this
2080 * function, vector 1~N can be used respectively for the queues of the
2081 * function. Tx and Rx queues with the same number share the interrupt
2082 * vector. In the initialization clearing the all hardware mapping
2083 * relationship configurations between queues and interrupt vectors is
2084 * needed, so some error caused by the residual configurations, such as
2085 * the unexpected Tx interrupt, can be avoid. Because of the hardware
2086 * constraints in hns3 hardware engine, we have to implement clearing
2087 * the mapping relationship configurations by binding all queues to the
2088 * last interrupt vector and reserving the last interrupt vector. This
2089 * method results in a decrease of the maximum queues when upper
2090 * applications call the rte_eth_dev_configure API function to enable
2093 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2094 hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
2095 for (i = 0; i < hw->intr_tqps_num; i++) {
2097 * Set gap limiter and rate limiter configuration of queue's
2100 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2101 HNS3_TQP_INTR_GL_DEFAULT);
2102 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2103 HNS3_TQP_INTR_GL_DEFAULT);
2104 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2106 ret = hns3_bind_ring_with_vector(hw, vec, false,
2107 HNS3_RING_TYPE_TX, i);
2109 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2110 "vector: %d, ret=%d", i, vec, ret);
2114 ret = hns3_bind_ring_with_vector(hw, vec, false,
2115 HNS3_RING_TYPE_RX, i);
2117 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2118 "vector: %d, ret=%d", i, vec, ret);
2127 hns3_dev_configure(struct rte_eth_dev *dev)
2129 struct hns3_adapter *hns = dev->data->dev_private;
2130 struct rte_eth_conf *conf = &dev->data->dev_conf;
2131 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2132 struct hns3_hw *hw = &hns->hw;
2133 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2134 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2135 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2136 struct rte_eth_rss_conf rss_conf;
2141 * Hardware does not support individually enable/disable/reset the Tx or
2142 * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2143 * and Rx queues at the same time. When the numbers of Tx queues
2144 * allocated by upper applications are not equal to the numbers of Rx
2145 * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2146 * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2147 * these fake queues are imperceptible, and can not be used by upper
2150 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2152 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2156 hw->adapter_state = HNS3_NIC_CONFIGURING;
2157 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2158 hns3_err(hw, "setting link speed/duplex not supported");
2163 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2164 ret = hns3_check_dcb_cfg(dev);
2169 /* When RSS is not configured, redirect the packet queue 0 */
2170 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2171 rss_conf = conf->rx_adv_conf.rss_conf;
2172 if (rss_conf.rss_key == NULL) {
2173 rss_conf.rss_key = rss_cfg->key;
2174 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2177 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2183 * If jumbo frames are enabled, MTU needs to be refreshed
2184 * according to the maximum RX packet length.
2186 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2188 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2189 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2190 * can safely assign to "uint16_t" type variable.
2192 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2193 ret = hns3_dev_mtu_set(dev, mtu);
2196 dev->data->mtu = mtu;
2199 ret = hns3_dev_configure_vlan(dev);
2203 hw->adapter_state = HNS3_NIC_CONFIGURED;
2208 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2209 hw->adapter_state = HNS3_NIC_INITIALIZED;
2215 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2217 struct hns3_config_max_frm_size_cmd *req;
2218 struct hns3_cmd_desc desc;
2220 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2222 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2223 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2224 req->min_frm_size = RTE_ETHER_MIN_LEN;
2226 return hns3_cmd_send(hw, &desc, 1);
2230 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2234 ret = hns3_set_mac_mtu(hw, mps);
2236 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2240 ret = hns3_buffer_alloc(hw);
2242 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2250 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2252 struct hns3_adapter *hns = dev->data->dev_private;
2253 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2254 struct hns3_hw *hw = &hns->hw;
2255 bool is_jumbo_frame;
2258 if (dev->data->dev_started) {
2259 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2260 "before configuration", dev->data->port_id);
2264 rte_spinlock_lock(&hw->lock);
2265 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2266 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2269 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2270 * assign to "uint16_t" type variable.
2272 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2274 rte_spinlock_unlock(&hw->lock);
2275 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2276 dev->data->port_id, mtu, ret);
2279 hns->pf.mps = (uint16_t)frame_size;
2281 dev->data->dev_conf.rxmode.offloads |=
2282 DEV_RX_OFFLOAD_JUMBO_FRAME;
2284 dev->data->dev_conf.rxmode.offloads &=
2285 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2286 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2287 rte_spinlock_unlock(&hw->lock);
2293 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2295 struct hns3_adapter *hns = eth_dev->data->dev_private;
2296 struct hns3_hw *hw = &hns->hw;
2297 uint16_t queue_num = hw->tqps_num;
2300 * In interrupt mode, 'max_rx_queues' is set based on the number of
2301 * MSI-X interrupt resources of the hardware.
2303 if (hw->data->dev_conf.intr_conf.rxq == 1)
2304 queue_num = hw->intr_tqps_num;
2306 info->max_rx_queues = queue_num;
2307 info->max_tx_queues = hw->tqps_num;
2308 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2309 info->min_rx_bufsize = hw->rx_buf_len;
2310 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2311 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2312 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2313 DEV_RX_OFFLOAD_TCP_CKSUM |
2314 DEV_RX_OFFLOAD_UDP_CKSUM |
2315 DEV_RX_OFFLOAD_SCTP_CKSUM |
2316 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2317 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2318 DEV_RX_OFFLOAD_KEEP_CRC |
2319 DEV_RX_OFFLOAD_SCATTER |
2320 DEV_RX_OFFLOAD_VLAN_STRIP |
2321 DEV_RX_OFFLOAD_QINQ_STRIP |
2322 DEV_RX_OFFLOAD_VLAN_FILTER |
2323 DEV_RX_OFFLOAD_VLAN_EXTEND |
2324 DEV_RX_OFFLOAD_JUMBO_FRAME);
2325 info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2326 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2327 DEV_TX_OFFLOAD_IPV4_CKSUM |
2328 DEV_TX_OFFLOAD_TCP_CKSUM |
2329 DEV_TX_OFFLOAD_UDP_CKSUM |
2330 DEV_TX_OFFLOAD_SCTP_CKSUM |
2331 DEV_TX_OFFLOAD_VLAN_INSERT |
2332 DEV_TX_OFFLOAD_QINQ_INSERT |
2333 DEV_TX_OFFLOAD_MULTI_SEGS |
2334 DEV_TX_OFFLOAD_TCP_TSO |
2335 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2336 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2337 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2338 info->tx_queue_offload_capa);
2340 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2341 .nb_max = HNS3_MAX_RING_DESC,
2342 .nb_min = HNS3_MIN_RING_DESC,
2343 .nb_align = HNS3_ALIGN_RING_DESC,
2346 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2347 .nb_max = HNS3_MAX_RING_DESC,
2348 .nb_min = HNS3_MIN_RING_DESC,
2349 .nb_align = HNS3_ALIGN_RING_DESC,
2352 info->vmdq_queue_num = 0;
2354 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2355 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2356 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2358 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2359 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2360 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2361 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2362 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2363 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2369 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2372 struct hns3_adapter *hns = eth_dev->data->dev_private;
2373 struct hns3_hw *hw = &hns->hw;
2376 ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2377 ret += 1; /* add the size of '\0' */
2378 if (fw_size < (uint32_t)ret)
2385 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2386 __rte_unused int wait_to_complete)
2388 struct hns3_adapter *hns = eth_dev->data->dev_private;
2389 struct hns3_hw *hw = &hns->hw;
2390 struct hns3_mac *mac = &hw->mac;
2391 struct rte_eth_link new_link;
2393 if (!hns3_is_reset_pending(hns)) {
2394 hns3_update_speed_duplex(eth_dev);
2395 hns3_update_link_status(hw);
2398 memset(&new_link, 0, sizeof(new_link));
2399 switch (mac->link_speed) {
2400 case ETH_SPEED_NUM_10M:
2401 case ETH_SPEED_NUM_100M:
2402 case ETH_SPEED_NUM_1G:
2403 case ETH_SPEED_NUM_10G:
2404 case ETH_SPEED_NUM_25G:
2405 case ETH_SPEED_NUM_40G:
2406 case ETH_SPEED_NUM_50G:
2407 case ETH_SPEED_NUM_100G:
2408 new_link.link_speed = mac->link_speed;
2411 new_link.link_speed = ETH_SPEED_NUM_100M;
2415 new_link.link_duplex = mac->link_duplex;
2416 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2417 new_link.link_autoneg =
2418 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2420 return rte_eth_linkstatus_set(eth_dev, &new_link);
2424 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2426 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2427 struct hns3_pf *pf = &hns->pf;
2429 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2432 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2438 hns3_query_function_status(struct hns3_hw *hw)
2440 #define HNS3_QUERY_MAX_CNT 10
2441 #define HNS3_QUERY_SLEEP_MSCOEND 1
2442 struct hns3_func_status_cmd *req;
2443 struct hns3_cmd_desc desc;
2447 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2448 req = (struct hns3_func_status_cmd *)desc.data;
2451 ret = hns3_cmd_send(hw, &desc, 1);
2453 PMD_INIT_LOG(ERR, "query function status failed %d",
2458 /* Check pf reset is done */
2462 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2463 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2465 return hns3_parse_func_status(hw, req);
2469 hns3_query_pf_resource(struct hns3_hw *hw)
2471 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2472 struct hns3_pf *pf = &hns->pf;
2473 struct hns3_pf_res_cmd *req;
2474 struct hns3_cmd_desc desc;
2478 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2479 ret = hns3_cmd_send(hw, &desc, 1);
2481 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2485 req = (struct hns3_pf_res_cmd *)desc.data;
2486 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2487 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2488 hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2489 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2491 if (req->tx_buf_size)
2493 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2495 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2497 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2499 if (req->dv_buf_size)
2501 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2503 pf->dv_buf_size = HNS3_DEFAULT_DV;
2505 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2507 num_msi = hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2508 HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2509 hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
2515 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2517 struct hns3_cfg_param_cmd *req;
2518 uint64_t mac_addr_tmp_high;
2519 uint64_t mac_addr_tmp;
2522 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2524 /* get the configuration */
2525 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2526 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2527 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2528 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2529 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2530 HNS3_CFG_TQP_DESC_N_M,
2531 HNS3_CFG_TQP_DESC_N_S);
2533 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2534 HNS3_CFG_PHY_ADDR_M,
2535 HNS3_CFG_PHY_ADDR_S);
2536 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2537 HNS3_CFG_MEDIA_TP_M,
2538 HNS3_CFG_MEDIA_TP_S);
2539 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2540 HNS3_CFG_RX_BUF_LEN_M,
2541 HNS3_CFG_RX_BUF_LEN_S);
2542 /* get mac address */
2543 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2544 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2545 HNS3_CFG_MAC_ADDR_H_M,
2546 HNS3_CFG_MAC_ADDR_H_S);
2548 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2550 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2551 HNS3_CFG_DEFAULT_SPEED_M,
2552 HNS3_CFG_DEFAULT_SPEED_S);
2553 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2554 HNS3_CFG_RSS_SIZE_M,
2555 HNS3_CFG_RSS_SIZE_S);
2557 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2558 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2560 req = (struct hns3_cfg_param_cmd *)desc[1].data;
2561 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2563 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2564 HNS3_CFG_SPEED_ABILITY_M,
2565 HNS3_CFG_SPEED_ABILITY_S);
2566 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2567 HNS3_CFG_UMV_TBL_SPACE_M,
2568 HNS3_CFG_UMV_TBL_SPACE_S);
2569 if (!cfg->umv_space)
2570 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2573 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2574 * @hw: pointer to struct hns3_hw
2575 * @hcfg: the config structure to be getted
2578 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2580 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2581 struct hns3_cfg_param_cmd *req;
2586 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2588 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2589 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2591 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2592 i * HNS3_CFG_RD_LEN_BYTES);
2593 /* Len should be divided by 4 when send to hardware */
2594 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2595 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2596 req->offset = rte_cpu_to_le_32(offset);
2599 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2601 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2605 hns3_parse_cfg(hcfg, desc);
2611 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2613 switch (speed_cmd) {
2614 case HNS3_CFG_SPEED_10M:
2615 *speed = ETH_SPEED_NUM_10M;
2617 case HNS3_CFG_SPEED_100M:
2618 *speed = ETH_SPEED_NUM_100M;
2620 case HNS3_CFG_SPEED_1G:
2621 *speed = ETH_SPEED_NUM_1G;
2623 case HNS3_CFG_SPEED_10G:
2624 *speed = ETH_SPEED_NUM_10G;
2626 case HNS3_CFG_SPEED_25G:
2627 *speed = ETH_SPEED_NUM_25G;
2629 case HNS3_CFG_SPEED_40G:
2630 *speed = ETH_SPEED_NUM_40G;
2632 case HNS3_CFG_SPEED_50G:
2633 *speed = ETH_SPEED_NUM_50G;
2635 case HNS3_CFG_SPEED_100G:
2636 *speed = ETH_SPEED_NUM_100G;
2646 hns3_get_board_configuration(struct hns3_hw *hw)
2648 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2649 struct hns3_pf *pf = &hns->pf;
2650 struct hns3_cfg cfg;
2653 ret = hns3_get_board_cfg(hw, &cfg);
2655 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2659 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2660 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2664 hw->mac.media_type = cfg.media_type;
2665 hw->rss_size_max = cfg.rss_size_max;
2666 hw->rx_buf_len = cfg.rx_buf_len;
2667 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2668 hw->mac.phy_addr = cfg.phy_addr;
2669 hw->mac.default_addr_setted = false;
2670 hw->num_tx_desc = cfg.tqp_desc_num;
2671 hw->num_rx_desc = cfg.tqp_desc_num;
2672 hw->dcb_info.num_pg = 1;
2673 hw->dcb_info.hw_pfc_map = 0;
2675 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2677 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2678 cfg.default_speed, ret);
2682 pf->tc_max = cfg.tc_num;
2683 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2684 PMD_INIT_LOG(WARNING,
2685 "Get TC num(%u) from flash, set TC num to 1",
2690 /* Dev does not support DCB */
2691 if (!hns3_dev_dcb_supported(hw)) {
2695 pf->pfc_max = pf->tc_max;
2697 hw->dcb_info.num_tc = 1;
2698 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2699 hw->tqps_num / hw->dcb_info.num_tc);
2700 hns3_set_bit(hw->hw_tc_map, 0, 1);
2701 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2703 pf->wanted_umv_size = cfg.umv_space;
2709 hns3_get_configuration(struct hns3_hw *hw)
2713 ret = hns3_query_function_status(hw);
2715 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2719 /* Get pf resource */
2720 ret = hns3_query_pf_resource(hw);
2722 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2726 ret = hns3_get_board_configuration(hw);
2728 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2736 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2737 uint16_t tqp_vid, bool is_pf)
2739 struct hns3_tqp_map_cmd *req;
2740 struct hns3_cmd_desc desc;
2743 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2745 req = (struct hns3_tqp_map_cmd *)desc.data;
2746 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2747 req->tqp_vf = func_id;
2748 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2750 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2751 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2753 ret = hns3_cmd_send(hw, &desc, 1);
2755 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2761 hns3_map_tqp(struct hns3_hw *hw)
2763 uint16_t tqps_num = hw->total_tqps_num;
2772 * In current version VF is not supported when PF is driven by DPDK
2773 * driver, so we allocate tqps to PF as much as possible.
2776 num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2777 for (func_id = 0; func_id < num; func_id++) {
2778 is_pf = func_id == 0 ? true : false;
2780 i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2781 ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2792 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2794 struct hns3_config_mac_speed_dup_cmd *req;
2795 struct hns3_cmd_desc desc;
2798 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2800 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2802 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2805 case ETH_SPEED_NUM_10M:
2806 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2807 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2809 case ETH_SPEED_NUM_100M:
2810 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2811 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2813 case ETH_SPEED_NUM_1G:
2814 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2815 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2817 case ETH_SPEED_NUM_10G:
2818 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2819 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2821 case ETH_SPEED_NUM_25G:
2822 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2823 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2825 case ETH_SPEED_NUM_40G:
2826 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2827 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2829 case ETH_SPEED_NUM_50G:
2830 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2831 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2833 case ETH_SPEED_NUM_100G:
2834 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2835 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2838 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2842 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2844 ret = hns3_cmd_send(hw, &desc, 1);
2846 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2852 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2854 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2855 struct hns3_pf *pf = &hns->pf;
2856 struct hns3_priv_buf *priv;
2857 uint32_t i, total_size;
2859 total_size = pf->pkt_buf_size;
2861 /* alloc tx buffer for all enabled tc */
2862 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2863 priv = &buf_alloc->priv_buf[i];
2865 if (hw->hw_tc_map & BIT(i)) {
2866 if (total_size < pf->tx_buf_size)
2869 priv->tx_buf_size = pf->tx_buf_size;
2871 priv->tx_buf_size = 0;
2873 total_size -= priv->tx_buf_size;
2880 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2882 /* TX buffer size is unit by 128 byte */
2883 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
2884 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
2885 struct hns3_tx_buff_alloc_cmd *req;
2886 struct hns3_cmd_desc desc;
2891 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2893 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2894 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2895 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2897 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2898 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2899 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2902 ret = hns3_cmd_send(hw, &desc, 1);
2904 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2910 hns3_get_tc_num(struct hns3_hw *hw)
2915 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2916 if (hw->hw_tc_map & BIT(i))
2922 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2924 struct hns3_priv_buf *priv;
2925 uint32_t rx_priv = 0;
2928 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2929 priv = &buf_alloc->priv_buf[i];
2931 rx_priv += priv->buf_size;
2937 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2939 uint32_t total_tx_size = 0;
2942 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2943 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2945 return total_tx_size;
2948 /* Get the number of pfc enabled TCs, which have private buffer */
2950 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2952 struct hns3_priv_buf *priv;
2956 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2957 priv = &buf_alloc->priv_buf[i];
2958 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2965 /* Get the number of pfc disabled TCs, which have private buffer */
2967 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2968 struct hns3_pkt_buf_alloc *buf_alloc)
2970 struct hns3_priv_buf *priv;
2974 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2975 priv = &buf_alloc->priv_buf[i];
2976 if (hw->hw_tc_map & BIT(i) &&
2977 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2985 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2988 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2989 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2990 struct hns3_pf *pf = &hns->pf;
2991 uint32_t shared_buf, aligned_mps;
2996 tc_num = hns3_get_tc_num(hw);
2997 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2999 if (hns3_dev_dcb_supported(hw))
3000 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3003 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3006 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3007 shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3008 HNS3_BUF_SIZE_UNIT);
3010 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3011 if (rx_all < rx_priv + shared_std)
3014 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3015 buf_alloc->s_buf.buf_size = shared_buf;
3016 if (hns3_dev_dcb_supported(hw)) {
3017 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3018 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3019 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3020 HNS3_BUF_SIZE_UNIT);
3022 buf_alloc->s_buf.self.high =
3023 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3024 buf_alloc->s_buf.self.low = aligned_mps;
3027 if (hns3_dev_dcb_supported(hw)) {
3028 hi_thrd = shared_buf - pf->dv_buf_size;
3030 if (tc_num <= NEED_RESERVE_TC_NUM)
3031 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3035 hi_thrd = hi_thrd / tc_num;
3037 hi_thrd = max_t(uint32_t, hi_thrd,
3038 HNS3_BUF_MUL_BY * aligned_mps);
3039 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3040 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3042 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3043 lo_thrd = aligned_mps;
3046 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3047 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3048 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3055 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3056 struct hns3_pkt_buf_alloc *buf_alloc)
3058 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3059 struct hns3_pf *pf = &hns->pf;
3060 struct hns3_priv_buf *priv;
3061 uint32_t aligned_mps;
3065 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3066 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3068 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3069 priv = &buf_alloc->priv_buf[i];
3076 if (!(hw->hw_tc_map & BIT(i)))
3080 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3081 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3082 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3083 HNS3_BUF_SIZE_UNIT);
3086 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3090 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3093 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3097 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3098 struct hns3_pkt_buf_alloc *buf_alloc)
3100 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3101 struct hns3_pf *pf = &hns->pf;
3102 struct hns3_priv_buf *priv;
3103 int no_pfc_priv_num;
3108 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3109 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3111 /* let the last to be cleared first */
3112 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3113 priv = &buf_alloc->priv_buf[i];
3114 mask = BIT((uint8_t)i);
3116 if (hw->hw_tc_map & mask &&
3117 !(hw->dcb_info.hw_pfc_map & mask)) {
3118 /* Clear the no pfc TC private buffer */
3126 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3127 no_pfc_priv_num == 0)
3131 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3135 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3136 struct hns3_pkt_buf_alloc *buf_alloc)
3138 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3139 struct hns3_pf *pf = &hns->pf;
3140 struct hns3_priv_buf *priv;
3146 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3147 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3149 /* let the last to be cleared first */
3150 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3151 priv = &buf_alloc->priv_buf[i];
3152 mask = BIT((uint8_t)i);
3154 if (hw->hw_tc_map & mask &&
3155 hw->dcb_info.hw_pfc_map & mask) {
3156 /* Reduce the number of pfc TC with private buffer */
3163 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3168 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3172 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3173 struct hns3_pkt_buf_alloc *buf_alloc)
3175 #define COMPENSATE_BUFFER 0x3C00
3176 #define COMPENSATE_HALF_MPS_NUM 5
3177 #define PRIV_WL_GAP 0x1800
3178 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3179 struct hns3_pf *pf = &hns->pf;
3180 uint32_t tc_num = hns3_get_tc_num(hw);
3181 uint32_t half_mps = pf->mps >> 1;
3182 struct hns3_priv_buf *priv;
3183 uint32_t min_rx_priv;
3187 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3189 rx_priv = rx_priv / tc_num;
3191 if (tc_num <= NEED_RESERVE_TC_NUM)
3192 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3195 * Minimum value of private buffer in rx direction (min_rx_priv) is
3196 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3197 * buffer if rx_priv is greater than min_rx_priv.
3199 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3200 COMPENSATE_HALF_MPS_NUM * half_mps;
3201 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3202 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3204 if (rx_priv < min_rx_priv)
3207 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3208 priv = &buf_alloc->priv_buf[i];
3215 if (!(hw->hw_tc_map & BIT(i)))
3219 priv->buf_size = rx_priv;
3220 priv->wl.high = rx_priv - pf->dv_buf_size;
3221 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3224 buf_alloc->s_buf.buf_size = 0;
3230 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3231 * @hw: pointer to struct hns3_hw
3232 * @buf_alloc: pointer to buffer calculation data
3233 * @return: 0: calculate sucessful, negative: fail
3236 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3238 /* When DCB is not supported, rx private buffer is not allocated. */
3239 if (!hns3_dev_dcb_supported(hw)) {
3240 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3241 struct hns3_pf *pf = &hns->pf;
3242 uint32_t rx_all = pf->pkt_buf_size;
3244 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3245 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3252 * Try to allocate privated packet buffer for all TCs without share
3255 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3259 * Try to allocate privated packet buffer for all TCs with share
3262 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3266 * For different application scenes, the enabled port number, TC number
3267 * and no_drop TC number are different. In order to obtain the better
3268 * performance, software could allocate the buffer size and configure
3269 * the waterline by tring to decrease the private buffer size according
3270 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3273 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3276 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3279 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3286 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3288 struct hns3_rx_priv_buff_cmd *req;
3289 struct hns3_cmd_desc desc;
3294 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3295 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3297 /* Alloc private buffer TCs */
3298 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3299 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3302 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3303 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3306 buf_size = buf_alloc->s_buf.buf_size;
3307 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3308 (1 << HNS3_TC0_PRI_BUF_EN_B));
3310 ret = hns3_cmd_send(hw, &desc, 1);
3312 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3318 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3320 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3321 struct hns3_rx_priv_wl_buf *req;
3322 struct hns3_priv_buf *priv;
3323 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3327 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3328 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3330 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3332 /* The first descriptor set the NEXT bit to 1 */
3334 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3336 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3338 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3339 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3341 priv = &buf_alloc->priv_buf[idx];
3342 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3344 req->tc_wl[j].high |=
3345 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3346 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3348 req->tc_wl[j].low |=
3349 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3353 /* Send 2 descriptor at one time */
3354 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3356 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3362 hns3_common_thrd_config(struct hns3_hw *hw,
3363 struct hns3_pkt_buf_alloc *buf_alloc)
3365 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3366 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3367 struct hns3_rx_com_thrd *req;
3368 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3369 struct hns3_tc_thrd *tc;
3374 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3375 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3377 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3379 /* The first descriptor set the NEXT bit to 1 */
3381 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3383 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3385 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3386 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3387 tc = &s_buf->tc_thrd[tc_idx];
3389 req->com_thrd[j].high =
3390 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3391 req->com_thrd[j].high |=
3392 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3393 req->com_thrd[j].low =
3394 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3395 req->com_thrd[j].low |=
3396 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3400 /* Send 2 descriptors at one time */
3401 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3403 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3409 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3411 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3412 struct hns3_rx_com_wl *req;
3413 struct hns3_cmd_desc desc;
3416 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3418 req = (struct hns3_rx_com_wl *)desc.data;
3419 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3420 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3422 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3423 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3425 ret = hns3_cmd_send(hw, &desc, 1);
3427 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3433 hns3_buffer_alloc(struct hns3_hw *hw)
3435 struct hns3_pkt_buf_alloc pkt_buf;
3438 memset(&pkt_buf, 0, sizeof(pkt_buf));
3439 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3442 "could not calc tx buffer size for all TCs %d",
3447 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3449 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3453 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3456 "could not calc rx priv buffer size for all TCs %d",
3461 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3463 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3467 if (hns3_dev_dcb_supported(hw)) {
3468 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3471 "could not configure rx private waterline %d",
3476 ret = hns3_common_thrd_config(hw, &pkt_buf);
3479 "could not configure common threshold %d",
3485 ret = hns3_common_wl_config(hw, &pkt_buf);
3487 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3494 hns3_mac_init(struct hns3_hw *hw)
3496 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3497 struct hns3_mac *mac = &hw->mac;
3498 struct hns3_pf *pf = &hns->pf;
3501 pf->support_sfp_query = true;
3502 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3503 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3505 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3509 mac->link_status = ETH_LINK_DOWN;
3511 return hns3_config_mtu(hw, pf->mps);
3515 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3517 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
3518 #define HNS3_ETHERTYPE_ALREADY_ADD 1
3519 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
3520 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
3525 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3530 switch (resp_code) {
3531 case HNS3_ETHERTYPE_SUCCESS_ADD:
3532 case HNS3_ETHERTYPE_ALREADY_ADD:
3535 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3537 "add mac ethertype failed for manager table overflow.");
3538 return_status = -EIO;
3540 case HNS3_ETHERTYPE_KEY_CONFLICT:
3541 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3542 return_status = -EIO;
3546 "add mac ethertype failed for undefined, code=%d.",
3548 return_status = -EIO;
3551 return return_status;
3555 hns3_add_mgr_tbl(struct hns3_hw *hw,
3556 const struct hns3_mac_mgr_tbl_entry_cmd *req)
3558 struct hns3_cmd_desc desc;
3563 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3564 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3566 ret = hns3_cmd_send(hw, &desc, 1);
3569 "add mac ethertype failed for cmd_send, ret =%d.",
3574 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3575 retval = rte_le_to_cpu_16(desc.retval);
3577 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3581 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3582 int *table_item_num)
3584 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3587 * In current version, we add one item in management table as below:
3588 * 0x0180C200000E -- LLDP MC address
3591 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3592 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3593 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3594 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3595 tbl->i_port_bitmap = 0x1;
3596 *table_item_num = 1;
3600 hns3_init_mgr_tbl(struct hns3_hw *hw)
3602 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
3603 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3608 memset(mgr_table, 0, sizeof(mgr_table));
3609 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3610 for (i = 0; i < table_item_num; i++) {
3611 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3613 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3623 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3624 bool en_mc, bool en_bc, int vport_id)
3629 memset(param, 0, sizeof(struct hns3_promisc_param));
3631 param->enable = HNS3_PROMISC_EN_UC;
3633 param->enable |= HNS3_PROMISC_EN_MC;
3635 param->enable |= HNS3_PROMISC_EN_BC;
3636 param->vf_id = vport_id;
3640 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3642 struct hns3_promisc_cfg_cmd *req;
3643 struct hns3_cmd_desc desc;
3646 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3648 req = (struct hns3_promisc_cfg_cmd *)desc.data;
3649 req->vf_id = param->vf_id;
3650 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3651 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3653 ret = hns3_cmd_send(hw, &desc, 1);
3655 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3661 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3663 struct hns3_promisc_param param;
3664 bool en_bc_pmc = true;
3669 * In current version VF is not supported when PF is driven by DPDK
3670 * driver, the PF-related vf_id is 0, just need to configure parameters
3675 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3676 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
3684 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3686 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3687 struct hns3_pf *pf = &hns->pf;
3688 struct hns3_promisc_param param;
3692 /* func_id 0 is denoted PF, the VFs start from 1 */
3693 for (func_id = 1; func_id < pf->func_num; func_id++) {
3694 hns3_promisc_param_init(¶m, false, false, false, func_id);
3695 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
3704 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3706 struct hns3_adapter *hns = dev->data->dev_private;
3707 struct hns3_hw *hw = &hns->hw;
3710 rte_spinlock_lock(&hw->lock);
3711 ret = hns3_set_promisc_mode(hw, true, true);
3712 rte_spinlock_unlock(&hw->lock);
3714 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
3721 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3723 bool allmulti = dev->data->all_multicast ? true : false;
3724 struct hns3_adapter *hns = dev->data->dev_private;
3725 struct hns3_hw *hw = &hns->hw;
3728 /* If now in all_multicast mode, must remain in all_multicast mode. */
3729 rte_spinlock_lock(&hw->lock);
3730 ret = hns3_set_promisc_mode(hw, false, allmulti);
3731 rte_spinlock_unlock(&hw->lock);
3733 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
3740 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3742 struct hns3_adapter *hns = dev->data->dev_private;
3743 struct hns3_hw *hw = &hns->hw;
3746 if (dev->data->promiscuous)
3749 rte_spinlock_lock(&hw->lock);
3750 ret = hns3_set_promisc_mode(hw, false, true);
3751 rte_spinlock_unlock(&hw->lock);
3753 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
3760 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3762 struct hns3_adapter *hns = dev->data->dev_private;
3763 struct hns3_hw *hw = &hns->hw;
3766 /* If now in promiscuous mode, must remain in all_multicast mode. */
3767 if (dev->data->promiscuous)
3770 rte_spinlock_lock(&hw->lock);
3771 ret = hns3_set_promisc_mode(hw, false, false);
3772 rte_spinlock_unlock(&hw->lock);
3774 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
3781 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3783 struct hns3_hw *hw = &hns->hw;
3784 bool allmulti = hw->data->all_multicast ? true : false;
3786 if (hw->data->promiscuous)
3787 return hns3_set_promisc_mode(hw, true, true);
3789 return hns3_set_promisc_mode(hw, false, allmulti);
3793 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3795 struct hns3_sfp_speed_cmd *resp;
3796 struct hns3_cmd_desc desc;
3799 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3800 resp = (struct hns3_sfp_speed_cmd *)desc.data;
3801 ret = hns3_cmd_send(hw, &desc, 1);
3802 if (ret == -EOPNOTSUPP) {
3803 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3806 hns3_err(hw, "get sfp speed failed %d", ret);
3810 *speed = resp->sfp_speed;
3816 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3818 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3819 duplex = ETH_LINK_FULL_DUPLEX;
3825 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3827 struct hns3_mac *mac = &hw->mac;
3830 duplex = hns3_check_speed_dup(duplex, speed);
3831 if (mac->link_speed == speed && mac->link_duplex == duplex)
3834 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3838 mac->link_speed = speed;
3839 mac->link_duplex = duplex;
3845 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3847 struct hns3_adapter *hns = eth_dev->data->dev_private;
3848 struct hns3_hw *hw = &hns->hw;
3849 struct hns3_pf *pf = &hns->pf;
3853 /* If IMP do not support get SFP/qSFP speed, return directly */
3854 if (!pf->support_sfp_query)
3857 ret = hns3_get_sfp_speed(hw, &speed);
3858 if (ret == -EOPNOTSUPP) {
3859 pf->support_sfp_query = false;
3864 if (speed == ETH_SPEED_NUM_NONE)
3865 return 0; /* do nothing if no SFP */
3867 /* Config full duplex for SFP */
3868 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3872 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3874 struct hns3_config_mac_mode_cmd *req;
3875 struct hns3_cmd_desc desc;
3876 uint32_t loop_en = 0;
3880 req = (struct hns3_config_mac_mode_cmd *)desc.data;
3882 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3885 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3886 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3887 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3888 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3889 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3890 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3891 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3892 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3893 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3894 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3895 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3896 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3897 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3898 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3899 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3901 ret = hns3_cmd_send(hw, &desc, 1);
3903 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3909 hns3_get_mac_link_status(struct hns3_hw *hw)
3911 struct hns3_link_status_cmd *req;
3912 struct hns3_cmd_desc desc;
3916 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3917 ret = hns3_cmd_send(hw, &desc, 1);
3919 hns3_err(hw, "get link status cmd failed %d", ret);
3920 return ETH_LINK_DOWN;
3923 req = (struct hns3_link_status_cmd *)desc.data;
3924 link_status = req->status & HNS3_LINK_STATUS_UP_M;
3926 return !!link_status;
3930 hns3_update_link_status(struct hns3_hw *hw)
3934 state = hns3_get_mac_link_status(hw);
3935 if (state != hw->mac.link_status) {
3936 hw->mac.link_status = state;
3937 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
3942 hns3_service_handler(void *param)
3944 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3945 struct hns3_adapter *hns = eth_dev->data->dev_private;
3946 struct hns3_hw *hw = &hns->hw;
3948 if (!hns3_is_reset_pending(hns)) {
3949 hns3_update_speed_duplex(eth_dev);
3950 hns3_update_link_status(hw);
3952 hns3_warn(hw, "Cancel the query when reset is pending");
3954 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3958 hns3_init_hardware(struct hns3_adapter *hns)
3960 struct hns3_hw *hw = &hns->hw;
3963 ret = hns3_map_tqp(hw);
3965 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3969 ret = hns3_init_umv_space(hw);
3971 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3975 ret = hns3_mac_init(hw);
3977 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3981 ret = hns3_init_mgr_tbl(hw);
3983 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3987 ret = hns3_set_promisc_mode(hw, false, false);
3989 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3993 ret = hns3_clear_all_vfs_promisc_mode(hw);
3995 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
4000 ret = hns3_init_vlan_config(hns);
4002 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4006 ret = hns3_dcb_init(hw);
4008 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4012 ret = hns3_init_fd_config(hns);
4014 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4018 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4020 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4024 ret = hns3_config_gro(hw, false);
4026 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4032 hns3_uninit_umv_space(hw);
4037 hns3_init_pf(struct rte_eth_dev *eth_dev)
4039 struct rte_device *dev = eth_dev->device;
4040 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4041 struct hns3_adapter *hns = eth_dev->data->dev_private;
4042 struct hns3_hw *hw = &hns->hw;
4045 PMD_INIT_FUNC_TRACE();
4047 /* Get hardware io base address from pcie BAR2 IO space */
4048 hw->io_base = pci_dev->mem_resource[2].addr;
4050 /* Firmware command queue initialize */
4051 ret = hns3_cmd_init_queue(hw);
4053 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4054 goto err_cmd_init_queue;
4057 hns3_clear_all_event_cause(hw);
4059 /* Firmware command initialize */
4060 ret = hns3_cmd_init(hw);
4062 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4066 ret = rte_intr_callback_register(&pci_dev->intr_handle,
4067 hns3_interrupt_handler,
4070 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4071 goto err_intr_callback_register;
4074 /* Enable interrupt */
4075 rte_intr_enable(&pci_dev->intr_handle);
4076 hns3_pf_enable_irq0(hw);
4078 /* Get configuration */
4079 ret = hns3_get_configuration(hw);
4081 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4082 goto err_get_config;
4085 ret = hns3_init_hardware(hns);
4087 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4088 goto err_get_config;
4091 /* Initialize flow director filter list & hash */
4092 ret = hns3_fdir_filter_init(hns);
4094 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4098 hns3_set_default_rss_args(hw);
4100 ret = hns3_enable_hw_error_intr(hns, true);
4102 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4108 * In the initialization clearing the all hardware mapping relationship
4109 * configurations between queues and interrupt vectors is needed, so
4110 * some error caused by the residual configurations, such as the
4111 * unexpected interrupt, can be avoid.
4113 ret = hns3_init_ring_with_vector(hw);
4120 hns3_fdir_filter_uninit(hns);
4122 hns3_uninit_umv_space(hw);
4125 hns3_pf_disable_irq0(hw);
4126 rte_intr_disable(&pci_dev->intr_handle);
4127 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4129 err_intr_callback_register:
4131 hns3_cmd_uninit(hw);
4132 hns3_cmd_destroy_queue(hw);
4140 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4142 struct hns3_adapter *hns = eth_dev->data->dev_private;
4143 struct rte_device *dev = eth_dev->device;
4144 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4145 struct hns3_hw *hw = &hns->hw;
4147 PMD_INIT_FUNC_TRACE();
4149 hns3_enable_hw_error_intr(hns, false);
4150 hns3_rss_uninit(hns);
4151 hns3_fdir_filter_uninit(hns);
4152 hns3_uninit_umv_space(hw);
4153 hns3_pf_disable_irq0(hw);
4154 rte_intr_disable(&pci_dev->intr_handle);
4155 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4157 hns3_cmd_uninit(hw);
4158 hns3_cmd_destroy_queue(hw);
4163 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4165 struct hns3_hw *hw = &hns->hw;
4168 ret = hns3_dcb_cfg_update(hns);
4173 ret = hns3_start_queues(hns, reset_queue);
4175 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4180 ret = hns3_cfg_mac_mode(hw, true);
4182 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4183 goto err_config_mac_mode;
4187 err_config_mac_mode:
4188 hns3_stop_queues(hns, true);
4193 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4195 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4196 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4197 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4198 uint32_t intr_vector;
4204 if (dev->data->dev_conf.intr_conf.rxq == 0)
4207 /* disable uio/vfio intr/eventfd mapping */
4208 rte_intr_disable(intr_handle);
4210 /* check and configure queue intr-vector mapping */
4211 if (rte_intr_cap_multiple(intr_handle) ||
4212 !RTE_ETH_DEV_SRIOV(dev).active) {
4213 intr_vector = hw->used_rx_queues;
4214 /* creates event fd for each intr vector when MSIX is used */
4215 if (rte_intr_efd_enable(intr_handle, intr_vector))
4218 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4219 intr_handle->intr_vec =
4220 rte_zmalloc("intr_vec",
4221 hw->used_rx_queues * sizeof(int), 0);
4222 if (intr_handle->intr_vec == NULL) {
4223 hns3_err(hw, "Failed to allocate %d rx_queues"
4224 " intr_vec", hw->used_rx_queues);
4226 goto alloc_intr_vec_error;
4230 if (rte_intr_allow_others(intr_handle)) {
4231 vec = RTE_INTR_VEC_RXTX_OFFSET;
4232 base = RTE_INTR_VEC_RXTX_OFFSET;
4234 if (rte_intr_dp_is_en(intr_handle)) {
4235 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4236 ret = hns3_bind_ring_with_vector(hw, vec, true,
4240 goto bind_vector_error;
4241 intr_handle->intr_vec[q_id] = vec;
4242 if (vec < base + intr_handle->nb_efd - 1)
4246 rte_intr_enable(intr_handle);
4250 rte_intr_efd_disable(intr_handle);
4251 if (intr_handle->intr_vec) {
4252 free(intr_handle->intr_vec);
4253 intr_handle->intr_vec = NULL;
4256 alloc_intr_vec_error:
4257 rte_intr_efd_disable(intr_handle);
4262 hns3_dev_start(struct rte_eth_dev *dev)
4264 struct hns3_adapter *hns = dev->data->dev_private;
4265 struct hns3_hw *hw = &hns->hw;
4268 PMD_INIT_FUNC_TRACE();
4269 if (rte_atomic16_read(&hw->reset.resetting))
4272 rte_spinlock_lock(&hw->lock);
4273 hw->adapter_state = HNS3_NIC_STARTING;
4275 ret = hns3_do_start(hns, true);
4277 hw->adapter_state = HNS3_NIC_CONFIGURED;
4278 rte_spinlock_unlock(&hw->lock);
4282 hw->adapter_state = HNS3_NIC_STARTED;
4283 rte_spinlock_unlock(&hw->lock);
4285 ret = hns3_map_rx_interrupt(dev);
4288 hns3_set_rxtx_function(dev);
4289 hns3_mp_req_start_rxtx(dev);
4290 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4292 hns3_info(hw, "hns3 dev start successful!");
4297 hns3_do_stop(struct hns3_adapter *hns)
4299 struct hns3_hw *hw = &hns->hw;
4303 ret = hns3_cfg_mac_mode(hw, false);
4306 hw->mac.link_status = ETH_LINK_DOWN;
4308 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4309 hns3_configure_all_mac_addr(hns, true);
4312 reset_queue = false;
4313 hw->mac.default_addr_setted = false;
4314 return hns3_stop_queues(hns, reset_queue);
4318 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4320 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4321 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4322 struct hns3_adapter *hns = dev->data->dev_private;
4323 struct hns3_hw *hw = &hns->hw;
4328 if (dev->data->dev_conf.intr_conf.rxq == 0)
4331 /* unmap the ring with vector */
4332 if (rte_intr_allow_others(intr_handle)) {
4333 vec = RTE_INTR_VEC_RXTX_OFFSET;
4334 base = RTE_INTR_VEC_RXTX_OFFSET;
4336 if (rte_intr_dp_is_en(intr_handle)) {
4337 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4338 (void)hns3_bind_ring_with_vector(hw, vec, false,
4341 if (vec < base + intr_handle->nb_efd - 1)
4345 /* Clean datapath event and queue/vec mapping */
4346 rte_intr_efd_disable(intr_handle);
4347 if (intr_handle->intr_vec) {
4348 rte_free(intr_handle->intr_vec);
4349 intr_handle->intr_vec = NULL;
4354 hns3_dev_stop(struct rte_eth_dev *dev)
4356 struct hns3_adapter *hns = dev->data->dev_private;
4357 struct hns3_hw *hw = &hns->hw;
4359 PMD_INIT_FUNC_TRACE();
4361 hw->adapter_state = HNS3_NIC_STOPPING;
4362 hns3_set_rxtx_function(dev);
4364 /* Disable datapath on secondary process. */
4365 hns3_mp_req_stop_rxtx(dev);
4366 /* Prevent crashes when queues are still in use. */
4367 rte_delay_ms(hw->tqps_num);
4369 rte_spinlock_lock(&hw->lock);
4370 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4372 hns3_dev_release_mbufs(hns);
4373 hw->adapter_state = HNS3_NIC_CONFIGURED;
4375 rte_eal_alarm_cancel(hns3_service_handler, dev);
4376 rte_spinlock_unlock(&hw->lock);
4377 hns3_unmap_rx_interrupt(dev);
4381 hns3_dev_close(struct rte_eth_dev *eth_dev)
4383 struct hns3_adapter *hns = eth_dev->data->dev_private;
4384 struct hns3_hw *hw = &hns->hw;
4386 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4387 rte_free(eth_dev->process_private);
4388 eth_dev->process_private = NULL;
4392 if (hw->adapter_state == HNS3_NIC_STARTED)
4393 hns3_dev_stop(eth_dev);
4395 hw->adapter_state = HNS3_NIC_CLOSING;
4396 hns3_reset_abort(hns);
4397 hw->adapter_state = HNS3_NIC_CLOSED;
4399 hns3_configure_all_mc_mac_addr(hns, true);
4400 hns3_remove_all_vlan_table(hns);
4401 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4402 hns3_uninit_pf(eth_dev);
4403 hns3_free_all_queues(eth_dev);
4404 rte_free(hw->reset.wait_data);
4405 rte_free(eth_dev->process_private);
4406 eth_dev->process_private = NULL;
4407 hns3_mp_uninit_primary();
4408 hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4412 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4414 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4415 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4417 fc_conf->pause_time = pf->pause_time;
4419 /* return fc current mode */
4420 switch (hw->current_mode) {
4422 fc_conf->mode = RTE_FC_FULL;
4424 case HNS3_FC_TX_PAUSE:
4425 fc_conf->mode = RTE_FC_TX_PAUSE;
4427 case HNS3_FC_RX_PAUSE:
4428 fc_conf->mode = RTE_FC_RX_PAUSE;
4432 fc_conf->mode = RTE_FC_NONE;
4440 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4444 hw->requested_mode = HNS3_FC_NONE;
4446 case RTE_FC_RX_PAUSE:
4447 hw->requested_mode = HNS3_FC_RX_PAUSE;
4449 case RTE_FC_TX_PAUSE:
4450 hw->requested_mode = HNS3_FC_TX_PAUSE;
4453 hw->requested_mode = HNS3_FC_FULL;
4456 hw->requested_mode = HNS3_FC_NONE;
4457 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4458 "configured to RTE_FC_NONE", mode);
4464 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4466 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4467 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4470 if (fc_conf->high_water || fc_conf->low_water ||
4471 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4472 hns3_err(hw, "Unsupported flow control settings specified, "
4473 "high_water(%u), low_water(%u), send_xon(%u) and "
4474 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4475 fc_conf->high_water, fc_conf->low_water,
4476 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4479 if (fc_conf->autoneg) {
4480 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4483 if (!fc_conf->pause_time) {
4484 hns3_err(hw, "Invalid pause time %d setting.",
4485 fc_conf->pause_time);
4489 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4490 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4491 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4492 "current_fc_status = %d", hw->current_fc_status);
4496 hns3_get_fc_mode(hw, fc_conf->mode);
4497 if (hw->requested_mode == hw->current_mode &&
4498 pf->pause_time == fc_conf->pause_time)
4501 rte_spinlock_lock(&hw->lock);
4502 ret = hns3_fc_enable(dev, fc_conf);
4503 rte_spinlock_unlock(&hw->lock);
4509 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4510 struct rte_eth_pfc_conf *pfc_conf)
4512 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4513 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4517 if (!hns3_dev_dcb_supported(hw)) {
4518 hns3_err(hw, "This port does not support dcb configurations.");
4522 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4523 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4524 hns3_err(hw, "Unsupported flow control settings specified, "
4525 "high_water(%u), low_water(%u), send_xon(%u) and "
4526 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4527 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4528 pfc_conf->fc.send_xon,
4529 pfc_conf->fc.mac_ctrl_frame_fwd);
4532 if (pfc_conf->fc.autoneg) {
4533 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4536 if (pfc_conf->fc.pause_time == 0) {
4537 hns3_err(hw, "Invalid pause time %d setting.",
4538 pfc_conf->fc.pause_time);
4542 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4543 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4544 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4545 "current_fc_status = %d", hw->current_fc_status);
4549 priority = pfc_conf->priority;
4550 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4551 if (hw->dcb_info.pfc_en & BIT(priority) &&
4552 hw->requested_mode == hw->current_mode &&
4553 pfc_conf->fc.pause_time == pf->pause_time)
4556 rte_spinlock_lock(&hw->lock);
4557 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4558 rte_spinlock_unlock(&hw->lock);
4564 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4566 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4567 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4568 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4571 rte_spinlock_lock(&hw->lock);
4572 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4573 dcb_info->nb_tcs = pf->local_max_tc;
4575 dcb_info->nb_tcs = 1;
4577 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4578 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4579 for (i = 0; i < dcb_info->nb_tcs; i++)
4580 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4582 for (i = 0; i < hw->num_tc; i++) {
4583 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4584 dcb_info->tc_queue.tc_txq[0][i].base =
4585 hw->tc_queue[i].tqp_offset;
4586 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4587 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4588 hw->tc_queue[i].tqp_count;
4590 rte_spinlock_unlock(&hw->lock);
4596 hns3_reinit_dev(struct hns3_adapter *hns)
4598 struct hns3_hw *hw = &hns->hw;
4601 ret = hns3_cmd_init(hw);
4603 hns3_err(hw, "Failed to init cmd: %d", ret);
4607 ret = hns3_reset_all_queues(hns);
4609 hns3_err(hw, "Failed to reset all queues: %d", ret);
4613 ret = hns3_init_hardware(hns);
4615 hns3_err(hw, "Failed to init hardware: %d", ret);
4619 ret = hns3_enable_hw_error_intr(hns, true);
4621 hns3_err(hw, "fail to enable hw error interrupts: %d",
4625 hns3_info(hw, "Reset done, driver initialization finished.");
4631 is_pf_reset_done(struct hns3_hw *hw)
4633 uint32_t val, reg, reg_bit;
4635 switch (hw->reset.level) {
4636 case HNS3_IMP_RESET:
4637 reg = HNS3_GLOBAL_RESET_REG;
4638 reg_bit = HNS3_IMP_RESET_BIT;
4640 case HNS3_GLOBAL_RESET:
4641 reg = HNS3_GLOBAL_RESET_REG;
4642 reg_bit = HNS3_GLOBAL_RESET_BIT;
4644 case HNS3_FUNC_RESET:
4645 reg = HNS3_FUN_RST_ING;
4646 reg_bit = HNS3_FUN_RST_ING_B;
4648 case HNS3_FLR_RESET:
4650 hns3_err(hw, "Wait for unsupported reset level: %d",
4654 val = hns3_read_dev(hw, reg);
4655 if (hns3_get_bit(val, reg_bit))
4662 hns3_is_reset_pending(struct hns3_adapter *hns)
4664 struct hns3_hw *hw = &hns->hw;
4665 enum hns3_reset_level reset;
4667 hns3_check_event_cause(hns, NULL);
4668 reset = hns3_get_reset_level(hns, &hw->reset.pending);
4669 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4670 hns3_warn(hw, "High level reset %d is pending", reset);
4673 reset = hns3_get_reset_level(hns, &hw->reset.request);
4674 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4675 hns3_warn(hw, "High level reset %d is request", reset);
4682 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4684 struct hns3_hw *hw = &hns->hw;
4685 struct hns3_wait_data *wait_data = hw->reset.wait_data;
4688 if (wait_data->result == HNS3_WAIT_SUCCESS)
4690 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4691 gettimeofday(&tv, NULL);
4692 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4693 tv.tv_sec, tv.tv_usec);
4695 } else if (wait_data->result == HNS3_WAIT_REQUEST)
4698 wait_data->hns = hns;
4699 wait_data->check_completion = is_pf_reset_done;
4700 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4701 HNS3_RESET_WAIT_MS + get_timeofday_ms();
4702 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4703 wait_data->count = HNS3_RESET_WAIT_CNT;
4704 wait_data->result = HNS3_WAIT_REQUEST;
4705 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4710 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4712 struct hns3_cmd_desc desc;
4713 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4715 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4716 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4717 req->fun_reset_vfid = func_id;
4719 return hns3_cmd_send(hw, &desc, 1);
4723 hns3_imp_reset_cmd(struct hns3_hw *hw)
4725 struct hns3_cmd_desc desc;
4727 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4728 desc.data[0] = 0xeedd;
4730 return hns3_cmd_send(hw, &desc, 1);
4734 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4736 struct hns3_hw *hw = &hns->hw;
4740 gettimeofday(&tv, NULL);
4741 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4742 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4743 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4744 tv.tv_sec, tv.tv_usec);
4748 switch (reset_level) {
4749 case HNS3_IMP_RESET:
4750 hns3_imp_reset_cmd(hw);
4751 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4752 tv.tv_sec, tv.tv_usec);
4754 case HNS3_GLOBAL_RESET:
4755 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4756 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4757 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4758 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4759 tv.tv_sec, tv.tv_usec);
4761 case HNS3_FUNC_RESET:
4762 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4763 tv.tv_sec, tv.tv_usec);
4764 /* schedule again to check later */
4765 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4766 hns3_schedule_reset(hns);
4769 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4772 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4775 static enum hns3_reset_level
4776 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4778 struct hns3_hw *hw = &hns->hw;
4779 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4781 /* Return the highest priority reset level amongst all */
4782 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4783 reset_level = HNS3_IMP_RESET;
4784 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4785 reset_level = HNS3_GLOBAL_RESET;
4786 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4787 reset_level = HNS3_FUNC_RESET;
4788 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4789 reset_level = HNS3_FLR_RESET;
4791 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4792 return HNS3_NONE_RESET;
4798 hns3_prepare_reset(struct hns3_adapter *hns)
4800 struct hns3_hw *hw = &hns->hw;
4804 switch (hw->reset.level) {
4805 case HNS3_FUNC_RESET:
4806 ret = hns3_func_reset_cmd(hw, 0);
4811 * After performaning pf reset, it is not necessary to do the
4812 * mailbox handling or send any command to firmware, because
4813 * any mailbox handling or command to firmware is only valid
4814 * after hns3_cmd_init is called.
4816 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4817 hw->reset.stats.request_cnt++;
4819 case HNS3_IMP_RESET:
4820 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4821 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4822 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4831 hns3_set_rst_done(struct hns3_hw *hw)
4833 struct hns3_pf_rst_done_cmd *req;
4834 struct hns3_cmd_desc desc;
4836 req = (struct hns3_pf_rst_done_cmd *)desc.data;
4837 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4838 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4839 return hns3_cmd_send(hw, &desc, 1);
4843 hns3_stop_service(struct hns3_adapter *hns)
4845 struct hns3_hw *hw = &hns->hw;
4846 struct rte_eth_dev *eth_dev;
4848 eth_dev = &rte_eth_devices[hw->data->port_id];
4849 if (hw->adapter_state == HNS3_NIC_STARTED)
4850 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4851 hw->mac.link_status = ETH_LINK_DOWN;
4853 hns3_set_rxtx_function(eth_dev);
4855 /* Disable datapath on secondary process. */
4856 hns3_mp_req_stop_rxtx(eth_dev);
4857 rte_delay_ms(hw->tqps_num);
4859 rte_spinlock_lock(&hw->lock);
4860 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4861 hw->adapter_state == HNS3_NIC_STOPPING) {
4863 hw->reset.mbuf_deferred_free = true;
4865 hw->reset.mbuf_deferred_free = false;
4868 * It is cumbersome for hardware to pick-and-choose entries for deletion
4869 * from table space. Hence, for function reset software intervention is
4870 * required to delete the entries
4872 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
4873 hns3_configure_all_mc_mac_addr(hns, true);
4874 rte_spinlock_unlock(&hw->lock);
4880 hns3_start_service(struct hns3_adapter *hns)
4882 struct hns3_hw *hw = &hns->hw;
4883 struct rte_eth_dev *eth_dev;
4885 if (hw->reset.level == HNS3_IMP_RESET ||
4886 hw->reset.level == HNS3_GLOBAL_RESET)
4887 hns3_set_rst_done(hw);
4888 eth_dev = &rte_eth_devices[hw->data->port_id];
4889 hns3_set_rxtx_function(eth_dev);
4890 hns3_mp_req_start_rxtx(eth_dev);
4891 if (hw->adapter_state == HNS3_NIC_STARTED)
4892 hns3_service_handler(eth_dev);
4898 hns3_restore_conf(struct hns3_adapter *hns)
4900 struct hns3_hw *hw = &hns->hw;
4903 ret = hns3_configure_all_mac_addr(hns, false);
4907 ret = hns3_configure_all_mc_mac_addr(hns, false);
4911 ret = hns3_dev_promisc_restore(hns);
4915 ret = hns3_restore_vlan_table(hns);
4919 ret = hns3_restore_vlan_conf(hns);
4923 ret = hns3_restore_all_fdir_filter(hns);
4927 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
4928 ret = hns3_do_start(hns, false);
4931 hns3_info(hw, "hns3 dev restart successful!");
4932 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
4933 hw->adapter_state = HNS3_NIC_CONFIGURED;
4937 hns3_configure_all_mc_mac_addr(hns, true);
4939 hns3_configure_all_mac_addr(hns, true);
4944 hns3_reset_service(void *param)
4946 struct hns3_adapter *hns = (struct hns3_adapter *)param;
4947 struct hns3_hw *hw = &hns->hw;
4948 enum hns3_reset_level reset_level;
4949 struct timeval tv_delta;
4950 struct timeval tv_start;
4956 * The interrupt is not triggered within the delay time.
4957 * The interrupt may have been lost. It is necessary to handle
4958 * the interrupt to recover from the error.
4960 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
4961 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
4962 hns3_err(hw, "Handling interrupts in delayed tasks");
4963 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
4964 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4965 if (reset_level == HNS3_NONE_RESET) {
4966 hns3_err(hw, "No reset level is set, try IMP reset");
4967 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
4970 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
4973 * Check if there is any ongoing reset in the hardware. This status can
4974 * be checked from reset_pending. If there is then, we need to wait for
4975 * hardware to complete reset.
4976 * a. If we are able to figure out in reasonable time that hardware
4977 * has fully resetted then, we can proceed with driver, client
4979 * b. else, we can come back later to check this status so re-sched
4982 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4983 if (reset_level != HNS3_NONE_RESET) {
4984 gettimeofday(&tv_start, NULL);
4985 ret = hns3_reset_process(hns, reset_level);
4986 gettimeofday(&tv, NULL);
4987 timersub(&tv, &tv_start, &tv_delta);
4988 msec = tv_delta.tv_sec * MSEC_PER_SEC +
4989 tv_delta.tv_usec / USEC_PER_MSEC;
4990 if (msec > HNS3_RESET_PROCESS_MS)
4991 hns3_err(hw, "%d handle long time delta %" PRIx64
4992 " ms time=%ld.%.6ld",
4993 hw->reset.level, msec,
4994 tv.tv_sec, tv.tv_usec);
4999 /* Check if we got any *new* reset requests to be honored */
5000 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5001 if (reset_level != HNS3_NONE_RESET)
5002 hns3_msix_process(hns, reset_level);
5005 static const struct eth_dev_ops hns3_eth_dev_ops = {
5006 .dev_start = hns3_dev_start,
5007 .dev_stop = hns3_dev_stop,
5008 .dev_close = hns3_dev_close,
5009 .promiscuous_enable = hns3_dev_promiscuous_enable,
5010 .promiscuous_disable = hns3_dev_promiscuous_disable,
5011 .allmulticast_enable = hns3_dev_allmulticast_enable,
5012 .allmulticast_disable = hns3_dev_allmulticast_disable,
5013 .mtu_set = hns3_dev_mtu_set,
5014 .stats_get = hns3_stats_get,
5015 .stats_reset = hns3_stats_reset,
5016 .xstats_get = hns3_dev_xstats_get,
5017 .xstats_get_names = hns3_dev_xstats_get_names,
5018 .xstats_reset = hns3_dev_xstats_reset,
5019 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
5020 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5021 .dev_infos_get = hns3_dev_infos_get,
5022 .fw_version_get = hns3_fw_version_get,
5023 .rx_queue_setup = hns3_rx_queue_setup,
5024 .tx_queue_setup = hns3_tx_queue_setup,
5025 .rx_queue_release = hns3_dev_rx_queue_release,
5026 .tx_queue_release = hns3_dev_tx_queue_release,
5027 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
5028 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
5029 .dev_configure = hns3_dev_configure,
5030 .flow_ctrl_get = hns3_flow_ctrl_get,
5031 .flow_ctrl_set = hns3_flow_ctrl_set,
5032 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5033 .mac_addr_add = hns3_add_mac_addr,
5034 .mac_addr_remove = hns3_remove_mac_addr,
5035 .mac_addr_set = hns3_set_default_mac_addr,
5036 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
5037 .link_update = hns3_dev_link_update,
5038 .rss_hash_update = hns3_dev_rss_hash_update,
5039 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
5040 .reta_update = hns3_dev_rss_reta_update,
5041 .reta_query = hns3_dev_rss_reta_query,
5042 .filter_ctrl = hns3_dev_filter_ctrl,
5043 .vlan_filter_set = hns3_vlan_filter_set,
5044 .vlan_tpid_set = hns3_vlan_tpid_set,
5045 .vlan_offload_set = hns3_vlan_offload_set,
5046 .vlan_pvid_set = hns3_vlan_pvid_set,
5047 .get_reg = hns3_get_regs,
5048 .get_dcb_info = hns3_get_dcb_info,
5049 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5052 static const struct hns3_reset_ops hns3_reset_ops = {
5053 .reset_service = hns3_reset_service,
5054 .stop_service = hns3_stop_service,
5055 .prepare_reset = hns3_prepare_reset,
5056 .wait_hardware_ready = hns3_wait_hardware_ready,
5057 .reinit_dev = hns3_reinit_dev,
5058 .restore_conf = hns3_restore_conf,
5059 .start_service = hns3_start_service,
5063 hns3_dev_init(struct rte_eth_dev *eth_dev)
5065 struct rte_device *dev = eth_dev->device;
5066 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5067 struct hns3_adapter *hns = eth_dev->data->dev_private;
5068 struct hns3_hw *hw = &hns->hw;
5069 uint16_t device_id = pci_dev->id.device_id;
5072 PMD_INIT_FUNC_TRACE();
5073 eth_dev->process_private = (struct hns3_process_private *)
5074 rte_zmalloc_socket("hns3_filter_list",
5075 sizeof(struct hns3_process_private),
5076 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5077 if (eth_dev->process_private == NULL) {
5078 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5081 /* initialize flow filter lists */
5082 hns3_filterlist_init(eth_dev);
5084 hns3_set_rxtx_function(eth_dev);
5085 eth_dev->dev_ops = &hns3_eth_dev_ops;
5086 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5087 hns3_mp_init_secondary();
5088 hw->secondary_cnt++;
5092 hns3_mp_init_primary();
5093 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5095 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5096 device_id == HNS3_DEV_ID_50GE_RDMA ||
5097 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5098 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5101 hw->data = eth_dev->data;
5104 * Set default max packet size according to the mtu
5105 * default vale in DPDK frame.
5107 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5109 ret = hns3_reset_init(hw);
5111 goto err_init_reset;
5112 hw->reset.ops = &hns3_reset_ops;
5114 ret = hns3_init_pf(eth_dev);
5116 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5120 /* Allocate memory for storing MAC addresses */
5121 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5122 sizeof(struct rte_ether_addr) *
5123 HNS3_UC_MACADDR_NUM, 0);
5124 if (eth_dev->data->mac_addrs == NULL) {
5125 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5126 "to store MAC addresses",
5127 sizeof(struct rte_ether_addr) *
5128 HNS3_UC_MACADDR_NUM);
5130 goto err_rte_zmalloc;
5133 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5134 ð_dev->data->mac_addrs[0]);
5136 hw->adapter_state = HNS3_NIC_INITIALIZED;
5138 * Pass the information to the rte_eth_dev_close() that it should also
5139 * release the private port resources.
5141 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5143 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5144 hns3_err(hw, "Reschedule reset service after dev_init");
5145 hns3_schedule_reset(hns);
5147 /* IMP will wait ready flag before reset */
5148 hns3_notify_reset_ready(hw, false);
5151 hns3_info(hw, "hns3 dev initialization successful!");
5155 hns3_uninit_pf(eth_dev);
5158 rte_free(hw->reset.wait_data);
5160 eth_dev->dev_ops = NULL;
5161 eth_dev->rx_pkt_burst = NULL;
5162 eth_dev->tx_pkt_burst = NULL;
5163 eth_dev->tx_pkt_prepare = NULL;
5164 rte_free(eth_dev->process_private);
5165 eth_dev->process_private = NULL;
5170 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5172 struct hns3_adapter *hns = eth_dev->data->dev_private;
5173 struct hns3_hw *hw = &hns->hw;
5175 PMD_INIT_FUNC_TRACE();
5177 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5180 eth_dev->dev_ops = NULL;
5181 eth_dev->rx_pkt_burst = NULL;
5182 eth_dev->tx_pkt_burst = NULL;
5183 eth_dev->tx_pkt_prepare = NULL;
5184 if (hw->adapter_state < HNS3_NIC_CLOSING)
5185 hns3_dev_close(eth_dev);
5187 hw->adapter_state = HNS3_NIC_REMOVED;
5192 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5193 struct rte_pci_device *pci_dev)
5195 return rte_eth_dev_pci_generic_probe(pci_dev,
5196 sizeof(struct hns3_adapter),
5201 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5203 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5206 static const struct rte_pci_id pci_id_hns3_map[] = {
5207 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5208 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5209 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5210 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5211 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5212 { .vendor_id = 0, /* sentinel */ },
5215 static struct rte_pci_driver rte_hns3_pmd = {
5216 .id_table = pci_id_hns3_map,
5217 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5218 .probe = eth_hns3_pci_probe,
5219 .remove = eth_hns3_pci_remove,
5222 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5223 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5224 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5226 RTE_INIT(hns3_init_log)
5228 hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5229 if (hns3_logtype_init >= 0)
5230 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5231 hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5232 if (hns3_logtype_driver >= 0)
5233 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);