1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
12 #include <rte_atomic.h>
13 #include <rte_bus_pci.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_interrupts.h>
26 #include "hns3_ethdev.h"
27 #include "hns3_logs.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_intr.h"
30 #include "hns3_regs.h"
34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
37 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
38 #define HNS3_INVALID_PVID 0xFFFF
40 #define HNS3_FILTER_TYPE_VF 0
41 #define HNS3_FILTER_TYPE_PORT 1
42 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
43 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
44 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
45 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
46 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
47 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
48 | HNS3_FILTER_FE_ROCE_EGRESS_B)
49 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
50 | HNS3_FILTER_FE_ROCE_INGRESS_B)
52 /* Reset related Registers */
53 #define HNS3_GLOBAL_RESET_BIT 0
54 #define HNS3_CORE_RESET_BIT 1
55 #define HNS3_IMP_RESET_BIT 2
56 #define HNS3_FUN_RST_ING_B 0
58 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
59 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
60 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U
61 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
63 #define HNS3_RESET_WAIT_MS 100
64 #define HNS3_RESET_WAIT_CNT 200
67 HNS3_VECTOR0_EVENT_RST,
68 HNS3_VECTOR0_EVENT_MBX,
69 HNS3_VECTOR0_EVENT_ERR,
70 HNS3_VECTOR0_EVENT_OTHER,
73 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
75 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
76 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
78 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
80 static int hns3_add_mc_addr(struct hns3_hw *hw,
81 struct rte_ether_addr *mac_addr);
82 static int hns3_remove_mc_addr(struct hns3_hw *hw,
83 struct rte_ether_addr *mac_addr);
86 hns3_pf_disable_irq0(struct hns3_hw *hw)
88 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
92 hns3_pf_enable_irq0(struct hns3_hw *hw)
94 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
97 static enum hns3_evt_cause
98 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
100 struct hns3_hw *hw = &hns->hw;
101 uint32_t vector0_int_stats;
102 uint32_t cmdq_src_val;
103 uint32_t hw_err_src_reg;
105 enum hns3_evt_cause ret;
107 /* fetch the events from their corresponding regs */
108 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
109 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
110 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
113 * Assumption: If by any chance reset and mailbox events are reported
114 * together then we will only process reset event and defer the
115 * processing of the mailbox events. Since, we would have not cleared
116 * RX CMDQ event this time we would receive again another interrupt
117 * from H/W just for the mailbox.
119 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
120 rte_atomic16_set(&hw->reset.disable_cmd, 1);
121 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
122 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
124 hw->reset.stats.imp_cnt++;
125 hns3_warn(hw, "IMP reset detected, clear reset status");
127 hns3_schedule_delayed_reset(hns);
128 hns3_warn(hw, "IMP reset detected, don't clear reset status");
131 ret = HNS3_VECTOR0_EVENT_RST;
136 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
137 rte_atomic16_set(&hw->reset.disable_cmd, 1);
138 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
139 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
141 hw->reset.stats.global_cnt++;
142 hns3_warn(hw, "Global reset detected, clear reset status");
144 hns3_schedule_delayed_reset(hns);
145 hns3_warn(hw, "Global reset detected, don't clear reset status");
148 ret = HNS3_VECTOR0_EVENT_RST;
152 /* check for vector0 msix event source */
153 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
154 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
155 val = vector0_int_stats | hw_err_src_reg;
156 ret = HNS3_VECTOR0_EVENT_ERR;
160 /* check for vector0 mailbox(=CMDQ RX) event source */
161 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
162 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
164 ret = HNS3_VECTOR0_EVENT_MBX;
168 if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
169 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
170 vector0_int_stats, cmdq_src_val, hw_err_src_reg);
171 val = vector0_int_stats;
172 ret = HNS3_VECTOR0_EVENT_OTHER;
181 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
183 if (event_type == HNS3_VECTOR0_EVENT_RST)
184 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
185 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
186 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
190 hns3_clear_all_event_cause(struct hns3_hw *hw)
192 uint32_t vector0_int_stats;
193 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
195 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
196 hns3_warn(hw, "Probe during IMP reset interrupt");
198 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
199 hns3_warn(hw, "Probe during Global reset interrupt");
201 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
202 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
203 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
204 BIT(HNS3_VECTOR0_CORERESET_INT_B));
205 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
209 hns3_interrupt_handler(void *param)
211 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
212 struct hns3_adapter *hns = dev->data->dev_private;
213 struct hns3_hw *hw = &hns->hw;
214 enum hns3_evt_cause event_cause;
215 uint32_t clearval = 0;
217 /* Disable interrupt */
218 hns3_pf_disable_irq0(hw);
220 event_cause = hns3_check_event_cause(hns, &clearval);
222 /* vector 0 interrupt is shared with reset and mailbox source events. */
223 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
224 hns3_warn(hw, "Received err interrupt");
225 hns3_handle_msix_error(hns, &hw->reset.request);
226 hns3_handle_ras_error(hns, &hw->reset.request);
227 hns3_schedule_reset(hns);
228 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
229 hns3_warn(hw, "Received reset interrupt");
230 hns3_schedule_reset(hns);
231 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
232 hns3_dev_handle_mbx_msg(hw);
234 hns3_err(hw, "Received unknown event");
236 hns3_clear_event_cause(hw, event_cause, clearval);
237 /* Enable interrupt if it is not cause by reset */
238 hns3_pf_enable_irq0(hw);
242 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
244 #define HNS3_VLAN_ID_OFFSET_STEP 160
245 #define HNS3_VLAN_BYTE_SIZE 8
246 struct hns3_vlan_filter_pf_cfg_cmd *req;
247 struct hns3_hw *hw = &hns->hw;
248 uint8_t vlan_offset_byte_val;
249 struct hns3_cmd_desc desc;
250 uint8_t vlan_offset_byte;
251 uint8_t vlan_offset_base;
254 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
256 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
257 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
259 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
261 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
262 req->vlan_offset = vlan_offset_base;
263 req->vlan_cfg = on ? 0 : 1;
264 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
266 ret = hns3_cmd_send(hw, &desc, 1);
268 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
275 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
277 struct hns3_user_vlan_table *vlan_entry;
278 struct hns3_pf *pf = &hns->pf;
280 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
281 if (vlan_entry->vlan_id == vlan_id) {
282 if (vlan_entry->hd_tbl_status)
283 hns3_set_port_vlan_filter(hns, vlan_id, 0);
284 LIST_REMOVE(vlan_entry, next);
285 rte_free(vlan_entry);
292 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
295 struct hns3_user_vlan_table *vlan_entry;
296 struct hns3_hw *hw = &hns->hw;
297 struct hns3_pf *pf = &hns->pf;
299 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
300 if (vlan_entry->vlan_id == vlan_id)
304 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
305 if (vlan_entry == NULL) {
306 hns3_err(hw, "Failed to malloc hns3 vlan table");
310 vlan_entry->hd_tbl_status = writen_to_tbl;
311 vlan_entry->vlan_id = vlan_id;
313 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
317 hns3_restore_vlan_table(struct hns3_adapter *hns)
319 struct hns3_user_vlan_table *vlan_entry;
320 struct hns3_hw *hw = &hns->hw;
321 struct hns3_pf *pf = &hns->pf;
325 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
326 return hns3_vlan_pvid_configure(hns,
327 hw->port_base_vlan_cfg.pvid, 1);
329 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
330 if (vlan_entry->hd_tbl_status) {
331 vlan_id = vlan_entry->vlan_id;
332 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
342 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
344 struct hns3_hw *hw = &hns->hw;
345 bool writen_to_tbl = false;
349 * When vlan filter is enabled, hardware regards packets without vlan
350 * as packets with vlan 0. So, to receive packets without vlan, vlan id
351 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
353 if (on == 0 && vlan_id == 0)
357 * When port base vlan enabled, we use port base vlan as the vlan
358 * filter condition. In this case, we don't update vlan filter table
359 * when user add new vlan or remove exist vlan, just update the
360 * vlan list. The vlan id in vlan list will be writen in vlan filter
361 * table until port base vlan disabled
363 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
364 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
365 writen_to_tbl = true;
370 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
372 hns3_rm_dev_vlan_table(hns, vlan_id);
378 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
380 struct hns3_adapter *hns = dev->data->dev_private;
381 struct hns3_hw *hw = &hns->hw;
384 rte_spinlock_lock(&hw->lock);
385 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
386 rte_spinlock_unlock(&hw->lock);
391 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
394 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
395 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
396 struct hns3_hw *hw = &hns->hw;
397 struct hns3_cmd_desc desc;
400 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
401 vlan_type != ETH_VLAN_TYPE_OUTER)) {
402 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
406 if (tpid != RTE_ETHER_TYPE_VLAN) {
407 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
411 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
412 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
414 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
415 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
416 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
417 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
418 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
419 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
420 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
421 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
424 ret = hns3_cmd_send(hw, &desc, 1);
426 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
431 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
433 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
434 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
435 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
437 ret = hns3_cmd_send(hw, &desc, 1);
439 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
445 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
448 struct hns3_adapter *hns = dev->data->dev_private;
449 struct hns3_hw *hw = &hns->hw;
452 rte_spinlock_lock(&hw->lock);
453 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
454 rte_spinlock_unlock(&hw->lock);
459 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
460 struct hns3_rx_vtag_cfg *vcfg)
462 struct hns3_vport_vtag_rx_cfg_cmd *req;
463 struct hns3_hw *hw = &hns->hw;
464 struct hns3_cmd_desc desc;
469 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
471 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
472 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
473 vcfg->strip_tag1_en ? 1 : 0);
474 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
475 vcfg->strip_tag2_en ? 1 : 0);
476 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
477 vcfg->vlan1_vlan_prionly ? 1 : 0);
478 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
479 vcfg->vlan2_vlan_prionly ? 1 : 0);
481 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
482 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
483 vcfg->strip_tag1_discard_en ? 1 : 0);
484 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
485 vcfg->strip_tag2_discard_en ? 1 : 0);
487 * In current version VF is not supported when PF is driven by DPDK
488 * driver, just need to configure parameters for PF vport.
490 vport_id = HNS3_PF_FUNC_ID;
491 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
492 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
493 req->vf_bitmap[req->vf_offset] = bitmap;
495 ret = hns3_cmd_send(hw, &desc, 1);
497 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
502 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
503 struct hns3_rx_vtag_cfg *vcfg)
505 struct hns3_pf *pf = &hns->pf;
506 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
510 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
511 struct hns3_tx_vtag_cfg *vcfg)
513 struct hns3_pf *pf = &hns->pf;
514 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
518 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
520 struct hns3_rx_vtag_cfg rxvlan_cfg;
521 struct hns3_hw *hw = &hns->hw;
524 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
525 rxvlan_cfg.strip_tag1_en = false;
526 rxvlan_cfg.strip_tag2_en = enable;
527 rxvlan_cfg.strip_tag2_discard_en = false;
529 rxvlan_cfg.strip_tag1_en = enable;
530 rxvlan_cfg.strip_tag2_en = true;
531 rxvlan_cfg.strip_tag2_discard_en = true;
534 rxvlan_cfg.strip_tag1_discard_en = false;
535 rxvlan_cfg.vlan1_vlan_prionly = false;
536 rxvlan_cfg.vlan2_vlan_prionly = false;
537 rxvlan_cfg.rx_vlan_offload_en = enable;
539 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
541 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
545 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
551 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
552 uint8_t fe_type, bool filter_en, uint8_t vf_id)
554 struct hns3_vlan_filter_ctrl_cmd *req;
555 struct hns3_cmd_desc desc;
558 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
560 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
561 req->vlan_type = vlan_type;
562 req->vlan_fe = filter_en ? fe_type : 0;
565 ret = hns3_cmd_send(hw, &desc, 1);
567 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
573 hns3_vlan_filter_init(struct hns3_adapter *hns)
575 struct hns3_hw *hw = &hns->hw;
578 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
579 HNS3_FILTER_FE_EGRESS, false,
582 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
586 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
587 HNS3_FILTER_FE_INGRESS, false,
590 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
596 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
598 struct hns3_hw *hw = &hns->hw;
601 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
602 HNS3_FILTER_FE_INGRESS, enable,
605 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
606 enable ? "enable" : "disable", ret);
612 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
614 struct hns3_adapter *hns = dev->data->dev_private;
615 struct hns3_hw *hw = &hns->hw;
616 struct rte_eth_rxmode *rxmode;
617 unsigned int tmp_mask;
621 rte_spinlock_lock(&hw->lock);
622 rxmode = &dev->data->dev_conf.rxmode;
623 tmp_mask = (unsigned int)mask;
624 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
625 /* ignore vlan filter configuration during promiscuous mode */
626 if (!dev->data->promiscuous) {
627 /* Enable or disable VLAN filter */
628 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
631 ret = hns3_enable_vlan_filter(hns, enable);
633 rte_spinlock_unlock(&hw->lock);
634 hns3_err(hw, "failed to %s rx filter, ret = %d",
635 enable ? "enable" : "disable", ret);
641 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
642 /* Enable or disable VLAN stripping */
643 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
646 ret = hns3_en_hw_strip_rxvtag(hns, enable);
648 rte_spinlock_unlock(&hw->lock);
649 hns3_err(hw, "failed to %s rx strip, ret = %d",
650 enable ? "enable" : "disable", ret);
655 rte_spinlock_unlock(&hw->lock);
661 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
662 struct hns3_tx_vtag_cfg *vcfg)
664 struct hns3_vport_vtag_tx_cfg_cmd *req;
665 struct hns3_cmd_desc desc;
666 struct hns3_hw *hw = &hns->hw;
671 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
673 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
674 req->def_vlan_tag1 = vcfg->default_tag1;
675 req->def_vlan_tag2 = vcfg->default_tag2;
676 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
677 vcfg->accept_tag1 ? 1 : 0);
678 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
679 vcfg->accept_untag1 ? 1 : 0);
680 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
681 vcfg->accept_tag2 ? 1 : 0);
682 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
683 vcfg->accept_untag2 ? 1 : 0);
684 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
685 vcfg->insert_tag1_en ? 1 : 0);
686 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
687 vcfg->insert_tag2_en ? 1 : 0);
688 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
690 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
691 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
692 vcfg->tag_shift_mode_en ? 1 : 0);
695 * In current version VF is not supported when PF is driven by DPDK
696 * driver, just need to configure parameters for PF vport.
698 vport_id = HNS3_PF_FUNC_ID;
699 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
700 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
701 req->vf_bitmap[req->vf_offset] = bitmap;
703 ret = hns3_cmd_send(hw, &desc, 1);
705 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
711 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
714 struct hns3_hw *hw = &hns->hw;
715 struct hns3_tx_vtag_cfg txvlan_cfg;
718 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
719 txvlan_cfg.accept_tag1 = true;
720 txvlan_cfg.insert_tag1_en = false;
721 txvlan_cfg.default_tag1 = 0;
723 txvlan_cfg.accept_tag1 =
724 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
725 txvlan_cfg.insert_tag1_en = true;
726 txvlan_cfg.default_tag1 = pvid;
729 txvlan_cfg.accept_untag1 = true;
730 txvlan_cfg.accept_tag2 = true;
731 txvlan_cfg.accept_untag2 = true;
732 txvlan_cfg.insert_tag2_en = false;
733 txvlan_cfg.default_tag2 = 0;
734 txvlan_cfg.tag_shift_mode_en = true;
736 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
738 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
743 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
749 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
751 struct hns3_user_vlan_table *vlan_entry;
752 struct hns3_pf *pf = &hns->pf;
754 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
755 if (vlan_entry->hd_tbl_status) {
756 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
757 vlan_entry->hd_tbl_status = false;
762 vlan_entry = LIST_FIRST(&pf->vlan_list);
764 LIST_REMOVE(vlan_entry, next);
765 rte_free(vlan_entry);
766 vlan_entry = LIST_FIRST(&pf->vlan_list);
772 hns3_add_all_vlan_table(struct hns3_adapter *hns)
774 struct hns3_user_vlan_table *vlan_entry;
775 struct hns3_pf *pf = &hns->pf;
777 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
778 if (!vlan_entry->hd_tbl_status) {
779 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
780 vlan_entry->hd_tbl_status = true;
786 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
788 struct hns3_hw *hw = &hns->hw;
791 hns3_rm_all_vlan_table(hns, true);
792 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
793 ret = hns3_set_port_vlan_filter(hns,
794 hw->port_base_vlan_cfg.pvid, 0);
796 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
804 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
805 uint16_t port_base_vlan_state, uint16_t new_pvid)
807 struct hns3_hw *hw = &hns->hw;
811 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
812 old_pvid = hw->port_base_vlan_cfg.pvid;
813 if (old_pvid != HNS3_INVALID_PVID) {
814 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
816 hns3_err(hw, "failed to remove old pvid %u, "
817 "ret = %d", old_pvid, ret);
822 hns3_rm_all_vlan_table(hns, false);
823 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
825 hns3_err(hw, "failed to add new pvid %u, ret = %d",
830 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
832 hns3_err(hw, "failed to remove pvid %u, ret = %d",
837 hns3_add_all_vlan_table(hns);
843 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
845 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
846 struct hns3_rx_vtag_cfg rx_vlan_cfg;
850 rx_strip_en = old_cfg->rx_vlan_offload_en;
852 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
853 rx_vlan_cfg.strip_tag2_en = true;
854 rx_vlan_cfg.strip_tag2_discard_en = true;
856 rx_vlan_cfg.strip_tag1_en = false;
857 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
858 rx_vlan_cfg.strip_tag2_discard_en = false;
860 rx_vlan_cfg.strip_tag1_discard_en = false;
861 rx_vlan_cfg.vlan1_vlan_prionly = false;
862 rx_vlan_cfg.vlan2_vlan_prionly = false;
863 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
865 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
869 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
874 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
876 struct hns3_hw *hw = &hns->hw;
877 uint16_t port_base_vlan_state;
880 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
881 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
882 hns3_warn(hw, "Invalid operation! As current pvid set "
883 "is %u, disable pvid %u is invalid",
884 hw->port_base_vlan_cfg.pvid, pvid);
888 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
889 HNS3_PORT_BASE_VLAN_DISABLE;
890 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
892 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
897 ret = hns3_en_pvid_strip(hns, on);
899 hns3_err(hw, "failed to config rx vlan strip for pvid, "
904 if (pvid == HNS3_INVALID_PVID)
906 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
908 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
914 hw->port_base_vlan_cfg.state = port_base_vlan_state;
915 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
920 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
922 struct hns3_adapter *hns = dev->data->dev_private;
923 struct hns3_hw *hw = &hns->hw;
924 bool pvid_en_state_change;
928 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
929 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
930 RTE_ETHER_MAX_VLAN_ID);
935 * If PVID configuration state change, should refresh the PVID
936 * configuration state in struct hns3_tx_queue/hns3_rx_queue.
938 pvid_state = hw->port_base_vlan_cfg.state;
939 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
940 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
941 pvid_en_state_change = false;
943 pvid_en_state_change = true;
945 rte_spinlock_lock(&hw->lock);
946 ret = hns3_vlan_pvid_configure(hns, pvid, on);
947 rte_spinlock_unlock(&hw->lock);
951 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
952 * need be processed by PMD driver.
954 if (pvid_en_state_change &&
955 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
956 hns3_update_all_queues_pvid_proc_en(hw);
962 hns3_default_vlan_config(struct hns3_adapter *hns)
964 struct hns3_hw *hw = &hns->hw;
968 * When vlan filter is enabled, hardware regards packets without vlan
969 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
970 * table, packets without vlan won't be received. So, add vlan 0 as
973 ret = hns3_vlan_filter_configure(hns, 0, 1);
975 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
980 hns3_init_vlan_config(struct hns3_adapter *hns)
982 struct hns3_hw *hw = &hns->hw;
986 * This function can be called in the initialization and reset process,
987 * when in reset process, it means that hardware had been reseted
988 * successfully and we need to restore the hardware configuration to
989 * ensure that the hardware configuration remains unchanged before and
992 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
993 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
994 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
997 ret = hns3_vlan_filter_init(hns);
999 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1003 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1004 RTE_ETHER_TYPE_VLAN);
1006 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1011 * When in the reinit dev stage of the reset process, the following
1012 * vlan-related configurations may differ from those at initialization,
1013 * we will restore configurations to hardware in hns3_restore_vlan_table
1014 * and hns3_restore_vlan_conf later.
1016 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1017 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1019 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1023 ret = hns3_en_hw_strip_rxvtag(hns, false);
1025 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1031 return hns3_default_vlan_config(hns);
1035 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1037 struct hns3_pf *pf = &hns->pf;
1038 struct hns3_hw *hw = &hns->hw;
1043 if (!hw->data->promiscuous) {
1044 /* restore vlan filter states */
1045 offloads = hw->data->dev_conf.rxmode.offloads;
1046 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1047 ret = hns3_enable_vlan_filter(hns, enable);
1049 hns3_err(hw, "failed to restore vlan rx filter conf, "
1055 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1057 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1061 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1063 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1069 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1071 struct hns3_adapter *hns = dev->data->dev_private;
1072 struct rte_eth_dev_data *data = dev->data;
1073 struct rte_eth_txmode *txmode;
1074 struct hns3_hw *hw = &hns->hw;
1078 txmode = &data->dev_conf.txmode;
1079 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1081 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1082 "configuration is not supported! Ignore these two "
1083 "parameters: hw_vlan_reject_tagged(%d), "
1084 "hw_vlan_reject_untagged(%d)",
1085 txmode->hw_vlan_reject_tagged,
1086 txmode->hw_vlan_reject_untagged);
1088 /* Apply vlan offload setting */
1089 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1090 ret = hns3_vlan_offload_set(dev, mask);
1092 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1098 * If pvid config is not set in rte_eth_conf, driver needn't to set
1099 * VLAN pvid related configuration to hardware.
1101 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1104 /* Apply pvid setting */
1105 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1106 txmode->hw_vlan_insert_pvid);
1108 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1115 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1116 unsigned int tso_mss_max)
1118 struct hns3_cfg_tso_status_cmd *req;
1119 struct hns3_cmd_desc desc;
1122 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1124 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1127 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1129 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1132 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1134 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1136 return hns3_cmd_send(hw, &desc, 1);
1140 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1141 uint16_t *allocated_size, bool is_alloc)
1143 struct hns3_umv_spc_alc_cmd *req;
1144 struct hns3_cmd_desc desc;
1147 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1148 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1149 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1150 req->space_size = rte_cpu_to_le_32(space_size);
1152 ret = hns3_cmd_send(hw, &desc, 1);
1154 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1155 is_alloc ? "allocate" : "free", ret);
1159 if (is_alloc && allocated_size)
1160 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1166 hns3_init_umv_space(struct hns3_hw *hw)
1168 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1169 struct hns3_pf *pf = &hns->pf;
1170 uint16_t allocated_size = 0;
1173 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1178 if (allocated_size < pf->wanted_umv_size)
1179 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1180 pf->wanted_umv_size, allocated_size);
1182 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1183 pf->wanted_umv_size;
1184 pf->used_umv_size = 0;
1189 hns3_uninit_umv_space(struct hns3_hw *hw)
1191 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1192 struct hns3_pf *pf = &hns->pf;
1195 if (pf->max_umv_size == 0)
1198 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1202 pf->max_umv_size = 0;
1208 hns3_is_umv_space_full(struct hns3_hw *hw)
1210 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1211 struct hns3_pf *pf = &hns->pf;
1214 is_full = (pf->used_umv_size >= pf->max_umv_size);
1220 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1222 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1223 struct hns3_pf *pf = &hns->pf;
1226 if (pf->used_umv_size > 0)
1227 pf->used_umv_size--;
1229 pf->used_umv_size++;
1233 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1234 const uint8_t *addr, bool is_mc)
1236 const unsigned char *mac_addr = addr;
1237 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1238 ((uint32_t)mac_addr[2] << 16) |
1239 ((uint32_t)mac_addr[1] << 8) |
1240 (uint32_t)mac_addr[0];
1241 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1243 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1245 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1246 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1247 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1250 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1251 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1255 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1257 enum hns3_mac_vlan_tbl_opcode op)
1260 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1265 if (op == HNS3_MAC_VLAN_ADD) {
1266 if (resp_code == 0 || resp_code == 1) {
1268 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1269 hns3_err(hw, "add mac addr failed for uc_overflow");
1271 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1272 hns3_err(hw, "add mac addr failed for mc_overflow");
1276 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1279 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1280 if (resp_code == 0) {
1282 } else if (resp_code == 1) {
1283 hns3_dbg(hw, "remove mac addr failed for miss");
1287 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1290 } else if (op == HNS3_MAC_VLAN_LKUP) {
1291 if (resp_code == 0) {
1293 } else if (resp_code == 1) {
1294 hns3_dbg(hw, "lookup mac addr failed for miss");
1298 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1303 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1310 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1311 struct hns3_mac_vlan_tbl_entry_cmd *req,
1312 struct hns3_cmd_desc *desc, bool is_mc)
1318 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1320 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1321 memcpy(desc[0].data, req,
1322 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1323 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1325 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1326 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1328 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1330 memcpy(desc[0].data, req,
1331 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1332 ret = hns3_cmd_send(hw, desc, 1);
1335 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1339 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1340 retval = rte_le_to_cpu_16(desc[0].retval);
1342 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1343 HNS3_MAC_VLAN_LKUP);
1347 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1348 struct hns3_mac_vlan_tbl_entry_cmd *req,
1349 struct hns3_cmd_desc *mc_desc)
1356 if (mc_desc == NULL) {
1357 struct hns3_cmd_desc desc;
1359 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1360 memcpy(desc.data, req,
1361 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1362 ret = hns3_cmd_send(hw, &desc, 1);
1363 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1364 retval = rte_le_to_cpu_16(desc.retval);
1366 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1369 hns3_cmd_reuse_desc(&mc_desc[0], false);
1370 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1371 hns3_cmd_reuse_desc(&mc_desc[1], false);
1372 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1373 hns3_cmd_reuse_desc(&mc_desc[2], false);
1374 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1375 memcpy(mc_desc[0].data, req,
1376 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1377 mc_desc[0].retval = 0;
1378 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1379 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1380 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1382 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1387 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1395 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1396 struct hns3_mac_vlan_tbl_entry_cmd *req)
1398 struct hns3_cmd_desc desc;
1403 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1405 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1407 ret = hns3_cmd_send(hw, &desc, 1);
1409 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1412 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1413 retval = rte_le_to_cpu_16(desc.retval);
1415 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1416 HNS3_MAC_VLAN_REMOVE);
1420 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1422 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1423 struct hns3_mac_vlan_tbl_entry_cmd req;
1424 struct hns3_pf *pf = &hns->pf;
1425 struct hns3_cmd_desc desc[3];
1426 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1427 uint16_t egress_port = 0;
1431 /* check if mac addr is valid */
1432 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1433 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1435 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1440 memset(&req, 0, sizeof(req));
1443 * In current version VF is not supported when PF is driven by DPDK
1444 * driver, just need to configure parameters for PF vport.
1446 vf_id = HNS3_PF_FUNC_ID;
1447 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1448 HNS3_MAC_EPORT_VFID_S, vf_id);
1450 req.egress_port = rte_cpu_to_le_16(egress_port);
1452 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1455 * Lookup the mac address in the mac_vlan table, and add
1456 * it if the entry is inexistent. Repeated unicast entry
1457 * is not allowed in the mac vlan table.
1459 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1460 if (ret == -ENOENT) {
1461 if (!hns3_is_umv_space_full(hw)) {
1462 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1464 hns3_update_umv_space(hw, false);
1468 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1473 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1475 /* check if we just hit the duplicate */
1477 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1481 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1488 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1490 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1491 struct rte_ether_addr *addr;
1495 for (i = 0; i < hw->mc_addrs_num; i++) {
1496 addr = &hw->mc_addrs[i];
1497 /* Check if there are duplicate addresses */
1498 if (rte_is_same_ether_addr(addr, mac_addr)) {
1499 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1501 hns3_err(hw, "failed to add mc mac addr, same addrs"
1502 "(%s) is added by the set_mc_mac_addr_list "
1508 ret = hns3_add_mc_addr(hw, mac_addr);
1510 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1512 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1519 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1521 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1524 ret = hns3_remove_mc_addr(hw, mac_addr);
1526 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1528 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1535 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1536 uint32_t idx, __rte_unused uint32_t pool)
1538 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1539 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1542 rte_spinlock_lock(&hw->lock);
1545 * In hns3 network engine adding UC and MC mac address with different
1546 * commands with firmware. We need to determine whether the input
1547 * address is a UC or a MC address to call different commands.
1548 * By the way, it is recommended calling the API function named
1549 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1550 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1551 * may affect the specifications of UC mac addresses.
1553 if (rte_is_multicast_ether_addr(mac_addr))
1554 ret = hns3_add_mc_addr_common(hw, mac_addr);
1556 ret = hns3_add_uc_addr_common(hw, mac_addr);
1559 rte_spinlock_unlock(&hw->lock);
1560 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1562 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1568 hw->mac.default_addr_setted = true;
1569 rte_spinlock_unlock(&hw->lock);
1575 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1577 struct hns3_mac_vlan_tbl_entry_cmd req;
1578 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1581 /* check if mac addr is valid */
1582 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1583 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1585 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1590 memset(&req, 0, sizeof(req));
1591 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1592 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1593 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1594 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1597 hns3_update_umv_space(hw, true);
1603 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1605 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606 /* index will be checked by upper level rte interface */
1607 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1608 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1611 rte_spinlock_lock(&hw->lock);
1613 if (rte_is_multicast_ether_addr(mac_addr))
1614 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1616 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1617 rte_spinlock_unlock(&hw->lock);
1619 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1621 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1627 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1628 struct rte_ether_addr *mac_addr)
1630 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631 struct rte_ether_addr *oaddr;
1632 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1633 bool default_addr_setted;
1634 bool rm_succes = false;
1638 * It has been guaranteed that input parameter named mac_addr is valid
1639 * address in the rte layer of DPDK framework.
1641 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1642 default_addr_setted = hw->mac.default_addr_setted;
1643 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1646 rte_spinlock_lock(&hw->lock);
1647 if (default_addr_setted) {
1648 ret = hns3_remove_uc_addr_common(hw, oaddr);
1650 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1652 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1659 ret = hns3_add_uc_addr_common(hw, mac_addr);
1661 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1663 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1664 goto err_add_uc_addr;
1667 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1669 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1670 goto err_pause_addr_cfg;
1673 rte_ether_addr_copy(mac_addr,
1674 (struct rte_ether_addr *)hw->mac.mac_addr);
1675 hw->mac.default_addr_setted = true;
1676 rte_spinlock_unlock(&hw->lock);
1681 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1683 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1686 "Failed to roll back to del setted mac addr(%s): %d",
1692 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1694 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1697 "Failed to restore old uc mac addr(%s): %d",
1699 hw->mac.default_addr_setted = false;
1702 rte_spinlock_unlock(&hw->lock);
1708 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1710 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1711 struct hns3_hw *hw = &hns->hw;
1712 struct rte_ether_addr *addr;
1717 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1718 addr = &hw->data->mac_addrs[i];
1719 if (rte_is_zero_ether_addr(addr))
1721 if (rte_is_multicast_ether_addr(addr))
1722 ret = del ? hns3_remove_mc_addr(hw, addr) :
1723 hns3_add_mc_addr(hw, addr);
1725 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1726 hns3_add_uc_addr_common(hw, addr);
1730 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1732 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1733 "ret = %d.", del ? "remove" : "restore",
1741 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1743 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1747 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1748 word_num = vfid / 32;
1749 bit_num = vfid % 32;
1751 desc[1].data[word_num] &=
1752 rte_cpu_to_le_32(~(1UL << bit_num));
1754 desc[1].data[word_num] |=
1755 rte_cpu_to_le_32(1UL << bit_num);
1757 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1758 bit_num = vfid % 32;
1760 desc[2].data[word_num] &=
1761 rte_cpu_to_le_32(~(1UL << bit_num));
1763 desc[2].data[word_num] |=
1764 rte_cpu_to_le_32(1UL << bit_num);
1769 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1771 struct hns3_mac_vlan_tbl_entry_cmd req;
1772 struct hns3_cmd_desc desc[3];
1773 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1777 /* Check if mac addr is valid */
1778 if (!rte_is_multicast_ether_addr(mac_addr)) {
1779 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1781 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1786 memset(&req, 0, sizeof(req));
1787 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1788 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1789 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1791 /* This mac addr do not exist, add new entry for it */
1792 memset(desc[0].data, 0, sizeof(desc[0].data));
1793 memset(desc[1].data, 0, sizeof(desc[0].data));
1794 memset(desc[2].data, 0, sizeof(desc[0].data));
1798 * In current version VF is not supported when PF is driven by DPDK
1799 * driver, just need to configure parameters for PF vport.
1801 vf_id = HNS3_PF_FUNC_ID;
1802 hns3_update_desc_vfid(desc, vf_id, false);
1803 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1806 hns3_err(hw, "mc mac vlan table is full");
1807 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1809 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1816 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1818 struct hns3_mac_vlan_tbl_entry_cmd req;
1819 struct hns3_cmd_desc desc[3];
1820 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1824 /* Check if mac addr is valid */
1825 if (!rte_is_multicast_ether_addr(mac_addr)) {
1826 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1828 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1833 memset(&req, 0, sizeof(req));
1834 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1835 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1836 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1839 * This mac addr exist, remove this handle's VFID for it.
1840 * In current version VF is not supported when PF is driven by
1841 * DPDK driver, just need to configure parameters for PF vport.
1843 vf_id = HNS3_PF_FUNC_ID;
1844 hns3_update_desc_vfid(desc, vf_id, true);
1846 /* All the vfid is zero, so need to delete this entry */
1847 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1848 } else if (ret == -ENOENT) {
1849 /* This mac addr doesn't exist. */
1854 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1856 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1863 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1864 struct rte_ether_addr *mc_addr_set,
1865 uint32_t nb_mc_addr)
1867 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1868 struct rte_ether_addr *addr;
1872 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1873 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1874 "invalid. valid range: 0~%d",
1875 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1879 /* Check if input mac addresses are valid */
1880 for (i = 0; i < nb_mc_addr; i++) {
1881 addr = &mc_addr_set[i];
1882 if (!rte_is_multicast_ether_addr(addr)) {
1883 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1886 "failed to set mc mac addr, addr(%s) invalid.",
1891 /* Check if there are duplicate addresses */
1892 for (j = i + 1; j < nb_mc_addr; j++) {
1893 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1894 rte_ether_format_addr(mac_str,
1895 RTE_ETHER_ADDR_FMT_SIZE,
1897 hns3_err(hw, "failed to set mc mac addr, "
1898 "addrs invalid. two same addrs(%s).",
1905 * Check if there are duplicate addresses between mac_addrs
1908 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1909 if (rte_is_same_ether_addr(addr,
1910 &hw->data->mac_addrs[j])) {
1911 rte_ether_format_addr(mac_str,
1912 RTE_ETHER_ADDR_FMT_SIZE,
1914 hns3_err(hw, "failed to set mc mac addr, "
1915 "addrs invalid. addrs(%s) has already "
1916 "configured in mac_addr add API",
1927 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1928 struct rte_ether_addr *mc_addr_set,
1930 struct rte_ether_addr *reserved_addr_list,
1931 int *reserved_addr_num,
1932 struct rte_ether_addr *add_addr_list,
1934 struct rte_ether_addr *rm_addr_list,
1937 struct rte_ether_addr *addr;
1938 int current_addr_num;
1939 int reserved_num = 0;
1947 /* Calculate the mc mac address list that should be removed */
1948 current_addr_num = hw->mc_addrs_num;
1949 for (i = 0; i < current_addr_num; i++) {
1950 addr = &hw->mc_addrs[i];
1952 for (j = 0; j < mc_addr_num; j++) {
1953 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1960 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1963 rte_ether_addr_copy(addr,
1964 &reserved_addr_list[reserved_num]);
1969 /* Calculate the mc mac address list that should be added */
1970 for (i = 0; i < mc_addr_num; i++) {
1971 addr = &mc_addr_set[i];
1973 for (j = 0; j < current_addr_num; j++) {
1974 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1981 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1986 /* Reorder the mc mac address list maintained by driver */
1987 for (i = 0; i < reserved_num; i++)
1988 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1990 for (i = 0; i < rm_num; i++) {
1991 num = reserved_num + i;
1992 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1995 *reserved_addr_num = reserved_num;
1996 *add_addr_num = add_num;
1997 *rm_addr_num = rm_num;
2001 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2002 struct rte_ether_addr *mc_addr_set,
2003 uint32_t nb_mc_addr)
2005 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2007 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2008 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2009 struct rte_ether_addr *addr;
2010 int reserved_addr_num;
2018 /* Check if input parameters are valid */
2019 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2023 rte_spinlock_lock(&hw->lock);
2026 * Calculate the mc mac address lists those should be removed and be
2027 * added, Reorder the mc mac address list maintained by driver.
2029 mc_addr_num = (int)nb_mc_addr;
2030 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2031 reserved_addr_list, &reserved_addr_num,
2032 add_addr_list, &add_addr_num,
2033 rm_addr_list, &rm_addr_num);
2035 /* Remove mc mac addresses */
2036 for (i = 0; i < rm_addr_num; i++) {
2037 num = rm_addr_num - i - 1;
2038 addr = &rm_addr_list[num];
2039 ret = hns3_remove_mc_addr(hw, addr);
2041 rte_spinlock_unlock(&hw->lock);
2047 /* Add mc mac addresses */
2048 for (i = 0; i < add_addr_num; i++) {
2049 addr = &add_addr_list[i];
2050 ret = hns3_add_mc_addr(hw, addr);
2052 rte_spinlock_unlock(&hw->lock);
2056 num = reserved_addr_num + i;
2057 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2060 rte_spinlock_unlock(&hw->lock);
2066 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2068 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2069 struct hns3_hw *hw = &hns->hw;
2070 struct rte_ether_addr *addr;
2075 for (i = 0; i < hw->mc_addrs_num; i++) {
2076 addr = &hw->mc_addrs[i];
2077 if (!rte_is_multicast_ether_addr(addr))
2080 ret = hns3_remove_mc_addr(hw, addr);
2082 ret = hns3_add_mc_addr(hw, addr);
2085 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2087 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2088 del ? "Remove" : "Restore", mac_str, ret);
2095 hns3_check_mq_mode(struct rte_eth_dev *dev)
2097 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2098 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2099 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2101 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2102 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2107 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2108 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2110 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2111 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2112 "rx_mq_mode = %d", rx_mq_mode);
2116 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2117 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2118 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2119 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2120 rx_mq_mode, tx_mq_mode);
2124 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2125 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2126 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2127 dcb_rx_conf->nb_tcs, pf->tc_max);
2131 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2132 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2133 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2134 "nb_tcs(%d) != %d or %d in rx direction.",
2135 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2139 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2140 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2141 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2145 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2146 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2147 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2148 "is not equal to one in tx direction.",
2149 i, dcb_rx_conf->dcb_tc[i]);
2152 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2153 max_tc = dcb_rx_conf->dcb_tc[i];
2156 num_tc = max_tc + 1;
2157 if (num_tc > dcb_rx_conf->nb_tcs) {
2158 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2159 num_tc, dcb_rx_conf->nb_tcs);
2168 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2170 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2172 if (!hns3_dev_dcb_supported(hw)) {
2173 hns3_err(hw, "this port does not support dcb configurations.");
2177 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2178 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2182 /* Check multiple queue mode */
2183 return hns3_check_mq_mode(dev);
2187 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2188 enum hns3_ring_type queue_type, uint16_t queue_id)
2190 struct hns3_cmd_desc desc;
2191 struct hns3_ctrl_vector_chain_cmd *req =
2192 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2193 enum hns3_cmd_status status;
2194 enum hns3_opcode_type op;
2195 uint16_t tqp_type_and_id = 0;
2200 op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2201 hns3_cmd_setup_basic_desc(&desc, op, false);
2202 req->int_vector_id = vector_id;
2204 if (queue_type == HNS3_RING_TYPE_RX)
2205 gl = HNS3_RING_GL_RX;
2207 gl = HNS3_RING_GL_TX;
2211 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2213 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2214 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2216 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2217 req->int_cause_num = 1;
2218 op_str = mmap ? "Map" : "Unmap";
2219 status = hns3_cmd_send(hw, &desc, 1);
2221 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2222 op_str, queue_id, req->int_vector_id, status);
2230 hns3_init_ring_with_vector(struct hns3_hw *hw)
2237 * In hns3 network engine, vector 0 is always the misc interrupt of this
2238 * function, vector 1~N can be used respectively for the queues of the
2239 * function. Tx and Rx queues with the same number share the interrupt
2240 * vector. In the initialization clearing the all hardware mapping
2241 * relationship configurations between queues and interrupt vectors is
2242 * needed, so some error caused by the residual configurations, such as
2243 * the unexpected Tx interrupt, can be avoid.
2245 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2246 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2247 vec = vec - 1; /* the last interrupt is reserved */
2248 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2249 for (i = 0; i < hw->intr_tqps_num; i++) {
2251 * Set gap limiter/rate limiter/quanity limiter algorithm
2252 * configuration for interrupt coalesce of queue's interrupt.
2254 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2255 HNS3_TQP_INTR_GL_DEFAULT);
2256 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2257 HNS3_TQP_INTR_GL_DEFAULT);
2258 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2259 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2261 ret = hns3_bind_ring_with_vector(hw, vec, false,
2262 HNS3_RING_TYPE_TX, i);
2264 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2265 "vector: %d, ret=%d", i, vec, ret);
2269 ret = hns3_bind_ring_with_vector(hw, vec, false,
2270 HNS3_RING_TYPE_RX, i);
2272 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2273 "vector: %d, ret=%d", i, vec, ret);
2282 hns3_dev_configure(struct rte_eth_dev *dev)
2284 struct hns3_adapter *hns = dev->data->dev_private;
2285 struct rte_eth_conf *conf = &dev->data->dev_conf;
2286 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2287 struct hns3_hw *hw = &hns->hw;
2288 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2289 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2290 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2291 struct rte_eth_rss_conf rss_conf;
2297 * Hardware does not support individually enable/disable/reset the Tx or
2298 * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2299 * and Rx queues at the same time. When the numbers of Tx queues
2300 * allocated by upper applications are not equal to the numbers of Rx
2301 * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2302 * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2303 * these fake queues are imperceptible, and can not be used by upper
2306 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2308 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2312 hw->adapter_state = HNS3_NIC_CONFIGURING;
2313 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2314 hns3_err(hw, "setting link speed/duplex not supported");
2319 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2320 ret = hns3_check_dcb_cfg(dev);
2325 /* When RSS is not configured, redirect the packet queue 0 */
2326 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2327 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2328 rss_conf = conf->rx_adv_conf.rss_conf;
2329 hw->rss_dis_flag = false;
2330 if (rss_conf.rss_key == NULL) {
2331 rss_conf.rss_key = rss_cfg->key;
2332 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2335 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2341 * If jumbo frames are enabled, MTU needs to be refreshed
2342 * according to the maximum RX packet length.
2344 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2346 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2347 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2348 * can safely assign to "uint16_t" type variable.
2350 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2351 ret = hns3_dev_mtu_set(dev, mtu);
2354 dev->data->mtu = mtu;
2357 ret = hns3_dev_configure_vlan(dev);
2361 /* config hardware GRO */
2362 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2363 ret = hns3_config_gro(hw, gro_en);
2367 hns->rx_simple_allowed = true;
2368 hns->rx_vec_allowed = true;
2369 hns->tx_simple_allowed = true;
2370 hns->tx_vec_allowed = true;
2372 hns3_init_rx_ptype_tble(dev);
2373 hw->adapter_state = HNS3_NIC_CONFIGURED;
2378 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2379 hw->adapter_state = HNS3_NIC_INITIALIZED;
2385 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2387 struct hns3_config_max_frm_size_cmd *req;
2388 struct hns3_cmd_desc desc;
2390 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2392 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2393 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2394 req->min_frm_size = RTE_ETHER_MIN_LEN;
2396 return hns3_cmd_send(hw, &desc, 1);
2400 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2404 ret = hns3_set_mac_mtu(hw, mps);
2406 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2410 ret = hns3_buffer_alloc(hw);
2412 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2418 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2420 struct hns3_adapter *hns = dev->data->dev_private;
2421 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2422 struct hns3_hw *hw = &hns->hw;
2423 bool is_jumbo_frame;
2426 if (dev->data->dev_started) {
2427 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2428 "before configuration", dev->data->port_id);
2432 rte_spinlock_lock(&hw->lock);
2433 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2434 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2437 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2438 * assign to "uint16_t" type variable.
2440 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2442 rte_spinlock_unlock(&hw->lock);
2443 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2444 dev->data->port_id, mtu, ret);
2447 hns->pf.mps = (uint16_t)frame_size;
2449 dev->data->dev_conf.rxmode.offloads |=
2450 DEV_RX_OFFLOAD_JUMBO_FRAME;
2452 dev->data->dev_conf.rxmode.offloads &=
2453 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2454 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2455 rte_spinlock_unlock(&hw->lock);
2461 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2463 struct hns3_adapter *hns = eth_dev->data->dev_private;
2464 struct hns3_hw *hw = &hns->hw;
2465 uint16_t queue_num = hw->tqps_num;
2468 * In interrupt mode, 'max_rx_queues' is set based on the number of
2469 * MSI-X interrupt resources of the hardware.
2471 if (hw->data->dev_conf.intr_conf.rxq == 1)
2472 queue_num = hw->intr_tqps_num;
2474 info->max_rx_queues = queue_num;
2475 info->max_tx_queues = hw->tqps_num;
2476 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2477 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2478 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2479 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2480 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2481 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2482 DEV_RX_OFFLOAD_TCP_CKSUM |
2483 DEV_RX_OFFLOAD_UDP_CKSUM |
2484 DEV_RX_OFFLOAD_SCTP_CKSUM |
2485 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2486 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2487 DEV_RX_OFFLOAD_KEEP_CRC |
2488 DEV_RX_OFFLOAD_SCATTER |
2489 DEV_RX_OFFLOAD_VLAN_STRIP |
2490 DEV_RX_OFFLOAD_VLAN_FILTER |
2491 DEV_RX_OFFLOAD_JUMBO_FRAME |
2492 DEV_RX_OFFLOAD_RSS_HASH |
2493 DEV_RX_OFFLOAD_TCP_LRO);
2494 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2495 DEV_TX_OFFLOAD_IPV4_CKSUM |
2496 DEV_TX_OFFLOAD_TCP_CKSUM |
2497 DEV_TX_OFFLOAD_UDP_CKSUM |
2498 DEV_TX_OFFLOAD_SCTP_CKSUM |
2499 DEV_TX_OFFLOAD_MULTI_SEGS |
2500 DEV_TX_OFFLOAD_TCP_TSO |
2501 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2502 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2503 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2504 DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2505 hns3_txvlan_cap_get(hw));
2507 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2508 .nb_max = HNS3_MAX_RING_DESC,
2509 .nb_min = HNS3_MIN_RING_DESC,
2510 .nb_align = HNS3_ALIGN_RING_DESC,
2513 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2514 .nb_max = HNS3_MAX_RING_DESC,
2515 .nb_min = HNS3_MIN_RING_DESC,
2516 .nb_align = HNS3_ALIGN_RING_DESC,
2517 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2518 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2521 info->default_rxconf = (struct rte_eth_rxconf) {
2522 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2524 * If there are no available Rx buffer descriptors, incoming
2525 * packets are always dropped by hardware based on hns3 network
2531 info->default_txconf = (struct rte_eth_txconf) {
2532 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2536 info->vmdq_queue_num = 0;
2538 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2539 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2540 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2542 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2543 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2544 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2545 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2546 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2547 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2553 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2556 struct hns3_adapter *hns = eth_dev->data->dev_private;
2557 struct hns3_hw *hw = &hns->hw;
2558 uint32_t version = hw->fw_version;
2561 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2562 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2563 HNS3_FW_VERSION_BYTE3_S),
2564 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2565 HNS3_FW_VERSION_BYTE2_S),
2566 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2567 HNS3_FW_VERSION_BYTE1_S),
2568 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2569 HNS3_FW_VERSION_BYTE0_S));
2570 ret += 1; /* add the size of '\0' */
2571 if (fw_size < (uint32_t)ret)
2578 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2579 __rte_unused int wait_to_complete)
2581 struct hns3_adapter *hns = eth_dev->data->dev_private;
2582 struct hns3_hw *hw = &hns->hw;
2583 struct hns3_mac *mac = &hw->mac;
2584 struct rte_eth_link new_link;
2586 if (!hns3_is_reset_pending(hns)) {
2587 hns3_update_speed_duplex(eth_dev);
2588 hns3_update_link_status(hw);
2591 memset(&new_link, 0, sizeof(new_link));
2592 switch (mac->link_speed) {
2593 case ETH_SPEED_NUM_10M:
2594 case ETH_SPEED_NUM_100M:
2595 case ETH_SPEED_NUM_1G:
2596 case ETH_SPEED_NUM_10G:
2597 case ETH_SPEED_NUM_25G:
2598 case ETH_SPEED_NUM_40G:
2599 case ETH_SPEED_NUM_50G:
2600 case ETH_SPEED_NUM_100G:
2601 case ETH_SPEED_NUM_200G:
2602 new_link.link_speed = mac->link_speed;
2605 new_link.link_speed = ETH_SPEED_NUM_100M;
2609 new_link.link_duplex = mac->link_duplex;
2610 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2611 new_link.link_autoneg =
2612 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2614 return rte_eth_linkstatus_set(eth_dev, &new_link);
2618 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2620 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2621 struct hns3_pf *pf = &hns->pf;
2623 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2626 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2632 hns3_query_function_status(struct hns3_hw *hw)
2634 #define HNS3_QUERY_MAX_CNT 10
2635 #define HNS3_QUERY_SLEEP_MSCOEND 1
2636 struct hns3_func_status_cmd *req;
2637 struct hns3_cmd_desc desc;
2641 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2642 req = (struct hns3_func_status_cmd *)desc.data;
2645 ret = hns3_cmd_send(hw, &desc, 1);
2647 PMD_INIT_LOG(ERR, "query function status failed %d",
2652 /* Check pf reset is done */
2656 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2657 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2659 return hns3_parse_func_status(hw, req);
2663 hns3_query_pf_resource(struct hns3_hw *hw)
2665 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2666 struct hns3_pf *pf = &hns->pf;
2667 struct hns3_pf_res_cmd *req;
2668 struct hns3_cmd_desc desc;
2671 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2672 ret = hns3_cmd_send(hw, &desc, 1);
2674 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2678 req = (struct hns3_pf_res_cmd *)desc.data;
2679 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2680 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2681 hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2682 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2684 if (req->tx_buf_size)
2686 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2688 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2690 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2692 if (req->dv_buf_size)
2694 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2696 pf->dv_buf_size = HNS3_DEFAULT_DV;
2698 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2701 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2702 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2708 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2710 struct hns3_cfg_param_cmd *req;
2711 uint64_t mac_addr_tmp_high;
2712 uint64_t mac_addr_tmp;
2715 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2717 /* get the configuration */
2718 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2719 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2720 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2721 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2722 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2723 HNS3_CFG_TQP_DESC_N_M,
2724 HNS3_CFG_TQP_DESC_N_S);
2726 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2727 HNS3_CFG_PHY_ADDR_M,
2728 HNS3_CFG_PHY_ADDR_S);
2729 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2730 HNS3_CFG_MEDIA_TP_M,
2731 HNS3_CFG_MEDIA_TP_S);
2732 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2733 HNS3_CFG_RX_BUF_LEN_M,
2734 HNS3_CFG_RX_BUF_LEN_S);
2735 /* get mac address */
2736 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2737 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2738 HNS3_CFG_MAC_ADDR_H_M,
2739 HNS3_CFG_MAC_ADDR_H_S);
2741 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2743 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2744 HNS3_CFG_DEFAULT_SPEED_M,
2745 HNS3_CFG_DEFAULT_SPEED_S);
2746 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2747 HNS3_CFG_RSS_SIZE_M,
2748 HNS3_CFG_RSS_SIZE_S);
2750 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2751 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2753 req = (struct hns3_cfg_param_cmd *)desc[1].data;
2754 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2756 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2757 HNS3_CFG_SPEED_ABILITY_M,
2758 HNS3_CFG_SPEED_ABILITY_S);
2759 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2760 HNS3_CFG_UMV_TBL_SPACE_M,
2761 HNS3_CFG_UMV_TBL_SPACE_S);
2762 if (!cfg->umv_space)
2763 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2766 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2767 * @hw: pointer to struct hns3_hw
2768 * @hcfg: the config structure to be getted
2771 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2773 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2774 struct hns3_cfg_param_cmd *req;
2779 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2781 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2782 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2784 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2785 i * HNS3_CFG_RD_LEN_BYTES);
2786 /* Len should be divided by 4 when send to hardware */
2787 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2788 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2789 req->offset = rte_cpu_to_le_32(offset);
2792 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2794 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2798 hns3_parse_cfg(hcfg, desc);
2804 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2806 switch (speed_cmd) {
2807 case HNS3_CFG_SPEED_10M:
2808 *speed = ETH_SPEED_NUM_10M;
2810 case HNS3_CFG_SPEED_100M:
2811 *speed = ETH_SPEED_NUM_100M;
2813 case HNS3_CFG_SPEED_1G:
2814 *speed = ETH_SPEED_NUM_1G;
2816 case HNS3_CFG_SPEED_10G:
2817 *speed = ETH_SPEED_NUM_10G;
2819 case HNS3_CFG_SPEED_25G:
2820 *speed = ETH_SPEED_NUM_25G;
2822 case HNS3_CFG_SPEED_40G:
2823 *speed = ETH_SPEED_NUM_40G;
2825 case HNS3_CFG_SPEED_50G:
2826 *speed = ETH_SPEED_NUM_50G;
2828 case HNS3_CFG_SPEED_100G:
2829 *speed = ETH_SPEED_NUM_100G;
2831 case HNS3_CFG_SPEED_200G:
2832 *speed = ETH_SPEED_NUM_200G;
2842 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2844 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2845 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2846 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2847 hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2851 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2853 struct hns3_dev_specs_0_cmd *req0;
2855 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2857 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2858 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2859 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2860 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2864 hns3_query_dev_specifications(struct hns3_hw *hw)
2866 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2870 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2871 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2873 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2875 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2877 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2881 hns3_parse_dev_specifications(hw, desc);
2887 hns3_get_capability(struct hns3_hw *hw)
2889 struct rte_pci_device *pci_dev;
2890 struct rte_eth_dev *eth_dev;
2895 eth_dev = &rte_eth_devices[hw->data->port_id];
2896 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2897 device_id = pci_dev->id.device_id;
2899 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
2900 device_id == HNS3_DEV_ID_50GE_RDMA ||
2901 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
2902 device_id == HNS3_DEV_ID_200G_RDMA)
2903 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
2905 /* Get PCI revision id */
2906 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
2907 HNS3_PCI_REVISION_ID);
2908 if (ret != HNS3_PCI_REVISION_ID_LEN) {
2909 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
2913 hw->revision = revision;
2915 if (revision < PCI_REVISION_ID_HIP09_A) {
2916 hns3_set_default_dev_specifications(hw);
2917 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
2918 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
2919 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
2920 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
2921 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
2922 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
2926 ret = hns3_query_dev_specifications(hw);
2929 "failed to query dev specifications, ret = %d",
2934 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
2935 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
2936 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
2937 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
2938 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
2939 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
2945 hns3_get_board_configuration(struct hns3_hw *hw)
2947 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2948 struct hns3_pf *pf = &hns->pf;
2949 struct hns3_cfg cfg;
2952 ret = hns3_get_board_cfg(hw, &cfg);
2954 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2958 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
2959 !hns3_dev_copper_supported(hw)) {
2960 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2964 hw->mac.media_type = cfg.media_type;
2965 hw->rss_size_max = cfg.rss_size_max;
2966 hw->rss_dis_flag = false;
2967 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2968 hw->mac.phy_addr = cfg.phy_addr;
2969 hw->mac.default_addr_setted = false;
2970 hw->num_tx_desc = cfg.tqp_desc_num;
2971 hw->num_rx_desc = cfg.tqp_desc_num;
2972 hw->dcb_info.num_pg = 1;
2973 hw->dcb_info.hw_pfc_map = 0;
2975 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2977 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2978 cfg.default_speed, ret);
2982 pf->tc_max = cfg.tc_num;
2983 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2984 PMD_INIT_LOG(WARNING,
2985 "Get TC num(%u) from flash, set TC num to 1",
2990 /* Dev does not support DCB */
2991 if (!hns3_dev_dcb_supported(hw)) {
2995 pf->pfc_max = pf->tc_max;
2997 hw->dcb_info.num_tc = 1;
2998 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2999 hw->tqps_num / hw->dcb_info.num_tc);
3000 hns3_set_bit(hw->hw_tc_map, 0, 1);
3001 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3003 pf->wanted_umv_size = cfg.umv_space;
3009 hns3_get_configuration(struct hns3_hw *hw)
3013 ret = hns3_query_function_status(hw);
3015 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3019 /* Get device capability */
3020 ret = hns3_get_capability(hw);
3022 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3026 /* Get pf resource */
3027 ret = hns3_query_pf_resource(hw);
3029 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3033 ret = hns3_get_board_configuration(hw);
3035 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
3041 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3042 uint16_t tqp_vid, bool is_pf)
3044 struct hns3_tqp_map_cmd *req;
3045 struct hns3_cmd_desc desc;
3048 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3050 req = (struct hns3_tqp_map_cmd *)desc.data;
3051 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3052 req->tqp_vf = func_id;
3053 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3055 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3056 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3058 ret = hns3_cmd_send(hw, &desc, 1);
3060 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3066 hns3_map_tqp(struct hns3_hw *hw)
3068 uint16_t tqps_num = hw->total_tqps_num;
3077 * In current version VF is not supported when PF is driven by DPDK
3078 * driver, so we allocate tqps to PF as much as possible.
3081 num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
3082 for (func_id = HNS3_PF_FUNC_ID; func_id < num; func_id++) {
3083 is_pf = func_id == HNS3_PF_FUNC_ID ? true : false;
3085 i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
3086 ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
3097 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3099 struct hns3_config_mac_speed_dup_cmd *req;
3100 struct hns3_cmd_desc desc;
3103 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3105 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3107 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3110 case ETH_SPEED_NUM_10M:
3111 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3112 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3114 case ETH_SPEED_NUM_100M:
3115 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3116 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3118 case ETH_SPEED_NUM_1G:
3119 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3120 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3122 case ETH_SPEED_NUM_10G:
3123 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3124 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3126 case ETH_SPEED_NUM_25G:
3127 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3128 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3130 case ETH_SPEED_NUM_40G:
3131 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3132 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3134 case ETH_SPEED_NUM_50G:
3135 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3136 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3138 case ETH_SPEED_NUM_100G:
3139 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3140 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3142 case ETH_SPEED_NUM_200G:
3143 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3144 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3147 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3151 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3153 ret = hns3_cmd_send(hw, &desc, 1);
3155 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3161 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3163 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3164 struct hns3_pf *pf = &hns->pf;
3165 struct hns3_priv_buf *priv;
3166 uint32_t i, total_size;
3168 total_size = pf->pkt_buf_size;
3170 /* alloc tx buffer for all enabled tc */
3171 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3172 priv = &buf_alloc->priv_buf[i];
3174 if (hw->hw_tc_map & BIT(i)) {
3175 if (total_size < pf->tx_buf_size)
3178 priv->tx_buf_size = pf->tx_buf_size;
3180 priv->tx_buf_size = 0;
3182 total_size -= priv->tx_buf_size;
3189 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3191 /* TX buffer size is unit by 128 byte */
3192 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3193 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3194 struct hns3_tx_buff_alloc_cmd *req;
3195 struct hns3_cmd_desc desc;
3200 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3202 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3203 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3204 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3206 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3207 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3208 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3211 ret = hns3_cmd_send(hw, &desc, 1);
3213 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3219 hns3_get_tc_num(struct hns3_hw *hw)
3224 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3225 if (hw->hw_tc_map & BIT(i))
3231 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3233 struct hns3_priv_buf *priv;
3234 uint32_t rx_priv = 0;
3237 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3238 priv = &buf_alloc->priv_buf[i];
3240 rx_priv += priv->buf_size;
3246 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3248 uint32_t total_tx_size = 0;
3251 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3252 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3254 return total_tx_size;
3257 /* Get the number of pfc enabled TCs, which have private buffer */
3259 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3261 struct hns3_priv_buf *priv;
3265 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3266 priv = &buf_alloc->priv_buf[i];
3267 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3274 /* Get the number of pfc disabled TCs, which have private buffer */
3276 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3277 struct hns3_pkt_buf_alloc *buf_alloc)
3279 struct hns3_priv_buf *priv;
3283 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3284 priv = &buf_alloc->priv_buf[i];
3285 if (hw->hw_tc_map & BIT(i) &&
3286 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3294 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3297 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3298 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3299 struct hns3_pf *pf = &hns->pf;
3300 uint32_t shared_buf, aligned_mps;
3305 tc_num = hns3_get_tc_num(hw);
3306 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3308 if (hns3_dev_dcb_supported(hw))
3309 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3312 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3315 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3316 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3317 HNS3_BUF_SIZE_UNIT);
3319 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3320 if (rx_all < rx_priv + shared_std)
3323 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3324 buf_alloc->s_buf.buf_size = shared_buf;
3325 if (hns3_dev_dcb_supported(hw)) {
3326 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3327 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3328 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3329 HNS3_BUF_SIZE_UNIT);
3331 buf_alloc->s_buf.self.high =
3332 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3333 buf_alloc->s_buf.self.low = aligned_mps;
3336 if (hns3_dev_dcb_supported(hw)) {
3337 hi_thrd = shared_buf - pf->dv_buf_size;
3339 if (tc_num <= NEED_RESERVE_TC_NUM)
3340 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3344 hi_thrd = hi_thrd / tc_num;
3346 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3347 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3348 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3350 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3351 lo_thrd = aligned_mps;
3354 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3355 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3356 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3363 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3364 struct hns3_pkt_buf_alloc *buf_alloc)
3366 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3367 struct hns3_pf *pf = &hns->pf;
3368 struct hns3_priv_buf *priv;
3369 uint32_t aligned_mps;
3373 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3374 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3376 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3377 priv = &buf_alloc->priv_buf[i];
3384 if (!(hw->hw_tc_map & BIT(i)))
3388 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3389 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3390 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3391 HNS3_BUF_SIZE_UNIT);
3394 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3398 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3401 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3405 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3406 struct hns3_pkt_buf_alloc *buf_alloc)
3408 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3409 struct hns3_pf *pf = &hns->pf;
3410 struct hns3_priv_buf *priv;
3411 int no_pfc_priv_num;
3416 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3417 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3419 /* let the last to be cleared first */
3420 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3421 priv = &buf_alloc->priv_buf[i];
3422 mask = BIT((uint8_t)i);
3424 if (hw->hw_tc_map & mask &&
3425 !(hw->dcb_info.hw_pfc_map & mask)) {
3426 /* Clear the no pfc TC private buffer */
3434 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3435 no_pfc_priv_num == 0)
3439 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3443 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3444 struct hns3_pkt_buf_alloc *buf_alloc)
3446 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3447 struct hns3_pf *pf = &hns->pf;
3448 struct hns3_priv_buf *priv;
3454 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3455 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3457 /* let the last to be cleared first */
3458 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3459 priv = &buf_alloc->priv_buf[i];
3460 mask = BIT((uint8_t)i);
3462 if (hw->hw_tc_map & mask &&
3463 hw->dcb_info.hw_pfc_map & mask) {
3464 /* Reduce the number of pfc TC with private buffer */
3471 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3476 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3480 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3481 struct hns3_pkt_buf_alloc *buf_alloc)
3483 #define COMPENSATE_BUFFER 0x3C00
3484 #define COMPENSATE_HALF_MPS_NUM 5
3485 #define PRIV_WL_GAP 0x1800
3486 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3487 struct hns3_pf *pf = &hns->pf;
3488 uint32_t tc_num = hns3_get_tc_num(hw);
3489 uint32_t half_mps = pf->mps >> 1;
3490 struct hns3_priv_buf *priv;
3491 uint32_t min_rx_priv;
3495 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3497 rx_priv = rx_priv / tc_num;
3499 if (tc_num <= NEED_RESERVE_TC_NUM)
3500 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3503 * Minimum value of private buffer in rx direction (min_rx_priv) is
3504 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3505 * buffer if rx_priv is greater than min_rx_priv.
3507 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3508 COMPENSATE_HALF_MPS_NUM * half_mps;
3509 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3510 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3512 if (rx_priv < min_rx_priv)
3515 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3516 priv = &buf_alloc->priv_buf[i];
3523 if (!(hw->hw_tc_map & BIT(i)))
3527 priv->buf_size = rx_priv;
3528 priv->wl.high = rx_priv - pf->dv_buf_size;
3529 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3532 buf_alloc->s_buf.buf_size = 0;
3538 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3539 * @hw: pointer to struct hns3_hw
3540 * @buf_alloc: pointer to buffer calculation data
3541 * @return: 0: calculate sucessful, negative: fail
3544 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3546 /* When DCB is not supported, rx private buffer is not allocated. */
3547 if (!hns3_dev_dcb_supported(hw)) {
3548 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3549 struct hns3_pf *pf = &hns->pf;
3550 uint32_t rx_all = pf->pkt_buf_size;
3552 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3553 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3560 * Try to allocate privated packet buffer for all TCs without share
3563 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3567 * Try to allocate privated packet buffer for all TCs with share
3570 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3574 * For different application scenes, the enabled port number, TC number
3575 * and no_drop TC number are different. In order to obtain the better
3576 * performance, software could allocate the buffer size and configure
3577 * the waterline by tring to decrease the private buffer size according
3578 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3581 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3584 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3587 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3594 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3596 struct hns3_rx_priv_buff_cmd *req;
3597 struct hns3_cmd_desc desc;
3602 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3603 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3605 /* Alloc private buffer TCs */
3606 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3607 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3610 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3611 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3614 buf_size = buf_alloc->s_buf.buf_size;
3615 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3616 (1 << HNS3_TC0_PRI_BUF_EN_B));
3618 ret = hns3_cmd_send(hw, &desc, 1);
3620 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3626 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3628 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3629 struct hns3_rx_priv_wl_buf *req;
3630 struct hns3_priv_buf *priv;
3631 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3635 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3636 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3638 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3640 /* The first descriptor set the NEXT bit to 1 */
3642 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3644 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3646 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3647 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3649 priv = &buf_alloc->priv_buf[idx];
3650 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3652 req->tc_wl[j].high |=
3653 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3654 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3656 req->tc_wl[j].low |=
3657 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3661 /* Send 2 descriptor at one time */
3662 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3664 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3670 hns3_common_thrd_config(struct hns3_hw *hw,
3671 struct hns3_pkt_buf_alloc *buf_alloc)
3673 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3674 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3675 struct hns3_rx_com_thrd *req;
3676 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3677 struct hns3_tc_thrd *tc;
3682 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3683 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3685 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3687 /* The first descriptor set the NEXT bit to 1 */
3689 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3691 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3693 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3694 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3695 tc = &s_buf->tc_thrd[tc_idx];
3697 req->com_thrd[j].high =
3698 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3699 req->com_thrd[j].high |=
3700 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3701 req->com_thrd[j].low =
3702 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3703 req->com_thrd[j].low |=
3704 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3708 /* Send 2 descriptors at one time */
3709 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3711 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3717 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3719 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3720 struct hns3_rx_com_wl *req;
3721 struct hns3_cmd_desc desc;
3724 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3726 req = (struct hns3_rx_com_wl *)desc.data;
3727 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3728 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3730 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3731 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3733 ret = hns3_cmd_send(hw, &desc, 1);
3735 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3741 hns3_buffer_alloc(struct hns3_hw *hw)
3743 struct hns3_pkt_buf_alloc pkt_buf;
3746 memset(&pkt_buf, 0, sizeof(pkt_buf));
3747 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3750 "could not calc tx buffer size for all TCs %d",
3755 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3757 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3761 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3764 "could not calc rx priv buffer size for all TCs %d",
3769 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3771 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3775 if (hns3_dev_dcb_supported(hw)) {
3776 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3779 "could not configure rx private waterline %d",
3784 ret = hns3_common_thrd_config(hw, &pkt_buf);
3787 "could not configure common threshold %d",
3793 ret = hns3_common_wl_config(hw, &pkt_buf);
3795 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3802 hns3_mac_init(struct hns3_hw *hw)
3804 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3805 struct hns3_mac *mac = &hw->mac;
3806 struct hns3_pf *pf = &hns->pf;
3809 pf->support_sfp_query = true;
3810 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3811 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3813 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3817 mac->link_status = ETH_LINK_DOWN;
3819 return hns3_config_mtu(hw, pf->mps);
3823 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3825 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
3826 #define HNS3_ETHERTYPE_ALREADY_ADD 1
3827 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
3828 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
3833 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3838 switch (resp_code) {
3839 case HNS3_ETHERTYPE_SUCCESS_ADD:
3840 case HNS3_ETHERTYPE_ALREADY_ADD:
3843 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3845 "add mac ethertype failed for manager table overflow.");
3846 return_status = -EIO;
3848 case HNS3_ETHERTYPE_KEY_CONFLICT:
3849 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3850 return_status = -EIO;
3854 "add mac ethertype failed for undefined, code=%d.",
3856 return_status = -EIO;
3860 return return_status;
3864 hns3_add_mgr_tbl(struct hns3_hw *hw,
3865 const struct hns3_mac_mgr_tbl_entry_cmd *req)
3867 struct hns3_cmd_desc desc;
3872 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3873 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3875 ret = hns3_cmd_send(hw, &desc, 1);
3878 "add mac ethertype failed for cmd_send, ret =%d.",
3883 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3884 retval = rte_le_to_cpu_16(desc.retval);
3886 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3890 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3891 int *table_item_num)
3893 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3896 * In current version, we add one item in management table as below:
3897 * 0x0180C200000E -- LLDP MC address
3900 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3901 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3902 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3903 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3904 tbl->i_port_bitmap = 0x1;
3905 *table_item_num = 1;
3909 hns3_init_mgr_tbl(struct hns3_hw *hw)
3911 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
3912 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3917 memset(mgr_table, 0, sizeof(mgr_table));
3918 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3919 for (i = 0; i < table_item_num; i++) {
3920 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3922 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3932 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3933 bool en_mc, bool en_bc, int vport_id)
3938 memset(param, 0, sizeof(struct hns3_promisc_param));
3940 param->enable = HNS3_PROMISC_EN_UC;
3942 param->enable |= HNS3_PROMISC_EN_MC;
3944 param->enable |= HNS3_PROMISC_EN_BC;
3945 param->vf_id = vport_id;
3949 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3951 struct hns3_promisc_cfg_cmd *req;
3952 struct hns3_cmd_desc desc;
3955 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3957 req = (struct hns3_promisc_cfg_cmd *)desc.data;
3958 req->vf_id = param->vf_id;
3959 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3960 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3962 ret = hns3_cmd_send(hw, &desc, 1);
3964 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3970 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3972 struct hns3_promisc_param param;
3973 bool en_bc_pmc = true;
3977 * In current version VF is not supported when PF is driven by DPDK
3978 * driver, just need to configure parameters for PF vport.
3980 vf_id = HNS3_PF_FUNC_ID;
3982 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3983 return hns3_cmd_set_promisc_mode(hw, ¶m);
3987 hns3_promisc_init(struct hns3_hw *hw)
3989 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3990 struct hns3_pf *pf = &hns->pf;
3991 struct hns3_promisc_param param;
3995 ret = hns3_set_promisc_mode(hw, false, false);
3997 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4002 * In current version VFs are not supported when PF is driven by DPDK
4003 * driver. After PF has been taken over by DPDK, the original VF will
4004 * be invalid. So, there is a possibility of entry residues. It should
4005 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4008 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4009 hns3_promisc_param_init(¶m, false, false, false, func_id);
4010 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4012 PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode,"
4013 " ret = %d", func_id, ret);
4022 hns3_promisc_uninit(struct hns3_hw *hw)
4024 struct hns3_promisc_param param;
4028 func_id = HNS3_PF_FUNC_ID;
4031 * In current version VFs are not supported when PF is driven by
4032 * DPDK driver, and VFs' promisc mode status has been cleared during
4033 * init and their status will not change. So just clear PF's promisc
4034 * mode status during uninit.
4036 hns3_promisc_param_init(¶m, false, false, false, func_id);
4037 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4039 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4040 " uninit, ret = %d", ret);
4044 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4046 bool allmulti = dev->data->all_multicast ? true : false;
4047 struct hns3_adapter *hns = dev->data->dev_private;
4048 struct hns3_hw *hw = &hns->hw;
4053 rte_spinlock_lock(&hw->lock);
4054 ret = hns3_set_promisc_mode(hw, true, true);
4056 rte_spinlock_unlock(&hw->lock);
4057 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4063 * When promiscuous mode was enabled, disable the vlan filter to let
4064 * all packets coming in in the receiving direction.
4066 offloads = dev->data->dev_conf.rxmode.offloads;
4067 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4068 ret = hns3_enable_vlan_filter(hns, false);
4070 hns3_err(hw, "failed to enable promiscuous mode due to "
4071 "failure to disable vlan filter, ret = %d",
4073 err = hns3_set_promisc_mode(hw, false, allmulti);
4075 hns3_err(hw, "failed to restore promiscuous "
4076 "status after disable vlan filter "
4077 "failed during enabling promiscuous "
4078 "mode, ret = %d", ret);
4082 rte_spinlock_unlock(&hw->lock);
4088 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4090 bool allmulti = dev->data->all_multicast ? true : false;
4091 struct hns3_adapter *hns = dev->data->dev_private;
4092 struct hns3_hw *hw = &hns->hw;
4097 /* If now in all_multicast mode, must remain in all_multicast mode. */
4098 rte_spinlock_lock(&hw->lock);
4099 ret = hns3_set_promisc_mode(hw, false, allmulti);
4101 rte_spinlock_unlock(&hw->lock);
4102 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4106 /* when promiscuous mode was disabled, restore the vlan filter status */
4107 offloads = dev->data->dev_conf.rxmode.offloads;
4108 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4109 ret = hns3_enable_vlan_filter(hns, true);
4111 hns3_err(hw, "failed to disable promiscuous mode due to"
4112 " failure to restore vlan filter, ret = %d",
4114 err = hns3_set_promisc_mode(hw, true, true);
4116 hns3_err(hw, "failed to restore promiscuous "
4117 "status after enabling vlan filter "
4118 "failed during disabling promiscuous "
4119 "mode, ret = %d", ret);
4122 rte_spinlock_unlock(&hw->lock);
4128 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4130 struct hns3_adapter *hns = dev->data->dev_private;
4131 struct hns3_hw *hw = &hns->hw;
4134 if (dev->data->promiscuous)
4137 rte_spinlock_lock(&hw->lock);
4138 ret = hns3_set_promisc_mode(hw, false, true);
4139 rte_spinlock_unlock(&hw->lock);
4141 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4148 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4150 struct hns3_adapter *hns = dev->data->dev_private;
4151 struct hns3_hw *hw = &hns->hw;
4154 /* If now in promiscuous mode, must remain in all_multicast mode. */
4155 if (dev->data->promiscuous)
4158 rte_spinlock_lock(&hw->lock);
4159 ret = hns3_set_promisc_mode(hw, false, false);
4160 rte_spinlock_unlock(&hw->lock);
4162 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4169 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4171 struct hns3_hw *hw = &hns->hw;
4172 bool allmulti = hw->data->all_multicast ? true : false;
4175 if (hw->data->promiscuous) {
4176 ret = hns3_set_promisc_mode(hw, true, true);
4178 hns3_err(hw, "failed to restore promiscuous mode, "
4183 ret = hns3_set_promisc_mode(hw, false, allmulti);
4185 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4191 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4193 struct hns3_sfp_speed_cmd *resp;
4194 struct hns3_cmd_desc desc;
4197 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4198 resp = (struct hns3_sfp_speed_cmd *)desc.data;
4199 ret = hns3_cmd_send(hw, &desc, 1);
4200 if (ret == -EOPNOTSUPP) {
4201 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4204 hns3_err(hw, "get sfp speed failed %d", ret);
4208 *speed = resp->sfp_speed;
4214 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4216 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4217 duplex = ETH_LINK_FULL_DUPLEX;
4223 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4225 struct hns3_mac *mac = &hw->mac;
4228 duplex = hns3_check_speed_dup(duplex, speed);
4229 if (mac->link_speed == speed && mac->link_duplex == duplex)
4232 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4236 mac->link_speed = speed;
4237 mac->link_duplex = duplex;
4243 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4245 struct hns3_adapter *hns = eth_dev->data->dev_private;
4246 struct hns3_hw *hw = &hns->hw;
4247 struct hns3_pf *pf = &hns->pf;
4251 /* If IMP do not support get SFP/qSFP speed, return directly */
4252 if (!pf->support_sfp_query)
4255 ret = hns3_get_sfp_speed(hw, &speed);
4256 if (ret == -EOPNOTSUPP) {
4257 pf->support_sfp_query = false;
4262 if (speed == ETH_SPEED_NUM_NONE)
4263 return 0; /* do nothing if no SFP */
4265 /* Config full duplex for SFP */
4266 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4270 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4272 struct hns3_config_mac_mode_cmd *req;
4273 struct hns3_cmd_desc desc;
4274 uint32_t loop_en = 0;
4278 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4280 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4283 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4284 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4285 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4286 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4287 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4288 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4289 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4290 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4291 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4292 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4295 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4296 * when receiving frames. Otherwise, CRC will be stripped.
4298 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4299 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4301 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4302 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4303 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4304 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4305 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4307 ret = hns3_cmd_send(hw, &desc, 1);
4309 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4315 hns3_get_mac_link_status(struct hns3_hw *hw)
4317 struct hns3_link_status_cmd *req;
4318 struct hns3_cmd_desc desc;
4322 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4323 ret = hns3_cmd_send(hw, &desc, 1);
4325 hns3_err(hw, "get link status cmd failed %d", ret);
4326 return ETH_LINK_DOWN;
4329 req = (struct hns3_link_status_cmd *)desc.data;
4330 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4332 return !!link_status;
4336 hns3_update_link_status(struct hns3_hw *hw)
4340 state = hns3_get_mac_link_status(hw);
4341 if (state != hw->mac.link_status) {
4342 hw->mac.link_status = state;
4343 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4348 hns3_service_handler(void *param)
4350 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4351 struct hns3_adapter *hns = eth_dev->data->dev_private;
4352 struct hns3_hw *hw = &hns->hw;
4354 if (!hns3_is_reset_pending(hns)) {
4355 hns3_update_speed_duplex(eth_dev);
4356 hns3_update_link_status(hw);
4358 hns3_warn(hw, "Cancel the query when reset is pending");
4360 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4364 hns3_init_hardware(struct hns3_adapter *hns)
4366 struct hns3_hw *hw = &hns->hw;
4369 ret = hns3_map_tqp(hw);
4371 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4375 ret = hns3_init_umv_space(hw);
4377 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4381 ret = hns3_mac_init(hw);
4383 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4387 ret = hns3_init_mgr_tbl(hw);
4389 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4393 ret = hns3_promisc_init(hw);
4395 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4400 ret = hns3_init_vlan_config(hns);
4402 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4406 ret = hns3_dcb_init(hw);
4408 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4412 ret = hns3_init_fd_config(hns);
4414 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4418 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4420 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4424 ret = hns3_config_gro(hw, false);
4426 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4431 * In the initialization clearing the all hardware mapping relationship
4432 * configurations between queues and interrupt vectors is needed, so
4433 * some error caused by the residual configurations, such as the
4434 * unexpected interrupt, can be avoid.
4436 ret = hns3_init_ring_with_vector(hw);
4438 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4445 hns3_uninit_umv_space(hw);
4450 hns3_clear_hw(struct hns3_hw *hw)
4452 struct hns3_cmd_desc desc;
4455 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4457 ret = hns3_cmd_send(hw, &desc, 1);
4458 if (ret && ret != -EOPNOTSUPP)
4465 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4470 * The new firmware support report more hardware error types by
4471 * msix mode. These errors are defined as RAS errors in hardware
4472 * and belong to a different type from the MSI-x errors processed
4473 * by the network driver.
4475 * Network driver should open the new error report on initialition
4477 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4478 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4479 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4483 hns3_init_pf(struct rte_eth_dev *eth_dev)
4485 struct rte_device *dev = eth_dev->device;
4486 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4487 struct hns3_adapter *hns = eth_dev->data->dev_private;
4488 struct hns3_hw *hw = &hns->hw;
4491 PMD_INIT_FUNC_TRACE();
4493 /* Get hardware io base address from pcie BAR2 IO space */
4494 hw->io_base = pci_dev->mem_resource[2].addr;
4496 /* Firmware command queue initialize */
4497 ret = hns3_cmd_init_queue(hw);
4499 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4500 goto err_cmd_init_queue;
4503 hns3_clear_all_event_cause(hw);
4505 /* Firmware command initialize */
4506 ret = hns3_cmd_init(hw);
4508 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4513 * To ensure that the hardware environment is clean during
4514 * initialization, the driver actively clear the hardware environment
4515 * during initialization, including PF and corresponding VFs' vlan, mac,
4516 * flow table configurations, etc.
4518 ret = hns3_clear_hw(hw);
4520 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4524 hns3_config_all_msix_error(hw, true);
4526 ret = rte_intr_callback_register(&pci_dev->intr_handle,
4527 hns3_interrupt_handler,
4530 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4531 goto err_intr_callback_register;
4534 /* Enable interrupt */
4535 rte_intr_enable(&pci_dev->intr_handle);
4536 hns3_pf_enable_irq0(hw);
4538 /* Get configuration */
4539 ret = hns3_get_configuration(hw);
4541 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4542 goto err_get_config;
4545 ret = hns3_init_hardware(hns);
4547 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4548 goto err_get_config;
4551 /* Initialize flow director filter list & hash */
4552 ret = hns3_fdir_filter_init(hns);
4554 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4558 hns3_set_default_rss_args(hw);
4560 ret = hns3_enable_hw_error_intr(hns, true);
4562 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4570 hns3_fdir_filter_uninit(hns);
4572 hns3_uninit_umv_space(hw);
4575 hns3_pf_disable_irq0(hw);
4576 rte_intr_disable(&pci_dev->intr_handle);
4577 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4579 err_intr_callback_register:
4581 hns3_cmd_uninit(hw);
4582 hns3_cmd_destroy_queue(hw);
4590 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4592 struct hns3_adapter *hns = eth_dev->data->dev_private;
4593 struct rte_device *dev = eth_dev->device;
4594 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4595 struct hns3_hw *hw = &hns->hw;
4597 PMD_INIT_FUNC_TRACE();
4599 hns3_enable_hw_error_intr(hns, false);
4600 hns3_rss_uninit(hns);
4601 (void)hns3_config_gro(hw, false);
4602 hns3_promisc_uninit(hw);
4603 hns3_fdir_filter_uninit(hns);
4604 hns3_uninit_umv_space(hw);
4605 hns3_pf_disable_irq0(hw);
4606 rte_intr_disable(&pci_dev->intr_handle);
4607 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4609 hns3_config_all_msix_error(hw, false);
4610 hns3_cmd_uninit(hw);
4611 hns3_cmd_destroy_queue(hw);
4616 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4618 struct hns3_hw *hw = &hns->hw;
4621 ret = hns3_dcb_cfg_update(hns);
4626 ret = hns3_start_queues(hns, reset_queue);
4628 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4633 ret = hns3_cfg_mac_mode(hw, true);
4635 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4636 goto err_config_mac_mode;
4640 err_config_mac_mode:
4641 hns3_stop_queues(hns, true);
4646 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4648 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4649 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4650 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4651 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4652 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4653 uint32_t intr_vector;
4657 if (dev->data->dev_conf.intr_conf.rxq == 0)
4660 /* disable uio/vfio intr/eventfd mapping */
4661 rte_intr_disable(intr_handle);
4663 /* check and configure queue intr-vector mapping */
4664 if (rte_intr_cap_multiple(intr_handle) ||
4665 !RTE_ETH_DEV_SRIOV(dev).active) {
4666 intr_vector = hw->used_rx_queues;
4667 /* creates event fd for each intr vector when MSIX is used */
4668 if (rte_intr_efd_enable(intr_handle, intr_vector))
4671 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4672 intr_handle->intr_vec =
4673 rte_zmalloc("intr_vec",
4674 hw->used_rx_queues * sizeof(int), 0);
4675 if (intr_handle->intr_vec == NULL) {
4676 hns3_err(hw, "Failed to allocate %d rx_queues"
4677 " intr_vec", hw->used_rx_queues);
4679 goto alloc_intr_vec_error;
4683 if (rte_intr_allow_others(intr_handle)) {
4684 vec = RTE_INTR_VEC_RXTX_OFFSET;
4685 base = RTE_INTR_VEC_RXTX_OFFSET;
4687 if (rte_intr_dp_is_en(intr_handle)) {
4688 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4689 ret = hns3_bind_ring_with_vector(hw, vec, true,
4693 goto bind_vector_error;
4694 intr_handle->intr_vec[q_id] = vec;
4695 if (vec < base + intr_handle->nb_efd - 1)
4699 rte_intr_enable(intr_handle);
4703 rte_intr_efd_disable(intr_handle);
4704 if (intr_handle->intr_vec) {
4705 free(intr_handle->intr_vec);
4706 intr_handle->intr_vec = NULL;
4709 alloc_intr_vec_error:
4710 rte_intr_efd_disable(intr_handle);
4715 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4717 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4718 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4719 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4723 if (dev->data->dev_conf.intr_conf.rxq == 0)
4726 if (rte_intr_dp_is_en(intr_handle)) {
4727 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4728 ret = hns3_bind_ring_with_vector(hw,
4729 intr_handle->intr_vec[q_id], true,
4730 HNS3_RING_TYPE_RX, q_id);
4740 hns3_restore_filter(struct rte_eth_dev *dev)
4742 hns3_restore_rss_filter(dev);
4746 hns3_dev_start(struct rte_eth_dev *dev)
4748 struct hns3_adapter *hns = dev->data->dev_private;
4749 struct hns3_hw *hw = &hns->hw;
4752 PMD_INIT_FUNC_TRACE();
4753 if (rte_atomic16_read(&hw->reset.resetting))
4756 rte_spinlock_lock(&hw->lock);
4757 hw->adapter_state = HNS3_NIC_STARTING;
4759 ret = hns3_do_start(hns, true);
4761 hw->adapter_state = HNS3_NIC_CONFIGURED;
4762 rte_spinlock_unlock(&hw->lock);
4765 ret = hns3_map_rx_interrupt(dev);
4767 hw->adapter_state = HNS3_NIC_CONFIGURED;
4768 rte_spinlock_unlock(&hw->lock);
4772 hw->adapter_state = HNS3_NIC_STARTED;
4773 rte_spinlock_unlock(&hw->lock);
4775 hns3_rx_scattered_calc(dev);
4776 hns3_set_rxtx_function(dev);
4777 hns3_mp_req_start_rxtx(dev);
4778 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4780 hns3_restore_filter(dev);
4782 /* Enable interrupt of all rx queues before enabling queues */
4783 hns3_dev_all_rx_queue_intr_enable(hw, true);
4785 * When finished the initialization, enable queues to receive/transmit
4788 hns3_enable_all_queues(hw, true);
4790 hns3_info(hw, "hns3 dev start successful!");
4795 hns3_do_stop(struct hns3_adapter *hns)
4797 struct hns3_hw *hw = &hns->hw;
4801 ret = hns3_cfg_mac_mode(hw, false);
4804 hw->mac.link_status = ETH_LINK_DOWN;
4806 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4807 hns3_configure_all_mac_addr(hns, true);
4810 reset_queue = false;
4811 hw->mac.default_addr_setted = false;
4812 return hns3_stop_queues(hns, reset_queue);
4816 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4818 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4819 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4820 struct hns3_adapter *hns = dev->data->dev_private;
4821 struct hns3_hw *hw = &hns->hw;
4822 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4823 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4826 if (dev->data->dev_conf.intr_conf.rxq == 0)
4829 /* unmap the ring with vector */
4830 if (rte_intr_allow_others(intr_handle)) {
4831 vec = RTE_INTR_VEC_RXTX_OFFSET;
4832 base = RTE_INTR_VEC_RXTX_OFFSET;
4834 if (rte_intr_dp_is_en(intr_handle)) {
4835 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4836 (void)hns3_bind_ring_with_vector(hw, vec, false,
4839 if (vec < base + intr_handle->nb_efd - 1)
4843 /* Clean datapath event and queue/vec mapping */
4844 rte_intr_efd_disable(intr_handle);
4845 if (intr_handle->intr_vec) {
4846 rte_free(intr_handle->intr_vec);
4847 intr_handle->intr_vec = NULL;
4852 hns3_dev_stop(struct rte_eth_dev *dev)
4854 struct hns3_adapter *hns = dev->data->dev_private;
4855 struct hns3_hw *hw = &hns->hw;
4857 PMD_INIT_FUNC_TRACE();
4859 hw->adapter_state = HNS3_NIC_STOPPING;
4860 hns3_set_rxtx_function(dev);
4862 /* Disable datapath on secondary process. */
4863 hns3_mp_req_stop_rxtx(dev);
4864 /* Prevent crashes when queues are still in use. */
4865 rte_delay_ms(hw->tqps_num);
4867 rte_spinlock_lock(&hw->lock);
4868 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4870 hns3_unmap_rx_interrupt(dev);
4871 hns3_dev_release_mbufs(hns);
4872 hw->adapter_state = HNS3_NIC_CONFIGURED;
4874 hns3_rx_scattered_reset(dev);
4875 rte_eal_alarm_cancel(hns3_service_handler, dev);
4876 rte_spinlock_unlock(&hw->lock);
4880 hns3_dev_close(struct rte_eth_dev *eth_dev)
4882 struct hns3_adapter *hns = eth_dev->data->dev_private;
4883 struct hns3_hw *hw = &hns->hw;
4885 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4886 rte_free(eth_dev->process_private);
4887 eth_dev->process_private = NULL;
4891 if (hw->adapter_state == HNS3_NIC_STARTED)
4892 hns3_dev_stop(eth_dev);
4894 hw->adapter_state = HNS3_NIC_CLOSING;
4895 hns3_reset_abort(hns);
4896 hw->adapter_state = HNS3_NIC_CLOSED;
4898 hns3_configure_all_mc_mac_addr(hns, true);
4899 hns3_remove_all_vlan_table(hns);
4900 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4901 hns3_uninit_pf(eth_dev);
4902 hns3_free_all_queues(eth_dev);
4903 rte_free(hw->reset.wait_data);
4904 rte_free(eth_dev->process_private);
4905 eth_dev->process_private = NULL;
4906 hns3_mp_uninit_primary();
4907 hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4911 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4913 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4914 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4916 fc_conf->pause_time = pf->pause_time;
4918 /* return fc current mode */
4919 switch (hw->current_mode) {
4921 fc_conf->mode = RTE_FC_FULL;
4923 case HNS3_FC_TX_PAUSE:
4924 fc_conf->mode = RTE_FC_TX_PAUSE;
4926 case HNS3_FC_RX_PAUSE:
4927 fc_conf->mode = RTE_FC_RX_PAUSE;
4931 fc_conf->mode = RTE_FC_NONE;
4939 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4943 hw->requested_mode = HNS3_FC_NONE;
4945 case RTE_FC_RX_PAUSE:
4946 hw->requested_mode = HNS3_FC_RX_PAUSE;
4948 case RTE_FC_TX_PAUSE:
4949 hw->requested_mode = HNS3_FC_TX_PAUSE;
4952 hw->requested_mode = HNS3_FC_FULL;
4955 hw->requested_mode = HNS3_FC_NONE;
4956 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4957 "configured to RTE_FC_NONE", mode);
4963 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4965 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4966 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4969 if (fc_conf->high_water || fc_conf->low_water ||
4970 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4971 hns3_err(hw, "Unsupported flow control settings specified, "
4972 "high_water(%u), low_water(%u), send_xon(%u) and "
4973 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4974 fc_conf->high_water, fc_conf->low_water,
4975 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4978 if (fc_conf->autoneg) {
4979 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4982 if (!fc_conf->pause_time) {
4983 hns3_err(hw, "Invalid pause time %d setting.",
4984 fc_conf->pause_time);
4988 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4989 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4990 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4991 "current_fc_status = %d", hw->current_fc_status);
4995 hns3_get_fc_mode(hw, fc_conf->mode);
4996 if (hw->requested_mode == hw->current_mode &&
4997 pf->pause_time == fc_conf->pause_time)
5000 rte_spinlock_lock(&hw->lock);
5001 ret = hns3_fc_enable(dev, fc_conf);
5002 rte_spinlock_unlock(&hw->lock);
5008 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5009 struct rte_eth_pfc_conf *pfc_conf)
5011 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5012 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5016 if (!hns3_dev_dcb_supported(hw)) {
5017 hns3_err(hw, "This port does not support dcb configurations.");
5021 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5022 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5023 hns3_err(hw, "Unsupported flow control settings specified, "
5024 "high_water(%u), low_water(%u), send_xon(%u) and "
5025 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5026 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5027 pfc_conf->fc.send_xon,
5028 pfc_conf->fc.mac_ctrl_frame_fwd);
5031 if (pfc_conf->fc.autoneg) {
5032 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5035 if (pfc_conf->fc.pause_time == 0) {
5036 hns3_err(hw, "Invalid pause time %d setting.",
5037 pfc_conf->fc.pause_time);
5041 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5042 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5043 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5044 "current_fc_status = %d", hw->current_fc_status);
5048 priority = pfc_conf->priority;
5049 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5050 if (hw->dcb_info.pfc_en & BIT(priority) &&
5051 hw->requested_mode == hw->current_mode &&
5052 pfc_conf->fc.pause_time == pf->pause_time)
5055 rte_spinlock_lock(&hw->lock);
5056 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5057 rte_spinlock_unlock(&hw->lock);
5063 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5065 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5066 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5067 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5070 rte_spinlock_lock(&hw->lock);
5071 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5072 dcb_info->nb_tcs = pf->local_max_tc;
5074 dcb_info->nb_tcs = 1;
5076 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5077 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5078 for (i = 0; i < dcb_info->nb_tcs; i++)
5079 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5081 for (i = 0; i < hw->num_tc; i++) {
5082 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5083 dcb_info->tc_queue.tc_txq[0][i].base =
5084 hw->tc_queue[i].tqp_offset;
5085 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5086 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5087 hw->tc_queue[i].tqp_count;
5089 rte_spinlock_unlock(&hw->lock);
5095 hns3_reinit_dev(struct hns3_adapter *hns)
5097 struct hns3_hw *hw = &hns->hw;
5100 ret = hns3_cmd_init(hw);
5102 hns3_err(hw, "Failed to init cmd: %d", ret);
5106 ret = hns3_reset_all_queues(hns);
5108 hns3_err(hw, "Failed to reset all queues: %d", ret);
5112 ret = hns3_init_hardware(hns);
5114 hns3_err(hw, "Failed to init hardware: %d", ret);
5118 ret = hns3_enable_hw_error_intr(hns, true);
5120 hns3_err(hw, "fail to enable hw error interrupts: %d",
5124 hns3_info(hw, "Reset done, driver initialization finished.");
5130 is_pf_reset_done(struct hns3_hw *hw)
5132 uint32_t val, reg, reg_bit;
5134 switch (hw->reset.level) {
5135 case HNS3_IMP_RESET:
5136 reg = HNS3_GLOBAL_RESET_REG;
5137 reg_bit = HNS3_IMP_RESET_BIT;
5139 case HNS3_GLOBAL_RESET:
5140 reg = HNS3_GLOBAL_RESET_REG;
5141 reg_bit = HNS3_GLOBAL_RESET_BIT;
5143 case HNS3_FUNC_RESET:
5144 reg = HNS3_FUN_RST_ING;
5145 reg_bit = HNS3_FUN_RST_ING_B;
5147 case HNS3_FLR_RESET:
5149 hns3_err(hw, "Wait for unsupported reset level: %d",
5153 val = hns3_read_dev(hw, reg);
5154 if (hns3_get_bit(val, reg_bit))
5161 hns3_is_reset_pending(struct hns3_adapter *hns)
5163 struct hns3_hw *hw = &hns->hw;
5164 enum hns3_reset_level reset;
5166 hns3_check_event_cause(hns, NULL);
5167 reset = hns3_get_reset_level(hns, &hw->reset.pending);
5168 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5169 hns3_warn(hw, "High level reset %d is pending", reset);
5172 reset = hns3_get_reset_level(hns, &hw->reset.request);
5173 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5174 hns3_warn(hw, "High level reset %d is request", reset);
5181 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5183 struct hns3_hw *hw = &hns->hw;
5184 struct hns3_wait_data *wait_data = hw->reset.wait_data;
5187 if (wait_data->result == HNS3_WAIT_SUCCESS)
5189 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5190 gettimeofday(&tv, NULL);
5191 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5192 tv.tv_sec, tv.tv_usec);
5194 } else if (wait_data->result == HNS3_WAIT_REQUEST)
5197 wait_data->hns = hns;
5198 wait_data->check_completion = is_pf_reset_done;
5199 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5200 HNS3_RESET_WAIT_MS + get_timeofday_ms();
5201 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5202 wait_data->count = HNS3_RESET_WAIT_CNT;
5203 wait_data->result = HNS3_WAIT_REQUEST;
5204 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5209 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5211 struct hns3_cmd_desc desc;
5212 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5214 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5215 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5216 req->fun_reset_vfid = func_id;
5218 return hns3_cmd_send(hw, &desc, 1);
5222 hns3_imp_reset_cmd(struct hns3_hw *hw)
5224 struct hns3_cmd_desc desc;
5226 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5227 desc.data[0] = 0xeedd;
5229 return hns3_cmd_send(hw, &desc, 1);
5233 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5235 struct hns3_hw *hw = &hns->hw;
5239 gettimeofday(&tv, NULL);
5240 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5241 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5242 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5243 tv.tv_sec, tv.tv_usec);
5247 switch (reset_level) {
5248 case HNS3_IMP_RESET:
5249 hns3_imp_reset_cmd(hw);
5250 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5251 tv.tv_sec, tv.tv_usec);
5253 case HNS3_GLOBAL_RESET:
5254 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5255 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5256 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5257 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5258 tv.tv_sec, tv.tv_usec);
5260 case HNS3_FUNC_RESET:
5261 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5262 tv.tv_sec, tv.tv_usec);
5263 /* schedule again to check later */
5264 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5265 hns3_schedule_reset(hns);
5268 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5271 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5274 static enum hns3_reset_level
5275 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5277 struct hns3_hw *hw = &hns->hw;
5278 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5280 /* Return the highest priority reset level amongst all */
5281 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5282 reset_level = HNS3_IMP_RESET;
5283 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5284 reset_level = HNS3_GLOBAL_RESET;
5285 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5286 reset_level = HNS3_FUNC_RESET;
5287 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5288 reset_level = HNS3_FLR_RESET;
5290 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5291 return HNS3_NONE_RESET;
5297 hns3_record_imp_error(struct hns3_adapter *hns)
5299 struct hns3_hw *hw = &hns->hw;
5302 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5303 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5304 hns3_warn(hw, "Detected IMP RD poison!");
5305 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5306 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5307 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5310 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5311 hns3_warn(hw, "Detected IMP CMDQ error!");
5312 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5313 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5314 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5319 hns3_prepare_reset(struct hns3_adapter *hns)
5321 struct hns3_hw *hw = &hns->hw;
5325 switch (hw->reset.level) {
5326 case HNS3_FUNC_RESET:
5327 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5332 * After performaning pf reset, it is not necessary to do the
5333 * mailbox handling or send any command to firmware, because
5334 * any mailbox handling or command to firmware is only valid
5335 * after hns3_cmd_init is called.
5337 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5338 hw->reset.stats.request_cnt++;
5340 case HNS3_IMP_RESET:
5341 hns3_record_imp_error(hns);
5342 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5343 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5344 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5353 hns3_set_rst_done(struct hns3_hw *hw)
5355 struct hns3_pf_rst_done_cmd *req;
5356 struct hns3_cmd_desc desc;
5358 req = (struct hns3_pf_rst_done_cmd *)desc.data;
5359 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5360 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5361 return hns3_cmd_send(hw, &desc, 1);
5365 hns3_stop_service(struct hns3_adapter *hns)
5367 struct hns3_hw *hw = &hns->hw;
5368 struct rte_eth_dev *eth_dev;
5370 eth_dev = &rte_eth_devices[hw->data->port_id];
5371 if (hw->adapter_state == HNS3_NIC_STARTED)
5372 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5373 hw->mac.link_status = ETH_LINK_DOWN;
5375 hns3_set_rxtx_function(eth_dev);
5377 /* Disable datapath on secondary process. */
5378 hns3_mp_req_stop_rxtx(eth_dev);
5379 rte_delay_ms(hw->tqps_num);
5381 rte_spinlock_lock(&hw->lock);
5382 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5383 hw->adapter_state == HNS3_NIC_STOPPING) {
5385 hw->reset.mbuf_deferred_free = true;
5387 hw->reset.mbuf_deferred_free = false;
5390 * It is cumbersome for hardware to pick-and-choose entries for deletion
5391 * from table space. Hence, for function reset software intervention is
5392 * required to delete the entries
5394 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5395 hns3_configure_all_mc_mac_addr(hns, true);
5396 rte_spinlock_unlock(&hw->lock);
5402 hns3_start_service(struct hns3_adapter *hns)
5404 struct hns3_hw *hw = &hns->hw;
5405 struct rte_eth_dev *eth_dev;
5407 if (hw->reset.level == HNS3_IMP_RESET ||
5408 hw->reset.level == HNS3_GLOBAL_RESET)
5409 hns3_set_rst_done(hw);
5410 eth_dev = &rte_eth_devices[hw->data->port_id];
5411 hns3_set_rxtx_function(eth_dev);
5412 hns3_mp_req_start_rxtx(eth_dev);
5413 if (hw->adapter_state == HNS3_NIC_STARTED) {
5414 hns3_service_handler(eth_dev);
5416 /* Enable interrupt of all rx queues before enabling queues */
5417 hns3_dev_all_rx_queue_intr_enable(hw, true);
5419 * When finished the initialization, enable queues to receive
5420 * and transmit packets.
5422 hns3_enable_all_queues(hw, true);
5429 hns3_restore_conf(struct hns3_adapter *hns)
5431 struct hns3_hw *hw = &hns->hw;
5434 ret = hns3_configure_all_mac_addr(hns, false);
5438 ret = hns3_configure_all_mc_mac_addr(hns, false);
5442 ret = hns3_dev_promisc_restore(hns);
5446 ret = hns3_restore_vlan_table(hns);
5450 ret = hns3_restore_vlan_conf(hns);
5454 ret = hns3_restore_all_fdir_filter(hns);
5458 ret = hns3_restore_rx_interrupt(hw);
5462 ret = hns3_restore_gro_conf(hw);
5466 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5467 ret = hns3_do_start(hns, false);
5470 hns3_info(hw, "hns3 dev restart successful!");
5471 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5472 hw->adapter_state = HNS3_NIC_CONFIGURED;
5476 hns3_configure_all_mc_mac_addr(hns, true);
5478 hns3_configure_all_mac_addr(hns, true);
5483 hns3_reset_service(void *param)
5485 struct hns3_adapter *hns = (struct hns3_adapter *)param;
5486 struct hns3_hw *hw = &hns->hw;
5487 enum hns3_reset_level reset_level;
5488 struct timeval tv_delta;
5489 struct timeval tv_start;
5495 * The interrupt is not triggered within the delay time.
5496 * The interrupt may have been lost. It is necessary to handle
5497 * the interrupt to recover from the error.
5499 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5500 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5501 hns3_err(hw, "Handling interrupts in delayed tasks");
5502 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5503 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5504 if (reset_level == HNS3_NONE_RESET) {
5505 hns3_err(hw, "No reset level is set, try IMP reset");
5506 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5509 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5512 * Check if there is any ongoing reset in the hardware. This status can
5513 * be checked from reset_pending. If there is then, we need to wait for
5514 * hardware to complete reset.
5515 * a. If we are able to figure out in reasonable time that hardware
5516 * has fully resetted then, we can proceed with driver, client
5518 * b. else, we can come back later to check this status so re-sched
5521 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5522 if (reset_level != HNS3_NONE_RESET) {
5523 gettimeofday(&tv_start, NULL);
5524 ret = hns3_reset_process(hns, reset_level);
5525 gettimeofday(&tv, NULL);
5526 timersub(&tv, &tv_start, &tv_delta);
5527 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5528 tv_delta.tv_usec / USEC_PER_MSEC;
5529 if (msec > HNS3_RESET_PROCESS_MS)
5530 hns3_err(hw, "%d handle long time delta %" PRIx64
5531 " ms time=%ld.%.6ld",
5532 hw->reset.level, msec,
5533 tv.tv_sec, tv.tv_usec);
5538 /* Check if we got any *new* reset requests to be honored */
5539 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5540 if (reset_level != HNS3_NONE_RESET)
5541 hns3_msix_process(hns, reset_level);
5544 static const struct eth_dev_ops hns3_eth_dev_ops = {
5545 .dev_configure = hns3_dev_configure,
5546 .dev_start = hns3_dev_start,
5547 .dev_stop = hns3_dev_stop,
5548 .dev_close = hns3_dev_close,
5549 .promiscuous_enable = hns3_dev_promiscuous_enable,
5550 .promiscuous_disable = hns3_dev_promiscuous_disable,
5551 .allmulticast_enable = hns3_dev_allmulticast_enable,
5552 .allmulticast_disable = hns3_dev_allmulticast_disable,
5553 .mtu_set = hns3_dev_mtu_set,
5554 .stats_get = hns3_stats_get,
5555 .stats_reset = hns3_stats_reset,
5556 .xstats_get = hns3_dev_xstats_get,
5557 .xstats_get_names = hns3_dev_xstats_get_names,
5558 .xstats_reset = hns3_dev_xstats_reset,
5559 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
5560 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5561 .dev_infos_get = hns3_dev_infos_get,
5562 .fw_version_get = hns3_fw_version_get,
5563 .rx_queue_setup = hns3_rx_queue_setup,
5564 .tx_queue_setup = hns3_tx_queue_setup,
5565 .rx_queue_release = hns3_dev_rx_queue_release,
5566 .tx_queue_release = hns3_dev_tx_queue_release,
5567 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
5568 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
5569 .rxq_info_get = hns3_rxq_info_get,
5570 .txq_info_get = hns3_txq_info_get,
5571 .rx_burst_mode_get = hns3_rx_burst_mode_get,
5572 .tx_burst_mode_get = hns3_tx_burst_mode_get,
5573 .flow_ctrl_get = hns3_flow_ctrl_get,
5574 .flow_ctrl_set = hns3_flow_ctrl_set,
5575 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5576 .mac_addr_add = hns3_add_mac_addr,
5577 .mac_addr_remove = hns3_remove_mac_addr,
5578 .mac_addr_set = hns3_set_default_mac_addr,
5579 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
5580 .link_update = hns3_dev_link_update,
5581 .rss_hash_update = hns3_dev_rss_hash_update,
5582 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
5583 .reta_update = hns3_dev_rss_reta_update,
5584 .reta_query = hns3_dev_rss_reta_query,
5585 .filter_ctrl = hns3_dev_filter_ctrl,
5586 .vlan_filter_set = hns3_vlan_filter_set,
5587 .vlan_tpid_set = hns3_vlan_tpid_set,
5588 .vlan_offload_set = hns3_vlan_offload_set,
5589 .vlan_pvid_set = hns3_vlan_pvid_set,
5590 .get_reg = hns3_get_regs,
5591 .get_dcb_info = hns3_get_dcb_info,
5592 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5595 static const struct hns3_reset_ops hns3_reset_ops = {
5596 .reset_service = hns3_reset_service,
5597 .stop_service = hns3_stop_service,
5598 .prepare_reset = hns3_prepare_reset,
5599 .wait_hardware_ready = hns3_wait_hardware_ready,
5600 .reinit_dev = hns3_reinit_dev,
5601 .restore_conf = hns3_restore_conf,
5602 .start_service = hns3_start_service,
5606 hns3_dev_init(struct rte_eth_dev *eth_dev)
5608 struct hns3_adapter *hns = eth_dev->data->dev_private;
5609 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
5610 struct rte_ether_addr *eth_addr;
5611 struct hns3_hw *hw = &hns->hw;
5614 PMD_INIT_FUNC_TRACE();
5616 eth_dev->process_private = (struct hns3_process_private *)
5617 rte_zmalloc_socket("hns3_filter_list",
5618 sizeof(struct hns3_process_private),
5619 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5620 if (eth_dev->process_private == NULL) {
5621 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5624 /* initialize flow filter lists */
5625 hns3_filterlist_init(eth_dev);
5627 hns3_set_rxtx_function(eth_dev);
5628 eth_dev->dev_ops = &hns3_eth_dev_ops;
5629 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5630 ret = hns3_mp_init_secondary();
5632 PMD_INIT_LOG(ERR, "Failed to init for secondary "
5633 "process, ret = %d", ret);
5634 goto err_mp_init_secondary;
5637 hw->secondary_cnt++;
5641 ret = hns3_mp_init_primary();
5644 "Failed to init for primary process, ret = %d",
5646 goto err_mp_init_primary;
5649 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5651 hw->data = eth_dev->data;
5654 * Set default max packet size according to the mtu
5655 * default vale in DPDK frame.
5657 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5659 ret = hns3_reset_init(hw);
5661 goto err_init_reset;
5662 hw->reset.ops = &hns3_reset_ops;
5664 ret = hns3_init_pf(eth_dev);
5666 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5670 /* Allocate memory for storing MAC addresses */
5671 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5672 sizeof(struct rte_ether_addr) *
5673 HNS3_UC_MACADDR_NUM, 0);
5674 if (eth_dev->data->mac_addrs == NULL) {
5675 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5676 "to store MAC addresses",
5677 sizeof(struct rte_ether_addr) *
5678 HNS3_UC_MACADDR_NUM);
5680 goto err_rte_zmalloc;
5683 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
5684 if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
5685 rte_eth_random_addr(hw->mac.mac_addr);
5686 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
5687 (struct rte_ether_addr *)hw->mac.mac_addr);
5688 hns3_warn(hw, "default mac_addr from firmware is an invalid "
5689 "unicast address, using random MAC address %s",
5692 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5693 ð_dev->data->mac_addrs[0]);
5695 hw->adapter_state = HNS3_NIC_INITIALIZED;
5697 * Pass the information to the rte_eth_dev_close() that it should also
5698 * release the private port resources.
5700 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5702 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5703 hns3_err(hw, "Reschedule reset service after dev_init");
5704 hns3_schedule_reset(hns);
5706 /* IMP will wait ready flag before reset */
5707 hns3_notify_reset_ready(hw, false);
5710 hns3_info(hw, "hns3 dev initialization successful!");
5714 hns3_uninit_pf(eth_dev);
5717 rte_free(hw->reset.wait_data);
5720 hns3_mp_uninit_primary();
5722 err_mp_init_primary:
5723 err_mp_init_secondary:
5724 eth_dev->dev_ops = NULL;
5725 eth_dev->rx_pkt_burst = NULL;
5726 eth_dev->tx_pkt_burst = NULL;
5727 eth_dev->tx_pkt_prepare = NULL;
5728 rte_free(eth_dev->process_private);
5729 eth_dev->process_private = NULL;
5734 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5736 struct hns3_adapter *hns = eth_dev->data->dev_private;
5737 struct hns3_hw *hw = &hns->hw;
5739 PMD_INIT_FUNC_TRACE();
5741 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5744 eth_dev->dev_ops = NULL;
5745 eth_dev->rx_pkt_burst = NULL;
5746 eth_dev->tx_pkt_burst = NULL;
5747 eth_dev->tx_pkt_prepare = NULL;
5748 if (hw->adapter_state < HNS3_NIC_CLOSING)
5749 hns3_dev_close(eth_dev);
5751 hw->adapter_state = HNS3_NIC_REMOVED;
5756 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5757 struct rte_pci_device *pci_dev)
5759 return rte_eth_dev_pci_generic_probe(pci_dev,
5760 sizeof(struct hns3_adapter),
5765 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5767 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5770 static const struct rte_pci_id pci_id_hns3_map[] = {
5771 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5772 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5773 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5774 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5775 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5776 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
5777 { .vendor_id = 0, /* sentinel */ },
5780 static struct rte_pci_driver rte_hns3_pmd = {
5781 .id_table = pci_id_hns3_map,
5782 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5783 .probe = eth_hns3_pci_probe,
5784 .remove = eth_hns3_pci_remove,
5787 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5788 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5789 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5790 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
5791 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);