1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
6 #include <rte_bus_pci.h>
7 #include <ethdev_pci.h>
9 #include <rte_kvargs.h>
11 #include "hns3_ethdev.h"
12 #include "hns3_logs.h"
13 #include "hns3_rxtx.h"
14 #include "hns3_intr.h"
15 #include "hns3_regs.h"
19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
22 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
23 #define HNS3_SERVICE_QUICK_INTERVAL 10
24 #define HNS3_INVALID_PVID 0xFFFF
26 #define HNS3_FILTER_TYPE_VF 0
27 #define HNS3_FILTER_TYPE_PORT 1
28 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
29 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
30 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
31 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
32 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
33 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
34 | HNS3_FILTER_FE_ROCE_EGRESS_B)
35 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
36 | HNS3_FILTER_FE_ROCE_INGRESS_B)
38 /* Reset related Registers */
39 #define HNS3_GLOBAL_RESET_BIT 0
40 #define HNS3_CORE_RESET_BIT 1
41 #define HNS3_IMP_RESET_BIT 2
42 #define HNS3_FUN_RST_ING_B 0
44 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
45 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
46 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U
47 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
49 #define HNS3_RESET_WAIT_MS 100
50 #define HNS3_RESET_WAIT_CNT 200
52 /* FEC mode order defined in HNS3 hardware */
53 #define HNS3_HW_FEC_MODE_NOFEC 0
54 #define HNS3_HW_FEC_MODE_BASER 1
55 #define HNS3_HW_FEC_MODE_RS 2
58 HNS3_VECTOR0_EVENT_RST,
59 HNS3_VECTOR0_EVENT_MBX,
60 HNS3_VECTOR0_EVENT_ERR,
61 HNS3_VECTOR0_EVENT_OTHER,
64 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
65 { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
66 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
67 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
69 { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
70 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
71 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
72 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
74 { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
75 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
76 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
78 { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
79 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
80 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
81 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
83 { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
84 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
85 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
87 { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
88 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
89 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
92 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
94 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
95 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
97 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
98 static bool hns3_update_link_status(struct hns3_hw *hw);
100 static int hns3_add_mc_addr(struct hns3_hw *hw,
101 struct rte_ether_addr *mac_addr);
102 static int hns3_remove_mc_addr(struct hns3_hw *hw,
103 struct rte_ether_addr *mac_addr);
104 static int hns3_restore_fec(struct hns3_hw *hw);
105 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
106 static int hns3_do_stop(struct hns3_adapter *hns);
108 void hns3_ether_format_addr(char *buf, uint16_t size,
109 const struct rte_ether_addr *ether_addr)
111 snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
112 ether_addr->addr_bytes[0],
113 ether_addr->addr_bytes[4],
114 ether_addr->addr_bytes[5]);
118 hns3_pf_disable_irq0(struct hns3_hw *hw)
120 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
124 hns3_pf_enable_irq0(struct hns3_hw *hw)
126 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
129 static enum hns3_evt_cause
130 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
133 struct hns3_hw *hw = &hns->hw;
135 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
136 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
137 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
139 hw->reset.stats.imp_cnt++;
140 hns3_warn(hw, "IMP reset detected, clear reset status");
142 hns3_schedule_delayed_reset(hns);
143 hns3_warn(hw, "IMP reset detected, don't clear reset status");
146 return HNS3_VECTOR0_EVENT_RST;
149 static enum hns3_evt_cause
150 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
153 struct hns3_hw *hw = &hns->hw;
155 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
156 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
157 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
159 hw->reset.stats.global_cnt++;
160 hns3_warn(hw, "Global reset detected, clear reset status");
162 hns3_schedule_delayed_reset(hns);
164 "Global reset detected, don't clear reset status");
167 return HNS3_VECTOR0_EVENT_RST;
170 static enum hns3_evt_cause
171 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
173 struct hns3_hw *hw = &hns->hw;
174 uint32_t vector0_int_stats;
175 uint32_t cmdq_src_val;
176 uint32_t hw_err_src_reg;
178 enum hns3_evt_cause ret;
181 /* fetch the events from their corresponding regs */
182 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
183 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
184 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
186 is_delay = clearval == NULL ? true : false;
188 * Assumption: If by any chance reset and mailbox events are reported
189 * together then we will only process reset event and defer the
190 * processing of the mailbox events. Since, we would have not cleared
191 * RX CMDQ event this time we would receive again another interrupt
192 * from H/W just for the mailbox.
194 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
195 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
200 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
201 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
205 /* check for vector0 msix event source */
206 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
207 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
208 val = vector0_int_stats | hw_err_src_reg;
209 ret = HNS3_VECTOR0_EVENT_ERR;
213 /* check for vector0 mailbox(=CMDQ RX) event source */
214 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
215 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
217 ret = HNS3_VECTOR0_EVENT_MBX;
221 val = vector0_int_stats;
222 ret = HNS3_VECTOR0_EVENT_OTHER;
231 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
233 if (event_type == HNS3_VECTOR0_EVENT_RST)
234 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
235 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
236 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
240 hns3_clear_all_event_cause(struct hns3_hw *hw)
242 uint32_t vector0_int_stats;
243 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
245 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
246 hns3_warn(hw, "Probe during IMP reset interrupt");
248 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
249 hns3_warn(hw, "Probe during Global reset interrupt");
251 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
252 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
253 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
254 BIT(HNS3_VECTOR0_CORERESET_INT_B));
255 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
259 hns3_handle_mac_tnl(struct hns3_hw *hw)
261 struct hns3_cmd_desc desc;
265 /* query and clear mac tnl interruptions */
266 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
267 ret = hns3_cmd_send(hw, &desc, 1);
269 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
273 status = rte_le_to_cpu_32(desc.data[0]);
275 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
276 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
278 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
279 ret = hns3_cmd_send(hw, &desc, 1);
281 hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
287 hns3_interrupt_handler(void *param)
289 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
290 struct hns3_adapter *hns = dev->data->dev_private;
291 struct hns3_hw *hw = &hns->hw;
292 enum hns3_evt_cause event_cause;
293 uint32_t clearval = 0;
294 uint32_t vector0_int;
298 /* Disable interrupt */
299 hns3_pf_disable_irq0(hw);
301 event_cause = hns3_check_event_cause(hns, &clearval);
302 vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
303 ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
304 cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
305 /* vector 0 interrupt is shared with reset and mailbox source events. */
306 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
307 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
308 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
309 vector0_int, ras_int, cmdq_int);
310 hns3_handle_msix_error(hns, &hw->reset.request);
311 hns3_handle_ras_error(hns, &hw->reset.request);
312 hns3_handle_mac_tnl(hw);
313 hns3_schedule_reset(hns);
314 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
315 hns3_warn(hw, "received reset interrupt");
316 hns3_schedule_reset(hns);
317 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
318 hns3_dev_handle_mbx_msg(hw);
320 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
321 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
322 vector0_int, ras_int, cmdq_int);
325 hns3_clear_event_cause(hw, event_cause, clearval);
326 /* Enable interrupt if it is not cause by reset */
327 hns3_pf_enable_irq0(hw);
331 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
333 #define HNS3_VLAN_ID_OFFSET_STEP 160
334 #define HNS3_VLAN_BYTE_SIZE 8
335 struct hns3_vlan_filter_pf_cfg_cmd *req;
336 struct hns3_hw *hw = &hns->hw;
337 uint8_t vlan_offset_byte_val;
338 struct hns3_cmd_desc desc;
339 uint8_t vlan_offset_byte;
340 uint8_t vlan_offset_base;
343 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
345 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
346 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
348 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
350 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
351 req->vlan_offset = vlan_offset_base;
352 req->vlan_cfg = on ? 0 : 1;
353 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
355 ret = hns3_cmd_send(hw, &desc, 1);
357 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
364 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
366 struct hns3_user_vlan_table *vlan_entry;
367 struct hns3_pf *pf = &hns->pf;
369 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
370 if (vlan_entry->vlan_id == vlan_id) {
371 if (vlan_entry->hd_tbl_status)
372 hns3_set_port_vlan_filter(hns, vlan_id, 0);
373 LIST_REMOVE(vlan_entry, next);
374 rte_free(vlan_entry);
381 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
384 struct hns3_user_vlan_table *vlan_entry;
385 struct hns3_hw *hw = &hns->hw;
386 struct hns3_pf *pf = &hns->pf;
388 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
389 if (vlan_entry->vlan_id == vlan_id)
393 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
394 if (vlan_entry == NULL) {
395 hns3_err(hw, "Failed to malloc hns3 vlan table");
399 vlan_entry->hd_tbl_status = writen_to_tbl;
400 vlan_entry->vlan_id = vlan_id;
402 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
406 hns3_restore_vlan_table(struct hns3_adapter *hns)
408 struct hns3_user_vlan_table *vlan_entry;
409 struct hns3_hw *hw = &hns->hw;
410 struct hns3_pf *pf = &hns->pf;
414 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
415 return hns3_vlan_pvid_configure(hns,
416 hw->port_base_vlan_cfg.pvid, 1);
418 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
419 if (vlan_entry->hd_tbl_status) {
420 vlan_id = vlan_entry->vlan_id;
421 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
431 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
433 struct hns3_hw *hw = &hns->hw;
434 bool writen_to_tbl = false;
438 * When vlan filter is enabled, hardware regards packets without vlan
439 * as packets with vlan 0. So, to receive packets without vlan, vlan id
440 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
442 if (on == 0 && vlan_id == 0)
446 * When port base vlan enabled, we use port base vlan as the vlan
447 * filter condition. In this case, we don't update vlan filter table
448 * when user add new vlan or remove exist vlan, just update the
449 * vlan list. The vlan id in vlan list will be writen in vlan filter
450 * table until port base vlan disabled
452 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
453 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
454 writen_to_tbl = true;
459 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
461 hns3_rm_dev_vlan_table(hns, vlan_id);
467 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
469 struct hns3_adapter *hns = dev->data->dev_private;
470 struct hns3_hw *hw = &hns->hw;
473 rte_spinlock_lock(&hw->lock);
474 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
475 rte_spinlock_unlock(&hw->lock);
480 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
483 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
484 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
485 struct hns3_hw *hw = &hns->hw;
486 struct hns3_cmd_desc desc;
489 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
490 vlan_type != ETH_VLAN_TYPE_OUTER)) {
491 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
495 if (tpid != RTE_ETHER_TYPE_VLAN) {
496 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
500 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
501 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
503 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
504 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
505 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
506 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
507 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
508 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
509 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
510 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
513 ret = hns3_cmd_send(hw, &desc, 1);
515 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
520 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
522 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
523 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
524 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
526 ret = hns3_cmd_send(hw, &desc, 1);
528 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
534 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
537 struct hns3_adapter *hns = dev->data->dev_private;
538 struct hns3_hw *hw = &hns->hw;
541 rte_spinlock_lock(&hw->lock);
542 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
543 rte_spinlock_unlock(&hw->lock);
548 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
549 struct hns3_rx_vtag_cfg *vcfg)
551 struct hns3_vport_vtag_rx_cfg_cmd *req;
552 struct hns3_hw *hw = &hns->hw;
553 struct hns3_cmd_desc desc;
558 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
560 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
561 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
562 vcfg->strip_tag1_en ? 1 : 0);
563 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
564 vcfg->strip_tag2_en ? 1 : 0);
565 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
566 vcfg->vlan1_vlan_prionly ? 1 : 0);
567 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
568 vcfg->vlan2_vlan_prionly ? 1 : 0);
570 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
571 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
572 vcfg->strip_tag1_discard_en ? 1 : 0);
573 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
574 vcfg->strip_tag2_discard_en ? 1 : 0);
576 * In current version VF is not supported when PF is driven by DPDK
577 * driver, just need to configure parameters for PF vport.
579 vport_id = HNS3_PF_FUNC_ID;
580 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
581 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
582 req->vf_bitmap[req->vf_offset] = bitmap;
584 ret = hns3_cmd_send(hw, &desc, 1);
586 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
591 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
592 struct hns3_rx_vtag_cfg *vcfg)
594 struct hns3_pf *pf = &hns->pf;
595 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
599 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
600 struct hns3_tx_vtag_cfg *vcfg)
602 struct hns3_pf *pf = &hns->pf;
603 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
607 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
609 struct hns3_rx_vtag_cfg rxvlan_cfg;
610 struct hns3_hw *hw = &hns->hw;
613 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
614 rxvlan_cfg.strip_tag1_en = false;
615 rxvlan_cfg.strip_tag2_en = enable;
616 rxvlan_cfg.strip_tag2_discard_en = false;
618 rxvlan_cfg.strip_tag1_en = enable;
619 rxvlan_cfg.strip_tag2_en = true;
620 rxvlan_cfg.strip_tag2_discard_en = true;
623 rxvlan_cfg.strip_tag1_discard_en = false;
624 rxvlan_cfg.vlan1_vlan_prionly = false;
625 rxvlan_cfg.vlan2_vlan_prionly = false;
626 rxvlan_cfg.rx_vlan_offload_en = enable;
628 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
630 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
634 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
640 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
641 uint8_t fe_type, bool filter_en, uint8_t vf_id)
643 struct hns3_vlan_filter_ctrl_cmd *req;
644 struct hns3_cmd_desc desc;
647 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
649 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
650 req->vlan_type = vlan_type;
651 req->vlan_fe = filter_en ? fe_type : 0;
654 ret = hns3_cmd_send(hw, &desc, 1);
656 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
662 hns3_vlan_filter_init(struct hns3_adapter *hns)
664 struct hns3_hw *hw = &hns->hw;
667 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
668 HNS3_FILTER_FE_EGRESS, false,
671 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
675 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
676 HNS3_FILTER_FE_INGRESS, false,
679 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
685 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
687 struct hns3_hw *hw = &hns->hw;
690 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
691 HNS3_FILTER_FE_INGRESS, enable,
694 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
695 enable ? "enable" : "disable", ret);
701 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
703 struct hns3_adapter *hns = dev->data->dev_private;
704 struct hns3_hw *hw = &hns->hw;
705 struct rte_eth_rxmode *rxmode;
706 unsigned int tmp_mask;
710 rte_spinlock_lock(&hw->lock);
711 rxmode = &dev->data->dev_conf.rxmode;
712 tmp_mask = (unsigned int)mask;
713 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
714 /* ignore vlan filter configuration during promiscuous mode */
715 if (!dev->data->promiscuous) {
716 /* Enable or disable VLAN filter */
717 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
720 ret = hns3_enable_vlan_filter(hns, enable);
722 rte_spinlock_unlock(&hw->lock);
723 hns3_err(hw, "failed to %s rx filter, ret = %d",
724 enable ? "enable" : "disable", ret);
730 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
731 /* Enable or disable VLAN stripping */
732 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
735 ret = hns3_en_hw_strip_rxvtag(hns, enable);
737 rte_spinlock_unlock(&hw->lock);
738 hns3_err(hw, "failed to %s rx strip, ret = %d",
739 enable ? "enable" : "disable", ret);
744 rte_spinlock_unlock(&hw->lock);
750 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
751 struct hns3_tx_vtag_cfg *vcfg)
753 struct hns3_vport_vtag_tx_cfg_cmd *req;
754 struct hns3_cmd_desc desc;
755 struct hns3_hw *hw = &hns->hw;
760 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
762 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
763 req->def_vlan_tag1 = vcfg->default_tag1;
764 req->def_vlan_tag2 = vcfg->default_tag2;
765 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
766 vcfg->accept_tag1 ? 1 : 0);
767 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
768 vcfg->accept_untag1 ? 1 : 0);
769 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
770 vcfg->accept_tag2 ? 1 : 0);
771 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
772 vcfg->accept_untag2 ? 1 : 0);
773 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
774 vcfg->insert_tag1_en ? 1 : 0);
775 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
776 vcfg->insert_tag2_en ? 1 : 0);
777 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
779 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
780 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
781 vcfg->tag_shift_mode_en ? 1 : 0);
784 * In current version VF is not supported when PF is driven by DPDK
785 * driver, just need to configure parameters for PF vport.
787 vport_id = HNS3_PF_FUNC_ID;
788 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
789 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
790 req->vf_bitmap[req->vf_offset] = bitmap;
792 ret = hns3_cmd_send(hw, &desc, 1);
794 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
800 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
803 struct hns3_hw *hw = &hns->hw;
804 struct hns3_tx_vtag_cfg txvlan_cfg;
807 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
808 txvlan_cfg.accept_tag1 = true;
809 txvlan_cfg.insert_tag1_en = false;
810 txvlan_cfg.default_tag1 = 0;
812 txvlan_cfg.accept_tag1 =
813 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
814 txvlan_cfg.insert_tag1_en = true;
815 txvlan_cfg.default_tag1 = pvid;
818 txvlan_cfg.accept_untag1 = true;
819 txvlan_cfg.accept_tag2 = true;
820 txvlan_cfg.accept_untag2 = true;
821 txvlan_cfg.insert_tag2_en = false;
822 txvlan_cfg.default_tag2 = 0;
823 txvlan_cfg.tag_shift_mode_en = true;
825 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
827 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
832 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
838 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
840 struct hns3_user_vlan_table *vlan_entry;
841 struct hns3_pf *pf = &hns->pf;
843 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
844 if (vlan_entry->hd_tbl_status) {
845 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
846 vlan_entry->hd_tbl_status = false;
851 vlan_entry = LIST_FIRST(&pf->vlan_list);
853 LIST_REMOVE(vlan_entry, next);
854 rte_free(vlan_entry);
855 vlan_entry = LIST_FIRST(&pf->vlan_list);
861 hns3_add_all_vlan_table(struct hns3_adapter *hns)
863 struct hns3_user_vlan_table *vlan_entry;
864 struct hns3_pf *pf = &hns->pf;
866 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
867 if (!vlan_entry->hd_tbl_status) {
868 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
869 vlan_entry->hd_tbl_status = true;
875 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
877 struct hns3_hw *hw = &hns->hw;
880 hns3_rm_all_vlan_table(hns, true);
881 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
882 ret = hns3_set_port_vlan_filter(hns,
883 hw->port_base_vlan_cfg.pvid, 0);
885 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
893 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
894 uint16_t port_base_vlan_state, uint16_t new_pvid)
896 struct hns3_hw *hw = &hns->hw;
900 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
901 old_pvid = hw->port_base_vlan_cfg.pvid;
902 if (old_pvid != HNS3_INVALID_PVID) {
903 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
905 hns3_err(hw, "failed to remove old pvid %u, "
906 "ret = %d", old_pvid, ret);
911 hns3_rm_all_vlan_table(hns, false);
912 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
914 hns3_err(hw, "failed to add new pvid %u, ret = %d",
919 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
921 hns3_err(hw, "failed to remove pvid %u, ret = %d",
926 hns3_add_all_vlan_table(hns);
932 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
934 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
935 struct hns3_rx_vtag_cfg rx_vlan_cfg;
939 rx_strip_en = old_cfg->rx_vlan_offload_en;
941 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
942 rx_vlan_cfg.strip_tag2_en = true;
943 rx_vlan_cfg.strip_tag2_discard_en = true;
945 rx_vlan_cfg.strip_tag1_en = false;
946 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
947 rx_vlan_cfg.strip_tag2_discard_en = false;
949 rx_vlan_cfg.strip_tag1_discard_en = false;
950 rx_vlan_cfg.vlan1_vlan_prionly = false;
951 rx_vlan_cfg.vlan2_vlan_prionly = false;
952 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
954 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
958 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
963 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
965 struct hns3_hw *hw = &hns->hw;
966 uint16_t port_base_vlan_state;
969 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
970 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
971 hns3_warn(hw, "Invalid operation! As current pvid set "
972 "is %u, disable pvid %u is invalid",
973 hw->port_base_vlan_cfg.pvid, pvid);
977 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
978 HNS3_PORT_BASE_VLAN_DISABLE;
979 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
981 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
986 ret = hns3_en_pvid_strip(hns, on);
988 hns3_err(hw, "failed to config rx vlan strip for pvid, "
993 if (pvid == HNS3_INVALID_PVID)
995 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
997 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1003 hw->port_base_vlan_cfg.state = port_base_vlan_state;
1004 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1009 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1011 struct hns3_adapter *hns = dev->data->dev_private;
1012 struct hns3_hw *hw = &hns->hw;
1013 bool pvid_en_state_change;
1014 uint16_t pvid_state;
1017 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1018 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1019 RTE_ETHER_MAX_VLAN_ID);
1024 * If PVID configuration state change, should refresh the PVID
1025 * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1027 pvid_state = hw->port_base_vlan_cfg.state;
1028 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1029 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1030 pvid_en_state_change = false;
1032 pvid_en_state_change = true;
1034 rte_spinlock_lock(&hw->lock);
1035 ret = hns3_vlan_pvid_configure(hns, pvid, on);
1036 rte_spinlock_unlock(&hw->lock);
1040 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1041 * need be processed by PMD driver.
1043 if (pvid_en_state_change &&
1044 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1045 hns3_update_all_queues_pvid_proc_en(hw);
1051 hns3_default_vlan_config(struct hns3_adapter *hns)
1053 struct hns3_hw *hw = &hns->hw;
1057 * When vlan filter is enabled, hardware regards packets without vlan
1058 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1059 * table, packets without vlan won't be received. So, add vlan 0 as
1062 ret = hns3_vlan_filter_configure(hns, 0, 1);
1064 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1069 hns3_init_vlan_config(struct hns3_adapter *hns)
1071 struct hns3_hw *hw = &hns->hw;
1075 * This function can be called in the initialization and reset process,
1076 * when in reset process, it means that hardware had been reseted
1077 * successfully and we need to restore the hardware configuration to
1078 * ensure that the hardware configuration remains unchanged before and
1081 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1082 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1083 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1086 ret = hns3_vlan_filter_init(hns);
1088 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1092 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1093 RTE_ETHER_TYPE_VLAN);
1095 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1100 * When in the reinit dev stage of the reset process, the following
1101 * vlan-related configurations may differ from those at initialization,
1102 * we will restore configurations to hardware in hns3_restore_vlan_table
1103 * and hns3_restore_vlan_conf later.
1105 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1106 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1108 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1112 ret = hns3_en_hw_strip_rxvtag(hns, false);
1114 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1120 return hns3_default_vlan_config(hns);
1124 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1126 struct hns3_pf *pf = &hns->pf;
1127 struct hns3_hw *hw = &hns->hw;
1132 if (!hw->data->promiscuous) {
1133 /* restore vlan filter states */
1134 offloads = hw->data->dev_conf.rxmode.offloads;
1135 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1136 ret = hns3_enable_vlan_filter(hns, enable);
1138 hns3_err(hw, "failed to restore vlan rx filter conf, "
1144 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1146 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1150 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1152 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1158 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1160 struct hns3_adapter *hns = dev->data->dev_private;
1161 struct rte_eth_dev_data *data = dev->data;
1162 struct rte_eth_txmode *txmode;
1163 struct hns3_hw *hw = &hns->hw;
1167 txmode = &data->dev_conf.txmode;
1168 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1170 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1171 "configuration is not supported! Ignore these two "
1172 "parameters: hw_vlan_reject_tagged(%u), "
1173 "hw_vlan_reject_untagged(%u)",
1174 txmode->hw_vlan_reject_tagged,
1175 txmode->hw_vlan_reject_untagged);
1177 /* Apply vlan offload setting */
1178 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1179 ret = hns3_vlan_offload_set(dev, mask);
1181 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1187 * If pvid config is not set in rte_eth_conf, driver needn't to set
1188 * VLAN pvid related configuration to hardware.
1190 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1193 /* Apply pvid setting */
1194 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1195 txmode->hw_vlan_insert_pvid);
1197 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1204 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1205 unsigned int tso_mss_max)
1207 struct hns3_cfg_tso_status_cmd *req;
1208 struct hns3_cmd_desc desc;
1211 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1213 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1216 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1218 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1221 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1223 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1225 return hns3_cmd_send(hw, &desc, 1);
1229 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1230 uint16_t *allocated_size, bool is_alloc)
1232 struct hns3_umv_spc_alc_cmd *req;
1233 struct hns3_cmd_desc desc;
1236 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1237 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1238 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1239 req->space_size = rte_cpu_to_le_32(space_size);
1241 ret = hns3_cmd_send(hw, &desc, 1);
1243 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1244 is_alloc ? "allocate" : "free", ret);
1248 if (is_alloc && allocated_size)
1249 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1255 hns3_init_umv_space(struct hns3_hw *hw)
1257 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1258 struct hns3_pf *pf = &hns->pf;
1259 uint16_t allocated_size = 0;
1262 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1267 if (allocated_size < pf->wanted_umv_size)
1268 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1269 pf->wanted_umv_size, allocated_size);
1271 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1272 pf->wanted_umv_size;
1273 pf->used_umv_size = 0;
1278 hns3_uninit_umv_space(struct hns3_hw *hw)
1280 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1281 struct hns3_pf *pf = &hns->pf;
1284 if (pf->max_umv_size == 0)
1287 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1291 pf->max_umv_size = 0;
1297 hns3_is_umv_space_full(struct hns3_hw *hw)
1299 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1300 struct hns3_pf *pf = &hns->pf;
1303 is_full = (pf->used_umv_size >= pf->max_umv_size);
1309 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1311 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1312 struct hns3_pf *pf = &hns->pf;
1315 if (pf->used_umv_size > 0)
1316 pf->used_umv_size--;
1318 pf->used_umv_size++;
1322 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1323 const uint8_t *addr, bool is_mc)
1325 const unsigned char *mac_addr = addr;
1326 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1327 ((uint32_t)mac_addr[2] << 16) |
1328 ((uint32_t)mac_addr[1] << 8) |
1329 (uint32_t)mac_addr[0];
1330 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1332 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1334 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1335 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1336 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1339 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1340 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1344 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1346 enum hns3_mac_vlan_tbl_opcode op)
1349 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1354 if (op == HNS3_MAC_VLAN_ADD) {
1355 if (resp_code == 0 || resp_code == 1) {
1357 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1358 hns3_err(hw, "add mac addr failed for uc_overflow");
1360 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1361 hns3_err(hw, "add mac addr failed for mc_overflow");
1365 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1368 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1369 if (resp_code == 0) {
1371 } else if (resp_code == 1) {
1372 hns3_dbg(hw, "remove mac addr failed for miss");
1376 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1379 } else if (op == HNS3_MAC_VLAN_LKUP) {
1380 if (resp_code == 0) {
1382 } else if (resp_code == 1) {
1383 hns3_dbg(hw, "lookup mac addr failed for miss");
1387 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1392 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1399 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1400 struct hns3_mac_vlan_tbl_entry_cmd *req,
1401 struct hns3_cmd_desc *desc, bool is_mc)
1407 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1409 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1410 memcpy(desc[0].data, req,
1411 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1412 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1414 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1415 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1417 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1419 memcpy(desc[0].data, req,
1420 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1421 ret = hns3_cmd_send(hw, desc, 1);
1424 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1428 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1429 retval = rte_le_to_cpu_16(desc[0].retval);
1431 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1432 HNS3_MAC_VLAN_LKUP);
1436 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1437 struct hns3_mac_vlan_tbl_entry_cmd *req,
1438 struct hns3_cmd_desc *mc_desc)
1445 if (mc_desc == NULL) {
1446 struct hns3_cmd_desc desc;
1448 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1449 memcpy(desc.data, req,
1450 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1451 ret = hns3_cmd_send(hw, &desc, 1);
1452 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1453 retval = rte_le_to_cpu_16(desc.retval);
1455 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1458 hns3_cmd_reuse_desc(&mc_desc[0], false);
1459 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1460 hns3_cmd_reuse_desc(&mc_desc[1], false);
1461 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1462 hns3_cmd_reuse_desc(&mc_desc[2], false);
1463 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1464 memcpy(mc_desc[0].data, req,
1465 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1466 mc_desc[0].retval = 0;
1467 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1468 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1469 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1471 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1476 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1484 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1485 struct hns3_mac_vlan_tbl_entry_cmd *req)
1487 struct hns3_cmd_desc desc;
1492 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1494 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1496 ret = hns3_cmd_send(hw, &desc, 1);
1498 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1501 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1502 retval = rte_le_to_cpu_16(desc.retval);
1504 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1505 HNS3_MAC_VLAN_REMOVE);
1509 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1511 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1512 struct hns3_mac_vlan_tbl_entry_cmd req;
1513 struct hns3_pf *pf = &hns->pf;
1514 struct hns3_cmd_desc desc[3];
1515 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1516 uint16_t egress_port = 0;
1520 /* check if mac addr is valid */
1521 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1522 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1524 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1529 memset(&req, 0, sizeof(req));
1532 * In current version VF is not supported when PF is driven by DPDK
1533 * driver, just need to configure parameters for PF vport.
1535 vf_id = HNS3_PF_FUNC_ID;
1536 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1537 HNS3_MAC_EPORT_VFID_S, vf_id);
1539 req.egress_port = rte_cpu_to_le_16(egress_port);
1541 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1544 * Lookup the mac address in the mac_vlan table, and add
1545 * it if the entry is inexistent. Repeated unicast entry
1546 * is not allowed in the mac vlan table.
1548 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1549 if (ret == -ENOENT) {
1550 if (!hns3_is_umv_space_full(hw)) {
1551 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1553 hns3_update_umv_space(hw, false);
1557 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1562 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1564 /* check if we just hit the duplicate */
1566 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1570 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1577 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1579 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1580 struct rte_ether_addr *addr;
1584 for (i = 0; i < hw->mc_addrs_num; i++) {
1585 addr = &hw->mc_addrs[i];
1586 /* Check if there are duplicate addresses */
1587 if (rte_is_same_ether_addr(addr, mac_addr)) {
1588 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1590 hns3_err(hw, "failed to add mc mac addr, same addrs"
1591 "(%s) is added by the set_mc_mac_addr_list "
1597 ret = hns3_add_mc_addr(hw, mac_addr);
1599 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1601 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1608 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1610 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1613 ret = hns3_remove_mc_addr(hw, mac_addr);
1615 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1617 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1624 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1625 uint32_t idx, __rte_unused uint32_t pool)
1627 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1628 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1631 rte_spinlock_lock(&hw->lock);
1634 * In hns3 network engine adding UC and MC mac address with different
1635 * commands with firmware. We need to determine whether the input
1636 * address is a UC or a MC address to call different commands.
1637 * By the way, it is recommended calling the API function named
1638 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1639 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1640 * may affect the specifications of UC mac addresses.
1642 if (rte_is_multicast_ether_addr(mac_addr))
1643 ret = hns3_add_mc_addr_common(hw, mac_addr);
1645 ret = hns3_add_uc_addr_common(hw, mac_addr);
1648 rte_spinlock_unlock(&hw->lock);
1649 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1651 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1657 hw->mac.default_addr_setted = true;
1658 rte_spinlock_unlock(&hw->lock);
1664 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1666 struct hns3_mac_vlan_tbl_entry_cmd req;
1667 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1670 /* check if mac addr is valid */
1671 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1672 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1674 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1679 memset(&req, 0, sizeof(req));
1680 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1681 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1682 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1683 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1686 hns3_update_umv_space(hw, true);
1692 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1694 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1695 /* index will be checked by upper level rte interface */
1696 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1697 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1700 rte_spinlock_lock(&hw->lock);
1702 if (rte_is_multicast_ether_addr(mac_addr))
1703 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1705 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1706 rte_spinlock_unlock(&hw->lock);
1708 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1710 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1716 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1717 struct rte_ether_addr *mac_addr)
1719 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1720 struct rte_ether_addr *oaddr;
1721 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1722 bool default_addr_setted;
1723 bool rm_succes = false;
1727 * It has been guaranteed that input parameter named mac_addr is valid
1728 * address in the rte layer of DPDK framework.
1730 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1731 default_addr_setted = hw->mac.default_addr_setted;
1732 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1735 rte_spinlock_lock(&hw->lock);
1736 if (default_addr_setted) {
1737 ret = hns3_remove_uc_addr_common(hw, oaddr);
1739 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1741 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1748 ret = hns3_add_uc_addr_common(hw, mac_addr);
1750 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1752 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1753 goto err_add_uc_addr;
1756 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1758 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1759 goto err_pause_addr_cfg;
1762 rte_ether_addr_copy(mac_addr,
1763 (struct rte_ether_addr *)hw->mac.mac_addr);
1764 hw->mac.default_addr_setted = true;
1765 rte_spinlock_unlock(&hw->lock);
1770 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1772 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1775 "Failed to roll back to del setted mac addr(%s): %d",
1781 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1783 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1786 "Failed to restore old uc mac addr(%s): %d",
1788 hw->mac.default_addr_setted = false;
1791 rte_spinlock_unlock(&hw->lock);
1797 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1799 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1800 struct hns3_hw *hw = &hns->hw;
1801 struct rte_ether_addr *addr;
1806 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1807 addr = &hw->data->mac_addrs[i];
1808 if (rte_is_zero_ether_addr(addr))
1810 if (rte_is_multicast_ether_addr(addr))
1811 ret = del ? hns3_remove_mc_addr(hw, addr) :
1812 hns3_add_mc_addr(hw, addr);
1814 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1815 hns3_add_uc_addr_common(hw, addr);
1819 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1821 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1822 "ret = %d.", del ? "remove" : "restore",
1830 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1832 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1836 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1837 word_num = vfid / 32;
1838 bit_num = vfid % 32;
1840 desc[1].data[word_num] &=
1841 rte_cpu_to_le_32(~(1UL << bit_num));
1843 desc[1].data[word_num] |=
1844 rte_cpu_to_le_32(1UL << bit_num);
1846 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1847 bit_num = vfid % 32;
1849 desc[2].data[word_num] &=
1850 rte_cpu_to_le_32(~(1UL << bit_num));
1852 desc[2].data[word_num] |=
1853 rte_cpu_to_le_32(1UL << bit_num);
1858 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1860 struct hns3_mac_vlan_tbl_entry_cmd req;
1861 struct hns3_cmd_desc desc[3];
1862 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1866 /* Check if mac addr is valid */
1867 if (!rte_is_multicast_ether_addr(mac_addr)) {
1868 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1870 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1875 memset(&req, 0, sizeof(req));
1876 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1877 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1878 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1880 /* This mac addr do not exist, add new entry for it */
1881 memset(desc[0].data, 0, sizeof(desc[0].data));
1882 memset(desc[1].data, 0, sizeof(desc[0].data));
1883 memset(desc[2].data, 0, sizeof(desc[0].data));
1887 * In current version VF is not supported when PF is driven by DPDK
1888 * driver, just need to configure parameters for PF vport.
1890 vf_id = HNS3_PF_FUNC_ID;
1891 hns3_update_desc_vfid(desc, vf_id, false);
1892 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1895 hns3_err(hw, "mc mac vlan table is full");
1896 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1898 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1905 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1907 struct hns3_mac_vlan_tbl_entry_cmd req;
1908 struct hns3_cmd_desc desc[3];
1909 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1913 /* Check if mac addr is valid */
1914 if (!rte_is_multicast_ether_addr(mac_addr)) {
1915 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1917 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1922 memset(&req, 0, sizeof(req));
1923 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1924 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1925 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1928 * This mac addr exist, remove this handle's VFID for it.
1929 * In current version VF is not supported when PF is driven by
1930 * DPDK driver, just need to configure parameters for PF vport.
1932 vf_id = HNS3_PF_FUNC_ID;
1933 hns3_update_desc_vfid(desc, vf_id, true);
1935 /* All the vfid is zero, so need to delete this entry */
1936 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1937 } else if (ret == -ENOENT) {
1938 /* This mac addr doesn't exist. */
1943 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1945 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1952 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1953 struct rte_ether_addr *mc_addr_set,
1954 uint32_t nb_mc_addr)
1956 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1957 struct rte_ether_addr *addr;
1961 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1962 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1963 "invalid. valid range: 0~%d",
1964 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1968 /* Check if input mac addresses are valid */
1969 for (i = 0; i < nb_mc_addr; i++) {
1970 addr = &mc_addr_set[i];
1971 if (!rte_is_multicast_ether_addr(addr)) {
1972 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1975 "failed to set mc mac addr, addr(%s) invalid.",
1980 /* Check if there are duplicate addresses */
1981 for (j = i + 1; j < nb_mc_addr; j++) {
1982 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1983 hns3_ether_format_addr(mac_str,
1984 RTE_ETHER_ADDR_FMT_SIZE,
1986 hns3_err(hw, "failed to set mc mac addr, "
1987 "addrs invalid. two same addrs(%s).",
1994 * Check if there are duplicate addresses between mac_addrs
1997 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1998 if (rte_is_same_ether_addr(addr,
1999 &hw->data->mac_addrs[j])) {
2000 hns3_ether_format_addr(mac_str,
2001 RTE_ETHER_ADDR_FMT_SIZE,
2003 hns3_err(hw, "failed to set mc mac addr, "
2004 "addrs invalid. addrs(%s) has already "
2005 "configured in mac_addr add API",
2016 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2017 struct rte_ether_addr *mc_addr_set,
2019 struct rte_ether_addr *reserved_addr_list,
2020 int *reserved_addr_num,
2021 struct rte_ether_addr *add_addr_list,
2023 struct rte_ether_addr *rm_addr_list,
2026 struct rte_ether_addr *addr;
2027 int current_addr_num;
2028 int reserved_num = 0;
2036 /* Calculate the mc mac address list that should be removed */
2037 current_addr_num = hw->mc_addrs_num;
2038 for (i = 0; i < current_addr_num; i++) {
2039 addr = &hw->mc_addrs[i];
2041 for (j = 0; j < mc_addr_num; j++) {
2042 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2049 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2052 rte_ether_addr_copy(addr,
2053 &reserved_addr_list[reserved_num]);
2058 /* Calculate the mc mac address list that should be added */
2059 for (i = 0; i < mc_addr_num; i++) {
2060 addr = &mc_addr_set[i];
2062 for (j = 0; j < current_addr_num; j++) {
2063 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2070 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2075 /* Reorder the mc mac address list maintained by driver */
2076 for (i = 0; i < reserved_num; i++)
2077 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2079 for (i = 0; i < rm_num; i++) {
2080 num = reserved_num + i;
2081 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2084 *reserved_addr_num = reserved_num;
2085 *add_addr_num = add_num;
2086 *rm_addr_num = rm_num;
2090 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2091 struct rte_ether_addr *mc_addr_set,
2092 uint32_t nb_mc_addr)
2094 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2096 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2097 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2098 struct rte_ether_addr *addr;
2099 int reserved_addr_num;
2107 /* Check if input parameters are valid */
2108 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2112 rte_spinlock_lock(&hw->lock);
2115 * Calculate the mc mac address lists those should be removed and be
2116 * added, Reorder the mc mac address list maintained by driver.
2118 mc_addr_num = (int)nb_mc_addr;
2119 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2120 reserved_addr_list, &reserved_addr_num,
2121 add_addr_list, &add_addr_num,
2122 rm_addr_list, &rm_addr_num);
2124 /* Remove mc mac addresses */
2125 for (i = 0; i < rm_addr_num; i++) {
2126 num = rm_addr_num - i - 1;
2127 addr = &rm_addr_list[num];
2128 ret = hns3_remove_mc_addr(hw, addr);
2130 rte_spinlock_unlock(&hw->lock);
2136 /* Add mc mac addresses */
2137 for (i = 0; i < add_addr_num; i++) {
2138 addr = &add_addr_list[i];
2139 ret = hns3_add_mc_addr(hw, addr);
2141 rte_spinlock_unlock(&hw->lock);
2145 num = reserved_addr_num + i;
2146 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2149 rte_spinlock_unlock(&hw->lock);
2155 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2157 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2158 struct hns3_hw *hw = &hns->hw;
2159 struct rte_ether_addr *addr;
2164 for (i = 0; i < hw->mc_addrs_num; i++) {
2165 addr = &hw->mc_addrs[i];
2166 if (!rte_is_multicast_ether_addr(addr))
2169 ret = hns3_remove_mc_addr(hw, addr);
2171 ret = hns3_add_mc_addr(hw, addr);
2174 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2176 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2177 del ? "Remove" : "Restore", mac_str, ret);
2184 hns3_check_mq_mode(struct rte_eth_dev *dev)
2186 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2187 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2188 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2189 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2190 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2191 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2196 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2197 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2199 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2200 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2201 "rx_mq_mode = %d", rx_mq_mode);
2205 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2206 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2207 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2208 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2209 rx_mq_mode, tx_mq_mode);
2213 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2214 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2215 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2216 dcb_rx_conf->nb_tcs, pf->tc_max);
2220 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2221 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2222 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2223 "nb_tcs(%d) != %d or %d in rx direction.",
2224 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2228 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2229 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2230 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2234 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2235 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2236 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2237 "is not equal to one in tx direction.",
2238 i, dcb_rx_conf->dcb_tc[i]);
2241 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2242 max_tc = dcb_rx_conf->dcb_tc[i];
2245 num_tc = max_tc + 1;
2246 if (num_tc > dcb_rx_conf->nb_tcs) {
2247 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2248 num_tc, dcb_rx_conf->nb_tcs);
2257 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2259 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2261 if (!hns3_dev_dcb_supported(hw)) {
2262 hns3_err(hw, "this port does not support dcb configurations.");
2266 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2267 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2271 /* Check multiple queue mode */
2272 return hns3_check_mq_mode(dev);
2276 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2277 enum hns3_ring_type queue_type, uint16_t queue_id)
2279 struct hns3_cmd_desc desc;
2280 struct hns3_ctrl_vector_chain_cmd *req =
2281 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2282 enum hns3_cmd_status status;
2283 enum hns3_opcode_type op;
2284 uint16_t tqp_type_and_id = 0;
2288 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2289 hns3_cmd_setup_basic_desc(&desc, op, false);
2290 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2291 HNS3_TQP_INT_ID_L_S);
2292 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2293 HNS3_TQP_INT_ID_H_S);
2295 if (queue_type == HNS3_RING_TYPE_RX)
2296 gl = HNS3_RING_GL_RX;
2298 gl = HNS3_RING_GL_TX;
2302 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2304 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2305 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2307 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2308 req->int_cause_num = 1;
2309 status = hns3_cmd_send(hw, &desc, 1);
2311 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2312 en ? "Map" : "Unmap", queue_id, vector_id, status);
2320 hns3_init_ring_with_vector(struct hns3_hw *hw)
2327 * In hns3 network engine, vector 0 is always the misc interrupt of this
2328 * function, vector 1~N can be used respectively for the queues of the
2329 * function. Tx and Rx queues with the same number share the interrupt
2330 * vector. In the initialization clearing the all hardware mapping
2331 * relationship configurations between queues and interrupt vectors is
2332 * needed, so some error caused by the residual configurations, such as
2333 * the unexpected Tx interrupt, can be avoid.
2335 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2336 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2337 vec = vec - 1; /* the last interrupt is reserved */
2338 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2339 for (i = 0; i < hw->intr_tqps_num; i++) {
2341 * Set gap limiter/rate limiter/quanity limiter algorithm
2342 * configuration for interrupt coalesce of queue's interrupt.
2344 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2345 HNS3_TQP_INTR_GL_DEFAULT);
2346 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2347 HNS3_TQP_INTR_GL_DEFAULT);
2348 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2350 * QL(quantity limiter) is not used currently, just set 0 to
2353 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2355 ret = hns3_bind_ring_with_vector(hw, vec, false,
2356 HNS3_RING_TYPE_TX, i);
2358 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2359 "vector: %u, ret=%d", i, vec, ret);
2363 ret = hns3_bind_ring_with_vector(hw, vec, false,
2364 HNS3_RING_TYPE_RX, i);
2366 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2367 "vector: %u, ret=%d", i, vec, ret);
2376 hns3_dev_configure(struct rte_eth_dev *dev)
2378 struct hns3_adapter *hns = dev->data->dev_private;
2379 struct rte_eth_conf *conf = &dev->data->dev_conf;
2380 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2381 struct hns3_hw *hw = &hns->hw;
2382 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2383 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2384 struct rte_eth_rss_conf rss_conf;
2385 uint32_t max_rx_pkt_len;
2390 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2393 * Some versions of hardware network engine does not support
2394 * individually enable/disable/reset the Tx or Rx queue. These devices
2395 * must enable/disable/reset Tx and Rx queues at the same time. When the
2396 * numbers of Tx queues allocated by upper applications are not equal to
2397 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2398 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2399 * work as usual. But these fake queues are imperceptible, and can not
2400 * be used by upper applications.
2402 if (!hns3_dev_indep_txrx_supported(hw)) {
2403 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2405 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2411 hw->adapter_state = HNS3_NIC_CONFIGURING;
2412 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2413 hns3_err(hw, "setting link speed/duplex not supported");
2418 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2419 ret = hns3_check_dcb_cfg(dev);
2424 /* When RSS is not configured, redirect the packet queue 0 */
2425 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2426 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2427 rss_conf = conf->rx_adv_conf.rss_conf;
2428 hw->rss_dis_flag = false;
2429 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2435 * If jumbo frames are enabled, MTU needs to be refreshed
2436 * according to the maximum RX packet length.
2438 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2439 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2440 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2441 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2442 hns3_err(hw, "maximum Rx packet length must be greater "
2443 "than %u and less than %u when jumbo frame enabled.",
2444 (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2445 (uint16_t)HNS3_MAX_FRAME_LEN);
2450 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2451 ret = hns3_dev_mtu_set(dev, mtu);
2454 dev->data->mtu = mtu;
2457 ret = hns3_dev_configure_vlan(dev);
2461 /* config hardware GRO */
2462 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2463 ret = hns3_config_gro(hw, gro_en);
2467 hns->rx_simple_allowed = true;
2468 hns->rx_vec_allowed = true;
2469 hns->tx_simple_allowed = true;
2470 hns->tx_vec_allowed = true;
2472 hns3_init_rx_ptype_tble(dev);
2473 hw->adapter_state = HNS3_NIC_CONFIGURED;
2478 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2479 hw->adapter_state = HNS3_NIC_INITIALIZED;
2485 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2487 struct hns3_config_max_frm_size_cmd *req;
2488 struct hns3_cmd_desc desc;
2490 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2492 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2493 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2494 req->min_frm_size = RTE_ETHER_MIN_LEN;
2496 return hns3_cmd_send(hw, &desc, 1);
2500 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2502 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2503 uint16_t original_mps = hns->pf.mps;
2507 ret = hns3_set_mac_mtu(hw, mps);
2509 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2514 ret = hns3_buffer_alloc(hw);
2516 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2523 err = hns3_set_mac_mtu(hw, original_mps);
2525 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2528 hns->pf.mps = original_mps;
2534 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2536 struct hns3_adapter *hns = dev->data->dev_private;
2537 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2538 struct hns3_hw *hw = &hns->hw;
2539 bool is_jumbo_frame;
2542 if (dev->data->dev_started) {
2543 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2544 "before configuration", dev->data->port_id);
2548 rte_spinlock_lock(&hw->lock);
2549 is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2550 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2553 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2554 * assign to "uint16_t" type variable.
2556 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2558 rte_spinlock_unlock(&hw->lock);
2559 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2560 dev->data->port_id, mtu, ret);
2565 dev->data->dev_conf.rxmode.offloads |=
2566 DEV_RX_OFFLOAD_JUMBO_FRAME;
2568 dev->data->dev_conf.rxmode.offloads &=
2569 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2570 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2571 rte_spinlock_unlock(&hw->lock);
2577 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2579 struct hns3_adapter *hns = eth_dev->data->dev_private;
2580 struct hns3_hw *hw = &hns->hw;
2581 uint16_t queue_num = hw->tqps_num;
2584 * In interrupt mode, 'max_rx_queues' is set based on the number of
2585 * MSI-X interrupt resources of the hardware.
2587 if (hw->data->dev_conf.intr_conf.rxq == 1)
2588 queue_num = hw->intr_tqps_num;
2590 info->max_rx_queues = queue_num;
2591 info->max_tx_queues = hw->tqps_num;
2592 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2593 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2594 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2595 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2596 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2597 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2598 DEV_RX_OFFLOAD_TCP_CKSUM |
2599 DEV_RX_OFFLOAD_UDP_CKSUM |
2600 DEV_RX_OFFLOAD_SCTP_CKSUM |
2601 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2602 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2603 DEV_RX_OFFLOAD_KEEP_CRC |
2604 DEV_RX_OFFLOAD_SCATTER |
2605 DEV_RX_OFFLOAD_VLAN_STRIP |
2606 DEV_RX_OFFLOAD_VLAN_FILTER |
2607 DEV_RX_OFFLOAD_JUMBO_FRAME |
2608 DEV_RX_OFFLOAD_RSS_HASH |
2609 DEV_RX_OFFLOAD_TCP_LRO);
2610 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2611 DEV_TX_OFFLOAD_IPV4_CKSUM |
2612 DEV_TX_OFFLOAD_TCP_CKSUM |
2613 DEV_TX_OFFLOAD_UDP_CKSUM |
2614 DEV_TX_OFFLOAD_SCTP_CKSUM |
2615 DEV_TX_OFFLOAD_MULTI_SEGS |
2616 DEV_TX_OFFLOAD_TCP_TSO |
2617 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2618 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2619 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2620 DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2621 hns3_txvlan_cap_get(hw));
2623 if (hns3_dev_outer_udp_cksum_supported(hw))
2624 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2626 if (hns3_dev_indep_txrx_supported(hw))
2627 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2628 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2630 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2631 .nb_max = HNS3_MAX_RING_DESC,
2632 .nb_min = HNS3_MIN_RING_DESC,
2633 .nb_align = HNS3_ALIGN_RING_DESC,
2636 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2637 .nb_max = HNS3_MAX_RING_DESC,
2638 .nb_min = HNS3_MIN_RING_DESC,
2639 .nb_align = HNS3_ALIGN_RING_DESC,
2640 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2641 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2644 info->default_rxconf = (struct rte_eth_rxconf) {
2645 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2647 * If there are no available Rx buffer descriptors, incoming
2648 * packets are always dropped by hardware based on hns3 network
2654 info->default_txconf = (struct rte_eth_txconf) {
2655 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2659 info->vmdq_queue_num = 0;
2661 info->reta_size = hw->rss_ind_tbl_size;
2662 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2663 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2665 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2666 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2667 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2668 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2669 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2670 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2676 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2679 struct hns3_adapter *hns = eth_dev->data->dev_private;
2680 struct hns3_hw *hw = &hns->hw;
2681 uint32_t version = hw->fw_version;
2684 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2685 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2686 HNS3_FW_VERSION_BYTE3_S),
2687 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2688 HNS3_FW_VERSION_BYTE2_S),
2689 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2690 HNS3_FW_VERSION_BYTE1_S),
2691 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2692 HNS3_FW_VERSION_BYTE0_S));
2693 ret += 1; /* add the size of '\0' */
2694 if (fw_size < (uint32_t)ret)
2701 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2702 __rte_unused int wait_to_complete)
2704 struct hns3_adapter *hns = eth_dev->data->dev_private;
2705 struct hns3_hw *hw = &hns->hw;
2706 struct hns3_mac *mac = &hw->mac;
2707 struct rte_eth_link new_link;
2709 if (!hns3_is_reset_pending(hns)) {
2710 hns3_update_link_status(hw);
2711 hns3_update_link_info(eth_dev);
2714 memset(&new_link, 0, sizeof(new_link));
2715 switch (mac->link_speed) {
2716 case ETH_SPEED_NUM_10M:
2717 case ETH_SPEED_NUM_100M:
2718 case ETH_SPEED_NUM_1G:
2719 case ETH_SPEED_NUM_10G:
2720 case ETH_SPEED_NUM_25G:
2721 case ETH_SPEED_NUM_40G:
2722 case ETH_SPEED_NUM_50G:
2723 case ETH_SPEED_NUM_100G:
2724 case ETH_SPEED_NUM_200G:
2725 new_link.link_speed = mac->link_speed;
2728 if (mac->link_status)
2729 new_link.link_speed = ETH_SPEED_NUM_UNKNOWN;
2731 new_link.link_speed = ETH_SPEED_NUM_NONE;
2735 new_link.link_duplex = mac->link_duplex;
2736 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2737 new_link.link_autoneg =
2738 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2740 return rte_eth_linkstatus_set(eth_dev, &new_link);
2744 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2746 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2747 struct hns3_pf *pf = &hns->pf;
2749 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2752 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2758 hns3_query_function_status(struct hns3_hw *hw)
2760 #define HNS3_QUERY_MAX_CNT 10
2761 #define HNS3_QUERY_SLEEP_MSCOEND 1
2762 struct hns3_func_status_cmd *req;
2763 struct hns3_cmd_desc desc;
2767 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2768 req = (struct hns3_func_status_cmd *)desc.data;
2771 ret = hns3_cmd_send(hw, &desc, 1);
2773 PMD_INIT_LOG(ERR, "query function status failed %d",
2778 /* Check pf reset is done */
2782 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2783 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2785 return hns3_parse_func_status(hw, req);
2789 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2791 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2792 struct hns3_pf *pf = &hns->pf;
2794 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2796 * The total_tqps_num obtained from firmware is maximum tqp
2797 * numbers of this port, which should be used for PF and VFs.
2798 * There is no need for pf to have so many tqp numbers in
2799 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2800 * coming from config file, is assigned to maximum queue number
2801 * for the PF of this port by user. So users can modify the
2802 * maximum queue number of PF according to their own application
2803 * scenarios, which is more flexible to use. In addition, many
2804 * memories can be saved due to allocating queue statistics
2805 * room according to the actual number of queues required. The
2806 * maximum queue number of PF for network engine with
2807 * revision_id greater than 0x30 is assigned by config file.
2809 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2810 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2811 "must be greater than 0.",
2812 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2816 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2817 hw->total_tqps_num);
2820 * Due to the limitation on the number of PF interrupts
2821 * available, the maximum queue number assigned to PF on
2822 * the network engine with revision_id 0x21 is 64.
2824 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2825 HNS3_MAX_TQP_NUM_HIP08_PF);
2832 hns3_query_pf_resource(struct hns3_hw *hw)
2834 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2835 struct hns3_pf *pf = &hns->pf;
2836 struct hns3_pf_res_cmd *req;
2837 struct hns3_cmd_desc desc;
2840 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2841 ret = hns3_cmd_send(hw, &desc, 1);
2843 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2847 req = (struct hns3_pf_res_cmd *)desc.data;
2848 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2849 rte_le_to_cpu_16(req->ext_tqp_num);
2850 ret = hns3_get_pf_max_tqp_num(hw);
2854 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2855 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2857 if (req->tx_buf_size)
2859 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2861 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2863 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2865 if (req->dv_buf_size)
2867 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2869 pf->dv_buf_size = HNS3_DEFAULT_DV;
2871 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2874 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2875 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2881 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2883 struct hns3_cfg_param_cmd *req;
2884 uint64_t mac_addr_tmp_high;
2885 uint8_t ext_rss_size_max;
2886 uint64_t mac_addr_tmp;
2889 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2891 /* get the configuration */
2892 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2893 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2894 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2895 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2896 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2897 HNS3_CFG_TQP_DESC_N_M,
2898 HNS3_CFG_TQP_DESC_N_S);
2900 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2901 HNS3_CFG_PHY_ADDR_M,
2902 HNS3_CFG_PHY_ADDR_S);
2903 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2904 HNS3_CFG_MEDIA_TP_M,
2905 HNS3_CFG_MEDIA_TP_S);
2906 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2907 HNS3_CFG_RX_BUF_LEN_M,
2908 HNS3_CFG_RX_BUF_LEN_S);
2909 /* get mac address */
2910 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2911 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2912 HNS3_CFG_MAC_ADDR_H_M,
2913 HNS3_CFG_MAC_ADDR_H_S);
2915 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2917 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2918 HNS3_CFG_DEFAULT_SPEED_M,
2919 HNS3_CFG_DEFAULT_SPEED_S);
2920 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2921 HNS3_CFG_RSS_SIZE_M,
2922 HNS3_CFG_RSS_SIZE_S);
2924 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2925 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2927 req = (struct hns3_cfg_param_cmd *)desc[1].data;
2928 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2930 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2931 HNS3_CFG_SPEED_ABILITY_M,
2932 HNS3_CFG_SPEED_ABILITY_S);
2933 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2934 HNS3_CFG_UMV_TBL_SPACE_M,
2935 HNS3_CFG_UMV_TBL_SPACE_S);
2936 if (!cfg->umv_space)
2937 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2939 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2940 HNS3_CFG_EXT_RSS_SIZE_M,
2941 HNS3_CFG_EXT_RSS_SIZE_S);
2944 * Field ext_rss_size_max obtained from firmware will be more flexible
2945 * for future changes and expansions, which is an exponent of 2, instead
2946 * of reading out directly. If this field is not zero, hns3 PF PMD
2947 * driver uses it as rss_size_max under one TC. Device, whose revision
2948 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2949 * maximum number of queues supported under a TC through this field.
2951 if (ext_rss_size_max)
2952 cfg->rss_size_max = 1U << ext_rss_size_max;
2955 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2956 * @hw: pointer to struct hns3_hw
2957 * @hcfg: the config structure to be getted
2960 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2962 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2963 struct hns3_cfg_param_cmd *req;
2968 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2970 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2971 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2973 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2974 i * HNS3_CFG_RD_LEN_BYTES);
2975 /* Len should be divided by 4 when send to hardware */
2976 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2977 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2978 req->offset = rte_cpu_to_le_32(offset);
2981 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2983 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2987 hns3_parse_cfg(hcfg, desc);
2993 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2995 switch (speed_cmd) {
2996 case HNS3_CFG_SPEED_10M:
2997 *speed = ETH_SPEED_NUM_10M;
2999 case HNS3_CFG_SPEED_100M:
3000 *speed = ETH_SPEED_NUM_100M;
3002 case HNS3_CFG_SPEED_1G:
3003 *speed = ETH_SPEED_NUM_1G;
3005 case HNS3_CFG_SPEED_10G:
3006 *speed = ETH_SPEED_NUM_10G;
3008 case HNS3_CFG_SPEED_25G:
3009 *speed = ETH_SPEED_NUM_25G;
3011 case HNS3_CFG_SPEED_40G:
3012 *speed = ETH_SPEED_NUM_40G;
3014 case HNS3_CFG_SPEED_50G:
3015 *speed = ETH_SPEED_NUM_50G;
3017 case HNS3_CFG_SPEED_100G:
3018 *speed = ETH_SPEED_NUM_100G;
3020 case HNS3_CFG_SPEED_200G:
3021 *speed = ETH_SPEED_NUM_200G;
3031 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3033 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3034 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3035 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3036 hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3037 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3041 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3043 struct hns3_dev_specs_0_cmd *req0;
3045 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3047 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3048 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3049 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3050 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3051 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3055 hns3_check_dev_specifications(struct hns3_hw *hw)
3057 if (hw->rss_ind_tbl_size == 0 ||
3058 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3059 hns3_err(hw, "the size of hash lookup table configured (%u)"
3060 " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3061 HNS3_RSS_IND_TBL_SIZE_MAX);
3069 hns3_query_dev_specifications(struct hns3_hw *hw)
3071 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3075 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3076 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3078 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3080 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3082 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3086 hns3_parse_dev_specifications(hw, desc);
3088 return hns3_check_dev_specifications(hw);
3092 hns3_get_capability(struct hns3_hw *hw)
3094 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3095 struct rte_pci_device *pci_dev;
3096 struct hns3_pf *pf = &hns->pf;
3097 struct rte_eth_dev *eth_dev;
3102 eth_dev = &rte_eth_devices[hw->data->port_id];
3103 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3104 device_id = pci_dev->id.device_id;
3106 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3107 device_id == HNS3_DEV_ID_50GE_RDMA ||
3108 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3109 device_id == HNS3_DEV_ID_200G_RDMA)
3110 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3112 /* Get PCI revision id */
3113 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3114 HNS3_PCI_REVISION_ID);
3115 if (ret != HNS3_PCI_REVISION_ID_LEN) {
3116 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3120 hw->revision = revision;
3122 if (revision < PCI_REVISION_ID_HIP09_A) {
3123 hns3_set_default_dev_specifications(hw);
3124 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3125 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3126 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3127 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3128 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3129 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3130 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3131 hw->rss_info.ipv6_sctp_offload_supported = false;
3132 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3136 ret = hns3_query_dev_specifications(hw);
3139 "failed to query dev specifications, ret = %d",
3144 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3145 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3146 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3147 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3148 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3149 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3150 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3151 hw->rss_info.ipv6_sctp_offload_supported = true;
3152 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3158 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3162 switch (media_type) {
3163 case HNS3_MEDIA_TYPE_COPPER:
3164 if (!hns3_dev_copper_supported(hw)) {
3166 "Media type is copper, not supported.");
3172 case HNS3_MEDIA_TYPE_FIBER:
3175 case HNS3_MEDIA_TYPE_BACKPLANE:
3176 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3180 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3189 hns3_get_board_configuration(struct hns3_hw *hw)
3191 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3192 struct hns3_pf *pf = &hns->pf;
3193 struct hns3_cfg cfg;
3196 ret = hns3_get_board_cfg(hw, &cfg);
3198 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3202 ret = hns3_check_media_type(hw, cfg.media_type);
3206 hw->mac.media_type = cfg.media_type;
3207 hw->rss_size_max = cfg.rss_size_max;
3208 hw->rss_dis_flag = false;
3209 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3210 hw->mac.phy_addr = cfg.phy_addr;
3211 hw->mac.default_addr_setted = false;
3212 hw->num_tx_desc = cfg.tqp_desc_num;
3213 hw->num_rx_desc = cfg.tqp_desc_num;
3214 hw->dcb_info.num_pg = 1;
3215 hw->dcb_info.hw_pfc_map = 0;
3217 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3219 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3220 cfg.default_speed, ret);
3224 pf->tc_max = cfg.tc_num;
3225 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3226 PMD_INIT_LOG(WARNING,
3227 "Get TC num(%u) from flash, set TC num to 1",
3232 /* Dev does not support DCB */
3233 if (!hns3_dev_dcb_supported(hw)) {
3237 pf->pfc_max = pf->tc_max;
3239 hw->dcb_info.num_tc = 1;
3240 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3241 hw->tqps_num / hw->dcb_info.num_tc);
3242 hns3_set_bit(hw->hw_tc_map, 0, 1);
3243 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3245 pf->wanted_umv_size = cfg.umv_space;
3251 hns3_get_configuration(struct hns3_hw *hw)
3255 ret = hns3_query_function_status(hw);
3257 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3261 /* Get device capability */
3262 ret = hns3_get_capability(hw);
3264 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3268 /* Get pf resource */
3269 ret = hns3_query_pf_resource(hw);
3271 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3275 ret = hns3_get_board_configuration(hw);
3277 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3281 ret = hns3_query_dev_fec_info(hw);
3284 "failed to query FEC information, ret = %d", ret);
3290 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3291 uint16_t tqp_vid, bool is_pf)
3293 struct hns3_tqp_map_cmd *req;
3294 struct hns3_cmd_desc desc;
3297 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3299 req = (struct hns3_tqp_map_cmd *)desc.data;
3300 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3301 req->tqp_vf = func_id;
3302 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3304 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3305 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3307 ret = hns3_cmd_send(hw, &desc, 1);
3309 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3315 hns3_map_tqp(struct hns3_hw *hw)
3321 * In current version, VF is not supported when PF is driven by DPDK
3322 * driver, so we assign total tqps_num tqps allocated to this port
3325 for (i = 0; i < hw->total_tqps_num; i++) {
3326 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3335 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3337 struct hns3_config_mac_speed_dup_cmd *req;
3338 struct hns3_cmd_desc desc;
3341 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3343 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3345 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3348 case ETH_SPEED_NUM_10M:
3349 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3350 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3352 case ETH_SPEED_NUM_100M:
3353 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3354 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3356 case ETH_SPEED_NUM_1G:
3357 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3358 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3360 case ETH_SPEED_NUM_10G:
3361 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3362 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3364 case ETH_SPEED_NUM_25G:
3365 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3366 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3368 case ETH_SPEED_NUM_40G:
3369 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3370 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3372 case ETH_SPEED_NUM_50G:
3373 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3374 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3376 case ETH_SPEED_NUM_100G:
3377 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3378 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3380 case ETH_SPEED_NUM_200G:
3381 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3382 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3385 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3389 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3391 ret = hns3_cmd_send(hw, &desc, 1);
3393 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3399 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3401 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3402 struct hns3_pf *pf = &hns->pf;
3403 struct hns3_priv_buf *priv;
3404 uint32_t i, total_size;
3406 total_size = pf->pkt_buf_size;
3408 /* alloc tx buffer for all enabled tc */
3409 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3410 priv = &buf_alloc->priv_buf[i];
3412 if (hw->hw_tc_map & BIT(i)) {
3413 if (total_size < pf->tx_buf_size)
3416 priv->tx_buf_size = pf->tx_buf_size;
3418 priv->tx_buf_size = 0;
3420 total_size -= priv->tx_buf_size;
3427 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3429 /* TX buffer size is unit by 128 byte */
3430 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3431 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3432 struct hns3_tx_buff_alloc_cmd *req;
3433 struct hns3_cmd_desc desc;
3438 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3440 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3441 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3442 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3444 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3445 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3446 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3449 ret = hns3_cmd_send(hw, &desc, 1);
3451 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3457 hns3_get_tc_num(struct hns3_hw *hw)
3462 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3463 if (hw->hw_tc_map & BIT(i))
3469 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3471 struct hns3_priv_buf *priv;
3472 uint32_t rx_priv = 0;
3475 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3476 priv = &buf_alloc->priv_buf[i];
3478 rx_priv += priv->buf_size;
3484 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3486 uint32_t total_tx_size = 0;
3489 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3490 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3492 return total_tx_size;
3495 /* Get the number of pfc enabled TCs, which have private buffer */
3497 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3499 struct hns3_priv_buf *priv;
3503 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3504 priv = &buf_alloc->priv_buf[i];
3505 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3512 /* Get the number of pfc disabled TCs, which have private buffer */
3514 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3515 struct hns3_pkt_buf_alloc *buf_alloc)
3517 struct hns3_priv_buf *priv;
3521 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3522 priv = &buf_alloc->priv_buf[i];
3523 if (hw->hw_tc_map & BIT(i) &&
3524 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3532 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3535 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3536 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3537 struct hns3_pf *pf = &hns->pf;
3538 uint32_t shared_buf, aligned_mps;
3543 tc_num = hns3_get_tc_num(hw);
3544 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3546 if (hns3_dev_dcb_supported(hw))
3547 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3550 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3553 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3554 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3555 HNS3_BUF_SIZE_UNIT);
3557 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3558 if (rx_all < rx_priv + shared_std)
3561 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3562 buf_alloc->s_buf.buf_size = shared_buf;
3563 if (hns3_dev_dcb_supported(hw)) {
3564 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3565 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3566 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3567 HNS3_BUF_SIZE_UNIT);
3569 buf_alloc->s_buf.self.high =
3570 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3571 buf_alloc->s_buf.self.low = aligned_mps;
3574 if (hns3_dev_dcb_supported(hw)) {
3575 hi_thrd = shared_buf - pf->dv_buf_size;
3577 if (tc_num <= NEED_RESERVE_TC_NUM)
3578 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3582 hi_thrd = hi_thrd / tc_num;
3584 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3585 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3586 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3588 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3589 lo_thrd = aligned_mps;
3592 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3593 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3594 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3601 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3602 struct hns3_pkt_buf_alloc *buf_alloc)
3604 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3605 struct hns3_pf *pf = &hns->pf;
3606 struct hns3_priv_buf *priv;
3607 uint32_t aligned_mps;
3611 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3612 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3614 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3615 priv = &buf_alloc->priv_buf[i];
3622 if (!(hw->hw_tc_map & BIT(i)))
3626 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3627 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3628 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3629 HNS3_BUF_SIZE_UNIT);
3632 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3636 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3639 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3643 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3644 struct hns3_pkt_buf_alloc *buf_alloc)
3646 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3647 struct hns3_pf *pf = &hns->pf;
3648 struct hns3_priv_buf *priv;
3649 int no_pfc_priv_num;
3654 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3655 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3657 /* let the last to be cleared first */
3658 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3659 priv = &buf_alloc->priv_buf[i];
3660 mask = BIT((uint8_t)i);
3662 if (hw->hw_tc_map & mask &&
3663 !(hw->dcb_info.hw_pfc_map & mask)) {
3664 /* Clear the no pfc TC private buffer */
3672 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3673 no_pfc_priv_num == 0)
3677 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3681 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3682 struct hns3_pkt_buf_alloc *buf_alloc)
3684 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3685 struct hns3_pf *pf = &hns->pf;
3686 struct hns3_priv_buf *priv;
3692 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3693 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3695 /* let the last to be cleared first */
3696 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3697 priv = &buf_alloc->priv_buf[i];
3698 mask = BIT((uint8_t)i);
3699 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3700 /* Reduce the number of pfc TC with private buffer */
3707 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3712 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3716 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3717 struct hns3_pkt_buf_alloc *buf_alloc)
3719 #define COMPENSATE_BUFFER 0x3C00
3720 #define COMPENSATE_HALF_MPS_NUM 5
3721 #define PRIV_WL_GAP 0x1800
3722 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3723 struct hns3_pf *pf = &hns->pf;
3724 uint32_t tc_num = hns3_get_tc_num(hw);
3725 uint32_t half_mps = pf->mps >> 1;
3726 struct hns3_priv_buf *priv;
3727 uint32_t min_rx_priv;
3731 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3733 rx_priv = rx_priv / tc_num;
3735 if (tc_num <= NEED_RESERVE_TC_NUM)
3736 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3739 * Minimum value of private buffer in rx direction (min_rx_priv) is
3740 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3741 * buffer if rx_priv is greater than min_rx_priv.
3743 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3744 COMPENSATE_HALF_MPS_NUM * half_mps;
3745 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3746 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3748 if (rx_priv < min_rx_priv)
3751 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3752 priv = &buf_alloc->priv_buf[i];
3758 if (!(hw->hw_tc_map & BIT(i)))
3762 priv->buf_size = rx_priv;
3763 priv->wl.high = rx_priv - pf->dv_buf_size;
3764 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3767 buf_alloc->s_buf.buf_size = 0;
3773 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3774 * @hw: pointer to struct hns3_hw
3775 * @buf_alloc: pointer to buffer calculation data
3776 * @return: 0: calculate sucessful, negative: fail
3779 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3781 /* When DCB is not supported, rx private buffer is not allocated. */
3782 if (!hns3_dev_dcb_supported(hw)) {
3783 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3784 struct hns3_pf *pf = &hns->pf;
3785 uint32_t rx_all = pf->pkt_buf_size;
3787 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3788 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3795 * Try to allocate privated packet buffer for all TCs without share
3798 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3802 * Try to allocate privated packet buffer for all TCs with share
3805 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3809 * For different application scenes, the enabled port number, TC number
3810 * and no_drop TC number are different. In order to obtain the better
3811 * performance, software could allocate the buffer size and configure
3812 * the waterline by tring to decrease the private buffer size according
3813 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3816 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3819 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3822 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3829 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3831 struct hns3_rx_priv_buff_cmd *req;
3832 struct hns3_cmd_desc desc;
3837 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3838 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3840 /* Alloc private buffer TCs */
3841 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3842 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3845 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3846 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3849 buf_size = buf_alloc->s_buf.buf_size;
3850 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3851 (1 << HNS3_TC0_PRI_BUF_EN_B));
3853 ret = hns3_cmd_send(hw, &desc, 1);
3855 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3861 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3863 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3864 struct hns3_rx_priv_wl_buf *req;
3865 struct hns3_priv_buf *priv;
3866 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3870 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3871 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3873 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3875 /* The first descriptor set the NEXT bit to 1 */
3877 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3879 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3881 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3882 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3884 priv = &buf_alloc->priv_buf[idx];
3885 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3887 req->tc_wl[j].high |=
3888 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3889 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3891 req->tc_wl[j].low |=
3892 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3896 /* Send 2 descriptor at one time */
3897 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3899 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3905 hns3_common_thrd_config(struct hns3_hw *hw,
3906 struct hns3_pkt_buf_alloc *buf_alloc)
3908 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3909 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3910 struct hns3_rx_com_thrd *req;
3911 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3912 struct hns3_tc_thrd *tc;
3917 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3918 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3920 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3922 /* The first descriptor set the NEXT bit to 1 */
3924 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3926 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3928 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3929 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3930 tc = &s_buf->tc_thrd[tc_idx];
3932 req->com_thrd[j].high =
3933 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3934 req->com_thrd[j].high |=
3935 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3936 req->com_thrd[j].low =
3937 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3938 req->com_thrd[j].low |=
3939 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3943 /* Send 2 descriptors at one time */
3944 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3946 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3952 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3954 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3955 struct hns3_rx_com_wl *req;
3956 struct hns3_cmd_desc desc;
3959 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3961 req = (struct hns3_rx_com_wl *)desc.data;
3962 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3963 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3965 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3966 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3968 ret = hns3_cmd_send(hw, &desc, 1);
3970 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3976 hns3_buffer_alloc(struct hns3_hw *hw)
3978 struct hns3_pkt_buf_alloc pkt_buf;
3981 memset(&pkt_buf, 0, sizeof(pkt_buf));
3982 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3985 "could not calc tx buffer size for all TCs %d",
3990 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3992 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3996 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3999 "could not calc rx priv buffer size for all TCs %d",
4004 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4006 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4010 if (hns3_dev_dcb_supported(hw)) {
4011 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4014 "could not configure rx private waterline %d",
4019 ret = hns3_common_thrd_config(hw, &pkt_buf);
4022 "could not configure common threshold %d",
4028 ret = hns3_common_wl_config(hw, &pkt_buf);
4030 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4037 hns3_firmware_compat_config(struct hns3_hw *hw, bool is_init)
4039 struct hns3_firmware_compat_cmd *req;
4040 struct hns3_cmd_desc desc;
4041 uint32_t compat = 0;
4043 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_FIRMWARE_COMPAT_CFG, false);
4044 req = (struct hns3_firmware_compat_cmd *)desc.data;
4047 hns3_set_bit(compat, HNS3_LINK_EVENT_REPORT_EN_B, 1);
4048 hns3_set_bit(compat, HNS3_NCSI_ERROR_REPORT_EN_B, 0);
4049 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4050 hns3_set_bit(compat, HNS3_FIRMWARE_PHY_DRIVER_EN_B, 1);
4053 req->compat = rte_cpu_to_le_32(compat);
4055 return hns3_cmd_send(hw, &desc, 1);
4059 hns3_mac_init(struct hns3_hw *hw)
4061 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4062 struct hns3_mac *mac = &hw->mac;
4063 struct hns3_pf *pf = &hns->pf;
4066 pf->support_sfp_query = true;
4067 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4068 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4070 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4074 mac->link_status = ETH_LINK_DOWN;
4076 return hns3_config_mtu(hw, pf->mps);
4080 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4082 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
4083 #define HNS3_ETHERTYPE_ALREADY_ADD 1
4084 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
4085 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
4090 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4095 switch (resp_code) {
4096 case HNS3_ETHERTYPE_SUCCESS_ADD:
4097 case HNS3_ETHERTYPE_ALREADY_ADD:
4100 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4102 "add mac ethertype failed for manager table overflow.");
4103 return_status = -EIO;
4105 case HNS3_ETHERTYPE_KEY_CONFLICT:
4106 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4107 return_status = -EIO;
4111 "add mac ethertype failed for undefined, code=%u.",
4113 return_status = -EIO;
4117 return return_status;
4121 hns3_add_mgr_tbl(struct hns3_hw *hw,
4122 const struct hns3_mac_mgr_tbl_entry_cmd *req)
4124 struct hns3_cmd_desc desc;
4129 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4130 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4132 ret = hns3_cmd_send(hw, &desc, 1);
4135 "add mac ethertype failed for cmd_send, ret =%d.",
4140 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4141 retval = rte_le_to_cpu_16(desc.retval);
4143 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4147 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4148 int *table_item_num)
4150 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4153 * In current version, we add one item in management table as below:
4154 * 0x0180C200000E -- LLDP MC address
4157 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4158 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4159 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4160 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4161 tbl->i_port_bitmap = 0x1;
4162 *table_item_num = 1;
4166 hns3_init_mgr_tbl(struct hns3_hw *hw)
4168 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
4169 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4174 memset(mgr_table, 0, sizeof(mgr_table));
4175 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4176 for (i = 0; i < table_item_num; i++) {
4177 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4179 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4189 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4190 bool en_mc, bool en_bc, int vport_id)
4195 memset(param, 0, sizeof(struct hns3_promisc_param));
4197 param->enable = HNS3_PROMISC_EN_UC;
4199 param->enable |= HNS3_PROMISC_EN_MC;
4201 param->enable |= HNS3_PROMISC_EN_BC;
4202 param->vf_id = vport_id;
4206 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4208 struct hns3_promisc_cfg_cmd *req;
4209 struct hns3_cmd_desc desc;
4212 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4214 req = (struct hns3_promisc_cfg_cmd *)desc.data;
4215 req->vf_id = param->vf_id;
4216 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4217 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4219 ret = hns3_cmd_send(hw, &desc, 1);
4221 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4227 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4229 struct hns3_promisc_param param;
4230 bool en_bc_pmc = true;
4234 * In current version VF is not supported when PF is driven by DPDK
4235 * driver, just need to configure parameters for PF vport.
4237 vf_id = HNS3_PF_FUNC_ID;
4239 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4240 return hns3_cmd_set_promisc_mode(hw, ¶m);
4244 hns3_promisc_init(struct hns3_hw *hw)
4246 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4247 struct hns3_pf *pf = &hns->pf;
4248 struct hns3_promisc_param param;
4252 ret = hns3_set_promisc_mode(hw, false, false);
4254 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4259 * In current version VFs are not supported when PF is driven by DPDK
4260 * driver. After PF has been taken over by DPDK, the original VF will
4261 * be invalid. So, there is a possibility of entry residues. It should
4262 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4265 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4266 hns3_promisc_param_init(¶m, false, false, false, func_id);
4267 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4269 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4270 " ret = %d", func_id, ret);
4279 hns3_promisc_uninit(struct hns3_hw *hw)
4281 struct hns3_promisc_param param;
4285 func_id = HNS3_PF_FUNC_ID;
4288 * In current version VFs are not supported when PF is driven by
4289 * DPDK driver, and VFs' promisc mode status has been cleared during
4290 * init and their status will not change. So just clear PF's promisc
4291 * mode status during uninit.
4293 hns3_promisc_param_init(¶m, false, false, false, func_id);
4294 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4296 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4297 " uninit, ret = %d", ret);
4301 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4303 bool allmulti = dev->data->all_multicast ? true : false;
4304 struct hns3_adapter *hns = dev->data->dev_private;
4305 struct hns3_hw *hw = &hns->hw;
4310 rte_spinlock_lock(&hw->lock);
4311 ret = hns3_set_promisc_mode(hw, true, true);
4313 rte_spinlock_unlock(&hw->lock);
4314 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4320 * When promiscuous mode was enabled, disable the vlan filter to let
4321 * all packets coming in in the receiving direction.
4323 offloads = dev->data->dev_conf.rxmode.offloads;
4324 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4325 ret = hns3_enable_vlan_filter(hns, false);
4327 hns3_err(hw, "failed to enable promiscuous mode due to "
4328 "failure to disable vlan filter, ret = %d",
4330 err = hns3_set_promisc_mode(hw, false, allmulti);
4332 hns3_err(hw, "failed to restore promiscuous "
4333 "status after disable vlan filter "
4334 "failed during enabling promiscuous "
4335 "mode, ret = %d", ret);
4339 rte_spinlock_unlock(&hw->lock);
4345 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4347 bool allmulti = dev->data->all_multicast ? true : false;
4348 struct hns3_adapter *hns = dev->data->dev_private;
4349 struct hns3_hw *hw = &hns->hw;
4354 /* If now in all_multicast mode, must remain in all_multicast mode. */
4355 rte_spinlock_lock(&hw->lock);
4356 ret = hns3_set_promisc_mode(hw, false, allmulti);
4358 rte_spinlock_unlock(&hw->lock);
4359 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4363 /* when promiscuous mode was disabled, restore the vlan filter status */
4364 offloads = dev->data->dev_conf.rxmode.offloads;
4365 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4366 ret = hns3_enable_vlan_filter(hns, true);
4368 hns3_err(hw, "failed to disable promiscuous mode due to"
4369 " failure to restore vlan filter, ret = %d",
4371 err = hns3_set_promisc_mode(hw, true, true);
4373 hns3_err(hw, "failed to restore promiscuous "
4374 "status after enabling vlan filter "
4375 "failed during disabling promiscuous "
4376 "mode, ret = %d", ret);
4379 rte_spinlock_unlock(&hw->lock);
4385 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4387 struct hns3_adapter *hns = dev->data->dev_private;
4388 struct hns3_hw *hw = &hns->hw;
4391 if (dev->data->promiscuous)
4394 rte_spinlock_lock(&hw->lock);
4395 ret = hns3_set_promisc_mode(hw, false, true);
4396 rte_spinlock_unlock(&hw->lock);
4398 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4405 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4407 struct hns3_adapter *hns = dev->data->dev_private;
4408 struct hns3_hw *hw = &hns->hw;
4411 /* If now in promiscuous mode, must remain in all_multicast mode. */
4412 if (dev->data->promiscuous)
4415 rte_spinlock_lock(&hw->lock);
4416 ret = hns3_set_promisc_mode(hw, false, false);
4417 rte_spinlock_unlock(&hw->lock);
4419 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4426 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4428 struct hns3_hw *hw = &hns->hw;
4429 bool allmulti = hw->data->all_multicast ? true : false;
4432 if (hw->data->promiscuous) {
4433 ret = hns3_set_promisc_mode(hw, true, true);
4435 hns3_err(hw, "failed to restore promiscuous mode, "
4440 ret = hns3_set_promisc_mode(hw, false, allmulti);
4442 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4448 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4450 struct hns3_sfp_speed_cmd *resp;
4451 struct hns3_cmd_desc desc;
4454 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4455 resp = (struct hns3_sfp_speed_cmd *)desc.data;
4456 ret = hns3_cmd_send(hw, &desc, 1);
4457 if (ret == -EOPNOTSUPP) {
4458 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4461 hns3_err(hw, "get sfp speed failed %d", ret);
4465 *speed = resp->sfp_speed;
4471 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4473 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4474 duplex = ETH_LINK_FULL_DUPLEX;
4480 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4482 struct hns3_mac *mac = &hw->mac;
4485 duplex = hns3_check_speed_dup(duplex, speed);
4486 if (mac->link_speed == speed && mac->link_duplex == duplex)
4489 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4493 ret = hns3_port_shaper_update(hw, speed);
4497 mac->link_speed = speed;
4498 mac->link_duplex = duplex;
4504 hns3_update_fiber_link_info(struct hns3_hw *hw)
4506 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4510 /* If IMP do not support get SFP/qSFP speed, return directly */
4511 if (!pf->support_sfp_query)
4514 ret = hns3_get_sfp_speed(hw, &speed);
4515 if (ret == -EOPNOTSUPP) {
4516 pf->support_sfp_query = false;
4521 if (speed == ETH_SPEED_NUM_NONE)
4522 return 0; /* do nothing if no SFP */
4524 /* Config full duplex for SFP */
4525 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4529 hns3_parse_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4531 struct hns3_phy_params_bd0_cmd *req;
4533 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4534 mac->link_speed = rte_le_to_cpu_32(req->speed);
4535 mac->link_duplex = hns3_get_bit(req->duplex,
4536 HNS3_PHY_DUPLEX_CFG_B);
4537 mac->link_autoneg = hns3_get_bit(req->autoneg,
4538 HNS3_PHY_AUTONEG_CFG_B);
4539 mac->supported_capa = rte_le_to_cpu_32(req->supported);
4540 mac->advertising = rte_le_to_cpu_32(req->advertising);
4541 mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4542 mac->support_autoneg = !!(mac->supported_capa &
4543 HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4547 hns3_get_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4549 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4553 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4554 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4556 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4558 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4560 ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4562 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4566 hns3_parse_phy_params(desc, mac);
4572 hns3_update_phy_link_info(struct hns3_hw *hw)
4574 struct hns3_mac *mac = &hw->mac;
4575 struct hns3_mac mac_info;
4578 memset(&mac_info, 0, sizeof(struct hns3_mac));
4579 ret = hns3_get_phy_params(hw, &mac_info);
4583 if (mac_info.link_speed != mac->link_speed) {
4584 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4589 mac->link_speed = mac_info.link_speed;
4590 mac->link_duplex = mac_info.link_duplex;
4591 mac->link_autoneg = mac_info.link_autoneg;
4592 mac->supported_capa = mac_info.supported_capa;
4593 mac->advertising = mac_info.advertising;
4594 mac->lp_advertising = mac_info.lp_advertising;
4595 mac->support_autoneg = mac_info.support_autoneg;
4601 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4603 struct hns3_adapter *hns = eth_dev->data->dev_private;
4604 struct hns3_hw *hw = &hns->hw;
4607 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4608 ret = hns3_update_phy_link_info(hw);
4609 else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4610 ret = hns3_update_fiber_link_info(hw);
4616 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4618 struct hns3_config_mac_mode_cmd *req;
4619 struct hns3_cmd_desc desc;
4620 uint32_t loop_en = 0;
4624 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4626 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4629 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4630 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4631 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4632 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4633 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4634 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4635 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4636 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4637 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4638 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4641 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4642 * when receiving frames. Otherwise, CRC will be stripped.
4644 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4645 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4647 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4648 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4649 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4650 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4651 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4653 ret = hns3_cmd_send(hw, &desc, 1);
4655 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4661 hns3_get_mac_link_status(struct hns3_hw *hw)
4663 struct hns3_link_status_cmd *req;
4664 struct hns3_cmd_desc desc;
4668 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4669 ret = hns3_cmd_send(hw, &desc, 1);
4671 hns3_err(hw, "get link status cmd failed %d", ret);
4672 return ETH_LINK_DOWN;
4675 req = (struct hns3_link_status_cmd *)desc.data;
4676 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4678 return !!link_status;
4682 hns3_update_link_status(struct hns3_hw *hw)
4686 state = hns3_get_mac_link_status(hw);
4687 if (state != hw->mac.link_status) {
4688 hw->mac.link_status = state;
4689 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4690 hns3_config_mac_tnl_int(hw,
4691 state == ETH_LINK_UP ? true : false);
4699 * Current, the PF driver get link status by two ways:
4700 * 1) Periodic polling in the intr thread context, driver call
4701 * hns3_update_link_status to update link status.
4702 * 2) Firmware report async interrupt, driver process the event in the intr
4703 * thread context, and call hns3_update_link_status to update link status.
4705 * If detect link status changed, driver need report LSE. One method is add the
4706 * report LSE logic in hns3_update_link_status.
4708 * But the PF driver ops(link_update) also call hns3_update_link_status to
4709 * update link status.
4710 * If we report LSE in hns3_update_link_status, it may lead to deadlock in the
4711 * bonding application.
4713 * So add the one new API which used only in intr thread context.
4716 hns3_update_link_status_and_event(struct hns3_hw *hw)
4718 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4719 bool changed = hns3_update_link_status(hw);
4721 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4725 hns3_service_handler(void *param)
4727 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4728 struct hns3_adapter *hns = eth_dev->data->dev_private;
4729 struct hns3_hw *hw = &hns->hw;
4731 if (!hns3_is_reset_pending(hns)) {
4732 hns3_update_link_status_and_event(hw);
4733 hns3_update_link_info(eth_dev);
4735 hns3_warn(hw, "Cancel the query when reset is pending");
4738 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4742 hns3_init_hardware(struct hns3_adapter *hns)
4744 struct hns3_hw *hw = &hns->hw;
4747 ret = hns3_map_tqp(hw);
4749 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4753 ret = hns3_init_umv_space(hw);
4755 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4759 ret = hns3_mac_init(hw);
4761 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4765 ret = hns3_init_mgr_tbl(hw);
4767 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4771 ret = hns3_promisc_init(hw);
4773 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4778 ret = hns3_init_vlan_config(hns);
4780 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4784 ret = hns3_dcb_init(hw);
4786 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4790 ret = hns3_init_fd_config(hns);
4792 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4796 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4798 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4802 ret = hns3_config_gro(hw, false);
4804 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4809 * In the initialization clearing the all hardware mapping relationship
4810 * configurations between queues and interrupt vectors is needed, so
4811 * some error caused by the residual configurations, such as the
4812 * unexpected interrupt, can be avoid.
4814 ret = hns3_init_ring_with_vector(hw);
4816 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4821 * Requiring firmware to enable some features, driver can
4822 * still work without it.
4824 ret = hns3_firmware_compat_config(hw, true);
4826 PMD_INIT_LOG(WARNING, "firmware compatible features not "
4827 "supported, ret = %d.", ret);
4832 hns3_uninit_umv_space(hw);
4837 hns3_clear_hw(struct hns3_hw *hw)
4839 struct hns3_cmd_desc desc;
4842 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4844 ret = hns3_cmd_send(hw, &desc, 1);
4845 if (ret && ret != -EOPNOTSUPP)
4852 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4857 * The new firmware support report more hardware error types by
4858 * msix mode. These errors are defined as RAS errors in hardware
4859 * and belong to a different type from the MSI-x errors processed
4860 * by the network driver.
4862 * Network driver should open the new error report on initialition
4864 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4865 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4866 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4870 hns3_init_pf(struct rte_eth_dev *eth_dev)
4872 struct rte_device *dev = eth_dev->device;
4873 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4874 struct hns3_adapter *hns = eth_dev->data->dev_private;
4875 struct hns3_hw *hw = &hns->hw;
4878 PMD_INIT_FUNC_TRACE();
4880 /* Get hardware io base address from pcie BAR2 IO space */
4881 hw->io_base = pci_dev->mem_resource[2].addr;
4883 /* Firmware command queue initialize */
4884 ret = hns3_cmd_init_queue(hw);
4886 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4887 goto err_cmd_init_queue;
4890 hns3_clear_all_event_cause(hw);
4892 /* Firmware command initialize */
4893 ret = hns3_cmd_init(hw);
4895 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4900 * To ensure that the hardware environment is clean during
4901 * initialization, the driver actively clear the hardware environment
4902 * during initialization, including PF and corresponding VFs' vlan, mac,
4903 * flow table configurations, etc.
4905 ret = hns3_clear_hw(hw);
4907 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4911 /* Hardware statistics of imissed registers cleared. */
4912 ret = hns3_update_imissed_stats(hw, true);
4914 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
4918 hns3_config_all_msix_error(hw, true);
4920 ret = rte_intr_callback_register(&pci_dev->intr_handle,
4921 hns3_interrupt_handler,
4924 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4925 goto err_intr_callback_register;
4928 /* Enable interrupt */
4929 rte_intr_enable(&pci_dev->intr_handle);
4930 hns3_pf_enable_irq0(hw);
4932 /* Get configuration */
4933 ret = hns3_get_configuration(hw);
4935 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4936 goto err_get_config;
4939 ret = hns3_tqp_stats_init(hw);
4941 goto err_get_config;
4943 ret = hns3_init_hardware(hns);
4945 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4949 /* Initialize flow director filter list & hash */
4950 ret = hns3_fdir_filter_init(hns);
4952 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4956 hns3_rss_set_default_args(hw);
4958 ret = hns3_enable_hw_error_intr(hns, true);
4960 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4962 goto err_enable_intr;
4965 hns3_tm_conf_init(eth_dev);
4970 hns3_fdir_filter_uninit(hns);
4972 (void)hns3_firmware_compat_config(hw, false);
4973 hns3_uninit_umv_space(hw);
4975 hns3_tqp_stats_uninit(hw);
4977 hns3_pf_disable_irq0(hw);
4978 rte_intr_disable(&pci_dev->intr_handle);
4979 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4981 err_intr_callback_register:
4983 hns3_cmd_uninit(hw);
4984 hns3_cmd_destroy_queue(hw);
4992 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4994 struct hns3_adapter *hns = eth_dev->data->dev_private;
4995 struct rte_device *dev = eth_dev->device;
4996 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4997 struct hns3_hw *hw = &hns->hw;
4999 PMD_INIT_FUNC_TRACE();
5001 hns3_tm_conf_uninit(eth_dev);
5002 hns3_enable_hw_error_intr(hns, false);
5003 hns3_rss_uninit(hns);
5004 (void)hns3_config_gro(hw, false);
5005 hns3_promisc_uninit(hw);
5006 hns3_fdir_filter_uninit(hns);
5007 (void)hns3_firmware_compat_config(hw, false);
5008 hns3_uninit_umv_space(hw);
5009 hns3_tqp_stats_uninit(hw);
5010 hns3_config_mac_tnl_int(hw, false);
5011 hns3_pf_disable_irq0(hw);
5012 rte_intr_disable(&pci_dev->intr_handle);
5013 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5015 hns3_config_all_msix_error(hw, false);
5016 hns3_cmd_uninit(hw);
5017 hns3_cmd_destroy_queue(hw);
5022 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5024 struct hns3_hw *hw = &hns->hw;
5027 ret = hns3_dcb_cfg_update(hns);
5032 * The hns3_dcb_cfg_update may configure TM module, so
5033 * hns3_tm_conf_update must called later.
5035 ret = hns3_tm_conf_update(hw);
5037 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5041 hns3_enable_rxd_adv_layout(hw);
5043 ret = hns3_init_queues(hns, reset_queue);
5045 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5049 ret = hns3_cfg_mac_mode(hw, true);
5051 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5052 goto err_config_mac_mode;
5056 err_config_mac_mode:
5057 hns3_dev_release_mbufs(hns);
5059 * Here is exception handling, hns3_reset_all_tqps will have the
5060 * corresponding error message if it is handled incorrectly, so it is
5061 * not necessary to check hns3_reset_all_tqps return value, here keep
5062 * ret as the error code causing the exception.
5064 (void)hns3_reset_all_tqps(hns);
5069 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5071 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5072 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5073 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5074 uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5075 uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5076 uint32_t intr_vector;
5081 * hns3 needs a separate interrupt to be used as event interrupt which
5082 * could not be shared with task queue pair, so KERNEL drivers need
5083 * support multiple interrupt vectors.
5085 if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5086 !rte_intr_cap_multiple(intr_handle))
5089 rte_intr_disable(intr_handle);
5090 intr_vector = hw->used_rx_queues;
5091 /* creates event fd for each intr vector when MSIX is used */
5092 if (rte_intr_efd_enable(intr_handle, intr_vector))
5095 if (intr_handle->intr_vec == NULL) {
5096 intr_handle->intr_vec =
5097 rte_zmalloc("intr_vec",
5098 hw->used_rx_queues * sizeof(int), 0);
5099 if (intr_handle->intr_vec == NULL) {
5100 hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5101 hw->used_rx_queues);
5103 goto alloc_intr_vec_error;
5107 if (rte_intr_allow_others(intr_handle)) {
5108 vec = RTE_INTR_VEC_RXTX_OFFSET;
5109 base = RTE_INTR_VEC_RXTX_OFFSET;
5112 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5113 ret = hns3_bind_ring_with_vector(hw, vec, true,
5114 HNS3_RING_TYPE_RX, q_id);
5116 goto bind_vector_error;
5117 intr_handle->intr_vec[q_id] = vec;
5119 * If there are not enough efds (e.g. not enough interrupt),
5120 * remaining queues will be bond to the last interrupt.
5122 if (vec < base + intr_handle->nb_efd - 1)
5125 rte_intr_enable(intr_handle);
5129 rte_free(intr_handle->intr_vec);
5130 intr_handle->intr_vec = NULL;
5131 alloc_intr_vec_error:
5132 rte_intr_efd_disable(intr_handle);
5137 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5139 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5140 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5141 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5145 if (dev->data->dev_conf.intr_conf.rxq == 0)
5148 if (rte_intr_dp_is_en(intr_handle)) {
5149 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5150 ret = hns3_bind_ring_with_vector(hw,
5151 intr_handle->intr_vec[q_id], true,
5152 HNS3_RING_TYPE_RX, q_id);
5162 hns3_restore_filter(struct rte_eth_dev *dev)
5164 hns3_restore_rss_filter(dev);
5168 hns3_dev_start(struct rte_eth_dev *dev)
5170 struct hns3_adapter *hns = dev->data->dev_private;
5171 struct hns3_hw *hw = &hns->hw;
5174 PMD_INIT_FUNC_TRACE();
5175 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5178 rte_spinlock_lock(&hw->lock);
5179 hw->adapter_state = HNS3_NIC_STARTING;
5181 ret = hns3_do_start(hns, true);
5183 hw->adapter_state = HNS3_NIC_CONFIGURED;
5184 rte_spinlock_unlock(&hw->lock);
5187 ret = hns3_map_rx_interrupt(dev);
5189 goto map_rx_inter_err;
5192 * There are three register used to control the status of a TQP
5193 * (contains a pair of Tx queue and Rx queue) in the new version network
5194 * engine. One is used to control the enabling of Tx queue, the other is
5195 * used to control the enabling of Rx queue, and the last is the master
5196 * switch used to control the enabling of the tqp. The Tx register and
5197 * TQP register must be enabled at the same time to enable a Tx queue.
5198 * The same applies to the Rx queue. For the older network engine, this
5199 * function only refresh the enabled flag, and it is used to update the
5200 * status of queue in the dpdk framework.
5202 ret = hns3_start_all_txqs(dev);
5204 goto map_rx_inter_err;
5206 ret = hns3_start_all_rxqs(dev);
5208 goto start_all_rxqs_fail;
5210 hw->adapter_state = HNS3_NIC_STARTED;
5211 rte_spinlock_unlock(&hw->lock);
5213 hns3_rx_scattered_calc(dev);
5214 hns3_set_rxtx_function(dev);
5215 hns3_mp_req_start_rxtx(dev);
5216 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5218 hns3_restore_filter(dev);
5220 /* Enable interrupt of all rx queues before enabling queues */
5221 hns3_dev_all_rx_queue_intr_enable(hw, true);
5224 * After finished the initialization, enable tqps to receive/transmit
5225 * packets and refresh all queue status.
5227 hns3_start_tqps(hw);
5229 hns3_tm_dev_start_proc(hw);
5231 hns3_info(hw, "hns3 dev start successful!");
5235 start_all_rxqs_fail:
5236 hns3_stop_all_txqs(dev);
5238 (void)hns3_do_stop(hns);
5239 hw->adapter_state = HNS3_NIC_CONFIGURED;
5240 rte_spinlock_unlock(&hw->lock);
5246 hns3_do_stop(struct hns3_adapter *hns)
5248 struct hns3_hw *hw = &hns->hw;
5252 * The "hns3_do_stop" function will also be called by .stop_service to
5253 * prepare reset. At the time of global or IMP reset, the command cannot
5254 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5255 * accessed during the reset process. So the mbuf can not be released
5256 * during reset and is required to be released after the reset is
5259 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)
5260 hns3_dev_release_mbufs(hns);
5262 ret = hns3_cfg_mac_mode(hw, false);
5265 hw->mac.link_status = ETH_LINK_DOWN;
5267 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5268 hns3_configure_all_mac_addr(hns, true);
5269 ret = hns3_reset_all_tqps(hns);
5271 hns3_err(hw, "failed to reset all queues ret = %d.",
5276 hw->mac.default_addr_setted = false;
5281 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5283 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5284 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5285 struct hns3_adapter *hns = dev->data->dev_private;
5286 struct hns3_hw *hw = &hns->hw;
5287 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5288 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5291 if (dev->data->dev_conf.intr_conf.rxq == 0)
5294 /* unmap the ring with vector */
5295 if (rte_intr_allow_others(intr_handle)) {
5296 vec = RTE_INTR_VEC_RXTX_OFFSET;
5297 base = RTE_INTR_VEC_RXTX_OFFSET;
5299 if (rte_intr_dp_is_en(intr_handle)) {
5300 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5301 (void)hns3_bind_ring_with_vector(hw, vec, false,
5304 if (vec < base + intr_handle->nb_efd - 1)
5308 /* Clean datapath event and queue/vec mapping */
5309 rte_intr_efd_disable(intr_handle);
5310 if (intr_handle->intr_vec) {
5311 rte_free(intr_handle->intr_vec);
5312 intr_handle->intr_vec = NULL;
5317 hns3_dev_stop(struct rte_eth_dev *dev)
5319 struct hns3_adapter *hns = dev->data->dev_private;
5320 struct hns3_hw *hw = &hns->hw;
5322 PMD_INIT_FUNC_TRACE();
5323 dev->data->dev_started = 0;
5325 hw->adapter_state = HNS3_NIC_STOPPING;
5326 hns3_set_rxtx_function(dev);
5328 /* Disable datapath on secondary process. */
5329 hns3_mp_req_stop_rxtx(dev);
5330 /* Prevent crashes when queues are still in use. */
5331 rte_delay_ms(hw->tqps_num);
5333 rte_spinlock_lock(&hw->lock);
5334 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5335 hns3_tm_dev_stop_proc(hw);
5336 hns3_config_mac_tnl_int(hw, false);
5339 hns3_unmap_rx_interrupt(dev);
5340 hw->adapter_state = HNS3_NIC_CONFIGURED;
5342 hns3_rx_scattered_reset(dev);
5343 rte_eal_alarm_cancel(hns3_service_handler, dev);
5344 rte_spinlock_unlock(&hw->lock);
5350 hns3_dev_close(struct rte_eth_dev *eth_dev)
5352 struct hns3_adapter *hns = eth_dev->data->dev_private;
5353 struct hns3_hw *hw = &hns->hw;
5356 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5357 rte_free(eth_dev->process_private);
5358 eth_dev->process_private = NULL;
5362 if (hw->adapter_state == HNS3_NIC_STARTED)
5363 ret = hns3_dev_stop(eth_dev);
5365 hw->adapter_state = HNS3_NIC_CLOSING;
5366 hns3_reset_abort(hns);
5367 hw->adapter_state = HNS3_NIC_CLOSED;
5369 hns3_configure_all_mc_mac_addr(hns, true);
5370 hns3_remove_all_vlan_table(hns);
5371 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5372 hns3_uninit_pf(eth_dev);
5373 hns3_free_all_queues(eth_dev);
5374 rte_free(hw->reset.wait_data);
5375 rte_free(eth_dev->process_private);
5376 eth_dev->process_private = NULL;
5377 hns3_mp_uninit_primary();
5378 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5384 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5386 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5387 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5389 fc_conf->pause_time = pf->pause_time;
5391 /* return fc current mode */
5392 switch (hw->current_mode) {
5394 fc_conf->mode = RTE_FC_FULL;
5396 case HNS3_FC_TX_PAUSE:
5397 fc_conf->mode = RTE_FC_TX_PAUSE;
5399 case HNS3_FC_RX_PAUSE:
5400 fc_conf->mode = RTE_FC_RX_PAUSE;
5404 fc_conf->mode = RTE_FC_NONE;
5412 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5416 hw->requested_mode = HNS3_FC_NONE;
5418 case RTE_FC_RX_PAUSE:
5419 hw->requested_mode = HNS3_FC_RX_PAUSE;
5421 case RTE_FC_TX_PAUSE:
5422 hw->requested_mode = HNS3_FC_TX_PAUSE;
5425 hw->requested_mode = HNS3_FC_FULL;
5428 hw->requested_mode = HNS3_FC_NONE;
5429 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5430 "configured to RTE_FC_NONE", mode);
5436 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5438 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5439 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5442 if (fc_conf->high_water || fc_conf->low_water ||
5443 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5444 hns3_err(hw, "Unsupported flow control settings specified, "
5445 "high_water(%u), low_water(%u), send_xon(%u) and "
5446 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5447 fc_conf->high_water, fc_conf->low_water,
5448 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5451 if (fc_conf->autoneg) {
5452 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5455 if (!fc_conf->pause_time) {
5456 hns3_err(hw, "Invalid pause time %u setting.",
5457 fc_conf->pause_time);
5461 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5462 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5463 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5464 "current_fc_status = %d", hw->current_fc_status);
5468 hns3_get_fc_mode(hw, fc_conf->mode);
5469 if (hw->requested_mode == hw->current_mode &&
5470 pf->pause_time == fc_conf->pause_time)
5473 rte_spinlock_lock(&hw->lock);
5474 ret = hns3_fc_enable(dev, fc_conf);
5475 rte_spinlock_unlock(&hw->lock);
5481 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5482 struct rte_eth_pfc_conf *pfc_conf)
5484 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5485 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5489 if (!hns3_dev_dcb_supported(hw)) {
5490 hns3_err(hw, "This port does not support dcb configurations.");
5494 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5495 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5496 hns3_err(hw, "Unsupported flow control settings specified, "
5497 "high_water(%u), low_water(%u), send_xon(%u) and "
5498 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5499 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5500 pfc_conf->fc.send_xon,
5501 pfc_conf->fc.mac_ctrl_frame_fwd);
5504 if (pfc_conf->fc.autoneg) {
5505 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5508 if (pfc_conf->fc.pause_time == 0) {
5509 hns3_err(hw, "Invalid pause time %u setting.",
5510 pfc_conf->fc.pause_time);
5514 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5515 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5516 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5517 "current_fc_status = %d", hw->current_fc_status);
5521 priority = pfc_conf->priority;
5522 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5523 if (hw->dcb_info.pfc_en & BIT(priority) &&
5524 hw->requested_mode == hw->current_mode &&
5525 pfc_conf->fc.pause_time == pf->pause_time)
5528 rte_spinlock_lock(&hw->lock);
5529 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5530 rte_spinlock_unlock(&hw->lock);
5536 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5538 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5539 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5540 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5543 rte_spinlock_lock(&hw->lock);
5544 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5545 dcb_info->nb_tcs = pf->local_max_tc;
5547 dcb_info->nb_tcs = 1;
5549 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5550 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5551 for (i = 0; i < dcb_info->nb_tcs; i++)
5552 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5554 for (i = 0; i < hw->num_tc; i++) {
5555 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5556 dcb_info->tc_queue.tc_txq[0][i].base =
5557 hw->tc_queue[i].tqp_offset;
5558 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5559 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5560 hw->tc_queue[i].tqp_count;
5562 rte_spinlock_unlock(&hw->lock);
5568 hns3_reinit_dev(struct hns3_adapter *hns)
5570 struct hns3_hw *hw = &hns->hw;
5573 ret = hns3_cmd_init(hw);
5575 hns3_err(hw, "Failed to init cmd: %d", ret);
5579 ret = hns3_reset_all_tqps(hns);
5581 hns3_err(hw, "Failed to reset all queues: %d", ret);
5585 ret = hns3_init_hardware(hns);
5587 hns3_err(hw, "Failed to init hardware: %d", ret);
5591 ret = hns3_enable_hw_error_intr(hns, true);
5593 hns3_err(hw, "fail to enable hw error interrupts: %d",
5597 hns3_info(hw, "Reset done, driver initialization finished.");
5603 is_pf_reset_done(struct hns3_hw *hw)
5605 uint32_t val, reg, reg_bit;
5607 switch (hw->reset.level) {
5608 case HNS3_IMP_RESET:
5609 reg = HNS3_GLOBAL_RESET_REG;
5610 reg_bit = HNS3_IMP_RESET_BIT;
5612 case HNS3_GLOBAL_RESET:
5613 reg = HNS3_GLOBAL_RESET_REG;
5614 reg_bit = HNS3_GLOBAL_RESET_BIT;
5616 case HNS3_FUNC_RESET:
5617 reg = HNS3_FUN_RST_ING;
5618 reg_bit = HNS3_FUN_RST_ING_B;
5620 case HNS3_FLR_RESET:
5622 hns3_err(hw, "Wait for unsupported reset level: %d",
5626 val = hns3_read_dev(hw, reg);
5627 if (hns3_get_bit(val, reg_bit))
5634 hns3_is_reset_pending(struct hns3_adapter *hns)
5636 struct hns3_hw *hw = &hns->hw;
5637 enum hns3_reset_level reset;
5639 hns3_check_event_cause(hns, NULL);
5640 reset = hns3_get_reset_level(hns, &hw->reset.pending);
5641 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5642 hns3_warn(hw, "High level reset %d is pending", reset);
5645 reset = hns3_get_reset_level(hns, &hw->reset.request);
5646 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5647 hns3_warn(hw, "High level reset %d is request", reset);
5654 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5656 struct hns3_hw *hw = &hns->hw;
5657 struct hns3_wait_data *wait_data = hw->reset.wait_data;
5660 if (wait_data->result == HNS3_WAIT_SUCCESS)
5662 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5663 gettimeofday(&tv, NULL);
5664 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5665 tv.tv_sec, tv.tv_usec);
5667 } else if (wait_data->result == HNS3_WAIT_REQUEST)
5670 wait_data->hns = hns;
5671 wait_data->check_completion = is_pf_reset_done;
5672 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5673 HNS3_RESET_WAIT_MS + get_timeofday_ms();
5674 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5675 wait_data->count = HNS3_RESET_WAIT_CNT;
5676 wait_data->result = HNS3_WAIT_REQUEST;
5677 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5682 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5684 struct hns3_cmd_desc desc;
5685 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5687 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5688 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5689 req->fun_reset_vfid = func_id;
5691 return hns3_cmd_send(hw, &desc, 1);
5695 hns3_imp_reset_cmd(struct hns3_hw *hw)
5697 struct hns3_cmd_desc desc;
5699 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5700 desc.data[0] = 0xeedd;
5702 return hns3_cmd_send(hw, &desc, 1);
5706 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5708 struct hns3_hw *hw = &hns->hw;
5712 gettimeofday(&tv, NULL);
5713 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5714 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5715 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5716 tv.tv_sec, tv.tv_usec);
5720 switch (reset_level) {
5721 case HNS3_IMP_RESET:
5722 hns3_imp_reset_cmd(hw);
5723 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5724 tv.tv_sec, tv.tv_usec);
5726 case HNS3_GLOBAL_RESET:
5727 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5728 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5729 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5730 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5731 tv.tv_sec, tv.tv_usec);
5733 case HNS3_FUNC_RESET:
5734 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5735 tv.tv_sec, tv.tv_usec);
5736 /* schedule again to check later */
5737 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5738 hns3_schedule_reset(hns);
5741 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5744 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5747 static enum hns3_reset_level
5748 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5750 struct hns3_hw *hw = &hns->hw;
5751 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5753 /* Return the highest priority reset level amongst all */
5754 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5755 reset_level = HNS3_IMP_RESET;
5756 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5757 reset_level = HNS3_GLOBAL_RESET;
5758 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5759 reset_level = HNS3_FUNC_RESET;
5760 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5761 reset_level = HNS3_FLR_RESET;
5763 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5764 return HNS3_NONE_RESET;
5770 hns3_record_imp_error(struct hns3_adapter *hns)
5772 struct hns3_hw *hw = &hns->hw;
5775 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5776 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5777 hns3_warn(hw, "Detected IMP RD poison!");
5778 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5779 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5782 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5783 hns3_warn(hw, "Detected IMP CMDQ error!");
5784 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5785 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5790 hns3_prepare_reset(struct hns3_adapter *hns)
5792 struct hns3_hw *hw = &hns->hw;
5796 switch (hw->reset.level) {
5797 case HNS3_FUNC_RESET:
5798 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5803 * After performaning pf reset, it is not necessary to do the
5804 * mailbox handling or send any command to firmware, because
5805 * any mailbox handling or command to firmware is only valid
5806 * after hns3_cmd_init is called.
5808 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
5809 hw->reset.stats.request_cnt++;
5811 case HNS3_IMP_RESET:
5812 hns3_record_imp_error(hns);
5813 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5814 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5815 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5824 hns3_set_rst_done(struct hns3_hw *hw)
5826 struct hns3_pf_rst_done_cmd *req;
5827 struct hns3_cmd_desc desc;
5829 req = (struct hns3_pf_rst_done_cmd *)desc.data;
5830 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5831 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5832 return hns3_cmd_send(hw, &desc, 1);
5836 hns3_stop_service(struct hns3_adapter *hns)
5838 struct hns3_hw *hw = &hns->hw;
5839 struct rte_eth_dev *eth_dev;
5841 eth_dev = &rte_eth_devices[hw->data->port_id];
5842 if (hw->adapter_state == HNS3_NIC_STARTED) {
5843 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5844 hns3_update_link_status_and_event(hw);
5846 hw->mac.link_status = ETH_LINK_DOWN;
5848 hns3_set_rxtx_function(eth_dev);
5850 /* Disable datapath on secondary process. */
5851 hns3_mp_req_stop_rxtx(eth_dev);
5852 rte_delay_ms(hw->tqps_num);
5854 rte_spinlock_lock(&hw->lock);
5855 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5856 hw->adapter_state == HNS3_NIC_STOPPING) {
5857 hns3_enable_all_queues(hw, false);
5859 hw->reset.mbuf_deferred_free = true;
5861 hw->reset.mbuf_deferred_free = false;
5864 * It is cumbersome for hardware to pick-and-choose entries for deletion
5865 * from table space. Hence, for function reset software intervention is
5866 * required to delete the entries
5868 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
5869 hns3_configure_all_mc_mac_addr(hns, true);
5870 rte_spinlock_unlock(&hw->lock);
5876 hns3_start_service(struct hns3_adapter *hns)
5878 struct hns3_hw *hw = &hns->hw;
5879 struct rte_eth_dev *eth_dev;
5881 if (hw->reset.level == HNS3_IMP_RESET ||
5882 hw->reset.level == HNS3_GLOBAL_RESET)
5883 hns3_set_rst_done(hw);
5884 eth_dev = &rte_eth_devices[hw->data->port_id];
5885 hns3_set_rxtx_function(eth_dev);
5886 hns3_mp_req_start_rxtx(eth_dev);
5887 if (hw->adapter_state == HNS3_NIC_STARTED) {
5889 * This API parent function already hold the hns3_hw.lock, the
5890 * hns3_service_handler may report lse, in bonding application
5891 * it will call driver's ops which may acquire the hns3_hw.lock
5892 * again, thus lead to deadlock.
5893 * We defer calls hns3_service_handler to avoid the deadlock.
5895 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
5896 hns3_service_handler, eth_dev);
5898 /* Enable interrupt of all rx queues before enabling queues */
5899 hns3_dev_all_rx_queue_intr_enable(hw, true);
5901 * Enable state of each rxq and txq will be recovered after
5902 * reset, so we need to restore them before enable all tqps;
5904 hns3_restore_tqp_enable_state(hw);
5906 * When finished the initialization, enable queues to receive
5907 * and transmit packets.
5909 hns3_enable_all_queues(hw, true);
5916 hns3_restore_conf(struct hns3_adapter *hns)
5918 struct hns3_hw *hw = &hns->hw;
5921 ret = hns3_configure_all_mac_addr(hns, false);
5925 ret = hns3_configure_all_mc_mac_addr(hns, false);
5929 ret = hns3_dev_promisc_restore(hns);
5933 ret = hns3_restore_vlan_table(hns);
5937 ret = hns3_restore_vlan_conf(hns);
5941 ret = hns3_restore_all_fdir_filter(hns);
5945 ret = hns3_restore_rx_interrupt(hw);
5949 ret = hns3_restore_gro_conf(hw);
5953 ret = hns3_restore_fec(hw);
5957 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5958 ret = hns3_do_start(hns, false);
5961 hns3_info(hw, "hns3 dev restart successful!");
5962 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5963 hw->adapter_state = HNS3_NIC_CONFIGURED;
5967 hns3_configure_all_mc_mac_addr(hns, true);
5969 hns3_configure_all_mac_addr(hns, true);
5974 hns3_reset_service(void *param)
5976 struct hns3_adapter *hns = (struct hns3_adapter *)param;
5977 struct hns3_hw *hw = &hns->hw;
5978 enum hns3_reset_level reset_level;
5979 struct timeval tv_delta;
5980 struct timeval tv_start;
5986 * The interrupt is not triggered within the delay time.
5987 * The interrupt may have been lost. It is necessary to handle
5988 * the interrupt to recover from the error.
5990 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
5991 SCHEDULE_DEFERRED) {
5992 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
5994 hns3_err(hw, "Handling interrupts in delayed tasks");
5995 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5996 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5997 if (reset_level == HNS3_NONE_RESET) {
5998 hns3_err(hw, "No reset level is set, try IMP reset");
5999 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6002 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6005 * Check if there is any ongoing reset in the hardware. This status can
6006 * be checked from reset_pending. If there is then, we need to wait for
6007 * hardware to complete reset.
6008 * a. If we are able to figure out in reasonable time that hardware
6009 * has fully resetted then, we can proceed with driver, client
6011 * b. else, we can come back later to check this status so re-sched
6014 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6015 if (reset_level != HNS3_NONE_RESET) {
6016 gettimeofday(&tv_start, NULL);
6017 ret = hns3_reset_process(hns, reset_level);
6018 gettimeofday(&tv, NULL);
6019 timersub(&tv, &tv_start, &tv_delta);
6020 msec = tv_delta.tv_sec * MSEC_PER_SEC +
6021 tv_delta.tv_usec / USEC_PER_MSEC;
6022 if (msec > HNS3_RESET_PROCESS_MS)
6023 hns3_err(hw, "%d handle long time delta %" PRIx64
6024 " ms time=%ld.%.6ld",
6025 hw->reset.level, msec,
6026 tv.tv_sec, tv.tv_usec);
6031 /* Check if we got any *new* reset requests to be honored */
6032 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6033 if (reset_level != HNS3_NONE_RESET)
6034 hns3_msix_process(hns, reset_level);
6038 hns3_get_speed_capa_num(uint16_t device_id)
6042 switch (device_id) {
6043 case HNS3_DEV_ID_25GE:
6044 case HNS3_DEV_ID_25GE_RDMA:
6047 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6048 case HNS3_DEV_ID_200G_RDMA:
6060 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6063 switch (device_id) {
6064 case HNS3_DEV_ID_25GE:
6066 case HNS3_DEV_ID_25GE_RDMA:
6067 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6068 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6070 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6071 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6072 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6074 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6075 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6076 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6078 case HNS3_DEV_ID_200G_RDMA:
6079 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6080 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6090 hns3_fec_get_capability(struct rte_eth_dev *dev,
6091 struct rte_eth_fec_capa *speed_fec_capa,
6094 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6095 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6096 uint16_t device_id = pci_dev->id.device_id;
6097 unsigned int capa_num;
6100 capa_num = hns3_get_speed_capa_num(device_id);
6101 if (capa_num == 0) {
6102 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6107 if (speed_fec_capa == NULL || num < capa_num)
6110 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6118 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6120 struct hns3_config_fec_cmd *req;
6121 struct hns3_cmd_desc desc;
6125 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6126 * in device of link speed
6129 if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6134 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6135 req = (struct hns3_config_fec_cmd *)desc.data;
6136 ret = hns3_cmd_send(hw, &desc, 1);
6138 hns3_err(hw, "get current fec auto state failed, ret = %d",
6143 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6148 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6150 #define QUERY_ACTIVE_SPEED 1
6151 struct hns3_sfp_speed_cmd *resp;
6152 uint32_t tmp_fec_capa;
6154 struct hns3_cmd_desc desc;
6158 * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6159 * configured FEC mode is returned.
6160 * If link is up, current FEC mode is returned.
6162 if (hw->mac.link_status == ETH_LINK_DOWN) {
6163 ret = get_current_fec_auto_state(hw, &auto_state);
6167 if (auto_state == 0x1) {
6168 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6173 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
6174 resp = (struct hns3_sfp_speed_cmd *)desc.data;
6175 resp->query_type = QUERY_ACTIVE_SPEED;
6177 ret = hns3_cmd_send(hw, &desc, 1);
6178 if (ret == -EOPNOTSUPP) {
6179 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6182 hns3_err(hw, "get FEC failed, ret = %d", ret);
6187 * FEC mode order defined in hns3 hardware is inconsistend with
6188 * that defined in the ethdev library. So the sequence needs
6191 switch (resp->active_fec) {
6192 case HNS3_HW_FEC_MODE_NOFEC:
6193 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6195 case HNS3_HW_FEC_MODE_BASER:
6196 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6198 case HNS3_HW_FEC_MODE_RS:
6199 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6202 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6206 *fec_capa = tmp_fec_capa;
6211 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6213 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6215 return hns3_fec_get_internal(hw, fec_capa);
6219 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6221 struct hns3_config_fec_cmd *req;
6222 struct hns3_cmd_desc desc;
6225 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6227 req = (struct hns3_config_fec_cmd *)desc.data;
6229 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6230 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6231 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6233 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6234 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6235 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6237 case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6238 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6239 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6241 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6242 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6247 ret = hns3_cmd_send(hw, &desc, 1);
6249 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6255 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6257 struct hns3_mac *mac = &hw->mac;
6260 switch (mac->link_speed) {
6261 case ETH_SPEED_NUM_10G:
6262 cur_capa = fec_capa[1].capa;
6264 case ETH_SPEED_NUM_25G:
6265 case ETH_SPEED_NUM_100G:
6266 case ETH_SPEED_NUM_200G:
6267 cur_capa = fec_capa[0].capa;
6278 is_fec_mode_one_bit_set(uint32_t mode)
6283 for (i = 0; i < sizeof(mode); i++)
6284 if (mode >> i & 0x1)
6287 return cnt == 1 ? true : false;
6291 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6293 #define FEC_CAPA_NUM 2
6294 struct hns3_adapter *hns = dev->data->dev_private;
6295 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6296 struct hns3_pf *pf = &hns->pf;
6298 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6300 uint32_t num = FEC_CAPA_NUM;
6303 ret = hns3_fec_get_capability(dev, fec_capa, num);
6307 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6308 if (!is_fec_mode_one_bit_set(mode))
6309 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6310 "FEC mode should be only one bit set", mode);
6313 * Check whether the configured mode is within the FEC capability.
6314 * If not, the configured mode will not be supported.
6316 cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6317 if (!(cur_capa & mode)) {
6318 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6322 ret = hns3_set_fec_hw(hw, mode);
6326 pf->fec_mode = mode;
6331 hns3_restore_fec(struct hns3_hw *hw)
6333 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6334 struct hns3_pf *pf = &hns->pf;
6335 uint32_t mode = pf->fec_mode;
6338 ret = hns3_set_fec_hw(hw, mode);
6340 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6347 hns3_query_dev_fec_info(struct hns3_hw *hw)
6349 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6350 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6353 ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6355 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6361 hns3_optical_module_existed(struct hns3_hw *hw)
6363 struct hns3_cmd_desc desc;
6367 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
6368 ret = hns3_cmd_send(hw, &desc, 1);
6371 "fail to get optical module exist state, ret = %d.\n",
6375 existed = !!desc.data[0];
6381 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
6382 uint32_t len, uint8_t *data)
6384 #define HNS3_SFP_INFO_CMD_NUM 6
6385 #define HNS3_SFP_INFO_MAX_LEN \
6386 (HNS3_SFP_INFO_BD0_LEN + \
6387 (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
6388 struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
6389 struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
6395 for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6396 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
6398 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
6399 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
6402 sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
6403 sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
6404 read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
6405 sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
6407 ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
6409 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
6414 /* The data format in BD0 is different with the others. */
6415 copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
6416 memcpy(data, sfp_info_bd0->data, copy_len);
6417 read_len = copy_len;
6419 for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6420 if (read_len >= len)
6423 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
6424 memcpy(data + read_len, desc[i].data, copy_len);
6425 read_len += copy_len;
6428 return (int)read_len;
6432 hns3_get_module_eeprom(struct rte_eth_dev *dev,
6433 struct rte_dev_eeprom_info *info)
6435 struct hns3_adapter *hns = dev->data->dev_private;
6436 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6437 uint32_t offset = info->offset;
6438 uint32_t len = info->length;
6439 uint8_t *data = info->data;
6440 uint32_t read_len = 0;
6442 if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
6445 if (!hns3_optical_module_existed(hw)) {
6446 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
6450 while (read_len < len) {
6452 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
6464 hns3_get_module_info(struct rte_eth_dev *dev,
6465 struct rte_eth_dev_module_info *modinfo)
6467 #define HNS3_SFF8024_ID_SFP 0x03
6468 #define HNS3_SFF8024_ID_QSFP_8438 0x0c
6469 #define HNS3_SFF8024_ID_QSFP_8436_8636 0x0d
6470 #define HNS3_SFF8024_ID_QSFP28_8636 0x11
6471 #define HNS3_SFF_8636_V1_3 0x03
6472 struct hns3_adapter *hns = dev->data->dev_private;
6473 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6474 struct rte_dev_eeprom_info info;
6475 struct hns3_sfp_type sfp_type;
6478 memset(&sfp_type, 0, sizeof(sfp_type));
6479 memset(&info, 0, sizeof(info));
6480 info.data = (uint8_t *)&sfp_type;
6481 info.length = sizeof(sfp_type);
6482 ret = hns3_get_module_eeprom(dev, &info);
6486 switch (sfp_type.type) {
6487 case HNS3_SFF8024_ID_SFP:
6488 modinfo->type = RTE_ETH_MODULE_SFF_8472;
6489 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
6491 case HNS3_SFF8024_ID_QSFP_8438:
6492 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6493 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6495 case HNS3_SFF8024_ID_QSFP_8436_8636:
6496 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
6497 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6498 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6500 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6501 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6504 case HNS3_SFF8024_ID_QSFP28_8636:
6505 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6506 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6509 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
6510 sfp_type.type, sfp_type.ext_type);
6518 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
6520 uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
6524 if (strcmp(value, "vec") == 0)
6525 hint = HNS3_IO_FUNC_HINT_VEC;
6526 else if (strcmp(value, "sve") == 0)
6527 hint = HNS3_IO_FUNC_HINT_SVE;
6528 else if (strcmp(value, "simple") == 0)
6529 hint = HNS3_IO_FUNC_HINT_SIMPLE;
6530 else if (strcmp(value, "common") == 0)
6531 hint = HNS3_IO_FUNC_HINT_COMMON;
6533 /* If the hint is valid then update output parameters */
6534 if (hint != HNS3_IO_FUNC_HINT_NONE)
6535 *(uint32_t *)extra_args = hint;
6541 hns3_get_io_hint_func_name(uint32_t hint)
6544 case HNS3_IO_FUNC_HINT_VEC:
6546 case HNS3_IO_FUNC_HINT_SVE:
6548 case HNS3_IO_FUNC_HINT_SIMPLE:
6550 case HNS3_IO_FUNC_HINT_COMMON:
6558 hns3_parse_devargs(struct rte_eth_dev *dev)
6560 struct hns3_adapter *hns = dev->data->dev_private;
6561 uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
6562 uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
6563 struct hns3_hw *hw = &hns->hw;
6564 struct rte_kvargs *kvlist;
6566 if (dev->device->devargs == NULL)
6569 kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
6573 rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
6574 &hns3_parse_io_hint_func, &rx_func_hint);
6575 rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
6576 &hns3_parse_io_hint_func, &tx_func_hint);
6577 rte_kvargs_free(kvlist);
6579 if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
6580 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
6581 hns3_get_io_hint_func_name(rx_func_hint));
6582 hns->rx_func_hint = rx_func_hint;
6583 if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
6584 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
6585 hns3_get_io_hint_func_name(tx_func_hint));
6586 hns->tx_func_hint = tx_func_hint;
6589 static const struct eth_dev_ops hns3_eth_dev_ops = {
6590 .dev_configure = hns3_dev_configure,
6591 .dev_start = hns3_dev_start,
6592 .dev_stop = hns3_dev_stop,
6593 .dev_close = hns3_dev_close,
6594 .promiscuous_enable = hns3_dev_promiscuous_enable,
6595 .promiscuous_disable = hns3_dev_promiscuous_disable,
6596 .allmulticast_enable = hns3_dev_allmulticast_enable,
6597 .allmulticast_disable = hns3_dev_allmulticast_disable,
6598 .mtu_set = hns3_dev_mtu_set,
6599 .stats_get = hns3_stats_get,
6600 .stats_reset = hns3_stats_reset,
6601 .xstats_get = hns3_dev_xstats_get,
6602 .xstats_get_names = hns3_dev_xstats_get_names,
6603 .xstats_reset = hns3_dev_xstats_reset,
6604 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
6605 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6606 .dev_infos_get = hns3_dev_infos_get,
6607 .fw_version_get = hns3_fw_version_get,
6608 .rx_queue_setup = hns3_rx_queue_setup,
6609 .tx_queue_setup = hns3_tx_queue_setup,
6610 .rx_queue_release = hns3_dev_rx_queue_release,
6611 .tx_queue_release = hns3_dev_tx_queue_release,
6612 .rx_queue_start = hns3_dev_rx_queue_start,
6613 .rx_queue_stop = hns3_dev_rx_queue_stop,
6614 .tx_queue_start = hns3_dev_tx_queue_start,
6615 .tx_queue_stop = hns3_dev_tx_queue_stop,
6616 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
6617 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
6618 .rxq_info_get = hns3_rxq_info_get,
6619 .txq_info_get = hns3_txq_info_get,
6620 .rx_burst_mode_get = hns3_rx_burst_mode_get,
6621 .tx_burst_mode_get = hns3_tx_burst_mode_get,
6622 .flow_ctrl_get = hns3_flow_ctrl_get,
6623 .flow_ctrl_set = hns3_flow_ctrl_set,
6624 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6625 .mac_addr_add = hns3_add_mac_addr,
6626 .mac_addr_remove = hns3_remove_mac_addr,
6627 .mac_addr_set = hns3_set_default_mac_addr,
6628 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
6629 .link_update = hns3_dev_link_update,
6630 .rss_hash_update = hns3_dev_rss_hash_update,
6631 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
6632 .reta_update = hns3_dev_rss_reta_update,
6633 .reta_query = hns3_dev_rss_reta_query,
6634 .flow_ops_get = hns3_dev_flow_ops_get,
6635 .vlan_filter_set = hns3_vlan_filter_set,
6636 .vlan_tpid_set = hns3_vlan_tpid_set,
6637 .vlan_offload_set = hns3_vlan_offload_set,
6638 .vlan_pvid_set = hns3_vlan_pvid_set,
6639 .get_reg = hns3_get_regs,
6640 .get_module_info = hns3_get_module_info,
6641 .get_module_eeprom = hns3_get_module_eeprom,
6642 .get_dcb_info = hns3_get_dcb_info,
6643 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6644 .fec_get_capability = hns3_fec_get_capability,
6645 .fec_get = hns3_fec_get,
6646 .fec_set = hns3_fec_set,
6647 .tm_ops_get = hns3_tm_ops_get,
6648 .tx_done_cleanup = hns3_tx_done_cleanup,
6651 static const struct hns3_reset_ops hns3_reset_ops = {
6652 .reset_service = hns3_reset_service,
6653 .stop_service = hns3_stop_service,
6654 .prepare_reset = hns3_prepare_reset,
6655 .wait_hardware_ready = hns3_wait_hardware_ready,
6656 .reinit_dev = hns3_reinit_dev,
6657 .restore_conf = hns3_restore_conf,
6658 .start_service = hns3_start_service,
6662 hns3_dev_init(struct rte_eth_dev *eth_dev)
6664 struct hns3_adapter *hns = eth_dev->data->dev_private;
6665 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6666 struct rte_ether_addr *eth_addr;
6667 struct hns3_hw *hw = &hns->hw;
6670 PMD_INIT_FUNC_TRACE();
6672 eth_dev->process_private = (struct hns3_process_private *)
6673 rte_zmalloc_socket("hns3_filter_list",
6674 sizeof(struct hns3_process_private),
6675 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6676 if (eth_dev->process_private == NULL) {
6677 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6680 /* initialize flow filter lists */
6681 hns3_filterlist_init(eth_dev);
6683 hns3_set_rxtx_function(eth_dev);
6684 eth_dev->dev_ops = &hns3_eth_dev_ops;
6685 eth_dev->rx_queue_count = hns3_rx_queue_count;
6686 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6687 ret = hns3_mp_init_secondary();
6689 PMD_INIT_LOG(ERR, "Failed to init for secondary "
6690 "process, ret = %d", ret);
6691 goto err_mp_init_secondary;
6694 hw->secondary_cnt++;
6698 ret = hns3_mp_init_primary();
6701 "Failed to init for primary process, ret = %d",
6703 goto err_mp_init_primary;
6706 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6708 hw->data = eth_dev->data;
6709 hns3_parse_devargs(eth_dev);
6712 * Set default max packet size according to the mtu
6713 * default vale in DPDK frame.
6715 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6717 ret = hns3_reset_init(hw);
6719 goto err_init_reset;
6720 hw->reset.ops = &hns3_reset_ops;
6722 ret = hns3_init_pf(eth_dev);
6724 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6728 /* Allocate memory for storing MAC addresses */
6729 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6730 sizeof(struct rte_ether_addr) *
6731 HNS3_UC_MACADDR_NUM, 0);
6732 if (eth_dev->data->mac_addrs == NULL) {
6733 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6734 "to store MAC addresses",
6735 sizeof(struct rte_ether_addr) *
6736 HNS3_UC_MACADDR_NUM);
6738 goto err_rte_zmalloc;
6741 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6742 if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6743 rte_eth_random_addr(hw->mac.mac_addr);
6744 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6745 (struct rte_ether_addr *)hw->mac.mac_addr);
6746 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6747 "unicast address, using random MAC address %s",
6750 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6751 ð_dev->data->mac_addrs[0]);
6753 hw->adapter_state = HNS3_NIC_INITIALIZED;
6755 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6757 hns3_err(hw, "Reschedule reset service after dev_init");
6758 hns3_schedule_reset(hns);
6760 /* IMP will wait ready flag before reset */
6761 hns3_notify_reset_ready(hw, false);
6764 hns3_info(hw, "hns3 dev initialization successful!");
6768 hns3_uninit_pf(eth_dev);
6771 rte_free(hw->reset.wait_data);
6774 hns3_mp_uninit_primary();
6776 err_mp_init_primary:
6777 err_mp_init_secondary:
6778 eth_dev->dev_ops = NULL;
6779 eth_dev->rx_pkt_burst = NULL;
6780 eth_dev->rx_descriptor_status = NULL;
6781 eth_dev->tx_pkt_burst = NULL;
6782 eth_dev->tx_pkt_prepare = NULL;
6783 eth_dev->tx_descriptor_status = NULL;
6784 rte_free(eth_dev->process_private);
6785 eth_dev->process_private = NULL;
6790 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6792 struct hns3_adapter *hns = eth_dev->data->dev_private;
6793 struct hns3_hw *hw = &hns->hw;
6795 PMD_INIT_FUNC_TRACE();
6797 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6798 rte_free(eth_dev->process_private);
6799 eth_dev->process_private = NULL;
6803 if (hw->adapter_state < HNS3_NIC_CLOSING)
6804 hns3_dev_close(eth_dev);
6806 hw->adapter_state = HNS3_NIC_REMOVED;
6811 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6812 struct rte_pci_device *pci_dev)
6814 return rte_eth_dev_pci_generic_probe(pci_dev,
6815 sizeof(struct hns3_adapter),
6820 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6822 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6825 static const struct rte_pci_id pci_id_hns3_map[] = {
6826 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6827 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6828 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6829 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6830 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6831 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6832 { .vendor_id = 0, }, /* sentinel */
6835 static struct rte_pci_driver rte_hns3_pmd = {
6836 .id_table = pci_id_hns3_map,
6837 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6838 .probe = eth_hns3_pci_probe,
6839 .remove = eth_hns3_pci_remove,
6842 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6843 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6844 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6845 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
6846 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
6847 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common ");
6848 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6849 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);