drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9 #include <rte_kvargs.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18
  19 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  20 #define HNS3_SERVICE_QUICK_INTERVAL     10
  21 #define HNS3_INVALID_PVID               0xFFFF
  22
  23 #define HNS3_FILTER_TYPE_VF             0
  24 #define HNS3_FILTER_TYPE_PORT           1
  25 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  26 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  27 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  28 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  29 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  30 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  31                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  32 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  33                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  34
  35 /* Reset related Registers */
  36 #define HNS3_GLOBAL_RESET_BIT           0
  37 #define HNS3_CORE_RESET_BIT             1
  38 #define HNS3_IMP_RESET_BIT              2
  39 #define HNS3_FUN_RST_ING_B              0
  40
  41 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  42 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  43 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  44 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  45
  46 #define HNS3_RESET_WAIT_MS      100
  47 #define HNS3_RESET_WAIT_CNT     200
  48
  49 /* FEC mode order defined in HNS3 hardware */
  50 #define HNS3_HW_FEC_MODE_NOFEC  0
  51 #define HNS3_HW_FEC_MODE_BASER  1
  52 #define HNS3_HW_FEC_MODE_RS     2
  53
  54 enum hns3_evt_cause {
  55         HNS3_VECTOR0_EVENT_RST,
  56         HNS3_VECTOR0_EVENT_MBX,
  57         HNS3_VECTOR0_EVENT_ERR,
  58         HNS3_VECTOR0_EVENT_PTP,
  59         HNS3_VECTOR0_EVENT_OTHER,
  60 };
  61
  62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  63         { RTE_ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  64                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  66
  67         { RTE_ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  71
  72         { RTE_ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  75
  76         { RTE_ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  80
  81         { RTE_ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  82                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  84
  85         { RTE_ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  88 };
  89
  90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  91                                                  uint64_t *levels);
  92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  94                                     int on);
  95 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  96 static bool hns3_update_link_status(struct hns3_hw *hw);
  97
  98 static int hns3_add_mc_mac_addr(struct hns3_hw *hw,
  99                                 struct rte_ether_addr *mac_addr);
 100 static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 101                                    struct rte_ether_addr *mac_addr);
 102 static int hns3_restore_fec(struct hns3_hw *hw);
 103 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 104 static int hns3_do_stop(struct hns3_adapter *hns);
 105 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
 106 static int hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable);
 107
 108 void hns3_ether_format_addr(char *buf, uint16_t size,
 109                             const struct rte_ether_addr *ether_addr)
 110 {
 111         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 112                 ether_addr->addr_bytes[0],
 113                 ether_addr->addr_bytes[4],
 114                 ether_addr->addr_bytes[5]);
 115 }
 116
 117 static void
 118 hns3_pf_disable_irq0(struct hns3_hw *hw)
 119 {
 120         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 121 }
 122
 123 static void
 124 hns3_pf_enable_irq0(struct hns3_hw *hw)
 125 {
 126         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 127 }
 128
 129 static enum hns3_evt_cause
 130 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 131                           uint32_t *vec_val)
 132 {
 133         struct hns3_hw *hw = &hns->hw;
 134
 135         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 136         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 137         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 138         if (!is_delay) {
 139                 hw->reset.stats.imp_cnt++;
 140                 hns3_warn(hw, "IMP reset detected, clear reset status");
 141         } else {
 142                 hns3_schedule_delayed_reset(hns);
 143                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 144         }
 145
 146         return HNS3_VECTOR0_EVENT_RST;
 147 }
 148
 149 static enum hns3_evt_cause
 150 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 151                              uint32_t *vec_val)
 152 {
 153         struct hns3_hw *hw = &hns->hw;
 154
 155         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 156         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 157         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 158         if (!is_delay) {
 159                 hw->reset.stats.global_cnt++;
 160                 hns3_warn(hw, "Global reset detected, clear reset status");
 161         } else {
 162                 hns3_schedule_delayed_reset(hns);
 163                 hns3_warn(hw,
 164                           "Global reset detected, don't clear reset status");
 165         }
 166
 167         return HNS3_VECTOR0_EVENT_RST;
 168 }
 169
 170 static enum hns3_evt_cause
 171 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 172 {
 173         struct hns3_hw *hw = &hns->hw;
 174         uint32_t vector0_int_stats;
 175         uint32_t cmdq_src_val;
 176         uint32_t hw_err_src_reg;
 177         uint32_t val;
 178         enum hns3_evt_cause ret;
 179         bool is_delay;
 180
 181         /* fetch the events from their corresponding regs */
 182         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 183         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 184         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 185
 186         is_delay = clearval == NULL ? true : false;
 187         /*
 188          * Assumption: If by any chance reset and mailbox events are reported
 189          * together then we will only process reset event and defer the
 190          * processing of the mailbox events. Since, we would have not cleared
 191          * RX CMDQ event this time we would receive again another interrupt
 192          * from H/W just for the mailbox.
 193          */
 194         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 195                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 196                 goto out;
 197         }
 198
 199         /* Global reset */
 200         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 201                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 202                 goto out;
 203         }
 204
 205         /* Check for vector0 1588 event source */
 206         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
 207                 val = BIT(HNS3_VECTOR0_1588_INT_B);
 208                 ret = HNS3_VECTOR0_EVENT_PTP;
 209                 goto out;
 210         }
 211
 212         /* check for vector0 msix event source */
 213         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 214             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 215                 val = vector0_int_stats | hw_err_src_reg;
 216                 ret = HNS3_VECTOR0_EVENT_ERR;
 217                 goto out;
 218         }
 219
 220         /* check for vector0 mailbox(=CMDQ RX) event source */
 221         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 222                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 223                 val = cmdq_src_val;
 224                 ret = HNS3_VECTOR0_EVENT_MBX;
 225                 goto out;
 226         }
 227
 228         val = vector0_int_stats;
 229         ret = HNS3_VECTOR0_EVENT_OTHER;
 230 out:
 231
 232         if (clearval)
 233                 *clearval = val;
 234         return ret;
 235 }
 236
 237 static bool
 238 hns3_is_1588_event_type(uint32_t event_type)
 239 {
 240         return (event_type == HNS3_VECTOR0_EVENT_PTP);
 241 }
 242
 243 static void
 244 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 245 {
 246         if (event_type == HNS3_VECTOR0_EVENT_RST ||
 247             hns3_is_1588_event_type(event_type))
 248                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 249         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 250                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 251 }
 252
 253 static void
 254 hns3_clear_all_event_cause(struct hns3_hw *hw)
 255 {
 256         uint32_t vector0_int_stats;
 257
 258         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 259         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 260                 hns3_warn(hw, "Probe during IMP reset interrupt");
 261
 262         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 263                 hns3_warn(hw, "Probe during Global reset interrupt");
 264
 265         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 266                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 267                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 268                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 269         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 270         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
 271                                 BIT(HNS3_VECTOR0_1588_INT_B));
 272 }
 273
 274 static void
 275 hns3_handle_mac_tnl(struct hns3_hw *hw)
 276 {
 277         struct hns3_cmd_desc desc;
 278         uint32_t status;
 279         int ret;
 280
 281         /* query and clear mac tnl interrupt */
 282         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 283         ret = hns3_cmd_send(hw, &desc, 1);
 284         if (ret) {
 285                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 286                 return;
 287         }
 288
 289         status = rte_le_to_cpu_32(desc.data[0]);
 290         if (status) {
 291                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 292                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 293                                           false);
 294                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 295                 ret = hns3_cmd_send(hw, &desc, 1);
 296                 if (ret)
 297                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 298                                  ret);
 299         }
 300 }
 301
 302 static void
 303 hns3_interrupt_handler(void *param)
 304 {
 305         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 306         struct hns3_adapter *hns = dev->data->dev_private;
 307         struct hns3_hw *hw = &hns->hw;
 308         enum hns3_evt_cause event_cause;
 309         uint32_t clearval = 0;
 310         uint32_t vector0_int;
 311         uint32_t ras_int;
 312         uint32_t cmdq_int;
 313
 314         /* Disable interrupt */
 315         hns3_pf_disable_irq0(hw);
 316
 317         event_cause = hns3_check_event_cause(hns, &clearval);
 318         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 319         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 320         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 321         hns3_clear_event_cause(hw, event_cause, clearval);
 322         /* vector 0 interrupt is shared with reset and mailbox source events. */
 323         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 324                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 325                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 326                           vector0_int, ras_int, cmdq_int);
 327                 hns3_handle_mac_tnl(hw);
 328                 hns3_handle_error(hns);
 329         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 330                 hns3_warn(hw, "received reset interrupt");
 331                 hns3_schedule_reset(hns);
 332         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 333                 hns3_dev_handle_mbx_msg(hw);
 334         } else {
 335                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 336                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 337                           vector0_int, ras_int, cmdq_int);
 338         }
 339
 340         /* Enable interrupt if it is not cause by reset */
 341         hns3_pf_enable_irq0(hw);
 342 }
 343
 344 static int
 345 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 346 {
 347 #define HNS3_VLAN_ID_OFFSET_STEP        160
 348 #define HNS3_VLAN_BYTE_SIZE             8
 349         struct hns3_vlan_filter_pf_cfg_cmd *req;
 350         struct hns3_hw *hw = &hns->hw;
 351         uint8_t vlan_offset_byte_val;
 352         struct hns3_cmd_desc desc;
 353         uint8_t vlan_offset_byte;
 354         uint8_t vlan_offset_base;
 355         int ret;
 356
 357         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 358
 359         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 360         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 361                            HNS3_VLAN_BYTE_SIZE;
 362         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 363
 364         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 365         req->vlan_offset = vlan_offset_base;
 366         req->vlan_cfg = on ? 0 : 1;
 367         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 368
 369         ret = hns3_cmd_send(hw, &desc, 1);
 370         if (ret)
 371                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 372                          vlan_id, ret);
 373
 374         return ret;
 375 }
 376
 377 static void
 378 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 379 {
 380         struct hns3_user_vlan_table *vlan_entry;
 381         struct hns3_pf *pf = &hns->pf;
 382
 383         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 384                 if (vlan_entry->vlan_id == vlan_id) {
 385                         if (vlan_entry->hd_tbl_status)
 386                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 387                         LIST_REMOVE(vlan_entry, next);
 388                         rte_free(vlan_entry);
 389                         break;
 390                 }
 391         }
 392 }
 393
 394 static void
 395 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 396                         bool writen_to_tbl)
 397 {
 398         struct hns3_user_vlan_table *vlan_entry;
 399         struct hns3_hw *hw = &hns->hw;
 400         struct hns3_pf *pf = &hns->pf;
 401
 402         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 403                 if (vlan_entry->vlan_id == vlan_id)
 404                         return;
 405         }
 406
 407         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 408         if (vlan_entry == NULL) {
 409                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 410                 return;
 411         }
 412
 413         vlan_entry->hd_tbl_status = writen_to_tbl;
 414         vlan_entry->vlan_id = vlan_id;
 415
 416         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 417 }
 418
 419 static int
 420 hns3_restore_vlan_table(struct hns3_adapter *hns)
 421 {
 422         struct hns3_user_vlan_table *vlan_entry;
 423         struct hns3_hw *hw = &hns->hw;
 424         struct hns3_pf *pf = &hns->pf;
 425         uint16_t vlan_id;
 426         int ret = 0;
 427
 428         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 429                 return hns3_vlan_pvid_configure(hns,
 430                                                 hw->port_base_vlan_cfg.pvid, 1);
 431
 432         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 433                 if (vlan_entry->hd_tbl_status) {
 434                         vlan_id = vlan_entry->vlan_id;
 435                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 436                         if (ret)
 437                                 break;
 438                 }
 439         }
 440
 441         return ret;
 442 }
 443
 444 static int
 445 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 446 {
 447         struct hns3_hw *hw = &hns->hw;
 448         bool writen_to_tbl = false;
 449         int ret = 0;
 450
 451         /*
 452          * When vlan filter is enabled, hardware regards packets without vlan
 453          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 454          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 455          */
 456         if (on == 0 && vlan_id == 0)
 457                 return 0;
 458
 459         /*
 460          * When port base vlan enabled, we use port base vlan as the vlan
 461          * filter condition. In this case, we don't update vlan filter table
 462          * when user add new vlan or remove exist vlan, just update the
 463          * vlan list. The vlan id in vlan list will be written in vlan filter
 464          * table until port base vlan disabled
 465          */
 466         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 467                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 468                 writen_to_tbl = true;
 469         }
 470
 471         if (ret == 0) {
 472                 if (on)
 473                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 474                 else
 475                         hns3_rm_dev_vlan_table(hns, vlan_id);
 476         }
 477         return ret;
 478 }
 479
 480 static int
 481 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 482 {
 483         struct hns3_adapter *hns = dev->data->dev_private;
 484         struct hns3_hw *hw = &hns->hw;
 485         int ret;
 486
 487         rte_spinlock_lock(&hw->lock);
 488         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 489         rte_spinlock_unlock(&hw->lock);
 490         return ret;
 491 }
 492
 493 static int
 494 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 495                          uint16_t tpid)
 496 {
 497         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 498         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 499         struct hns3_hw *hw = &hns->hw;
 500         struct hns3_cmd_desc desc;
 501         int ret;
 502
 503         if ((vlan_type != RTE_ETH_VLAN_TYPE_INNER &&
 504              vlan_type != RTE_ETH_VLAN_TYPE_OUTER)) {
 505                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 506                 return -EINVAL;
 507         }
 508
 509         if (tpid != RTE_ETHER_TYPE_VLAN) {
 510                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 511                 return -EINVAL;
 512         }
 513
 514         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 515         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 516
 517         if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) {
 518                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 519                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 520         } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) {
 521                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 522                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 523                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 524                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 525         }
 526
 527         ret = hns3_cmd_send(hw, &desc, 1);
 528         if (ret) {
 529                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 530                          ret);
 531                 return ret;
 532         }
 533
 534         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 535
 536         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 537         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 538         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 539
 540         ret = hns3_cmd_send(hw, &desc, 1);
 541         if (ret)
 542                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 543                          ret);
 544         return ret;
 545 }
 546
 547 static int
 548 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 549                    uint16_t tpid)
 550 {
 551         struct hns3_adapter *hns = dev->data->dev_private;
 552         struct hns3_hw *hw = &hns->hw;
 553         int ret;
 554
 555         rte_spinlock_lock(&hw->lock);
 556         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 557         rte_spinlock_unlock(&hw->lock);
 558         return ret;
 559 }
 560
 561 static int
 562 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 563                              struct hns3_rx_vtag_cfg *vcfg)
 564 {
 565         struct hns3_vport_vtag_rx_cfg_cmd *req;
 566         struct hns3_hw *hw = &hns->hw;
 567         struct hns3_cmd_desc desc;
 568         uint16_t vport_id;
 569         uint8_t bitmap;
 570         int ret;
 571
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 573
 574         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 575         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 576                      vcfg->strip_tag1_en ? 1 : 0);
 577         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 578                      vcfg->strip_tag2_en ? 1 : 0);
 579         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 580                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 581         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 582                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 583
 584         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 585         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 586                      vcfg->strip_tag1_discard_en ? 1 : 0);
 587         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 588                      vcfg->strip_tag2_discard_en ? 1 : 0);
 589         /*
 590          * In current version VF is not supported when PF is driven by DPDK
 591          * driver, just need to configure parameters for PF vport.
 592          */
 593         vport_id = HNS3_PF_FUNC_ID;
 594         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 595         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 596         req->vf_bitmap[req->vf_offset] = bitmap;
 597
 598         ret = hns3_cmd_send(hw, &desc, 1);
 599         if (ret)
 600                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 601         return ret;
 602 }
 603
 604 static void
 605 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 606                            struct hns3_rx_vtag_cfg *vcfg)
 607 {
 608         struct hns3_pf *pf = &hns->pf;
 609         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 610 }
 611
 612 static void
 613 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 614                            struct hns3_tx_vtag_cfg *vcfg)
 615 {
 616         struct hns3_pf *pf = &hns->pf;
 617         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 618 }
 619
 620 static int
 621 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 622 {
 623         struct hns3_rx_vtag_cfg rxvlan_cfg;
 624         struct hns3_hw *hw = &hns->hw;
 625         int ret;
 626
 627         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 628                 rxvlan_cfg.strip_tag1_en = false;
 629                 rxvlan_cfg.strip_tag2_en = enable;
 630                 rxvlan_cfg.strip_tag2_discard_en = false;
 631         } else {
 632                 rxvlan_cfg.strip_tag1_en = enable;
 633                 rxvlan_cfg.strip_tag2_en = true;
 634                 rxvlan_cfg.strip_tag2_discard_en = true;
 635         }
 636
 637         rxvlan_cfg.strip_tag1_discard_en = false;
 638         rxvlan_cfg.vlan1_vlan_prionly = false;
 639         rxvlan_cfg.vlan2_vlan_prionly = false;
 640         rxvlan_cfg.rx_vlan_offload_en = enable;
 641
 642         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 643         if (ret) {
 644                 hns3_err(hw, "%s strip rx vtag failed, ret = %d.",
 645                                 enable ? "enable" : "disable", ret);
 646                 return ret;
 647         }
 648
 649         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 650
 651         return ret;
 652 }
 653
 654 static int
 655 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 656                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 657 {
 658         struct hns3_vlan_filter_ctrl_cmd *req;
 659         struct hns3_cmd_desc desc;
 660         int ret;
 661
 662         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 663
 664         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 665         req->vlan_type = vlan_type;
 666         req->vlan_fe = filter_en ? fe_type : 0;
 667         req->vf_id = vf_id;
 668
 669         ret = hns3_cmd_send(hw, &desc, 1);
 670         if (ret)
 671                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 672
 673         return ret;
 674 }
 675
 676 static int
 677 hns3_vlan_filter_init(struct hns3_adapter *hns)
 678 {
 679         struct hns3_hw *hw = &hns->hw;
 680         int ret;
 681
 682         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 683                                         HNS3_FILTER_FE_EGRESS, false,
 684                                         HNS3_PF_FUNC_ID);
 685         if (ret) {
 686                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 687                 return ret;
 688         }
 689
 690         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 691                                         HNS3_FILTER_FE_INGRESS, false,
 692                                         HNS3_PF_FUNC_ID);
 693         if (ret)
 694                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 695
 696         return ret;
 697 }
 698
 699 static int
 700 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 701 {
 702         struct hns3_hw *hw = &hns->hw;
 703         int ret;
 704
 705         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 706                                         HNS3_FILTER_FE_INGRESS, enable,
 707                                         HNS3_PF_FUNC_ID);
 708         if (ret)
 709                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 710                          enable ? "enable" : "disable", ret);
 711
 712         return ret;
 713 }
 714
 715 static int
 716 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 717 {
 718         struct hns3_adapter *hns = dev->data->dev_private;
 719         struct hns3_hw *hw = &hns->hw;
 720         struct rte_eth_rxmode *rxmode;
 721         unsigned int tmp_mask;
 722         bool enable;
 723         int ret = 0;
 724
 725         rte_spinlock_lock(&hw->lock);
 726         rxmode = &dev->data->dev_conf.rxmode;
 727         tmp_mask = (unsigned int)mask;
 728         if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
 729                 /* ignore vlan filter configuration during promiscuous mode */
 730                 if (!dev->data->promiscuous) {
 731                         /* Enable or disable VLAN filter */
 732                         enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ?
 733                                  true : false;
 734
 735                         ret = hns3_enable_vlan_filter(hns, enable);
 736                         if (ret) {
 737                                 rte_spinlock_unlock(&hw->lock);
 738                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 739                                          enable ? "enable" : "disable", ret);
 740                                 return ret;
 741                         }
 742                 }
 743         }
 744
 745         if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
 746                 /* Enable or disable VLAN stripping */
 747                 enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ?
 748                     true : false;
 749
 750                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 751                 if (ret) {
 752                         rte_spinlock_unlock(&hw->lock);
 753                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 754                                  enable ? "enable" : "disable", ret);
 755                         return ret;
 756                 }
 757         }
 758
 759         rte_spinlock_unlock(&hw->lock);
 760
 761         return ret;
 762 }
 763
 764 static int
 765 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 766                              struct hns3_tx_vtag_cfg *vcfg)
 767 {
 768         struct hns3_vport_vtag_tx_cfg_cmd *req;
 769         struct hns3_cmd_desc desc;
 770         struct hns3_hw *hw = &hns->hw;
 771         uint16_t vport_id;
 772         uint8_t bitmap;
 773         int ret;
 774
 775         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 776
 777         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 778         req->def_vlan_tag1 = vcfg->default_tag1;
 779         req->def_vlan_tag2 = vcfg->default_tag2;
 780         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 781                      vcfg->accept_tag1 ? 1 : 0);
 782         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 783                      vcfg->accept_untag1 ? 1 : 0);
 784         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 785                      vcfg->accept_tag2 ? 1 : 0);
 786         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 787                      vcfg->accept_untag2 ? 1 : 0);
 788         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 789                      vcfg->insert_tag1_en ? 1 : 0);
 790         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 791                      vcfg->insert_tag2_en ? 1 : 0);
 792         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 793
 794         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 795         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 796                      vcfg->tag_shift_mode_en ? 1 : 0);
 797
 798         /*
 799          * In current version VF is not supported when PF is driven by DPDK
 800          * driver, just need to configure parameters for PF vport.
 801          */
 802         vport_id = HNS3_PF_FUNC_ID;
 803         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 804         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 805         req->vf_bitmap[req->vf_offset] = bitmap;
 806
 807         ret = hns3_cmd_send(hw, &desc, 1);
 808         if (ret)
 809                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 810
 811         return ret;
 812 }
 813
 814 static int
 815 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 816                      uint16_t pvid)
 817 {
 818         struct hns3_hw *hw = &hns->hw;
 819         struct hns3_tx_vtag_cfg txvlan_cfg;
 820         int ret;
 821
 822         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 823                 txvlan_cfg.accept_tag1 = true;
 824                 txvlan_cfg.insert_tag1_en = false;
 825                 txvlan_cfg.default_tag1 = 0;
 826         } else {
 827                 txvlan_cfg.accept_tag1 =
 828                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 829                 txvlan_cfg.insert_tag1_en = true;
 830                 txvlan_cfg.default_tag1 = pvid;
 831         }
 832
 833         txvlan_cfg.accept_untag1 = true;
 834         txvlan_cfg.accept_tag2 = true;
 835         txvlan_cfg.accept_untag2 = true;
 836         txvlan_cfg.insert_tag2_en = false;
 837         txvlan_cfg.default_tag2 = 0;
 838         txvlan_cfg.tag_shift_mode_en = true;
 839
 840         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 841         if (ret) {
 842                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 843                          ret);
 844                 return ret;
 845         }
 846
 847         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 848         return ret;
 849 }
 850
 851
 852 static void
 853 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 854 {
 855         struct hns3_user_vlan_table *vlan_entry;
 856         struct hns3_pf *pf = &hns->pf;
 857
 858         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 859                 if (vlan_entry->hd_tbl_status) {
 860                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 861                         vlan_entry->hd_tbl_status = false;
 862                 }
 863         }
 864
 865         if (is_del_list) {
 866                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 867                 while (vlan_entry) {
 868                         LIST_REMOVE(vlan_entry, next);
 869                         rte_free(vlan_entry);
 870                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 871                 }
 872         }
 873 }
 874
 875 static void
 876 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 877 {
 878         struct hns3_user_vlan_table *vlan_entry;
 879         struct hns3_pf *pf = &hns->pf;
 880
 881         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 882                 if (!vlan_entry->hd_tbl_status) {
 883                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 884                         vlan_entry->hd_tbl_status = true;
 885                 }
 886         }
 887 }
 888
 889 static void
 890 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 891 {
 892         struct hns3_hw *hw = &hns->hw;
 893         int ret;
 894
 895         hns3_rm_all_vlan_table(hns, true);
 896         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 897                 ret = hns3_set_port_vlan_filter(hns,
 898                                                 hw->port_base_vlan_cfg.pvid, 0);
 899                 if (ret) {
 900                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 901                                  ret);
 902                         return;
 903                 }
 904         }
 905 }
 906
 907 static int
 908 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 909                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 910 {
 911         struct hns3_hw *hw = &hns->hw;
 912         uint16_t old_pvid;
 913         int ret;
 914
 915         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 916                 old_pvid = hw->port_base_vlan_cfg.pvid;
 917                 if (old_pvid != HNS3_INVALID_PVID) {
 918                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 919                         if (ret) {
 920                                 hns3_err(hw, "failed to remove old pvid %u, "
 921                                                 "ret = %d", old_pvid, ret);
 922                                 return ret;
 923                         }
 924                 }
 925
 926                 hns3_rm_all_vlan_table(hns, false);
 927                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 928                 if (ret) {
 929                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 930                                         new_pvid, ret);
 931                         return ret;
 932                 }
 933         } else {
 934                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 935                 if (ret) {
 936                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 937                                         new_pvid, ret);
 938                         return ret;
 939                 }
 940
 941                 hns3_add_all_vlan_table(hns);
 942         }
 943         return 0;
 944 }
 945
 946 static int
 947 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 948 {
 949         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 950         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 951         bool rx_strip_en;
 952         int ret;
 953
 954         rx_strip_en = old_cfg->rx_vlan_offload_en;
 955         if (on) {
 956                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 957                 rx_vlan_cfg.strip_tag2_en = true;
 958                 rx_vlan_cfg.strip_tag2_discard_en = true;
 959         } else {
 960                 rx_vlan_cfg.strip_tag1_en = false;
 961                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 962                 rx_vlan_cfg.strip_tag2_discard_en = false;
 963         }
 964         rx_vlan_cfg.strip_tag1_discard_en = false;
 965         rx_vlan_cfg.vlan1_vlan_prionly = false;
 966         rx_vlan_cfg.vlan2_vlan_prionly = false;
 967         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 968
 969         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 970         if (ret)
 971                 return ret;
 972
 973         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 974         return ret;
 975 }
 976
 977 static int
 978 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 979 {
 980         struct hns3_hw *hw = &hns->hw;
 981         uint16_t port_base_vlan_state;
 982         int ret, err;
 983
 984         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 985                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 986                         hns3_warn(hw, "Invalid operation! As current pvid set "
 987                                   "is %u, disable pvid %u is invalid",
 988                                   hw->port_base_vlan_cfg.pvid, pvid);
 989                 return 0;
 990         }
 991
 992         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 993                                     HNS3_PORT_BASE_VLAN_DISABLE;
 994         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 995         if (ret) {
 996                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 997                          ret);
 998                 return ret;
 999         }
1000
1001         ret = hns3_en_pvid_strip(hns, on);
1002         if (ret) {
1003                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1004                          "ret = %d", ret);
1005                 goto pvid_vlan_strip_fail;
1006         }
1007
1008         if (pvid == HNS3_INVALID_PVID)
1009                 goto out;
1010         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1011         if (ret) {
1012                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1013                          ret);
1014                 goto vlan_filter_set_fail;
1015         }
1016
1017 out:
1018         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1019         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1020         return ret;
1021
1022 vlan_filter_set_fail:
1023         err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1024                                         HNS3_PORT_BASE_VLAN_ENABLE);
1025         if (err)
1026                 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1027
1028 pvid_vlan_strip_fail:
1029         err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1030                                         hw->port_base_vlan_cfg.pvid);
1031         if (err)
1032                 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1033
1034         return ret;
1035 }
1036
1037 static int
1038 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1039 {
1040         struct hns3_adapter *hns = dev->data->dev_private;
1041         struct hns3_hw *hw = &hns->hw;
1042         bool pvid_en_state_change;
1043         uint16_t pvid_state;
1044         int ret;
1045
1046         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1047                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1048                          RTE_ETHER_MAX_VLAN_ID);
1049                 return -EINVAL;
1050         }
1051
1052         /*
1053          * If PVID configuration state change, should refresh the PVID
1054          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1055          */
1056         pvid_state = hw->port_base_vlan_cfg.state;
1057         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1058             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1059                 pvid_en_state_change = false;
1060         else
1061                 pvid_en_state_change = true;
1062
1063         rte_spinlock_lock(&hw->lock);
1064         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1065         rte_spinlock_unlock(&hw->lock);
1066         if (ret)
1067                 return ret;
1068         /*
1069          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1070          * need be processed by PMD driver.
1071          */
1072         if (pvid_en_state_change &&
1073             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1074                 hns3_update_all_queues_pvid_proc_en(hw);
1075
1076         return 0;
1077 }
1078
1079 static int
1080 hns3_default_vlan_config(struct hns3_adapter *hns)
1081 {
1082         struct hns3_hw *hw = &hns->hw;
1083         int ret;
1084
1085         /*
1086          * When vlan filter is enabled, hardware regards packets without vlan
1087          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1088          * table, packets without vlan won't be received. So, add vlan 0 as
1089          * the default vlan.
1090          */
1091         ret = hns3_vlan_filter_configure(hns, 0, 1);
1092         if (ret)
1093                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1094         return ret;
1095 }
1096
1097 static int
1098 hns3_init_vlan_config(struct hns3_adapter *hns)
1099 {
1100         struct hns3_hw *hw = &hns->hw;
1101         int ret;
1102
1103         /*
1104          * This function can be called in the initialization and reset process,
1105          * when in reset process, it means that hardware had been reseted
1106          * successfully and we need to restore the hardware configuration to
1107          * ensure that the hardware configuration remains unchanged before and
1108          * after reset.
1109          */
1110         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1111                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1112                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1113         }
1114
1115         ret = hns3_vlan_filter_init(hns);
1116         if (ret) {
1117                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1118                 return ret;
1119         }
1120
1121         ret = hns3_vlan_tpid_configure(hns, RTE_ETH_VLAN_TYPE_INNER,
1122                                        RTE_ETHER_TYPE_VLAN);
1123         if (ret) {
1124                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1125                 return ret;
1126         }
1127
1128         /*
1129          * When in the reinit dev stage of the reset process, the following
1130          * vlan-related configurations may differ from those at initialization,
1131          * we will restore configurations to hardware in hns3_restore_vlan_table
1132          * and hns3_restore_vlan_conf later.
1133          */
1134         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1135                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1136                 if (ret) {
1137                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1138                         return ret;
1139                 }
1140
1141                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1142                 if (ret) {
1143                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1144                                  ret);
1145                         return ret;
1146                 }
1147         }
1148
1149         return hns3_default_vlan_config(hns);
1150 }
1151
1152 static int
1153 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1154 {
1155         struct hns3_pf *pf = &hns->pf;
1156         struct hns3_hw *hw = &hns->hw;
1157         uint64_t offloads;
1158         bool enable;
1159         int ret;
1160
1161         if (!hw->data->promiscuous) {
1162                 /* restore vlan filter states */
1163                 offloads = hw->data->dev_conf.rxmode.offloads;
1164                 enable = offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ? true : false;
1165                 ret = hns3_enable_vlan_filter(hns, enable);
1166                 if (ret) {
1167                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1168                                  "ret = %d", ret);
1169                         return ret;
1170                 }
1171         }
1172
1173         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1174         if (ret) {
1175                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1176                 return ret;
1177         }
1178
1179         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1180         if (ret)
1181                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1182
1183         return ret;
1184 }
1185
1186 static int
1187 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1188 {
1189         struct hns3_adapter *hns = dev->data->dev_private;
1190         struct rte_eth_dev_data *data = dev->data;
1191         struct rte_eth_txmode *txmode;
1192         struct hns3_hw *hw = &hns->hw;
1193         int mask;
1194         int ret;
1195
1196         txmode = &data->dev_conf.txmode;
1197         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1198                 hns3_warn(hw,
1199                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1200                           "configuration is not supported! Ignore these two "
1201                           "parameters: hw_vlan_reject_tagged(%u), "
1202                           "hw_vlan_reject_untagged(%u)",
1203                           txmode->hw_vlan_reject_tagged,
1204                           txmode->hw_vlan_reject_untagged);
1205
1206         /* Apply vlan offload setting */
1207         mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK;
1208         ret = hns3_vlan_offload_set(dev, mask);
1209         if (ret) {
1210                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1211                          ret);
1212                 return ret;
1213         }
1214
1215         /*
1216          * If pvid config is not set in rte_eth_conf, driver needn't to set
1217          * VLAN pvid related configuration to hardware.
1218          */
1219         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1220                 return 0;
1221
1222         /* Apply pvid setting */
1223         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1224                                  txmode->hw_vlan_insert_pvid);
1225         if (ret)
1226                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1227                          txmode->pvid, ret);
1228
1229         return ret;
1230 }
1231
1232 static int
1233 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1234                 unsigned int tso_mss_max)
1235 {
1236         struct hns3_cfg_tso_status_cmd *req;
1237         struct hns3_cmd_desc desc;
1238         uint16_t tso_mss;
1239
1240         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1241
1242         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1243
1244         tso_mss = 0;
1245         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1246                        tso_mss_min);
1247         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1248
1249         tso_mss = 0;
1250         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1251                        tso_mss_max);
1252         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1253
1254         return hns3_cmd_send(hw, &desc, 1);
1255 }
1256
1257 static int
1258 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1259                    uint16_t *allocated_size, bool is_alloc)
1260 {
1261         struct hns3_umv_spc_alc_cmd *req;
1262         struct hns3_cmd_desc desc;
1263         int ret;
1264
1265         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1266         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1267         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1268         req->space_size = rte_cpu_to_le_32(space_size);
1269
1270         ret = hns3_cmd_send(hw, &desc, 1);
1271         if (ret) {
1272                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1273                              is_alloc ? "allocate" : "free", ret);
1274                 return ret;
1275         }
1276
1277         if (is_alloc && allocated_size)
1278                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1279
1280         return 0;
1281 }
1282
1283 static int
1284 hns3_init_umv_space(struct hns3_hw *hw)
1285 {
1286         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1287         struct hns3_pf *pf = &hns->pf;
1288         uint16_t allocated_size = 0;
1289         int ret;
1290
1291         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1292                                  true);
1293         if (ret)
1294                 return ret;
1295
1296         if (allocated_size < pf->wanted_umv_size)
1297                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1298                              pf->wanted_umv_size, allocated_size);
1299
1300         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1301                                                 pf->wanted_umv_size;
1302         pf->used_umv_size = 0;
1303         return 0;
1304 }
1305
1306 static int
1307 hns3_uninit_umv_space(struct hns3_hw *hw)
1308 {
1309         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1310         struct hns3_pf *pf = &hns->pf;
1311         int ret;
1312
1313         if (pf->max_umv_size == 0)
1314                 return 0;
1315
1316         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1317         if (ret)
1318                 return ret;
1319
1320         pf->max_umv_size = 0;
1321
1322         return 0;
1323 }
1324
1325 static bool
1326 hns3_is_umv_space_full(struct hns3_hw *hw)
1327 {
1328         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1329         struct hns3_pf *pf = &hns->pf;
1330         bool is_full;
1331
1332         is_full = (pf->used_umv_size >= pf->max_umv_size);
1333
1334         return is_full;
1335 }
1336
1337 static void
1338 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1339 {
1340         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1341         struct hns3_pf *pf = &hns->pf;
1342
1343         if (is_free) {
1344                 if (pf->used_umv_size > 0)
1345                         pf->used_umv_size--;
1346         } else
1347                 pf->used_umv_size++;
1348 }
1349
1350 static void
1351 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1352                       const uint8_t *addr, bool is_mc)
1353 {
1354         const unsigned char *mac_addr = addr;
1355         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1356                             ((uint32_t)mac_addr[2] << 16) |
1357                             ((uint32_t)mac_addr[1] << 8) |
1358                             (uint32_t)mac_addr[0];
1359         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1360
1361         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1362         if (is_mc) {
1363                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1364                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1365                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1366         }
1367
1368         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1369         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1370 }
1371
1372 static int
1373 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1374                              uint8_t resp_code,
1375                              enum hns3_mac_vlan_tbl_opcode op)
1376 {
1377         if (cmdq_resp) {
1378                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1379                          cmdq_resp);
1380                 return -EIO;
1381         }
1382
1383         if (op == HNS3_MAC_VLAN_ADD) {
1384                 if (resp_code == 0 || resp_code == 1) {
1385                         return 0;
1386                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1387                         hns3_err(hw, "add mac addr failed for uc_overflow");
1388                         return -ENOSPC;
1389                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1390                         hns3_err(hw, "add mac addr failed for mc_overflow");
1391                         return -ENOSPC;
1392                 }
1393
1394                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1395                          resp_code);
1396                 return -EIO;
1397         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1398                 if (resp_code == 0) {
1399                         return 0;
1400                 } else if (resp_code == 1) {
1401                         hns3_dbg(hw, "remove mac addr failed for miss");
1402                         return -ENOENT;
1403                 }
1404
1405                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1406                          resp_code);
1407                 return -EIO;
1408         } else if (op == HNS3_MAC_VLAN_LKUP) {
1409                 if (resp_code == 0) {
1410                         return 0;
1411                 } else if (resp_code == 1) {
1412                         hns3_dbg(hw, "lookup mac addr failed for miss");
1413                         return -ENOENT;
1414                 }
1415
1416                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1417                          resp_code);
1418                 return -EIO;
1419         }
1420
1421         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1422                  op);
1423
1424         return -EINVAL;
1425 }
1426
1427 static int
1428 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1429                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1430                          struct hns3_cmd_desc *desc, uint8_t desc_num)
1431 {
1432         uint8_t resp_code;
1433         uint16_t retval;
1434         int ret;
1435         int i;
1436
1437         if (desc_num == HNS3_MC_MAC_VLAN_OPS_DESC_NUM) {
1438                 for (i = 0; i < desc_num - 1; i++) {
1439                         hns3_cmd_setup_basic_desc(&desc[i],
1440                                                   HNS3_OPC_MAC_VLAN_ADD, true);
1441                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1442                         if (i == 0)
1443                                 memcpy(desc[i].data, req,
1444                                 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1445                 }
1446                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_MAC_VLAN_ADD,
1447                                           true);
1448         } else {
1449                 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD,
1450                                           true);
1451                 memcpy(desc[0].data, req,
1452                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1453         }
1454         ret = hns3_cmd_send(hw, desc, desc_num);
1455         if (ret) {
1456                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1457                          ret);
1458                 return ret;
1459         }
1460         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1461         retval = rte_le_to_cpu_16(desc[0].retval);
1462
1463         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1464                                             HNS3_MAC_VLAN_LKUP);
1465 }
1466
1467 static int
1468 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1469                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1470                       struct hns3_cmd_desc *desc, uint8_t desc_num)
1471 {
1472         uint8_t resp_code;
1473         uint16_t retval;
1474         int cfg_status;
1475         int ret;
1476         int i;
1477
1478         if (desc_num == HNS3_UC_MAC_VLAN_OPS_DESC_NUM) {
1479                 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_MAC_VLAN_ADD, false);
1480                 memcpy(desc->data, req,
1481                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1482                 ret = hns3_cmd_send(hw, desc, desc_num);
1483                 resp_code = (rte_le_to_cpu_32(desc->data[0]) >> 8) & 0xff;
1484                 retval = rte_le_to_cpu_16(desc->retval);
1485
1486                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1487                                                           HNS3_MAC_VLAN_ADD);
1488         } else {
1489                 for (i = 0; i < desc_num; i++) {
1490                         hns3_cmd_reuse_desc(&desc[i], false);
1491                         if (i == desc_num - 1)
1492                                 desc[i].flag &=
1493                                         rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1494                         else
1495                                 desc[i].flag |=
1496                                         rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1497                 }
1498                 memcpy(desc[0].data, req,
1499                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1500                 desc[0].retval = 0;
1501                 ret = hns3_cmd_send(hw, desc, desc_num);
1502                 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1503                 retval = rte_le_to_cpu_16(desc[0].retval);
1504
1505                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1506                                                           HNS3_MAC_VLAN_ADD);
1507         }
1508
1509         if (ret) {
1510                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1511                 return ret;
1512         }
1513
1514         return cfg_status;
1515 }
1516
1517 static int
1518 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1519                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1520 {
1521         struct hns3_cmd_desc desc;
1522         uint8_t resp_code;
1523         uint16_t retval;
1524         int ret;
1525
1526         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1527
1528         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1529
1530         ret = hns3_cmd_send(hw, &desc, 1);
1531         if (ret) {
1532                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1533                 return ret;
1534         }
1535         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1536         retval = rte_le_to_cpu_16(desc.retval);
1537
1538         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1539                                             HNS3_MAC_VLAN_REMOVE);
1540 }
1541
1542 static int
1543 hns3_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1544 {
1545         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1546         struct hns3_mac_vlan_tbl_entry_cmd req;
1547         struct hns3_pf *pf = &hns->pf;
1548         struct hns3_cmd_desc desc;
1549         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1550         uint16_t egress_port = 0;
1551         uint8_t vf_id;
1552         int ret;
1553
1554         /* check if mac addr is valid */
1555         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1556                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1557                                       mac_addr);
1558                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1559                          mac_str);
1560                 return -EINVAL;
1561         }
1562
1563         memset(&req, 0, sizeof(req));
1564
1565         /*
1566          * In current version VF is not supported when PF is driven by DPDK
1567          * driver, just need to configure parameters for PF vport.
1568          */
1569         vf_id = HNS3_PF_FUNC_ID;
1570         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1571                        HNS3_MAC_EPORT_VFID_S, vf_id);
1572
1573         req.egress_port = rte_cpu_to_le_16(egress_port);
1574
1575         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1576
1577         /*
1578          * Lookup the mac address in the mac_vlan table, and add
1579          * it if the entry is inexistent. Repeated unicast entry
1580          * is not allowed in the mac vlan table.
1581          */
1582         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc,
1583                                         HNS3_UC_MAC_VLAN_OPS_DESC_NUM);
1584         if (ret == -ENOENT) {
1585                 if (!hns3_is_umv_space_full(hw)) {
1586                         ret = hns3_add_mac_vlan_tbl(hw, &req, &desc,
1587                                                 HNS3_UC_MAC_VLAN_OPS_DESC_NUM);
1588                         if (!ret)
1589                                 hns3_update_umv_space(hw, false);
1590                         return ret;
1591                 }
1592
1593                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1594
1595                 return -ENOSPC;
1596         }
1597
1598         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1599
1600         /* check if we just hit the duplicate */
1601         if (ret == 0) {
1602                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1603                 return 0;
1604         }
1605
1606         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1607                  mac_str);
1608
1609         return ret;
1610 }
1611
1612 static bool
1613 hns3_find_duplicate_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mc_addr)
1614 {
1615         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1616         struct rte_ether_addr *addr;
1617         int i;
1618
1619         for (i = 0; i < hw->mc_addrs_num; i++) {
1620                 addr = &hw->mc_addrs[i];
1621                 /* Check if there are duplicate addresses in mc_addrs[] */
1622                 if (rte_is_same_ether_addr(addr, mc_addr)) {
1623                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1624                                                addr);
1625                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1626                                  "(%s) is added by the set_mc_mac_addr_list "
1627                                  "API", mac_str);
1628                         return true;
1629                 }
1630         }
1631
1632         return false;
1633 }
1634
1635 int
1636 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1637                   __rte_unused uint32_t idx, __rte_unused uint32_t pool)
1638 {
1639         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1641         int ret;
1642
1643         rte_spinlock_lock(&hw->lock);
1644
1645         /*
1646          * In hns3 network engine adding UC and MC mac address with different
1647          * commands with firmware. We need to determine whether the input
1648          * address is a UC or a MC address to call different commands.
1649          * By the way, it is recommended calling the API function named
1650          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1651          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1652          * may affect the specifications of UC mac addresses.
1653          */
1654         if (rte_is_multicast_ether_addr(mac_addr)) {
1655                 if (hns3_find_duplicate_mc_addr(hw, mac_addr)) {
1656                         rte_spinlock_unlock(&hw->lock);
1657                         return -EINVAL;
1658                 }
1659                 ret = hw->ops.add_mc_mac_addr(hw, mac_addr);
1660         } else {
1661                 ret = hw->ops.add_uc_mac_addr(hw, mac_addr);
1662         }
1663         rte_spinlock_unlock(&hw->lock);
1664         if (ret) {
1665                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1666                                       mac_addr);
1667                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1668                          ret);
1669         }
1670
1671         return ret;
1672 }
1673
1674 static int
1675 hns3_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1676 {
1677         struct hns3_mac_vlan_tbl_entry_cmd req;
1678         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1679         int ret;
1680
1681         /* check if mac addr is valid */
1682         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1683                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1684                                       mac_addr);
1685                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1686                          mac_str);
1687                 return -EINVAL;
1688         }
1689
1690         memset(&req, 0, sizeof(req));
1691         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1692         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1693         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1694         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1695                 return 0;
1696         else if (ret == 0)
1697                 hns3_update_umv_space(hw, true);
1698
1699         return ret;
1700 }
1701
1702 void
1703 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1704 {
1705         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1706         /* index will be checked by upper level rte interface */
1707         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1708         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1709         int ret;
1710
1711         rte_spinlock_lock(&hw->lock);
1712
1713         if (rte_is_multicast_ether_addr(mac_addr))
1714                 ret = hw->ops.del_mc_mac_addr(hw, mac_addr);
1715         else
1716                 ret = hw->ops.del_uc_mac_addr(hw, mac_addr);
1717         rte_spinlock_unlock(&hw->lock);
1718         if (ret) {
1719                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1720                                       mac_addr);
1721                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1722                          ret);
1723         }
1724 }
1725
1726 static int
1727 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1728                           struct rte_ether_addr *mac_addr)
1729 {
1730         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1731         struct rte_ether_addr *oaddr;
1732         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1733         int ret, ret_val;
1734
1735         rte_spinlock_lock(&hw->lock);
1736         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1737         ret = hw->ops.del_uc_mac_addr(hw, oaddr);
1738         if (ret) {
1739                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1740                                       oaddr);
1741                 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1742                           mac_str, ret);
1743
1744                 rte_spinlock_unlock(&hw->lock);
1745                 return ret;
1746         }
1747
1748         ret = hw->ops.add_uc_mac_addr(hw, mac_addr);
1749         if (ret) {
1750                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1751                                       mac_addr);
1752                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1753                 goto err_add_uc_addr;
1754         }
1755
1756         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1757         if (ret) {
1758                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1759                 goto err_pause_addr_cfg;
1760         }
1761
1762         rte_ether_addr_copy(mac_addr,
1763                             (struct rte_ether_addr *)hw->mac.mac_addr);
1764         rte_spinlock_unlock(&hw->lock);
1765
1766         return 0;
1767
1768 err_pause_addr_cfg:
1769         ret_val = hw->ops.del_uc_mac_addr(hw, mac_addr);
1770         if (ret_val) {
1771                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1772                                       mac_addr);
1773                 hns3_warn(hw,
1774                           "Failed to roll back to del setted mac addr(%s): %d",
1775                           mac_str, ret_val);
1776         }
1777
1778 err_add_uc_addr:
1779         ret_val = hw->ops.add_uc_mac_addr(hw, oaddr);
1780         if (ret_val) {
1781                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, oaddr);
1782                 hns3_warn(hw, "Failed to restore old uc mac addr(%s): %d",
1783                                   mac_str, ret_val);
1784         }
1785         rte_spinlock_unlock(&hw->lock);
1786
1787         return ret;
1788 }
1789
1790 int
1791 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1792 {
1793         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1794         struct hns3_hw *hw = &hns->hw;
1795         struct hns3_hw_ops *ops = &hw->ops;
1796         struct rte_ether_addr *addr;
1797         uint16_t mac_addrs_capa;
1798         int ret = 0;
1799         int i;
1800
1801         mac_addrs_capa =
1802                 hns->is_vf ? HNS3_VF_UC_MACADDR_NUM : HNS3_UC_MACADDR_NUM;
1803         for (i = 0; i < mac_addrs_capa; i++) {
1804                 addr = &hw->data->mac_addrs[i];
1805                 if (rte_is_zero_ether_addr(addr))
1806                         continue;
1807                 if (rte_is_multicast_ether_addr(addr))
1808                         ret = del ? ops->del_mc_mac_addr(hw, addr) :
1809                               ops->add_mc_mac_addr(hw, addr);
1810                 else
1811                         ret = del ? ops->del_uc_mac_addr(hw, addr) :
1812                               ops->add_uc_mac_addr(hw, addr);
1813
1814                 if (ret) {
1815                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1816                                                addr);
1817                         hns3_err(hw, "failed to %s mac addr(%s) index:%d ret = %d.",
1818                                  del ? "remove" : "restore", mac_str, i, ret);
1819                 }
1820         }
1821
1822         return ret;
1823 }
1824
1825 static void
1826 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1827 {
1828 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1829         uint8_t word_num;
1830         uint8_t bit_num;
1831
1832         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1833                 word_num = vfid / 32;
1834                 bit_num = vfid % 32;
1835                 if (clr)
1836                         desc[1].data[word_num] &=
1837                             rte_cpu_to_le_32(~(1UL << bit_num));
1838                 else
1839                         desc[1].data[word_num] |=
1840                             rte_cpu_to_le_32(1UL << bit_num);
1841         } else {
1842                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1843                 bit_num = vfid % 32;
1844                 if (clr)
1845                         desc[2].data[word_num] &=
1846                             rte_cpu_to_le_32(~(1UL << bit_num));
1847                 else
1848                         desc[2].data[word_num] |=
1849                             rte_cpu_to_le_32(1UL << bit_num);
1850         }
1851 }
1852
1853 static int
1854 hns3_add_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1855 {
1856         struct hns3_cmd_desc desc[HNS3_MC_MAC_VLAN_OPS_DESC_NUM];
1857         struct hns3_mac_vlan_tbl_entry_cmd req;
1858         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1859         uint8_t vf_id;
1860         int ret;
1861
1862         /* Check if mac addr is valid */
1863         if (!rte_is_multicast_ether_addr(mac_addr)) {
1864                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1865                                       mac_addr);
1866                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1867                          mac_str);
1868                 return -EINVAL;
1869         }
1870
1871         memset(&req, 0, sizeof(req));
1872         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1873         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1874         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc,
1875                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1876         if (ret) {
1877                 /* This mac addr do not exist, add new entry for it */
1878                 memset(desc[0].data, 0, sizeof(desc[0].data));
1879                 memset(desc[1].data, 0, sizeof(desc[0].data));
1880                 memset(desc[2].data, 0, sizeof(desc[0].data));
1881         }
1882
1883         /*
1884          * In current version VF is not supported when PF is driven by DPDK
1885          * driver, just need to configure parameters for PF vport.
1886          */
1887         vf_id = HNS3_PF_FUNC_ID;
1888         hns3_update_desc_vfid(desc, vf_id, false);
1889         ret = hns3_add_mac_vlan_tbl(hw, &req, desc,
1890                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1891         if (ret) {
1892                 if (ret == -ENOSPC)
1893                         hns3_err(hw, "mc mac vlan table is full");
1894                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1895                                       mac_addr);
1896                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1897         }
1898
1899         return ret;
1900 }
1901
1902 static int
1903 hns3_remove_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1904 {
1905         struct hns3_mac_vlan_tbl_entry_cmd req;
1906         struct hns3_cmd_desc desc[3];
1907         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1908         uint8_t vf_id;
1909         int ret;
1910
1911         /* Check if mac addr is valid */
1912         if (!rte_is_multicast_ether_addr(mac_addr)) {
1913                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1914                                       mac_addr);
1915                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1916                          mac_str);
1917                 return -EINVAL;
1918         }
1919
1920         memset(&req, 0, sizeof(req));
1921         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1922         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1923         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc,
1924                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1925         if (ret == 0) {
1926                 /*
1927                  * This mac addr exist, remove this handle's VFID for it.
1928                  * In current version VF is not supported when PF is driven by
1929                  * DPDK driver, just need to configure parameters for PF vport.
1930                  */
1931                 vf_id = HNS3_PF_FUNC_ID;
1932                 hns3_update_desc_vfid(desc, vf_id, true);
1933
1934                 /* All the vfid is zero, so need to delete this entry */
1935                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1936         } else if (ret == -ENOENT) {
1937                 /* This mac addr doesn't exist. */
1938                 return 0;
1939         }
1940
1941         if (ret) {
1942                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1943                                       mac_addr);
1944                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1945         }
1946
1947         return ret;
1948 }
1949
1950 static int
1951 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1952                            struct rte_ether_addr *mc_addr_set,
1953                            uint32_t nb_mc_addr)
1954 {
1955         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1956         struct rte_ether_addr *addr;
1957         uint32_t i;
1958         uint32_t j;
1959
1960         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1961                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1962                          "invalid. valid range: 0~%d",
1963                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1964                 return -EINVAL;
1965         }
1966
1967         /* Check if input mac addresses are valid */
1968         for (i = 0; i < nb_mc_addr; i++) {
1969                 addr = &mc_addr_set[i];
1970                 if (!rte_is_multicast_ether_addr(addr)) {
1971                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1972                                               addr);
1973                         hns3_err(hw,
1974                                  "failed to set mc mac addr, addr(%s) invalid.",
1975                                  mac_str);
1976                         return -EINVAL;
1977                 }
1978
1979                 /* Check if there are duplicate addresses */
1980                 for (j = i + 1; j < nb_mc_addr; j++) {
1981                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1982                                 hns3_ether_format_addr(mac_str,
1983                                                       RTE_ETHER_ADDR_FMT_SIZE,
1984                                                       addr);
1985                                 hns3_err(hw, "failed to set mc mac addr, "
1986                                          "addrs invalid. two same addrs(%s).",
1987                                          mac_str);
1988                                 return -EINVAL;
1989                         }
1990                 }
1991
1992                 /*
1993                  * Check if there are duplicate addresses between mac_addrs
1994                  * and mc_addr_set
1995                  */
1996                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1997                         if (rte_is_same_ether_addr(addr,
1998                                                    &hw->data->mac_addrs[j])) {
1999                                 hns3_ether_format_addr(mac_str,
2000                                                       RTE_ETHER_ADDR_FMT_SIZE,
2001                                                       addr);
2002                                 hns3_err(hw, "failed to set mc mac addr, "
2003                                          "addrs invalid. addrs(%s) has already "
2004                                          "configured in mac_addr add API",
2005                                          mac_str);
2006                                 return -EINVAL;
2007                         }
2008                 }
2009         }
2010
2011         return 0;
2012 }
2013
2014 static void
2015 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2016                            struct rte_ether_addr *mc_addr_set,
2017                            int mc_addr_num,
2018                            struct rte_ether_addr *reserved_addr_list,
2019                            int *reserved_addr_num,
2020                            struct rte_ether_addr *add_addr_list,
2021                            int *add_addr_num,
2022                            struct rte_ether_addr *rm_addr_list,
2023                            int *rm_addr_num)
2024 {
2025         struct rte_ether_addr *addr;
2026         int current_addr_num;
2027         int reserved_num = 0;
2028         int add_num = 0;
2029         int rm_num = 0;
2030         int num;
2031         int i;
2032         int j;
2033         bool same_addr;
2034
2035         /* Calculate the mc mac address list that should be removed */
2036         current_addr_num = hw->mc_addrs_num;
2037         for (i = 0; i < current_addr_num; i++) {
2038                 addr = &hw->mc_addrs[i];
2039                 same_addr = false;
2040                 for (j = 0; j < mc_addr_num; j++) {
2041                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2042                                 same_addr = true;
2043                                 break;
2044                         }
2045                 }
2046
2047                 if (!same_addr) {
2048                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2049                         rm_num++;
2050                 } else {
2051                         rte_ether_addr_copy(addr,
2052                                             &reserved_addr_list[reserved_num]);
2053                         reserved_num++;
2054                 }
2055         }
2056
2057         /* Calculate the mc mac address list that should be added */
2058         for (i = 0; i < mc_addr_num; i++) {
2059                 addr = &mc_addr_set[i];
2060                 same_addr = false;
2061                 for (j = 0; j < current_addr_num; j++) {
2062                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2063                                 same_addr = true;
2064                                 break;
2065                         }
2066                 }
2067
2068                 if (!same_addr) {
2069                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2070                         add_num++;
2071                 }
2072         }
2073
2074         /* Reorder the mc mac address list maintained by driver */
2075         for (i = 0; i < reserved_num; i++)
2076                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2077
2078         for (i = 0; i < rm_num; i++) {
2079                 num = reserved_num + i;
2080                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2081         }
2082
2083         *reserved_addr_num = reserved_num;
2084         *add_addr_num = add_num;
2085         *rm_addr_num = rm_num;
2086 }
2087
2088 static int
2089 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2090                           struct rte_ether_addr *mc_addr_set,
2091                           uint32_t nb_mc_addr)
2092 {
2093         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2094         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2095         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2096         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2097         struct rte_ether_addr *addr;
2098         int reserved_addr_num;
2099         int add_addr_num;
2100         int rm_addr_num;
2101         int mc_addr_num;
2102         int num;
2103         int ret;
2104         int i;
2105
2106         /* Check if input parameters are valid */
2107         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2108         if (ret)
2109                 return ret;
2110
2111         rte_spinlock_lock(&hw->lock);
2112
2113         /*
2114          * Calculate the mc mac address lists those should be removed and be
2115          * added, Reorder the mc mac address list maintained by driver.
2116          */
2117         mc_addr_num = (int)nb_mc_addr;
2118         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2119                                    reserved_addr_list, &reserved_addr_num,
2120                                    add_addr_list, &add_addr_num,
2121                                    rm_addr_list, &rm_addr_num);
2122
2123         /* Remove mc mac addresses */
2124         for (i = 0; i < rm_addr_num; i++) {
2125                 num = rm_addr_num - i - 1;
2126                 addr = &rm_addr_list[num];
2127                 ret = hw->ops.del_mc_mac_addr(hw, addr);
2128                 if (ret) {
2129                         rte_spinlock_unlock(&hw->lock);
2130                         return ret;
2131                 }
2132                 hw->mc_addrs_num--;
2133         }
2134
2135         /* Add mc mac addresses */
2136         for (i = 0; i < add_addr_num; i++) {
2137                 addr = &add_addr_list[i];
2138                 ret = hw->ops.add_mc_mac_addr(hw, addr);
2139                 if (ret) {
2140                         rte_spinlock_unlock(&hw->lock);
2141                         return ret;
2142                 }
2143
2144                 num = reserved_addr_num + i;
2145                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2146                 hw->mc_addrs_num++;
2147         }
2148         rte_spinlock_unlock(&hw->lock);
2149
2150         return 0;
2151 }
2152
2153 int
2154 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2155 {
2156         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2157         struct hns3_hw *hw = &hns->hw;
2158         struct rte_ether_addr *addr;
2159         int ret = 0;
2160         int i;
2161
2162         for (i = 0; i < hw->mc_addrs_num; i++) {
2163                 addr = &hw->mc_addrs[i];
2164                 if (!rte_is_multicast_ether_addr(addr))
2165                         continue;
2166                 if (del)
2167                         ret = hw->ops.del_mc_mac_addr(hw, addr);
2168                 else
2169                         ret = hw->ops.add_mc_mac_addr(hw, addr);
2170                 if (ret) {
2171                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2172                                               addr);
2173                         hns3_dbg(hw, "failed to %s mc mac addr: %s ret = %d",
2174                                  del ? "Remove" : "Restore", mac_str, ret);
2175                 }
2176         }
2177         return ret;
2178 }
2179
2180 static int
2181 hns3_check_mq_mode(struct rte_eth_dev *dev)
2182 {
2183         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2184         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2185         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2186         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2187         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2188         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2189         uint8_t num_tc;
2190         int max_tc = 0;
2191         int i;
2192
2193         if ((rx_mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) ||
2194             (tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB ||
2195              tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_ONLY)) {
2196                 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
2197                          rx_mq_mode, tx_mq_mode);
2198                 return -EOPNOTSUPP;
2199         }
2200
2201         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2202         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2203         if (rx_mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
2204                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2205                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2206                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2207                         return -EINVAL;
2208                 }
2209
2210                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2211                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2212                         hns3_err(hw, "on RTE_ETH_MQ_RX_DCB_RSS mode, "
2213                                  "nb_tcs(%d) != %d or %d in rx direction.",
2214                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2215                         return -EINVAL;
2216                 }
2217
2218                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2219                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2220                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2221                         return -EINVAL;
2222                 }
2223
2224                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2225                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2226                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2227                                          "is not equal to one in tx direction.",
2228                                          i, dcb_rx_conf->dcb_tc[i]);
2229                                 return -EINVAL;
2230                         }
2231                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2232                                 max_tc = dcb_rx_conf->dcb_tc[i];
2233                 }
2234
2235                 num_tc = max_tc + 1;
2236                 if (num_tc > dcb_rx_conf->nb_tcs) {
2237                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2238                                  num_tc, dcb_rx_conf->nb_tcs);
2239                         return -EINVAL;
2240                 }
2241         }
2242
2243         return 0;
2244 }
2245
2246 static int
2247 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2248                            enum hns3_ring_type queue_type, uint16_t queue_id)
2249 {
2250         struct hns3_cmd_desc desc;
2251         struct hns3_ctrl_vector_chain_cmd *req =
2252                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2253         enum hns3_opcode_type op;
2254         uint16_t tqp_type_and_id = 0;
2255         uint16_t type;
2256         uint16_t gl;
2257         int ret;
2258
2259         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2260         hns3_cmd_setup_basic_desc(&desc, op, false);
2261         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2262                                               HNS3_TQP_INT_ID_L_S);
2263         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2264                                               HNS3_TQP_INT_ID_H_S);
2265
2266         if (queue_type == HNS3_RING_TYPE_RX)
2267                 gl = HNS3_RING_GL_RX;
2268         else
2269                 gl = HNS3_RING_GL_TX;
2270
2271         type = queue_type;
2272
2273         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2274                        type);
2275         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2276         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2277                        gl);
2278         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2279         req->int_cause_num = 1;
2280         ret = hns3_cmd_send(hw, &desc, 1);
2281         if (ret) {
2282                 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2283                          en ? "Map" : "Unmap", queue_id, vector_id, ret);
2284                 return ret;
2285         }
2286
2287         return 0;
2288 }
2289
2290 static int
2291 hns3_init_ring_with_vector(struct hns3_hw *hw)
2292 {
2293         uint16_t vec;
2294         int ret;
2295         int i;
2296
2297         /*
2298          * In hns3 network engine, vector 0 is always the misc interrupt of this
2299          * function, vector 1~N can be used respectively for the queues of the
2300          * function. Tx and Rx queues with the same number share the interrupt
2301          * vector. In the initialization clearing the all hardware mapping
2302          * relationship configurations between queues and interrupt vectors is
2303          * needed, so some error caused by the residual configurations, such as
2304          * the unexpected Tx interrupt, can be avoid.
2305          */
2306         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2307         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2308                 vec = vec - 1; /* the last interrupt is reserved */
2309         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2310         for (i = 0; i < hw->intr_tqps_num; i++) {
2311                 /*
2312                  * Set gap limiter/rate limiter/quanity limiter algorithm
2313                  * configuration for interrupt coalesce of queue's interrupt.
2314                  */
2315                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2316                                        HNS3_TQP_INTR_GL_DEFAULT);
2317                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2318                                        HNS3_TQP_INTR_GL_DEFAULT);
2319                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2320                 /*
2321                  * QL(quantity limiter) is not used currently, just set 0 to
2322                  * close it.
2323                  */
2324                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2325
2326                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2327                                                  HNS3_RING_TYPE_TX, i);
2328                 if (ret) {
2329                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2330                                           "vector: %u, ret=%d", i, vec, ret);
2331                         return ret;
2332                 }
2333
2334                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2335                                                  HNS3_RING_TYPE_RX, i);
2336                 if (ret) {
2337                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2338                                           "vector: %u, ret=%d", i, vec, ret);
2339                         return ret;
2340                 }
2341         }
2342
2343         return 0;
2344 }
2345
2346 static int
2347 hns3_setup_dcb(struct rte_eth_dev *dev)
2348 {
2349         struct hns3_adapter *hns = dev->data->dev_private;
2350         struct hns3_hw *hw = &hns->hw;
2351         int ret;
2352
2353         if (!hns3_dev_get_support(hw, DCB)) {
2354                 hns3_err(hw, "this port does not support dcb configurations.");
2355                 return -EOPNOTSUPP;
2356         }
2357
2358         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2359                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2360                 return -EOPNOTSUPP;
2361         }
2362
2363         ret = hns3_dcb_configure(hns);
2364         if (ret)
2365                 hns3_err(hw, "failed to config dcb: %d", ret);
2366
2367         return ret;
2368 }
2369
2370 static int
2371 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
2372 {
2373         int ret;
2374
2375         /*
2376          * Some hardware doesn't support auto-negotiation, but users may not
2377          * configure link_speeds (default 0), which means auto-negotiation.
2378          * In this case, it should return success.
2379          */
2380         if (link_speeds == RTE_ETH_LINK_SPEED_AUTONEG &&
2381             hw->mac.support_autoneg == 0)
2382                 return 0;
2383
2384         if (link_speeds != RTE_ETH_LINK_SPEED_AUTONEG) {
2385                 ret = hns3_check_port_speed(hw, link_speeds);
2386                 if (ret)
2387                         return ret;
2388         }
2389
2390         return 0;
2391 }
2392
2393 static int
2394 hns3_check_dev_conf(struct rte_eth_dev *dev)
2395 {
2396         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2397         struct rte_eth_conf *conf = &dev->data->dev_conf;
2398         int ret;
2399
2400         ret = hns3_check_mq_mode(dev);
2401         if (ret)
2402                 return ret;
2403
2404         return hns3_check_link_speed(hw, conf->link_speeds);
2405 }
2406
2407 static int
2408 hns3_dev_configure(struct rte_eth_dev *dev)
2409 {
2410         struct hns3_adapter *hns = dev->data->dev_private;
2411         struct rte_eth_conf *conf = &dev->data->dev_conf;
2412         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2413         struct hns3_hw *hw = &hns->hw;
2414         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2415         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2416         struct rte_eth_rss_conf rss_conf;
2417         bool gro_en;
2418         int ret;
2419
2420         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2421
2422         /*
2423          * Some versions of hardware network engine does not support
2424          * individually enable/disable/reset the Tx or Rx queue. These devices
2425          * must enable/disable/reset Tx and Rx queues at the same time. When the
2426          * numbers of Tx queues allocated by upper applications are not equal to
2427          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2428          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2429          * work as usual. But these fake queues are imperceptible, and can not
2430          * be used by upper applications.
2431          */
2432         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2433         if (ret) {
2434                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
2435                 hw->cfg_max_queues = 0;
2436                 return ret;
2437         }
2438
2439         hw->adapter_state = HNS3_NIC_CONFIGURING;
2440         ret = hns3_check_dev_conf(dev);
2441         if (ret)
2442                 goto cfg_err;
2443
2444         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
2445                 ret = hns3_setup_dcb(dev);
2446                 if (ret)
2447                         goto cfg_err;
2448         }
2449
2450         /* When RSS is not configured, redirect the packet queue 0 */
2451         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
2452                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2453                 rss_conf = conf->rx_adv_conf.rss_conf;
2454                 hw->rss_dis_flag = false;
2455                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2456                 if (ret)
2457                         goto cfg_err;
2458         }
2459
2460         ret = hns3_dev_mtu_set(dev, conf->rxmode.mtu);
2461         if (ret != 0)
2462                 goto cfg_err;
2463
2464         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2465         if (ret)
2466                 goto cfg_err;
2467
2468         ret = hns3_dev_configure_vlan(dev);
2469         if (ret)
2470                 goto cfg_err;
2471
2472         /* config hardware GRO */
2473         gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
2474         ret = hns3_config_gro(hw, gro_en);
2475         if (ret)
2476                 goto cfg_err;
2477
2478         hns3_init_rx_ptype_tble(dev);
2479         hw->adapter_state = HNS3_NIC_CONFIGURED;
2480
2481         return 0;
2482
2483 cfg_err:
2484         hw->cfg_max_queues = 0;
2485         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2486         hw->adapter_state = HNS3_NIC_INITIALIZED;
2487
2488         return ret;
2489 }
2490
2491 static int
2492 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2493 {
2494         struct hns3_config_max_frm_size_cmd *req;
2495         struct hns3_cmd_desc desc;
2496
2497         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2498
2499         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2500         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2501         req->min_frm_size = RTE_ETHER_MIN_LEN;
2502
2503         return hns3_cmd_send(hw, &desc, 1);
2504 }
2505
2506 static int
2507 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2508 {
2509         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2510         uint16_t original_mps = hns->pf.mps;
2511         int err;
2512         int ret;
2513
2514         ret = hns3_set_mac_mtu(hw, mps);
2515         if (ret) {
2516                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2517                 return ret;
2518         }
2519
2520         hns->pf.mps = mps;
2521         ret = hns3_buffer_alloc(hw);
2522         if (ret) {
2523                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2524                 goto rollback;
2525         }
2526
2527         return 0;
2528
2529 rollback:
2530         err = hns3_set_mac_mtu(hw, original_mps);
2531         if (err) {
2532                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2533                 return ret;
2534         }
2535         hns->pf.mps = original_mps;
2536
2537         return ret;
2538 }
2539
2540 static int
2541 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2542 {
2543         struct hns3_adapter *hns = dev->data->dev_private;
2544         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2545         struct hns3_hw *hw = &hns->hw;
2546         int ret;
2547
2548         if (dev->data->dev_started) {
2549                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2550                          "before configuration", dev->data->port_id);
2551                 return -EBUSY;
2552         }
2553
2554         rte_spinlock_lock(&hw->lock);
2555         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2556
2557         /*
2558          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2559          * assign to "uint16_t" type variable.
2560          */
2561         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2562         if (ret) {
2563                 rte_spinlock_unlock(&hw->lock);
2564                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2565                          dev->data->port_id, mtu, ret);
2566                 return ret;
2567         }
2568
2569         rte_spinlock_unlock(&hw->lock);
2570
2571         return 0;
2572 }
2573
2574 static uint32_t
2575 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2576 {
2577         uint32_t speed_capa = 0;
2578
2579         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2580                 speed_capa |= RTE_ETH_LINK_SPEED_10M_HD;
2581         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2582                 speed_capa |= RTE_ETH_LINK_SPEED_10M;
2583         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2584                 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD;
2585         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2586                 speed_capa |= RTE_ETH_LINK_SPEED_100M;
2587         if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2588                 speed_capa |= RTE_ETH_LINK_SPEED_1G;
2589
2590         return speed_capa;
2591 }
2592
2593 static uint32_t
2594 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2595 {
2596         uint32_t speed_capa = 0;
2597
2598         if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2599                 speed_capa |= RTE_ETH_LINK_SPEED_1G;
2600         if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2601                 speed_capa |= RTE_ETH_LINK_SPEED_10G;
2602         if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2603                 speed_capa |= RTE_ETH_LINK_SPEED_25G;
2604         if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2605                 speed_capa |= RTE_ETH_LINK_SPEED_40G;
2606         if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2607                 speed_capa |= RTE_ETH_LINK_SPEED_50G;
2608         if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2609                 speed_capa |= RTE_ETH_LINK_SPEED_100G;
2610         if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2611                 speed_capa |= RTE_ETH_LINK_SPEED_200G;
2612
2613         return speed_capa;
2614 }
2615
2616 static uint32_t
2617 hns3_get_speed_capa(struct hns3_hw *hw)
2618 {
2619         struct hns3_mac *mac = &hw->mac;
2620         uint32_t speed_capa;
2621
2622         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2623                 speed_capa =
2624                         hns3_get_copper_port_speed_capa(mac->supported_speed);
2625         else
2626                 speed_capa =
2627                         hns3_get_firber_port_speed_capa(mac->supported_speed);
2628
2629         if (mac->support_autoneg == 0)
2630                 speed_capa |= RTE_ETH_LINK_SPEED_FIXED;
2631
2632         return speed_capa;
2633 }
2634
2635 int
2636 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2637 {
2638         struct hns3_adapter *hns = eth_dev->data->dev_private;
2639         struct hns3_hw *hw = &hns->hw;
2640         uint16_t queue_num = hw->tqps_num;
2641
2642         /*
2643          * In interrupt mode, 'max_rx_queues' is set based on the number of
2644          * MSI-X interrupt resources of the hardware.
2645          */
2646         if (hw->data->dev_conf.intr_conf.rxq == 1)
2647                 queue_num = hw->intr_tqps_num;
2648
2649         info->max_rx_queues = queue_num;
2650         info->max_tx_queues = hw->tqps_num;
2651         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2652         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2653         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2654         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2655         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2656         info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
2657                                  RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
2658                                  RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
2659                                  RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
2660                                  RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2661                                  RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
2662                                  RTE_ETH_RX_OFFLOAD_KEEP_CRC |
2663                                  RTE_ETH_RX_OFFLOAD_SCATTER |
2664                                  RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
2665                                  RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
2666                                  RTE_ETH_RX_OFFLOAD_RSS_HASH |
2667                                  RTE_ETH_RX_OFFLOAD_TCP_LRO);
2668         info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2669                                  RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
2670                                  RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
2671                                  RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
2672                                  RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
2673                                  RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
2674                                  RTE_ETH_TX_OFFLOAD_TCP_TSO |
2675                                  RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
2676                                  RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
2677                                  RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
2678                                  RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
2679                                  hns3_txvlan_cap_get(hw));
2680
2681         if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
2682                 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
2683
2684         if (hns3_dev_get_support(hw, INDEP_TXRX))
2685                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2686                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2687
2688         if (hns3_dev_get_support(hw, PTP))
2689                 info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP;
2690
2691         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2692                 .nb_max = HNS3_MAX_RING_DESC,
2693                 .nb_min = HNS3_MIN_RING_DESC,
2694                 .nb_align = HNS3_ALIGN_RING_DESC,
2695         };
2696
2697         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2698                 .nb_max = HNS3_MAX_RING_DESC,
2699                 .nb_min = HNS3_MIN_RING_DESC,
2700                 .nb_align = HNS3_ALIGN_RING_DESC,
2701                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2702                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2703         };
2704
2705         info->speed_capa = hns3_get_speed_capa(hw);
2706         info->default_rxconf = (struct rte_eth_rxconf) {
2707                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2708                 /*
2709                  * If there are no available Rx buffer descriptors, incoming
2710                  * packets are always dropped by hardware based on hns3 network
2711                  * engine.
2712                  */
2713                 .rx_drop_en = 1,
2714                 .offloads = 0,
2715         };
2716         info->default_txconf = (struct rte_eth_txconf) {
2717                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2718                 .offloads = 0,
2719         };
2720
2721         info->reta_size = hw->rss_ind_tbl_size;
2722         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2723         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2724
2725         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2726         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2727         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2728         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2729         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2730         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2731
2732         return 0;
2733 }
2734
2735 static int
2736 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2737                     size_t fw_size)
2738 {
2739         struct hns3_adapter *hns = eth_dev->data->dev_private;
2740         struct hns3_hw *hw = &hns->hw;
2741         uint32_t version = hw->fw_version;
2742         int ret;
2743
2744         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2745                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2746                                       HNS3_FW_VERSION_BYTE3_S),
2747                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2748                                       HNS3_FW_VERSION_BYTE2_S),
2749                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2750                                       HNS3_FW_VERSION_BYTE1_S),
2751                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2752                                       HNS3_FW_VERSION_BYTE0_S));
2753         if (ret < 0)
2754                 return -EINVAL;
2755
2756         ret += 1; /* add the size of '\0' */
2757         if (fw_size < (size_t)ret)
2758                 return ret;
2759         else
2760                 return 0;
2761 }
2762
2763 static int
2764 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2765 {
2766         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2767         int ret;
2768
2769         (void)hns3_update_link_status(hw);
2770
2771         ret = hns3_update_link_info(eth_dev);
2772         if (ret)
2773                 hw->mac.link_status = RTE_ETH_LINK_DOWN;
2774
2775         return ret;
2776 }
2777
2778 static void
2779 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2780                       struct rte_eth_link *new_link)
2781 {
2782         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2783         struct hns3_mac *mac = &hw->mac;
2784
2785         switch (mac->link_speed) {
2786         case RTE_ETH_SPEED_NUM_10M:
2787         case RTE_ETH_SPEED_NUM_100M:
2788         case RTE_ETH_SPEED_NUM_1G:
2789         case RTE_ETH_SPEED_NUM_10G:
2790         case RTE_ETH_SPEED_NUM_25G:
2791         case RTE_ETH_SPEED_NUM_40G:
2792         case RTE_ETH_SPEED_NUM_50G:
2793         case RTE_ETH_SPEED_NUM_100G:
2794         case RTE_ETH_SPEED_NUM_200G:
2795                 if (mac->link_status)
2796                         new_link->link_speed = mac->link_speed;
2797                 break;
2798         default:
2799                 if (mac->link_status)
2800                         new_link->link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2801                 break;
2802         }
2803
2804         if (!mac->link_status)
2805                 new_link->link_speed = RTE_ETH_SPEED_NUM_NONE;
2806
2807         new_link->link_duplex = mac->link_duplex;
2808         new_link->link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2809         new_link->link_autoneg = mac->link_autoneg;
2810 }
2811
2812 static int
2813 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2814 {
2815 #define HNS3_LINK_CHECK_INTERVAL 100  /* 100ms */
2816 #define HNS3_MAX_LINK_CHECK_TIMES 20  /* 2s (100 * 20ms) in total */
2817
2818         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2819         uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2820         struct hns3_mac *mac = &hw->mac;
2821         struct rte_eth_link new_link;
2822         int ret;
2823
2824         /* When port is stopped, report link down. */
2825         if (eth_dev->data->dev_started == 0) {
2826                 new_link.link_autoneg = mac->link_autoneg;
2827                 new_link.link_duplex = mac->link_duplex;
2828                 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2829                 new_link.link_status = RTE_ETH_LINK_DOWN;
2830                 goto out;
2831         }
2832
2833         do {
2834                 ret = hns3_update_port_link_info(eth_dev);
2835                 if (ret) {
2836                         hns3_err(hw, "failed to get port link info, ret = %d.",
2837                                  ret);
2838                         break;
2839                 }
2840
2841                 if (!wait_to_complete || mac->link_status == RTE_ETH_LINK_UP)
2842                         break;
2843
2844                 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2845         } while (retry_cnt--);
2846
2847         memset(&new_link, 0, sizeof(new_link));
2848         hns3_setup_linkstatus(eth_dev, &new_link);
2849
2850 out:
2851         return rte_eth_linkstatus_set(eth_dev, &new_link);
2852 }
2853
2854 static int
2855 hns3_dev_set_link_up(struct rte_eth_dev *dev)
2856 {
2857         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2858         int ret;
2859
2860         /*
2861          * The "tx_pkt_burst" will be restored. But the secondary process does
2862          * not support the mechanism for notifying the primary process.
2863          */
2864         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2865                 hns3_err(hw, "secondary process does not support to set link up.");
2866                 return -ENOTSUP;
2867         }
2868
2869         /*
2870          * If device isn't started Rx/Tx function is still disabled, setting
2871          * link up is not allowed. But it is probably better to return success
2872          * to reduce the impact on the upper layer.
2873          */
2874         if (hw->adapter_state != HNS3_NIC_STARTED) {
2875                 hns3_info(hw, "device isn't started, can't set link up.");
2876                 return 0;
2877         }
2878
2879         if (!hw->set_link_down)
2880                 return 0;
2881
2882         rte_spinlock_lock(&hw->lock);
2883         ret = hns3_cfg_mac_mode(hw, true);
2884         if (ret) {
2885                 rte_spinlock_unlock(&hw->lock);
2886                 hns3_err(hw, "failed to set link up, ret = %d", ret);
2887                 return ret;
2888         }
2889
2890         hw->set_link_down = false;
2891         hns3_start_tx_datapath(dev);
2892         rte_spinlock_unlock(&hw->lock);
2893
2894         return 0;
2895 }
2896
2897 static int
2898 hns3_dev_set_link_down(struct rte_eth_dev *dev)
2899 {
2900         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2901         int ret;
2902
2903         /*
2904          * The "tx_pkt_burst" will be set to dummy function. But the secondary
2905          * process does not support the mechanism for notifying the primary
2906          * process.
2907          */
2908         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2909                 hns3_err(hw, "secondary process does not support to set link down.");
2910                 return -ENOTSUP;
2911         }
2912
2913         /*
2914          * If device isn't started or the API has been called, link status is
2915          * down, return success.
2916          */
2917         if (hw->adapter_state != HNS3_NIC_STARTED || hw->set_link_down)
2918                 return 0;
2919
2920         rte_spinlock_lock(&hw->lock);
2921         hns3_stop_tx_datapath(dev);
2922         ret = hns3_cfg_mac_mode(hw, false);
2923         if (ret) {
2924                 hns3_start_tx_datapath(dev);
2925                 rte_spinlock_unlock(&hw->lock);
2926                 hns3_err(hw, "failed to set link down, ret = %d", ret);
2927                 return ret;
2928         }
2929
2930         hw->set_link_down = true;
2931         rte_spinlock_unlock(&hw->lock);
2932
2933         return 0;
2934 }
2935
2936 static int
2937 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2938 {
2939         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2940         struct hns3_pf *pf = &hns->pf;
2941
2942         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2943                 return -EINVAL;
2944
2945         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2946
2947         return 0;
2948 }
2949
2950 static int
2951 hns3_query_function_status(struct hns3_hw *hw)
2952 {
2953 #define HNS3_QUERY_MAX_CNT              10
2954 #define HNS3_QUERY_SLEEP_MSCOEND        1
2955         struct hns3_func_status_cmd *req;
2956         struct hns3_cmd_desc desc;
2957         int timeout = 0;
2958         int ret;
2959
2960         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2961         req = (struct hns3_func_status_cmd *)desc.data;
2962
2963         do {
2964                 ret = hns3_cmd_send(hw, &desc, 1);
2965                 if (ret) {
2966                         PMD_INIT_LOG(ERR, "query function status failed %d",
2967                                      ret);
2968                         return ret;
2969                 }
2970
2971                 /* Check pf reset is done */
2972                 if (req->pf_state)
2973                         break;
2974
2975                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2976         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2977
2978         return hns3_parse_func_status(hw, req);
2979 }
2980
2981 static int
2982 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2983 {
2984         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2985         struct hns3_pf *pf = &hns->pf;
2986
2987         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2988                 /*
2989                  * The total_tqps_num obtained from firmware is maximum tqp
2990                  * numbers of this port, which should be used for PF and VFs.
2991                  * There is no need for pf to have so many tqp numbers in
2992                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2993                  * coming from config file, is assigned to maximum queue number
2994                  * for the PF of this port by user. So users can modify the
2995                  * maximum queue number of PF according to their own application
2996                  * scenarios, which is more flexible to use. In addition, many
2997                  * memories can be saved due to allocating queue statistics
2998                  * room according to the actual number of queues required. The
2999                  * maximum queue number of PF for network engine with
3000                  * revision_id greater than 0x30 is assigned by config file.
3001                  */
3002                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
3003                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
3004                                  "must be greater than 0.",
3005                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
3006                         return -EINVAL;
3007                 }
3008
3009                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
3010                                        hw->total_tqps_num);
3011         } else {
3012                 /*
3013                  * Due to the limitation on the number of PF interrupts
3014                  * available, the maximum queue number assigned to PF on
3015                  * the network engine with revision_id 0x21 is 64.
3016                  */
3017                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
3018                                        HNS3_MAX_TQP_NUM_HIP08_PF);
3019         }
3020
3021         return 0;
3022 }
3023
3024 static int
3025 hns3_query_pf_resource(struct hns3_hw *hw)
3026 {
3027         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3028         struct hns3_pf *pf = &hns->pf;
3029         struct hns3_pf_res_cmd *req;
3030         struct hns3_cmd_desc desc;
3031         int ret;
3032
3033         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
3034         ret = hns3_cmd_send(hw, &desc, 1);
3035         if (ret) {
3036                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
3037                 return ret;
3038         }
3039
3040         req = (struct hns3_pf_res_cmd *)desc.data;
3041         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
3042                              rte_le_to_cpu_16(req->ext_tqp_num);
3043         ret = hns3_get_pf_max_tqp_num(hw);
3044         if (ret)
3045                 return ret;
3046
3047         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
3048         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
3049
3050         if (req->tx_buf_size)
3051                 pf->tx_buf_size =
3052                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
3053         else
3054                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
3055
3056         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
3057
3058         if (req->dv_buf_size)
3059                 pf->dv_buf_size =
3060                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3061         else
3062                 pf->dv_buf_size = HNS3_DEFAULT_DV;
3063
3064         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3065
3066         hw->num_msi =
3067                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3068                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3069
3070         return 0;
3071 }
3072
3073 static void
3074 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3075 {
3076         struct hns3_cfg_param_cmd *req;
3077         uint64_t mac_addr_tmp_high;
3078         uint8_t ext_rss_size_max;
3079         uint64_t mac_addr_tmp;
3080         uint32_t i;
3081
3082         req = (struct hns3_cfg_param_cmd *)desc[0].data;
3083
3084         /* get the configuration */
3085         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3086                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3087         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3088                                            HNS3_CFG_TQP_DESC_N_M,
3089                                            HNS3_CFG_TQP_DESC_N_S);
3090
3091         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3092                                        HNS3_CFG_PHY_ADDR_M,
3093                                        HNS3_CFG_PHY_ADDR_S);
3094         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3095                                          HNS3_CFG_MEDIA_TP_M,
3096                                          HNS3_CFG_MEDIA_TP_S);
3097         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3098                                          HNS3_CFG_RX_BUF_LEN_M,
3099                                          HNS3_CFG_RX_BUF_LEN_S);
3100         /* get mac address */
3101         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3102         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3103                                            HNS3_CFG_MAC_ADDR_H_M,
3104                                            HNS3_CFG_MAC_ADDR_H_S);
3105
3106         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3107
3108         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3109                                             HNS3_CFG_DEFAULT_SPEED_M,
3110                                             HNS3_CFG_DEFAULT_SPEED_S);
3111         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3112                                            HNS3_CFG_RSS_SIZE_M,
3113                                            HNS3_CFG_RSS_SIZE_S);
3114
3115         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3116                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3117
3118         req = (struct hns3_cfg_param_cmd *)desc[1].data;
3119         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3120
3121         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3122                                             HNS3_CFG_SPEED_ABILITY_M,
3123                                             HNS3_CFG_SPEED_ABILITY_S);
3124         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3125                                         HNS3_CFG_UMV_TBL_SPACE_M,
3126                                         HNS3_CFG_UMV_TBL_SPACE_S);
3127         if (!cfg->umv_space)
3128                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3129
3130         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3131                                                HNS3_CFG_EXT_RSS_SIZE_M,
3132                                                HNS3_CFG_EXT_RSS_SIZE_S);
3133         /*
3134          * Field ext_rss_size_max obtained from firmware will be more flexible
3135          * for future changes and expansions, which is an exponent of 2, instead
3136          * of reading out directly. If this field is not zero, hns3 PF PMD
3137          * driver uses it as rss_size_max under one TC. Device, whose revision
3138          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3139          * maximum number of queues supported under a TC through this field.
3140          */
3141         if (ext_rss_size_max)
3142                 cfg->rss_size_max = 1U << ext_rss_size_max;
3143 }
3144
3145 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3146  * @hw: pointer to struct hns3_hw
3147  * @hcfg: the config structure to be getted
3148  */
3149 static int
3150 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3151 {
3152         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3153         struct hns3_cfg_param_cmd *req;
3154         uint32_t offset;
3155         uint32_t i;
3156         int ret;
3157
3158         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3159                 offset = 0;
3160                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3161                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3162                                           true);
3163                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3164                                i * HNS3_CFG_RD_LEN_BYTES);
3165                 /* Len should be divided by 4 when send to hardware */
3166                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3167                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3168                 req->offset = rte_cpu_to_le_32(offset);
3169         }
3170
3171         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3172         if (ret) {
3173                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3174                 return ret;
3175         }
3176
3177         hns3_parse_cfg(hcfg, desc);
3178
3179         return 0;
3180 }
3181
3182 static int
3183 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3184 {
3185         switch (speed_cmd) {
3186         case HNS3_CFG_SPEED_10M:
3187                 *speed = RTE_ETH_SPEED_NUM_10M;
3188                 break;
3189         case HNS3_CFG_SPEED_100M:
3190                 *speed = RTE_ETH_SPEED_NUM_100M;
3191                 break;
3192         case HNS3_CFG_SPEED_1G:
3193                 *speed = RTE_ETH_SPEED_NUM_1G;
3194                 break;
3195         case HNS3_CFG_SPEED_10G:
3196                 *speed = RTE_ETH_SPEED_NUM_10G;
3197                 break;
3198         case HNS3_CFG_SPEED_25G:
3199                 *speed = RTE_ETH_SPEED_NUM_25G;
3200                 break;
3201         case HNS3_CFG_SPEED_40G:
3202                 *speed = RTE_ETH_SPEED_NUM_40G;
3203                 break;
3204         case HNS3_CFG_SPEED_50G:
3205                 *speed = RTE_ETH_SPEED_NUM_50G;
3206                 break;
3207         case HNS3_CFG_SPEED_100G:
3208                 *speed = RTE_ETH_SPEED_NUM_100G;
3209                 break;
3210         case HNS3_CFG_SPEED_200G:
3211                 *speed = RTE_ETH_SPEED_NUM_200G;
3212                 break;
3213         default:
3214                 return -EINVAL;
3215         }
3216
3217         return 0;
3218 }
3219
3220 static void
3221 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3222 {
3223         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3224         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3225         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3226         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3227         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3228 }
3229
3230 static void
3231 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3232 {
3233         struct hns3_dev_specs_0_cmd *req0;
3234
3235         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3236
3237         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3238         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3239         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3240         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3241         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3242 }
3243
3244 static int
3245 hns3_check_dev_specifications(struct hns3_hw *hw)
3246 {
3247         if (hw->rss_ind_tbl_size == 0 ||
3248             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3249                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3250                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3251                               HNS3_RSS_IND_TBL_SIZE_MAX);
3252                 return -EINVAL;
3253         }
3254
3255         return 0;
3256 }
3257
3258 static int
3259 hns3_query_dev_specifications(struct hns3_hw *hw)
3260 {
3261         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3262         int ret;
3263         int i;
3264
3265         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3266                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3267                                           true);
3268                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3269         }
3270         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3271
3272         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3273         if (ret)
3274                 return ret;
3275
3276         hns3_parse_dev_specifications(hw, desc);
3277
3278         return hns3_check_dev_specifications(hw);
3279 }
3280
3281 static int
3282 hns3_get_capability(struct hns3_hw *hw)
3283 {
3284         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3285         struct rte_pci_device *pci_dev;
3286         struct hns3_pf *pf = &hns->pf;
3287         struct rte_eth_dev *eth_dev;
3288         uint16_t device_id;
3289         uint8_t revision;
3290         int ret;
3291
3292         eth_dev = &rte_eth_devices[hw->data->port_id];
3293         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3294         device_id = pci_dev->id.device_id;
3295
3296         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3297             device_id == HNS3_DEV_ID_50GE_RDMA ||
3298             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3299             device_id == HNS3_DEV_ID_200G_RDMA)
3300                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3301
3302         /* Get PCI revision id */
3303         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3304                                   HNS3_PCI_REVISION_ID);
3305         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3306                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3307                              ret);
3308                 return -EIO;
3309         }
3310         hw->revision = revision;
3311
3312         if (revision < PCI_REVISION_ID_HIP09_A) {
3313                 hns3_set_default_dev_specifications(hw);
3314                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3315                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3316                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3317                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3318                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3319                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3320                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3321                 hw->rss_info.ipv6_sctp_offload_supported = false;
3322                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3323                 pf->support_multi_tc_pause = false;
3324                 return 0;
3325         }
3326
3327         ret = hns3_query_dev_specifications(hw);
3328         if (ret) {
3329                 PMD_INIT_LOG(ERR,
3330                              "failed to query dev specifications, ret = %d",
3331                              ret);
3332                 return ret;
3333         }
3334
3335         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3336         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3337         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3338         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3339         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3340         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3341         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3342         hw->rss_info.ipv6_sctp_offload_supported = true;
3343         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3344         pf->support_multi_tc_pause = true;
3345
3346         return 0;
3347 }
3348
3349 static int
3350 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3351 {
3352         int ret;
3353
3354         switch (media_type) {
3355         case HNS3_MEDIA_TYPE_COPPER:
3356                 if (!hns3_dev_get_support(hw, COPPER)) {
3357                         PMD_INIT_LOG(ERR,
3358                                      "Media type is copper, not supported.");
3359                         ret = -EOPNOTSUPP;
3360                 } else {
3361                         ret = 0;
3362                 }
3363                 break;
3364         case HNS3_MEDIA_TYPE_FIBER:
3365                 ret = 0;
3366                 break;
3367         case HNS3_MEDIA_TYPE_BACKPLANE:
3368                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3369                 ret = -EOPNOTSUPP;
3370                 break;
3371         default:
3372                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3373                 ret = -EINVAL;
3374                 break;
3375         }
3376
3377         return ret;
3378 }
3379
3380 static int
3381 hns3_get_board_configuration(struct hns3_hw *hw)
3382 {
3383         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3384         struct hns3_pf *pf = &hns->pf;
3385         struct hns3_cfg cfg;
3386         int ret;
3387
3388         ret = hns3_get_board_cfg(hw, &cfg);
3389         if (ret) {
3390                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3391                 return ret;
3392         }
3393
3394         ret = hns3_check_media_type(hw, cfg.media_type);
3395         if (ret)
3396                 return ret;
3397
3398         hw->mac.media_type = cfg.media_type;
3399         hw->rss_size_max = cfg.rss_size_max;
3400         hw->rss_dis_flag = false;
3401         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3402         hw->mac.phy_addr = cfg.phy_addr;
3403         hw->num_tx_desc = cfg.tqp_desc_num;
3404         hw->num_rx_desc = cfg.tqp_desc_num;
3405         hw->dcb_info.num_pg = 1;
3406         hw->dcb_info.hw_pfc_map = 0;
3407
3408         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3409         if (ret) {
3410                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3411                              cfg.default_speed, ret);
3412                 return ret;
3413         }
3414
3415         pf->tc_max = cfg.tc_num;
3416         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3417                 PMD_INIT_LOG(WARNING,
3418                              "Get TC num(%u) from flash, set TC num to 1",
3419                              pf->tc_max);
3420                 pf->tc_max = 1;
3421         }
3422
3423         /* Dev does not support DCB */
3424         if (!hns3_dev_get_support(hw, DCB)) {
3425                 pf->tc_max = 1;
3426                 pf->pfc_max = 0;
3427         } else
3428                 pf->pfc_max = pf->tc_max;
3429
3430         hw->dcb_info.num_tc = 1;
3431         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3432                                      hw->tqps_num / hw->dcb_info.num_tc);
3433         hns3_set_bit(hw->hw_tc_map, 0, 1);
3434         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3435
3436         pf->wanted_umv_size = cfg.umv_space;
3437
3438         return ret;
3439 }
3440
3441 static int
3442 hns3_get_configuration(struct hns3_hw *hw)
3443 {
3444         int ret;
3445
3446         ret = hns3_query_function_status(hw);
3447         if (ret) {
3448                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3449                 return ret;
3450         }
3451
3452         /* Get device capability */
3453         ret = hns3_get_capability(hw);
3454         if (ret) {
3455                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3456                 return ret;
3457         }
3458
3459         /* Get pf resource */
3460         ret = hns3_query_pf_resource(hw);
3461         if (ret) {
3462                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3463                 return ret;
3464         }
3465
3466         ret = hns3_get_board_configuration(hw);
3467         if (ret) {
3468                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3469                 return ret;
3470         }
3471
3472         ret = hns3_query_dev_fec_info(hw);
3473         if (ret)
3474                 PMD_INIT_LOG(ERR,
3475                              "failed to query FEC information, ret = %d", ret);
3476
3477         return ret;
3478 }
3479
3480 static int
3481 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3482                       uint16_t tqp_vid, bool is_pf)
3483 {
3484         struct hns3_tqp_map_cmd *req;
3485         struct hns3_cmd_desc desc;
3486         int ret;
3487
3488         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3489
3490         req = (struct hns3_tqp_map_cmd *)desc.data;
3491         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3492         req->tqp_vf = func_id;
3493         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3494         if (!is_pf)
3495                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3496         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3497
3498         ret = hns3_cmd_send(hw, &desc, 1);
3499         if (ret)
3500                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3501
3502         return ret;
3503 }
3504
3505 static int
3506 hns3_map_tqp(struct hns3_hw *hw)
3507 {
3508         int ret;
3509         int i;
3510
3511         /*
3512          * In current version, VF is not supported when PF is driven by DPDK
3513          * driver, so we assign total tqps_num tqps allocated to this port
3514          * to PF.
3515          */
3516         for (i = 0; i < hw->total_tqps_num; i++) {
3517                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3518                 if (ret)
3519                         return ret;
3520         }
3521
3522         return 0;
3523 }
3524
3525 static int
3526 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3527 {
3528         struct hns3_config_mac_speed_dup_cmd *req;
3529         struct hns3_cmd_desc desc;
3530         int ret;
3531
3532         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3533
3534         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3535
3536         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3537
3538         switch (speed) {
3539         case RTE_ETH_SPEED_NUM_10M:
3540                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3541                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3542                 break;
3543         case RTE_ETH_SPEED_NUM_100M:
3544                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3545                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3546                 break;
3547         case RTE_ETH_SPEED_NUM_1G:
3548                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3549                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3550                 break;
3551         case RTE_ETH_SPEED_NUM_10G:
3552                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3553                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3554                 break;
3555         case RTE_ETH_SPEED_NUM_25G:
3556                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3557                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3558                 break;
3559         case RTE_ETH_SPEED_NUM_40G:
3560                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3561                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3562                 break;
3563         case RTE_ETH_SPEED_NUM_50G:
3564                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3565                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3566                 break;
3567         case RTE_ETH_SPEED_NUM_100G:
3568                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3569                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3570                 break;
3571         case RTE_ETH_SPEED_NUM_200G:
3572                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3573                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3574                 break;
3575         default:
3576                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3577                 return -EINVAL;
3578         }
3579
3580         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3581
3582         ret = hns3_cmd_send(hw, &desc, 1);
3583         if (ret)
3584                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3585
3586         return ret;
3587 }
3588
3589 static int
3590 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3591 {
3592         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3593         struct hns3_pf *pf = &hns->pf;
3594         struct hns3_priv_buf *priv;
3595         uint32_t i, total_size;
3596
3597         total_size = pf->pkt_buf_size;
3598
3599         /* alloc tx buffer for all enabled tc */
3600         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3601                 priv = &buf_alloc->priv_buf[i];
3602
3603                 if (hw->hw_tc_map & BIT(i)) {
3604                         if (total_size < pf->tx_buf_size)
3605                                 return -ENOMEM;
3606
3607                         priv->tx_buf_size = pf->tx_buf_size;
3608                 } else
3609                         priv->tx_buf_size = 0;
3610
3611                 total_size -= priv->tx_buf_size;
3612         }
3613
3614         return 0;
3615 }
3616
3617 static int
3618 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3619 {
3620 /* TX buffer size is unit by 128 byte */
3621 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3622 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3623         struct hns3_tx_buff_alloc_cmd *req;
3624         struct hns3_cmd_desc desc;
3625         uint32_t buf_size;
3626         uint32_t i;
3627         int ret;
3628
3629         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3630
3631         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3632         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3633                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3634
3635                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3636                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3637                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3638         }
3639
3640         ret = hns3_cmd_send(hw, &desc, 1);
3641         if (ret)
3642                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3643
3644         return ret;
3645 }
3646
3647 static int
3648 hns3_get_tc_num(struct hns3_hw *hw)
3649 {
3650         int cnt = 0;
3651         uint8_t i;
3652
3653         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3654                 if (hw->hw_tc_map & BIT(i))
3655                         cnt++;
3656         return cnt;
3657 }
3658
3659 static uint32_t
3660 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3661 {
3662         struct hns3_priv_buf *priv;
3663         uint32_t rx_priv = 0;
3664         int i;
3665
3666         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3667                 priv = &buf_alloc->priv_buf[i];
3668                 if (priv->enable)
3669                         rx_priv += priv->buf_size;
3670         }
3671         return rx_priv;
3672 }
3673
3674 static uint32_t
3675 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3676 {
3677         uint32_t total_tx_size = 0;
3678         uint32_t i;
3679
3680         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3681                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3682
3683         return total_tx_size;
3684 }
3685
3686 /* Get the number of pfc enabled TCs, which have private buffer */
3687 static int
3688 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3689 {
3690         struct hns3_priv_buf *priv;
3691         int cnt = 0;
3692         uint8_t i;
3693
3694         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3695                 priv = &buf_alloc->priv_buf[i];
3696                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3697                         cnt++;
3698         }
3699
3700         return cnt;
3701 }
3702
3703 /* Get the number of pfc disabled TCs, which have private buffer */
3704 static int
3705 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3706                          struct hns3_pkt_buf_alloc *buf_alloc)
3707 {
3708         struct hns3_priv_buf *priv;
3709         int cnt = 0;
3710         uint8_t i;
3711
3712         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3713                 priv = &buf_alloc->priv_buf[i];
3714                 if (hw->hw_tc_map & BIT(i) &&
3715                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3716                         cnt++;
3717         }
3718
3719         return cnt;
3720 }
3721
3722 static bool
3723 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3724                   uint32_t rx_all)
3725 {
3726         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3727         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3728         struct hns3_pf *pf = &hns->pf;
3729         uint32_t shared_buf, aligned_mps;
3730         uint32_t rx_priv;
3731         uint8_t tc_num;
3732         uint8_t i;
3733
3734         tc_num = hns3_get_tc_num(hw);
3735         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3736
3737         if (hns3_dev_get_support(hw, DCB))
3738                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3739                                         pf->dv_buf_size;
3740         else
3741                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3742                                         + pf->dv_buf_size;
3743
3744         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3745         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3746                              HNS3_BUF_SIZE_UNIT);
3747
3748         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3749         if (rx_all < rx_priv + shared_std)
3750                 return false;
3751
3752         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3753         buf_alloc->s_buf.buf_size = shared_buf;
3754         if (hns3_dev_get_support(hw, DCB)) {
3755                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3756                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3757                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3758                                   HNS3_BUF_SIZE_UNIT);
3759         } else {
3760                 buf_alloc->s_buf.self.high =
3761                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3762                 buf_alloc->s_buf.self.low = aligned_mps;
3763         }
3764
3765         if (hns3_dev_get_support(hw, DCB)) {
3766                 hi_thrd = shared_buf - pf->dv_buf_size;
3767
3768                 if (tc_num <= NEED_RESERVE_TC_NUM)
3769                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3770                                   BUF_MAX_PERCENT;
3771
3772                 if (tc_num)
3773                         hi_thrd = hi_thrd / tc_num;
3774
3775                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3776                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3777                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3778         } else {
3779                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3780                 lo_thrd = aligned_mps;
3781         }
3782
3783         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3784                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3785                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3786         }
3787
3788         return true;
3789 }
3790
3791 static bool
3792 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3793                      struct hns3_pkt_buf_alloc *buf_alloc)
3794 {
3795         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3796         struct hns3_pf *pf = &hns->pf;
3797         struct hns3_priv_buf *priv;
3798         uint32_t aligned_mps;
3799         uint32_t rx_all;
3800         uint8_t i;
3801
3802         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3803         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3804
3805         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3806                 priv = &buf_alloc->priv_buf[i];
3807
3808                 priv->enable = 0;
3809                 priv->wl.low = 0;
3810                 priv->wl.high = 0;
3811                 priv->buf_size = 0;
3812
3813                 if (!(hw->hw_tc_map & BIT(i)))
3814                         continue;
3815
3816                 priv->enable = 1;
3817                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3818                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3819                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3820                                                 HNS3_BUF_SIZE_UNIT);
3821                 } else {
3822                         priv->wl.low = 0;
3823                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3824                                         aligned_mps;
3825                 }
3826
3827                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3828         }
3829
3830         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3831 }
3832
3833 static bool
3834 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3835                              struct hns3_pkt_buf_alloc *buf_alloc)
3836 {
3837         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3838         struct hns3_pf *pf = &hns->pf;
3839         struct hns3_priv_buf *priv;
3840         int no_pfc_priv_num;
3841         uint32_t rx_all;
3842         uint8_t mask;
3843         int i;
3844
3845         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3846         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3847
3848         /* let the last to be cleared first */
3849         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3850                 priv = &buf_alloc->priv_buf[i];
3851                 mask = BIT((uint8_t)i);
3852                 if (hw->hw_tc_map & mask &&
3853                     !(hw->dcb_info.hw_pfc_map & mask)) {
3854                         /* Clear the no pfc TC private buffer */
3855                         priv->wl.low = 0;
3856                         priv->wl.high = 0;
3857                         priv->buf_size = 0;
3858                         priv->enable = 0;
3859                         no_pfc_priv_num--;
3860                 }
3861
3862                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3863                     no_pfc_priv_num == 0)
3864                         break;
3865         }
3866
3867         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3868 }
3869
3870 static bool
3871 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3872                            struct hns3_pkt_buf_alloc *buf_alloc)
3873 {
3874         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3875         struct hns3_pf *pf = &hns->pf;
3876         struct hns3_priv_buf *priv;
3877         uint32_t rx_all;
3878         int pfc_priv_num;
3879         uint8_t mask;
3880         int i;
3881
3882         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3883         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3884
3885         /* let the last to be cleared first */
3886         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3887                 priv = &buf_alloc->priv_buf[i];
3888                 mask = BIT((uint8_t)i);
3889                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3890                         /* Reduce the number of pfc TC with private buffer */
3891                         priv->wl.low = 0;
3892                         priv->enable = 0;
3893                         priv->wl.high = 0;
3894                         priv->buf_size = 0;
3895                         pfc_priv_num--;
3896                 }
3897                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3898                     pfc_priv_num == 0)
3899                         break;
3900         }
3901
3902         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3903 }
3904
3905 static bool
3906 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3907                           struct hns3_pkt_buf_alloc *buf_alloc)
3908 {
3909 #define COMPENSATE_BUFFER       0x3C00
3910 #define COMPENSATE_HALF_MPS_NUM 5
3911 #define PRIV_WL_GAP             0x1800
3912         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3913         struct hns3_pf *pf = &hns->pf;
3914         uint32_t tc_num = hns3_get_tc_num(hw);
3915         uint32_t half_mps = pf->mps >> 1;
3916         struct hns3_priv_buf *priv;
3917         uint32_t min_rx_priv;
3918         uint32_t rx_priv;
3919         uint8_t i;
3920
3921         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3922         if (tc_num)
3923                 rx_priv = rx_priv / tc_num;
3924
3925         if (tc_num <= NEED_RESERVE_TC_NUM)
3926                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3927
3928         /*
3929          * Minimum value of private buffer in rx direction (min_rx_priv) is
3930          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3931          * buffer if rx_priv is greater than min_rx_priv.
3932          */
3933         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3934                         COMPENSATE_HALF_MPS_NUM * half_mps;
3935         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3936         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3937         if (rx_priv < min_rx_priv)
3938                 return false;
3939
3940         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3941                 priv = &buf_alloc->priv_buf[i];
3942                 priv->enable = 0;
3943                 priv->wl.low = 0;
3944                 priv->wl.high = 0;
3945                 priv->buf_size = 0;
3946
3947                 if (!(hw->hw_tc_map & BIT(i)))
3948                         continue;
3949
3950                 priv->enable = 1;
3951                 priv->buf_size = rx_priv;
3952                 priv->wl.high = rx_priv - pf->dv_buf_size;
3953                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3954         }
3955
3956         buf_alloc->s_buf.buf_size = 0;
3957
3958         return true;
3959 }
3960
3961 /*
3962  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3963  * @hw: pointer to struct hns3_hw
3964  * @buf_alloc: pointer to buffer calculation data
3965  * @return: 0: calculate sucessful, negative: fail
3966  */
3967 static int
3968 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3969 {
3970         /* When DCB is not supported, rx private buffer is not allocated. */
3971         if (!hns3_dev_get_support(hw, DCB)) {
3972                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3973                 struct hns3_pf *pf = &hns->pf;
3974                 uint32_t rx_all = pf->pkt_buf_size;
3975
3976                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3977                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3978                         return -ENOMEM;
3979
3980                 return 0;
3981         }
3982
3983         /*
3984          * Try to allocate privated packet buffer for all TCs without share
3985          * buffer.
3986          */
3987         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3988                 return 0;
3989
3990         /*
3991          * Try to allocate privated packet buffer for all TCs with share
3992          * buffer.
3993          */
3994         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3995                 return 0;
3996
3997         /*
3998          * For different application scenes, the enabled port number, TC number
3999          * and no_drop TC number are different. In order to obtain the better
4000          * performance, software could allocate the buffer size and configure
4001          * the waterline by trying to decrease the private buffer size according
4002          * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
4003          * enabled tc.
4004          */
4005         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
4006                 return 0;
4007
4008         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
4009                 return 0;
4010
4011         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
4012                 return 0;
4013
4014         return -ENOMEM;
4015 }
4016
4017 static int
4018 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4019 {
4020         struct hns3_rx_priv_buff_cmd *req;
4021         struct hns3_cmd_desc desc;
4022         uint32_t buf_size;
4023         int ret;
4024         int i;
4025
4026         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
4027         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
4028
4029         /* Alloc private buffer TCs */
4030         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4031                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
4032
4033                 req->buf_num[i] =
4034                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
4035                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
4036         }
4037
4038         buf_size = buf_alloc->s_buf.buf_size;
4039         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
4040                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
4041
4042         ret = hns3_cmd_send(hw, &desc, 1);
4043         if (ret)
4044                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
4045
4046         return ret;
4047 }
4048
4049 static int
4050 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4051 {
4052 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
4053         struct hns3_rx_priv_wl_buf *req;
4054         struct hns3_priv_buf *priv;
4055         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4056         int i, j;
4057         int ret;
4058
4059         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4060                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4061                                           false);
4062                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4063
4064                 /* The first descriptor set the NEXT bit to 1 */
4065                 if (i == 0)
4066                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4067                 else
4068                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4069
4070                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4071                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4072
4073                         priv = &buf_alloc->priv_buf[idx];
4074                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4075                                                         HNS3_BUF_UNIT_S);
4076                         req->tc_wl[j].high |=
4077                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4078                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4079                                                         HNS3_BUF_UNIT_S);
4080                         req->tc_wl[j].low |=
4081                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4082                 }
4083         }
4084
4085         /* Send 2 descriptor at one time */
4086         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4087         if (ret)
4088                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4089                              ret);
4090         return ret;
4091 }
4092
4093 static int
4094 hns3_common_thrd_config(struct hns3_hw *hw,
4095                         struct hns3_pkt_buf_alloc *buf_alloc)
4096 {
4097 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4098         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4099         struct hns3_rx_com_thrd *req;
4100         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4101         struct hns3_tc_thrd *tc;
4102         int tc_idx;
4103         int i, j;
4104         int ret;
4105
4106         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4107                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4108                                           false);
4109                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4110
4111                 /* The first descriptor set the NEXT bit to 1 */
4112                 if (i == 0)
4113                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4114                 else
4115                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4116
4117                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4118                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4119                         tc = &s_buf->tc_thrd[tc_idx];
4120
4121                         req->com_thrd[j].high =
4122                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4123                         req->com_thrd[j].high |=
4124                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4125                         req->com_thrd[j].low =
4126                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4127                         req->com_thrd[j].low |=
4128                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4129                 }
4130         }
4131
4132         /* Send 2 descriptors at one time */
4133         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4134         if (ret)
4135                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4136
4137         return ret;
4138 }
4139
4140 static int
4141 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4142 {
4143         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4144         struct hns3_rx_com_wl *req;
4145         struct hns3_cmd_desc desc;
4146         int ret;
4147
4148         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4149
4150         req = (struct hns3_rx_com_wl *)desc.data;
4151         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4152         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4153
4154         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4155         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4156
4157         ret = hns3_cmd_send(hw, &desc, 1);
4158         if (ret)
4159                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4160
4161         return ret;
4162 }
4163
4164 int
4165 hns3_buffer_alloc(struct hns3_hw *hw)
4166 {
4167         struct hns3_pkt_buf_alloc pkt_buf;
4168         int ret;
4169
4170         memset(&pkt_buf, 0, sizeof(pkt_buf));
4171         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4172         if (ret) {
4173                 PMD_INIT_LOG(ERR,
4174                              "could not calc tx buffer size for all TCs %d",
4175                              ret);
4176                 return ret;
4177         }
4178
4179         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4180         if (ret) {
4181                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4182                 return ret;
4183         }
4184
4185         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4186         if (ret) {
4187                 PMD_INIT_LOG(ERR,
4188                              "could not calc rx priv buffer size for all TCs %d",
4189                              ret);
4190                 return ret;
4191         }
4192
4193         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4194         if (ret) {
4195                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4196                 return ret;
4197         }
4198
4199         if (hns3_dev_get_support(hw, DCB)) {
4200                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4201                 if (ret) {
4202                         PMD_INIT_LOG(ERR,
4203                                      "could not configure rx private waterline %d",
4204                                      ret);
4205                         return ret;
4206                 }
4207
4208                 ret = hns3_common_thrd_config(hw, &pkt_buf);
4209                 if (ret) {
4210                         PMD_INIT_LOG(ERR,
4211                                      "could not configure common threshold %d",
4212                                      ret);
4213                         return ret;
4214                 }
4215         }
4216
4217         ret = hns3_common_wl_config(hw, &pkt_buf);
4218         if (ret)
4219                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4220                              ret);
4221
4222         return ret;
4223 }
4224
4225 static int
4226 hns3_mac_init(struct hns3_hw *hw)
4227 {
4228         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4229         struct hns3_mac *mac = &hw->mac;
4230         struct hns3_pf *pf = &hns->pf;
4231         int ret;
4232
4233         pf->support_sfp_query = true;
4234         mac->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
4235         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4236         if (ret) {
4237                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4238                 return ret;
4239         }
4240
4241         mac->link_status = RTE_ETH_LINK_DOWN;
4242
4243         return hns3_config_mtu(hw, pf->mps);
4244 }
4245
4246 static int
4247 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4248 {
4249 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4250 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4251 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4252 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4253         int return_status;
4254
4255         if (cmdq_resp) {
4256                 PMD_INIT_LOG(ERR,
4257                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4258                              cmdq_resp);
4259                 return -EIO;
4260         }
4261
4262         switch (resp_code) {
4263         case HNS3_ETHERTYPE_SUCCESS_ADD:
4264         case HNS3_ETHERTYPE_ALREADY_ADD:
4265                 return_status = 0;
4266                 break;
4267         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4268                 PMD_INIT_LOG(ERR,
4269                              "add mac ethertype failed for manager table overflow.");
4270                 return_status = -EIO;
4271                 break;
4272         case HNS3_ETHERTYPE_KEY_CONFLICT:
4273                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4274                 return_status = -EIO;
4275                 break;
4276         default:
4277                 PMD_INIT_LOG(ERR,
4278                              "add mac ethertype failed for undefined, code=%u.",
4279                              resp_code);
4280                 return_status = -EIO;
4281                 break;
4282         }
4283
4284         return return_status;
4285 }
4286
4287 static int
4288 hns3_add_mgr_tbl(struct hns3_hw *hw,
4289                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4290 {
4291         struct hns3_cmd_desc desc;
4292         uint8_t resp_code;
4293         uint16_t retval;
4294         int ret;
4295
4296         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4297         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4298
4299         ret = hns3_cmd_send(hw, &desc, 1);
4300         if (ret) {
4301                 PMD_INIT_LOG(ERR,
4302                              "add mac ethertype failed for cmd_send, ret =%d.",
4303                              ret);
4304                 return ret;
4305         }
4306
4307         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4308         retval = rte_le_to_cpu_16(desc.retval);
4309
4310         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4311 }
4312
4313 static void
4314 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4315                      int *table_item_num)
4316 {
4317         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4318
4319         /*
4320          * In current version, we add one item in management table as below:
4321          * 0x0180C200000E -- LLDP MC address
4322          */
4323         tbl = mgr_table;
4324         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4325         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4326         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4327         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4328         tbl->i_port_bitmap = 0x1;
4329         *table_item_num = 1;
4330 }
4331
4332 static int
4333 hns3_init_mgr_tbl(struct hns3_hw *hw)
4334 {
4335 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4336         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4337         int table_item_num;
4338         int ret;
4339         int i;
4340
4341         memset(mgr_table, 0, sizeof(mgr_table));
4342         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4343         for (i = 0; i < table_item_num; i++) {
4344                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4345                 if (ret) {
4346                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4347                                      ret);
4348                         return ret;
4349                 }
4350         }
4351
4352         return 0;
4353 }
4354
4355 static void
4356 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4357                         bool en_mc, bool en_bc, int vport_id)
4358 {
4359         if (!param)
4360                 return;
4361
4362         memset(param, 0, sizeof(struct hns3_promisc_param));
4363         if (en_uc)
4364                 param->enable = HNS3_PROMISC_EN_UC;
4365         if (en_mc)
4366                 param->enable |= HNS3_PROMISC_EN_MC;
4367         if (en_bc)
4368                 param->enable |= HNS3_PROMISC_EN_BC;
4369         param->vf_id = vport_id;
4370 }
4371
4372 static int
4373 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4374 {
4375         struct hns3_promisc_cfg_cmd *req;
4376         struct hns3_cmd_desc desc;
4377         int ret;
4378
4379         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4380
4381         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4382         req->vf_id = param->vf_id;
4383         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4384             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4385
4386         ret = hns3_cmd_send(hw, &desc, 1);
4387         if (ret)
4388                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4389
4390         return ret;
4391 }
4392
4393 static int
4394 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4395 {
4396         struct hns3_promisc_param param;
4397         bool en_bc_pmc = true;
4398         uint8_t vf_id;
4399
4400         /*
4401          * In current version VF is not supported when PF is driven by DPDK
4402          * driver, just need to configure parameters for PF vport.
4403          */
4404         vf_id = HNS3_PF_FUNC_ID;
4405
4406         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4407         return hns3_cmd_set_promisc_mode(hw, &param);
4408 }
4409
4410 static int
4411 hns3_promisc_init(struct hns3_hw *hw)
4412 {
4413         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4414         struct hns3_pf *pf = &hns->pf;
4415         struct hns3_promisc_param param;
4416         uint16_t func_id;
4417         int ret;
4418
4419         ret = hns3_set_promisc_mode(hw, false, false);
4420         if (ret) {
4421                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4422                 return ret;
4423         }
4424
4425         /*
4426          * In current version VFs are not supported when PF is driven by DPDK
4427          * driver. After PF has been taken over by DPDK, the original VF will
4428          * be invalid. So, there is a possibility of entry residues. It should
4429          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4430          * during init.
4431          */
4432         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4433                 hns3_promisc_param_init(&param, false, false, false, func_id);
4434                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4435                 if (ret) {
4436                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4437                                         " ret = %d", func_id, ret);
4438                         return ret;
4439                 }
4440         }
4441
4442         return 0;
4443 }
4444
4445 static void
4446 hns3_promisc_uninit(struct hns3_hw *hw)
4447 {
4448         struct hns3_promisc_param param;
4449         uint16_t func_id;
4450         int ret;
4451
4452         func_id = HNS3_PF_FUNC_ID;
4453
4454         /*
4455          * In current version VFs are not supported when PF is driven by
4456          * DPDK driver, and VFs' promisc mode status has been cleared during
4457          * init and their status will not change. So just clear PF's promisc
4458          * mode status during uninit.
4459          */
4460         hns3_promisc_param_init(&param, false, false, false, func_id);
4461         ret = hns3_cmd_set_promisc_mode(hw, &param);
4462         if (ret)
4463                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4464                                 " uninit, ret = %d", ret);
4465 }
4466
4467 static int
4468 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4469 {
4470         bool allmulti = dev->data->all_multicast ? true : false;
4471         struct hns3_adapter *hns = dev->data->dev_private;
4472         struct hns3_hw *hw = &hns->hw;
4473         uint64_t offloads;
4474         int err;
4475         int ret;
4476
4477         rte_spinlock_lock(&hw->lock);
4478         ret = hns3_set_promisc_mode(hw, true, true);
4479         if (ret) {
4480                 rte_spinlock_unlock(&hw->lock);
4481                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4482                          ret);
4483                 return ret;
4484         }
4485
4486         /*
4487          * When promiscuous mode was enabled, disable the vlan filter to let
4488          * all packets coming in in the receiving direction.
4489          */
4490         offloads = dev->data->dev_conf.rxmode.offloads;
4491         if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
4492                 ret = hns3_enable_vlan_filter(hns, false);
4493                 if (ret) {
4494                         hns3_err(hw, "failed to enable promiscuous mode due to "
4495                                      "failure to disable vlan filter, ret = %d",
4496                                  ret);
4497                         err = hns3_set_promisc_mode(hw, false, allmulti);
4498                         if (err)
4499                                 hns3_err(hw, "failed to restore promiscuous "
4500                                          "status after disable vlan filter "
4501                                          "failed during enabling promiscuous "
4502                                          "mode, ret = %d", ret);
4503                 }
4504         }
4505
4506         rte_spinlock_unlock(&hw->lock);
4507
4508         return ret;
4509 }
4510
4511 static int
4512 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4513 {
4514         bool allmulti = dev->data->all_multicast ? true : false;
4515         struct hns3_adapter *hns = dev->data->dev_private;
4516         struct hns3_hw *hw = &hns->hw;
4517         uint64_t offloads;
4518         int err;
4519         int ret;
4520
4521         /* If now in all_multicast mode, must remain in all_multicast mode. */
4522         rte_spinlock_lock(&hw->lock);
4523         ret = hns3_set_promisc_mode(hw, false, allmulti);
4524         if (ret) {
4525                 rte_spinlock_unlock(&hw->lock);
4526                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4527                          ret);
4528                 return ret;
4529         }
4530         /* when promiscuous mode was disabled, restore the vlan filter status */
4531         offloads = dev->data->dev_conf.rxmode.offloads;
4532         if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
4533                 ret = hns3_enable_vlan_filter(hns, true);
4534                 if (ret) {
4535                         hns3_err(hw, "failed to disable promiscuous mode due to"
4536                                  " failure to restore vlan filter, ret = %d",
4537                                  ret);
4538                         err = hns3_set_promisc_mode(hw, true, true);
4539                         if (err)
4540                                 hns3_err(hw, "failed to restore promiscuous "
4541                                          "status after enabling vlan filter "
4542                                          "failed during disabling promiscuous "
4543                                          "mode, ret = %d", ret);
4544                 }
4545         }
4546         rte_spinlock_unlock(&hw->lock);
4547
4548         return ret;
4549 }
4550
4551 static int
4552 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4553 {
4554         struct hns3_adapter *hns = dev->data->dev_private;
4555         struct hns3_hw *hw = &hns->hw;
4556         int ret;
4557
4558         if (dev->data->promiscuous)
4559                 return 0;
4560
4561         rte_spinlock_lock(&hw->lock);
4562         ret = hns3_set_promisc_mode(hw, false, true);
4563         rte_spinlock_unlock(&hw->lock);
4564         if (ret)
4565                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4566                          ret);
4567
4568         return ret;
4569 }
4570
4571 static int
4572 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4573 {
4574         struct hns3_adapter *hns = dev->data->dev_private;
4575         struct hns3_hw *hw = &hns->hw;
4576         int ret;
4577
4578         /* If now in promiscuous mode, must remain in all_multicast mode. */
4579         if (dev->data->promiscuous)
4580                 return 0;
4581
4582         rte_spinlock_lock(&hw->lock);
4583         ret = hns3_set_promisc_mode(hw, false, false);
4584         rte_spinlock_unlock(&hw->lock);
4585         if (ret)
4586                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4587                          ret);
4588
4589         return ret;
4590 }
4591
4592 static int
4593 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4594 {
4595         struct hns3_hw *hw = &hns->hw;
4596         bool allmulti = hw->data->all_multicast ? true : false;
4597         int ret;
4598
4599         if (hw->data->promiscuous) {
4600                 ret = hns3_set_promisc_mode(hw, true, true);
4601                 if (ret)
4602                         hns3_err(hw, "failed to restore promiscuous mode, "
4603                                  "ret = %d", ret);
4604                 return ret;
4605         }
4606
4607         ret = hns3_set_promisc_mode(hw, false, allmulti);
4608         if (ret)
4609                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4610                          ret);
4611         return ret;
4612 }
4613
4614 static int
4615 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4616 {
4617         struct hns3_sfp_info_cmd *resp;
4618         struct hns3_cmd_desc desc;
4619         int ret;
4620
4621         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4622         resp = (struct hns3_sfp_info_cmd *)desc.data;
4623         resp->query_type = HNS3_ACTIVE_QUERY;
4624
4625         ret = hns3_cmd_send(hw, &desc, 1);
4626         if (ret == -EOPNOTSUPP) {
4627                 hns3_warn(hw, "firmware does not support get SFP info,"
4628                           " ret = %d.", ret);
4629                 return ret;
4630         } else if (ret) {
4631                 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4632                 return ret;
4633         }
4634
4635         /*
4636          * In some case, the speed of MAC obtained from firmware may be 0, it
4637          * shouldn't be set to mac->speed.
4638          */
4639         if (!rte_le_to_cpu_32(resp->sfp_speed))
4640                 return 0;
4641
4642         mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4643         /*
4644          * if resp->supported_speed is 0, it means it's an old version
4645          * firmware, do not update these params.
4646          */
4647         if (resp->supported_speed) {
4648                 mac_info->query_type = HNS3_ACTIVE_QUERY;
4649                 mac_info->supported_speed =
4650                                         rte_le_to_cpu_32(resp->supported_speed);
4651                 mac_info->support_autoneg = resp->autoneg_ability;
4652                 mac_info->link_autoneg = (resp->autoneg == 0) ? RTE_ETH_LINK_FIXED
4653                                         : RTE_ETH_LINK_AUTONEG;
4654         } else {
4655                 mac_info->query_type = HNS3_DEFAULT_QUERY;
4656         }
4657
4658         return 0;
4659 }
4660
4661 static uint8_t
4662 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4663 {
4664         if (!(speed == RTE_ETH_SPEED_NUM_10M || speed == RTE_ETH_SPEED_NUM_100M))
4665                 duplex = RTE_ETH_LINK_FULL_DUPLEX;
4666
4667         return duplex;
4668 }
4669
4670 static int
4671 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4672 {
4673         struct hns3_mac *mac = &hw->mac;
4674         int ret;
4675
4676         duplex = hns3_check_speed_dup(duplex, speed);
4677         if (mac->link_speed == speed && mac->link_duplex == duplex)
4678                 return 0;
4679
4680         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4681         if (ret)
4682                 return ret;
4683
4684         ret = hns3_port_shaper_update(hw, speed);
4685         if (ret)
4686                 return ret;
4687
4688         mac->link_speed = speed;
4689         mac->link_duplex = duplex;
4690
4691         return 0;
4692 }
4693
4694 static int
4695 hns3_update_fiber_link_info(struct hns3_hw *hw)
4696 {
4697         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4698         struct hns3_mac *mac = &hw->mac;
4699         struct hns3_mac mac_info;
4700         int ret;
4701
4702         /* If firmware do not support get SFP/qSFP speed, return directly */
4703         if (!pf->support_sfp_query)
4704                 return 0;
4705
4706         memset(&mac_info, 0, sizeof(struct hns3_mac));
4707         ret = hns3_get_sfp_info(hw, &mac_info);
4708         if (ret == -EOPNOTSUPP) {
4709                 pf->support_sfp_query = false;
4710                 return ret;
4711         } else if (ret)
4712                 return ret;
4713
4714         /* Do nothing if no SFP */
4715         if (mac_info.link_speed == RTE_ETH_SPEED_NUM_NONE)
4716                 return 0;
4717
4718         /*
4719          * If query_type is HNS3_ACTIVE_QUERY, it is no need
4720          * to reconfigure the speed of MAC. Otherwise, it indicates
4721          * that the current firmware only supports to obtain the
4722          * speed of the SFP, and the speed of MAC needs to reconfigure.
4723          */
4724         mac->query_type = mac_info.query_type;
4725         if (mac->query_type == HNS3_ACTIVE_QUERY) {
4726                 if (mac_info.link_speed != mac->link_speed) {
4727                         ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4728                         if (ret)
4729                                 return ret;
4730                 }
4731
4732                 mac->link_speed = mac_info.link_speed;
4733                 mac->supported_speed = mac_info.supported_speed;
4734                 mac->support_autoneg = mac_info.support_autoneg;
4735                 mac->link_autoneg = mac_info.link_autoneg;
4736
4737                 return 0;
4738         }
4739
4740         /* Config full duplex for SFP */
4741         return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4742                                       RTE_ETH_LINK_FULL_DUPLEX);
4743 }
4744
4745 static void
4746 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4747 {
4748 #define HNS3_PHY_SUPPORTED_SPEED_MASK   0x2f
4749
4750         struct hns3_phy_params_bd0_cmd *req;
4751         uint32_t supported;
4752
4753         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4754         mac->link_speed = rte_le_to_cpu_32(req->speed);
4755         mac->link_duplex = hns3_get_bit(req->duplex,
4756                                            HNS3_PHY_DUPLEX_CFG_B);
4757         mac->link_autoneg = hns3_get_bit(req->autoneg,
4758                                            HNS3_PHY_AUTONEG_CFG_B);
4759         mac->advertising = rte_le_to_cpu_32(req->advertising);
4760         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4761         supported = rte_le_to_cpu_32(req->supported);
4762         mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4763         mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4764 }
4765
4766 static int
4767 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4768 {
4769         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4770         uint16_t i;
4771         int ret;
4772
4773         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4774                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4775                                           true);
4776                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4777         }
4778         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4779
4780         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4781         if (ret) {
4782                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4783                 return ret;
4784         }
4785
4786         hns3_parse_copper_phy_params(desc, mac);
4787
4788         return 0;
4789 }
4790
4791 static int
4792 hns3_update_copper_link_info(struct hns3_hw *hw)
4793 {
4794         struct hns3_mac *mac = &hw->mac;
4795         struct hns3_mac mac_info;
4796         int ret;
4797
4798         memset(&mac_info, 0, sizeof(struct hns3_mac));
4799         ret = hns3_get_copper_phy_params(hw, &mac_info);
4800         if (ret)
4801                 return ret;
4802
4803         if (mac_info.link_speed != mac->link_speed) {
4804                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4805                 if (ret)
4806                         return ret;
4807         }
4808
4809         mac->link_speed = mac_info.link_speed;
4810         mac->link_duplex = mac_info.link_duplex;
4811         mac->link_autoneg = mac_info.link_autoneg;
4812         mac->supported_speed = mac_info.supported_speed;
4813         mac->advertising = mac_info.advertising;
4814         mac->lp_advertising = mac_info.lp_advertising;
4815         mac->support_autoneg = mac_info.support_autoneg;
4816
4817         return 0;
4818 }
4819
4820 static int
4821 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4822 {
4823         struct hns3_adapter *hns = eth_dev->data->dev_private;
4824         struct hns3_hw *hw = &hns->hw;
4825         int ret = 0;
4826
4827         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4828                 ret = hns3_update_copper_link_info(hw);
4829         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4830                 ret = hns3_update_fiber_link_info(hw);
4831
4832         return ret;
4833 }
4834
4835 static int
4836 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4837 {
4838         struct hns3_config_mac_mode_cmd *req;
4839         struct hns3_cmd_desc desc;
4840         uint32_t loop_en = 0;
4841         uint8_t val = 0;
4842         int ret;
4843
4844         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4845
4846         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4847         if (enable)
4848                 val = 1;
4849         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4850         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4851         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4852         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4853         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4854         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4855         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4856         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4857         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4858         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4859
4860         /*
4861          * If RTE_ETH_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4862          * when receiving frames. Otherwise, CRC will be stripped.
4863          */
4864         if (hw->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
4865                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4866         else
4867                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4868         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4869         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4870         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4871         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4872
4873         ret = hns3_cmd_send(hw, &desc, 1);
4874         if (ret)
4875                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4876
4877         return ret;
4878 }
4879
4880 static int
4881 hns3_get_mac_link_status(struct hns3_hw *hw)
4882 {
4883         struct hns3_link_status_cmd *req;
4884         struct hns3_cmd_desc desc;
4885         int link_status;
4886         int ret;
4887
4888         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4889         ret = hns3_cmd_send(hw, &desc, 1);
4890         if (ret) {
4891                 hns3_err(hw, "get link status cmd failed %d", ret);
4892                 return RTE_ETH_LINK_DOWN;
4893         }
4894
4895         req = (struct hns3_link_status_cmd *)desc.data;
4896         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4897
4898         return !!link_status;
4899 }
4900
4901 static bool
4902 hns3_update_link_status(struct hns3_hw *hw)
4903 {
4904         int state;
4905
4906         state = hns3_get_mac_link_status(hw);
4907         if (state != hw->mac.link_status) {
4908                 hw->mac.link_status = state;
4909                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4910                 return true;
4911         }
4912
4913         return false;
4914 }
4915
4916 void
4917 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4918 {
4919         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4920         struct rte_eth_link new_link;
4921         int ret;
4922
4923         if (query)
4924                 hns3_update_port_link_info(dev);
4925
4926         memset(&new_link, 0, sizeof(new_link));
4927         hns3_setup_linkstatus(dev, &new_link);
4928
4929         ret = rte_eth_linkstatus_set(dev, &new_link);
4930         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4931                 hns3_start_report_lse(dev);
4932 }
4933
4934 static void
4935 hns3_service_handler(void *param)
4936 {
4937         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4938         struct hns3_adapter *hns = eth_dev->data->dev_private;
4939         struct hns3_hw *hw = &hns->hw;
4940
4941         if (!hns3_is_reset_pending(hns))
4942                 hns3_update_linkstatus_and_event(hw, true);
4943         else
4944                 hns3_warn(hw, "Cancel the query when reset is pending");
4945
4946         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4947 }
4948
4949 static int
4950 hns3_init_hardware(struct hns3_adapter *hns)
4951 {
4952         struct hns3_hw *hw = &hns->hw;
4953         int ret;
4954
4955         ret = hns3_map_tqp(hw);
4956         if (ret) {
4957                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4958                 return ret;
4959         }
4960
4961         ret = hns3_init_umv_space(hw);
4962         if (ret) {
4963                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4964                 return ret;
4965         }
4966
4967         ret = hns3_mac_init(hw);
4968         if (ret) {
4969                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4970                 goto err_mac_init;
4971         }
4972
4973         ret = hns3_init_mgr_tbl(hw);
4974         if (ret) {
4975                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4976                 goto err_mac_init;
4977         }
4978
4979         ret = hns3_promisc_init(hw);
4980         if (ret) {
4981                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4982                              ret);
4983                 goto err_mac_init;
4984         }
4985
4986         ret = hns3_init_vlan_config(hns);
4987         if (ret) {
4988                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4989                 goto err_mac_init;
4990         }
4991
4992         ret = hns3_dcb_init(hw);
4993         if (ret) {
4994                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4995                 goto err_mac_init;
4996         }
4997
4998         ret = hns3_init_fd_config(hns);
4999         if (ret) {
5000                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
5001                 goto err_mac_init;
5002         }
5003
5004         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
5005         if (ret) {
5006                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
5007                 goto err_mac_init;
5008         }
5009
5010         ret = hns3_config_gro(hw, false);
5011         if (ret) {
5012                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
5013                 goto err_mac_init;
5014         }
5015
5016         /*
5017          * In the initialization clearing the all hardware mapping relationship
5018          * configurations between queues and interrupt vectors is needed, so
5019          * some error caused by the residual configurations, such as the
5020          * unexpected interrupt, can be avoid.
5021          */
5022         ret = hns3_init_ring_with_vector(hw);
5023         if (ret) {
5024                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
5025                 goto err_mac_init;
5026         }
5027
5028         return 0;
5029
5030 err_mac_init:
5031         hns3_uninit_umv_space(hw);
5032         return ret;
5033 }
5034
5035 static int
5036 hns3_clear_hw(struct hns3_hw *hw)
5037 {
5038         struct hns3_cmd_desc desc;
5039         int ret;
5040
5041         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
5042
5043         ret = hns3_cmd_send(hw, &desc, 1);
5044         if (ret && ret != -EOPNOTSUPP)
5045                 return ret;
5046
5047         return 0;
5048 }
5049
5050 static void
5051 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
5052 {
5053         uint32_t val;
5054
5055         /*
5056          * The new firmware support report more hardware error types by
5057          * msix mode. These errors are defined as RAS errors in hardware
5058          * and belong to a different type from the MSI-x errors processed
5059          * by the network driver.
5060          *
5061          * Network driver should open the new error report on initialization.
5062          */
5063         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5064         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5065         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5066 }
5067
5068 static uint32_t
5069 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5070 {
5071         struct hns3_mac *mac = &hw->mac;
5072
5073         switch (mac->link_speed) {
5074         case RTE_ETH_SPEED_NUM_1G:
5075                 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5076         case RTE_ETH_SPEED_NUM_10G:
5077                 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5078         case RTE_ETH_SPEED_NUM_25G:
5079                 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5080         case RTE_ETH_SPEED_NUM_40G:
5081                 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5082         case RTE_ETH_SPEED_NUM_50G:
5083                 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5084         case RTE_ETH_SPEED_NUM_100G:
5085                 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5086         case RTE_ETH_SPEED_NUM_200G:
5087                 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5088         default:
5089                 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5090                 return 0;
5091         }
5092 }
5093
5094 /*
5095  * Validity of supported_speed for firber and copper media type can be
5096  * guaranteed by the following policy:
5097  * Copper:
5098  *       Although the initialization of the phy in the firmware may not be
5099  *       completed, the firmware can guarantees that the supported_speed is
5100  *       an valid value.
5101  * Firber:
5102  *       If the version of firmware supports the acitive query way of the
5103  *       HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5104  *       through it. If unsupported, use the SFP's speed as the value of the
5105  *       supported_speed.
5106  */
5107 static int
5108 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5109 {
5110         struct hns3_adapter *hns = eth_dev->data->dev_private;
5111         struct hns3_hw *hw = &hns->hw;
5112         struct hns3_mac *mac = &hw->mac;
5113         int ret;
5114
5115         ret = hns3_update_link_info(eth_dev);
5116         if (ret)
5117                 return ret;
5118
5119         if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5120                 /*
5121                  * Some firmware does not support the report of supported_speed,
5122                  * and only report the effective speed of SFP. In this case, it
5123                  * is necessary to use the SFP's speed as the supported_speed.
5124                  */
5125                 if (mac->supported_speed == 0)
5126                         mac->supported_speed =
5127                                 hns3_set_firber_default_support_speed(hw);
5128         }
5129
5130         return 0;
5131 }
5132
5133 static void
5134 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
5135 {
5136         struct hns3_mac *mac = &hns->hw.mac;
5137
5138         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
5139                 hns->pf.support_fc_autoneg = true;
5140                 return;
5141         }
5142
5143         /*
5144          * Flow control auto-negotiation requires the cooperation of the driver
5145          * and firmware. Currently, the optical port does not support flow
5146          * control auto-negotiation.
5147          */
5148         hns->pf.support_fc_autoneg = false;
5149 }
5150
5151 static int
5152 hns3_init_pf(struct rte_eth_dev *eth_dev)
5153 {
5154         struct rte_device *dev = eth_dev->device;
5155         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5156         struct hns3_adapter *hns = eth_dev->data->dev_private;
5157         struct hns3_hw *hw = &hns->hw;
5158         int ret;
5159
5160         PMD_INIT_FUNC_TRACE();
5161
5162         /* Get hardware io base address from pcie BAR2 IO space */
5163         hw->io_base = pci_dev->mem_resource[2].addr;
5164
5165         /* Firmware command queue initialize */
5166         ret = hns3_cmd_init_queue(hw);
5167         if (ret) {
5168                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5169                 goto err_cmd_init_queue;
5170         }
5171
5172         hns3_clear_all_event_cause(hw);
5173
5174         /* Firmware command initialize */
5175         ret = hns3_cmd_init(hw);
5176         if (ret) {
5177                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5178                 goto err_cmd_init;
5179         }
5180
5181         hns3_tx_push_init(eth_dev);
5182
5183         /*
5184          * To ensure that the hardware environment is clean during
5185          * initialization, the driver actively clear the hardware environment
5186          * during initialization, including PF and corresponding VFs' vlan, mac,
5187          * flow table configurations, etc.
5188          */
5189         ret = hns3_clear_hw(hw);
5190         if (ret) {
5191                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5192                 goto err_cmd_init;
5193         }
5194
5195         /* Hardware statistics of imissed registers cleared. */
5196         ret = hns3_update_imissed_stats(hw, true);
5197         if (ret) {
5198                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5199                 goto err_cmd_init;
5200         }
5201
5202         hns3_config_all_msix_error(hw, true);
5203
5204         ret = rte_intr_callback_register(pci_dev->intr_handle,
5205                                          hns3_interrupt_handler,
5206                                          eth_dev);
5207         if (ret) {
5208                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5209                 goto err_intr_callback_register;
5210         }
5211
5212         ret = hns3_ptp_init(hw);
5213         if (ret)
5214                 goto err_get_config;
5215
5216         /* Enable interrupt */
5217         rte_intr_enable(pci_dev->intr_handle);
5218         hns3_pf_enable_irq0(hw);
5219
5220         /* Get configuration */
5221         ret = hns3_get_configuration(hw);
5222         if (ret) {
5223                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5224                 goto err_get_config;
5225         }
5226
5227         ret = hns3_tqp_stats_init(hw);
5228         if (ret)
5229                 goto err_get_config;
5230
5231         ret = hns3_init_hardware(hns);
5232         if (ret) {
5233                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5234                 goto err_init_hw;
5235         }
5236
5237         /* Initialize flow director filter list & hash */
5238         ret = hns3_fdir_filter_init(hns);
5239         if (ret) {
5240                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5241                 goto err_fdir;
5242         }
5243
5244         hns3_rss_set_default_args(hw);
5245
5246         ret = hns3_enable_hw_error_intr(hns, true);
5247         if (ret) {
5248                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5249                              ret);
5250                 goto err_enable_intr;
5251         }
5252
5253         ret = hns3_get_port_supported_speed(eth_dev);
5254         if (ret) {
5255                 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5256                              "by device, ret = %d.", ret);
5257                 goto err_supported_speed;
5258         }
5259
5260         hns3_get_fc_autoneg_capability(hns);
5261
5262         hns3_tm_conf_init(eth_dev);
5263
5264         return 0;
5265
5266 err_supported_speed:
5267         (void)hns3_enable_hw_error_intr(hns, false);
5268 err_enable_intr:
5269         hns3_fdir_filter_uninit(hns);
5270 err_fdir:
5271         hns3_uninit_umv_space(hw);
5272 err_init_hw:
5273         hns3_tqp_stats_uninit(hw);
5274 err_get_config:
5275         hns3_pf_disable_irq0(hw);
5276         rte_intr_disable(pci_dev->intr_handle);
5277         hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
5278                              eth_dev);
5279 err_intr_callback_register:
5280 err_cmd_init:
5281         hns3_cmd_uninit(hw);
5282         hns3_cmd_destroy_queue(hw);
5283 err_cmd_init_queue:
5284         hw->io_base = NULL;
5285
5286         return ret;
5287 }
5288
5289 static void
5290 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5291 {
5292         struct hns3_adapter *hns = eth_dev->data->dev_private;
5293         struct rte_device *dev = eth_dev->device;
5294         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5295         struct hns3_hw *hw = &hns->hw;
5296
5297         PMD_INIT_FUNC_TRACE();
5298
5299         hns3_tm_conf_uninit(eth_dev);
5300         hns3_enable_hw_error_intr(hns, false);
5301         hns3_rss_uninit(hns);
5302         (void)hns3_config_gro(hw, false);
5303         hns3_promisc_uninit(hw);
5304         hns3_flow_uninit(eth_dev);
5305         hns3_fdir_filter_uninit(hns);
5306         hns3_uninit_umv_space(hw);
5307         hns3_tqp_stats_uninit(hw);
5308         hns3_config_mac_tnl_int(hw, false);
5309         hns3_pf_disable_irq0(hw);
5310         rte_intr_disable(pci_dev->intr_handle);
5311         hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
5312                              eth_dev);
5313         hns3_config_all_msix_error(hw, false);
5314         hns3_cmd_uninit(hw);
5315         hns3_cmd_destroy_queue(hw);
5316         hw->io_base = NULL;
5317 }
5318
5319 static uint32_t
5320 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
5321 {
5322         uint32_t speed_bit;
5323
5324         switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) {
5325         case RTE_ETH_LINK_SPEED_10M:
5326                 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
5327                 break;
5328         case RTE_ETH_LINK_SPEED_10M_HD:
5329                 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
5330                 break;
5331         case RTE_ETH_LINK_SPEED_100M:
5332                 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
5333                 break;
5334         case RTE_ETH_LINK_SPEED_100M_HD:
5335                 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
5336                 break;
5337         case RTE_ETH_LINK_SPEED_1G:
5338                 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
5339                 break;
5340         default:
5341                 speed_bit = 0;
5342                 break;
5343         }
5344
5345         return speed_bit;
5346 }
5347
5348 static uint32_t
5349 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
5350 {
5351         uint32_t speed_bit;
5352
5353         switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) {
5354         case RTE_ETH_LINK_SPEED_1G:
5355                 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
5356                 break;
5357         case RTE_ETH_LINK_SPEED_10G:
5358                 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
5359                 break;
5360         case RTE_ETH_LINK_SPEED_25G:
5361                 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
5362                 break;
5363         case RTE_ETH_LINK_SPEED_40G:
5364                 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
5365                 break;
5366         case RTE_ETH_LINK_SPEED_50G:
5367                 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
5368                 break;
5369         case RTE_ETH_LINK_SPEED_100G:
5370                 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
5371                 break;
5372         case RTE_ETH_LINK_SPEED_200G:
5373                 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
5374                 break;
5375         default:
5376                 speed_bit = 0;
5377                 break;
5378         }
5379
5380         return speed_bit;
5381 }
5382
5383 static int
5384 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
5385 {
5386         struct hns3_mac *mac = &hw->mac;
5387         uint32_t supported_speed = mac->supported_speed;
5388         uint32_t speed_bit = 0;
5389
5390         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
5391                 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
5392         else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
5393                 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
5394
5395         if (!(speed_bit & supported_speed)) {
5396                 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
5397                          link_speeds);
5398                 return -EINVAL;
5399         }
5400
5401         return 0;
5402 }
5403
5404 static inline uint32_t
5405 hns3_get_link_speed(uint32_t link_speeds)
5406 {
5407         uint32_t speed = RTE_ETH_SPEED_NUM_NONE;
5408
5409         if (link_speeds & RTE_ETH_LINK_SPEED_10M ||
5410             link_speeds & RTE_ETH_LINK_SPEED_10M_HD)
5411                 speed = RTE_ETH_SPEED_NUM_10M;
5412         if (link_speeds & RTE_ETH_LINK_SPEED_100M ||
5413             link_speeds & RTE_ETH_LINK_SPEED_100M_HD)
5414                 speed = RTE_ETH_SPEED_NUM_100M;
5415         if (link_speeds & RTE_ETH_LINK_SPEED_1G)
5416                 speed = RTE_ETH_SPEED_NUM_1G;
5417         if (link_speeds & RTE_ETH_LINK_SPEED_10G)
5418                 speed = RTE_ETH_SPEED_NUM_10G;
5419         if (link_speeds & RTE_ETH_LINK_SPEED_25G)
5420                 speed = RTE_ETH_SPEED_NUM_25G;
5421         if (link_speeds & RTE_ETH_LINK_SPEED_40G)
5422                 speed = RTE_ETH_SPEED_NUM_40G;
5423         if (link_speeds & RTE_ETH_LINK_SPEED_50G)
5424                 speed = RTE_ETH_SPEED_NUM_50G;
5425         if (link_speeds & RTE_ETH_LINK_SPEED_100G)
5426                 speed = RTE_ETH_SPEED_NUM_100G;
5427         if (link_speeds & RTE_ETH_LINK_SPEED_200G)
5428                 speed = RTE_ETH_SPEED_NUM_200G;
5429
5430         return speed;
5431 }
5432
5433 static uint8_t
5434 hns3_get_link_duplex(uint32_t link_speeds)
5435 {
5436         if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) ||
5437             (link_speeds & RTE_ETH_LINK_SPEED_100M_HD))
5438                 return RTE_ETH_LINK_HALF_DUPLEX;
5439         else
5440                 return RTE_ETH_LINK_FULL_DUPLEX;
5441 }
5442
5443 static int
5444 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5445                                 struct hns3_set_link_speed_cfg *cfg)
5446 {
5447         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5448         struct hns3_phy_params_bd0_cmd *req;
5449         uint16_t i;
5450
5451         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5452                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5453                                           false);
5454                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5455         }
5456         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5457         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5458         req->autoneg = cfg->autoneg;
5459
5460         /*
5461          * The full speed capability is used to negotiate when
5462          * auto-negotiation is enabled.
5463          */
5464         if (cfg->autoneg) {
5465                 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5466                                     HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5467                                     HNS3_PHY_LINK_SPEED_100M_BIT |
5468                                     HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5469                                     HNS3_PHY_LINK_SPEED_1000M_BIT;
5470         } else {
5471                 req->speed = cfg->speed;
5472                 req->duplex = cfg->duplex;
5473         }
5474
5475         return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5476 }
5477
5478 static int
5479 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5480 {
5481         struct hns3_config_auto_neg_cmd *req;
5482         struct hns3_cmd_desc desc;
5483         uint32_t flag = 0;
5484         int ret;
5485
5486         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5487
5488         req = (struct hns3_config_auto_neg_cmd *)desc.data;
5489         if (enable)
5490                 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5491         req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5492
5493         ret = hns3_cmd_send(hw, &desc, 1);
5494         if (ret)
5495                 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5496
5497         return ret;
5498 }
5499
5500 static int
5501 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5502                                struct hns3_set_link_speed_cfg *cfg)
5503 {
5504         int ret;
5505
5506         if (hw->mac.support_autoneg) {
5507                 ret = hns3_set_autoneg(hw, cfg->autoneg);
5508                 if (ret) {
5509                         hns3_err(hw, "failed to configure auto-negotiation.");
5510                         return ret;
5511                 }
5512
5513                 /*
5514                  * To enable auto-negotiation, we only need to open the switch
5515                  * of auto-negotiation, then firmware sets all speed
5516                  * capabilities.
5517                  */
5518                 if (cfg->autoneg)
5519                         return 0;
5520         }
5521
5522         /*
5523          * Some hardware doesn't support auto-negotiation, but users may not
5524          * configure link_speeds (default 0), which means auto-negotiation.
5525          * In this case, a warning message need to be printed, instead of
5526          * an error.
5527          */
5528         if (cfg->autoneg) {
5529                 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
5530                 return 0;
5531         }
5532
5533         return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
5534 }
5535
5536 static int
5537 hns3_set_port_link_speed(struct hns3_hw *hw,
5538                          struct hns3_set_link_speed_cfg *cfg)
5539 {
5540         int ret;
5541
5542         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5543 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5544                 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5545                 if (pf->is_tmp_phy)
5546                         return 0;
5547 #endif
5548
5549                 ret = hns3_set_copper_port_link_speed(hw, cfg);
5550                 if (ret) {
5551                         hns3_err(hw, "failed to set copper port link speed,"
5552                                  "ret = %d.", ret);
5553                         return ret;
5554                 }
5555         } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5556                 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5557                 if (ret) {
5558                         hns3_err(hw, "failed to set fiber port link speed,"
5559                                  "ret = %d.", ret);
5560                         return ret;
5561                 }
5562         }
5563
5564         return 0;
5565 }
5566
5567 static int
5568 hns3_apply_link_speed(struct hns3_hw *hw)
5569 {
5570         struct rte_eth_conf *conf = &hw->data->dev_conf;
5571         struct hns3_set_link_speed_cfg cfg;
5572
5573         memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5574         cfg.autoneg = (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) ?
5575                         RTE_ETH_LINK_AUTONEG : RTE_ETH_LINK_FIXED;
5576         if (cfg.autoneg != RTE_ETH_LINK_AUTONEG) {
5577                 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5578                 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5579         }
5580
5581         return hns3_set_port_link_speed(hw, &cfg);
5582 }
5583
5584 static int
5585 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5586 {
5587         struct hns3_hw *hw = &hns->hw;
5588         bool link_en;
5589         int ret;
5590
5591         ret = hns3_update_queue_map_configure(hns);
5592         if (ret) {
5593                 hns3_err(hw, "failed to update queue mapping configuration, ret = %d",
5594                          ret);
5595                 return ret;
5596         }
5597
5598         /* Note: hns3_tm_conf_update must be called after configuring DCB. */
5599         ret = hns3_tm_conf_update(hw);
5600         if (ret) {
5601                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5602                 return ret;
5603         }
5604
5605         hns3_enable_rxd_adv_layout(hw);
5606
5607         ret = hns3_init_queues(hns, reset_queue);
5608         if (ret) {
5609                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5610                 return ret;
5611         }
5612
5613         link_en = hw->set_link_down ? false : true;
5614         ret = hns3_cfg_mac_mode(hw, link_en);
5615         if (ret) {
5616                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5617                 goto err_config_mac_mode;
5618         }
5619
5620         ret = hns3_apply_link_speed(hw);
5621         if (ret)
5622                 goto err_set_link_speed;
5623
5624         return 0;
5625
5626 err_set_link_speed:
5627         (void)hns3_cfg_mac_mode(hw, false);
5628
5629 err_config_mac_mode:
5630         hns3_dev_release_mbufs(hns);
5631         /*
5632          * Here is exception handling, hns3_reset_all_tqps will have the
5633          * corresponding error message if it is handled incorrectly, so it is
5634          * not necessary to check hns3_reset_all_tqps return value, here keep
5635          * ret as the error code causing the exception.
5636          */
5637         (void)hns3_reset_all_tqps(hns);
5638         return ret;
5639 }
5640
5641 static int
5642 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5643 {
5644         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5645         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5646         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5647         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5648         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5649         uint32_t intr_vector;
5650         uint16_t q_id;
5651         int ret;
5652
5653         /*
5654          * hns3 needs a separate interrupt to be used as event interrupt which
5655          * could not be shared with task queue pair, so KERNEL drivers need
5656          * support multiple interrupt vectors.
5657          */
5658         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5659             !rte_intr_cap_multiple(intr_handle))
5660                 return 0;
5661
5662         rte_intr_disable(intr_handle);
5663         intr_vector = hw->used_rx_queues;
5664         /* creates event fd for each intr vector when MSIX is used */
5665         if (rte_intr_efd_enable(intr_handle, intr_vector))
5666                 return -EINVAL;
5667
5668         /* Allocate vector list */
5669         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
5670                                     hw->used_rx_queues)) {
5671                 hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5672                          hw->used_rx_queues);
5673                 ret = -ENOMEM;
5674                 goto alloc_intr_vec_error;
5675         }
5676
5677         if (rte_intr_allow_others(intr_handle)) {
5678                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5679                 base = RTE_INTR_VEC_RXTX_OFFSET;
5680         }
5681
5682         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5683                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5684                                                  HNS3_RING_TYPE_RX, q_id);
5685                 if (ret)
5686                         goto bind_vector_error;
5687
5688                 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
5689                         goto bind_vector_error;
5690                 /*
5691                  * If there are not enough efds (e.g. not enough interrupt),
5692                  * remaining queues will be bond to the last interrupt.
5693                  */
5694                 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
5695                         vec++;
5696         }
5697         rte_intr_enable(intr_handle);
5698         return 0;
5699
5700 bind_vector_error:
5701         rte_intr_vec_list_free(intr_handle);
5702 alloc_intr_vec_error:
5703         rte_intr_efd_disable(intr_handle);
5704         return ret;
5705 }
5706
5707 static int
5708 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5709 {
5710         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5711         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5712         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5713         uint16_t q_id;
5714         int ret;
5715
5716         if (dev->data->dev_conf.intr_conf.rxq == 0)
5717                 return 0;
5718
5719         if (rte_intr_dp_is_en(intr_handle)) {
5720                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5721                         ret = hns3_bind_ring_with_vector(hw,
5722                                 rte_intr_vec_list_index_get(intr_handle,
5723                                                                    q_id),
5724                                 true, HNS3_RING_TYPE_RX, q_id);
5725                         if (ret)
5726                                 return ret;
5727                 }
5728         }
5729
5730         return 0;
5731 }
5732
5733 static void
5734 hns3_restore_filter(struct rte_eth_dev *dev)
5735 {
5736         hns3_restore_rss_filter(dev);
5737 }
5738
5739 static int
5740 hns3_dev_start(struct rte_eth_dev *dev)
5741 {
5742         struct hns3_adapter *hns = dev->data->dev_private;
5743         struct hns3_hw *hw = &hns->hw;
5744         bool old_state = hw->set_link_down;
5745         int ret;
5746
5747         PMD_INIT_FUNC_TRACE();
5748         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5749                 return -EBUSY;
5750
5751         rte_spinlock_lock(&hw->lock);
5752         hw->adapter_state = HNS3_NIC_STARTING;
5753
5754         /*
5755          * If the dev_set_link_down() API has been called, the "set_link_down"
5756          * flag can be cleared by dev_start() API. In addition, the flag should
5757          * also be cleared before calling hns3_do_start() so that MAC can be
5758          * enabled in dev_start stage.
5759          */
5760         hw->set_link_down = false;
5761         ret = hns3_do_start(hns, true);
5762         if (ret)
5763                 goto do_start_fail;
5764
5765         ret = hns3_map_rx_interrupt(dev);
5766         if (ret)
5767                 goto map_rx_inter_err;
5768
5769         /*
5770          * There are three register used to control the status of a TQP
5771          * (contains a pair of Tx queue and Rx queue) in the new version network
5772          * engine. One is used to control the enabling of Tx queue, the other is
5773          * used to control the enabling of Rx queue, and the last is the master
5774          * switch used to control the enabling of the tqp. The Tx register and
5775          * TQP register must be enabled at the same time to enable a Tx queue.
5776          * The same applies to the Rx queue. For the older network engine, this
5777          * function only refresh the enabled flag, and it is used to update the
5778          * status of queue in the dpdk framework.
5779          */
5780         ret = hns3_start_all_txqs(dev);
5781         if (ret)
5782                 goto map_rx_inter_err;
5783
5784         ret = hns3_start_all_rxqs(dev);
5785         if (ret)
5786                 goto start_all_rxqs_fail;
5787
5788         hw->adapter_state = HNS3_NIC_STARTED;
5789         rte_spinlock_unlock(&hw->lock);
5790
5791         hns3_rx_scattered_calc(dev);
5792         hns3_set_rxtx_function(dev);
5793         hns3_mp_req_start_rxtx(dev);
5794
5795         hns3_restore_filter(dev);
5796
5797         /* Enable interrupt of all rx queues before enabling queues */
5798         hns3_dev_all_rx_queue_intr_enable(hw, true);
5799
5800         /*
5801          * After finished the initialization, enable tqps to receive/transmit
5802          * packets and refresh all queue status.
5803          */
5804         hns3_start_tqps(hw);
5805
5806         hns3_tm_dev_start_proc(hw);
5807
5808         if (dev->data->dev_conf.intr_conf.lsc != 0)
5809                 hns3_dev_link_update(dev, 0);
5810         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5811
5812         hns3_info(hw, "hns3 dev start successful!");
5813
5814         return 0;
5815
5816 start_all_rxqs_fail:
5817         hns3_stop_all_txqs(dev);
5818 map_rx_inter_err:
5819         (void)hns3_do_stop(hns);
5820 do_start_fail:
5821         hw->set_link_down = old_state;
5822         hw->adapter_state = HNS3_NIC_CONFIGURED;
5823         rte_spinlock_unlock(&hw->lock);
5824
5825         return ret;
5826 }
5827
5828 static int
5829 hns3_do_stop(struct hns3_adapter *hns)
5830 {
5831         struct hns3_hw *hw = &hns->hw;
5832         int ret;
5833
5834         /*
5835          * The "hns3_do_stop" function will also be called by .stop_service to
5836          * prepare reset. At the time of global or IMP reset, the command cannot
5837          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5838          * accessed during the reset process. So the mbuf can not be released
5839          * during reset and is required to be released after the reset is
5840          * completed.
5841          */
5842         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5843                 hns3_dev_release_mbufs(hns);
5844
5845         ret = hns3_cfg_mac_mode(hw, false);
5846         if (ret)
5847                 return ret;
5848         hw->mac.link_status = RTE_ETH_LINK_DOWN;
5849
5850         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5851                 hns3_configure_all_mac_addr(hns, true);
5852                 ret = hns3_reset_all_tqps(hns);
5853                 if (ret) {
5854                         hns3_err(hw, "failed to reset all queues ret = %d.",
5855                                  ret);
5856                         return ret;
5857                 }
5858         }
5859
5860         return 0;
5861 }
5862
5863 static void
5864 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5865 {
5866         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5867         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5868         struct hns3_adapter *hns = dev->data->dev_private;
5869         struct hns3_hw *hw = &hns->hw;
5870         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5871         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5872         uint16_t q_id;
5873
5874         if (dev->data->dev_conf.intr_conf.rxq == 0)
5875                 return;
5876
5877         /* unmap the ring with vector */
5878         if (rte_intr_allow_others(intr_handle)) {
5879                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5880                 base = RTE_INTR_VEC_RXTX_OFFSET;
5881         }
5882         if (rte_intr_dp_is_en(intr_handle)) {
5883                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5884                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5885                                                          HNS3_RING_TYPE_RX,
5886                                                          q_id);
5887                         if (vec < base + rte_intr_nb_efd_get(intr_handle)
5888                                                                         - 1)
5889                                 vec++;
5890                 }
5891         }
5892         /* Clean datapath event and queue/vec mapping */
5893         rte_intr_efd_disable(intr_handle);
5894         rte_intr_vec_list_free(intr_handle);
5895 }
5896
5897 static int
5898 hns3_dev_stop(struct rte_eth_dev *dev)
5899 {
5900         struct hns3_adapter *hns = dev->data->dev_private;
5901         struct hns3_hw *hw = &hns->hw;
5902
5903         PMD_INIT_FUNC_TRACE();
5904         dev->data->dev_started = 0;
5905
5906         hw->adapter_state = HNS3_NIC_STOPPING;
5907         hns3_set_rxtx_function(dev);
5908         rte_wmb();
5909         /* Disable datapath on secondary process. */
5910         hns3_mp_req_stop_rxtx(dev);
5911         /* Prevent crashes when queues are still in use. */
5912         rte_delay_ms(hw->cfg_max_queues);
5913
5914         rte_spinlock_lock(&hw->lock);
5915         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5916                 hns3_tm_dev_stop_proc(hw);
5917                 hns3_config_mac_tnl_int(hw, false);
5918                 hns3_stop_tqps(hw);
5919                 hns3_do_stop(hns);
5920                 hns3_unmap_rx_interrupt(dev);
5921                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5922         }
5923         hns3_rx_scattered_reset(dev);
5924         rte_eal_alarm_cancel(hns3_service_handler, dev);
5925         hns3_stop_report_lse(dev);
5926         rte_spinlock_unlock(&hw->lock);
5927
5928         return 0;
5929 }
5930
5931 static int
5932 hns3_dev_close(struct rte_eth_dev *eth_dev)
5933 {
5934         struct hns3_adapter *hns = eth_dev->data->dev_private;
5935         struct hns3_hw *hw = &hns->hw;
5936         int ret = 0;
5937
5938         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5939                 return 0;
5940
5941         if (hw->adapter_state == HNS3_NIC_STARTED)
5942                 ret = hns3_dev_stop(eth_dev);
5943
5944         hw->adapter_state = HNS3_NIC_CLOSING;
5945         hns3_reset_abort(hns);
5946         hw->adapter_state = HNS3_NIC_CLOSED;
5947
5948         hns3_configure_all_mc_mac_addr(hns, true);
5949         hns3_remove_all_vlan_table(hns);
5950         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5951         hns3_uninit_pf(eth_dev);
5952         hns3_free_all_queues(eth_dev);
5953         rte_free(hw->reset.wait_data);
5954         hns3_mp_uninit_primary();
5955         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5956
5957         return ret;
5958 }
5959
5960 static void
5961 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5962                                    bool *tx_pause)
5963 {
5964         struct hns3_mac *mac = &hw->mac;
5965         uint32_t advertising = mac->advertising;
5966         uint32_t lp_advertising = mac->lp_advertising;
5967         *rx_pause = false;
5968         *tx_pause = false;
5969
5970         if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5971                 *rx_pause = true;
5972                 *tx_pause = true;
5973         } else if (advertising & lp_advertising &
5974                    HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5975                 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5976                         *rx_pause = true;
5977                 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5978                         *tx_pause = true;
5979         }
5980 }
5981
5982 static enum hns3_fc_mode
5983 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5984 {
5985         enum hns3_fc_mode current_mode;
5986         bool rx_pause = false;
5987         bool tx_pause = false;
5988
5989         switch (hw->mac.media_type) {
5990         case HNS3_MEDIA_TYPE_COPPER:
5991                 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5992                 break;
5993
5994         /*
5995          * Flow control auto-negotiation is not supported for fiber and
5996          * backpalne media type.
5997          */
5998         case HNS3_MEDIA_TYPE_FIBER:
5999         case HNS3_MEDIA_TYPE_BACKPLANE:
6000                 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
6001                 current_mode = hw->requested_fc_mode;
6002                 goto out;
6003         default:
6004                 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
6005                          hw->mac.media_type);
6006                 current_mode = HNS3_FC_NONE;
6007                 goto out;
6008         }
6009
6010         if (rx_pause && tx_pause)
6011                 current_mode = HNS3_FC_FULL;
6012         else if (rx_pause)
6013                 current_mode = HNS3_FC_RX_PAUSE;
6014         else if (tx_pause)
6015                 current_mode = HNS3_FC_TX_PAUSE;
6016         else
6017                 current_mode = HNS3_FC_NONE;
6018
6019 out:
6020         return current_mode;
6021 }
6022
6023 static enum hns3_fc_mode
6024 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
6025 {
6026         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6027         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6028         struct hns3_mac *mac = &hw->mac;
6029
6030         /*
6031          * When the flow control mode is obtained, the device may not complete
6032          * auto-negotiation. It is necessary to wait for link establishment.
6033          */
6034         (void)hns3_dev_link_update(dev, 1);
6035
6036         /*
6037          * If the link auto-negotiation of the nic is disabled, or the flow
6038          * control auto-negotiation is not supported, the forced flow control
6039          * mode is used.
6040          */
6041         if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
6042                 return hw->requested_fc_mode;
6043
6044         return hns3_get_autoneg_fc_mode(hw);
6045 }
6046
6047 static int
6048 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6049 {
6050         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6051         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6052         enum hns3_fc_mode current_mode;
6053
6054         current_mode = hns3_get_current_fc_mode(dev);
6055         switch (current_mode) {
6056         case HNS3_FC_FULL:
6057                 fc_conf->mode = RTE_ETH_FC_FULL;
6058                 break;
6059         case HNS3_FC_TX_PAUSE:
6060                 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
6061                 break;
6062         case HNS3_FC_RX_PAUSE:
6063                 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
6064                 break;
6065         case HNS3_FC_NONE:
6066         default:
6067                 fc_conf->mode = RTE_ETH_FC_NONE;
6068                 break;
6069         }
6070
6071         fc_conf->pause_time = pf->pause_time;
6072         fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
6073
6074         return 0;
6075 }
6076
6077 static int
6078 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
6079 {
6080         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
6081
6082         if (!pf->support_fc_autoneg) {
6083                 if (autoneg != 0) {
6084                         hns3_err(hw, "unsupported fc auto-negotiation setting.");
6085                         return -EOPNOTSUPP;
6086                 }
6087
6088                 /*
6089                  * Flow control auto-negotiation of the NIC is not supported,
6090                  * but other auto-negotiation features may be supported.
6091                  */
6092                 if (autoneg != hw->mac.link_autoneg) {
6093                         hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
6094                         return -EOPNOTSUPP;
6095                 }
6096
6097                 return 0;
6098         }
6099
6100         /*
6101          * If flow control auto-negotiation of the NIC is supported, all
6102          * auto-negotiation features are supported.
6103          */
6104         if (autoneg != hw->mac.link_autoneg) {
6105                 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
6106                 return -EOPNOTSUPP;
6107         }
6108
6109         return 0;
6110 }
6111
6112 static int
6113 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6114 {
6115         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6116         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6117         int ret;
6118
6119         if (fc_conf->high_water || fc_conf->low_water ||
6120             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
6121                 hns3_err(hw, "Unsupported flow control settings specified, "
6122                          "high_water(%u), low_water(%u), send_xon(%u) and "
6123                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6124                          fc_conf->high_water, fc_conf->low_water,
6125                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
6126                 return -EINVAL;
6127         }
6128
6129         ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
6130         if (ret)
6131                 return ret;
6132
6133         if (!fc_conf->pause_time) {
6134                 hns3_err(hw, "Invalid pause time %u setting.",
6135                          fc_conf->pause_time);
6136                 return -EINVAL;
6137         }
6138
6139         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6140             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
6141                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
6142                          "current_fc_status = %d", hw->current_fc_status);
6143                 return -EOPNOTSUPP;
6144         }
6145
6146         if (hw->num_tc > 1 && !pf->support_multi_tc_pause) {
6147                 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
6148                 return -EOPNOTSUPP;
6149         }
6150
6151         rte_spinlock_lock(&hw->lock);
6152         ret = hns3_fc_enable(dev, fc_conf);
6153         rte_spinlock_unlock(&hw->lock);
6154
6155         return ret;
6156 }
6157
6158 static int
6159 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
6160                             struct rte_eth_pfc_conf *pfc_conf)
6161 {
6162         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6163         int ret;
6164
6165         if (!hns3_dev_get_support(hw, DCB)) {
6166                 hns3_err(hw, "This port does not support dcb configurations.");
6167                 return -EOPNOTSUPP;
6168         }
6169
6170         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
6171             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
6172                 hns3_err(hw, "Unsupported flow control settings specified, "
6173                          "high_water(%u), low_water(%u), send_xon(%u) and "
6174                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6175                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
6176                          pfc_conf->fc.send_xon,
6177                          pfc_conf->fc.mac_ctrl_frame_fwd);
6178                 return -EINVAL;
6179         }
6180         if (pfc_conf->fc.autoneg) {
6181                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
6182                 return -EINVAL;
6183         }
6184         if (pfc_conf->fc.pause_time == 0) {
6185                 hns3_err(hw, "Invalid pause time %u setting.",
6186                          pfc_conf->fc.pause_time);
6187                 return -EINVAL;
6188         }
6189
6190         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6191             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
6192                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
6193                              "current_fc_status = %d", hw->current_fc_status);
6194                 return -EOPNOTSUPP;
6195         }
6196
6197         rte_spinlock_lock(&hw->lock);
6198         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
6199         rte_spinlock_unlock(&hw->lock);
6200
6201         return ret;
6202 }
6203
6204 static int
6205 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
6206 {
6207         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6208         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6209         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
6210         int i;
6211
6212         rte_spinlock_lock(&hw->lock);
6213         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG)
6214                 dcb_info->nb_tcs = pf->local_max_tc;
6215         else
6216                 dcb_info->nb_tcs = 1;
6217
6218         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
6219                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
6220         for (i = 0; i < dcb_info->nb_tcs; i++)
6221                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
6222
6223         for (i = 0; i < hw->num_tc; i++) {
6224                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
6225                 dcb_info->tc_queue.tc_txq[0][i].base =
6226                                                 hw->tc_queue[i].tqp_offset;
6227                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
6228                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
6229                                                 hw->tc_queue[i].tqp_count;
6230         }
6231         rte_spinlock_unlock(&hw->lock);
6232
6233         return 0;
6234 }
6235
6236 static int
6237 hns3_reinit_dev(struct hns3_adapter *hns)
6238 {
6239         struct hns3_hw *hw = &hns->hw;
6240         int ret;
6241
6242         ret = hns3_cmd_init(hw);
6243         if (ret) {
6244                 hns3_err(hw, "Failed to init cmd: %d", ret);
6245                 return ret;
6246         }
6247
6248         ret = hns3_reset_all_tqps(hns);
6249         if (ret) {
6250                 hns3_err(hw, "Failed to reset all queues: %d", ret);
6251                 return ret;
6252         }
6253
6254         ret = hns3_init_hardware(hns);
6255         if (ret) {
6256                 hns3_err(hw, "Failed to init hardware: %d", ret);
6257                 return ret;
6258         }
6259
6260         ret = hns3_enable_hw_error_intr(hns, true);
6261         if (ret) {
6262                 hns3_err(hw, "fail to enable hw error interrupts: %d",
6263                              ret);
6264                 return ret;
6265         }
6266         hns3_info(hw, "Reset done, driver initialization finished.");
6267
6268         return 0;
6269 }
6270
6271 static bool
6272 is_pf_reset_done(struct hns3_hw *hw)
6273 {
6274         uint32_t val, reg, reg_bit;
6275
6276         switch (hw->reset.level) {
6277         case HNS3_IMP_RESET:
6278                 reg = HNS3_GLOBAL_RESET_REG;
6279                 reg_bit = HNS3_IMP_RESET_BIT;
6280                 break;
6281         case HNS3_GLOBAL_RESET:
6282                 reg = HNS3_GLOBAL_RESET_REG;
6283                 reg_bit = HNS3_GLOBAL_RESET_BIT;
6284                 break;
6285         case HNS3_FUNC_RESET:
6286                 reg = HNS3_FUN_RST_ING;
6287                 reg_bit = HNS3_FUN_RST_ING_B;
6288                 break;
6289         case HNS3_FLR_RESET:
6290         default:
6291                 hns3_err(hw, "Wait for unsupported reset level: %d",
6292                          hw->reset.level);
6293                 return true;
6294         }
6295         val = hns3_read_dev(hw, reg);
6296         if (hns3_get_bit(val, reg_bit))
6297                 return false;
6298         else
6299                 return true;
6300 }
6301
6302 bool
6303 hns3_is_reset_pending(struct hns3_adapter *hns)
6304 {
6305         struct hns3_hw *hw = &hns->hw;
6306         enum hns3_reset_level reset;
6307
6308         hns3_check_event_cause(hns, NULL);
6309         reset = hns3_get_reset_level(hns, &hw->reset.pending);
6310         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6311             hw->reset.level < reset) {
6312                 hns3_warn(hw, "High level reset %d is pending", reset);
6313                 return true;
6314         }
6315         reset = hns3_get_reset_level(hns, &hw->reset.request);
6316         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6317             hw->reset.level < reset) {
6318                 hns3_warn(hw, "High level reset %d is request", reset);
6319                 return true;
6320         }
6321         return false;
6322 }
6323
6324 static int
6325 hns3_wait_hardware_ready(struct hns3_adapter *hns)
6326 {
6327         struct hns3_hw *hw = &hns->hw;
6328         struct hns3_wait_data *wait_data = hw->reset.wait_data;
6329         struct timeval tv;
6330
6331         if (wait_data->result == HNS3_WAIT_SUCCESS)
6332                 return 0;
6333         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
6334                 hns3_clock_gettime(&tv);
6335                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
6336                           tv.tv_sec, tv.tv_usec);
6337                 return -ETIME;
6338         } else if (wait_data->result == HNS3_WAIT_REQUEST)
6339                 return -EAGAIN;
6340
6341         wait_data->hns = hns;
6342         wait_data->check_completion = is_pf_reset_done;
6343         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
6344                                 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms();
6345         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
6346         wait_data->count = HNS3_RESET_WAIT_CNT;
6347         wait_data->result = HNS3_WAIT_REQUEST;
6348         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
6349         return -EAGAIN;
6350 }
6351
6352 static int
6353 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
6354 {
6355         struct hns3_cmd_desc desc;
6356         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6357
6358         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6359         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6360         req->fun_reset_vfid = func_id;
6361
6362         return hns3_cmd_send(hw, &desc, 1);
6363 }
6364
6365 static int
6366 hns3_imp_reset_cmd(struct hns3_hw *hw)
6367 {
6368         struct hns3_cmd_desc desc;
6369
6370         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6371         desc.data[0] = 0xeedd;
6372
6373         return hns3_cmd_send(hw, &desc, 1);
6374 }
6375
6376 static void
6377 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6378 {
6379         struct hns3_hw *hw = &hns->hw;
6380         struct timeval tv;
6381         uint32_t val;
6382
6383         hns3_clock_gettime(&tv);
6384         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6385             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6386                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6387                           tv.tv_sec, tv.tv_usec);
6388                 return;
6389         }
6390
6391         switch (reset_level) {
6392         case HNS3_IMP_RESET:
6393                 hns3_imp_reset_cmd(hw);
6394                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6395                           tv.tv_sec, tv.tv_usec);
6396                 break;
6397         case HNS3_GLOBAL_RESET:
6398                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6399                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6400                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6401                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6402                           tv.tv_sec, tv.tv_usec);
6403                 break;
6404         case HNS3_FUNC_RESET:
6405                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6406                           tv.tv_sec, tv.tv_usec);
6407                 /* schedule again to check later */
6408                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6409                 hns3_schedule_reset(hns);
6410                 break;
6411         default:
6412                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6413                 return;
6414         }
6415         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6416 }
6417
6418 static enum hns3_reset_level
6419 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6420 {
6421         struct hns3_hw *hw = &hns->hw;
6422         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6423
6424         /* Return the highest priority reset level amongst all */
6425         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6426                 reset_level = HNS3_IMP_RESET;
6427         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6428                 reset_level = HNS3_GLOBAL_RESET;
6429         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6430                 reset_level = HNS3_FUNC_RESET;
6431         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6432                 reset_level = HNS3_FLR_RESET;
6433
6434         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6435                 return HNS3_NONE_RESET;
6436
6437         return reset_level;
6438 }
6439
6440 static void
6441 hns3_record_imp_error(struct hns3_adapter *hns)
6442 {
6443         struct hns3_hw *hw = &hns->hw;
6444         uint32_t reg_val;
6445
6446         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6447         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6448                 hns3_warn(hw, "Detected IMP RD poison!");
6449                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6450                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6451         }
6452
6453         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6454                 hns3_warn(hw, "Detected IMP CMDQ error!");
6455                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6456                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6457         }
6458 }
6459
6460 static int
6461 hns3_prepare_reset(struct hns3_adapter *hns)
6462 {
6463         struct hns3_hw *hw = &hns->hw;
6464         uint32_t reg_val;
6465         int ret;
6466
6467         switch (hw->reset.level) {
6468         case HNS3_FUNC_RESET:
6469                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6470                 if (ret)
6471                         return ret;
6472
6473                 /*
6474                  * After performaning pf reset, it is not necessary to do the
6475                  * mailbox handling or send any command to firmware, because
6476                  * any mailbox handling or command to firmware is only valid
6477                  * after hns3_cmd_init is called.
6478                  */
6479                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6480                 hw->reset.stats.request_cnt++;
6481                 break;
6482         case HNS3_IMP_RESET:
6483                 hns3_record_imp_error(hns);
6484                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6485                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6486                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6487                 break;
6488         default:
6489                 break;
6490         }
6491         return 0;
6492 }
6493
6494 static int
6495 hns3_set_rst_done(struct hns3_hw *hw)
6496 {
6497         struct hns3_pf_rst_done_cmd *req;
6498         struct hns3_cmd_desc desc;
6499
6500         req = (struct hns3_pf_rst_done_cmd *)desc.data;
6501         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6502         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6503         return hns3_cmd_send(hw, &desc, 1);
6504 }
6505
6506 static int
6507 hns3_stop_service(struct hns3_adapter *hns)
6508 {
6509         struct hns3_hw *hw = &hns->hw;
6510         struct rte_eth_dev *eth_dev;
6511
6512         eth_dev = &rte_eth_devices[hw->data->port_id];
6513         hw->mac.link_status = RTE_ETH_LINK_DOWN;
6514         if (hw->adapter_state == HNS3_NIC_STARTED) {
6515                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6516                 hns3_update_linkstatus_and_event(hw, false);
6517         }
6518
6519         hns3_set_rxtx_function(eth_dev);
6520         rte_wmb();
6521         /* Disable datapath on secondary process. */
6522         hns3_mp_req_stop_rxtx(eth_dev);
6523         rte_delay_ms(hw->cfg_max_queues);
6524
6525         rte_spinlock_lock(&hw->lock);
6526         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6527             hw->adapter_state == HNS3_NIC_STOPPING) {
6528                 hns3_enable_all_queues(hw, false);
6529                 hns3_do_stop(hns);
6530                 hw->reset.mbuf_deferred_free = true;
6531         } else
6532                 hw->reset.mbuf_deferred_free = false;
6533
6534         /*
6535          * It is cumbersome for hardware to pick-and-choose entries for deletion
6536          * from table space. Hence, for function reset software intervention is
6537          * required to delete the entries
6538          */
6539         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6540                 hns3_configure_all_mc_mac_addr(hns, true);
6541         rte_spinlock_unlock(&hw->lock);
6542
6543         return 0;
6544 }
6545
6546 static int
6547 hns3_start_service(struct hns3_adapter *hns)
6548 {
6549         struct hns3_hw *hw = &hns->hw;
6550         struct rte_eth_dev *eth_dev;
6551
6552         if (hw->reset.level == HNS3_IMP_RESET ||
6553             hw->reset.level == HNS3_GLOBAL_RESET)
6554                 hns3_set_rst_done(hw);
6555         eth_dev = &rte_eth_devices[hw->data->port_id];
6556         hns3_set_rxtx_function(eth_dev);
6557         hns3_mp_req_start_rxtx(eth_dev);
6558         if (hw->adapter_state == HNS3_NIC_STARTED) {
6559                 /*
6560                  * This API parent function already hold the hns3_hw.lock, the
6561                  * hns3_service_handler may report lse, in bonding application
6562                  * it will call driver's ops which may acquire the hns3_hw.lock
6563                  * again, thus lead to deadlock.
6564                  * We defer calls hns3_service_handler to avoid the deadlock.
6565                  */
6566                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6567                                   hns3_service_handler, eth_dev);
6568
6569                 /* Enable interrupt of all rx queues before enabling queues */
6570                 hns3_dev_all_rx_queue_intr_enable(hw, true);
6571                 /*
6572                  * Enable state of each rxq and txq will be recovered after
6573                  * reset, so we need to restore them before enable all tqps;
6574                  */
6575                 hns3_restore_tqp_enable_state(hw);
6576                 /*
6577                  * When finished the initialization, enable queues to receive
6578                  * and transmit packets.
6579                  */
6580                 hns3_enable_all_queues(hw, true);
6581         }
6582
6583         return 0;
6584 }
6585
6586 static int
6587 hns3_restore_conf(struct hns3_adapter *hns)
6588 {
6589         struct hns3_hw *hw = &hns->hw;
6590         int ret;
6591
6592         ret = hns3_configure_all_mac_addr(hns, false);
6593         if (ret)
6594                 return ret;
6595
6596         ret = hns3_configure_all_mc_mac_addr(hns, false);
6597         if (ret)
6598                 goto err_mc_mac;
6599
6600         ret = hns3_dev_promisc_restore(hns);
6601         if (ret)
6602                 goto err_promisc;
6603
6604         ret = hns3_restore_vlan_table(hns);
6605         if (ret)
6606                 goto err_promisc;
6607
6608         ret = hns3_restore_vlan_conf(hns);
6609         if (ret)
6610                 goto err_promisc;
6611
6612         ret = hns3_restore_all_fdir_filter(hns);
6613         if (ret)
6614                 goto err_promisc;
6615
6616         ret = hns3_restore_ptp(hns);
6617         if (ret)
6618                 goto err_promisc;
6619
6620         ret = hns3_restore_rx_interrupt(hw);
6621         if (ret)
6622                 goto err_promisc;
6623
6624         ret = hns3_restore_gro_conf(hw);
6625         if (ret)
6626                 goto err_promisc;
6627
6628         ret = hns3_restore_fec(hw);
6629         if (ret)
6630                 goto err_promisc;
6631
6632         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6633                 ret = hns3_do_start(hns, false);
6634                 if (ret)
6635                         goto err_promisc;
6636                 hns3_info(hw, "hns3 dev restart successful!");
6637         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6638                 hw->adapter_state = HNS3_NIC_CONFIGURED;
6639         return 0;
6640
6641 err_promisc:
6642         hns3_configure_all_mc_mac_addr(hns, true);
6643 err_mc_mac:
6644         hns3_configure_all_mac_addr(hns, true);
6645         return ret;
6646 }
6647
6648 static void
6649 hns3_reset_service(void *param)
6650 {
6651         struct hns3_adapter *hns = (struct hns3_adapter *)param;
6652         struct hns3_hw *hw = &hns->hw;
6653         enum hns3_reset_level reset_level;
6654         struct timeval tv_delta;
6655         struct timeval tv_start;
6656         struct timeval tv;
6657         uint64_t msec;
6658         int ret;
6659
6660         /*
6661          * The interrupt is not triggered within the delay time.
6662          * The interrupt may have been lost. It is necessary to handle
6663          * the interrupt to recover from the error.
6664          */
6665         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6666                             SCHEDULE_DEFERRED) {
6667                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6668                                   __ATOMIC_RELAXED);
6669                 hns3_err(hw, "Handling interrupts in delayed tasks");
6670                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6671                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6672                 if (reset_level == HNS3_NONE_RESET) {
6673                         hns3_err(hw, "No reset level is set, try IMP reset");
6674                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6675                 }
6676         }
6677         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6678
6679         /*
6680          * Check if there is any ongoing reset in the hardware. This status can
6681          * be checked from reset_pending. If there is then, we need to wait for
6682          * hardware to complete reset.
6683          *    a. If we are able to figure out in reasonable time that hardware
6684          *       has fully resetted then, we can proceed with driver, client
6685          *       reset.
6686          *    b. else, we can come back later to check this status so re-sched
6687          *       now.
6688          */
6689         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6690         if (reset_level != HNS3_NONE_RESET) {
6691                 hns3_clock_gettime(&tv_start);
6692                 ret = hns3_reset_process(hns, reset_level);
6693                 hns3_clock_gettime(&tv);
6694                 timersub(&tv, &tv_start, &tv_delta);
6695                 msec = hns3_clock_calctime_ms(&tv_delta);
6696                 if (msec > HNS3_RESET_PROCESS_MS)
6697                         hns3_err(hw, "%d handle long time delta %" PRIu64
6698                                      " ms time=%ld.%.6ld",
6699                                  hw->reset.level, msec,
6700                                  tv.tv_sec, tv.tv_usec);
6701                 if (ret == -EAGAIN)
6702                         return;
6703         }
6704
6705         /* Check if we got any *new* reset requests to be honored */
6706         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6707         if (reset_level != HNS3_NONE_RESET)
6708                 hns3_msix_process(hns, reset_level);
6709 }
6710
6711 static unsigned int
6712 hns3_get_speed_capa_num(uint16_t device_id)
6713 {
6714         unsigned int num;
6715
6716         switch (device_id) {
6717         case HNS3_DEV_ID_25GE:
6718         case HNS3_DEV_ID_25GE_RDMA:
6719                 num = 2;
6720                 break;
6721         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6722         case HNS3_DEV_ID_200G_RDMA:
6723                 num = 1;
6724                 break;
6725         default:
6726                 num = 0;
6727                 break;
6728         }
6729
6730         return num;
6731 }
6732
6733 static int
6734 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6735                         uint16_t device_id)
6736 {
6737         switch (device_id) {
6738         case HNS3_DEV_ID_25GE:
6739         /* fallthrough */
6740         case HNS3_DEV_ID_25GE_RDMA:
6741                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6742                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6743
6744                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6745                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6746                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6747                 break;
6748         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6749                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6750                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6751                 break;
6752         case HNS3_DEV_ID_200G_RDMA:
6753                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6754                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6755                 break;
6756         default:
6757                 return -ENOTSUP;
6758         }
6759
6760         return 0;
6761 }
6762
6763 static int
6764 hns3_fec_get_capability(struct rte_eth_dev *dev,
6765                         struct rte_eth_fec_capa *speed_fec_capa,
6766                         unsigned int num)
6767 {
6768         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6769         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6770         uint16_t device_id = pci_dev->id.device_id;
6771         unsigned int capa_num;
6772         int ret;
6773
6774         capa_num = hns3_get_speed_capa_num(device_id);
6775         if (capa_num == 0) {
6776                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6777                          device_id);
6778                 return -ENOTSUP;
6779         }
6780
6781         if (speed_fec_capa == NULL || num < capa_num)
6782                 return capa_num;
6783
6784         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6785         if (ret)
6786                 return -ENOTSUP;
6787
6788         return capa_num;
6789 }
6790
6791 static int
6792 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6793 {
6794         struct hns3_config_fec_cmd *req;
6795         struct hns3_cmd_desc desc;
6796         int ret;
6797
6798         /*
6799          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6800          * in device of link speed
6801          * below 10 Gbps.
6802          */
6803         if (hw->mac.link_speed < RTE_ETH_SPEED_NUM_10G) {
6804                 *state = 0;
6805                 return 0;
6806         }
6807
6808         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6809         req = (struct hns3_config_fec_cmd *)desc.data;
6810         ret = hns3_cmd_send(hw, &desc, 1);
6811         if (ret) {
6812                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6813                          ret);
6814                 return ret;
6815         }
6816
6817         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6818         return 0;
6819 }
6820
6821 static int
6822 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6823 {
6824         struct hns3_sfp_info_cmd *resp;
6825         uint32_t tmp_fec_capa;
6826         uint8_t auto_state;
6827         struct hns3_cmd_desc desc;
6828         int ret;
6829
6830         /*
6831          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6832          * configured FEC mode is returned.
6833          * If link is up, current FEC mode is returned.
6834          */
6835         if (hw->mac.link_status == RTE_ETH_LINK_DOWN) {
6836                 ret = get_current_fec_auto_state(hw, &auto_state);
6837                 if (ret)
6838                         return ret;
6839
6840                 if (auto_state == 0x1) {
6841                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6842                         return 0;
6843                 }
6844         }
6845
6846         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6847         resp = (struct hns3_sfp_info_cmd *)desc.data;
6848         resp->query_type = HNS3_ACTIVE_QUERY;
6849
6850         ret = hns3_cmd_send(hw, &desc, 1);
6851         if (ret == -EOPNOTSUPP) {
6852                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6853                 return ret;
6854         } else if (ret) {
6855                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6856                 return ret;
6857         }
6858
6859         /*
6860          * FEC mode order defined in hns3 hardware is inconsistend with
6861          * that defined in the ethdev library. So the sequence needs
6862          * to be converted.
6863          */
6864         switch (resp->active_fec) {
6865         case HNS3_HW_FEC_MODE_NOFEC:
6866                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6867                 break;
6868         case HNS3_HW_FEC_MODE_BASER:
6869                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6870                 break;
6871         case HNS3_HW_FEC_MODE_RS:
6872                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6873                 break;
6874         default:
6875                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6876                 break;
6877         }
6878
6879         *fec_capa = tmp_fec_capa;
6880         return 0;
6881 }
6882
6883 static int
6884 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6885 {
6886         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6887
6888         return hns3_fec_get_internal(hw, fec_capa);
6889 }
6890
6891 static int
6892 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6893 {
6894         struct hns3_config_fec_cmd *req;
6895         struct hns3_cmd_desc desc;
6896         int ret;
6897
6898         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6899
6900         req = (struct hns3_config_fec_cmd *)desc.data;
6901         switch (mode) {
6902         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6903                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6904                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6905                 break;
6906         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6907                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6908                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6909                 break;
6910         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6911                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6912                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6913                 break;
6914         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6915                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6916                 break;
6917         default:
6918                 return 0;
6919         }
6920         ret = hns3_cmd_send(hw, &desc, 1);
6921         if (ret)
6922                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6923
6924         return ret;
6925 }
6926
6927 static uint32_t
6928 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6929 {
6930         struct hns3_mac *mac = &hw->mac;
6931         uint32_t cur_capa;
6932
6933         switch (mac->link_speed) {
6934         case RTE_ETH_SPEED_NUM_10G:
6935                 cur_capa = fec_capa[1].capa;
6936                 break;
6937         case RTE_ETH_SPEED_NUM_25G:
6938         case RTE_ETH_SPEED_NUM_100G:
6939         case RTE_ETH_SPEED_NUM_200G:
6940                 cur_capa = fec_capa[0].capa;
6941                 break;
6942         default:
6943                 cur_capa = 0;
6944                 break;
6945         }
6946
6947         return cur_capa;
6948 }
6949
6950 static bool
6951 is_fec_mode_one_bit_set(uint32_t mode)
6952 {
6953         int cnt = 0;
6954         uint8_t i;
6955
6956         for (i = 0; i < sizeof(mode); i++)
6957                 if (mode >> i & 0x1)
6958                         cnt++;
6959
6960         return cnt == 1 ? true : false;
6961 }
6962
6963 static int
6964 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6965 {
6966 #define FEC_CAPA_NUM 2
6967         struct hns3_adapter *hns = dev->data->dev_private;
6968         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6969         struct hns3_pf *pf = &hns->pf;
6970
6971         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6972         uint32_t cur_capa;
6973         uint32_t num = FEC_CAPA_NUM;
6974         int ret;
6975
6976         ret = hns3_fec_get_capability(dev, fec_capa, num);
6977         if (ret < 0)
6978                 return ret;
6979
6980         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6981         if (!is_fec_mode_one_bit_set(mode)) {
6982                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, "
6983                              "FEC mode should be only one bit set", mode);
6984                 return -EINVAL;
6985         }
6986
6987         /*
6988          * Check whether the configured mode is within the FEC capability.
6989          * If not, the configured mode will not be supported.
6990          */
6991         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6992         if (!(cur_capa & mode)) {
6993                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6994                 return -EINVAL;
6995         }
6996
6997         rte_spinlock_lock(&hw->lock);
6998         ret = hns3_set_fec_hw(hw, mode);
6999         if (ret) {
7000                 rte_spinlock_unlock(&hw->lock);
7001                 return ret;
7002         }
7003
7004         pf->fec_mode = mode;
7005         rte_spinlock_unlock(&hw->lock);
7006
7007         return 0;
7008 }
7009
7010 static int
7011 hns3_restore_fec(struct hns3_hw *hw)
7012 {
7013         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7014         struct hns3_pf *pf = &hns->pf;
7015         uint32_t mode = pf->fec_mode;
7016         int ret;
7017
7018         ret = hns3_set_fec_hw(hw, mode);
7019         if (ret)
7020                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
7021                          mode, ret);
7022
7023         return ret;
7024 }
7025
7026 static int
7027 hns3_query_dev_fec_info(struct hns3_hw *hw)
7028 {
7029         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7030         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
7031         int ret;
7032
7033         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
7034         if (ret)
7035                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
7036
7037         return ret;
7038 }
7039
7040 static bool
7041 hns3_optical_module_existed(struct hns3_hw *hw)
7042 {
7043         struct hns3_cmd_desc desc;
7044         bool existed;
7045         int ret;
7046
7047         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
7048         ret = hns3_cmd_send(hw, &desc, 1);
7049         if (ret) {
7050                 hns3_err(hw,
7051                          "fail to get optical module exist state, ret = %d.\n",
7052                          ret);
7053                 return false;
7054         }
7055         existed = !!desc.data[0];
7056
7057         return existed;
7058 }
7059
7060 static int
7061 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
7062                                 uint32_t len, uint8_t *data)
7063 {
7064 #define HNS3_SFP_INFO_CMD_NUM 6
7065 #define HNS3_SFP_INFO_MAX_LEN \
7066         (HNS3_SFP_INFO_BD0_LEN + \
7067         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
7068         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
7069         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
7070         uint16_t read_len;
7071         uint16_t copy_len;
7072         int ret;
7073         int i;
7074
7075         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7076                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
7077                                           true);
7078                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
7079                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
7080         }
7081
7082         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
7083         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
7084         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
7085         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
7086
7087         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
7088         if (ret) {
7089                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
7090                                 ret);
7091                 return ret;
7092         }
7093
7094         /* The data format in BD0 is different with the others. */
7095         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
7096         memcpy(data, sfp_info_bd0->data, copy_len);
7097         read_len = copy_len;
7098
7099         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7100                 if (read_len >= len)
7101                         break;
7102
7103                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
7104                 memcpy(data + read_len, desc[i].data, copy_len);
7105                 read_len += copy_len;
7106         }
7107
7108         return (int)read_len;
7109 }
7110
7111 static int
7112 hns3_get_module_eeprom(struct rte_eth_dev *dev,
7113                        struct rte_dev_eeprom_info *info)
7114 {
7115         struct hns3_adapter *hns = dev->data->dev_private;
7116         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7117         uint32_t offset = info->offset;
7118         uint32_t len = info->length;
7119         uint8_t *data = info->data;
7120         uint32_t read_len = 0;
7121
7122         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
7123                 return -ENOTSUP;
7124
7125         if (!hns3_optical_module_existed(hw)) {
7126                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
7127                 return -EIO;
7128         }
7129
7130         while (read_len < len) {
7131                 int ret;
7132                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
7133                                                   len - read_len,
7134                                                   data + read_len);
7135                 if (ret < 0)
7136                         return -EIO;
7137                 read_len += ret;
7138         }
7139
7140         return 0;
7141 }
7142
7143 static int
7144 hns3_get_module_info(struct rte_eth_dev *dev,
7145                      struct rte_eth_dev_module_info *modinfo)
7146 {
7147 #define HNS3_SFF8024_ID_SFP             0x03
7148 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
7149 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
7150 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
7151 #define HNS3_SFF_8636_V1_3              0x03
7152         struct hns3_adapter *hns = dev->data->dev_private;
7153         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7154         struct rte_dev_eeprom_info info;
7155         struct hns3_sfp_type sfp_type;
7156         int ret;
7157
7158         memset(&sfp_type, 0, sizeof(sfp_type));
7159         memset(&info, 0, sizeof(info));
7160         info.data = (uint8_t *)&sfp_type;
7161         info.length = sizeof(sfp_type);
7162         ret = hns3_get_module_eeprom(dev, &info);
7163         if (ret)
7164                 return ret;
7165
7166         switch (sfp_type.type) {
7167         case HNS3_SFF8024_ID_SFP:
7168                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7169                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7170                 break;
7171         case HNS3_SFF8024_ID_QSFP_8438:
7172                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7173                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7174                 break;
7175         case HNS3_SFF8024_ID_QSFP_8436_8636:
7176                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
7177                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
7178                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7179                 } else {
7180                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
7181                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7182                 }
7183                 break;
7184         case HNS3_SFF8024_ID_QSFP28_8636:
7185                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7186                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7187                 break;
7188         default:
7189                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
7190                          sfp_type.type, sfp_type.ext_type);
7191                 return -EINVAL;
7192         }
7193
7194         return 0;
7195 }
7196
7197 void
7198 hns3_clock_gettime(struct timeval *tv)
7199 {
7200 #ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */
7201 #define CLOCK_TYPE CLOCK_MONOTONIC_RAW
7202 #else
7203 #define CLOCK_TYPE CLOCK_MONOTONIC
7204 #endif
7205 #define NSEC_TO_USEC_DIV 1000
7206
7207         struct timespec spec;
7208         (void)clock_gettime(CLOCK_TYPE, &spec);
7209
7210         tv->tv_sec = spec.tv_sec;
7211         tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV;
7212 }
7213
7214 uint64_t
7215 hns3_clock_calctime_ms(struct timeval *tv)
7216 {
7217         return (uint64_t)tv->tv_sec * MSEC_PER_SEC +
7218                 tv->tv_usec / USEC_PER_MSEC;
7219 }
7220
7221 uint64_t
7222 hns3_clock_gettime_ms(void)
7223 {
7224         struct timeval tv;
7225
7226         hns3_clock_gettime(&tv);
7227         return hns3_clock_calctime_ms(&tv);
7228 }
7229
7230 static int
7231 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
7232 {
7233         uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
7234
7235         RTE_SET_USED(key);
7236
7237         if (strcmp(value, "vec") == 0)
7238                 hint = HNS3_IO_FUNC_HINT_VEC;
7239         else if (strcmp(value, "sve") == 0)
7240                 hint = HNS3_IO_FUNC_HINT_SVE;
7241         else if (strcmp(value, "simple") == 0)
7242                 hint = HNS3_IO_FUNC_HINT_SIMPLE;
7243         else if (strcmp(value, "common") == 0)
7244                 hint = HNS3_IO_FUNC_HINT_COMMON;
7245
7246         /* If the hint is valid then update output parameters */
7247         if (hint != HNS3_IO_FUNC_HINT_NONE)
7248                 *(uint32_t *)extra_args = hint;
7249
7250         return 0;
7251 }
7252
7253 static const char *
7254 hns3_get_io_hint_func_name(uint32_t hint)
7255 {
7256         switch (hint) {
7257         case HNS3_IO_FUNC_HINT_VEC:
7258                 return "vec";
7259         case HNS3_IO_FUNC_HINT_SVE:
7260                 return "sve";
7261         case HNS3_IO_FUNC_HINT_SIMPLE:
7262                 return "simple";
7263         case HNS3_IO_FUNC_HINT_COMMON:
7264                 return "common";
7265         default:
7266                 return "none";
7267         }
7268 }
7269
7270 static int
7271 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args)
7272 {
7273         uint64_t val;
7274
7275         RTE_SET_USED(key);
7276
7277         val = strtoull(value, NULL, 16);
7278         *(uint64_t *)extra_args = val;
7279
7280         return 0;
7281 }
7282
7283 static int
7284 hns3_parse_mbx_time_limit(const char *key, const char *value, void *extra_args)
7285 {
7286         uint32_t val;
7287
7288         RTE_SET_USED(key);
7289
7290         val = strtoul(value, NULL, 10);
7291
7292         /*
7293          * 500ms is empirical value in process of mailbox communication. If
7294          * the delay value is set to one lower thanthe empirical value, mailbox
7295          * communication may fail.
7296          */
7297         if (val > HNS3_MBX_DEF_TIME_LIMIT_MS && val <= UINT16_MAX)
7298                 *(uint16_t *)extra_args = val;
7299
7300         return 0;
7301 }
7302
7303 void
7304 hns3_parse_devargs(struct rte_eth_dev *dev)
7305 {
7306         uint16_t mbx_time_limit_ms = HNS3_MBX_DEF_TIME_LIMIT_MS;
7307         struct hns3_adapter *hns = dev->data->dev_private;
7308         uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7309         uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7310         struct hns3_hw *hw = &hns->hw;
7311         uint64_t dev_caps_mask = 0;
7312         struct rte_kvargs *kvlist;
7313
7314         if (dev->device->devargs == NULL)
7315                 return;
7316
7317         kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
7318         if (!kvlist)
7319                 return;
7320
7321         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
7322                            &hns3_parse_io_hint_func, &rx_func_hint);
7323         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
7324                            &hns3_parse_io_hint_func, &tx_func_hint);
7325         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK,
7326                            &hns3_parse_dev_caps_mask, &dev_caps_mask);
7327         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_MBX_TIME_LIMIT_MS,
7328                            &hns3_parse_mbx_time_limit, &mbx_time_limit_ms);
7329
7330         rte_kvargs_free(kvlist);
7331
7332         if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7333                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
7334                           hns3_get_io_hint_func_name(rx_func_hint));
7335         hns->rx_func_hint = rx_func_hint;
7336         if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7337                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
7338                           hns3_get_io_hint_func_name(tx_func_hint));
7339         hns->tx_func_hint = tx_func_hint;
7340
7341         if (dev_caps_mask != 0)
7342                 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".",
7343                           HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask);
7344         hns->dev_caps_mask = dev_caps_mask;
7345
7346         if (mbx_time_limit_ms != HNS3_MBX_DEF_TIME_LIMIT_MS)
7347                 hns3_warn(hw, "parsed %s = %u.", HNS3_DEVARG_MBX_TIME_LIMIT_MS,
7348                                 mbx_time_limit_ms);
7349         hns->mbx_time_limit_ms = mbx_time_limit_ms;
7350 }
7351
7352 static const struct eth_dev_ops hns3_eth_dev_ops = {
7353         .dev_configure      = hns3_dev_configure,
7354         .dev_start          = hns3_dev_start,
7355         .dev_stop           = hns3_dev_stop,
7356         .dev_close          = hns3_dev_close,
7357         .promiscuous_enable = hns3_dev_promiscuous_enable,
7358         .promiscuous_disable = hns3_dev_promiscuous_disable,
7359         .allmulticast_enable  = hns3_dev_allmulticast_enable,
7360         .allmulticast_disable = hns3_dev_allmulticast_disable,
7361         .mtu_set            = hns3_dev_mtu_set,
7362         .stats_get          = hns3_stats_get,
7363         .stats_reset        = hns3_stats_reset,
7364         .xstats_get         = hns3_dev_xstats_get,
7365         .xstats_get_names   = hns3_dev_xstats_get_names,
7366         .xstats_reset       = hns3_dev_xstats_reset,
7367         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
7368         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
7369         .dev_infos_get          = hns3_dev_infos_get,
7370         .fw_version_get         = hns3_fw_version_get,
7371         .rx_queue_setup         = hns3_rx_queue_setup,
7372         .tx_queue_setup         = hns3_tx_queue_setup,
7373         .rx_queue_release       = hns3_dev_rx_queue_release,
7374         .tx_queue_release       = hns3_dev_tx_queue_release,
7375         .rx_queue_start         = hns3_dev_rx_queue_start,
7376         .rx_queue_stop          = hns3_dev_rx_queue_stop,
7377         .tx_queue_start         = hns3_dev_tx_queue_start,
7378         .tx_queue_stop          = hns3_dev_tx_queue_stop,
7379         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
7380         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
7381         .rxq_info_get           = hns3_rxq_info_get,
7382         .txq_info_get           = hns3_txq_info_get,
7383         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
7384         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
7385         .flow_ctrl_get          = hns3_flow_ctrl_get,
7386         .flow_ctrl_set          = hns3_flow_ctrl_set,
7387         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
7388         .mac_addr_add           = hns3_add_mac_addr,
7389         .mac_addr_remove        = hns3_remove_mac_addr,
7390         .mac_addr_set           = hns3_set_default_mac_addr,
7391         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
7392         .link_update            = hns3_dev_link_update,
7393         .dev_set_link_up        = hns3_dev_set_link_up,
7394         .dev_set_link_down      = hns3_dev_set_link_down,
7395         .rss_hash_update        = hns3_dev_rss_hash_update,
7396         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
7397         .reta_update            = hns3_dev_rss_reta_update,
7398         .reta_query             = hns3_dev_rss_reta_query,
7399         .flow_ops_get           = hns3_dev_flow_ops_get,
7400         .vlan_filter_set        = hns3_vlan_filter_set,
7401         .vlan_tpid_set          = hns3_vlan_tpid_set,
7402         .vlan_offload_set       = hns3_vlan_offload_set,
7403         .vlan_pvid_set          = hns3_vlan_pvid_set,
7404         .get_reg                = hns3_get_regs,
7405         .get_module_info        = hns3_get_module_info,
7406         .get_module_eeprom      = hns3_get_module_eeprom,
7407         .get_dcb_info           = hns3_get_dcb_info,
7408         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
7409         .fec_get_capability     = hns3_fec_get_capability,
7410         .fec_get                = hns3_fec_get,
7411         .fec_set                = hns3_fec_set,
7412         .tm_ops_get             = hns3_tm_ops_get,
7413         .tx_done_cleanup        = hns3_tx_done_cleanup,
7414         .timesync_enable            = hns3_timesync_enable,
7415         .timesync_disable           = hns3_timesync_disable,
7416         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
7417         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
7418         .timesync_adjust_time       = hns3_timesync_adjust_time,
7419         .timesync_read_time         = hns3_timesync_read_time,
7420         .timesync_write_time        = hns3_timesync_write_time,
7421 };
7422
7423 static const struct hns3_reset_ops hns3_reset_ops = {
7424         .reset_service       = hns3_reset_service,
7425         .stop_service        = hns3_stop_service,
7426         .prepare_reset       = hns3_prepare_reset,
7427         .wait_hardware_ready = hns3_wait_hardware_ready,
7428         .reinit_dev          = hns3_reinit_dev,
7429         .restore_conf        = hns3_restore_conf,
7430         .start_service       = hns3_start_service,
7431 };
7432
7433 static void
7434 hns3_init_hw_ops(struct hns3_hw *hw)
7435 {
7436         hw->ops.add_mc_mac_addr = hns3_add_mc_mac_addr;
7437         hw->ops.del_mc_mac_addr = hns3_remove_mc_mac_addr;
7438         hw->ops.add_uc_mac_addr = hns3_add_uc_mac_addr;
7439         hw->ops.del_uc_mac_addr = hns3_remove_uc_mac_addr;
7440 }
7441
7442 static int
7443 hns3_dev_init(struct rte_eth_dev *eth_dev)
7444 {
7445         struct hns3_adapter *hns = eth_dev->data->dev_private;
7446         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
7447         struct rte_ether_addr *eth_addr;
7448         struct hns3_hw *hw = &hns->hw;
7449         int ret;
7450
7451         PMD_INIT_FUNC_TRACE();
7452
7453         hns3_flow_init(eth_dev);
7454
7455         hns3_set_rxtx_function(eth_dev);
7456         eth_dev->dev_ops = &hns3_eth_dev_ops;
7457         eth_dev->rx_queue_count = hns3_rx_queue_count;
7458         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7459                 ret = hns3_mp_init_secondary();
7460                 if (ret) {
7461                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
7462                                      "process, ret = %d", ret);
7463                         goto err_mp_init_secondary;
7464                 }
7465                 hw->secondary_cnt++;
7466                 hns3_tx_push_init(eth_dev);
7467                 return 0;
7468         }
7469
7470         ret = hns3_mp_init_primary();
7471         if (ret) {
7472                 PMD_INIT_LOG(ERR,
7473                              "Failed to init for primary process, ret = %d",
7474                              ret);
7475                 goto err_mp_init_primary;
7476         }
7477
7478         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
7479         hns->is_vf = false;
7480         hw->data = eth_dev->data;
7481         hns3_parse_devargs(eth_dev);
7482
7483         /*
7484          * Set default max packet size according to the mtu
7485          * default vale in DPDK frame.
7486          */
7487         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
7488
7489         ret = hns3_reset_init(hw);
7490         if (ret)
7491                 goto err_init_reset;
7492         hw->reset.ops = &hns3_reset_ops;
7493
7494         hns3_init_hw_ops(hw);
7495         ret = hns3_init_pf(eth_dev);
7496         if (ret) {
7497                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
7498                 goto err_init_pf;
7499         }
7500
7501         /* Allocate memory for storing MAC addresses */
7502         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
7503                                                sizeof(struct rte_ether_addr) *
7504                                                HNS3_UC_MACADDR_NUM, 0);
7505         if (eth_dev->data->mac_addrs == NULL) {
7506                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
7507                              "to store MAC addresses",
7508                              sizeof(struct rte_ether_addr) *
7509                              HNS3_UC_MACADDR_NUM);
7510                 ret = -ENOMEM;
7511                 goto err_rte_zmalloc;
7512         }
7513
7514         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
7515         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
7516                 rte_eth_random_addr(hw->mac.mac_addr);
7517                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
7518                                 (struct rte_ether_addr *)hw->mac.mac_addr);
7519                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
7520                           "unicast address, using random MAC address %s",
7521                           mac_str);
7522         }
7523         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7524                             &eth_dev->data->mac_addrs[0]);
7525
7526         hw->adapter_state = HNS3_NIC_INITIALIZED;
7527
7528         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7529                             SCHEDULE_PENDING) {
7530                 hns3_err(hw, "Reschedule reset service after dev_init");
7531                 hns3_schedule_reset(hns);
7532         } else {
7533                 /* IMP will wait ready flag before reset */
7534                 hns3_notify_reset_ready(hw, false);
7535         }
7536
7537         hns3_info(hw, "hns3 dev initialization successful!");
7538         return 0;
7539
7540 err_rte_zmalloc:
7541         hns3_uninit_pf(eth_dev);
7542
7543 err_init_pf:
7544         rte_free(hw->reset.wait_data);
7545
7546 err_init_reset:
7547         hns3_mp_uninit_primary();
7548
7549 err_mp_init_primary:
7550 err_mp_init_secondary:
7551         eth_dev->dev_ops = NULL;
7552         eth_dev->rx_pkt_burst = NULL;
7553         eth_dev->rx_descriptor_status = NULL;
7554         eth_dev->tx_pkt_burst = NULL;
7555         eth_dev->tx_pkt_prepare = NULL;
7556         eth_dev->tx_descriptor_status = NULL;
7557         return ret;
7558 }
7559
7560 static int
7561 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7562 {
7563         struct hns3_adapter *hns = eth_dev->data->dev_private;
7564         struct hns3_hw *hw = &hns->hw;
7565
7566         PMD_INIT_FUNC_TRACE();
7567
7568         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
7569                 return 0;
7570
7571         if (hw->adapter_state < HNS3_NIC_CLOSING)
7572                 hns3_dev_close(eth_dev);
7573
7574         hw->adapter_state = HNS3_NIC_REMOVED;
7575         return 0;
7576 }
7577
7578 static int
7579 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7580                    struct rte_pci_device *pci_dev)
7581 {
7582         return rte_eth_dev_pci_generic_probe(pci_dev,
7583                                              sizeof(struct hns3_adapter),
7584                                              hns3_dev_init);
7585 }
7586
7587 static int
7588 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7589 {
7590         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7591 }
7592
7593 static const struct rte_pci_id pci_id_hns3_map[] = {
7594         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7595         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7596         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7597         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7598         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7599         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7600         { .vendor_id = 0, }, /* sentinel */
7601 };
7602
7603 static struct rte_pci_driver rte_hns3_pmd = {
7604         .id_table = pci_id_hns3_map,
7605         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7606         .probe = eth_hns3_pci_probe,
7607         .remove = eth_hns3_pci_remove,
7608 };
7609
7610 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7611 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7612 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7613 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7614                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7615                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
7616                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
7617                 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16> ");
7618 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE);
7619 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE);