1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
6 #include <rte_bus_pci.h>
7 #include <ethdev_pci.h>
9 #include <rte_kvargs.h>
11 #include "hns3_ethdev.h"
12 #include "hns3_logs.h"
13 #include "hns3_rxtx.h"
14 #include "hns3_intr.h"
15 #include "hns3_regs.h"
19 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
20 #define HNS3_SERVICE_QUICK_INTERVAL 10
21 #define HNS3_INVALID_PVID 0xFFFF
23 #define HNS3_FILTER_TYPE_VF 0
24 #define HNS3_FILTER_TYPE_PORT 1
25 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
26 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
27 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
28 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
29 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
30 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
31 | HNS3_FILTER_FE_ROCE_EGRESS_B)
32 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
33 | HNS3_FILTER_FE_ROCE_INGRESS_B)
35 /* Reset related Registers */
36 #define HNS3_GLOBAL_RESET_BIT 0
37 #define HNS3_CORE_RESET_BIT 1
38 #define HNS3_IMP_RESET_BIT 2
39 #define HNS3_FUN_RST_ING_B 0
41 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
42 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
43 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U
44 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
46 #define HNS3_RESET_WAIT_MS 100
47 #define HNS3_RESET_WAIT_CNT 200
49 /* FEC mode order defined in HNS3 hardware */
50 #define HNS3_HW_FEC_MODE_NOFEC 0
51 #define HNS3_HW_FEC_MODE_BASER 1
52 #define HNS3_HW_FEC_MODE_RS 2
55 HNS3_VECTOR0_EVENT_RST,
56 HNS3_VECTOR0_EVENT_MBX,
57 HNS3_VECTOR0_EVENT_ERR,
58 HNS3_VECTOR0_EVENT_PTP,
59 HNS3_VECTOR0_EVENT_OTHER,
62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
63 { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
64 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
65 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
67 { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
68 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
69 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
70 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
72 { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
73 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
74 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
76 { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
77 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
78 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
79 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
81 { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
82 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
83 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
85 { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
86 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
87 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
95 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
96 static bool hns3_update_link_status(struct hns3_hw *hw);
98 static int hns3_add_mc_addr(struct hns3_hw *hw,
99 struct rte_ether_addr *mac_addr);
100 static int hns3_remove_mc_addr(struct hns3_hw *hw,
101 struct rte_ether_addr *mac_addr);
102 static int hns3_restore_fec(struct hns3_hw *hw);
103 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
104 static int hns3_do_stop(struct hns3_adapter *hns);
105 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
107 void hns3_ether_format_addr(char *buf, uint16_t size,
108 const struct rte_ether_addr *ether_addr)
110 snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
111 ether_addr->addr_bytes[0],
112 ether_addr->addr_bytes[4],
113 ether_addr->addr_bytes[5]);
117 hns3_pf_disable_irq0(struct hns3_hw *hw)
119 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
123 hns3_pf_enable_irq0(struct hns3_hw *hw)
125 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
128 static enum hns3_evt_cause
129 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
132 struct hns3_hw *hw = &hns->hw;
134 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
135 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
136 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
138 hw->reset.stats.imp_cnt++;
139 hns3_warn(hw, "IMP reset detected, clear reset status");
141 hns3_schedule_delayed_reset(hns);
142 hns3_warn(hw, "IMP reset detected, don't clear reset status");
145 return HNS3_VECTOR0_EVENT_RST;
148 static enum hns3_evt_cause
149 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
152 struct hns3_hw *hw = &hns->hw;
154 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
155 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
156 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
158 hw->reset.stats.global_cnt++;
159 hns3_warn(hw, "Global reset detected, clear reset status");
161 hns3_schedule_delayed_reset(hns);
163 "Global reset detected, don't clear reset status");
166 return HNS3_VECTOR0_EVENT_RST;
169 static enum hns3_evt_cause
170 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
172 struct hns3_hw *hw = &hns->hw;
173 uint32_t vector0_int_stats;
174 uint32_t cmdq_src_val;
175 uint32_t hw_err_src_reg;
177 enum hns3_evt_cause ret;
180 /* fetch the events from their corresponding regs */
181 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
182 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
183 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
185 is_delay = clearval == NULL ? true : false;
187 * Assumption: If by any chance reset and mailbox events are reported
188 * together then we will only process reset event and defer the
189 * processing of the mailbox events. Since, we would have not cleared
190 * RX CMDQ event this time we would receive again another interrupt
191 * from H/W just for the mailbox.
193 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
194 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
199 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
200 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
204 /* Check for vector0 1588 event source */
205 if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
206 val = BIT(HNS3_VECTOR0_1588_INT_B);
207 ret = HNS3_VECTOR0_EVENT_PTP;
211 /* check for vector0 msix event source */
212 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
213 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
214 val = vector0_int_stats | hw_err_src_reg;
215 ret = HNS3_VECTOR0_EVENT_ERR;
219 /* check for vector0 mailbox(=CMDQ RX) event source */
220 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
221 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
223 ret = HNS3_VECTOR0_EVENT_MBX;
227 val = vector0_int_stats;
228 ret = HNS3_VECTOR0_EVENT_OTHER;
237 hns3_is_1588_event_type(uint32_t event_type)
239 return (event_type == HNS3_VECTOR0_EVENT_PTP);
243 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
245 if (event_type == HNS3_VECTOR0_EVENT_RST ||
246 hns3_is_1588_event_type(event_type))
247 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
248 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
249 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
253 hns3_clear_all_event_cause(struct hns3_hw *hw)
255 uint32_t vector0_int_stats;
257 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
258 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
259 hns3_warn(hw, "Probe during IMP reset interrupt");
261 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
262 hns3_warn(hw, "Probe during Global reset interrupt");
264 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
265 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
266 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
267 BIT(HNS3_VECTOR0_CORERESET_INT_B));
268 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
269 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
270 BIT(HNS3_VECTOR0_1588_INT_B));
274 hns3_handle_mac_tnl(struct hns3_hw *hw)
276 struct hns3_cmd_desc desc;
280 /* query and clear mac tnl interrupt */
281 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
282 ret = hns3_cmd_send(hw, &desc, 1);
284 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
288 status = rte_le_to_cpu_32(desc.data[0]);
290 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
291 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
293 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
294 ret = hns3_cmd_send(hw, &desc, 1);
296 hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
302 hns3_interrupt_handler(void *param)
304 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
305 struct hns3_adapter *hns = dev->data->dev_private;
306 struct hns3_hw *hw = &hns->hw;
307 enum hns3_evt_cause event_cause;
308 uint32_t clearval = 0;
309 uint32_t vector0_int;
313 /* Disable interrupt */
314 hns3_pf_disable_irq0(hw);
316 event_cause = hns3_check_event_cause(hns, &clearval);
317 vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
318 ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
319 cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
320 hns3_clear_event_cause(hw, event_cause, clearval);
321 /* vector 0 interrupt is shared with reset and mailbox source events. */
322 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
323 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
324 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
325 vector0_int, ras_int, cmdq_int);
326 hns3_handle_mac_tnl(hw);
327 hns3_handle_error(hns);
328 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
329 hns3_warn(hw, "received reset interrupt");
330 hns3_schedule_reset(hns);
331 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
332 hns3_dev_handle_mbx_msg(hw);
334 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
335 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
336 vector0_int, ras_int, cmdq_int);
339 /* Enable interrupt if it is not cause by reset */
340 hns3_pf_enable_irq0(hw);
344 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
346 #define HNS3_VLAN_ID_OFFSET_STEP 160
347 #define HNS3_VLAN_BYTE_SIZE 8
348 struct hns3_vlan_filter_pf_cfg_cmd *req;
349 struct hns3_hw *hw = &hns->hw;
350 uint8_t vlan_offset_byte_val;
351 struct hns3_cmd_desc desc;
352 uint8_t vlan_offset_byte;
353 uint8_t vlan_offset_base;
356 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
358 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
359 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
361 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
363 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
364 req->vlan_offset = vlan_offset_base;
365 req->vlan_cfg = on ? 0 : 1;
366 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
368 ret = hns3_cmd_send(hw, &desc, 1);
370 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
377 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
379 struct hns3_user_vlan_table *vlan_entry;
380 struct hns3_pf *pf = &hns->pf;
382 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
383 if (vlan_entry->vlan_id == vlan_id) {
384 if (vlan_entry->hd_tbl_status)
385 hns3_set_port_vlan_filter(hns, vlan_id, 0);
386 LIST_REMOVE(vlan_entry, next);
387 rte_free(vlan_entry);
394 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
397 struct hns3_user_vlan_table *vlan_entry;
398 struct hns3_hw *hw = &hns->hw;
399 struct hns3_pf *pf = &hns->pf;
401 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
402 if (vlan_entry->vlan_id == vlan_id)
406 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
407 if (vlan_entry == NULL) {
408 hns3_err(hw, "Failed to malloc hns3 vlan table");
412 vlan_entry->hd_tbl_status = writen_to_tbl;
413 vlan_entry->vlan_id = vlan_id;
415 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
419 hns3_restore_vlan_table(struct hns3_adapter *hns)
421 struct hns3_user_vlan_table *vlan_entry;
422 struct hns3_hw *hw = &hns->hw;
423 struct hns3_pf *pf = &hns->pf;
427 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
428 return hns3_vlan_pvid_configure(hns,
429 hw->port_base_vlan_cfg.pvid, 1);
431 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
432 if (vlan_entry->hd_tbl_status) {
433 vlan_id = vlan_entry->vlan_id;
434 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
444 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
446 struct hns3_hw *hw = &hns->hw;
447 bool writen_to_tbl = false;
451 * When vlan filter is enabled, hardware regards packets without vlan
452 * as packets with vlan 0. So, to receive packets without vlan, vlan id
453 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
455 if (on == 0 && vlan_id == 0)
459 * When port base vlan enabled, we use port base vlan as the vlan
460 * filter condition. In this case, we don't update vlan filter table
461 * when user add new vlan or remove exist vlan, just update the
462 * vlan list. The vlan id in vlan list will be written in vlan filter
463 * table until port base vlan disabled
465 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
466 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
467 writen_to_tbl = true;
472 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
474 hns3_rm_dev_vlan_table(hns, vlan_id);
480 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
482 struct hns3_adapter *hns = dev->data->dev_private;
483 struct hns3_hw *hw = &hns->hw;
486 rte_spinlock_lock(&hw->lock);
487 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
488 rte_spinlock_unlock(&hw->lock);
493 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
496 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
497 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
498 struct hns3_hw *hw = &hns->hw;
499 struct hns3_cmd_desc desc;
502 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
503 vlan_type != ETH_VLAN_TYPE_OUTER)) {
504 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
508 if (tpid != RTE_ETHER_TYPE_VLAN) {
509 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
513 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
514 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
516 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
517 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
518 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
519 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
520 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
521 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
522 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
523 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
526 ret = hns3_cmd_send(hw, &desc, 1);
528 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
533 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
535 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
536 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
537 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
539 ret = hns3_cmd_send(hw, &desc, 1);
541 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
547 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
550 struct hns3_adapter *hns = dev->data->dev_private;
551 struct hns3_hw *hw = &hns->hw;
554 rte_spinlock_lock(&hw->lock);
555 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
556 rte_spinlock_unlock(&hw->lock);
561 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
562 struct hns3_rx_vtag_cfg *vcfg)
564 struct hns3_vport_vtag_rx_cfg_cmd *req;
565 struct hns3_hw *hw = &hns->hw;
566 struct hns3_cmd_desc desc;
571 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
573 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
574 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
575 vcfg->strip_tag1_en ? 1 : 0);
576 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
577 vcfg->strip_tag2_en ? 1 : 0);
578 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
579 vcfg->vlan1_vlan_prionly ? 1 : 0);
580 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
581 vcfg->vlan2_vlan_prionly ? 1 : 0);
583 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
584 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
585 vcfg->strip_tag1_discard_en ? 1 : 0);
586 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
587 vcfg->strip_tag2_discard_en ? 1 : 0);
589 * In current version VF is not supported when PF is driven by DPDK
590 * driver, just need to configure parameters for PF vport.
592 vport_id = HNS3_PF_FUNC_ID;
593 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
594 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
595 req->vf_bitmap[req->vf_offset] = bitmap;
597 ret = hns3_cmd_send(hw, &desc, 1);
599 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
604 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
605 struct hns3_rx_vtag_cfg *vcfg)
607 struct hns3_pf *pf = &hns->pf;
608 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
612 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
613 struct hns3_tx_vtag_cfg *vcfg)
615 struct hns3_pf *pf = &hns->pf;
616 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
620 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
622 struct hns3_rx_vtag_cfg rxvlan_cfg;
623 struct hns3_hw *hw = &hns->hw;
626 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
627 rxvlan_cfg.strip_tag1_en = false;
628 rxvlan_cfg.strip_tag2_en = enable;
629 rxvlan_cfg.strip_tag2_discard_en = false;
631 rxvlan_cfg.strip_tag1_en = enable;
632 rxvlan_cfg.strip_tag2_en = true;
633 rxvlan_cfg.strip_tag2_discard_en = true;
636 rxvlan_cfg.strip_tag1_discard_en = false;
637 rxvlan_cfg.vlan1_vlan_prionly = false;
638 rxvlan_cfg.vlan2_vlan_prionly = false;
639 rxvlan_cfg.rx_vlan_offload_en = enable;
641 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
643 hns3_err(hw, "%s strip rx vtag failed, ret = %d.",
644 enable ? "enable" : "disable", ret);
648 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
654 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
655 uint8_t fe_type, bool filter_en, uint8_t vf_id)
657 struct hns3_vlan_filter_ctrl_cmd *req;
658 struct hns3_cmd_desc desc;
661 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
663 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
664 req->vlan_type = vlan_type;
665 req->vlan_fe = filter_en ? fe_type : 0;
668 ret = hns3_cmd_send(hw, &desc, 1);
670 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
676 hns3_vlan_filter_init(struct hns3_adapter *hns)
678 struct hns3_hw *hw = &hns->hw;
681 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
682 HNS3_FILTER_FE_EGRESS, false,
685 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
689 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
690 HNS3_FILTER_FE_INGRESS, false,
693 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
699 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
701 struct hns3_hw *hw = &hns->hw;
704 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
705 HNS3_FILTER_FE_INGRESS, enable,
708 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
709 enable ? "enable" : "disable", ret);
715 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
717 struct hns3_adapter *hns = dev->data->dev_private;
718 struct hns3_hw *hw = &hns->hw;
719 struct rte_eth_rxmode *rxmode;
720 unsigned int tmp_mask;
724 rte_spinlock_lock(&hw->lock);
725 rxmode = &dev->data->dev_conf.rxmode;
726 tmp_mask = (unsigned int)mask;
727 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
728 /* ignore vlan filter configuration during promiscuous mode */
729 if (!dev->data->promiscuous) {
730 /* Enable or disable VLAN filter */
731 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
734 ret = hns3_enable_vlan_filter(hns, enable);
736 rte_spinlock_unlock(&hw->lock);
737 hns3_err(hw, "failed to %s rx filter, ret = %d",
738 enable ? "enable" : "disable", ret);
744 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
745 /* Enable or disable VLAN stripping */
746 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
749 ret = hns3_en_hw_strip_rxvtag(hns, enable);
751 rte_spinlock_unlock(&hw->lock);
752 hns3_err(hw, "failed to %s rx strip, ret = %d",
753 enable ? "enable" : "disable", ret);
758 rte_spinlock_unlock(&hw->lock);
764 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
765 struct hns3_tx_vtag_cfg *vcfg)
767 struct hns3_vport_vtag_tx_cfg_cmd *req;
768 struct hns3_cmd_desc desc;
769 struct hns3_hw *hw = &hns->hw;
774 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
776 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
777 req->def_vlan_tag1 = vcfg->default_tag1;
778 req->def_vlan_tag2 = vcfg->default_tag2;
779 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
780 vcfg->accept_tag1 ? 1 : 0);
781 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
782 vcfg->accept_untag1 ? 1 : 0);
783 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
784 vcfg->accept_tag2 ? 1 : 0);
785 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
786 vcfg->accept_untag2 ? 1 : 0);
787 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
788 vcfg->insert_tag1_en ? 1 : 0);
789 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
790 vcfg->insert_tag2_en ? 1 : 0);
791 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
793 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
794 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
795 vcfg->tag_shift_mode_en ? 1 : 0);
798 * In current version VF is not supported when PF is driven by DPDK
799 * driver, just need to configure parameters for PF vport.
801 vport_id = HNS3_PF_FUNC_ID;
802 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
803 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
804 req->vf_bitmap[req->vf_offset] = bitmap;
806 ret = hns3_cmd_send(hw, &desc, 1);
808 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
814 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
817 struct hns3_hw *hw = &hns->hw;
818 struct hns3_tx_vtag_cfg txvlan_cfg;
821 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
822 txvlan_cfg.accept_tag1 = true;
823 txvlan_cfg.insert_tag1_en = false;
824 txvlan_cfg.default_tag1 = 0;
826 txvlan_cfg.accept_tag1 =
827 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
828 txvlan_cfg.insert_tag1_en = true;
829 txvlan_cfg.default_tag1 = pvid;
832 txvlan_cfg.accept_untag1 = true;
833 txvlan_cfg.accept_tag2 = true;
834 txvlan_cfg.accept_untag2 = true;
835 txvlan_cfg.insert_tag2_en = false;
836 txvlan_cfg.default_tag2 = 0;
837 txvlan_cfg.tag_shift_mode_en = true;
839 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
841 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
846 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
852 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
854 struct hns3_user_vlan_table *vlan_entry;
855 struct hns3_pf *pf = &hns->pf;
857 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
858 if (vlan_entry->hd_tbl_status) {
859 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
860 vlan_entry->hd_tbl_status = false;
865 vlan_entry = LIST_FIRST(&pf->vlan_list);
867 LIST_REMOVE(vlan_entry, next);
868 rte_free(vlan_entry);
869 vlan_entry = LIST_FIRST(&pf->vlan_list);
875 hns3_add_all_vlan_table(struct hns3_adapter *hns)
877 struct hns3_user_vlan_table *vlan_entry;
878 struct hns3_pf *pf = &hns->pf;
880 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
881 if (!vlan_entry->hd_tbl_status) {
882 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
883 vlan_entry->hd_tbl_status = true;
889 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
891 struct hns3_hw *hw = &hns->hw;
894 hns3_rm_all_vlan_table(hns, true);
895 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
896 ret = hns3_set_port_vlan_filter(hns,
897 hw->port_base_vlan_cfg.pvid, 0);
899 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
907 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
908 uint16_t port_base_vlan_state, uint16_t new_pvid)
910 struct hns3_hw *hw = &hns->hw;
914 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
915 old_pvid = hw->port_base_vlan_cfg.pvid;
916 if (old_pvid != HNS3_INVALID_PVID) {
917 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
919 hns3_err(hw, "failed to remove old pvid %u, "
920 "ret = %d", old_pvid, ret);
925 hns3_rm_all_vlan_table(hns, false);
926 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
928 hns3_err(hw, "failed to add new pvid %u, ret = %d",
933 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
935 hns3_err(hw, "failed to remove pvid %u, ret = %d",
940 hns3_add_all_vlan_table(hns);
946 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
948 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
949 struct hns3_rx_vtag_cfg rx_vlan_cfg;
953 rx_strip_en = old_cfg->rx_vlan_offload_en;
955 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
956 rx_vlan_cfg.strip_tag2_en = true;
957 rx_vlan_cfg.strip_tag2_discard_en = true;
959 rx_vlan_cfg.strip_tag1_en = false;
960 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
961 rx_vlan_cfg.strip_tag2_discard_en = false;
963 rx_vlan_cfg.strip_tag1_discard_en = false;
964 rx_vlan_cfg.vlan1_vlan_prionly = false;
965 rx_vlan_cfg.vlan2_vlan_prionly = false;
966 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
968 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
972 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
977 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
979 struct hns3_hw *hw = &hns->hw;
980 uint16_t port_base_vlan_state;
983 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
984 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
985 hns3_warn(hw, "Invalid operation! As current pvid set "
986 "is %u, disable pvid %u is invalid",
987 hw->port_base_vlan_cfg.pvid, pvid);
991 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
992 HNS3_PORT_BASE_VLAN_DISABLE;
993 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
995 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
1000 ret = hns3_en_pvid_strip(hns, on);
1002 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1004 goto pvid_vlan_strip_fail;
1007 if (pvid == HNS3_INVALID_PVID)
1009 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1011 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1013 goto vlan_filter_set_fail;
1017 hw->port_base_vlan_cfg.state = port_base_vlan_state;
1018 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1021 vlan_filter_set_fail:
1022 err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1023 HNS3_PORT_BASE_VLAN_ENABLE);
1025 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1027 pvid_vlan_strip_fail:
1028 err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1029 hw->port_base_vlan_cfg.pvid);
1031 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1037 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1039 struct hns3_adapter *hns = dev->data->dev_private;
1040 struct hns3_hw *hw = &hns->hw;
1041 bool pvid_en_state_change;
1042 uint16_t pvid_state;
1045 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1046 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1047 RTE_ETHER_MAX_VLAN_ID);
1052 * If PVID configuration state change, should refresh the PVID
1053 * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1055 pvid_state = hw->port_base_vlan_cfg.state;
1056 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1057 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1058 pvid_en_state_change = false;
1060 pvid_en_state_change = true;
1062 rte_spinlock_lock(&hw->lock);
1063 ret = hns3_vlan_pvid_configure(hns, pvid, on);
1064 rte_spinlock_unlock(&hw->lock);
1068 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1069 * need be processed by PMD driver.
1071 if (pvid_en_state_change &&
1072 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1073 hns3_update_all_queues_pvid_proc_en(hw);
1079 hns3_default_vlan_config(struct hns3_adapter *hns)
1081 struct hns3_hw *hw = &hns->hw;
1085 * When vlan filter is enabled, hardware regards packets without vlan
1086 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1087 * table, packets without vlan won't be received. So, add vlan 0 as
1090 ret = hns3_vlan_filter_configure(hns, 0, 1);
1092 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1097 hns3_init_vlan_config(struct hns3_adapter *hns)
1099 struct hns3_hw *hw = &hns->hw;
1103 * This function can be called in the initialization and reset process,
1104 * when in reset process, it means that hardware had been reseted
1105 * successfully and we need to restore the hardware configuration to
1106 * ensure that the hardware configuration remains unchanged before and
1109 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1110 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1111 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1114 ret = hns3_vlan_filter_init(hns);
1116 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1120 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1121 RTE_ETHER_TYPE_VLAN);
1123 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1128 * When in the reinit dev stage of the reset process, the following
1129 * vlan-related configurations may differ from those at initialization,
1130 * we will restore configurations to hardware in hns3_restore_vlan_table
1131 * and hns3_restore_vlan_conf later.
1133 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1134 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1136 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1140 ret = hns3_en_hw_strip_rxvtag(hns, false);
1142 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1148 return hns3_default_vlan_config(hns);
1152 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1154 struct hns3_pf *pf = &hns->pf;
1155 struct hns3_hw *hw = &hns->hw;
1160 if (!hw->data->promiscuous) {
1161 /* restore vlan filter states */
1162 offloads = hw->data->dev_conf.rxmode.offloads;
1163 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1164 ret = hns3_enable_vlan_filter(hns, enable);
1166 hns3_err(hw, "failed to restore vlan rx filter conf, "
1172 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1174 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1178 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1180 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1186 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1188 struct hns3_adapter *hns = dev->data->dev_private;
1189 struct rte_eth_dev_data *data = dev->data;
1190 struct rte_eth_txmode *txmode;
1191 struct hns3_hw *hw = &hns->hw;
1195 txmode = &data->dev_conf.txmode;
1196 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1198 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1199 "configuration is not supported! Ignore these two "
1200 "parameters: hw_vlan_reject_tagged(%u), "
1201 "hw_vlan_reject_untagged(%u)",
1202 txmode->hw_vlan_reject_tagged,
1203 txmode->hw_vlan_reject_untagged);
1205 /* Apply vlan offload setting */
1206 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1207 ret = hns3_vlan_offload_set(dev, mask);
1209 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1215 * If pvid config is not set in rte_eth_conf, driver needn't to set
1216 * VLAN pvid related configuration to hardware.
1218 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1221 /* Apply pvid setting */
1222 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1223 txmode->hw_vlan_insert_pvid);
1225 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1232 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1233 unsigned int tso_mss_max)
1235 struct hns3_cfg_tso_status_cmd *req;
1236 struct hns3_cmd_desc desc;
1239 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1241 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1244 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1246 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1249 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1251 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1253 return hns3_cmd_send(hw, &desc, 1);
1257 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1258 uint16_t *allocated_size, bool is_alloc)
1260 struct hns3_umv_spc_alc_cmd *req;
1261 struct hns3_cmd_desc desc;
1264 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1265 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1266 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1267 req->space_size = rte_cpu_to_le_32(space_size);
1269 ret = hns3_cmd_send(hw, &desc, 1);
1271 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1272 is_alloc ? "allocate" : "free", ret);
1276 if (is_alloc && allocated_size)
1277 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1283 hns3_init_umv_space(struct hns3_hw *hw)
1285 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1286 struct hns3_pf *pf = &hns->pf;
1287 uint16_t allocated_size = 0;
1290 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1295 if (allocated_size < pf->wanted_umv_size)
1296 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1297 pf->wanted_umv_size, allocated_size);
1299 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1300 pf->wanted_umv_size;
1301 pf->used_umv_size = 0;
1306 hns3_uninit_umv_space(struct hns3_hw *hw)
1308 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1309 struct hns3_pf *pf = &hns->pf;
1312 if (pf->max_umv_size == 0)
1315 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1319 pf->max_umv_size = 0;
1325 hns3_is_umv_space_full(struct hns3_hw *hw)
1327 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1328 struct hns3_pf *pf = &hns->pf;
1331 is_full = (pf->used_umv_size >= pf->max_umv_size);
1337 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1339 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1340 struct hns3_pf *pf = &hns->pf;
1343 if (pf->used_umv_size > 0)
1344 pf->used_umv_size--;
1346 pf->used_umv_size++;
1350 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1351 const uint8_t *addr, bool is_mc)
1353 const unsigned char *mac_addr = addr;
1354 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1355 ((uint32_t)mac_addr[2] << 16) |
1356 ((uint32_t)mac_addr[1] << 8) |
1357 (uint32_t)mac_addr[0];
1358 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1360 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1362 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1363 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1364 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1367 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1368 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1372 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1374 enum hns3_mac_vlan_tbl_opcode op)
1377 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1382 if (op == HNS3_MAC_VLAN_ADD) {
1383 if (resp_code == 0 || resp_code == 1) {
1385 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1386 hns3_err(hw, "add mac addr failed for uc_overflow");
1388 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1389 hns3_err(hw, "add mac addr failed for mc_overflow");
1393 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1396 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1397 if (resp_code == 0) {
1399 } else if (resp_code == 1) {
1400 hns3_dbg(hw, "remove mac addr failed for miss");
1404 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1407 } else if (op == HNS3_MAC_VLAN_LKUP) {
1408 if (resp_code == 0) {
1410 } else if (resp_code == 1) {
1411 hns3_dbg(hw, "lookup mac addr failed for miss");
1415 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1420 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1427 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1428 struct hns3_mac_vlan_tbl_entry_cmd *req,
1429 struct hns3_cmd_desc *desc, bool is_mc)
1435 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1437 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1438 memcpy(desc[0].data, req,
1439 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1440 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1442 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1443 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1445 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1447 memcpy(desc[0].data, req,
1448 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1449 ret = hns3_cmd_send(hw, desc, 1);
1452 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1456 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1457 retval = rte_le_to_cpu_16(desc[0].retval);
1459 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1460 HNS3_MAC_VLAN_LKUP);
1464 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1465 struct hns3_mac_vlan_tbl_entry_cmd *req,
1466 struct hns3_cmd_desc *mc_desc)
1473 if (mc_desc == NULL) {
1474 struct hns3_cmd_desc desc;
1476 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1477 memcpy(desc.data, req,
1478 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1479 ret = hns3_cmd_send(hw, &desc, 1);
1480 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1481 retval = rte_le_to_cpu_16(desc.retval);
1483 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1486 hns3_cmd_reuse_desc(&mc_desc[0], false);
1487 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1488 hns3_cmd_reuse_desc(&mc_desc[1], false);
1489 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1490 hns3_cmd_reuse_desc(&mc_desc[2], false);
1491 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1492 memcpy(mc_desc[0].data, req,
1493 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1494 mc_desc[0].retval = 0;
1495 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1496 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1497 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1499 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1504 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1512 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1513 struct hns3_mac_vlan_tbl_entry_cmd *req)
1515 struct hns3_cmd_desc desc;
1520 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1522 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1524 ret = hns3_cmd_send(hw, &desc, 1);
1526 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1529 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1530 retval = rte_le_to_cpu_16(desc.retval);
1532 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1533 HNS3_MAC_VLAN_REMOVE);
1537 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1539 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1540 struct hns3_mac_vlan_tbl_entry_cmd req;
1541 struct hns3_pf *pf = &hns->pf;
1542 struct hns3_cmd_desc desc[3];
1543 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1544 uint16_t egress_port = 0;
1548 /* check if mac addr is valid */
1549 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1550 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1552 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1557 memset(&req, 0, sizeof(req));
1560 * In current version VF is not supported when PF is driven by DPDK
1561 * driver, just need to configure parameters for PF vport.
1563 vf_id = HNS3_PF_FUNC_ID;
1564 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1565 HNS3_MAC_EPORT_VFID_S, vf_id);
1567 req.egress_port = rte_cpu_to_le_16(egress_port);
1569 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1572 * Lookup the mac address in the mac_vlan table, and add
1573 * it if the entry is inexistent. Repeated unicast entry
1574 * is not allowed in the mac vlan table.
1576 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1577 if (ret == -ENOENT) {
1578 if (!hns3_is_umv_space_full(hw)) {
1579 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1581 hns3_update_umv_space(hw, false);
1585 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1590 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1592 /* check if we just hit the duplicate */
1594 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1598 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1605 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1607 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1608 struct rte_ether_addr *addr;
1612 for (i = 0; i < hw->mc_addrs_num; i++) {
1613 addr = &hw->mc_addrs[i];
1614 /* Check if there are duplicate addresses */
1615 if (rte_is_same_ether_addr(addr, mac_addr)) {
1616 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1618 hns3_err(hw, "failed to add mc mac addr, same addrs"
1619 "(%s) is added by the set_mc_mac_addr_list "
1625 ret = hns3_add_mc_addr(hw, mac_addr);
1627 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1629 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1636 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1638 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1641 ret = hns3_remove_mc_addr(hw, mac_addr);
1643 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1645 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1652 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1653 uint32_t idx, __rte_unused uint32_t pool)
1655 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1656 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1659 rte_spinlock_lock(&hw->lock);
1662 * In hns3 network engine adding UC and MC mac address with different
1663 * commands with firmware. We need to determine whether the input
1664 * address is a UC or a MC address to call different commands.
1665 * By the way, it is recommended calling the API function named
1666 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1667 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1668 * may affect the specifications of UC mac addresses.
1670 if (rte_is_multicast_ether_addr(mac_addr))
1671 ret = hns3_add_mc_addr_common(hw, mac_addr);
1673 ret = hns3_add_uc_addr_common(hw, mac_addr);
1676 rte_spinlock_unlock(&hw->lock);
1677 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1679 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1685 hw->mac.default_addr_setted = true;
1686 rte_spinlock_unlock(&hw->lock);
1692 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1694 struct hns3_mac_vlan_tbl_entry_cmd req;
1695 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1698 /* check if mac addr is valid */
1699 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1700 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1702 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1707 memset(&req, 0, sizeof(req));
1708 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1709 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1710 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1711 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1714 hns3_update_umv_space(hw, true);
1720 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1722 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1723 /* index will be checked by upper level rte interface */
1724 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1725 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1728 rte_spinlock_lock(&hw->lock);
1730 if (rte_is_multicast_ether_addr(mac_addr))
1731 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1733 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1734 rte_spinlock_unlock(&hw->lock);
1736 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1738 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1744 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1745 struct rte_ether_addr *mac_addr)
1747 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1748 struct rte_ether_addr *oaddr;
1749 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1750 bool default_addr_setted;
1754 * It has been guaranteed that input parameter named mac_addr is valid
1755 * address in the rte layer of DPDK framework.
1757 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1758 default_addr_setted = hw->mac.default_addr_setted;
1759 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1762 rte_spinlock_lock(&hw->lock);
1763 if (default_addr_setted) {
1764 ret = hns3_remove_uc_addr_common(hw, oaddr);
1766 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1768 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1771 rte_spinlock_unlock(&hw->lock);
1776 ret = hns3_add_uc_addr_common(hw, mac_addr);
1778 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1780 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1781 goto err_add_uc_addr;
1784 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1786 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1787 goto err_pause_addr_cfg;
1790 rte_ether_addr_copy(mac_addr,
1791 (struct rte_ether_addr *)hw->mac.mac_addr);
1792 hw->mac.default_addr_setted = true;
1793 rte_spinlock_unlock(&hw->lock);
1798 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1800 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1803 "Failed to roll back to del setted mac addr(%s): %d",
1808 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1810 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, oaddr);
1811 hns3_warn(hw, "Failed to restore old uc mac addr(%s): %d",
1813 hw->mac.default_addr_setted = false;
1815 rte_spinlock_unlock(&hw->lock);
1821 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1823 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1824 struct hns3_hw *hw = &hns->hw;
1825 struct rte_ether_addr *addr;
1830 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1831 addr = &hw->data->mac_addrs[i];
1832 if (rte_is_zero_ether_addr(addr))
1834 if (rte_is_multicast_ether_addr(addr))
1835 ret = del ? hns3_remove_mc_addr(hw, addr) :
1836 hns3_add_mc_addr(hw, addr);
1838 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1839 hns3_add_uc_addr_common(hw, addr);
1843 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1845 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1846 "ret = %d.", del ? "remove" : "restore",
1854 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1856 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1860 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1861 word_num = vfid / 32;
1862 bit_num = vfid % 32;
1864 desc[1].data[word_num] &=
1865 rte_cpu_to_le_32(~(1UL << bit_num));
1867 desc[1].data[word_num] |=
1868 rte_cpu_to_le_32(1UL << bit_num);
1870 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1871 bit_num = vfid % 32;
1873 desc[2].data[word_num] &=
1874 rte_cpu_to_le_32(~(1UL << bit_num));
1876 desc[2].data[word_num] |=
1877 rte_cpu_to_le_32(1UL << bit_num);
1882 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1884 struct hns3_mac_vlan_tbl_entry_cmd req;
1885 struct hns3_cmd_desc desc[3];
1886 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1890 /* Check if mac addr is valid */
1891 if (!rte_is_multicast_ether_addr(mac_addr)) {
1892 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1894 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1899 memset(&req, 0, sizeof(req));
1900 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1901 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1902 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1904 /* This mac addr do not exist, add new entry for it */
1905 memset(desc[0].data, 0, sizeof(desc[0].data));
1906 memset(desc[1].data, 0, sizeof(desc[0].data));
1907 memset(desc[2].data, 0, sizeof(desc[0].data));
1911 * In current version VF is not supported when PF is driven by DPDK
1912 * driver, just need to configure parameters for PF vport.
1914 vf_id = HNS3_PF_FUNC_ID;
1915 hns3_update_desc_vfid(desc, vf_id, false);
1916 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1919 hns3_err(hw, "mc mac vlan table is full");
1920 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1922 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1929 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1931 struct hns3_mac_vlan_tbl_entry_cmd req;
1932 struct hns3_cmd_desc desc[3];
1933 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1937 /* Check if mac addr is valid */
1938 if (!rte_is_multicast_ether_addr(mac_addr)) {
1939 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1941 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1946 memset(&req, 0, sizeof(req));
1947 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1948 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1949 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1952 * This mac addr exist, remove this handle's VFID for it.
1953 * In current version VF is not supported when PF is driven by
1954 * DPDK driver, just need to configure parameters for PF vport.
1956 vf_id = HNS3_PF_FUNC_ID;
1957 hns3_update_desc_vfid(desc, vf_id, true);
1959 /* All the vfid is zero, so need to delete this entry */
1960 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1961 } else if (ret == -ENOENT) {
1962 /* This mac addr doesn't exist. */
1967 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1969 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1976 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1977 struct rte_ether_addr *mc_addr_set,
1978 uint32_t nb_mc_addr)
1980 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1981 struct rte_ether_addr *addr;
1985 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1986 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1987 "invalid. valid range: 0~%d",
1988 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1992 /* Check if input mac addresses are valid */
1993 for (i = 0; i < nb_mc_addr; i++) {
1994 addr = &mc_addr_set[i];
1995 if (!rte_is_multicast_ether_addr(addr)) {
1996 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1999 "failed to set mc mac addr, addr(%s) invalid.",
2004 /* Check if there are duplicate addresses */
2005 for (j = i + 1; j < nb_mc_addr; j++) {
2006 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2007 hns3_ether_format_addr(mac_str,
2008 RTE_ETHER_ADDR_FMT_SIZE,
2010 hns3_err(hw, "failed to set mc mac addr, "
2011 "addrs invalid. two same addrs(%s).",
2018 * Check if there are duplicate addresses between mac_addrs
2021 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2022 if (rte_is_same_ether_addr(addr,
2023 &hw->data->mac_addrs[j])) {
2024 hns3_ether_format_addr(mac_str,
2025 RTE_ETHER_ADDR_FMT_SIZE,
2027 hns3_err(hw, "failed to set mc mac addr, "
2028 "addrs invalid. addrs(%s) has already "
2029 "configured in mac_addr add API",
2040 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2041 struct rte_ether_addr *mc_addr_set,
2043 struct rte_ether_addr *reserved_addr_list,
2044 int *reserved_addr_num,
2045 struct rte_ether_addr *add_addr_list,
2047 struct rte_ether_addr *rm_addr_list,
2050 struct rte_ether_addr *addr;
2051 int current_addr_num;
2052 int reserved_num = 0;
2060 /* Calculate the mc mac address list that should be removed */
2061 current_addr_num = hw->mc_addrs_num;
2062 for (i = 0; i < current_addr_num; i++) {
2063 addr = &hw->mc_addrs[i];
2065 for (j = 0; j < mc_addr_num; j++) {
2066 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2073 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2076 rte_ether_addr_copy(addr,
2077 &reserved_addr_list[reserved_num]);
2082 /* Calculate the mc mac address list that should be added */
2083 for (i = 0; i < mc_addr_num; i++) {
2084 addr = &mc_addr_set[i];
2086 for (j = 0; j < current_addr_num; j++) {
2087 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2094 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2099 /* Reorder the mc mac address list maintained by driver */
2100 for (i = 0; i < reserved_num; i++)
2101 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2103 for (i = 0; i < rm_num; i++) {
2104 num = reserved_num + i;
2105 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2108 *reserved_addr_num = reserved_num;
2109 *add_addr_num = add_num;
2110 *rm_addr_num = rm_num;
2114 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2115 struct rte_ether_addr *mc_addr_set,
2116 uint32_t nb_mc_addr)
2118 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2119 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2120 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2121 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2122 struct rte_ether_addr *addr;
2123 int reserved_addr_num;
2131 /* Check if input parameters are valid */
2132 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2136 rte_spinlock_lock(&hw->lock);
2139 * Calculate the mc mac address lists those should be removed and be
2140 * added, Reorder the mc mac address list maintained by driver.
2142 mc_addr_num = (int)nb_mc_addr;
2143 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2144 reserved_addr_list, &reserved_addr_num,
2145 add_addr_list, &add_addr_num,
2146 rm_addr_list, &rm_addr_num);
2148 /* Remove mc mac addresses */
2149 for (i = 0; i < rm_addr_num; i++) {
2150 num = rm_addr_num - i - 1;
2151 addr = &rm_addr_list[num];
2152 ret = hns3_remove_mc_addr(hw, addr);
2154 rte_spinlock_unlock(&hw->lock);
2160 /* Add mc mac addresses */
2161 for (i = 0; i < add_addr_num; i++) {
2162 addr = &add_addr_list[i];
2163 ret = hns3_add_mc_addr(hw, addr);
2165 rte_spinlock_unlock(&hw->lock);
2169 num = reserved_addr_num + i;
2170 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2173 rte_spinlock_unlock(&hw->lock);
2179 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2181 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2182 struct hns3_hw *hw = &hns->hw;
2183 struct rte_ether_addr *addr;
2188 for (i = 0; i < hw->mc_addrs_num; i++) {
2189 addr = &hw->mc_addrs[i];
2190 if (!rte_is_multicast_ether_addr(addr))
2193 ret = hns3_remove_mc_addr(hw, addr);
2195 ret = hns3_add_mc_addr(hw, addr);
2198 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2200 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2201 del ? "Remove" : "Restore", mac_str, ret);
2208 hns3_check_mq_mode(struct rte_eth_dev *dev)
2210 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2211 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2212 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2213 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2214 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2215 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2220 if ((rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG) ||
2221 (tx_mq_mode == ETH_MQ_TX_VMDQ_DCB ||
2222 tx_mq_mode == ETH_MQ_TX_VMDQ_ONLY)) {
2223 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
2224 rx_mq_mode, tx_mq_mode);
2228 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2229 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2230 if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
2231 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2232 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2233 dcb_rx_conf->nb_tcs, pf->tc_max);
2237 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2238 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2239 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2240 "nb_tcs(%d) != %d or %d in rx direction.",
2241 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2245 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2246 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2247 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2251 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2252 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2253 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2254 "is not equal to one in tx direction.",
2255 i, dcb_rx_conf->dcb_tc[i]);
2258 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2259 max_tc = dcb_rx_conf->dcb_tc[i];
2262 num_tc = max_tc + 1;
2263 if (num_tc > dcb_rx_conf->nb_tcs) {
2264 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2265 num_tc, dcb_rx_conf->nb_tcs);
2274 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2275 enum hns3_ring_type queue_type, uint16_t queue_id)
2277 struct hns3_cmd_desc desc;
2278 struct hns3_ctrl_vector_chain_cmd *req =
2279 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2280 enum hns3_opcode_type op;
2281 uint16_t tqp_type_and_id = 0;
2286 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2287 hns3_cmd_setup_basic_desc(&desc, op, false);
2288 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2289 HNS3_TQP_INT_ID_L_S);
2290 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2291 HNS3_TQP_INT_ID_H_S);
2293 if (queue_type == HNS3_RING_TYPE_RX)
2294 gl = HNS3_RING_GL_RX;
2296 gl = HNS3_RING_GL_TX;
2300 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2302 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2303 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2305 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2306 req->int_cause_num = 1;
2307 ret = hns3_cmd_send(hw, &desc, 1);
2309 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2310 en ? "Map" : "Unmap", queue_id, vector_id, ret);
2318 hns3_init_ring_with_vector(struct hns3_hw *hw)
2325 * In hns3 network engine, vector 0 is always the misc interrupt of this
2326 * function, vector 1~N can be used respectively for the queues of the
2327 * function. Tx and Rx queues with the same number share the interrupt
2328 * vector. In the initialization clearing the all hardware mapping
2329 * relationship configurations between queues and interrupt vectors is
2330 * needed, so some error caused by the residual configurations, such as
2331 * the unexpected Tx interrupt, can be avoid.
2333 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2334 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2335 vec = vec - 1; /* the last interrupt is reserved */
2336 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2337 for (i = 0; i < hw->intr_tqps_num; i++) {
2339 * Set gap limiter/rate limiter/quanity limiter algorithm
2340 * configuration for interrupt coalesce of queue's interrupt.
2342 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2343 HNS3_TQP_INTR_GL_DEFAULT);
2344 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2345 HNS3_TQP_INTR_GL_DEFAULT);
2346 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2348 * QL(quantity limiter) is not used currently, just set 0 to
2351 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2353 ret = hns3_bind_ring_with_vector(hw, vec, false,
2354 HNS3_RING_TYPE_TX, i);
2356 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2357 "vector: %u, ret=%d", i, vec, ret);
2361 ret = hns3_bind_ring_with_vector(hw, vec, false,
2362 HNS3_RING_TYPE_RX, i);
2364 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2365 "vector: %u, ret=%d", i, vec, ret);
2374 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2376 struct hns3_adapter *hns = dev->data->dev_private;
2377 struct hns3_hw *hw = &hns->hw;
2378 uint32_t max_rx_pkt_len;
2382 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2386 * If jumbo frames are enabled, MTU needs to be refreshed
2387 * according to the maximum RX packet length.
2389 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2390 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2391 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2392 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2393 "and no more than %u when jumbo frame enabled.",
2394 (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2395 (uint16_t)HNS3_MAX_FRAME_LEN);
2399 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2400 ret = hns3_dev_mtu_set(dev, mtu);
2403 dev->data->mtu = mtu;
2409 hns3_setup_dcb(struct rte_eth_dev *dev)
2411 struct hns3_adapter *hns = dev->data->dev_private;
2412 struct hns3_hw *hw = &hns->hw;
2415 if (!hns3_dev_dcb_supported(hw)) {
2416 hns3_err(hw, "this port does not support dcb configurations.");
2420 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2421 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2425 ret = hns3_dcb_configure(hns);
2427 hns3_err(hw, "failed to config dcb: %d", ret);
2433 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
2438 * Some hardware doesn't support auto-negotiation, but users may not
2439 * configure link_speeds (default 0), which means auto-negotiation.
2440 * In this case, it should return success.
2442 if (link_speeds == ETH_LINK_SPEED_AUTONEG &&
2443 hw->mac.support_autoneg == 0)
2446 if (link_speeds != ETH_LINK_SPEED_AUTONEG) {
2447 ret = hns3_check_port_speed(hw, link_speeds);
2456 hns3_check_dev_conf(struct rte_eth_dev *dev)
2458 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2459 struct rte_eth_conf *conf = &dev->data->dev_conf;
2462 ret = hns3_check_mq_mode(dev);
2466 return hns3_check_link_speed(hw, conf->link_speeds);
2470 hns3_dev_configure(struct rte_eth_dev *dev)
2472 struct hns3_adapter *hns = dev->data->dev_private;
2473 struct rte_eth_conf *conf = &dev->data->dev_conf;
2474 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2475 struct hns3_hw *hw = &hns->hw;
2476 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2477 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2478 struct rte_eth_rss_conf rss_conf;
2482 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2485 * Some versions of hardware network engine does not support
2486 * individually enable/disable/reset the Tx or Rx queue. These devices
2487 * must enable/disable/reset Tx and Rx queues at the same time. When the
2488 * numbers of Tx queues allocated by upper applications are not equal to
2489 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2490 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2491 * work as usual. But these fake queues are imperceptible, and can not
2492 * be used by upper applications.
2494 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2496 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
2497 hw->cfg_max_queues = 0;
2501 hw->adapter_state = HNS3_NIC_CONFIGURING;
2502 ret = hns3_check_dev_conf(dev);
2506 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2507 ret = hns3_setup_dcb(dev);
2512 /* When RSS is not configured, redirect the packet queue 0 */
2513 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2514 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2515 rss_conf = conf->rx_adv_conf.rss_conf;
2516 hw->rss_dis_flag = false;
2517 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2522 ret = hns3_refresh_mtu(dev, conf);
2526 ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2530 ret = hns3_dev_configure_vlan(dev);
2534 /* config hardware GRO */
2535 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2536 ret = hns3_config_gro(hw, gro_en);
2540 hns3_init_rx_ptype_tble(dev);
2541 hw->adapter_state = HNS3_NIC_CONFIGURED;
2546 hw->cfg_max_queues = 0;
2547 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2548 hw->adapter_state = HNS3_NIC_INITIALIZED;
2554 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2556 struct hns3_config_max_frm_size_cmd *req;
2557 struct hns3_cmd_desc desc;
2559 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2561 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2562 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2563 req->min_frm_size = RTE_ETHER_MIN_LEN;
2565 return hns3_cmd_send(hw, &desc, 1);
2569 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2571 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2572 uint16_t original_mps = hns->pf.mps;
2576 ret = hns3_set_mac_mtu(hw, mps);
2578 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2583 ret = hns3_buffer_alloc(hw);
2585 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2592 err = hns3_set_mac_mtu(hw, original_mps);
2594 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2597 hns->pf.mps = original_mps;
2603 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2605 struct hns3_adapter *hns = dev->data->dev_private;
2606 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2607 struct hns3_hw *hw = &hns->hw;
2608 bool is_jumbo_frame;
2611 if (dev->data->dev_started) {
2612 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2613 "before configuration", dev->data->port_id);
2617 rte_spinlock_lock(&hw->lock);
2618 is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2619 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2622 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2623 * assign to "uint16_t" type variable.
2625 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2627 rte_spinlock_unlock(&hw->lock);
2628 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2629 dev->data->port_id, mtu, ret);
2634 dev->data->dev_conf.rxmode.offloads |=
2635 DEV_RX_OFFLOAD_JUMBO_FRAME;
2637 dev->data->dev_conf.rxmode.offloads &=
2638 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2639 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2640 rte_spinlock_unlock(&hw->lock);
2646 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2648 uint32_t speed_capa = 0;
2650 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2651 speed_capa |= ETH_LINK_SPEED_10M_HD;
2652 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2653 speed_capa |= ETH_LINK_SPEED_10M;
2654 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2655 speed_capa |= ETH_LINK_SPEED_100M_HD;
2656 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2657 speed_capa |= ETH_LINK_SPEED_100M;
2658 if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2659 speed_capa |= ETH_LINK_SPEED_1G;
2665 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2667 uint32_t speed_capa = 0;
2669 if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2670 speed_capa |= ETH_LINK_SPEED_1G;
2671 if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2672 speed_capa |= ETH_LINK_SPEED_10G;
2673 if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2674 speed_capa |= ETH_LINK_SPEED_25G;
2675 if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2676 speed_capa |= ETH_LINK_SPEED_40G;
2677 if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2678 speed_capa |= ETH_LINK_SPEED_50G;
2679 if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2680 speed_capa |= ETH_LINK_SPEED_100G;
2681 if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2682 speed_capa |= ETH_LINK_SPEED_200G;
2688 hns3_get_speed_capa(struct hns3_hw *hw)
2690 struct hns3_mac *mac = &hw->mac;
2691 uint32_t speed_capa;
2693 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2695 hns3_get_copper_port_speed_capa(mac->supported_speed);
2698 hns3_get_firber_port_speed_capa(mac->supported_speed);
2700 if (mac->support_autoneg == 0)
2701 speed_capa |= ETH_LINK_SPEED_FIXED;
2707 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2709 struct hns3_adapter *hns = eth_dev->data->dev_private;
2710 struct hns3_hw *hw = &hns->hw;
2711 uint16_t queue_num = hw->tqps_num;
2714 * In interrupt mode, 'max_rx_queues' is set based on the number of
2715 * MSI-X interrupt resources of the hardware.
2717 if (hw->data->dev_conf.intr_conf.rxq == 1)
2718 queue_num = hw->intr_tqps_num;
2720 info->max_rx_queues = queue_num;
2721 info->max_tx_queues = hw->tqps_num;
2722 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2723 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2724 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2725 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2726 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2727 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2728 DEV_RX_OFFLOAD_TCP_CKSUM |
2729 DEV_RX_OFFLOAD_UDP_CKSUM |
2730 DEV_RX_OFFLOAD_SCTP_CKSUM |
2731 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2732 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2733 DEV_RX_OFFLOAD_KEEP_CRC |
2734 DEV_RX_OFFLOAD_SCATTER |
2735 DEV_RX_OFFLOAD_VLAN_STRIP |
2736 DEV_RX_OFFLOAD_VLAN_FILTER |
2737 DEV_RX_OFFLOAD_JUMBO_FRAME |
2738 DEV_RX_OFFLOAD_RSS_HASH |
2739 DEV_RX_OFFLOAD_TCP_LRO);
2740 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2741 DEV_TX_OFFLOAD_IPV4_CKSUM |
2742 DEV_TX_OFFLOAD_TCP_CKSUM |
2743 DEV_TX_OFFLOAD_UDP_CKSUM |
2744 DEV_TX_OFFLOAD_SCTP_CKSUM |
2745 DEV_TX_OFFLOAD_MULTI_SEGS |
2746 DEV_TX_OFFLOAD_TCP_TSO |
2747 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2748 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2749 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2750 DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2751 hns3_txvlan_cap_get(hw));
2753 if (hns3_dev_outer_udp_cksum_supported(hw))
2754 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2756 if (hns3_dev_indep_txrx_supported(hw))
2757 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2758 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2760 if (hns3_dev_ptp_supported(hw))
2761 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2763 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2764 .nb_max = HNS3_MAX_RING_DESC,
2765 .nb_min = HNS3_MIN_RING_DESC,
2766 .nb_align = HNS3_ALIGN_RING_DESC,
2769 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2770 .nb_max = HNS3_MAX_RING_DESC,
2771 .nb_min = HNS3_MIN_RING_DESC,
2772 .nb_align = HNS3_ALIGN_RING_DESC,
2773 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2774 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2777 info->speed_capa = hns3_get_speed_capa(hw);
2778 info->default_rxconf = (struct rte_eth_rxconf) {
2779 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2781 * If there are no available Rx buffer descriptors, incoming
2782 * packets are always dropped by hardware based on hns3 network
2788 info->default_txconf = (struct rte_eth_txconf) {
2789 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2793 info->reta_size = hw->rss_ind_tbl_size;
2794 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2795 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2797 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2798 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2799 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2800 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2801 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2802 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2808 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2811 struct hns3_adapter *hns = eth_dev->data->dev_private;
2812 struct hns3_hw *hw = &hns->hw;
2813 uint32_t version = hw->fw_version;
2816 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2817 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2818 HNS3_FW_VERSION_BYTE3_S),
2819 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2820 HNS3_FW_VERSION_BYTE2_S),
2821 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2822 HNS3_FW_VERSION_BYTE1_S),
2823 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2824 HNS3_FW_VERSION_BYTE0_S));
2828 ret += 1; /* add the size of '\0' */
2829 if (fw_size < (size_t)ret)
2836 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2838 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2841 (void)hns3_update_link_status(hw);
2843 ret = hns3_update_link_info(eth_dev);
2845 hw->mac.link_status = ETH_LINK_DOWN;
2851 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2852 struct rte_eth_link *new_link)
2854 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2855 struct hns3_mac *mac = &hw->mac;
2857 switch (mac->link_speed) {
2858 case ETH_SPEED_NUM_10M:
2859 case ETH_SPEED_NUM_100M:
2860 case ETH_SPEED_NUM_1G:
2861 case ETH_SPEED_NUM_10G:
2862 case ETH_SPEED_NUM_25G:
2863 case ETH_SPEED_NUM_40G:
2864 case ETH_SPEED_NUM_50G:
2865 case ETH_SPEED_NUM_100G:
2866 case ETH_SPEED_NUM_200G:
2867 if (mac->link_status)
2868 new_link->link_speed = mac->link_speed;
2871 if (mac->link_status)
2872 new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2876 if (!mac->link_status)
2877 new_link->link_speed = ETH_SPEED_NUM_NONE;
2879 new_link->link_duplex = mac->link_duplex;
2880 new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2881 new_link->link_autoneg = mac->link_autoneg;
2885 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2887 #define HNS3_LINK_CHECK_INTERVAL 100 /* 100ms */
2888 #define HNS3_MAX_LINK_CHECK_TIMES 20 /* 2s (100 * 20ms) in total */
2890 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2891 uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2892 struct hns3_mac *mac = &hw->mac;
2893 struct rte_eth_link new_link;
2896 /* When port is stopped, report link down. */
2897 if (eth_dev->data->dev_started == 0) {
2898 new_link.link_autoneg = mac->link_autoneg;
2899 new_link.link_duplex = mac->link_duplex;
2900 new_link.link_speed = ETH_SPEED_NUM_NONE;
2901 new_link.link_status = ETH_LINK_DOWN;
2906 ret = hns3_update_port_link_info(eth_dev);
2908 hns3_err(hw, "failed to get port link info, ret = %d.",
2913 if (!wait_to_complete || mac->link_status == ETH_LINK_UP)
2916 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2917 } while (retry_cnt--);
2919 memset(&new_link, 0, sizeof(new_link));
2920 hns3_setup_linkstatus(eth_dev, &new_link);
2923 return rte_eth_linkstatus_set(eth_dev, &new_link);
2927 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2929 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2930 struct hns3_pf *pf = &hns->pf;
2932 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2935 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2941 hns3_query_function_status(struct hns3_hw *hw)
2943 #define HNS3_QUERY_MAX_CNT 10
2944 #define HNS3_QUERY_SLEEP_MSCOEND 1
2945 struct hns3_func_status_cmd *req;
2946 struct hns3_cmd_desc desc;
2950 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2951 req = (struct hns3_func_status_cmd *)desc.data;
2954 ret = hns3_cmd_send(hw, &desc, 1);
2956 PMD_INIT_LOG(ERR, "query function status failed %d",
2961 /* Check pf reset is done */
2965 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2966 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2968 return hns3_parse_func_status(hw, req);
2972 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2974 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2975 struct hns3_pf *pf = &hns->pf;
2977 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2979 * The total_tqps_num obtained from firmware is maximum tqp
2980 * numbers of this port, which should be used for PF and VFs.
2981 * There is no need for pf to have so many tqp numbers in
2982 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2983 * coming from config file, is assigned to maximum queue number
2984 * for the PF of this port by user. So users can modify the
2985 * maximum queue number of PF according to their own application
2986 * scenarios, which is more flexible to use. In addition, many
2987 * memories can be saved due to allocating queue statistics
2988 * room according to the actual number of queues required. The
2989 * maximum queue number of PF for network engine with
2990 * revision_id greater than 0x30 is assigned by config file.
2992 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2993 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2994 "must be greater than 0.",
2995 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2999 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
3000 hw->total_tqps_num);
3003 * Due to the limitation on the number of PF interrupts
3004 * available, the maximum queue number assigned to PF on
3005 * the network engine with revision_id 0x21 is 64.
3007 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
3008 HNS3_MAX_TQP_NUM_HIP08_PF);
3015 hns3_query_pf_resource(struct hns3_hw *hw)
3017 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3018 struct hns3_pf *pf = &hns->pf;
3019 struct hns3_pf_res_cmd *req;
3020 struct hns3_cmd_desc desc;
3023 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
3024 ret = hns3_cmd_send(hw, &desc, 1);
3026 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
3030 req = (struct hns3_pf_res_cmd *)desc.data;
3031 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
3032 rte_le_to_cpu_16(req->ext_tqp_num);
3033 ret = hns3_get_pf_max_tqp_num(hw);
3037 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
3038 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
3040 if (req->tx_buf_size)
3042 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
3044 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
3046 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
3048 if (req->dv_buf_size)
3050 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3052 pf->dv_buf_size = HNS3_DEFAULT_DV;
3054 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3057 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3058 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3064 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3066 struct hns3_cfg_param_cmd *req;
3067 uint64_t mac_addr_tmp_high;
3068 uint8_t ext_rss_size_max;
3069 uint64_t mac_addr_tmp;
3072 req = (struct hns3_cfg_param_cmd *)desc[0].data;
3074 /* get the configuration */
3075 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3076 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3077 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3078 HNS3_CFG_TQP_DESC_N_M,
3079 HNS3_CFG_TQP_DESC_N_S);
3081 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3082 HNS3_CFG_PHY_ADDR_M,
3083 HNS3_CFG_PHY_ADDR_S);
3084 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3085 HNS3_CFG_MEDIA_TP_M,
3086 HNS3_CFG_MEDIA_TP_S);
3087 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3088 HNS3_CFG_RX_BUF_LEN_M,
3089 HNS3_CFG_RX_BUF_LEN_S);
3090 /* get mac address */
3091 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3092 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3093 HNS3_CFG_MAC_ADDR_H_M,
3094 HNS3_CFG_MAC_ADDR_H_S);
3096 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3098 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3099 HNS3_CFG_DEFAULT_SPEED_M,
3100 HNS3_CFG_DEFAULT_SPEED_S);
3101 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3102 HNS3_CFG_RSS_SIZE_M,
3103 HNS3_CFG_RSS_SIZE_S);
3105 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3106 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3108 req = (struct hns3_cfg_param_cmd *)desc[1].data;
3109 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3111 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3112 HNS3_CFG_SPEED_ABILITY_M,
3113 HNS3_CFG_SPEED_ABILITY_S);
3114 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3115 HNS3_CFG_UMV_TBL_SPACE_M,
3116 HNS3_CFG_UMV_TBL_SPACE_S);
3117 if (!cfg->umv_space)
3118 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3120 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3121 HNS3_CFG_EXT_RSS_SIZE_M,
3122 HNS3_CFG_EXT_RSS_SIZE_S);
3124 * Field ext_rss_size_max obtained from firmware will be more flexible
3125 * for future changes and expansions, which is an exponent of 2, instead
3126 * of reading out directly. If this field is not zero, hns3 PF PMD
3127 * driver uses it as rss_size_max under one TC. Device, whose revision
3128 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3129 * maximum number of queues supported under a TC through this field.
3131 if (ext_rss_size_max)
3132 cfg->rss_size_max = 1U << ext_rss_size_max;
3135 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3136 * @hw: pointer to struct hns3_hw
3137 * @hcfg: the config structure to be getted
3140 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3142 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3143 struct hns3_cfg_param_cmd *req;
3148 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3150 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3151 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3153 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3154 i * HNS3_CFG_RD_LEN_BYTES);
3155 /* Len should be divided by 4 when send to hardware */
3156 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3157 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3158 req->offset = rte_cpu_to_le_32(offset);
3161 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3163 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3167 hns3_parse_cfg(hcfg, desc);
3173 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3175 switch (speed_cmd) {
3176 case HNS3_CFG_SPEED_10M:
3177 *speed = ETH_SPEED_NUM_10M;
3179 case HNS3_CFG_SPEED_100M:
3180 *speed = ETH_SPEED_NUM_100M;
3182 case HNS3_CFG_SPEED_1G:
3183 *speed = ETH_SPEED_NUM_1G;
3185 case HNS3_CFG_SPEED_10G:
3186 *speed = ETH_SPEED_NUM_10G;
3188 case HNS3_CFG_SPEED_25G:
3189 *speed = ETH_SPEED_NUM_25G;
3191 case HNS3_CFG_SPEED_40G:
3192 *speed = ETH_SPEED_NUM_40G;
3194 case HNS3_CFG_SPEED_50G:
3195 *speed = ETH_SPEED_NUM_50G;
3197 case HNS3_CFG_SPEED_100G:
3198 *speed = ETH_SPEED_NUM_100G;
3200 case HNS3_CFG_SPEED_200G:
3201 *speed = ETH_SPEED_NUM_200G;
3211 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3213 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3214 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3215 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3216 hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3217 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3221 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3223 struct hns3_dev_specs_0_cmd *req0;
3225 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3227 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3228 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3229 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3230 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3231 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3235 hns3_check_dev_specifications(struct hns3_hw *hw)
3237 if (hw->rss_ind_tbl_size == 0 ||
3238 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3239 hns3_err(hw, "the size of hash lookup table configured (%u)"
3240 " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3241 HNS3_RSS_IND_TBL_SIZE_MAX);
3249 hns3_query_dev_specifications(struct hns3_hw *hw)
3251 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3255 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3256 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3258 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3260 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3262 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3266 hns3_parse_dev_specifications(hw, desc);
3268 return hns3_check_dev_specifications(hw);
3272 hns3_get_capability(struct hns3_hw *hw)
3274 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3275 struct rte_pci_device *pci_dev;
3276 struct hns3_pf *pf = &hns->pf;
3277 struct rte_eth_dev *eth_dev;
3282 eth_dev = &rte_eth_devices[hw->data->port_id];
3283 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3284 device_id = pci_dev->id.device_id;
3286 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3287 device_id == HNS3_DEV_ID_50GE_RDMA ||
3288 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3289 device_id == HNS3_DEV_ID_200G_RDMA)
3290 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3292 /* Get PCI revision id */
3293 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3294 HNS3_PCI_REVISION_ID);
3295 if (ret != HNS3_PCI_REVISION_ID_LEN) {
3296 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3300 hw->revision = revision;
3302 if (revision < PCI_REVISION_ID_HIP09_A) {
3303 hns3_set_default_dev_specifications(hw);
3304 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3305 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3306 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3307 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3308 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3309 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3310 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3311 hw->rss_info.ipv6_sctp_offload_supported = false;
3312 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3313 pf->support_multi_tc_pause = false;
3317 ret = hns3_query_dev_specifications(hw);
3320 "failed to query dev specifications, ret = %d",
3325 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3326 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3327 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3328 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3329 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3330 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3331 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3332 hw->rss_info.ipv6_sctp_offload_supported = true;
3333 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3334 pf->support_multi_tc_pause = true;
3340 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3344 switch (media_type) {
3345 case HNS3_MEDIA_TYPE_COPPER:
3346 if (!hns3_dev_copper_supported(hw)) {
3348 "Media type is copper, not supported.");
3354 case HNS3_MEDIA_TYPE_FIBER:
3357 case HNS3_MEDIA_TYPE_BACKPLANE:
3358 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3362 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3371 hns3_get_board_configuration(struct hns3_hw *hw)
3373 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3374 struct hns3_pf *pf = &hns->pf;
3375 struct hns3_cfg cfg;
3378 ret = hns3_get_board_cfg(hw, &cfg);
3380 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3384 ret = hns3_check_media_type(hw, cfg.media_type);
3388 hw->mac.media_type = cfg.media_type;
3389 hw->rss_size_max = cfg.rss_size_max;
3390 hw->rss_dis_flag = false;
3391 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3392 hw->mac.phy_addr = cfg.phy_addr;
3393 hw->mac.default_addr_setted = false;
3394 hw->num_tx_desc = cfg.tqp_desc_num;
3395 hw->num_rx_desc = cfg.tqp_desc_num;
3396 hw->dcb_info.num_pg = 1;
3397 hw->dcb_info.hw_pfc_map = 0;
3399 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3401 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3402 cfg.default_speed, ret);
3406 pf->tc_max = cfg.tc_num;
3407 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3408 PMD_INIT_LOG(WARNING,
3409 "Get TC num(%u) from flash, set TC num to 1",
3414 /* Dev does not support DCB */
3415 if (!hns3_dev_dcb_supported(hw)) {
3419 pf->pfc_max = pf->tc_max;
3421 hw->dcb_info.num_tc = 1;
3422 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3423 hw->tqps_num / hw->dcb_info.num_tc);
3424 hns3_set_bit(hw->hw_tc_map, 0, 1);
3425 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3427 pf->wanted_umv_size = cfg.umv_space;
3433 hns3_get_configuration(struct hns3_hw *hw)
3437 ret = hns3_query_function_status(hw);
3439 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3443 /* Get device capability */
3444 ret = hns3_get_capability(hw);
3446 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3450 /* Get pf resource */
3451 ret = hns3_query_pf_resource(hw);
3453 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3457 ret = hns3_get_board_configuration(hw);
3459 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3463 ret = hns3_query_dev_fec_info(hw);
3466 "failed to query FEC information, ret = %d", ret);
3472 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3473 uint16_t tqp_vid, bool is_pf)
3475 struct hns3_tqp_map_cmd *req;
3476 struct hns3_cmd_desc desc;
3479 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3481 req = (struct hns3_tqp_map_cmd *)desc.data;
3482 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3483 req->tqp_vf = func_id;
3484 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3486 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3487 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3489 ret = hns3_cmd_send(hw, &desc, 1);
3491 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3497 hns3_map_tqp(struct hns3_hw *hw)
3503 * In current version, VF is not supported when PF is driven by DPDK
3504 * driver, so we assign total tqps_num tqps allocated to this port
3507 for (i = 0; i < hw->total_tqps_num; i++) {
3508 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3517 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3519 struct hns3_config_mac_speed_dup_cmd *req;
3520 struct hns3_cmd_desc desc;
3523 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3525 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3527 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3530 case ETH_SPEED_NUM_10M:
3531 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3532 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3534 case ETH_SPEED_NUM_100M:
3535 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3536 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3538 case ETH_SPEED_NUM_1G:
3539 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3540 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3542 case ETH_SPEED_NUM_10G:
3543 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3544 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3546 case ETH_SPEED_NUM_25G:
3547 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3548 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3550 case ETH_SPEED_NUM_40G:
3551 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3552 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3554 case ETH_SPEED_NUM_50G:
3555 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3556 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3558 case ETH_SPEED_NUM_100G:
3559 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3560 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3562 case ETH_SPEED_NUM_200G:
3563 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3564 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3567 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3571 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3573 ret = hns3_cmd_send(hw, &desc, 1);
3575 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3581 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3583 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3584 struct hns3_pf *pf = &hns->pf;
3585 struct hns3_priv_buf *priv;
3586 uint32_t i, total_size;
3588 total_size = pf->pkt_buf_size;
3590 /* alloc tx buffer for all enabled tc */
3591 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3592 priv = &buf_alloc->priv_buf[i];
3594 if (hw->hw_tc_map & BIT(i)) {
3595 if (total_size < pf->tx_buf_size)
3598 priv->tx_buf_size = pf->tx_buf_size;
3600 priv->tx_buf_size = 0;
3602 total_size -= priv->tx_buf_size;
3609 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3611 /* TX buffer size is unit by 128 byte */
3612 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3613 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3614 struct hns3_tx_buff_alloc_cmd *req;
3615 struct hns3_cmd_desc desc;
3620 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3622 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3623 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3624 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3626 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3627 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3628 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3631 ret = hns3_cmd_send(hw, &desc, 1);
3633 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3639 hns3_get_tc_num(struct hns3_hw *hw)
3644 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3645 if (hw->hw_tc_map & BIT(i))
3651 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3653 struct hns3_priv_buf *priv;
3654 uint32_t rx_priv = 0;
3657 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3658 priv = &buf_alloc->priv_buf[i];
3660 rx_priv += priv->buf_size;
3666 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3668 uint32_t total_tx_size = 0;
3671 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3672 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3674 return total_tx_size;
3677 /* Get the number of pfc enabled TCs, which have private buffer */
3679 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3681 struct hns3_priv_buf *priv;
3685 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3686 priv = &buf_alloc->priv_buf[i];
3687 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3694 /* Get the number of pfc disabled TCs, which have private buffer */
3696 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3697 struct hns3_pkt_buf_alloc *buf_alloc)
3699 struct hns3_priv_buf *priv;
3703 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3704 priv = &buf_alloc->priv_buf[i];
3705 if (hw->hw_tc_map & BIT(i) &&
3706 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3714 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3717 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3718 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3719 struct hns3_pf *pf = &hns->pf;
3720 uint32_t shared_buf, aligned_mps;
3725 tc_num = hns3_get_tc_num(hw);
3726 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3728 if (hns3_dev_dcb_supported(hw))
3729 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3732 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3735 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3736 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3737 HNS3_BUF_SIZE_UNIT);
3739 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3740 if (rx_all < rx_priv + shared_std)
3743 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3744 buf_alloc->s_buf.buf_size = shared_buf;
3745 if (hns3_dev_dcb_supported(hw)) {
3746 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3747 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3748 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3749 HNS3_BUF_SIZE_UNIT);
3751 buf_alloc->s_buf.self.high =
3752 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3753 buf_alloc->s_buf.self.low = aligned_mps;
3756 if (hns3_dev_dcb_supported(hw)) {
3757 hi_thrd = shared_buf - pf->dv_buf_size;
3759 if (tc_num <= NEED_RESERVE_TC_NUM)
3760 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3764 hi_thrd = hi_thrd / tc_num;
3766 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3767 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3768 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3770 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3771 lo_thrd = aligned_mps;
3774 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3775 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3776 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3783 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3784 struct hns3_pkt_buf_alloc *buf_alloc)
3786 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3787 struct hns3_pf *pf = &hns->pf;
3788 struct hns3_priv_buf *priv;
3789 uint32_t aligned_mps;
3793 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3794 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3796 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3797 priv = &buf_alloc->priv_buf[i];
3804 if (!(hw->hw_tc_map & BIT(i)))
3808 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3809 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3810 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3811 HNS3_BUF_SIZE_UNIT);
3814 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3818 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3821 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3825 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3826 struct hns3_pkt_buf_alloc *buf_alloc)
3828 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3829 struct hns3_pf *pf = &hns->pf;
3830 struct hns3_priv_buf *priv;
3831 int no_pfc_priv_num;
3836 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3837 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3839 /* let the last to be cleared first */
3840 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3841 priv = &buf_alloc->priv_buf[i];
3842 mask = BIT((uint8_t)i);
3843 if (hw->hw_tc_map & mask &&
3844 !(hw->dcb_info.hw_pfc_map & mask)) {
3845 /* Clear the no pfc TC private buffer */
3853 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3854 no_pfc_priv_num == 0)
3858 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3862 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3863 struct hns3_pkt_buf_alloc *buf_alloc)
3865 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3866 struct hns3_pf *pf = &hns->pf;
3867 struct hns3_priv_buf *priv;
3873 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3874 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3876 /* let the last to be cleared first */
3877 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3878 priv = &buf_alloc->priv_buf[i];
3879 mask = BIT((uint8_t)i);
3880 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3881 /* Reduce the number of pfc TC with private buffer */
3888 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3893 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3897 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3898 struct hns3_pkt_buf_alloc *buf_alloc)
3900 #define COMPENSATE_BUFFER 0x3C00
3901 #define COMPENSATE_HALF_MPS_NUM 5
3902 #define PRIV_WL_GAP 0x1800
3903 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3904 struct hns3_pf *pf = &hns->pf;
3905 uint32_t tc_num = hns3_get_tc_num(hw);
3906 uint32_t half_mps = pf->mps >> 1;
3907 struct hns3_priv_buf *priv;
3908 uint32_t min_rx_priv;
3912 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3914 rx_priv = rx_priv / tc_num;
3916 if (tc_num <= NEED_RESERVE_TC_NUM)
3917 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3920 * Minimum value of private buffer in rx direction (min_rx_priv) is
3921 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3922 * buffer if rx_priv is greater than min_rx_priv.
3924 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3925 COMPENSATE_HALF_MPS_NUM * half_mps;
3926 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3927 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3928 if (rx_priv < min_rx_priv)
3931 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3932 priv = &buf_alloc->priv_buf[i];
3938 if (!(hw->hw_tc_map & BIT(i)))
3942 priv->buf_size = rx_priv;
3943 priv->wl.high = rx_priv - pf->dv_buf_size;
3944 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3947 buf_alloc->s_buf.buf_size = 0;
3953 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3954 * @hw: pointer to struct hns3_hw
3955 * @buf_alloc: pointer to buffer calculation data
3956 * @return: 0: calculate sucessful, negative: fail
3959 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3961 /* When DCB is not supported, rx private buffer is not allocated. */
3962 if (!hns3_dev_dcb_supported(hw)) {
3963 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3964 struct hns3_pf *pf = &hns->pf;
3965 uint32_t rx_all = pf->pkt_buf_size;
3967 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3968 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3975 * Try to allocate privated packet buffer for all TCs without share
3978 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3982 * Try to allocate privated packet buffer for all TCs with share
3985 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3989 * For different application scenes, the enabled port number, TC number
3990 * and no_drop TC number are different. In order to obtain the better
3991 * performance, software could allocate the buffer size and configure
3992 * the waterline by trying to decrease the private buffer size according
3993 * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
3996 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3999 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
4002 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
4009 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4011 struct hns3_rx_priv_buff_cmd *req;
4012 struct hns3_cmd_desc desc;
4017 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
4018 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
4020 /* Alloc private buffer TCs */
4021 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4022 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
4025 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
4026 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
4029 buf_size = buf_alloc->s_buf.buf_size;
4030 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
4031 (1 << HNS3_TC0_PRI_BUF_EN_B));
4033 ret = hns3_cmd_send(hw, &desc, 1);
4035 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
4041 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4043 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
4044 struct hns3_rx_priv_wl_buf *req;
4045 struct hns3_priv_buf *priv;
4046 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4050 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4051 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4053 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4055 /* The first descriptor set the NEXT bit to 1 */
4057 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4059 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4061 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4062 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4064 priv = &buf_alloc->priv_buf[idx];
4065 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4067 req->tc_wl[j].high |=
4068 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4069 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4071 req->tc_wl[j].low |=
4072 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4076 /* Send 2 descriptor at one time */
4077 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4079 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4085 hns3_common_thrd_config(struct hns3_hw *hw,
4086 struct hns3_pkt_buf_alloc *buf_alloc)
4088 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4089 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4090 struct hns3_rx_com_thrd *req;
4091 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4092 struct hns3_tc_thrd *tc;
4097 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4098 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4100 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4102 /* The first descriptor set the NEXT bit to 1 */
4104 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4106 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4108 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4109 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4110 tc = &s_buf->tc_thrd[tc_idx];
4112 req->com_thrd[j].high =
4113 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4114 req->com_thrd[j].high |=
4115 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4116 req->com_thrd[j].low =
4117 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4118 req->com_thrd[j].low |=
4119 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4123 /* Send 2 descriptors at one time */
4124 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4126 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4132 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4134 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4135 struct hns3_rx_com_wl *req;
4136 struct hns3_cmd_desc desc;
4139 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4141 req = (struct hns3_rx_com_wl *)desc.data;
4142 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4143 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4145 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4146 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4148 ret = hns3_cmd_send(hw, &desc, 1);
4150 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4156 hns3_buffer_alloc(struct hns3_hw *hw)
4158 struct hns3_pkt_buf_alloc pkt_buf;
4161 memset(&pkt_buf, 0, sizeof(pkt_buf));
4162 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4165 "could not calc tx buffer size for all TCs %d",
4170 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4172 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4176 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4179 "could not calc rx priv buffer size for all TCs %d",
4184 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4186 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4190 if (hns3_dev_dcb_supported(hw)) {
4191 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4194 "could not configure rx private waterline %d",
4199 ret = hns3_common_thrd_config(hw, &pkt_buf);
4202 "could not configure common threshold %d",
4208 ret = hns3_common_wl_config(hw, &pkt_buf);
4210 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4217 hns3_mac_init(struct hns3_hw *hw)
4219 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4220 struct hns3_mac *mac = &hw->mac;
4221 struct hns3_pf *pf = &hns->pf;
4224 pf->support_sfp_query = true;
4225 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4226 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4228 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4232 mac->link_status = ETH_LINK_DOWN;
4234 return hns3_config_mtu(hw, pf->mps);
4238 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4240 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
4241 #define HNS3_ETHERTYPE_ALREADY_ADD 1
4242 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
4243 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
4248 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4253 switch (resp_code) {
4254 case HNS3_ETHERTYPE_SUCCESS_ADD:
4255 case HNS3_ETHERTYPE_ALREADY_ADD:
4258 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4260 "add mac ethertype failed for manager table overflow.");
4261 return_status = -EIO;
4263 case HNS3_ETHERTYPE_KEY_CONFLICT:
4264 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4265 return_status = -EIO;
4269 "add mac ethertype failed for undefined, code=%u.",
4271 return_status = -EIO;
4275 return return_status;
4279 hns3_add_mgr_tbl(struct hns3_hw *hw,
4280 const struct hns3_mac_mgr_tbl_entry_cmd *req)
4282 struct hns3_cmd_desc desc;
4287 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4288 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4290 ret = hns3_cmd_send(hw, &desc, 1);
4293 "add mac ethertype failed for cmd_send, ret =%d.",
4298 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4299 retval = rte_le_to_cpu_16(desc.retval);
4301 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4305 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4306 int *table_item_num)
4308 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4311 * In current version, we add one item in management table as below:
4312 * 0x0180C200000E -- LLDP MC address
4315 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4316 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4317 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4318 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4319 tbl->i_port_bitmap = 0x1;
4320 *table_item_num = 1;
4324 hns3_init_mgr_tbl(struct hns3_hw *hw)
4326 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
4327 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4332 memset(mgr_table, 0, sizeof(mgr_table));
4333 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4334 for (i = 0; i < table_item_num; i++) {
4335 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4337 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4347 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4348 bool en_mc, bool en_bc, int vport_id)
4353 memset(param, 0, sizeof(struct hns3_promisc_param));
4355 param->enable = HNS3_PROMISC_EN_UC;
4357 param->enable |= HNS3_PROMISC_EN_MC;
4359 param->enable |= HNS3_PROMISC_EN_BC;
4360 param->vf_id = vport_id;
4364 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4366 struct hns3_promisc_cfg_cmd *req;
4367 struct hns3_cmd_desc desc;
4370 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4372 req = (struct hns3_promisc_cfg_cmd *)desc.data;
4373 req->vf_id = param->vf_id;
4374 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4375 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4377 ret = hns3_cmd_send(hw, &desc, 1);
4379 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4385 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4387 struct hns3_promisc_param param;
4388 bool en_bc_pmc = true;
4392 * In current version VF is not supported when PF is driven by DPDK
4393 * driver, just need to configure parameters for PF vport.
4395 vf_id = HNS3_PF_FUNC_ID;
4397 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4398 return hns3_cmd_set_promisc_mode(hw, ¶m);
4402 hns3_promisc_init(struct hns3_hw *hw)
4404 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4405 struct hns3_pf *pf = &hns->pf;
4406 struct hns3_promisc_param param;
4410 ret = hns3_set_promisc_mode(hw, false, false);
4412 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4417 * In current version VFs are not supported when PF is driven by DPDK
4418 * driver. After PF has been taken over by DPDK, the original VF will
4419 * be invalid. So, there is a possibility of entry residues. It should
4420 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4423 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4424 hns3_promisc_param_init(¶m, false, false, false, func_id);
4425 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4427 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4428 " ret = %d", func_id, ret);
4437 hns3_promisc_uninit(struct hns3_hw *hw)
4439 struct hns3_promisc_param param;
4443 func_id = HNS3_PF_FUNC_ID;
4446 * In current version VFs are not supported when PF is driven by
4447 * DPDK driver, and VFs' promisc mode status has been cleared during
4448 * init and their status will not change. So just clear PF's promisc
4449 * mode status during uninit.
4451 hns3_promisc_param_init(¶m, false, false, false, func_id);
4452 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4454 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4455 " uninit, ret = %d", ret);
4459 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4461 bool allmulti = dev->data->all_multicast ? true : false;
4462 struct hns3_adapter *hns = dev->data->dev_private;
4463 struct hns3_hw *hw = &hns->hw;
4468 rte_spinlock_lock(&hw->lock);
4469 ret = hns3_set_promisc_mode(hw, true, true);
4471 rte_spinlock_unlock(&hw->lock);
4472 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4478 * When promiscuous mode was enabled, disable the vlan filter to let
4479 * all packets coming in in the receiving direction.
4481 offloads = dev->data->dev_conf.rxmode.offloads;
4482 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4483 ret = hns3_enable_vlan_filter(hns, false);
4485 hns3_err(hw, "failed to enable promiscuous mode due to "
4486 "failure to disable vlan filter, ret = %d",
4488 err = hns3_set_promisc_mode(hw, false, allmulti);
4490 hns3_err(hw, "failed to restore promiscuous "
4491 "status after disable vlan filter "
4492 "failed during enabling promiscuous "
4493 "mode, ret = %d", ret);
4497 rte_spinlock_unlock(&hw->lock);
4503 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4505 bool allmulti = dev->data->all_multicast ? true : false;
4506 struct hns3_adapter *hns = dev->data->dev_private;
4507 struct hns3_hw *hw = &hns->hw;
4512 /* If now in all_multicast mode, must remain in all_multicast mode. */
4513 rte_spinlock_lock(&hw->lock);
4514 ret = hns3_set_promisc_mode(hw, false, allmulti);
4516 rte_spinlock_unlock(&hw->lock);
4517 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4521 /* when promiscuous mode was disabled, restore the vlan filter status */
4522 offloads = dev->data->dev_conf.rxmode.offloads;
4523 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4524 ret = hns3_enable_vlan_filter(hns, true);
4526 hns3_err(hw, "failed to disable promiscuous mode due to"
4527 " failure to restore vlan filter, ret = %d",
4529 err = hns3_set_promisc_mode(hw, true, true);
4531 hns3_err(hw, "failed to restore promiscuous "
4532 "status after enabling vlan filter "
4533 "failed during disabling promiscuous "
4534 "mode, ret = %d", ret);
4537 rte_spinlock_unlock(&hw->lock);
4543 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4545 struct hns3_adapter *hns = dev->data->dev_private;
4546 struct hns3_hw *hw = &hns->hw;
4549 if (dev->data->promiscuous)
4552 rte_spinlock_lock(&hw->lock);
4553 ret = hns3_set_promisc_mode(hw, false, true);
4554 rte_spinlock_unlock(&hw->lock);
4556 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4563 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4565 struct hns3_adapter *hns = dev->data->dev_private;
4566 struct hns3_hw *hw = &hns->hw;
4569 /* If now in promiscuous mode, must remain in all_multicast mode. */
4570 if (dev->data->promiscuous)
4573 rte_spinlock_lock(&hw->lock);
4574 ret = hns3_set_promisc_mode(hw, false, false);
4575 rte_spinlock_unlock(&hw->lock);
4577 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4584 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4586 struct hns3_hw *hw = &hns->hw;
4587 bool allmulti = hw->data->all_multicast ? true : false;
4590 if (hw->data->promiscuous) {
4591 ret = hns3_set_promisc_mode(hw, true, true);
4593 hns3_err(hw, "failed to restore promiscuous mode, "
4598 ret = hns3_set_promisc_mode(hw, false, allmulti);
4600 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4606 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4608 struct hns3_sfp_info_cmd *resp;
4609 struct hns3_cmd_desc desc;
4612 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4613 resp = (struct hns3_sfp_info_cmd *)desc.data;
4614 resp->query_type = HNS3_ACTIVE_QUERY;
4616 ret = hns3_cmd_send(hw, &desc, 1);
4617 if (ret == -EOPNOTSUPP) {
4618 hns3_warn(hw, "firmware does not support get SFP info,"
4622 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4627 * In some case, the speed of MAC obtained from firmware may be 0, it
4628 * shouldn't be set to mac->speed.
4630 if (!rte_le_to_cpu_32(resp->sfp_speed))
4633 mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4635 * if resp->supported_speed is 0, it means it's an old version
4636 * firmware, do not update these params.
4638 if (resp->supported_speed) {
4639 mac_info->query_type = HNS3_ACTIVE_QUERY;
4640 mac_info->supported_speed =
4641 rte_le_to_cpu_32(resp->supported_speed);
4642 mac_info->support_autoneg = resp->autoneg_ability;
4643 mac_info->link_autoneg = (resp->autoneg == 0) ? ETH_LINK_FIXED
4646 mac_info->query_type = HNS3_DEFAULT_QUERY;
4653 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4655 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4656 duplex = ETH_LINK_FULL_DUPLEX;
4662 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4664 struct hns3_mac *mac = &hw->mac;
4667 duplex = hns3_check_speed_dup(duplex, speed);
4668 if (mac->link_speed == speed && mac->link_duplex == duplex)
4671 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4675 ret = hns3_port_shaper_update(hw, speed);
4679 mac->link_speed = speed;
4680 mac->link_duplex = duplex;
4686 hns3_update_fiber_link_info(struct hns3_hw *hw)
4688 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4689 struct hns3_mac *mac = &hw->mac;
4690 struct hns3_mac mac_info;
4693 /* If firmware do not support get SFP/qSFP speed, return directly */
4694 if (!pf->support_sfp_query)
4697 memset(&mac_info, 0, sizeof(struct hns3_mac));
4698 ret = hns3_get_sfp_info(hw, &mac_info);
4699 if (ret == -EOPNOTSUPP) {
4700 pf->support_sfp_query = false;
4705 /* Do nothing if no SFP */
4706 if (mac_info.link_speed == ETH_SPEED_NUM_NONE)
4710 * If query_type is HNS3_ACTIVE_QUERY, it is no need
4711 * to reconfigure the speed of MAC. Otherwise, it indicates
4712 * that the current firmware only supports to obtain the
4713 * speed of the SFP, and the speed of MAC needs to reconfigure.
4715 mac->query_type = mac_info.query_type;
4716 if (mac->query_type == HNS3_ACTIVE_QUERY) {
4717 if (mac_info.link_speed != mac->link_speed) {
4718 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4723 mac->link_speed = mac_info.link_speed;
4724 mac->supported_speed = mac_info.supported_speed;
4725 mac->support_autoneg = mac_info.support_autoneg;
4726 mac->link_autoneg = mac_info.link_autoneg;
4731 /* Config full duplex for SFP */
4732 return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4733 ETH_LINK_FULL_DUPLEX);
4737 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4739 #define HNS3_PHY_SUPPORTED_SPEED_MASK 0x2f
4741 struct hns3_phy_params_bd0_cmd *req;
4744 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4745 mac->link_speed = rte_le_to_cpu_32(req->speed);
4746 mac->link_duplex = hns3_get_bit(req->duplex,
4747 HNS3_PHY_DUPLEX_CFG_B);
4748 mac->link_autoneg = hns3_get_bit(req->autoneg,
4749 HNS3_PHY_AUTONEG_CFG_B);
4750 mac->advertising = rte_le_to_cpu_32(req->advertising);
4751 mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4752 supported = rte_le_to_cpu_32(req->supported);
4753 mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4754 mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4758 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4760 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4764 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4765 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4767 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4769 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4771 ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4773 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4777 hns3_parse_copper_phy_params(desc, mac);
4783 hns3_update_copper_link_info(struct hns3_hw *hw)
4785 struct hns3_mac *mac = &hw->mac;
4786 struct hns3_mac mac_info;
4789 memset(&mac_info, 0, sizeof(struct hns3_mac));
4790 ret = hns3_get_copper_phy_params(hw, &mac_info);
4794 if (mac_info.link_speed != mac->link_speed) {
4795 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4800 mac->link_speed = mac_info.link_speed;
4801 mac->link_duplex = mac_info.link_duplex;
4802 mac->link_autoneg = mac_info.link_autoneg;
4803 mac->supported_speed = mac_info.supported_speed;
4804 mac->advertising = mac_info.advertising;
4805 mac->lp_advertising = mac_info.lp_advertising;
4806 mac->support_autoneg = mac_info.support_autoneg;
4812 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4814 struct hns3_adapter *hns = eth_dev->data->dev_private;
4815 struct hns3_hw *hw = &hns->hw;
4818 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4819 ret = hns3_update_copper_link_info(hw);
4820 else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4821 ret = hns3_update_fiber_link_info(hw);
4827 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4829 struct hns3_config_mac_mode_cmd *req;
4830 struct hns3_cmd_desc desc;
4831 uint32_t loop_en = 0;
4835 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4837 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4840 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4841 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4842 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4843 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4844 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4845 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4846 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4847 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4848 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4849 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4852 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4853 * when receiving frames. Otherwise, CRC will be stripped.
4855 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4856 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4858 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4859 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4860 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4861 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4862 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4864 ret = hns3_cmd_send(hw, &desc, 1);
4866 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4872 hns3_get_mac_link_status(struct hns3_hw *hw)
4874 struct hns3_link_status_cmd *req;
4875 struct hns3_cmd_desc desc;
4879 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4880 ret = hns3_cmd_send(hw, &desc, 1);
4882 hns3_err(hw, "get link status cmd failed %d", ret);
4883 return ETH_LINK_DOWN;
4886 req = (struct hns3_link_status_cmd *)desc.data;
4887 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4889 return !!link_status;
4893 hns3_update_link_status(struct hns3_hw *hw)
4897 state = hns3_get_mac_link_status(hw);
4898 if (state != hw->mac.link_status) {
4899 hw->mac.link_status = state;
4900 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4908 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4910 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4911 struct rte_eth_link new_link;
4915 hns3_update_port_link_info(dev);
4917 memset(&new_link, 0, sizeof(new_link));
4918 hns3_setup_linkstatus(dev, &new_link);
4920 ret = rte_eth_linkstatus_set(dev, &new_link);
4921 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4922 hns3_start_report_lse(dev);
4926 hns3_service_handler(void *param)
4928 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4929 struct hns3_adapter *hns = eth_dev->data->dev_private;
4930 struct hns3_hw *hw = &hns->hw;
4932 if (!hns3_is_reset_pending(hns))
4933 hns3_update_linkstatus_and_event(hw, true);
4935 hns3_warn(hw, "Cancel the query when reset is pending");
4937 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4941 hns3_init_hardware(struct hns3_adapter *hns)
4943 struct hns3_hw *hw = &hns->hw;
4946 ret = hns3_map_tqp(hw);
4948 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4952 ret = hns3_init_umv_space(hw);
4954 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4958 ret = hns3_mac_init(hw);
4960 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4964 ret = hns3_init_mgr_tbl(hw);
4966 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4970 ret = hns3_promisc_init(hw);
4972 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4977 ret = hns3_init_vlan_config(hns);
4979 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4983 ret = hns3_dcb_init(hw);
4985 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4989 ret = hns3_init_fd_config(hns);
4991 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4995 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4997 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
5001 ret = hns3_config_gro(hw, false);
5003 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
5008 * In the initialization clearing the all hardware mapping relationship
5009 * configurations between queues and interrupt vectors is needed, so
5010 * some error caused by the residual configurations, such as the
5011 * unexpected interrupt, can be avoid.
5013 ret = hns3_init_ring_with_vector(hw);
5015 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
5022 hns3_uninit_umv_space(hw);
5027 hns3_clear_hw(struct hns3_hw *hw)
5029 struct hns3_cmd_desc desc;
5032 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
5034 ret = hns3_cmd_send(hw, &desc, 1);
5035 if (ret && ret != -EOPNOTSUPP)
5042 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
5047 * The new firmware support report more hardware error types by
5048 * msix mode. These errors are defined as RAS errors in hardware
5049 * and belong to a different type from the MSI-x errors processed
5050 * by the network driver.
5052 * Network driver should open the new error report on initialization.
5054 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5055 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5056 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5060 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5062 struct hns3_mac *mac = &hw->mac;
5064 switch (mac->link_speed) {
5065 case ETH_SPEED_NUM_1G:
5066 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5067 case ETH_SPEED_NUM_10G:
5068 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5069 case ETH_SPEED_NUM_25G:
5070 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5071 case ETH_SPEED_NUM_40G:
5072 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5073 case ETH_SPEED_NUM_50G:
5074 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5075 case ETH_SPEED_NUM_100G:
5076 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5077 case ETH_SPEED_NUM_200G:
5078 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5080 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5086 * Validity of supported_speed for firber and copper media type can be
5087 * guaranteed by the following policy:
5089 * Although the initialization of the phy in the firmware may not be
5090 * completed, the firmware can guarantees that the supported_speed is
5093 * If the version of firmware supports the acitive query way of the
5094 * HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5095 * through it. If unsupported, use the SFP's speed as the value of the
5099 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5101 struct hns3_adapter *hns = eth_dev->data->dev_private;
5102 struct hns3_hw *hw = &hns->hw;
5103 struct hns3_mac *mac = &hw->mac;
5106 ret = hns3_update_link_info(eth_dev);
5110 if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5112 * Some firmware does not support the report of supported_speed,
5113 * and only report the effective speed of SFP. In this case, it
5114 * is necessary to use the SFP's speed as the supported_speed.
5116 if (mac->supported_speed == 0)
5117 mac->supported_speed =
5118 hns3_set_firber_default_support_speed(hw);
5125 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
5127 struct hns3_mac *mac = &hns->hw.mac;
5129 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
5130 hns->pf.support_fc_autoneg = true;
5135 * Flow control auto-negotiation requires the cooperation of the driver
5136 * and firmware. Currently, the optical port does not support flow
5137 * control auto-negotiation.
5139 hns->pf.support_fc_autoneg = false;
5143 hns3_init_pf(struct rte_eth_dev *eth_dev)
5145 struct rte_device *dev = eth_dev->device;
5146 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5147 struct hns3_adapter *hns = eth_dev->data->dev_private;
5148 struct hns3_hw *hw = &hns->hw;
5151 PMD_INIT_FUNC_TRACE();
5153 /* Get hardware io base address from pcie BAR2 IO space */
5154 hw->io_base = pci_dev->mem_resource[2].addr;
5156 /* Firmware command queue initialize */
5157 ret = hns3_cmd_init_queue(hw);
5159 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5160 goto err_cmd_init_queue;
5163 hns3_clear_all_event_cause(hw);
5165 /* Firmware command initialize */
5166 ret = hns3_cmd_init(hw);
5168 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5172 hns3_tx_push_init(eth_dev);
5175 * To ensure that the hardware environment is clean during
5176 * initialization, the driver actively clear the hardware environment
5177 * during initialization, including PF and corresponding VFs' vlan, mac,
5178 * flow table configurations, etc.
5180 ret = hns3_clear_hw(hw);
5182 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5186 /* Hardware statistics of imissed registers cleared. */
5187 ret = hns3_update_imissed_stats(hw, true);
5189 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5193 hns3_config_all_msix_error(hw, true);
5195 ret = rte_intr_callback_register(&pci_dev->intr_handle,
5196 hns3_interrupt_handler,
5199 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5200 goto err_intr_callback_register;
5203 ret = hns3_ptp_init(hw);
5205 goto err_get_config;
5207 /* Enable interrupt */
5208 rte_intr_enable(&pci_dev->intr_handle);
5209 hns3_pf_enable_irq0(hw);
5211 /* Get configuration */
5212 ret = hns3_get_configuration(hw);
5214 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5215 goto err_get_config;
5218 ret = hns3_tqp_stats_init(hw);
5220 goto err_get_config;
5222 ret = hns3_init_hardware(hns);
5224 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5228 /* Initialize flow director filter list & hash */
5229 ret = hns3_fdir_filter_init(hns);
5231 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5235 hns3_rss_set_default_args(hw);
5237 ret = hns3_enable_hw_error_intr(hns, true);
5239 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5241 goto err_enable_intr;
5244 ret = hns3_get_port_supported_speed(eth_dev);
5246 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5247 "by device, ret = %d.", ret);
5248 goto err_supported_speed;
5251 hns3_get_fc_autoneg_capability(hns);
5253 hns3_tm_conf_init(eth_dev);
5257 err_supported_speed:
5258 (void)hns3_enable_hw_error_intr(hns, false);
5260 hns3_fdir_filter_uninit(hns);
5262 hns3_uninit_umv_space(hw);
5264 hns3_tqp_stats_uninit(hw);
5266 hns3_pf_disable_irq0(hw);
5267 rte_intr_disable(&pci_dev->intr_handle);
5268 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5270 err_intr_callback_register:
5272 hns3_cmd_uninit(hw);
5273 hns3_cmd_destroy_queue(hw);
5281 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5283 struct hns3_adapter *hns = eth_dev->data->dev_private;
5284 struct rte_device *dev = eth_dev->device;
5285 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5286 struct hns3_hw *hw = &hns->hw;
5288 PMD_INIT_FUNC_TRACE();
5290 hns3_tm_conf_uninit(eth_dev);
5291 hns3_enable_hw_error_intr(hns, false);
5292 hns3_rss_uninit(hns);
5293 (void)hns3_config_gro(hw, false);
5294 hns3_promisc_uninit(hw);
5295 hns3_flow_uninit(eth_dev);
5296 hns3_fdir_filter_uninit(hns);
5297 hns3_uninit_umv_space(hw);
5298 hns3_tqp_stats_uninit(hw);
5299 hns3_config_mac_tnl_int(hw, false);
5300 hns3_pf_disable_irq0(hw);
5301 rte_intr_disable(&pci_dev->intr_handle);
5302 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5304 hns3_config_all_msix_error(hw, false);
5305 hns3_cmd_uninit(hw);
5306 hns3_cmd_destroy_queue(hw);
5311 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
5315 switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5316 case ETH_LINK_SPEED_10M:
5317 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
5319 case ETH_LINK_SPEED_10M_HD:
5320 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
5322 case ETH_LINK_SPEED_100M:
5323 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
5325 case ETH_LINK_SPEED_100M_HD:
5326 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
5328 case ETH_LINK_SPEED_1G:
5329 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
5340 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
5344 switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5345 case ETH_LINK_SPEED_1G:
5346 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
5348 case ETH_LINK_SPEED_10G:
5349 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
5351 case ETH_LINK_SPEED_25G:
5352 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
5354 case ETH_LINK_SPEED_40G:
5355 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
5357 case ETH_LINK_SPEED_50G:
5358 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
5360 case ETH_LINK_SPEED_100G:
5361 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
5363 case ETH_LINK_SPEED_200G:
5364 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
5375 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
5377 struct hns3_mac *mac = &hw->mac;
5378 uint32_t supported_speed = mac->supported_speed;
5379 uint32_t speed_bit = 0;
5381 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
5382 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
5383 else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
5384 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
5386 if (!(speed_bit & supported_speed)) {
5387 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
5395 static inline uint32_t
5396 hns3_get_link_speed(uint32_t link_speeds)
5398 uint32_t speed = ETH_SPEED_NUM_NONE;
5400 if (link_speeds & ETH_LINK_SPEED_10M ||
5401 link_speeds & ETH_LINK_SPEED_10M_HD)
5402 speed = ETH_SPEED_NUM_10M;
5403 if (link_speeds & ETH_LINK_SPEED_100M ||
5404 link_speeds & ETH_LINK_SPEED_100M_HD)
5405 speed = ETH_SPEED_NUM_100M;
5406 if (link_speeds & ETH_LINK_SPEED_1G)
5407 speed = ETH_SPEED_NUM_1G;
5408 if (link_speeds & ETH_LINK_SPEED_10G)
5409 speed = ETH_SPEED_NUM_10G;
5410 if (link_speeds & ETH_LINK_SPEED_25G)
5411 speed = ETH_SPEED_NUM_25G;
5412 if (link_speeds & ETH_LINK_SPEED_40G)
5413 speed = ETH_SPEED_NUM_40G;
5414 if (link_speeds & ETH_LINK_SPEED_50G)
5415 speed = ETH_SPEED_NUM_50G;
5416 if (link_speeds & ETH_LINK_SPEED_100G)
5417 speed = ETH_SPEED_NUM_100G;
5418 if (link_speeds & ETH_LINK_SPEED_200G)
5419 speed = ETH_SPEED_NUM_200G;
5425 hns3_get_link_duplex(uint32_t link_speeds)
5427 if ((link_speeds & ETH_LINK_SPEED_10M_HD) ||
5428 (link_speeds & ETH_LINK_SPEED_100M_HD))
5429 return ETH_LINK_HALF_DUPLEX;
5431 return ETH_LINK_FULL_DUPLEX;
5435 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5436 struct hns3_set_link_speed_cfg *cfg)
5438 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5439 struct hns3_phy_params_bd0_cmd *req;
5442 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5443 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5445 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5447 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5448 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5449 req->autoneg = cfg->autoneg;
5452 * The full speed capability is used to negotiate when
5453 * auto-negotiation is enabled.
5456 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5457 HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5458 HNS3_PHY_LINK_SPEED_100M_BIT |
5459 HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5460 HNS3_PHY_LINK_SPEED_1000M_BIT;
5462 req->speed = cfg->speed;
5463 req->duplex = cfg->duplex;
5466 return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5470 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5472 struct hns3_config_auto_neg_cmd *req;
5473 struct hns3_cmd_desc desc;
5477 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5479 req = (struct hns3_config_auto_neg_cmd *)desc.data;
5481 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5482 req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5484 ret = hns3_cmd_send(hw, &desc, 1);
5486 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5492 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5493 struct hns3_set_link_speed_cfg *cfg)
5497 if (hw->mac.support_autoneg) {
5498 ret = hns3_set_autoneg(hw, cfg->autoneg);
5500 hns3_err(hw, "failed to configure auto-negotiation.");
5505 * To enable auto-negotiation, we only need to open the switch
5506 * of auto-negotiation, then firmware sets all speed
5514 * Some hardware doesn't support auto-negotiation, but users may not
5515 * configure link_speeds (default 0), which means auto-negotiation.
5516 * In this case, a warning message need to be printed, instead of
5520 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
5524 return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
5528 hns3_set_port_link_speed(struct hns3_hw *hw,
5529 struct hns3_set_link_speed_cfg *cfg)
5533 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5534 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5535 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5540 ret = hns3_set_copper_port_link_speed(hw, cfg);
5542 hns3_err(hw, "failed to set copper port link speed,"
5546 } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5547 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5549 hns3_err(hw, "failed to set fiber port link speed,"
5559 hns3_apply_link_speed(struct hns3_hw *hw)
5561 struct rte_eth_conf *conf = &hw->data->dev_conf;
5562 struct hns3_set_link_speed_cfg cfg;
5564 memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5565 cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ?
5566 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
5567 if (cfg.autoneg != ETH_LINK_AUTONEG) {
5568 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5569 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5572 return hns3_set_port_link_speed(hw, &cfg);
5576 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5578 struct hns3_hw *hw = &hns->hw;
5581 ret = hns3_update_queue_map_configure(hns);
5583 hns3_err(hw, "failed to update queue mapping configuration, ret = %d",
5588 /* Note: hns3_tm_conf_update must be called after configuring DCB. */
5589 ret = hns3_tm_conf_update(hw);
5591 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5595 hns3_enable_rxd_adv_layout(hw);
5597 ret = hns3_init_queues(hns, reset_queue);
5599 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5603 ret = hns3_cfg_mac_mode(hw, true);
5605 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5606 goto err_config_mac_mode;
5609 ret = hns3_apply_link_speed(hw);
5611 goto err_set_link_speed;
5616 (void)hns3_cfg_mac_mode(hw, false);
5618 err_config_mac_mode:
5619 hns3_dev_release_mbufs(hns);
5621 * Here is exception handling, hns3_reset_all_tqps will have the
5622 * corresponding error message if it is handled incorrectly, so it is
5623 * not necessary to check hns3_reset_all_tqps return value, here keep
5624 * ret as the error code causing the exception.
5626 (void)hns3_reset_all_tqps(hns);
5631 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5633 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5634 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5635 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5636 uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5637 uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5638 uint32_t intr_vector;
5643 * hns3 needs a separate interrupt to be used as event interrupt which
5644 * could not be shared with task queue pair, so KERNEL drivers need
5645 * support multiple interrupt vectors.
5647 if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5648 !rte_intr_cap_multiple(intr_handle))
5651 rte_intr_disable(intr_handle);
5652 intr_vector = hw->used_rx_queues;
5653 /* creates event fd for each intr vector when MSIX is used */
5654 if (rte_intr_efd_enable(intr_handle, intr_vector))
5657 if (intr_handle->intr_vec == NULL) {
5658 intr_handle->intr_vec =
5659 rte_zmalloc("intr_vec",
5660 hw->used_rx_queues * sizeof(int), 0);
5661 if (intr_handle->intr_vec == NULL) {
5662 hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5663 hw->used_rx_queues);
5665 goto alloc_intr_vec_error;
5669 if (rte_intr_allow_others(intr_handle)) {
5670 vec = RTE_INTR_VEC_RXTX_OFFSET;
5671 base = RTE_INTR_VEC_RXTX_OFFSET;
5674 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5675 ret = hns3_bind_ring_with_vector(hw, vec, true,
5676 HNS3_RING_TYPE_RX, q_id);
5678 goto bind_vector_error;
5679 intr_handle->intr_vec[q_id] = vec;
5681 * If there are not enough efds (e.g. not enough interrupt),
5682 * remaining queues will be bond to the last interrupt.
5684 if (vec < base + intr_handle->nb_efd - 1)
5687 rte_intr_enable(intr_handle);
5691 rte_free(intr_handle->intr_vec);
5692 intr_handle->intr_vec = NULL;
5693 alloc_intr_vec_error:
5694 rte_intr_efd_disable(intr_handle);
5699 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5701 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5702 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5703 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5707 if (dev->data->dev_conf.intr_conf.rxq == 0)
5710 if (rte_intr_dp_is_en(intr_handle)) {
5711 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5712 ret = hns3_bind_ring_with_vector(hw,
5713 intr_handle->intr_vec[q_id], true,
5714 HNS3_RING_TYPE_RX, q_id);
5724 hns3_restore_filter(struct rte_eth_dev *dev)
5726 hns3_restore_rss_filter(dev);
5730 hns3_dev_start(struct rte_eth_dev *dev)
5732 struct hns3_adapter *hns = dev->data->dev_private;
5733 struct hns3_hw *hw = &hns->hw;
5736 PMD_INIT_FUNC_TRACE();
5737 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5740 rte_spinlock_lock(&hw->lock);
5741 hw->adapter_state = HNS3_NIC_STARTING;
5743 ret = hns3_do_start(hns, true);
5745 hw->adapter_state = HNS3_NIC_CONFIGURED;
5746 rte_spinlock_unlock(&hw->lock);
5749 ret = hns3_map_rx_interrupt(dev);
5751 goto map_rx_inter_err;
5754 * There are three register used to control the status of a TQP
5755 * (contains a pair of Tx queue and Rx queue) in the new version network
5756 * engine. One is used to control the enabling of Tx queue, the other is
5757 * used to control the enabling of Rx queue, and the last is the master
5758 * switch used to control the enabling of the tqp. The Tx register and
5759 * TQP register must be enabled at the same time to enable a Tx queue.
5760 * The same applies to the Rx queue. For the older network engine, this
5761 * function only refresh the enabled flag, and it is used to update the
5762 * status of queue in the dpdk framework.
5764 ret = hns3_start_all_txqs(dev);
5766 goto map_rx_inter_err;
5768 ret = hns3_start_all_rxqs(dev);
5770 goto start_all_rxqs_fail;
5772 hw->adapter_state = HNS3_NIC_STARTED;
5773 rte_spinlock_unlock(&hw->lock);
5775 hns3_rx_scattered_calc(dev);
5776 hns3_set_rxtx_function(dev);
5777 hns3_mp_req_start_rxtx(dev);
5779 hns3_restore_filter(dev);
5781 /* Enable interrupt of all rx queues before enabling queues */
5782 hns3_dev_all_rx_queue_intr_enable(hw, true);
5785 * After finished the initialization, enable tqps to receive/transmit
5786 * packets and refresh all queue status.
5788 hns3_start_tqps(hw);
5790 hns3_tm_dev_start_proc(hw);
5792 if (dev->data->dev_conf.intr_conf.lsc != 0)
5793 hns3_dev_link_update(dev, 0);
5794 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5796 hns3_info(hw, "hns3 dev start successful!");
5800 start_all_rxqs_fail:
5801 hns3_stop_all_txqs(dev);
5803 (void)hns3_do_stop(hns);
5804 hw->adapter_state = HNS3_NIC_CONFIGURED;
5805 rte_spinlock_unlock(&hw->lock);
5811 hns3_do_stop(struct hns3_adapter *hns)
5813 struct hns3_hw *hw = &hns->hw;
5817 * The "hns3_do_stop" function will also be called by .stop_service to
5818 * prepare reset. At the time of global or IMP reset, the command cannot
5819 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5820 * accessed during the reset process. So the mbuf can not be released
5821 * during reset and is required to be released after the reset is
5824 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)
5825 hns3_dev_release_mbufs(hns);
5827 ret = hns3_cfg_mac_mode(hw, false);
5830 hw->mac.link_status = ETH_LINK_DOWN;
5832 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5833 hns3_configure_all_mac_addr(hns, true);
5834 ret = hns3_reset_all_tqps(hns);
5836 hns3_err(hw, "failed to reset all queues ret = %d.",
5841 hw->mac.default_addr_setted = false;
5846 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5848 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5849 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5850 struct hns3_adapter *hns = dev->data->dev_private;
5851 struct hns3_hw *hw = &hns->hw;
5852 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5853 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5856 if (dev->data->dev_conf.intr_conf.rxq == 0)
5859 /* unmap the ring with vector */
5860 if (rte_intr_allow_others(intr_handle)) {
5861 vec = RTE_INTR_VEC_RXTX_OFFSET;
5862 base = RTE_INTR_VEC_RXTX_OFFSET;
5864 if (rte_intr_dp_is_en(intr_handle)) {
5865 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5866 (void)hns3_bind_ring_with_vector(hw, vec, false,
5869 if (vec < base + intr_handle->nb_efd - 1)
5873 /* Clean datapath event and queue/vec mapping */
5874 rte_intr_efd_disable(intr_handle);
5875 if (intr_handle->intr_vec) {
5876 rte_free(intr_handle->intr_vec);
5877 intr_handle->intr_vec = NULL;
5882 hns3_dev_stop(struct rte_eth_dev *dev)
5884 struct hns3_adapter *hns = dev->data->dev_private;
5885 struct hns3_hw *hw = &hns->hw;
5887 PMD_INIT_FUNC_TRACE();
5888 dev->data->dev_started = 0;
5890 hw->adapter_state = HNS3_NIC_STOPPING;
5891 hns3_set_rxtx_function(dev);
5893 /* Disable datapath on secondary process. */
5894 hns3_mp_req_stop_rxtx(dev);
5895 /* Prevent crashes when queues are still in use. */
5896 rte_delay_ms(hw->cfg_max_queues);
5898 rte_spinlock_lock(&hw->lock);
5899 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5900 hns3_tm_dev_stop_proc(hw);
5901 hns3_config_mac_tnl_int(hw, false);
5904 hns3_unmap_rx_interrupt(dev);
5905 hw->adapter_state = HNS3_NIC_CONFIGURED;
5907 hns3_rx_scattered_reset(dev);
5908 rte_eal_alarm_cancel(hns3_service_handler, dev);
5909 hns3_stop_report_lse(dev);
5910 rte_spinlock_unlock(&hw->lock);
5916 hns3_dev_close(struct rte_eth_dev *eth_dev)
5918 struct hns3_adapter *hns = eth_dev->data->dev_private;
5919 struct hns3_hw *hw = &hns->hw;
5922 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5925 if (hw->adapter_state == HNS3_NIC_STARTED)
5926 ret = hns3_dev_stop(eth_dev);
5928 hw->adapter_state = HNS3_NIC_CLOSING;
5929 hns3_reset_abort(hns);
5930 hw->adapter_state = HNS3_NIC_CLOSED;
5932 hns3_configure_all_mc_mac_addr(hns, true);
5933 hns3_remove_all_vlan_table(hns);
5934 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5935 hns3_uninit_pf(eth_dev);
5936 hns3_free_all_queues(eth_dev);
5937 rte_free(hw->reset.wait_data);
5938 hns3_mp_uninit_primary();
5939 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5945 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5948 struct hns3_mac *mac = &hw->mac;
5949 uint32_t advertising = mac->advertising;
5950 uint32_t lp_advertising = mac->lp_advertising;
5954 if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5957 } else if (advertising & lp_advertising &
5958 HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5959 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5961 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5966 static enum hns3_fc_mode
5967 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5969 enum hns3_fc_mode current_mode;
5970 bool rx_pause = false;
5971 bool tx_pause = false;
5973 switch (hw->mac.media_type) {
5974 case HNS3_MEDIA_TYPE_COPPER:
5975 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5979 * Flow control auto-negotiation is not supported for fiber and
5980 * backpalne media type.
5982 case HNS3_MEDIA_TYPE_FIBER:
5983 case HNS3_MEDIA_TYPE_BACKPLANE:
5984 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
5985 current_mode = hw->requested_fc_mode;
5988 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
5989 hw->mac.media_type);
5990 current_mode = HNS3_FC_NONE;
5994 if (rx_pause && tx_pause)
5995 current_mode = HNS3_FC_FULL;
5997 current_mode = HNS3_FC_RX_PAUSE;
5999 current_mode = HNS3_FC_TX_PAUSE;
6001 current_mode = HNS3_FC_NONE;
6004 return current_mode;
6007 static enum hns3_fc_mode
6008 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
6010 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6011 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6012 struct hns3_mac *mac = &hw->mac;
6015 * When the flow control mode is obtained, the device may not complete
6016 * auto-negotiation. It is necessary to wait for link establishment.
6018 (void)hns3_dev_link_update(dev, 1);
6021 * If the link auto-negotiation of the nic is disabled, or the flow
6022 * control auto-negotiation is not supported, the forced flow control
6025 if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
6026 return hw->requested_fc_mode;
6028 return hns3_get_autoneg_fc_mode(hw);
6032 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6034 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6035 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6036 enum hns3_fc_mode current_mode;
6038 current_mode = hns3_get_current_fc_mode(dev);
6039 switch (current_mode) {
6041 fc_conf->mode = RTE_FC_FULL;
6043 case HNS3_FC_TX_PAUSE:
6044 fc_conf->mode = RTE_FC_TX_PAUSE;
6046 case HNS3_FC_RX_PAUSE:
6047 fc_conf->mode = RTE_FC_RX_PAUSE;
6051 fc_conf->mode = RTE_FC_NONE;
6055 fc_conf->pause_time = pf->pause_time;
6056 fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
6062 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
6064 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
6066 if (!pf->support_fc_autoneg) {
6068 hns3_err(hw, "unsupported fc auto-negotiation setting.");
6073 * Flow control auto-negotiation of the NIC is not supported,
6074 * but other auto-negotiation features may be supported.
6076 if (autoneg != hw->mac.link_autoneg) {
6077 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
6085 * If flow control auto-negotiation of the NIC is supported, all
6086 * auto-negotiation features are supported.
6088 if (autoneg != hw->mac.link_autoneg) {
6089 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
6097 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6099 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6100 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6103 if (fc_conf->high_water || fc_conf->low_water ||
6104 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
6105 hns3_err(hw, "Unsupported flow control settings specified, "
6106 "high_water(%u), low_water(%u), send_xon(%u) and "
6107 "mac_ctrl_frame_fwd(%u) must be set to '0'",
6108 fc_conf->high_water, fc_conf->low_water,
6109 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
6113 ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
6117 if (!fc_conf->pause_time) {
6118 hns3_err(hw, "Invalid pause time %u setting.",
6119 fc_conf->pause_time);
6123 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6124 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
6125 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
6126 "current_fc_status = %d", hw->current_fc_status);
6130 if (hw->num_tc > 1 && !pf->support_multi_tc_pause) {
6131 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
6135 rte_spinlock_lock(&hw->lock);
6136 ret = hns3_fc_enable(dev, fc_conf);
6137 rte_spinlock_unlock(&hw->lock);
6143 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
6144 struct rte_eth_pfc_conf *pfc_conf)
6146 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6149 if (!hns3_dev_dcb_supported(hw)) {
6150 hns3_err(hw, "This port does not support dcb configurations.");
6154 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
6155 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
6156 hns3_err(hw, "Unsupported flow control settings specified, "
6157 "high_water(%u), low_water(%u), send_xon(%u) and "
6158 "mac_ctrl_frame_fwd(%u) must be set to '0'",
6159 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
6160 pfc_conf->fc.send_xon,
6161 pfc_conf->fc.mac_ctrl_frame_fwd);
6164 if (pfc_conf->fc.autoneg) {
6165 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
6168 if (pfc_conf->fc.pause_time == 0) {
6169 hns3_err(hw, "Invalid pause time %u setting.",
6170 pfc_conf->fc.pause_time);
6174 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6175 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
6176 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
6177 "current_fc_status = %d", hw->current_fc_status);
6181 rte_spinlock_lock(&hw->lock);
6182 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
6183 rte_spinlock_unlock(&hw->lock);
6189 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
6191 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6192 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6193 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
6196 rte_spinlock_lock(&hw->lock);
6197 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
6198 dcb_info->nb_tcs = pf->local_max_tc;
6200 dcb_info->nb_tcs = 1;
6202 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
6203 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
6204 for (i = 0; i < dcb_info->nb_tcs; i++)
6205 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
6207 for (i = 0; i < hw->num_tc; i++) {
6208 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
6209 dcb_info->tc_queue.tc_txq[0][i].base =
6210 hw->tc_queue[i].tqp_offset;
6211 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
6212 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
6213 hw->tc_queue[i].tqp_count;
6215 rte_spinlock_unlock(&hw->lock);
6221 hns3_reinit_dev(struct hns3_adapter *hns)
6223 struct hns3_hw *hw = &hns->hw;
6226 ret = hns3_cmd_init(hw);
6228 hns3_err(hw, "Failed to init cmd: %d", ret);
6232 ret = hns3_reset_all_tqps(hns);
6234 hns3_err(hw, "Failed to reset all queues: %d", ret);
6238 ret = hns3_init_hardware(hns);
6240 hns3_err(hw, "Failed to init hardware: %d", ret);
6244 ret = hns3_enable_hw_error_intr(hns, true);
6246 hns3_err(hw, "fail to enable hw error interrupts: %d",
6250 hns3_info(hw, "Reset done, driver initialization finished.");
6256 is_pf_reset_done(struct hns3_hw *hw)
6258 uint32_t val, reg, reg_bit;
6260 switch (hw->reset.level) {
6261 case HNS3_IMP_RESET:
6262 reg = HNS3_GLOBAL_RESET_REG;
6263 reg_bit = HNS3_IMP_RESET_BIT;
6265 case HNS3_GLOBAL_RESET:
6266 reg = HNS3_GLOBAL_RESET_REG;
6267 reg_bit = HNS3_GLOBAL_RESET_BIT;
6269 case HNS3_FUNC_RESET:
6270 reg = HNS3_FUN_RST_ING;
6271 reg_bit = HNS3_FUN_RST_ING_B;
6273 case HNS3_FLR_RESET:
6275 hns3_err(hw, "Wait for unsupported reset level: %d",
6279 val = hns3_read_dev(hw, reg);
6280 if (hns3_get_bit(val, reg_bit))
6287 hns3_is_reset_pending(struct hns3_adapter *hns)
6289 struct hns3_hw *hw = &hns->hw;
6290 enum hns3_reset_level reset;
6292 hns3_check_event_cause(hns, NULL);
6293 reset = hns3_get_reset_level(hns, &hw->reset.pending);
6294 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6295 hw->reset.level < reset) {
6296 hns3_warn(hw, "High level reset %d is pending", reset);
6299 reset = hns3_get_reset_level(hns, &hw->reset.request);
6300 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6301 hw->reset.level < reset) {
6302 hns3_warn(hw, "High level reset %d is request", reset);
6309 hns3_wait_hardware_ready(struct hns3_adapter *hns)
6311 struct hns3_hw *hw = &hns->hw;
6312 struct hns3_wait_data *wait_data = hw->reset.wait_data;
6315 if (wait_data->result == HNS3_WAIT_SUCCESS)
6317 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
6318 hns3_clock_gettime(&tv);
6319 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
6320 tv.tv_sec, tv.tv_usec);
6322 } else if (wait_data->result == HNS3_WAIT_REQUEST)
6325 wait_data->hns = hns;
6326 wait_data->check_completion = is_pf_reset_done;
6327 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
6328 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms();
6329 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
6330 wait_data->count = HNS3_RESET_WAIT_CNT;
6331 wait_data->result = HNS3_WAIT_REQUEST;
6332 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
6337 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
6339 struct hns3_cmd_desc desc;
6340 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6342 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6343 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6344 req->fun_reset_vfid = func_id;
6346 return hns3_cmd_send(hw, &desc, 1);
6350 hns3_imp_reset_cmd(struct hns3_hw *hw)
6352 struct hns3_cmd_desc desc;
6354 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6355 desc.data[0] = 0xeedd;
6357 return hns3_cmd_send(hw, &desc, 1);
6361 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6363 struct hns3_hw *hw = &hns->hw;
6367 hns3_clock_gettime(&tv);
6368 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6369 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6370 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6371 tv.tv_sec, tv.tv_usec);
6375 switch (reset_level) {
6376 case HNS3_IMP_RESET:
6377 hns3_imp_reset_cmd(hw);
6378 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6379 tv.tv_sec, tv.tv_usec);
6381 case HNS3_GLOBAL_RESET:
6382 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6383 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6384 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6385 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6386 tv.tv_sec, tv.tv_usec);
6388 case HNS3_FUNC_RESET:
6389 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6390 tv.tv_sec, tv.tv_usec);
6391 /* schedule again to check later */
6392 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6393 hns3_schedule_reset(hns);
6396 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6399 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6402 static enum hns3_reset_level
6403 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6405 struct hns3_hw *hw = &hns->hw;
6406 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6408 /* Return the highest priority reset level amongst all */
6409 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6410 reset_level = HNS3_IMP_RESET;
6411 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6412 reset_level = HNS3_GLOBAL_RESET;
6413 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6414 reset_level = HNS3_FUNC_RESET;
6415 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6416 reset_level = HNS3_FLR_RESET;
6418 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6419 return HNS3_NONE_RESET;
6425 hns3_record_imp_error(struct hns3_adapter *hns)
6427 struct hns3_hw *hw = &hns->hw;
6430 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6431 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6432 hns3_warn(hw, "Detected IMP RD poison!");
6433 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6434 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6437 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6438 hns3_warn(hw, "Detected IMP CMDQ error!");
6439 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6440 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6445 hns3_prepare_reset(struct hns3_adapter *hns)
6447 struct hns3_hw *hw = &hns->hw;
6451 switch (hw->reset.level) {
6452 case HNS3_FUNC_RESET:
6453 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6458 * After performaning pf reset, it is not necessary to do the
6459 * mailbox handling or send any command to firmware, because
6460 * any mailbox handling or command to firmware is only valid
6461 * after hns3_cmd_init is called.
6463 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6464 hw->reset.stats.request_cnt++;
6466 case HNS3_IMP_RESET:
6467 hns3_record_imp_error(hns);
6468 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6469 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6470 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6479 hns3_set_rst_done(struct hns3_hw *hw)
6481 struct hns3_pf_rst_done_cmd *req;
6482 struct hns3_cmd_desc desc;
6484 req = (struct hns3_pf_rst_done_cmd *)desc.data;
6485 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6486 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6487 return hns3_cmd_send(hw, &desc, 1);
6491 hns3_stop_service(struct hns3_adapter *hns)
6493 struct hns3_hw *hw = &hns->hw;
6494 struct rte_eth_dev *eth_dev;
6496 eth_dev = &rte_eth_devices[hw->data->port_id];
6497 hw->mac.link_status = ETH_LINK_DOWN;
6498 if (hw->adapter_state == HNS3_NIC_STARTED) {
6499 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6500 hns3_update_linkstatus_and_event(hw, false);
6503 hns3_set_rxtx_function(eth_dev);
6505 /* Disable datapath on secondary process. */
6506 hns3_mp_req_stop_rxtx(eth_dev);
6507 rte_delay_ms(hw->cfg_max_queues);
6509 rte_spinlock_lock(&hw->lock);
6510 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6511 hw->adapter_state == HNS3_NIC_STOPPING) {
6512 hns3_enable_all_queues(hw, false);
6514 hw->reset.mbuf_deferred_free = true;
6516 hw->reset.mbuf_deferred_free = false;
6519 * It is cumbersome for hardware to pick-and-choose entries for deletion
6520 * from table space. Hence, for function reset software intervention is
6521 * required to delete the entries
6523 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6524 hns3_configure_all_mc_mac_addr(hns, true);
6525 rte_spinlock_unlock(&hw->lock);
6531 hns3_start_service(struct hns3_adapter *hns)
6533 struct hns3_hw *hw = &hns->hw;
6534 struct rte_eth_dev *eth_dev;
6536 if (hw->reset.level == HNS3_IMP_RESET ||
6537 hw->reset.level == HNS3_GLOBAL_RESET)
6538 hns3_set_rst_done(hw);
6539 eth_dev = &rte_eth_devices[hw->data->port_id];
6540 hns3_set_rxtx_function(eth_dev);
6541 hns3_mp_req_start_rxtx(eth_dev);
6542 if (hw->adapter_state == HNS3_NIC_STARTED) {
6544 * This API parent function already hold the hns3_hw.lock, the
6545 * hns3_service_handler may report lse, in bonding application
6546 * it will call driver's ops which may acquire the hns3_hw.lock
6547 * again, thus lead to deadlock.
6548 * We defer calls hns3_service_handler to avoid the deadlock.
6550 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6551 hns3_service_handler, eth_dev);
6553 /* Enable interrupt of all rx queues before enabling queues */
6554 hns3_dev_all_rx_queue_intr_enable(hw, true);
6556 * Enable state of each rxq and txq will be recovered after
6557 * reset, so we need to restore them before enable all tqps;
6559 hns3_restore_tqp_enable_state(hw);
6561 * When finished the initialization, enable queues to receive
6562 * and transmit packets.
6564 hns3_enable_all_queues(hw, true);
6571 hns3_restore_conf(struct hns3_adapter *hns)
6573 struct hns3_hw *hw = &hns->hw;
6576 ret = hns3_configure_all_mac_addr(hns, false);
6580 ret = hns3_configure_all_mc_mac_addr(hns, false);
6584 ret = hns3_dev_promisc_restore(hns);
6588 ret = hns3_restore_vlan_table(hns);
6592 ret = hns3_restore_vlan_conf(hns);
6596 ret = hns3_restore_all_fdir_filter(hns);
6600 ret = hns3_restore_ptp(hns);
6604 ret = hns3_restore_rx_interrupt(hw);
6608 ret = hns3_restore_gro_conf(hw);
6612 ret = hns3_restore_fec(hw);
6616 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6617 ret = hns3_do_start(hns, false);
6620 hns3_info(hw, "hns3 dev restart successful!");
6621 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6622 hw->adapter_state = HNS3_NIC_CONFIGURED;
6626 hns3_configure_all_mc_mac_addr(hns, true);
6628 hns3_configure_all_mac_addr(hns, true);
6633 hns3_reset_service(void *param)
6635 struct hns3_adapter *hns = (struct hns3_adapter *)param;
6636 struct hns3_hw *hw = &hns->hw;
6637 enum hns3_reset_level reset_level;
6638 struct timeval tv_delta;
6639 struct timeval tv_start;
6645 * The interrupt is not triggered within the delay time.
6646 * The interrupt may have been lost. It is necessary to handle
6647 * the interrupt to recover from the error.
6649 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6650 SCHEDULE_DEFERRED) {
6651 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6653 hns3_err(hw, "Handling interrupts in delayed tasks");
6654 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6655 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6656 if (reset_level == HNS3_NONE_RESET) {
6657 hns3_err(hw, "No reset level is set, try IMP reset");
6658 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6661 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6664 * Check if there is any ongoing reset in the hardware. This status can
6665 * be checked from reset_pending. If there is then, we need to wait for
6666 * hardware to complete reset.
6667 * a. If we are able to figure out in reasonable time that hardware
6668 * has fully resetted then, we can proceed with driver, client
6670 * b. else, we can come back later to check this status so re-sched
6673 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6674 if (reset_level != HNS3_NONE_RESET) {
6675 hns3_clock_gettime(&tv_start);
6676 ret = hns3_reset_process(hns, reset_level);
6677 hns3_clock_gettime(&tv);
6678 timersub(&tv, &tv_start, &tv_delta);
6679 msec = hns3_clock_calctime_ms(&tv_delta);
6680 if (msec > HNS3_RESET_PROCESS_MS)
6681 hns3_err(hw, "%d handle long time delta %" PRIu64
6682 " ms time=%ld.%.6ld",
6683 hw->reset.level, msec,
6684 tv.tv_sec, tv.tv_usec);
6689 /* Check if we got any *new* reset requests to be honored */
6690 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6691 if (reset_level != HNS3_NONE_RESET)
6692 hns3_msix_process(hns, reset_level);
6696 hns3_get_speed_capa_num(uint16_t device_id)
6700 switch (device_id) {
6701 case HNS3_DEV_ID_25GE:
6702 case HNS3_DEV_ID_25GE_RDMA:
6705 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6706 case HNS3_DEV_ID_200G_RDMA:
6718 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6721 switch (device_id) {
6722 case HNS3_DEV_ID_25GE:
6724 case HNS3_DEV_ID_25GE_RDMA:
6725 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6726 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6728 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6729 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6730 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6732 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6733 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6734 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6736 case HNS3_DEV_ID_200G_RDMA:
6737 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6738 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6748 hns3_fec_get_capability(struct rte_eth_dev *dev,
6749 struct rte_eth_fec_capa *speed_fec_capa,
6752 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6753 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6754 uint16_t device_id = pci_dev->id.device_id;
6755 unsigned int capa_num;
6758 capa_num = hns3_get_speed_capa_num(device_id);
6759 if (capa_num == 0) {
6760 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6765 if (speed_fec_capa == NULL || num < capa_num)
6768 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6776 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6778 struct hns3_config_fec_cmd *req;
6779 struct hns3_cmd_desc desc;
6783 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6784 * in device of link speed
6787 if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6792 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6793 req = (struct hns3_config_fec_cmd *)desc.data;
6794 ret = hns3_cmd_send(hw, &desc, 1);
6796 hns3_err(hw, "get current fec auto state failed, ret = %d",
6801 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6806 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6808 struct hns3_sfp_info_cmd *resp;
6809 uint32_t tmp_fec_capa;
6811 struct hns3_cmd_desc desc;
6815 * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6816 * configured FEC mode is returned.
6817 * If link is up, current FEC mode is returned.
6819 if (hw->mac.link_status == ETH_LINK_DOWN) {
6820 ret = get_current_fec_auto_state(hw, &auto_state);
6824 if (auto_state == 0x1) {
6825 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6830 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6831 resp = (struct hns3_sfp_info_cmd *)desc.data;
6832 resp->query_type = HNS3_ACTIVE_QUERY;
6834 ret = hns3_cmd_send(hw, &desc, 1);
6835 if (ret == -EOPNOTSUPP) {
6836 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6839 hns3_err(hw, "get FEC failed, ret = %d", ret);
6844 * FEC mode order defined in hns3 hardware is inconsistend with
6845 * that defined in the ethdev library. So the sequence needs
6848 switch (resp->active_fec) {
6849 case HNS3_HW_FEC_MODE_NOFEC:
6850 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6852 case HNS3_HW_FEC_MODE_BASER:
6853 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6855 case HNS3_HW_FEC_MODE_RS:
6856 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6859 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6863 *fec_capa = tmp_fec_capa;
6868 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6870 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6872 return hns3_fec_get_internal(hw, fec_capa);
6876 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6878 struct hns3_config_fec_cmd *req;
6879 struct hns3_cmd_desc desc;
6882 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6884 req = (struct hns3_config_fec_cmd *)desc.data;
6886 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6887 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6888 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6890 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6891 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6892 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6894 case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6895 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6896 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6898 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6899 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6904 ret = hns3_cmd_send(hw, &desc, 1);
6906 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6912 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6914 struct hns3_mac *mac = &hw->mac;
6917 switch (mac->link_speed) {
6918 case ETH_SPEED_NUM_10G:
6919 cur_capa = fec_capa[1].capa;
6921 case ETH_SPEED_NUM_25G:
6922 case ETH_SPEED_NUM_100G:
6923 case ETH_SPEED_NUM_200G:
6924 cur_capa = fec_capa[0].capa;
6935 is_fec_mode_one_bit_set(uint32_t mode)
6940 for (i = 0; i < sizeof(mode); i++)
6941 if (mode >> i & 0x1)
6944 return cnt == 1 ? true : false;
6948 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6950 #define FEC_CAPA_NUM 2
6951 struct hns3_adapter *hns = dev->data->dev_private;
6952 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6953 struct hns3_pf *pf = &hns->pf;
6955 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6957 uint32_t num = FEC_CAPA_NUM;
6960 ret = hns3_fec_get_capability(dev, fec_capa, num);
6964 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6965 if (!is_fec_mode_one_bit_set(mode)) {
6966 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, "
6967 "FEC mode should be only one bit set", mode);
6972 * Check whether the configured mode is within the FEC capability.
6973 * If not, the configured mode will not be supported.
6975 cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6976 if (!(cur_capa & mode)) {
6977 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6981 rte_spinlock_lock(&hw->lock);
6982 ret = hns3_set_fec_hw(hw, mode);
6984 rte_spinlock_unlock(&hw->lock);
6988 pf->fec_mode = mode;
6989 rte_spinlock_unlock(&hw->lock);
6995 hns3_restore_fec(struct hns3_hw *hw)
6997 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6998 struct hns3_pf *pf = &hns->pf;
6999 uint32_t mode = pf->fec_mode;
7002 ret = hns3_set_fec_hw(hw, mode);
7004 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
7011 hns3_query_dev_fec_info(struct hns3_hw *hw)
7013 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7014 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
7017 ret = hns3_fec_get_internal(hw, &pf->fec_mode);
7019 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
7025 hns3_optical_module_existed(struct hns3_hw *hw)
7027 struct hns3_cmd_desc desc;
7031 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
7032 ret = hns3_cmd_send(hw, &desc, 1);
7035 "fail to get optical module exist state, ret = %d.\n",
7039 existed = !!desc.data[0];
7045 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
7046 uint32_t len, uint8_t *data)
7048 #define HNS3_SFP_INFO_CMD_NUM 6
7049 #define HNS3_SFP_INFO_MAX_LEN \
7050 (HNS3_SFP_INFO_BD0_LEN + \
7051 (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
7052 struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
7053 struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
7059 for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7060 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
7062 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
7063 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
7066 sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
7067 sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
7068 read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
7069 sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
7071 ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
7073 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
7078 /* The data format in BD0 is different with the others. */
7079 copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
7080 memcpy(data, sfp_info_bd0->data, copy_len);
7081 read_len = copy_len;
7083 for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7084 if (read_len >= len)
7087 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
7088 memcpy(data + read_len, desc[i].data, copy_len);
7089 read_len += copy_len;
7092 return (int)read_len;
7096 hns3_get_module_eeprom(struct rte_eth_dev *dev,
7097 struct rte_dev_eeprom_info *info)
7099 struct hns3_adapter *hns = dev->data->dev_private;
7100 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7101 uint32_t offset = info->offset;
7102 uint32_t len = info->length;
7103 uint8_t *data = info->data;
7104 uint32_t read_len = 0;
7106 if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
7109 if (!hns3_optical_module_existed(hw)) {
7110 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
7114 while (read_len < len) {
7116 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
7128 hns3_get_module_info(struct rte_eth_dev *dev,
7129 struct rte_eth_dev_module_info *modinfo)
7131 #define HNS3_SFF8024_ID_SFP 0x03
7132 #define HNS3_SFF8024_ID_QSFP_8438 0x0c
7133 #define HNS3_SFF8024_ID_QSFP_8436_8636 0x0d
7134 #define HNS3_SFF8024_ID_QSFP28_8636 0x11
7135 #define HNS3_SFF_8636_V1_3 0x03
7136 struct hns3_adapter *hns = dev->data->dev_private;
7137 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7138 struct rte_dev_eeprom_info info;
7139 struct hns3_sfp_type sfp_type;
7142 memset(&sfp_type, 0, sizeof(sfp_type));
7143 memset(&info, 0, sizeof(info));
7144 info.data = (uint8_t *)&sfp_type;
7145 info.length = sizeof(sfp_type);
7146 ret = hns3_get_module_eeprom(dev, &info);
7150 switch (sfp_type.type) {
7151 case HNS3_SFF8024_ID_SFP:
7152 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7153 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7155 case HNS3_SFF8024_ID_QSFP_8438:
7156 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7157 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7159 case HNS3_SFF8024_ID_QSFP_8436_8636:
7160 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
7161 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7162 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7164 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7165 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7168 case HNS3_SFF8024_ID_QSFP28_8636:
7169 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7170 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7173 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
7174 sfp_type.type, sfp_type.ext_type);
7182 hns3_clock_gettime(struct timeval *tv)
7184 #ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */
7185 #define CLOCK_TYPE CLOCK_MONOTONIC_RAW
7187 #define CLOCK_TYPE CLOCK_MONOTONIC
7189 #define NSEC_TO_USEC_DIV 1000
7191 struct timespec spec;
7192 (void)clock_gettime(CLOCK_TYPE, &spec);
7194 tv->tv_sec = spec.tv_sec;
7195 tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV;
7199 hns3_clock_calctime_ms(struct timeval *tv)
7201 return (uint64_t)tv->tv_sec * MSEC_PER_SEC +
7202 tv->tv_usec / USEC_PER_MSEC;
7206 hns3_clock_gettime_ms(void)
7210 hns3_clock_gettime(&tv);
7211 return hns3_clock_calctime_ms(&tv);
7215 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
7217 uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
7221 if (strcmp(value, "vec") == 0)
7222 hint = HNS3_IO_FUNC_HINT_VEC;
7223 else if (strcmp(value, "sve") == 0)
7224 hint = HNS3_IO_FUNC_HINT_SVE;
7225 else if (strcmp(value, "simple") == 0)
7226 hint = HNS3_IO_FUNC_HINT_SIMPLE;
7227 else if (strcmp(value, "common") == 0)
7228 hint = HNS3_IO_FUNC_HINT_COMMON;
7230 /* If the hint is valid then update output parameters */
7231 if (hint != HNS3_IO_FUNC_HINT_NONE)
7232 *(uint32_t *)extra_args = hint;
7238 hns3_get_io_hint_func_name(uint32_t hint)
7241 case HNS3_IO_FUNC_HINT_VEC:
7243 case HNS3_IO_FUNC_HINT_SVE:
7245 case HNS3_IO_FUNC_HINT_SIMPLE:
7247 case HNS3_IO_FUNC_HINT_COMMON:
7255 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args)
7261 val = strtoull(value, NULL, 16);
7262 *(uint64_t *)extra_args = val;
7268 hns3_parse_devargs(struct rte_eth_dev *dev)
7270 struct hns3_adapter *hns = dev->data->dev_private;
7271 uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7272 uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7273 struct hns3_hw *hw = &hns->hw;
7274 uint64_t dev_caps_mask = 0;
7275 struct rte_kvargs *kvlist;
7277 if (dev->device->devargs == NULL)
7280 kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
7284 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
7285 &hns3_parse_io_hint_func, &rx_func_hint);
7286 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
7287 &hns3_parse_io_hint_func, &tx_func_hint);
7288 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK,
7289 &hns3_parse_dev_caps_mask, &dev_caps_mask);
7290 rte_kvargs_free(kvlist);
7292 if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7293 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
7294 hns3_get_io_hint_func_name(rx_func_hint));
7295 hns->rx_func_hint = rx_func_hint;
7296 if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7297 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
7298 hns3_get_io_hint_func_name(tx_func_hint));
7299 hns->tx_func_hint = tx_func_hint;
7301 if (dev_caps_mask != 0)
7302 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".",
7303 HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask);
7304 hns->dev_caps_mask = dev_caps_mask;
7307 static const struct eth_dev_ops hns3_eth_dev_ops = {
7308 .dev_configure = hns3_dev_configure,
7309 .dev_start = hns3_dev_start,
7310 .dev_stop = hns3_dev_stop,
7311 .dev_close = hns3_dev_close,
7312 .promiscuous_enable = hns3_dev_promiscuous_enable,
7313 .promiscuous_disable = hns3_dev_promiscuous_disable,
7314 .allmulticast_enable = hns3_dev_allmulticast_enable,
7315 .allmulticast_disable = hns3_dev_allmulticast_disable,
7316 .mtu_set = hns3_dev_mtu_set,
7317 .stats_get = hns3_stats_get,
7318 .stats_reset = hns3_stats_reset,
7319 .xstats_get = hns3_dev_xstats_get,
7320 .xstats_get_names = hns3_dev_xstats_get_names,
7321 .xstats_reset = hns3_dev_xstats_reset,
7322 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
7323 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
7324 .dev_infos_get = hns3_dev_infos_get,
7325 .fw_version_get = hns3_fw_version_get,
7326 .rx_queue_setup = hns3_rx_queue_setup,
7327 .tx_queue_setup = hns3_tx_queue_setup,
7328 .rx_queue_release = hns3_dev_rx_queue_release,
7329 .tx_queue_release = hns3_dev_tx_queue_release,
7330 .rx_queue_start = hns3_dev_rx_queue_start,
7331 .rx_queue_stop = hns3_dev_rx_queue_stop,
7332 .tx_queue_start = hns3_dev_tx_queue_start,
7333 .tx_queue_stop = hns3_dev_tx_queue_stop,
7334 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
7335 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
7336 .rxq_info_get = hns3_rxq_info_get,
7337 .txq_info_get = hns3_txq_info_get,
7338 .rx_burst_mode_get = hns3_rx_burst_mode_get,
7339 .tx_burst_mode_get = hns3_tx_burst_mode_get,
7340 .flow_ctrl_get = hns3_flow_ctrl_get,
7341 .flow_ctrl_set = hns3_flow_ctrl_set,
7342 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
7343 .mac_addr_add = hns3_add_mac_addr,
7344 .mac_addr_remove = hns3_remove_mac_addr,
7345 .mac_addr_set = hns3_set_default_mac_addr,
7346 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
7347 .link_update = hns3_dev_link_update,
7348 .rss_hash_update = hns3_dev_rss_hash_update,
7349 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
7350 .reta_update = hns3_dev_rss_reta_update,
7351 .reta_query = hns3_dev_rss_reta_query,
7352 .flow_ops_get = hns3_dev_flow_ops_get,
7353 .vlan_filter_set = hns3_vlan_filter_set,
7354 .vlan_tpid_set = hns3_vlan_tpid_set,
7355 .vlan_offload_set = hns3_vlan_offload_set,
7356 .vlan_pvid_set = hns3_vlan_pvid_set,
7357 .get_reg = hns3_get_regs,
7358 .get_module_info = hns3_get_module_info,
7359 .get_module_eeprom = hns3_get_module_eeprom,
7360 .get_dcb_info = hns3_get_dcb_info,
7361 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
7362 .fec_get_capability = hns3_fec_get_capability,
7363 .fec_get = hns3_fec_get,
7364 .fec_set = hns3_fec_set,
7365 .tm_ops_get = hns3_tm_ops_get,
7366 .tx_done_cleanup = hns3_tx_done_cleanup,
7367 .timesync_enable = hns3_timesync_enable,
7368 .timesync_disable = hns3_timesync_disable,
7369 .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
7370 .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
7371 .timesync_adjust_time = hns3_timesync_adjust_time,
7372 .timesync_read_time = hns3_timesync_read_time,
7373 .timesync_write_time = hns3_timesync_write_time,
7376 static const struct hns3_reset_ops hns3_reset_ops = {
7377 .reset_service = hns3_reset_service,
7378 .stop_service = hns3_stop_service,
7379 .prepare_reset = hns3_prepare_reset,
7380 .wait_hardware_ready = hns3_wait_hardware_ready,
7381 .reinit_dev = hns3_reinit_dev,
7382 .restore_conf = hns3_restore_conf,
7383 .start_service = hns3_start_service,
7387 hns3_dev_init(struct rte_eth_dev *eth_dev)
7389 struct hns3_adapter *hns = eth_dev->data->dev_private;
7390 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
7391 struct rte_ether_addr *eth_addr;
7392 struct hns3_hw *hw = &hns->hw;
7395 PMD_INIT_FUNC_TRACE();
7397 hns3_flow_init(eth_dev);
7399 hns3_set_rxtx_function(eth_dev);
7400 eth_dev->dev_ops = &hns3_eth_dev_ops;
7401 eth_dev->rx_queue_count = hns3_rx_queue_count;
7402 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7403 ret = hns3_mp_init_secondary();
7405 PMD_INIT_LOG(ERR, "Failed to init for secondary "
7406 "process, ret = %d", ret);
7407 goto err_mp_init_secondary;
7409 hw->secondary_cnt++;
7410 hns3_tx_push_init(eth_dev);
7414 ret = hns3_mp_init_primary();
7417 "Failed to init for primary process, ret = %d",
7419 goto err_mp_init_primary;
7422 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
7424 hw->data = eth_dev->data;
7425 hns3_parse_devargs(eth_dev);
7428 * Set default max packet size according to the mtu
7429 * default vale in DPDK frame.
7431 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
7433 ret = hns3_reset_init(hw);
7435 goto err_init_reset;
7436 hw->reset.ops = &hns3_reset_ops;
7438 ret = hns3_init_pf(eth_dev);
7440 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
7444 /* Allocate memory for storing MAC addresses */
7445 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
7446 sizeof(struct rte_ether_addr) *
7447 HNS3_UC_MACADDR_NUM, 0);
7448 if (eth_dev->data->mac_addrs == NULL) {
7449 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
7450 "to store MAC addresses",
7451 sizeof(struct rte_ether_addr) *
7452 HNS3_UC_MACADDR_NUM);
7454 goto err_rte_zmalloc;
7457 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
7458 if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
7459 rte_eth_random_addr(hw->mac.mac_addr);
7460 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
7461 (struct rte_ether_addr *)hw->mac.mac_addr);
7462 hns3_warn(hw, "default mac_addr from firmware is an invalid "
7463 "unicast address, using random MAC address %s",
7466 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7467 ð_dev->data->mac_addrs[0]);
7469 hw->adapter_state = HNS3_NIC_INITIALIZED;
7471 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7473 hns3_err(hw, "Reschedule reset service after dev_init");
7474 hns3_schedule_reset(hns);
7476 /* IMP will wait ready flag before reset */
7477 hns3_notify_reset_ready(hw, false);
7480 hns3_info(hw, "hns3 dev initialization successful!");
7484 hns3_uninit_pf(eth_dev);
7487 rte_free(hw->reset.wait_data);
7490 hns3_mp_uninit_primary();
7492 err_mp_init_primary:
7493 err_mp_init_secondary:
7494 eth_dev->dev_ops = NULL;
7495 eth_dev->rx_pkt_burst = NULL;
7496 eth_dev->rx_descriptor_status = NULL;
7497 eth_dev->tx_pkt_burst = NULL;
7498 eth_dev->tx_pkt_prepare = NULL;
7499 eth_dev->tx_descriptor_status = NULL;
7504 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7506 struct hns3_adapter *hns = eth_dev->data->dev_private;
7507 struct hns3_hw *hw = &hns->hw;
7509 PMD_INIT_FUNC_TRACE();
7511 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
7514 if (hw->adapter_state < HNS3_NIC_CLOSING)
7515 hns3_dev_close(eth_dev);
7517 hw->adapter_state = HNS3_NIC_REMOVED;
7522 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7523 struct rte_pci_device *pci_dev)
7525 return rte_eth_dev_pci_generic_probe(pci_dev,
7526 sizeof(struct hns3_adapter),
7531 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7533 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7536 static const struct rte_pci_id pci_id_hns3_map[] = {
7537 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7538 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7539 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7540 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7541 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7542 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7543 { .vendor_id = 0, }, /* sentinel */
7546 static struct rte_pci_driver rte_hns3_pmd = {
7547 .id_table = pci_id_hns3_map,
7548 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7549 .probe = eth_hns3_pci_probe,
7550 .remove = eth_hns3_pci_remove,
7553 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7554 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7555 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7556 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7557 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7558 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
7559 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");
7560 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE);
7561 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE);