1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
6 #include <rte_bus_pci.h>
7 #include <ethdev_pci.h>
9 #include <rte_kvargs.h>
11 #include "hns3_ethdev.h"
12 #include "hns3_logs.h"
13 #include "hns3_rxtx.h"
14 #include "hns3_intr.h"
15 #include "hns3_regs.h"
19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
22 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
23 #define HNS3_SERVICE_QUICK_INTERVAL 10
24 #define HNS3_INVALID_PVID 0xFFFF
26 #define HNS3_FILTER_TYPE_VF 0
27 #define HNS3_FILTER_TYPE_PORT 1
28 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
29 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
30 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
31 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
32 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
33 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
34 | HNS3_FILTER_FE_ROCE_EGRESS_B)
35 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
36 | HNS3_FILTER_FE_ROCE_INGRESS_B)
38 /* Reset related Registers */
39 #define HNS3_GLOBAL_RESET_BIT 0
40 #define HNS3_CORE_RESET_BIT 1
41 #define HNS3_IMP_RESET_BIT 2
42 #define HNS3_FUN_RST_ING_B 0
44 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
45 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
46 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U
47 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
49 #define HNS3_RESET_WAIT_MS 100
50 #define HNS3_RESET_WAIT_CNT 200
52 /* FEC mode order defined in HNS3 hardware */
53 #define HNS3_HW_FEC_MODE_NOFEC 0
54 #define HNS3_HW_FEC_MODE_BASER 1
55 #define HNS3_HW_FEC_MODE_RS 2
58 HNS3_VECTOR0_EVENT_RST,
59 HNS3_VECTOR0_EVENT_MBX,
60 HNS3_VECTOR0_EVENT_ERR,
61 HNS3_VECTOR0_EVENT_PTP,
62 HNS3_VECTOR0_EVENT_OTHER,
65 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
66 { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
67 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
68 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
70 { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
71 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
72 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
73 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
75 { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
76 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
77 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
79 { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
80 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
81 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
82 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
84 { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
85 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
86 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
88 { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
89 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
90 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
93 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
95 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
96 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
98 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
99 static bool hns3_update_link_status(struct hns3_hw *hw);
101 static int hns3_add_mc_addr(struct hns3_hw *hw,
102 struct rte_ether_addr *mac_addr);
103 static int hns3_remove_mc_addr(struct hns3_hw *hw,
104 struct rte_ether_addr *mac_addr);
105 static int hns3_restore_fec(struct hns3_hw *hw);
106 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
107 static int hns3_do_stop(struct hns3_adapter *hns);
108 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
110 void hns3_ether_format_addr(char *buf, uint16_t size,
111 const struct rte_ether_addr *ether_addr)
113 snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
114 ether_addr->addr_bytes[0],
115 ether_addr->addr_bytes[4],
116 ether_addr->addr_bytes[5]);
120 hns3_pf_disable_irq0(struct hns3_hw *hw)
122 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
126 hns3_pf_enable_irq0(struct hns3_hw *hw)
128 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
131 static enum hns3_evt_cause
132 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
135 struct hns3_hw *hw = &hns->hw;
137 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
138 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
139 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
141 hw->reset.stats.imp_cnt++;
142 hns3_warn(hw, "IMP reset detected, clear reset status");
144 hns3_schedule_delayed_reset(hns);
145 hns3_warn(hw, "IMP reset detected, don't clear reset status");
148 return HNS3_VECTOR0_EVENT_RST;
151 static enum hns3_evt_cause
152 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
155 struct hns3_hw *hw = &hns->hw;
157 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
158 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
159 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
161 hw->reset.stats.global_cnt++;
162 hns3_warn(hw, "Global reset detected, clear reset status");
164 hns3_schedule_delayed_reset(hns);
166 "Global reset detected, don't clear reset status");
169 return HNS3_VECTOR0_EVENT_RST;
172 static enum hns3_evt_cause
173 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
175 struct hns3_hw *hw = &hns->hw;
176 uint32_t vector0_int_stats;
177 uint32_t cmdq_src_val;
178 uint32_t hw_err_src_reg;
180 enum hns3_evt_cause ret;
183 /* fetch the events from their corresponding regs */
184 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
185 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
186 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
188 is_delay = clearval == NULL ? true : false;
190 * Assumption: If by any chance reset and mailbox events are reported
191 * together then we will only process reset event and defer the
192 * processing of the mailbox events. Since, we would have not cleared
193 * RX CMDQ event this time we would receive again another interrupt
194 * from H/W just for the mailbox.
196 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
197 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
202 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
203 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
207 /* Check for vector0 1588 event source */
208 if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
209 val = BIT(HNS3_VECTOR0_1588_INT_B);
210 ret = HNS3_VECTOR0_EVENT_PTP;
214 /* check for vector0 msix event source */
215 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
216 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
217 val = vector0_int_stats | hw_err_src_reg;
218 ret = HNS3_VECTOR0_EVENT_ERR;
222 /* check for vector0 mailbox(=CMDQ RX) event source */
223 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
224 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
226 ret = HNS3_VECTOR0_EVENT_MBX;
230 val = vector0_int_stats;
231 ret = HNS3_VECTOR0_EVENT_OTHER;
240 hns3_is_1588_event_type(uint32_t event_type)
242 return (event_type == HNS3_VECTOR0_EVENT_PTP);
246 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
248 if (event_type == HNS3_VECTOR0_EVENT_RST ||
249 hns3_is_1588_event_type(event_type))
250 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
251 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
252 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
256 hns3_clear_all_event_cause(struct hns3_hw *hw)
258 uint32_t vector0_int_stats;
259 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
261 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
262 hns3_warn(hw, "Probe during IMP reset interrupt");
264 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
265 hns3_warn(hw, "Probe during Global reset interrupt");
267 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
268 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
269 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
270 BIT(HNS3_VECTOR0_CORERESET_INT_B));
271 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
272 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
273 BIT(HNS3_VECTOR0_1588_INT_B));
277 hns3_handle_mac_tnl(struct hns3_hw *hw)
279 struct hns3_cmd_desc desc;
283 /* query and clear mac tnl interrupt */
284 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
285 ret = hns3_cmd_send(hw, &desc, 1);
287 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
291 status = rte_le_to_cpu_32(desc.data[0]);
293 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
294 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
296 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
297 ret = hns3_cmd_send(hw, &desc, 1);
299 hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
305 hns3_interrupt_handler(void *param)
307 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
308 struct hns3_adapter *hns = dev->data->dev_private;
309 struct hns3_hw *hw = &hns->hw;
310 enum hns3_evt_cause event_cause;
311 uint32_t clearval = 0;
312 uint32_t vector0_int;
316 /* Disable interrupt */
317 hns3_pf_disable_irq0(hw);
319 event_cause = hns3_check_event_cause(hns, &clearval);
320 vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
321 ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
322 cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
323 /* vector 0 interrupt is shared with reset and mailbox source events. */
324 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
325 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
326 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
327 vector0_int, ras_int, cmdq_int);
328 hns3_handle_mac_tnl(hw);
329 hns3_handle_error(hns);
330 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
331 hns3_warn(hw, "received reset interrupt");
332 hns3_schedule_reset(hns);
333 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
334 hns3_dev_handle_mbx_msg(hw);
336 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
337 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
338 vector0_int, ras_int, cmdq_int);
341 hns3_clear_event_cause(hw, event_cause, clearval);
342 /* Enable interrupt if it is not cause by reset */
343 hns3_pf_enable_irq0(hw);
347 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
349 #define HNS3_VLAN_ID_OFFSET_STEP 160
350 #define HNS3_VLAN_BYTE_SIZE 8
351 struct hns3_vlan_filter_pf_cfg_cmd *req;
352 struct hns3_hw *hw = &hns->hw;
353 uint8_t vlan_offset_byte_val;
354 struct hns3_cmd_desc desc;
355 uint8_t vlan_offset_byte;
356 uint8_t vlan_offset_base;
359 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
361 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
362 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
364 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
366 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
367 req->vlan_offset = vlan_offset_base;
368 req->vlan_cfg = on ? 0 : 1;
369 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
371 ret = hns3_cmd_send(hw, &desc, 1);
373 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
380 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
382 struct hns3_user_vlan_table *vlan_entry;
383 struct hns3_pf *pf = &hns->pf;
385 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
386 if (vlan_entry->vlan_id == vlan_id) {
387 if (vlan_entry->hd_tbl_status)
388 hns3_set_port_vlan_filter(hns, vlan_id, 0);
389 LIST_REMOVE(vlan_entry, next);
390 rte_free(vlan_entry);
397 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
400 struct hns3_user_vlan_table *vlan_entry;
401 struct hns3_hw *hw = &hns->hw;
402 struct hns3_pf *pf = &hns->pf;
404 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
405 if (vlan_entry->vlan_id == vlan_id)
409 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
410 if (vlan_entry == NULL) {
411 hns3_err(hw, "Failed to malloc hns3 vlan table");
415 vlan_entry->hd_tbl_status = writen_to_tbl;
416 vlan_entry->vlan_id = vlan_id;
418 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
422 hns3_restore_vlan_table(struct hns3_adapter *hns)
424 struct hns3_user_vlan_table *vlan_entry;
425 struct hns3_hw *hw = &hns->hw;
426 struct hns3_pf *pf = &hns->pf;
430 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
431 return hns3_vlan_pvid_configure(hns,
432 hw->port_base_vlan_cfg.pvid, 1);
434 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
435 if (vlan_entry->hd_tbl_status) {
436 vlan_id = vlan_entry->vlan_id;
437 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
447 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
449 struct hns3_hw *hw = &hns->hw;
450 bool writen_to_tbl = false;
454 * When vlan filter is enabled, hardware regards packets without vlan
455 * as packets with vlan 0. So, to receive packets without vlan, vlan id
456 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
458 if (on == 0 && vlan_id == 0)
462 * When port base vlan enabled, we use port base vlan as the vlan
463 * filter condition. In this case, we don't update vlan filter table
464 * when user add new vlan or remove exist vlan, just update the
465 * vlan list. The vlan id in vlan list will be written in vlan filter
466 * table until port base vlan disabled
468 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
469 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
470 writen_to_tbl = true;
475 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
477 hns3_rm_dev_vlan_table(hns, vlan_id);
483 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
485 struct hns3_adapter *hns = dev->data->dev_private;
486 struct hns3_hw *hw = &hns->hw;
489 rte_spinlock_lock(&hw->lock);
490 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
491 rte_spinlock_unlock(&hw->lock);
496 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
499 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
500 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
501 struct hns3_hw *hw = &hns->hw;
502 struct hns3_cmd_desc desc;
505 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
506 vlan_type != ETH_VLAN_TYPE_OUTER)) {
507 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
511 if (tpid != RTE_ETHER_TYPE_VLAN) {
512 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
516 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
517 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
519 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
520 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
521 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
522 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
523 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
524 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
525 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
526 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
529 ret = hns3_cmd_send(hw, &desc, 1);
531 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
536 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
538 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
539 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
540 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
542 ret = hns3_cmd_send(hw, &desc, 1);
544 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
550 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
553 struct hns3_adapter *hns = dev->data->dev_private;
554 struct hns3_hw *hw = &hns->hw;
557 rte_spinlock_lock(&hw->lock);
558 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
559 rte_spinlock_unlock(&hw->lock);
564 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
565 struct hns3_rx_vtag_cfg *vcfg)
567 struct hns3_vport_vtag_rx_cfg_cmd *req;
568 struct hns3_hw *hw = &hns->hw;
569 struct hns3_cmd_desc desc;
574 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
576 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
577 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
578 vcfg->strip_tag1_en ? 1 : 0);
579 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
580 vcfg->strip_tag2_en ? 1 : 0);
581 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
582 vcfg->vlan1_vlan_prionly ? 1 : 0);
583 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
584 vcfg->vlan2_vlan_prionly ? 1 : 0);
586 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
587 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
588 vcfg->strip_tag1_discard_en ? 1 : 0);
589 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
590 vcfg->strip_tag2_discard_en ? 1 : 0);
592 * In current version VF is not supported when PF is driven by DPDK
593 * driver, just need to configure parameters for PF vport.
595 vport_id = HNS3_PF_FUNC_ID;
596 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
597 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
598 req->vf_bitmap[req->vf_offset] = bitmap;
600 ret = hns3_cmd_send(hw, &desc, 1);
602 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
607 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
608 struct hns3_rx_vtag_cfg *vcfg)
610 struct hns3_pf *pf = &hns->pf;
611 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
615 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
616 struct hns3_tx_vtag_cfg *vcfg)
618 struct hns3_pf *pf = &hns->pf;
619 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
623 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
625 struct hns3_rx_vtag_cfg rxvlan_cfg;
626 struct hns3_hw *hw = &hns->hw;
629 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
630 rxvlan_cfg.strip_tag1_en = false;
631 rxvlan_cfg.strip_tag2_en = enable;
632 rxvlan_cfg.strip_tag2_discard_en = false;
634 rxvlan_cfg.strip_tag1_en = enable;
635 rxvlan_cfg.strip_tag2_en = true;
636 rxvlan_cfg.strip_tag2_discard_en = true;
639 rxvlan_cfg.strip_tag1_discard_en = false;
640 rxvlan_cfg.vlan1_vlan_prionly = false;
641 rxvlan_cfg.vlan2_vlan_prionly = false;
642 rxvlan_cfg.rx_vlan_offload_en = enable;
644 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
646 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
650 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
656 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
657 uint8_t fe_type, bool filter_en, uint8_t vf_id)
659 struct hns3_vlan_filter_ctrl_cmd *req;
660 struct hns3_cmd_desc desc;
663 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
665 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
666 req->vlan_type = vlan_type;
667 req->vlan_fe = filter_en ? fe_type : 0;
670 ret = hns3_cmd_send(hw, &desc, 1);
672 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
678 hns3_vlan_filter_init(struct hns3_adapter *hns)
680 struct hns3_hw *hw = &hns->hw;
683 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
684 HNS3_FILTER_FE_EGRESS, false,
687 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
691 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
692 HNS3_FILTER_FE_INGRESS, false,
695 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
701 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
703 struct hns3_hw *hw = &hns->hw;
706 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
707 HNS3_FILTER_FE_INGRESS, enable,
710 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
711 enable ? "enable" : "disable", ret);
717 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
719 struct hns3_adapter *hns = dev->data->dev_private;
720 struct hns3_hw *hw = &hns->hw;
721 struct rte_eth_rxmode *rxmode;
722 unsigned int tmp_mask;
726 rte_spinlock_lock(&hw->lock);
727 rxmode = &dev->data->dev_conf.rxmode;
728 tmp_mask = (unsigned int)mask;
729 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
730 /* ignore vlan filter configuration during promiscuous mode */
731 if (!dev->data->promiscuous) {
732 /* Enable or disable VLAN filter */
733 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
736 ret = hns3_enable_vlan_filter(hns, enable);
738 rte_spinlock_unlock(&hw->lock);
739 hns3_err(hw, "failed to %s rx filter, ret = %d",
740 enable ? "enable" : "disable", ret);
746 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
747 /* Enable or disable VLAN stripping */
748 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
751 ret = hns3_en_hw_strip_rxvtag(hns, enable);
753 rte_spinlock_unlock(&hw->lock);
754 hns3_err(hw, "failed to %s rx strip, ret = %d",
755 enable ? "enable" : "disable", ret);
760 rte_spinlock_unlock(&hw->lock);
766 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
767 struct hns3_tx_vtag_cfg *vcfg)
769 struct hns3_vport_vtag_tx_cfg_cmd *req;
770 struct hns3_cmd_desc desc;
771 struct hns3_hw *hw = &hns->hw;
776 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
778 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
779 req->def_vlan_tag1 = vcfg->default_tag1;
780 req->def_vlan_tag2 = vcfg->default_tag2;
781 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
782 vcfg->accept_tag1 ? 1 : 0);
783 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
784 vcfg->accept_untag1 ? 1 : 0);
785 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
786 vcfg->accept_tag2 ? 1 : 0);
787 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
788 vcfg->accept_untag2 ? 1 : 0);
789 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
790 vcfg->insert_tag1_en ? 1 : 0);
791 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
792 vcfg->insert_tag2_en ? 1 : 0);
793 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
795 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
796 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
797 vcfg->tag_shift_mode_en ? 1 : 0);
800 * In current version VF is not supported when PF is driven by DPDK
801 * driver, just need to configure parameters for PF vport.
803 vport_id = HNS3_PF_FUNC_ID;
804 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
805 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
806 req->vf_bitmap[req->vf_offset] = bitmap;
808 ret = hns3_cmd_send(hw, &desc, 1);
810 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
816 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
819 struct hns3_hw *hw = &hns->hw;
820 struct hns3_tx_vtag_cfg txvlan_cfg;
823 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
824 txvlan_cfg.accept_tag1 = true;
825 txvlan_cfg.insert_tag1_en = false;
826 txvlan_cfg.default_tag1 = 0;
828 txvlan_cfg.accept_tag1 =
829 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
830 txvlan_cfg.insert_tag1_en = true;
831 txvlan_cfg.default_tag1 = pvid;
834 txvlan_cfg.accept_untag1 = true;
835 txvlan_cfg.accept_tag2 = true;
836 txvlan_cfg.accept_untag2 = true;
837 txvlan_cfg.insert_tag2_en = false;
838 txvlan_cfg.default_tag2 = 0;
839 txvlan_cfg.tag_shift_mode_en = true;
841 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
843 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
848 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
854 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
856 struct hns3_user_vlan_table *vlan_entry;
857 struct hns3_pf *pf = &hns->pf;
859 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
860 if (vlan_entry->hd_tbl_status) {
861 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
862 vlan_entry->hd_tbl_status = false;
867 vlan_entry = LIST_FIRST(&pf->vlan_list);
869 LIST_REMOVE(vlan_entry, next);
870 rte_free(vlan_entry);
871 vlan_entry = LIST_FIRST(&pf->vlan_list);
877 hns3_add_all_vlan_table(struct hns3_adapter *hns)
879 struct hns3_user_vlan_table *vlan_entry;
880 struct hns3_pf *pf = &hns->pf;
882 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
883 if (!vlan_entry->hd_tbl_status) {
884 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
885 vlan_entry->hd_tbl_status = true;
891 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
893 struct hns3_hw *hw = &hns->hw;
896 hns3_rm_all_vlan_table(hns, true);
897 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
898 ret = hns3_set_port_vlan_filter(hns,
899 hw->port_base_vlan_cfg.pvid, 0);
901 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
909 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
910 uint16_t port_base_vlan_state, uint16_t new_pvid)
912 struct hns3_hw *hw = &hns->hw;
916 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
917 old_pvid = hw->port_base_vlan_cfg.pvid;
918 if (old_pvid != HNS3_INVALID_PVID) {
919 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
921 hns3_err(hw, "failed to remove old pvid %u, "
922 "ret = %d", old_pvid, ret);
927 hns3_rm_all_vlan_table(hns, false);
928 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
930 hns3_err(hw, "failed to add new pvid %u, ret = %d",
935 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
937 hns3_err(hw, "failed to remove pvid %u, ret = %d",
942 hns3_add_all_vlan_table(hns);
948 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
950 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
951 struct hns3_rx_vtag_cfg rx_vlan_cfg;
955 rx_strip_en = old_cfg->rx_vlan_offload_en;
957 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
958 rx_vlan_cfg.strip_tag2_en = true;
959 rx_vlan_cfg.strip_tag2_discard_en = true;
961 rx_vlan_cfg.strip_tag1_en = false;
962 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
963 rx_vlan_cfg.strip_tag2_discard_en = false;
965 rx_vlan_cfg.strip_tag1_discard_en = false;
966 rx_vlan_cfg.vlan1_vlan_prionly = false;
967 rx_vlan_cfg.vlan2_vlan_prionly = false;
968 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
970 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
974 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
979 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
981 struct hns3_hw *hw = &hns->hw;
982 uint16_t port_base_vlan_state;
985 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
986 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
987 hns3_warn(hw, "Invalid operation! As current pvid set "
988 "is %u, disable pvid %u is invalid",
989 hw->port_base_vlan_cfg.pvid, pvid);
993 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
994 HNS3_PORT_BASE_VLAN_DISABLE;
995 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
997 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
1002 ret = hns3_en_pvid_strip(hns, on);
1004 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1006 goto pvid_vlan_strip_fail;
1009 if (pvid == HNS3_INVALID_PVID)
1011 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1013 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1015 goto vlan_filter_set_fail;
1019 hw->port_base_vlan_cfg.state = port_base_vlan_state;
1020 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1023 vlan_filter_set_fail:
1024 err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1025 HNS3_PORT_BASE_VLAN_ENABLE);
1027 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1029 pvid_vlan_strip_fail:
1030 err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1031 hw->port_base_vlan_cfg.pvid);
1033 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1039 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1041 struct hns3_adapter *hns = dev->data->dev_private;
1042 struct hns3_hw *hw = &hns->hw;
1043 bool pvid_en_state_change;
1044 uint16_t pvid_state;
1047 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1048 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1049 RTE_ETHER_MAX_VLAN_ID);
1054 * If PVID configuration state change, should refresh the PVID
1055 * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1057 pvid_state = hw->port_base_vlan_cfg.state;
1058 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1059 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1060 pvid_en_state_change = false;
1062 pvid_en_state_change = true;
1064 rte_spinlock_lock(&hw->lock);
1065 ret = hns3_vlan_pvid_configure(hns, pvid, on);
1066 rte_spinlock_unlock(&hw->lock);
1070 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1071 * need be processed by PMD driver.
1073 if (pvid_en_state_change &&
1074 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1075 hns3_update_all_queues_pvid_proc_en(hw);
1081 hns3_default_vlan_config(struct hns3_adapter *hns)
1083 struct hns3_hw *hw = &hns->hw;
1087 * When vlan filter is enabled, hardware regards packets without vlan
1088 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1089 * table, packets without vlan won't be received. So, add vlan 0 as
1092 ret = hns3_vlan_filter_configure(hns, 0, 1);
1094 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1099 hns3_init_vlan_config(struct hns3_adapter *hns)
1101 struct hns3_hw *hw = &hns->hw;
1105 * This function can be called in the initialization and reset process,
1106 * when in reset process, it means that hardware had been reseted
1107 * successfully and we need to restore the hardware configuration to
1108 * ensure that the hardware configuration remains unchanged before and
1111 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1112 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1113 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1116 ret = hns3_vlan_filter_init(hns);
1118 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1122 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1123 RTE_ETHER_TYPE_VLAN);
1125 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1130 * When in the reinit dev stage of the reset process, the following
1131 * vlan-related configurations may differ from those at initialization,
1132 * we will restore configurations to hardware in hns3_restore_vlan_table
1133 * and hns3_restore_vlan_conf later.
1135 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1136 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1138 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1142 ret = hns3_en_hw_strip_rxvtag(hns, false);
1144 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1150 return hns3_default_vlan_config(hns);
1154 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1156 struct hns3_pf *pf = &hns->pf;
1157 struct hns3_hw *hw = &hns->hw;
1162 if (!hw->data->promiscuous) {
1163 /* restore vlan filter states */
1164 offloads = hw->data->dev_conf.rxmode.offloads;
1165 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1166 ret = hns3_enable_vlan_filter(hns, enable);
1168 hns3_err(hw, "failed to restore vlan rx filter conf, "
1174 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1176 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1180 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1182 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1188 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1190 struct hns3_adapter *hns = dev->data->dev_private;
1191 struct rte_eth_dev_data *data = dev->data;
1192 struct rte_eth_txmode *txmode;
1193 struct hns3_hw *hw = &hns->hw;
1197 txmode = &data->dev_conf.txmode;
1198 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1200 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1201 "configuration is not supported! Ignore these two "
1202 "parameters: hw_vlan_reject_tagged(%u), "
1203 "hw_vlan_reject_untagged(%u)",
1204 txmode->hw_vlan_reject_tagged,
1205 txmode->hw_vlan_reject_untagged);
1207 /* Apply vlan offload setting */
1208 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1209 ret = hns3_vlan_offload_set(dev, mask);
1211 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1217 * If pvid config is not set in rte_eth_conf, driver needn't to set
1218 * VLAN pvid related configuration to hardware.
1220 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1223 /* Apply pvid setting */
1224 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1225 txmode->hw_vlan_insert_pvid);
1227 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1234 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1235 unsigned int tso_mss_max)
1237 struct hns3_cfg_tso_status_cmd *req;
1238 struct hns3_cmd_desc desc;
1241 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1243 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1246 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1248 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1251 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1253 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1255 return hns3_cmd_send(hw, &desc, 1);
1259 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1260 uint16_t *allocated_size, bool is_alloc)
1262 struct hns3_umv_spc_alc_cmd *req;
1263 struct hns3_cmd_desc desc;
1266 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1267 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1268 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1269 req->space_size = rte_cpu_to_le_32(space_size);
1271 ret = hns3_cmd_send(hw, &desc, 1);
1273 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1274 is_alloc ? "allocate" : "free", ret);
1278 if (is_alloc && allocated_size)
1279 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1285 hns3_init_umv_space(struct hns3_hw *hw)
1287 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1288 struct hns3_pf *pf = &hns->pf;
1289 uint16_t allocated_size = 0;
1292 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1297 if (allocated_size < pf->wanted_umv_size)
1298 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1299 pf->wanted_umv_size, allocated_size);
1301 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1302 pf->wanted_umv_size;
1303 pf->used_umv_size = 0;
1308 hns3_uninit_umv_space(struct hns3_hw *hw)
1310 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1311 struct hns3_pf *pf = &hns->pf;
1314 if (pf->max_umv_size == 0)
1317 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1321 pf->max_umv_size = 0;
1327 hns3_is_umv_space_full(struct hns3_hw *hw)
1329 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1330 struct hns3_pf *pf = &hns->pf;
1333 is_full = (pf->used_umv_size >= pf->max_umv_size);
1339 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1341 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1342 struct hns3_pf *pf = &hns->pf;
1345 if (pf->used_umv_size > 0)
1346 pf->used_umv_size--;
1348 pf->used_umv_size++;
1352 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1353 const uint8_t *addr, bool is_mc)
1355 const unsigned char *mac_addr = addr;
1356 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1357 ((uint32_t)mac_addr[2] << 16) |
1358 ((uint32_t)mac_addr[1] << 8) |
1359 (uint32_t)mac_addr[0];
1360 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1362 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1364 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1365 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1366 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1369 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1370 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1374 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1376 enum hns3_mac_vlan_tbl_opcode op)
1379 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1384 if (op == HNS3_MAC_VLAN_ADD) {
1385 if (resp_code == 0 || resp_code == 1) {
1387 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1388 hns3_err(hw, "add mac addr failed for uc_overflow");
1390 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1391 hns3_err(hw, "add mac addr failed for mc_overflow");
1395 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1398 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1399 if (resp_code == 0) {
1401 } else if (resp_code == 1) {
1402 hns3_dbg(hw, "remove mac addr failed for miss");
1406 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1409 } else if (op == HNS3_MAC_VLAN_LKUP) {
1410 if (resp_code == 0) {
1412 } else if (resp_code == 1) {
1413 hns3_dbg(hw, "lookup mac addr failed for miss");
1417 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1422 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1429 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1430 struct hns3_mac_vlan_tbl_entry_cmd *req,
1431 struct hns3_cmd_desc *desc, bool is_mc)
1437 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1439 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1440 memcpy(desc[0].data, req,
1441 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1442 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1444 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1445 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1447 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1449 memcpy(desc[0].data, req,
1450 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1451 ret = hns3_cmd_send(hw, desc, 1);
1454 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1458 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1459 retval = rte_le_to_cpu_16(desc[0].retval);
1461 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1462 HNS3_MAC_VLAN_LKUP);
1466 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1467 struct hns3_mac_vlan_tbl_entry_cmd *req,
1468 struct hns3_cmd_desc *mc_desc)
1475 if (mc_desc == NULL) {
1476 struct hns3_cmd_desc desc;
1478 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1479 memcpy(desc.data, req,
1480 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1481 ret = hns3_cmd_send(hw, &desc, 1);
1482 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1483 retval = rte_le_to_cpu_16(desc.retval);
1485 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1488 hns3_cmd_reuse_desc(&mc_desc[0], false);
1489 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1490 hns3_cmd_reuse_desc(&mc_desc[1], false);
1491 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1492 hns3_cmd_reuse_desc(&mc_desc[2], false);
1493 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1494 memcpy(mc_desc[0].data, req,
1495 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1496 mc_desc[0].retval = 0;
1497 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1498 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1499 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1501 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1506 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1514 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1515 struct hns3_mac_vlan_tbl_entry_cmd *req)
1517 struct hns3_cmd_desc desc;
1522 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1524 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1526 ret = hns3_cmd_send(hw, &desc, 1);
1528 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1531 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1532 retval = rte_le_to_cpu_16(desc.retval);
1534 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1535 HNS3_MAC_VLAN_REMOVE);
1539 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1541 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1542 struct hns3_mac_vlan_tbl_entry_cmd req;
1543 struct hns3_pf *pf = &hns->pf;
1544 struct hns3_cmd_desc desc[3];
1545 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1546 uint16_t egress_port = 0;
1550 /* check if mac addr is valid */
1551 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1552 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1554 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1559 memset(&req, 0, sizeof(req));
1562 * In current version VF is not supported when PF is driven by DPDK
1563 * driver, just need to configure parameters for PF vport.
1565 vf_id = HNS3_PF_FUNC_ID;
1566 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1567 HNS3_MAC_EPORT_VFID_S, vf_id);
1569 req.egress_port = rte_cpu_to_le_16(egress_port);
1571 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1574 * Lookup the mac address in the mac_vlan table, and add
1575 * it if the entry is inexistent. Repeated unicast entry
1576 * is not allowed in the mac vlan table.
1578 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1579 if (ret == -ENOENT) {
1580 if (!hns3_is_umv_space_full(hw)) {
1581 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1583 hns3_update_umv_space(hw, false);
1587 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1592 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1594 /* check if we just hit the duplicate */
1596 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1600 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1607 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1609 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1610 struct rte_ether_addr *addr;
1614 for (i = 0; i < hw->mc_addrs_num; i++) {
1615 addr = &hw->mc_addrs[i];
1616 /* Check if there are duplicate addresses */
1617 if (rte_is_same_ether_addr(addr, mac_addr)) {
1618 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1620 hns3_err(hw, "failed to add mc mac addr, same addrs"
1621 "(%s) is added by the set_mc_mac_addr_list "
1627 ret = hns3_add_mc_addr(hw, mac_addr);
1629 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1631 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1638 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1640 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1643 ret = hns3_remove_mc_addr(hw, mac_addr);
1645 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1647 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1654 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1655 uint32_t idx, __rte_unused uint32_t pool)
1657 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1658 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1661 rte_spinlock_lock(&hw->lock);
1664 * In hns3 network engine adding UC and MC mac address with different
1665 * commands with firmware. We need to determine whether the input
1666 * address is a UC or a MC address to call different commands.
1667 * By the way, it is recommended calling the API function named
1668 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1669 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1670 * may affect the specifications of UC mac addresses.
1672 if (rte_is_multicast_ether_addr(mac_addr))
1673 ret = hns3_add_mc_addr_common(hw, mac_addr);
1675 ret = hns3_add_uc_addr_common(hw, mac_addr);
1678 rte_spinlock_unlock(&hw->lock);
1679 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1681 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1687 hw->mac.default_addr_setted = true;
1688 rte_spinlock_unlock(&hw->lock);
1694 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1696 struct hns3_mac_vlan_tbl_entry_cmd req;
1697 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1700 /* check if mac addr is valid */
1701 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1702 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1704 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1709 memset(&req, 0, sizeof(req));
1710 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1711 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1712 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1713 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1716 hns3_update_umv_space(hw, true);
1722 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1724 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1725 /* index will be checked by upper level rte interface */
1726 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1727 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1730 rte_spinlock_lock(&hw->lock);
1732 if (rte_is_multicast_ether_addr(mac_addr))
1733 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1735 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1736 rte_spinlock_unlock(&hw->lock);
1738 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1740 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1746 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1747 struct rte_ether_addr *mac_addr)
1749 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1750 struct rte_ether_addr *oaddr;
1751 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1752 bool default_addr_setted;
1753 bool rm_succes = false;
1757 * It has been guaranteed that input parameter named mac_addr is valid
1758 * address in the rte layer of DPDK framework.
1760 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1761 default_addr_setted = hw->mac.default_addr_setted;
1762 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1765 rte_spinlock_lock(&hw->lock);
1766 if (default_addr_setted) {
1767 ret = hns3_remove_uc_addr_common(hw, oaddr);
1769 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1771 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1778 ret = hns3_add_uc_addr_common(hw, mac_addr);
1780 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1782 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1783 goto err_add_uc_addr;
1786 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1788 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1789 goto err_pause_addr_cfg;
1792 rte_ether_addr_copy(mac_addr,
1793 (struct rte_ether_addr *)hw->mac.mac_addr);
1794 hw->mac.default_addr_setted = true;
1795 rte_spinlock_unlock(&hw->lock);
1800 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1802 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1805 "Failed to roll back to del setted mac addr(%s): %d",
1811 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1813 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1816 "Failed to restore old uc mac addr(%s): %d",
1818 hw->mac.default_addr_setted = false;
1821 rte_spinlock_unlock(&hw->lock);
1827 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1829 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1830 struct hns3_hw *hw = &hns->hw;
1831 struct rte_ether_addr *addr;
1836 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1837 addr = &hw->data->mac_addrs[i];
1838 if (rte_is_zero_ether_addr(addr))
1840 if (rte_is_multicast_ether_addr(addr))
1841 ret = del ? hns3_remove_mc_addr(hw, addr) :
1842 hns3_add_mc_addr(hw, addr);
1844 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1845 hns3_add_uc_addr_common(hw, addr);
1849 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1851 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1852 "ret = %d.", del ? "remove" : "restore",
1860 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1862 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1866 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1867 word_num = vfid / 32;
1868 bit_num = vfid % 32;
1870 desc[1].data[word_num] &=
1871 rte_cpu_to_le_32(~(1UL << bit_num));
1873 desc[1].data[word_num] |=
1874 rte_cpu_to_le_32(1UL << bit_num);
1876 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1877 bit_num = vfid % 32;
1879 desc[2].data[word_num] &=
1880 rte_cpu_to_le_32(~(1UL << bit_num));
1882 desc[2].data[word_num] |=
1883 rte_cpu_to_le_32(1UL << bit_num);
1888 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1890 struct hns3_mac_vlan_tbl_entry_cmd req;
1891 struct hns3_cmd_desc desc[3];
1892 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1896 /* Check if mac addr is valid */
1897 if (!rte_is_multicast_ether_addr(mac_addr)) {
1898 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1900 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1905 memset(&req, 0, sizeof(req));
1906 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1907 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1908 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1910 /* This mac addr do not exist, add new entry for it */
1911 memset(desc[0].data, 0, sizeof(desc[0].data));
1912 memset(desc[1].data, 0, sizeof(desc[0].data));
1913 memset(desc[2].data, 0, sizeof(desc[0].data));
1917 * In current version VF is not supported when PF is driven by DPDK
1918 * driver, just need to configure parameters for PF vport.
1920 vf_id = HNS3_PF_FUNC_ID;
1921 hns3_update_desc_vfid(desc, vf_id, false);
1922 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1925 hns3_err(hw, "mc mac vlan table is full");
1926 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1928 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1935 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1937 struct hns3_mac_vlan_tbl_entry_cmd req;
1938 struct hns3_cmd_desc desc[3];
1939 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1943 /* Check if mac addr is valid */
1944 if (!rte_is_multicast_ether_addr(mac_addr)) {
1945 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1947 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1952 memset(&req, 0, sizeof(req));
1953 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1954 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1955 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1958 * This mac addr exist, remove this handle's VFID for it.
1959 * In current version VF is not supported when PF is driven by
1960 * DPDK driver, just need to configure parameters for PF vport.
1962 vf_id = HNS3_PF_FUNC_ID;
1963 hns3_update_desc_vfid(desc, vf_id, true);
1965 /* All the vfid is zero, so need to delete this entry */
1966 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1967 } else if (ret == -ENOENT) {
1968 /* This mac addr doesn't exist. */
1973 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1975 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1982 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1983 struct rte_ether_addr *mc_addr_set,
1984 uint32_t nb_mc_addr)
1986 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1987 struct rte_ether_addr *addr;
1991 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1992 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1993 "invalid. valid range: 0~%d",
1994 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1998 /* Check if input mac addresses are valid */
1999 for (i = 0; i < nb_mc_addr; i++) {
2000 addr = &mc_addr_set[i];
2001 if (!rte_is_multicast_ether_addr(addr)) {
2002 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2005 "failed to set mc mac addr, addr(%s) invalid.",
2010 /* Check if there are duplicate addresses */
2011 for (j = i + 1; j < nb_mc_addr; j++) {
2012 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2013 hns3_ether_format_addr(mac_str,
2014 RTE_ETHER_ADDR_FMT_SIZE,
2016 hns3_err(hw, "failed to set mc mac addr, "
2017 "addrs invalid. two same addrs(%s).",
2024 * Check if there are duplicate addresses between mac_addrs
2027 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2028 if (rte_is_same_ether_addr(addr,
2029 &hw->data->mac_addrs[j])) {
2030 hns3_ether_format_addr(mac_str,
2031 RTE_ETHER_ADDR_FMT_SIZE,
2033 hns3_err(hw, "failed to set mc mac addr, "
2034 "addrs invalid. addrs(%s) has already "
2035 "configured in mac_addr add API",
2046 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2047 struct rte_ether_addr *mc_addr_set,
2049 struct rte_ether_addr *reserved_addr_list,
2050 int *reserved_addr_num,
2051 struct rte_ether_addr *add_addr_list,
2053 struct rte_ether_addr *rm_addr_list,
2056 struct rte_ether_addr *addr;
2057 int current_addr_num;
2058 int reserved_num = 0;
2066 /* Calculate the mc mac address list that should be removed */
2067 current_addr_num = hw->mc_addrs_num;
2068 for (i = 0; i < current_addr_num; i++) {
2069 addr = &hw->mc_addrs[i];
2071 for (j = 0; j < mc_addr_num; j++) {
2072 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2079 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2082 rte_ether_addr_copy(addr,
2083 &reserved_addr_list[reserved_num]);
2088 /* Calculate the mc mac address list that should be added */
2089 for (i = 0; i < mc_addr_num; i++) {
2090 addr = &mc_addr_set[i];
2092 for (j = 0; j < current_addr_num; j++) {
2093 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2100 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2105 /* Reorder the mc mac address list maintained by driver */
2106 for (i = 0; i < reserved_num; i++)
2107 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2109 for (i = 0; i < rm_num; i++) {
2110 num = reserved_num + i;
2111 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2114 *reserved_addr_num = reserved_num;
2115 *add_addr_num = add_num;
2116 *rm_addr_num = rm_num;
2120 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2121 struct rte_ether_addr *mc_addr_set,
2122 uint32_t nb_mc_addr)
2124 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2126 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2127 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2128 struct rte_ether_addr *addr;
2129 int reserved_addr_num;
2137 /* Check if input parameters are valid */
2138 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2142 rte_spinlock_lock(&hw->lock);
2145 * Calculate the mc mac address lists those should be removed and be
2146 * added, Reorder the mc mac address list maintained by driver.
2148 mc_addr_num = (int)nb_mc_addr;
2149 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2150 reserved_addr_list, &reserved_addr_num,
2151 add_addr_list, &add_addr_num,
2152 rm_addr_list, &rm_addr_num);
2154 /* Remove mc mac addresses */
2155 for (i = 0; i < rm_addr_num; i++) {
2156 num = rm_addr_num - i - 1;
2157 addr = &rm_addr_list[num];
2158 ret = hns3_remove_mc_addr(hw, addr);
2160 rte_spinlock_unlock(&hw->lock);
2166 /* Add mc mac addresses */
2167 for (i = 0; i < add_addr_num; i++) {
2168 addr = &add_addr_list[i];
2169 ret = hns3_add_mc_addr(hw, addr);
2171 rte_spinlock_unlock(&hw->lock);
2175 num = reserved_addr_num + i;
2176 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2179 rte_spinlock_unlock(&hw->lock);
2185 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2187 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2188 struct hns3_hw *hw = &hns->hw;
2189 struct rte_ether_addr *addr;
2194 for (i = 0; i < hw->mc_addrs_num; i++) {
2195 addr = &hw->mc_addrs[i];
2196 if (!rte_is_multicast_ether_addr(addr))
2199 ret = hns3_remove_mc_addr(hw, addr);
2201 ret = hns3_add_mc_addr(hw, addr);
2204 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2206 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2207 del ? "Remove" : "Restore", mac_str, ret);
2214 hns3_check_mq_mode(struct rte_eth_dev *dev)
2216 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2217 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2218 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2219 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2220 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2221 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2226 if ((rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG) ||
2227 (tx_mq_mode == ETH_MQ_TX_VMDQ_DCB ||
2228 tx_mq_mode == ETH_MQ_TX_VMDQ_ONLY)) {
2229 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
2230 rx_mq_mode, tx_mq_mode);
2234 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2235 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2236 if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
2237 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2238 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2239 dcb_rx_conf->nb_tcs, pf->tc_max);
2243 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2244 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2245 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2246 "nb_tcs(%d) != %d or %d in rx direction.",
2247 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2251 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2252 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2253 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2257 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2258 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2259 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2260 "is not equal to one in tx direction.",
2261 i, dcb_rx_conf->dcb_tc[i]);
2264 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2265 max_tc = dcb_rx_conf->dcb_tc[i];
2268 num_tc = max_tc + 1;
2269 if (num_tc > dcb_rx_conf->nb_tcs) {
2270 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2271 num_tc, dcb_rx_conf->nb_tcs);
2280 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2282 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2284 if (!hns3_dev_dcb_supported(hw)) {
2285 hns3_err(hw, "this port does not support dcb configurations.");
2289 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2290 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2298 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2299 enum hns3_ring_type queue_type, uint16_t queue_id)
2301 struct hns3_cmd_desc desc;
2302 struct hns3_ctrl_vector_chain_cmd *req =
2303 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2304 enum hns3_opcode_type op;
2305 uint16_t tqp_type_and_id = 0;
2310 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2311 hns3_cmd_setup_basic_desc(&desc, op, false);
2312 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2313 HNS3_TQP_INT_ID_L_S);
2314 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2315 HNS3_TQP_INT_ID_H_S);
2317 if (queue_type == HNS3_RING_TYPE_RX)
2318 gl = HNS3_RING_GL_RX;
2320 gl = HNS3_RING_GL_TX;
2324 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2326 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2327 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2329 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2330 req->int_cause_num = 1;
2331 ret = hns3_cmd_send(hw, &desc, 1);
2333 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2334 en ? "Map" : "Unmap", queue_id, vector_id, ret);
2342 hns3_init_ring_with_vector(struct hns3_hw *hw)
2349 * In hns3 network engine, vector 0 is always the misc interrupt of this
2350 * function, vector 1~N can be used respectively for the queues of the
2351 * function. Tx and Rx queues with the same number share the interrupt
2352 * vector. In the initialization clearing the all hardware mapping
2353 * relationship configurations between queues and interrupt vectors is
2354 * needed, so some error caused by the residual configurations, such as
2355 * the unexpected Tx interrupt, can be avoid.
2357 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2358 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2359 vec = vec - 1; /* the last interrupt is reserved */
2360 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2361 for (i = 0; i < hw->intr_tqps_num; i++) {
2363 * Set gap limiter/rate limiter/quanity limiter algorithm
2364 * configuration for interrupt coalesce of queue's interrupt.
2366 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2367 HNS3_TQP_INTR_GL_DEFAULT);
2368 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2369 HNS3_TQP_INTR_GL_DEFAULT);
2370 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2372 * QL(quantity limiter) is not used currently, just set 0 to
2375 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2377 ret = hns3_bind_ring_with_vector(hw, vec, false,
2378 HNS3_RING_TYPE_TX, i);
2380 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2381 "vector: %u, ret=%d", i, vec, ret);
2385 ret = hns3_bind_ring_with_vector(hw, vec, false,
2386 HNS3_RING_TYPE_RX, i);
2388 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2389 "vector: %u, ret=%d", i, vec, ret);
2398 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2400 struct hns3_adapter *hns = dev->data->dev_private;
2401 struct hns3_hw *hw = &hns->hw;
2402 uint32_t max_rx_pkt_len;
2406 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2410 * If jumbo frames are enabled, MTU needs to be refreshed
2411 * according to the maximum RX packet length.
2413 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2414 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2415 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2416 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2417 "and no more than %u when jumbo frame enabled.",
2418 (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2419 (uint16_t)HNS3_MAX_FRAME_LEN);
2423 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2424 ret = hns3_dev_mtu_set(dev, mtu);
2427 dev->data->mtu = mtu;
2433 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
2438 * Some hardware doesn't support auto-negotiation, but users may not
2439 * configure link_speeds (default 0), which means auto-negotiation.
2440 * In this case, a warning message need to be printed, instead of
2443 if (link_speeds == ETH_LINK_SPEED_AUTONEG &&
2444 hw->mac.support_autoneg == 0) {
2445 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
2449 if (link_speeds != ETH_LINK_SPEED_AUTONEG) {
2450 ret = hns3_check_port_speed(hw, link_speeds);
2459 hns3_check_dev_conf(struct rte_eth_dev *dev)
2461 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2462 struct rte_eth_conf *conf = &dev->data->dev_conf;
2465 ret = hns3_check_mq_mode(dev);
2469 return hns3_check_link_speed(hw, conf->link_speeds);
2473 hns3_dev_configure(struct rte_eth_dev *dev)
2475 struct hns3_adapter *hns = dev->data->dev_private;
2476 struct rte_eth_conf *conf = &dev->data->dev_conf;
2477 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2478 struct hns3_hw *hw = &hns->hw;
2479 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2480 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2481 struct rte_eth_rss_conf rss_conf;
2485 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2488 * Some versions of hardware network engine does not support
2489 * individually enable/disable/reset the Tx or Rx queue. These devices
2490 * must enable/disable/reset Tx and Rx queues at the same time. When the
2491 * numbers of Tx queues allocated by upper applications are not equal to
2492 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2493 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2494 * work as usual. But these fake queues are imperceptible, and can not
2495 * be used by upper applications.
2497 if (!hns3_dev_indep_txrx_supported(hw)) {
2498 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2500 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2506 hw->adapter_state = HNS3_NIC_CONFIGURING;
2507 ret = hns3_check_dev_conf(dev);
2511 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2512 ret = hns3_check_dcb_cfg(dev);
2517 /* When RSS is not configured, redirect the packet queue 0 */
2518 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2519 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2520 rss_conf = conf->rx_adv_conf.rss_conf;
2521 hw->rss_dis_flag = false;
2522 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2527 ret = hns3_refresh_mtu(dev, conf);
2531 ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2535 ret = hns3_dev_configure_vlan(dev);
2539 /* config hardware GRO */
2540 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2541 ret = hns3_config_gro(hw, gro_en);
2545 hns3_init_rx_ptype_tble(dev);
2546 hw->adapter_state = HNS3_NIC_CONFIGURED;
2551 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2552 hw->adapter_state = HNS3_NIC_INITIALIZED;
2558 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2560 struct hns3_config_max_frm_size_cmd *req;
2561 struct hns3_cmd_desc desc;
2563 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2565 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2566 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2567 req->min_frm_size = RTE_ETHER_MIN_LEN;
2569 return hns3_cmd_send(hw, &desc, 1);
2573 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2575 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2576 uint16_t original_mps = hns->pf.mps;
2580 ret = hns3_set_mac_mtu(hw, mps);
2582 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2587 ret = hns3_buffer_alloc(hw);
2589 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2596 err = hns3_set_mac_mtu(hw, original_mps);
2598 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2601 hns->pf.mps = original_mps;
2607 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2609 struct hns3_adapter *hns = dev->data->dev_private;
2610 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2611 struct hns3_hw *hw = &hns->hw;
2612 bool is_jumbo_frame;
2615 if (dev->data->dev_started) {
2616 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2617 "before configuration", dev->data->port_id);
2621 rte_spinlock_lock(&hw->lock);
2622 is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2623 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2626 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2627 * assign to "uint16_t" type variable.
2629 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2631 rte_spinlock_unlock(&hw->lock);
2632 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2633 dev->data->port_id, mtu, ret);
2638 dev->data->dev_conf.rxmode.offloads |=
2639 DEV_RX_OFFLOAD_JUMBO_FRAME;
2641 dev->data->dev_conf.rxmode.offloads &=
2642 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2643 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2644 rte_spinlock_unlock(&hw->lock);
2650 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2652 uint32_t speed_capa = 0;
2654 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2655 speed_capa |= ETH_LINK_SPEED_10M_HD;
2656 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2657 speed_capa |= ETH_LINK_SPEED_10M;
2658 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2659 speed_capa |= ETH_LINK_SPEED_100M_HD;
2660 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2661 speed_capa |= ETH_LINK_SPEED_100M;
2662 if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2663 speed_capa |= ETH_LINK_SPEED_1G;
2669 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2671 uint32_t speed_capa = 0;
2673 if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2674 speed_capa |= ETH_LINK_SPEED_1G;
2675 if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2676 speed_capa |= ETH_LINK_SPEED_10G;
2677 if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2678 speed_capa |= ETH_LINK_SPEED_25G;
2679 if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2680 speed_capa |= ETH_LINK_SPEED_40G;
2681 if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2682 speed_capa |= ETH_LINK_SPEED_50G;
2683 if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2684 speed_capa |= ETH_LINK_SPEED_100G;
2685 if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2686 speed_capa |= ETH_LINK_SPEED_200G;
2692 hns3_get_speed_capa(struct hns3_hw *hw)
2694 struct hns3_mac *mac = &hw->mac;
2695 uint32_t speed_capa;
2697 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2699 hns3_get_copper_port_speed_capa(mac->supported_speed);
2702 hns3_get_firber_port_speed_capa(mac->supported_speed);
2704 if (mac->support_autoneg == 0)
2705 speed_capa |= ETH_LINK_SPEED_FIXED;
2711 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2713 struct hns3_adapter *hns = eth_dev->data->dev_private;
2714 struct hns3_hw *hw = &hns->hw;
2715 uint16_t queue_num = hw->tqps_num;
2718 * In interrupt mode, 'max_rx_queues' is set based on the number of
2719 * MSI-X interrupt resources of the hardware.
2721 if (hw->data->dev_conf.intr_conf.rxq == 1)
2722 queue_num = hw->intr_tqps_num;
2724 info->max_rx_queues = queue_num;
2725 info->max_tx_queues = hw->tqps_num;
2726 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2727 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2728 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2729 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2730 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2731 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2732 DEV_RX_OFFLOAD_TCP_CKSUM |
2733 DEV_RX_OFFLOAD_UDP_CKSUM |
2734 DEV_RX_OFFLOAD_SCTP_CKSUM |
2735 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2736 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2737 DEV_RX_OFFLOAD_KEEP_CRC |
2738 DEV_RX_OFFLOAD_SCATTER |
2739 DEV_RX_OFFLOAD_VLAN_STRIP |
2740 DEV_RX_OFFLOAD_VLAN_FILTER |
2741 DEV_RX_OFFLOAD_JUMBO_FRAME |
2742 DEV_RX_OFFLOAD_RSS_HASH |
2743 DEV_RX_OFFLOAD_TCP_LRO);
2744 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2745 DEV_TX_OFFLOAD_IPV4_CKSUM |
2746 DEV_TX_OFFLOAD_TCP_CKSUM |
2747 DEV_TX_OFFLOAD_UDP_CKSUM |
2748 DEV_TX_OFFLOAD_SCTP_CKSUM |
2749 DEV_TX_OFFLOAD_MULTI_SEGS |
2750 DEV_TX_OFFLOAD_TCP_TSO |
2751 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2752 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2753 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2754 DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2755 hns3_txvlan_cap_get(hw));
2757 if (hns3_dev_outer_udp_cksum_supported(hw))
2758 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2760 if (hns3_dev_indep_txrx_supported(hw))
2761 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2762 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2764 if (hns3_dev_ptp_supported(hw))
2765 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2767 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2768 .nb_max = HNS3_MAX_RING_DESC,
2769 .nb_min = HNS3_MIN_RING_DESC,
2770 .nb_align = HNS3_ALIGN_RING_DESC,
2773 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2774 .nb_max = HNS3_MAX_RING_DESC,
2775 .nb_min = HNS3_MIN_RING_DESC,
2776 .nb_align = HNS3_ALIGN_RING_DESC,
2777 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2778 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2781 info->speed_capa = hns3_get_speed_capa(hw);
2782 info->default_rxconf = (struct rte_eth_rxconf) {
2783 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2785 * If there are no available Rx buffer descriptors, incoming
2786 * packets are always dropped by hardware based on hns3 network
2792 info->default_txconf = (struct rte_eth_txconf) {
2793 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2797 info->vmdq_queue_num = 0;
2799 info->reta_size = hw->rss_ind_tbl_size;
2800 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2801 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2803 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2804 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2805 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2806 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2807 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2808 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2814 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2817 struct hns3_adapter *hns = eth_dev->data->dev_private;
2818 struct hns3_hw *hw = &hns->hw;
2819 uint32_t version = hw->fw_version;
2822 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2823 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2824 HNS3_FW_VERSION_BYTE3_S),
2825 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2826 HNS3_FW_VERSION_BYTE2_S),
2827 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2828 HNS3_FW_VERSION_BYTE1_S),
2829 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2830 HNS3_FW_VERSION_BYTE0_S));
2834 ret += 1; /* add the size of '\0' */
2835 if (fw_size < (size_t)ret)
2842 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2844 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2847 (void)hns3_update_link_status(hw);
2849 ret = hns3_update_link_info(eth_dev);
2851 hw->mac.link_status = ETH_LINK_DOWN;
2857 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2858 struct rte_eth_link *new_link)
2860 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2861 struct hns3_mac *mac = &hw->mac;
2863 switch (mac->link_speed) {
2864 case ETH_SPEED_NUM_10M:
2865 case ETH_SPEED_NUM_100M:
2866 case ETH_SPEED_NUM_1G:
2867 case ETH_SPEED_NUM_10G:
2868 case ETH_SPEED_NUM_25G:
2869 case ETH_SPEED_NUM_40G:
2870 case ETH_SPEED_NUM_50G:
2871 case ETH_SPEED_NUM_100G:
2872 case ETH_SPEED_NUM_200G:
2873 new_link->link_speed = mac->link_speed;
2876 if (mac->link_status)
2877 new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2879 new_link->link_speed = ETH_SPEED_NUM_NONE;
2883 new_link->link_duplex = mac->link_duplex;
2884 new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2885 new_link->link_autoneg = mac->link_autoneg;
2889 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2891 #define HNS3_LINK_CHECK_INTERVAL 100 /* 100ms */
2892 #define HNS3_MAX_LINK_CHECK_TIMES 20 /* 2s (100 * 20ms) in total */
2894 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2895 uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2896 struct hns3_mac *mac = &hw->mac;
2897 struct rte_eth_link new_link;
2901 ret = hns3_update_port_link_info(eth_dev);
2903 hns3_err(hw, "failed to get port link info, ret = %d.",
2908 if (!wait_to_complete || mac->link_status == ETH_LINK_UP)
2911 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2912 } while (retry_cnt--);
2914 memset(&new_link, 0, sizeof(new_link));
2915 hns3_setup_linkstatus(eth_dev, &new_link);
2917 return rte_eth_linkstatus_set(eth_dev, &new_link);
2921 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2923 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2924 struct hns3_pf *pf = &hns->pf;
2926 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2929 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2935 hns3_query_function_status(struct hns3_hw *hw)
2937 #define HNS3_QUERY_MAX_CNT 10
2938 #define HNS3_QUERY_SLEEP_MSCOEND 1
2939 struct hns3_func_status_cmd *req;
2940 struct hns3_cmd_desc desc;
2944 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2945 req = (struct hns3_func_status_cmd *)desc.data;
2948 ret = hns3_cmd_send(hw, &desc, 1);
2950 PMD_INIT_LOG(ERR, "query function status failed %d",
2955 /* Check pf reset is done */
2959 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2960 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2962 return hns3_parse_func_status(hw, req);
2966 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2968 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2969 struct hns3_pf *pf = &hns->pf;
2971 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2973 * The total_tqps_num obtained from firmware is maximum tqp
2974 * numbers of this port, which should be used for PF and VFs.
2975 * There is no need for pf to have so many tqp numbers in
2976 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2977 * coming from config file, is assigned to maximum queue number
2978 * for the PF of this port by user. So users can modify the
2979 * maximum queue number of PF according to their own application
2980 * scenarios, which is more flexible to use. In addition, many
2981 * memories can be saved due to allocating queue statistics
2982 * room according to the actual number of queues required. The
2983 * maximum queue number of PF for network engine with
2984 * revision_id greater than 0x30 is assigned by config file.
2986 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2987 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2988 "must be greater than 0.",
2989 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2993 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2994 hw->total_tqps_num);
2997 * Due to the limitation on the number of PF interrupts
2998 * available, the maximum queue number assigned to PF on
2999 * the network engine with revision_id 0x21 is 64.
3001 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
3002 HNS3_MAX_TQP_NUM_HIP08_PF);
3009 hns3_query_pf_resource(struct hns3_hw *hw)
3011 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3012 struct hns3_pf *pf = &hns->pf;
3013 struct hns3_pf_res_cmd *req;
3014 struct hns3_cmd_desc desc;
3017 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
3018 ret = hns3_cmd_send(hw, &desc, 1);
3020 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
3024 req = (struct hns3_pf_res_cmd *)desc.data;
3025 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
3026 rte_le_to_cpu_16(req->ext_tqp_num);
3027 ret = hns3_get_pf_max_tqp_num(hw);
3031 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
3032 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
3034 if (req->tx_buf_size)
3036 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
3038 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
3040 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
3042 if (req->dv_buf_size)
3044 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3046 pf->dv_buf_size = HNS3_DEFAULT_DV;
3048 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3051 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3052 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3058 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3060 struct hns3_cfg_param_cmd *req;
3061 uint64_t mac_addr_tmp_high;
3062 uint8_t ext_rss_size_max;
3063 uint64_t mac_addr_tmp;
3066 req = (struct hns3_cfg_param_cmd *)desc[0].data;
3068 /* get the configuration */
3069 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3070 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
3071 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3072 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3073 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3074 HNS3_CFG_TQP_DESC_N_M,
3075 HNS3_CFG_TQP_DESC_N_S);
3077 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3078 HNS3_CFG_PHY_ADDR_M,
3079 HNS3_CFG_PHY_ADDR_S);
3080 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3081 HNS3_CFG_MEDIA_TP_M,
3082 HNS3_CFG_MEDIA_TP_S);
3083 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3084 HNS3_CFG_RX_BUF_LEN_M,
3085 HNS3_CFG_RX_BUF_LEN_S);
3086 /* get mac address */
3087 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3088 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3089 HNS3_CFG_MAC_ADDR_H_M,
3090 HNS3_CFG_MAC_ADDR_H_S);
3092 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3094 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3095 HNS3_CFG_DEFAULT_SPEED_M,
3096 HNS3_CFG_DEFAULT_SPEED_S);
3097 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3098 HNS3_CFG_RSS_SIZE_M,
3099 HNS3_CFG_RSS_SIZE_S);
3101 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3102 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3104 req = (struct hns3_cfg_param_cmd *)desc[1].data;
3105 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3107 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3108 HNS3_CFG_SPEED_ABILITY_M,
3109 HNS3_CFG_SPEED_ABILITY_S);
3110 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3111 HNS3_CFG_UMV_TBL_SPACE_M,
3112 HNS3_CFG_UMV_TBL_SPACE_S);
3113 if (!cfg->umv_space)
3114 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3116 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3117 HNS3_CFG_EXT_RSS_SIZE_M,
3118 HNS3_CFG_EXT_RSS_SIZE_S);
3121 * Field ext_rss_size_max obtained from firmware will be more flexible
3122 * for future changes and expansions, which is an exponent of 2, instead
3123 * of reading out directly. If this field is not zero, hns3 PF PMD
3124 * driver uses it as rss_size_max under one TC. Device, whose revision
3125 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3126 * maximum number of queues supported under a TC through this field.
3128 if (ext_rss_size_max)
3129 cfg->rss_size_max = 1U << ext_rss_size_max;
3132 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3133 * @hw: pointer to struct hns3_hw
3134 * @hcfg: the config structure to be getted
3137 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3139 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3140 struct hns3_cfg_param_cmd *req;
3145 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3147 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3148 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3150 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3151 i * HNS3_CFG_RD_LEN_BYTES);
3152 /* Len should be divided by 4 when send to hardware */
3153 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3154 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3155 req->offset = rte_cpu_to_le_32(offset);
3158 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3160 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3164 hns3_parse_cfg(hcfg, desc);
3170 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3172 switch (speed_cmd) {
3173 case HNS3_CFG_SPEED_10M:
3174 *speed = ETH_SPEED_NUM_10M;
3176 case HNS3_CFG_SPEED_100M:
3177 *speed = ETH_SPEED_NUM_100M;
3179 case HNS3_CFG_SPEED_1G:
3180 *speed = ETH_SPEED_NUM_1G;
3182 case HNS3_CFG_SPEED_10G:
3183 *speed = ETH_SPEED_NUM_10G;
3185 case HNS3_CFG_SPEED_25G:
3186 *speed = ETH_SPEED_NUM_25G;
3188 case HNS3_CFG_SPEED_40G:
3189 *speed = ETH_SPEED_NUM_40G;
3191 case HNS3_CFG_SPEED_50G:
3192 *speed = ETH_SPEED_NUM_50G;
3194 case HNS3_CFG_SPEED_100G:
3195 *speed = ETH_SPEED_NUM_100G;
3197 case HNS3_CFG_SPEED_200G:
3198 *speed = ETH_SPEED_NUM_200G;
3208 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3210 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3211 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3212 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3213 hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3214 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3218 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3220 struct hns3_dev_specs_0_cmd *req0;
3222 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3224 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3225 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3226 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3227 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3228 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3232 hns3_check_dev_specifications(struct hns3_hw *hw)
3234 if (hw->rss_ind_tbl_size == 0 ||
3235 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3236 hns3_err(hw, "the size of hash lookup table configured (%u)"
3237 " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3238 HNS3_RSS_IND_TBL_SIZE_MAX);
3246 hns3_query_dev_specifications(struct hns3_hw *hw)
3248 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3252 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3253 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3255 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3257 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3259 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3263 hns3_parse_dev_specifications(hw, desc);
3265 return hns3_check_dev_specifications(hw);
3269 hns3_get_capability(struct hns3_hw *hw)
3271 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3272 struct rte_pci_device *pci_dev;
3273 struct hns3_pf *pf = &hns->pf;
3274 struct rte_eth_dev *eth_dev;
3279 eth_dev = &rte_eth_devices[hw->data->port_id];
3280 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3281 device_id = pci_dev->id.device_id;
3283 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3284 device_id == HNS3_DEV_ID_50GE_RDMA ||
3285 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3286 device_id == HNS3_DEV_ID_200G_RDMA)
3287 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3289 /* Get PCI revision id */
3290 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3291 HNS3_PCI_REVISION_ID);
3292 if (ret != HNS3_PCI_REVISION_ID_LEN) {
3293 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3297 hw->revision = revision;
3299 if (revision < PCI_REVISION_ID_HIP09_A) {
3300 hns3_set_default_dev_specifications(hw);
3301 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3302 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3303 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3304 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3305 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3306 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3307 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3308 hw->rss_info.ipv6_sctp_offload_supported = false;
3309 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3313 ret = hns3_query_dev_specifications(hw);
3316 "failed to query dev specifications, ret = %d",
3321 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3322 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3323 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3324 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3325 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3326 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3327 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3328 hw->rss_info.ipv6_sctp_offload_supported = true;
3329 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3335 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3339 switch (media_type) {
3340 case HNS3_MEDIA_TYPE_COPPER:
3341 if (!hns3_dev_copper_supported(hw)) {
3343 "Media type is copper, not supported.");
3349 case HNS3_MEDIA_TYPE_FIBER:
3352 case HNS3_MEDIA_TYPE_BACKPLANE:
3353 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3357 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3366 hns3_get_board_configuration(struct hns3_hw *hw)
3368 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3369 struct hns3_pf *pf = &hns->pf;
3370 struct hns3_cfg cfg;
3373 ret = hns3_get_board_cfg(hw, &cfg);
3375 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3379 ret = hns3_check_media_type(hw, cfg.media_type);
3383 hw->mac.media_type = cfg.media_type;
3384 hw->rss_size_max = cfg.rss_size_max;
3385 hw->rss_dis_flag = false;
3386 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3387 hw->mac.phy_addr = cfg.phy_addr;
3388 hw->mac.default_addr_setted = false;
3389 hw->num_tx_desc = cfg.tqp_desc_num;
3390 hw->num_rx_desc = cfg.tqp_desc_num;
3391 hw->dcb_info.num_pg = 1;
3392 hw->dcb_info.hw_pfc_map = 0;
3394 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3396 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3397 cfg.default_speed, ret);
3401 pf->tc_max = cfg.tc_num;
3402 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3403 PMD_INIT_LOG(WARNING,
3404 "Get TC num(%u) from flash, set TC num to 1",
3409 /* Dev does not support DCB */
3410 if (!hns3_dev_dcb_supported(hw)) {
3414 pf->pfc_max = pf->tc_max;
3416 hw->dcb_info.num_tc = 1;
3417 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3418 hw->tqps_num / hw->dcb_info.num_tc);
3419 hns3_set_bit(hw->hw_tc_map, 0, 1);
3420 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3422 pf->wanted_umv_size = cfg.umv_space;
3428 hns3_get_configuration(struct hns3_hw *hw)
3432 ret = hns3_query_function_status(hw);
3434 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3438 /* Get device capability */
3439 ret = hns3_get_capability(hw);
3441 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3445 /* Get pf resource */
3446 ret = hns3_query_pf_resource(hw);
3448 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3452 ret = hns3_get_board_configuration(hw);
3454 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3458 ret = hns3_query_dev_fec_info(hw);
3461 "failed to query FEC information, ret = %d", ret);
3467 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3468 uint16_t tqp_vid, bool is_pf)
3470 struct hns3_tqp_map_cmd *req;
3471 struct hns3_cmd_desc desc;
3474 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3476 req = (struct hns3_tqp_map_cmd *)desc.data;
3477 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3478 req->tqp_vf = func_id;
3479 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3481 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3482 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3484 ret = hns3_cmd_send(hw, &desc, 1);
3486 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3492 hns3_map_tqp(struct hns3_hw *hw)
3498 * In current version, VF is not supported when PF is driven by DPDK
3499 * driver, so we assign total tqps_num tqps allocated to this port
3502 for (i = 0; i < hw->total_tqps_num; i++) {
3503 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3512 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3514 struct hns3_config_mac_speed_dup_cmd *req;
3515 struct hns3_cmd_desc desc;
3518 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3520 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3522 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3525 case ETH_SPEED_NUM_10M:
3526 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3527 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3529 case ETH_SPEED_NUM_100M:
3530 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3531 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3533 case ETH_SPEED_NUM_1G:
3534 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3535 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3537 case ETH_SPEED_NUM_10G:
3538 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3539 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3541 case ETH_SPEED_NUM_25G:
3542 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3543 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3545 case ETH_SPEED_NUM_40G:
3546 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3547 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3549 case ETH_SPEED_NUM_50G:
3550 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3551 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3553 case ETH_SPEED_NUM_100G:
3554 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3555 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3557 case ETH_SPEED_NUM_200G:
3558 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3559 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3562 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3566 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3568 ret = hns3_cmd_send(hw, &desc, 1);
3570 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3576 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3578 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3579 struct hns3_pf *pf = &hns->pf;
3580 struct hns3_priv_buf *priv;
3581 uint32_t i, total_size;
3583 total_size = pf->pkt_buf_size;
3585 /* alloc tx buffer for all enabled tc */
3586 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3587 priv = &buf_alloc->priv_buf[i];
3589 if (hw->hw_tc_map & BIT(i)) {
3590 if (total_size < pf->tx_buf_size)
3593 priv->tx_buf_size = pf->tx_buf_size;
3595 priv->tx_buf_size = 0;
3597 total_size -= priv->tx_buf_size;
3604 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3606 /* TX buffer size is unit by 128 byte */
3607 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3608 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3609 struct hns3_tx_buff_alloc_cmd *req;
3610 struct hns3_cmd_desc desc;
3615 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3617 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3618 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3619 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3621 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3622 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3623 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3626 ret = hns3_cmd_send(hw, &desc, 1);
3628 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3634 hns3_get_tc_num(struct hns3_hw *hw)
3639 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3640 if (hw->hw_tc_map & BIT(i))
3646 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3648 struct hns3_priv_buf *priv;
3649 uint32_t rx_priv = 0;
3652 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3653 priv = &buf_alloc->priv_buf[i];
3655 rx_priv += priv->buf_size;
3661 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3663 uint32_t total_tx_size = 0;
3666 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3667 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3669 return total_tx_size;
3672 /* Get the number of pfc enabled TCs, which have private buffer */
3674 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3676 struct hns3_priv_buf *priv;
3680 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3681 priv = &buf_alloc->priv_buf[i];
3682 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3689 /* Get the number of pfc disabled TCs, which have private buffer */
3691 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3692 struct hns3_pkt_buf_alloc *buf_alloc)
3694 struct hns3_priv_buf *priv;
3698 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3699 priv = &buf_alloc->priv_buf[i];
3700 if (hw->hw_tc_map & BIT(i) &&
3701 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3709 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3712 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3713 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3714 struct hns3_pf *pf = &hns->pf;
3715 uint32_t shared_buf, aligned_mps;
3720 tc_num = hns3_get_tc_num(hw);
3721 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3723 if (hns3_dev_dcb_supported(hw))
3724 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3727 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3730 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3731 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3732 HNS3_BUF_SIZE_UNIT);
3734 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3735 if (rx_all < rx_priv + shared_std)
3738 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3739 buf_alloc->s_buf.buf_size = shared_buf;
3740 if (hns3_dev_dcb_supported(hw)) {
3741 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3742 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3743 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3744 HNS3_BUF_SIZE_UNIT);
3746 buf_alloc->s_buf.self.high =
3747 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3748 buf_alloc->s_buf.self.low = aligned_mps;
3751 if (hns3_dev_dcb_supported(hw)) {
3752 hi_thrd = shared_buf - pf->dv_buf_size;
3754 if (tc_num <= NEED_RESERVE_TC_NUM)
3755 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3759 hi_thrd = hi_thrd / tc_num;
3761 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3762 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3763 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3765 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3766 lo_thrd = aligned_mps;
3769 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3770 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3771 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3778 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3779 struct hns3_pkt_buf_alloc *buf_alloc)
3781 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3782 struct hns3_pf *pf = &hns->pf;
3783 struct hns3_priv_buf *priv;
3784 uint32_t aligned_mps;
3788 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3789 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3791 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3792 priv = &buf_alloc->priv_buf[i];
3799 if (!(hw->hw_tc_map & BIT(i)))
3803 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3804 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3805 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3806 HNS3_BUF_SIZE_UNIT);
3809 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3813 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3816 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3820 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3821 struct hns3_pkt_buf_alloc *buf_alloc)
3823 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3824 struct hns3_pf *pf = &hns->pf;
3825 struct hns3_priv_buf *priv;
3826 int no_pfc_priv_num;
3831 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3832 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3834 /* let the last to be cleared first */
3835 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3836 priv = &buf_alloc->priv_buf[i];
3837 mask = BIT((uint8_t)i);
3839 if (hw->hw_tc_map & mask &&
3840 !(hw->dcb_info.hw_pfc_map & mask)) {
3841 /* Clear the no pfc TC private buffer */
3849 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3850 no_pfc_priv_num == 0)
3854 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3858 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3859 struct hns3_pkt_buf_alloc *buf_alloc)
3861 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3862 struct hns3_pf *pf = &hns->pf;
3863 struct hns3_priv_buf *priv;
3869 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3870 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3872 /* let the last to be cleared first */
3873 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3874 priv = &buf_alloc->priv_buf[i];
3875 mask = BIT((uint8_t)i);
3876 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3877 /* Reduce the number of pfc TC with private buffer */
3884 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3889 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3893 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3894 struct hns3_pkt_buf_alloc *buf_alloc)
3896 #define COMPENSATE_BUFFER 0x3C00
3897 #define COMPENSATE_HALF_MPS_NUM 5
3898 #define PRIV_WL_GAP 0x1800
3899 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3900 struct hns3_pf *pf = &hns->pf;
3901 uint32_t tc_num = hns3_get_tc_num(hw);
3902 uint32_t half_mps = pf->mps >> 1;
3903 struct hns3_priv_buf *priv;
3904 uint32_t min_rx_priv;
3908 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3910 rx_priv = rx_priv / tc_num;
3912 if (tc_num <= NEED_RESERVE_TC_NUM)
3913 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3916 * Minimum value of private buffer in rx direction (min_rx_priv) is
3917 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3918 * buffer if rx_priv is greater than min_rx_priv.
3920 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3921 COMPENSATE_HALF_MPS_NUM * half_mps;
3922 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3923 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3925 if (rx_priv < min_rx_priv)
3928 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3929 priv = &buf_alloc->priv_buf[i];
3935 if (!(hw->hw_tc_map & BIT(i)))
3939 priv->buf_size = rx_priv;
3940 priv->wl.high = rx_priv - pf->dv_buf_size;
3941 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3944 buf_alloc->s_buf.buf_size = 0;
3950 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3951 * @hw: pointer to struct hns3_hw
3952 * @buf_alloc: pointer to buffer calculation data
3953 * @return: 0: calculate sucessful, negative: fail
3956 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3958 /* When DCB is not supported, rx private buffer is not allocated. */
3959 if (!hns3_dev_dcb_supported(hw)) {
3960 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3961 struct hns3_pf *pf = &hns->pf;
3962 uint32_t rx_all = pf->pkt_buf_size;
3964 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3965 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3972 * Try to allocate privated packet buffer for all TCs without share
3975 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3979 * Try to allocate privated packet buffer for all TCs with share
3982 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3986 * For different application scenes, the enabled port number, TC number
3987 * and no_drop TC number are different. In order to obtain the better
3988 * performance, software could allocate the buffer size and configure
3989 * the waterline by trying to decrease the private buffer size according
3990 * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
3993 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3996 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3999 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
4006 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4008 struct hns3_rx_priv_buff_cmd *req;
4009 struct hns3_cmd_desc desc;
4014 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
4015 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
4017 /* Alloc private buffer TCs */
4018 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4019 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
4022 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
4023 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
4026 buf_size = buf_alloc->s_buf.buf_size;
4027 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
4028 (1 << HNS3_TC0_PRI_BUF_EN_B));
4030 ret = hns3_cmd_send(hw, &desc, 1);
4032 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
4038 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4040 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
4041 struct hns3_rx_priv_wl_buf *req;
4042 struct hns3_priv_buf *priv;
4043 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4047 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4048 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4050 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4052 /* The first descriptor set the NEXT bit to 1 */
4054 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4056 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4058 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4059 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4061 priv = &buf_alloc->priv_buf[idx];
4062 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4064 req->tc_wl[j].high |=
4065 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4066 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4068 req->tc_wl[j].low |=
4069 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4073 /* Send 2 descriptor at one time */
4074 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4076 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4082 hns3_common_thrd_config(struct hns3_hw *hw,
4083 struct hns3_pkt_buf_alloc *buf_alloc)
4085 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4086 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4087 struct hns3_rx_com_thrd *req;
4088 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4089 struct hns3_tc_thrd *tc;
4094 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4095 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4097 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4099 /* The first descriptor set the NEXT bit to 1 */
4101 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4103 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4105 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4106 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4107 tc = &s_buf->tc_thrd[tc_idx];
4109 req->com_thrd[j].high =
4110 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4111 req->com_thrd[j].high |=
4112 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4113 req->com_thrd[j].low =
4114 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4115 req->com_thrd[j].low |=
4116 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4120 /* Send 2 descriptors at one time */
4121 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4123 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4129 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4131 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4132 struct hns3_rx_com_wl *req;
4133 struct hns3_cmd_desc desc;
4136 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4138 req = (struct hns3_rx_com_wl *)desc.data;
4139 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4140 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4142 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4143 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4145 ret = hns3_cmd_send(hw, &desc, 1);
4147 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4153 hns3_buffer_alloc(struct hns3_hw *hw)
4155 struct hns3_pkt_buf_alloc pkt_buf;
4158 memset(&pkt_buf, 0, sizeof(pkt_buf));
4159 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4162 "could not calc tx buffer size for all TCs %d",
4167 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4169 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4173 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4176 "could not calc rx priv buffer size for all TCs %d",
4181 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4183 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4187 if (hns3_dev_dcb_supported(hw)) {
4188 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4191 "could not configure rx private waterline %d",
4196 ret = hns3_common_thrd_config(hw, &pkt_buf);
4199 "could not configure common threshold %d",
4205 ret = hns3_common_wl_config(hw, &pkt_buf);
4207 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4214 hns3_mac_init(struct hns3_hw *hw)
4216 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4217 struct hns3_mac *mac = &hw->mac;
4218 struct hns3_pf *pf = &hns->pf;
4221 pf->support_sfp_query = true;
4222 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4223 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4225 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4229 mac->link_status = ETH_LINK_DOWN;
4231 return hns3_config_mtu(hw, pf->mps);
4235 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4237 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
4238 #define HNS3_ETHERTYPE_ALREADY_ADD 1
4239 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
4240 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
4245 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4250 switch (resp_code) {
4251 case HNS3_ETHERTYPE_SUCCESS_ADD:
4252 case HNS3_ETHERTYPE_ALREADY_ADD:
4255 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4257 "add mac ethertype failed for manager table overflow.");
4258 return_status = -EIO;
4260 case HNS3_ETHERTYPE_KEY_CONFLICT:
4261 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4262 return_status = -EIO;
4266 "add mac ethertype failed for undefined, code=%u.",
4268 return_status = -EIO;
4272 return return_status;
4276 hns3_add_mgr_tbl(struct hns3_hw *hw,
4277 const struct hns3_mac_mgr_tbl_entry_cmd *req)
4279 struct hns3_cmd_desc desc;
4284 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4285 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4287 ret = hns3_cmd_send(hw, &desc, 1);
4290 "add mac ethertype failed for cmd_send, ret =%d.",
4295 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4296 retval = rte_le_to_cpu_16(desc.retval);
4298 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4302 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4303 int *table_item_num)
4305 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4308 * In current version, we add one item in management table as below:
4309 * 0x0180C200000E -- LLDP MC address
4312 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4313 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4314 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4315 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4316 tbl->i_port_bitmap = 0x1;
4317 *table_item_num = 1;
4321 hns3_init_mgr_tbl(struct hns3_hw *hw)
4323 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
4324 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4329 memset(mgr_table, 0, sizeof(mgr_table));
4330 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4331 for (i = 0; i < table_item_num; i++) {
4332 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4334 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4344 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4345 bool en_mc, bool en_bc, int vport_id)
4350 memset(param, 0, sizeof(struct hns3_promisc_param));
4352 param->enable = HNS3_PROMISC_EN_UC;
4354 param->enable |= HNS3_PROMISC_EN_MC;
4356 param->enable |= HNS3_PROMISC_EN_BC;
4357 param->vf_id = vport_id;
4361 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4363 struct hns3_promisc_cfg_cmd *req;
4364 struct hns3_cmd_desc desc;
4367 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4369 req = (struct hns3_promisc_cfg_cmd *)desc.data;
4370 req->vf_id = param->vf_id;
4371 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4372 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4374 ret = hns3_cmd_send(hw, &desc, 1);
4376 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4382 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4384 struct hns3_promisc_param param;
4385 bool en_bc_pmc = true;
4389 * In current version VF is not supported when PF is driven by DPDK
4390 * driver, just need to configure parameters for PF vport.
4392 vf_id = HNS3_PF_FUNC_ID;
4394 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4395 return hns3_cmd_set_promisc_mode(hw, ¶m);
4399 hns3_promisc_init(struct hns3_hw *hw)
4401 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4402 struct hns3_pf *pf = &hns->pf;
4403 struct hns3_promisc_param param;
4407 ret = hns3_set_promisc_mode(hw, false, false);
4409 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4414 * In current version VFs are not supported when PF is driven by DPDK
4415 * driver. After PF has been taken over by DPDK, the original VF will
4416 * be invalid. So, there is a possibility of entry residues. It should
4417 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4420 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4421 hns3_promisc_param_init(¶m, false, false, false, func_id);
4422 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4424 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4425 " ret = %d", func_id, ret);
4434 hns3_promisc_uninit(struct hns3_hw *hw)
4436 struct hns3_promisc_param param;
4440 func_id = HNS3_PF_FUNC_ID;
4443 * In current version VFs are not supported when PF is driven by
4444 * DPDK driver, and VFs' promisc mode status has been cleared during
4445 * init and their status will not change. So just clear PF's promisc
4446 * mode status during uninit.
4448 hns3_promisc_param_init(¶m, false, false, false, func_id);
4449 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4451 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4452 " uninit, ret = %d", ret);
4456 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4458 bool allmulti = dev->data->all_multicast ? true : false;
4459 struct hns3_adapter *hns = dev->data->dev_private;
4460 struct hns3_hw *hw = &hns->hw;
4465 rte_spinlock_lock(&hw->lock);
4466 ret = hns3_set_promisc_mode(hw, true, true);
4468 rte_spinlock_unlock(&hw->lock);
4469 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4475 * When promiscuous mode was enabled, disable the vlan filter to let
4476 * all packets coming in in the receiving direction.
4478 offloads = dev->data->dev_conf.rxmode.offloads;
4479 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4480 ret = hns3_enable_vlan_filter(hns, false);
4482 hns3_err(hw, "failed to enable promiscuous mode due to "
4483 "failure to disable vlan filter, ret = %d",
4485 err = hns3_set_promisc_mode(hw, false, allmulti);
4487 hns3_err(hw, "failed to restore promiscuous "
4488 "status after disable vlan filter "
4489 "failed during enabling promiscuous "
4490 "mode, ret = %d", ret);
4494 rte_spinlock_unlock(&hw->lock);
4500 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4502 bool allmulti = dev->data->all_multicast ? true : false;
4503 struct hns3_adapter *hns = dev->data->dev_private;
4504 struct hns3_hw *hw = &hns->hw;
4509 /* If now in all_multicast mode, must remain in all_multicast mode. */
4510 rte_spinlock_lock(&hw->lock);
4511 ret = hns3_set_promisc_mode(hw, false, allmulti);
4513 rte_spinlock_unlock(&hw->lock);
4514 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4518 /* when promiscuous mode was disabled, restore the vlan filter status */
4519 offloads = dev->data->dev_conf.rxmode.offloads;
4520 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4521 ret = hns3_enable_vlan_filter(hns, true);
4523 hns3_err(hw, "failed to disable promiscuous mode due to"
4524 " failure to restore vlan filter, ret = %d",
4526 err = hns3_set_promisc_mode(hw, true, true);
4528 hns3_err(hw, "failed to restore promiscuous "
4529 "status after enabling vlan filter "
4530 "failed during disabling promiscuous "
4531 "mode, ret = %d", ret);
4534 rte_spinlock_unlock(&hw->lock);
4540 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4542 struct hns3_adapter *hns = dev->data->dev_private;
4543 struct hns3_hw *hw = &hns->hw;
4546 if (dev->data->promiscuous)
4549 rte_spinlock_lock(&hw->lock);
4550 ret = hns3_set_promisc_mode(hw, false, true);
4551 rte_spinlock_unlock(&hw->lock);
4553 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4560 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4562 struct hns3_adapter *hns = dev->data->dev_private;
4563 struct hns3_hw *hw = &hns->hw;
4566 /* If now in promiscuous mode, must remain in all_multicast mode. */
4567 if (dev->data->promiscuous)
4570 rte_spinlock_lock(&hw->lock);
4571 ret = hns3_set_promisc_mode(hw, false, false);
4572 rte_spinlock_unlock(&hw->lock);
4574 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4581 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4583 struct hns3_hw *hw = &hns->hw;
4584 bool allmulti = hw->data->all_multicast ? true : false;
4587 if (hw->data->promiscuous) {
4588 ret = hns3_set_promisc_mode(hw, true, true);
4590 hns3_err(hw, "failed to restore promiscuous mode, "
4595 ret = hns3_set_promisc_mode(hw, false, allmulti);
4597 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4603 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4605 struct hns3_sfp_info_cmd *resp;
4606 struct hns3_cmd_desc desc;
4609 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4610 resp = (struct hns3_sfp_info_cmd *)desc.data;
4611 resp->query_type = HNS3_ACTIVE_QUERY;
4613 ret = hns3_cmd_send(hw, &desc, 1);
4614 if (ret == -EOPNOTSUPP) {
4615 hns3_warn(hw, "firmware does not support get SFP info,"
4619 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4624 * In some case, the speed of MAC obtained from firmware may be 0, it
4625 * shouldn't be set to mac->speed.
4627 if (!rte_le_to_cpu_32(resp->sfp_speed))
4630 mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4632 * if resp->supported_speed is 0, it means it's an old version
4633 * firmware, do not update these params.
4635 if (resp->supported_speed) {
4636 mac_info->query_type = HNS3_ACTIVE_QUERY;
4637 mac_info->supported_speed =
4638 rte_le_to_cpu_32(resp->supported_speed);
4639 mac_info->support_autoneg = resp->autoneg_ability;
4640 mac_info->link_autoneg = (resp->autoneg == 0) ? ETH_LINK_FIXED
4643 mac_info->query_type = HNS3_DEFAULT_QUERY;
4650 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4652 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4653 duplex = ETH_LINK_FULL_DUPLEX;
4659 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4661 struct hns3_mac *mac = &hw->mac;
4664 duplex = hns3_check_speed_dup(duplex, speed);
4665 if (mac->link_speed == speed && mac->link_duplex == duplex)
4668 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4672 ret = hns3_port_shaper_update(hw, speed);
4676 mac->link_speed = speed;
4677 mac->link_duplex = duplex;
4683 hns3_update_fiber_link_info(struct hns3_hw *hw)
4685 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4686 struct hns3_mac *mac = &hw->mac;
4687 struct hns3_mac mac_info;
4690 /* If firmware do not support get SFP/qSFP speed, return directly */
4691 if (!pf->support_sfp_query)
4694 memset(&mac_info, 0, sizeof(struct hns3_mac));
4695 ret = hns3_get_sfp_info(hw, &mac_info);
4696 if (ret == -EOPNOTSUPP) {
4697 pf->support_sfp_query = false;
4702 /* Do nothing if no SFP */
4703 if (mac_info.link_speed == ETH_SPEED_NUM_NONE)
4707 * If query_type is HNS3_ACTIVE_QUERY, it is no need
4708 * to reconfigure the speed of MAC. Otherwise, it indicates
4709 * that the current firmware only supports to obtain the
4710 * speed of the SFP, and the speed of MAC needs to reconfigure.
4712 mac->query_type = mac_info.query_type;
4713 if (mac->query_type == HNS3_ACTIVE_QUERY) {
4714 if (mac_info.link_speed != mac->link_speed) {
4715 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4720 mac->link_speed = mac_info.link_speed;
4721 mac->supported_speed = mac_info.supported_speed;
4722 mac->support_autoneg = mac_info.support_autoneg;
4723 mac->link_autoneg = mac_info.link_autoneg;
4728 /* Config full duplex for SFP */
4729 return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4730 ETH_LINK_FULL_DUPLEX);
4734 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4736 #define HNS3_PHY_SUPPORTED_SPEED_MASK 0x2f
4738 struct hns3_phy_params_bd0_cmd *req;
4741 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4742 mac->link_speed = rte_le_to_cpu_32(req->speed);
4743 mac->link_duplex = hns3_get_bit(req->duplex,
4744 HNS3_PHY_DUPLEX_CFG_B);
4745 mac->link_autoneg = hns3_get_bit(req->autoneg,
4746 HNS3_PHY_AUTONEG_CFG_B);
4747 mac->advertising = rte_le_to_cpu_32(req->advertising);
4748 mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4749 supported = rte_le_to_cpu_32(req->supported);
4750 mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4751 mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4755 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4757 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4761 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4762 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4764 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4766 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4768 ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4770 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4774 hns3_parse_copper_phy_params(desc, mac);
4780 hns3_update_copper_link_info(struct hns3_hw *hw)
4782 struct hns3_mac *mac = &hw->mac;
4783 struct hns3_mac mac_info;
4786 memset(&mac_info, 0, sizeof(struct hns3_mac));
4787 ret = hns3_get_copper_phy_params(hw, &mac_info);
4791 if (mac_info.link_speed != mac->link_speed) {
4792 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4797 mac->link_speed = mac_info.link_speed;
4798 mac->link_duplex = mac_info.link_duplex;
4799 mac->link_autoneg = mac_info.link_autoneg;
4800 mac->supported_speed = mac_info.supported_speed;
4801 mac->advertising = mac_info.advertising;
4802 mac->lp_advertising = mac_info.lp_advertising;
4803 mac->support_autoneg = mac_info.support_autoneg;
4809 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4811 struct hns3_adapter *hns = eth_dev->data->dev_private;
4812 struct hns3_hw *hw = &hns->hw;
4815 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4816 ret = hns3_update_copper_link_info(hw);
4817 else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4818 ret = hns3_update_fiber_link_info(hw);
4824 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4826 struct hns3_config_mac_mode_cmd *req;
4827 struct hns3_cmd_desc desc;
4828 uint32_t loop_en = 0;
4832 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4834 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4837 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4838 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4839 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4840 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4841 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4842 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4843 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4844 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4845 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4846 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4849 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4850 * when receiving frames. Otherwise, CRC will be stripped.
4852 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4853 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4855 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4856 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4857 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4858 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4859 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4861 ret = hns3_cmd_send(hw, &desc, 1);
4863 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4869 hns3_get_mac_link_status(struct hns3_hw *hw)
4871 struct hns3_link_status_cmd *req;
4872 struct hns3_cmd_desc desc;
4876 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4877 ret = hns3_cmd_send(hw, &desc, 1);
4879 hns3_err(hw, "get link status cmd failed %d", ret);
4880 return ETH_LINK_DOWN;
4883 req = (struct hns3_link_status_cmd *)desc.data;
4884 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4886 return !!link_status;
4890 hns3_update_link_status(struct hns3_hw *hw)
4894 state = hns3_get_mac_link_status(hw);
4895 if (state != hw->mac.link_status) {
4896 hw->mac.link_status = state;
4897 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4898 hns3_config_mac_tnl_int(hw,
4899 state == ETH_LINK_UP ? true : false);
4907 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4909 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4910 struct rte_eth_link new_link;
4914 hns3_update_port_link_info(dev);
4916 memset(&new_link, 0, sizeof(new_link));
4917 hns3_setup_linkstatus(dev, &new_link);
4919 ret = rte_eth_linkstatus_set(dev, &new_link);
4920 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4921 hns3_start_report_lse(dev);
4925 hns3_service_handler(void *param)
4927 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4928 struct hns3_adapter *hns = eth_dev->data->dev_private;
4929 struct hns3_hw *hw = &hns->hw;
4931 if (!hns3_is_reset_pending(hns))
4932 hns3_update_linkstatus_and_event(hw, true);
4934 hns3_warn(hw, "Cancel the query when reset is pending");
4936 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4940 hns3_init_hardware(struct hns3_adapter *hns)
4942 struct hns3_hw *hw = &hns->hw;
4945 ret = hns3_map_tqp(hw);
4947 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4951 ret = hns3_init_umv_space(hw);
4953 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4957 ret = hns3_mac_init(hw);
4959 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4963 ret = hns3_init_mgr_tbl(hw);
4965 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4969 ret = hns3_promisc_init(hw);
4971 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4976 ret = hns3_init_vlan_config(hns);
4978 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4982 ret = hns3_dcb_init(hw);
4984 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4988 ret = hns3_init_fd_config(hns);
4990 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4994 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4996 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
5000 ret = hns3_config_gro(hw, false);
5002 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
5007 * In the initialization clearing the all hardware mapping relationship
5008 * configurations between queues and interrupt vectors is needed, so
5009 * some error caused by the residual configurations, such as the
5010 * unexpected interrupt, can be avoid.
5012 ret = hns3_init_ring_with_vector(hw);
5014 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
5021 hns3_uninit_umv_space(hw);
5026 hns3_clear_hw(struct hns3_hw *hw)
5028 struct hns3_cmd_desc desc;
5031 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
5033 ret = hns3_cmd_send(hw, &desc, 1);
5034 if (ret && ret != -EOPNOTSUPP)
5041 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
5046 * The new firmware support report more hardware error types by
5047 * msix mode. These errors are defined as RAS errors in hardware
5048 * and belong to a different type from the MSI-x errors processed
5049 * by the network driver.
5051 * Network driver should open the new error report on initialization.
5053 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5054 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5055 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5059 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5061 struct hns3_mac *mac = &hw->mac;
5063 switch (mac->link_speed) {
5064 case ETH_SPEED_NUM_1G:
5065 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5066 case ETH_SPEED_NUM_10G:
5067 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5068 case ETH_SPEED_NUM_25G:
5069 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5070 case ETH_SPEED_NUM_40G:
5071 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5072 case ETH_SPEED_NUM_50G:
5073 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5074 case ETH_SPEED_NUM_100G:
5075 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5076 case ETH_SPEED_NUM_200G:
5077 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5079 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5085 * Validity of supported_speed for firber and copper media type can be
5086 * guaranteed by the following policy:
5088 * Although the initialization of the phy in the firmware may not be
5089 * completed, the firmware can guarantees that the supported_speed is
5092 * If the version of firmware supports the acitive query way of the
5093 * HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5094 * through it. If unsupported, use the SFP's speed as the value of the
5098 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5100 struct hns3_adapter *hns = eth_dev->data->dev_private;
5101 struct hns3_hw *hw = &hns->hw;
5102 struct hns3_mac *mac = &hw->mac;
5105 ret = hns3_update_link_info(eth_dev);
5109 if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5111 * Some firmware does not support the report of supported_speed,
5112 * and only report the effective speed of SFP. In this case, it
5113 * is necessary to use the SFP's speed as the supported_speed.
5115 if (mac->supported_speed == 0)
5116 mac->supported_speed =
5117 hns3_set_firber_default_support_speed(hw);
5124 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
5126 struct hns3_mac *mac = &hns->hw.mac;
5128 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
5129 hns->pf.support_fc_autoneg = true;
5134 * Flow control auto-negotiation requires the cooperation of the driver
5135 * and firmware. Currently, the optical port does not support flow
5136 * control auto-negotiation.
5138 hns->pf.support_fc_autoneg = false;
5142 hns3_init_pf(struct rte_eth_dev *eth_dev)
5144 struct rte_device *dev = eth_dev->device;
5145 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5146 struct hns3_adapter *hns = eth_dev->data->dev_private;
5147 struct hns3_hw *hw = &hns->hw;
5150 PMD_INIT_FUNC_TRACE();
5152 /* Get hardware io base address from pcie BAR2 IO space */
5153 hw->io_base = pci_dev->mem_resource[2].addr;
5155 /* Firmware command queue initialize */
5156 ret = hns3_cmd_init_queue(hw);
5158 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5159 goto err_cmd_init_queue;
5162 hns3_clear_all_event_cause(hw);
5164 /* Firmware command initialize */
5165 ret = hns3_cmd_init(hw);
5167 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5172 * To ensure that the hardware environment is clean during
5173 * initialization, the driver actively clear the hardware environment
5174 * during initialization, including PF and corresponding VFs' vlan, mac,
5175 * flow table configurations, etc.
5177 ret = hns3_clear_hw(hw);
5179 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5183 /* Hardware statistics of imissed registers cleared. */
5184 ret = hns3_update_imissed_stats(hw, true);
5186 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5190 hns3_config_all_msix_error(hw, true);
5192 ret = rte_intr_callback_register(&pci_dev->intr_handle,
5193 hns3_interrupt_handler,
5196 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5197 goto err_intr_callback_register;
5200 ret = hns3_ptp_init(hw);
5202 goto err_get_config;
5204 /* Enable interrupt */
5205 rte_intr_enable(&pci_dev->intr_handle);
5206 hns3_pf_enable_irq0(hw);
5208 /* Get configuration */
5209 ret = hns3_get_configuration(hw);
5211 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5212 goto err_get_config;
5215 ret = hns3_tqp_stats_init(hw);
5217 goto err_get_config;
5219 ret = hns3_init_hardware(hns);
5221 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5225 /* Initialize flow director filter list & hash */
5226 ret = hns3_fdir_filter_init(hns);
5228 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5232 hns3_rss_set_default_args(hw);
5234 ret = hns3_enable_hw_error_intr(hns, true);
5236 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5238 goto err_enable_intr;
5241 ret = hns3_get_port_supported_speed(eth_dev);
5243 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5244 "by device, ret = %d.", ret);
5245 goto err_supported_speed;
5248 hns3_get_fc_autoneg_capability(hns);
5250 hns3_tm_conf_init(eth_dev);
5254 err_supported_speed:
5255 (void)hns3_enable_hw_error_intr(hns, false);
5257 hns3_fdir_filter_uninit(hns);
5259 hns3_uninit_umv_space(hw);
5261 hns3_tqp_stats_uninit(hw);
5263 hns3_pf_disable_irq0(hw);
5264 rte_intr_disable(&pci_dev->intr_handle);
5265 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5267 err_intr_callback_register:
5269 hns3_cmd_uninit(hw);
5270 hns3_cmd_destroy_queue(hw);
5278 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5280 struct hns3_adapter *hns = eth_dev->data->dev_private;
5281 struct rte_device *dev = eth_dev->device;
5282 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5283 struct hns3_hw *hw = &hns->hw;
5285 PMD_INIT_FUNC_TRACE();
5287 hns3_tm_conf_uninit(eth_dev);
5288 hns3_enable_hw_error_intr(hns, false);
5289 hns3_rss_uninit(hns);
5290 (void)hns3_config_gro(hw, false);
5291 hns3_promisc_uninit(hw);
5292 hns3_fdir_filter_uninit(hns);
5293 hns3_uninit_umv_space(hw);
5294 hns3_tqp_stats_uninit(hw);
5295 hns3_config_mac_tnl_int(hw, false);
5296 hns3_pf_disable_irq0(hw);
5297 rte_intr_disable(&pci_dev->intr_handle);
5298 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5300 hns3_config_all_msix_error(hw, false);
5301 hns3_cmd_uninit(hw);
5302 hns3_cmd_destroy_queue(hw);
5307 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
5311 switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5312 case ETH_LINK_SPEED_10M:
5313 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
5315 case ETH_LINK_SPEED_10M_HD:
5316 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
5318 case ETH_LINK_SPEED_100M:
5319 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
5321 case ETH_LINK_SPEED_100M_HD:
5322 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
5324 case ETH_LINK_SPEED_1G:
5325 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
5336 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
5340 switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5341 case ETH_LINK_SPEED_1G:
5342 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
5344 case ETH_LINK_SPEED_10G:
5345 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
5347 case ETH_LINK_SPEED_25G:
5348 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
5350 case ETH_LINK_SPEED_40G:
5351 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
5353 case ETH_LINK_SPEED_50G:
5354 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
5356 case ETH_LINK_SPEED_100G:
5357 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
5359 case ETH_LINK_SPEED_200G:
5360 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
5371 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
5373 struct hns3_mac *mac = &hw->mac;
5374 uint32_t supported_speed = mac->supported_speed;
5375 uint32_t speed_bit = 0;
5377 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
5378 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
5379 else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
5380 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
5382 if (!(speed_bit & supported_speed)) {
5383 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
5391 static inline uint32_t
5392 hns3_get_link_speed(uint32_t link_speeds)
5394 uint32_t speed = ETH_SPEED_NUM_NONE;
5396 if (link_speeds & ETH_LINK_SPEED_10M ||
5397 link_speeds & ETH_LINK_SPEED_10M_HD)
5398 speed = ETH_SPEED_NUM_10M;
5399 if (link_speeds & ETH_LINK_SPEED_100M ||
5400 link_speeds & ETH_LINK_SPEED_100M_HD)
5401 speed = ETH_SPEED_NUM_100M;
5402 if (link_speeds & ETH_LINK_SPEED_1G)
5403 speed = ETH_SPEED_NUM_1G;
5404 if (link_speeds & ETH_LINK_SPEED_10G)
5405 speed = ETH_SPEED_NUM_10G;
5406 if (link_speeds & ETH_LINK_SPEED_25G)
5407 speed = ETH_SPEED_NUM_25G;
5408 if (link_speeds & ETH_LINK_SPEED_40G)
5409 speed = ETH_SPEED_NUM_40G;
5410 if (link_speeds & ETH_LINK_SPEED_50G)
5411 speed = ETH_SPEED_NUM_50G;
5412 if (link_speeds & ETH_LINK_SPEED_100G)
5413 speed = ETH_SPEED_NUM_100G;
5414 if (link_speeds & ETH_LINK_SPEED_200G)
5415 speed = ETH_SPEED_NUM_200G;
5421 hns3_get_link_duplex(uint32_t link_speeds)
5423 if ((link_speeds & ETH_LINK_SPEED_10M_HD) ||
5424 (link_speeds & ETH_LINK_SPEED_100M_HD))
5425 return ETH_LINK_HALF_DUPLEX;
5427 return ETH_LINK_FULL_DUPLEX;
5431 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5432 struct hns3_set_link_speed_cfg *cfg)
5434 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5435 struct hns3_phy_params_bd0_cmd *req;
5438 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5439 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5441 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5443 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5444 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5445 req->autoneg = cfg->autoneg;
5448 * The full speed capability is used to negotiate when
5449 * auto-negotiation is enabled.
5452 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5453 HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5454 HNS3_PHY_LINK_SPEED_100M_BIT |
5455 HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5456 HNS3_PHY_LINK_SPEED_1000M_BIT;
5458 req->speed = cfg->speed;
5459 req->duplex = cfg->duplex;
5462 return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5466 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5468 struct hns3_config_auto_neg_cmd *req;
5469 struct hns3_cmd_desc desc;
5473 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5475 req = (struct hns3_config_auto_neg_cmd *)desc.data;
5477 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5478 req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5480 ret = hns3_cmd_send(hw, &desc, 1);
5482 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5488 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5489 struct hns3_set_link_speed_cfg *cfg)
5493 if (hw->mac.support_autoneg) {
5494 ret = hns3_set_autoneg(hw, cfg->autoneg);
5496 hns3_err(hw, "failed to configure auto-negotiation.");
5501 * To enable auto-negotiation, we only need to open the switch
5502 * of auto-negotiation, then firmware sets all speed
5510 * Some hardware doesn't support auto-negotiation, but users may not
5511 * configure link_speeds (default 0), which means auto-negotiation.
5512 * In this case, it should return success.
5517 return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
5521 hns3_set_port_link_speed(struct hns3_hw *hw,
5522 struct hns3_set_link_speed_cfg *cfg)
5526 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5527 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5528 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5533 ret = hns3_set_copper_port_link_speed(hw, cfg);
5535 hns3_err(hw, "failed to set copper port link speed,"
5539 } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5540 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5542 hns3_err(hw, "failed to set fiber port link speed,"
5552 hns3_apply_link_speed(struct hns3_hw *hw)
5554 struct rte_eth_conf *conf = &hw->data->dev_conf;
5555 struct hns3_set_link_speed_cfg cfg;
5557 memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5558 cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ?
5559 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
5560 if (cfg.autoneg != ETH_LINK_AUTONEG) {
5561 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5562 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5565 return hns3_set_port_link_speed(hw, &cfg);
5569 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5571 struct hns3_hw *hw = &hns->hw;
5574 ret = hns3_dcb_cfg_update(hns);
5579 * The hns3_dcb_cfg_update may configure TM module, so
5580 * hns3_tm_conf_update must called later.
5582 ret = hns3_tm_conf_update(hw);
5584 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5588 hns3_enable_rxd_adv_layout(hw);
5590 ret = hns3_init_queues(hns, reset_queue);
5592 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5596 ret = hns3_cfg_mac_mode(hw, true);
5598 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5599 goto err_config_mac_mode;
5602 ret = hns3_apply_link_speed(hw);
5604 goto err_config_mac_mode;
5608 err_config_mac_mode:
5609 (void)hns3_cfg_mac_mode(hw, false);
5610 hns3_dev_release_mbufs(hns);
5612 * Here is exception handling, hns3_reset_all_tqps will have the
5613 * corresponding error message if it is handled incorrectly, so it is
5614 * not necessary to check hns3_reset_all_tqps return value, here keep
5615 * ret as the error code causing the exception.
5617 (void)hns3_reset_all_tqps(hns);
5622 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5624 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5625 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5626 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5627 uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5628 uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5629 uint32_t intr_vector;
5634 * hns3 needs a separate interrupt to be used as event interrupt which
5635 * could not be shared with task queue pair, so KERNEL drivers need
5636 * support multiple interrupt vectors.
5638 if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5639 !rte_intr_cap_multiple(intr_handle))
5642 rte_intr_disable(intr_handle);
5643 intr_vector = hw->used_rx_queues;
5644 /* creates event fd for each intr vector when MSIX is used */
5645 if (rte_intr_efd_enable(intr_handle, intr_vector))
5648 if (intr_handle->intr_vec == NULL) {
5649 intr_handle->intr_vec =
5650 rte_zmalloc("intr_vec",
5651 hw->used_rx_queues * sizeof(int), 0);
5652 if (intr_handle->intr_vec == NULL) {
5653 hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5654 hw->used_rx_queues);
5656 goto alloc_intr_vec_error;
5660 if (rte_intr_allow_others(intr_handle)) {
5661 vec = RTE_INTR_VEC_RXTX_OFFSET;
5662 base = RTE_INTR_VEC_RXTX_OFFSET;
5665 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5666 ret = hns3_bind_ring_with_vector(hw, vec, true,
5667 HNS3_RING_TYPE_RX, q_id);
5669 goto bind_vector_error;
5670 intr_handle->intr_vec[q_id] = vec;
5672 * If there are not enough efds (e.g. not enough interrupt),
5673 * remaining queues will be bond to the last interrupt.
5675 if (vec < base + intr_handle->nb_efd - 1)
5678 rte_intr_enable(intr_handle);
5682 rte_free(intr_handle->intr_vec);
5683 intr_handle->intr_vec = NULL;
5684 alloc_intr_vec_error:
5685 rte_intr_efd_disable(intr_handle);
5690 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5692 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5693 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5694 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5698 if (dev->data->dev_conf.intr_conf.rxq == 0)
5701 if (rte_intr_dp_is_en(intr_handle)) {
5702 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5703 ret = hns3_bind_ring_with_vector(hw,
5704 intr_handle->intr_vec[q_id], true,
5705 HNS3_RING_TYPE_RX, q_id);
5715 hns3_restore_filter(struct rte_eth_dev *dev)
5717 hns3_restore_rss_filter(dev);
5721 hns3_dev_start(struct rte_eth_dev *dev)
5723 struct hns3_adapter *hns = dev->data->dev_private;
5724 struct hns3_hw *hw = &hns->hw;
5727 PMD_INIT_FUNC_TRACE();
5728 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5731 rte_spinlock_lock(&hw->lock);
5732 hw->adapter_state = HNS3_NIC_STARTING;
5734 ret = hns3_do_start(hns, true);
5736 hw->adapter_state = HNS3_NIC_CONFIGURED;
5737 rte_spinlock_unlock(&hw->lock);
5740 ret = hns3_map_rx_interrupt(dev);
5742 goto map_rx_inter_err;
5745 * There are three register used to control the status of a TQP
5746 * (contains a pair of Tx queue and Rx queue) in the new version network
5747 * engine. One is used to control the enabling of Tx queue, the other is
5748 * used to control the enabling of Rx queue, and the last is the master
5749 * switch used to control the enabling of the tqp. The Tx register and
5750 * TQP register must be enabled at the same time to enable a Tx queue.
5751 * The same applies to the Rx queue. For the older network engine, this
5752 * function only refresh the enabled flag, and it is used to update the
5753 * status of queue in the dpdk framework.
5755 ret = hns3_start_all_txqs(dev);
5757 goto map_rx_inter_err;
5759 ret = hns3_start_all_rxqs(dev);
5761 goto start_all_rxqs_fail;
5763 hw->adapter_state = HNS3_NIC_STARTED;
5764 rte_spinlock_unlock(&hw->lock);
5766 hns3_rx_scattered_calc(dev);
5767 hns3_set_rxtx_function(dev);
5768 hns3_mp_req_start_rxtx(dev);
5770 hns3_restore_filter(dev);
5772 /* Enable interrupt of all rx queues before enabling queues */
5773 hns3_dev_all_rx_queue_intr_enable(hw, true);
5776 * After finished the initialization, enable tqps to receive/transmit
5777 * packets and refresh all queue status.
5779 hns3_start_tqps(hw);
5781 hns3_tm_dev_start_proc(hw);
5783 if (dev->data->dev_conf.intr_conf.lsc != 0)
5784 hns3_dev_link_update(dev, 0);
5785 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5787 hns3_info(hw, "hns3 dev start successful!");
5791 start_all_rxqs_fail:
5792 hns3_stop_all_txqs(dev);
5794 (void)hns3_do_stop(hns);
5795 hw->adapter_state = HNS3_NIC_CONFIGURED;
5796 rte_spinlock_unlock(&hw->lock);
5802 hns3_do_stop(struct hns3_adapter *hns)
5804 struct hns3_hw *hw = &hns->hw;
5808 * The "hns3_do_stop" function will also be called by .stop_service to
5809 * prepare reset. At the time of global or IMP reset, the command cannot
5810 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5811 * accessed during the reset process. So the mbuf can not be released
5812 * during reset and is required to be released after the reset is
5815 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)
5816 hns3_dev_release_mbufs(hns);
5818 ret = hns3_cfg_mac_mode(hw, false);
5821 hw->mac.link_status = ETH_LINK_DOWN;
5823 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5824 hns3_configure_all_mac_addr(hns, true);
5825 ret = hns3_reset_all_tqps(hns);
5827 hns3_err(hw, "failed to reset all queues ret = %d.",
5832 hw->mac.default_addr_setted = false;
5837 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5839 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5840 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5841 struct hns3_adapter *hns = dev->data->dev_private;
5842 struct hns3_hw *hw = &hns->hw;
5843 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5844 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5847 if (dev->data->dev_conf.intr_conf.rxq == 0)
5850 /* unmap the ring with vector */
5851 if (rte_intr_allow_others(intr_handle)) {
5852 vec = RTE_INTR_VEC_RXTX_OFFSET;
5853 base = RTE_INTR_VEC_RXTX_OFFSET;
5855 if (rte_intr_dp_is_en(intr_handle)) {
5856 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5857 (void)hns3_bind_ring_with_vector(hw, vec, false,
5860 if (vec < base + intr_handle->nb_efd - 1)
5864 /* Clean datapath event and queue/vec mapping */
5865 rte_intr_efd_disable(intr_handle);
5866 if (intr_handle->intr_vec) {
5867 rte_free(intr_handle->intr_vec);
5868 intr_handle->intr_vec = NULL;
5873 hns3_dev_stop(struct rte_eth_dev *dev)
5875 struct hns3_adapter *hns = dev->data->dev_private;
5876 struct hns3_hw *hw = &hns->hw;
5878 PMD_INIT_FUNC_TRACE();
5879 dev->data->dev_started = 0;
5881 hw->adapter_state = HNS3_NIC_STOPPING;
5882 hns3_set_rxtx_function(dev);
5884 /* Disable datapath on secondary process. */
5885 hns3_mp_req_stop_rxtx(dev);
5886 /* Prevent crashes when queues are still in use. */
5887 rte_delay_ms(hw->tqps_num);
5889 rte_spinlock_lock(&hw->lock);
5890 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5891 hns3_tm_dev_stop_proc(hw);
5892 hns3_config_mac_tnl_int(hw, false);
5895 hns3_unmap_rx_interrupt(dev);
5896 hw->adapter_state = HNS3_NIC_CONFIGURED;
5898 hns3_rx_scattered_reset(dev);
5899 rte_eal_alarm_cancel(hns3_service_handler, dev);
5900 hns3_stop_report_lse(dev);
5901 rte_spinlock_unlock(&hw->lock);
5907 hns3_dev_close(struct rte_eth_dev *eth_dev)
5909 struct hns3_adapter *hns = eth_dev->data->dev_private;
5910 struct hns3_hw *hw = &hns->hw;
5913 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5914 rte_free(eth_dev->process_private);
5915 eth_dev->process_private = NULL;
5919 if (hw->adapter_state == HNS3_NIC_STARTED)
5920 ret = hns3_dev_stop(eth_dev);
5922 hw->adapter_state = HNS3_NIC_CLOSING;
5923 hns3_reset_abort(hns);
5924 hw->adapter_state = HNS3_NIC_CLOSED;
5926 hns3_configure_all_mc_mac_addr(hns, true);
5927 hns3_remove_all_vlan_table(hns);
5928 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5929 hns3_uninit_pf(eth_dev);
5930 hns3_free_all_queues(eth_dev);
5931 rte_free(hw->reset.wait_data);
5932 rte_free(eth_dev->process_private);
5933 eth_dev->process_private = NULL;
5934 hns3_mp_uninit_primary();
5935 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5941 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5944 struct hns3_mac *mac = &hw->mac;
5945 uint32_t advertising = mac->advertising;
5946 uint32_t lp_advertising = mac->lp_advertising;
5950 if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5953 } else if (advertising & lp_advertising &
5954 HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5955 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5957 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5962 static enum hns3_fc_mode
5963 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5965 enum hns3_fc_mode current_mode;
5966 bool rx_pause = false;
5967 bool tx_pause = false;
5969 switch (hw->mac.media_type) {
5970 case HNS3_MEDIA_TYPE_COPPER:
5971 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5975 * Flow control auto-negotiation is not supported for fiber and
5976 * backpalne media type.
5978 case HNS3_MEDIA_TYPE_FIBER:
5979 case HNS3_MEDIA_TYPE_BACKPLANE:
5980 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
5981 current_mode = hw->requested_fc_mode;
5984 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
5985 hw->mac.media_type);
5986 current_mode = HNS3_FC_NONE;
5990 if (rx_pause && tx_pause)
5991 current_mode = HNS3_FC_FULL;
5993 current_mode = HNS3_FC_RX_PAUSE;
5995 current_mode = HNS3_FC_TX_PAUSE;
5997 current_mode = HNS3_FC_NONE;
6000 return current_mode;
6003 static enum hns3_fc_mode
6004 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
6006 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6007 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6008 struct hns3_mac *mac = &hw->mac;
6011 * When the flow control mode is obtained, the device may not complete
6012 * auto-negotiation. It is necessary to wait for link establishment.
6014 (void)hns3_dev_link_update(dev, 1);
6017 * If the link auto-negotiation of the nic is disabled, or the flow
6018 * control auto-negotiation is not supported, the forced flow control
6021 if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
6022 return hw->requested_fc_mode;
6024 return hns3_get_autoneg_fc_mode(hw);
6028 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6030 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6031 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6032 enum hns3_fc_mode current_mode;
6034 current_mode = hns3_get_current_fc_mode(dev);
6035 switch (current_mode) {
6037 fc_conf->mode = RTE_FC_FULL;
6039 case HNS3_FC_TX_PAUSE:
6040 fc_conf->mode = RTE_FC_TX_PAUSE;
6042 case HNS3_FC_RX_PAUSE:
6043 fc_conf->mode = RTE_FC_RX_PAUSE;
6047 fc_conf->mode = RTE_FC_NONE;
6051 fc_conf->pause_time = pf->pause_time;
6052 fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
6058 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
6062 hw->requested_fc_mode = HNS3_FC_NONE;
6064 case RTE_FC_RX_PAUSE:
6065 hw->requested_fc_mode = HNS3_FC_RX_PAUSE;
6067 case RTE_FC_TX_PAUSE:
6068 hw->requested_fc_mode = HNS3_FC_TX_PAUSE;
6071 hw->requested_fc_mode = HNS3_FC_FULL;
6074 hw->requested_fc_mode = HNS3_FC_NONE;
6075 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
6076 "configured to RTE_FC_NONE", mode);
6082 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
6084 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
6086 if (!pf->support_fc_autoneg) {
6088 hns3_err(hw, "unsupported fc auto-negotiation setting.");
6093 * Flow control auto-negotiation of the NIC is not supported,
6094 * but other auto-negotiation features may be supported.
6096 if (autoneg != hw->mac.link_autoneg) {
6097 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
6105 * If flow control auto-negotiation of the NIC is supported, all
6106 * auto-negotiation features are supported.
6108 if (autoneg != hw->mac.link_autoneg) {
6109 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
6117 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6119 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6122 if (fc_conf->high_water || fc_conf->low_water ||
6123 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
6124 hns3_err(hw, "Unsupported flow control settings specified, "
6125 "high_water(%u), low_water(%u), send_xon(%u) and "
6126 "mac_ctrl_frame_fwd(%u) must be set to '0'",
6127 fc_conf->high_water, fc_conf->low_water,
6128 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
6132 ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
6136 if (!fc_conf->pause_time) {
6137 hns3_err(hw, "Invalid pause time %u setting.",
6138 fc_conf->pause_time);
6142 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6143 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
6144 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
6145 "current_fc_status = %d", hw->current_fc_status);
6149 if (hw->num_tc > 1) {
6150 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
6154 hns3_get_fc_mode(hw, fc_conf->mode);
6156 rte_spinlock_lock(&hw->lock);
6157 ret = hns3_fc_enable(dev, fc_conf);
6158 rte_spinlock_unlock(&hw->lock);
6164 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
6165 struct rte_eth_pfc_conf *pfc_conf)
6167 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6170 if (!hns3_dev_dcb_supported(hw)) {
6171 hns3_err(hw, "This port does not support dcb configurations.");
6175 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
6176 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
6177 hns3_err(hw, "Unsupported flow control settings specified, "
6178 "high_water(%u), low_water(%u), send_xon(%u) and "
6179 "mac_ctrl_frame_fwd(%u) must be set to '0'",
6180 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
6181 pfc_conf->fc.send_xon,
6182 pfc_conf->fc.mac_ctrl_frame_fwd);
6185 if (pfc_conf->fc.autoneg) {
6186 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
6189 if (pfc_conf->fc.pause_time == 0) {
6190 hns3_err(hw, "Invalid pause time %u setting.",
6191 pfc_conf->fc.pause_time);
6195 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6196 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
6197 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
6198 "current_fc_status = %d", hw->current_fc_status);
6202 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
6204 rte_spinlock_lock(&hw->lock);
6205 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
6206 rte_spinlock_unlock(&hw->lock);
6212 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
6214 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6215 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6216 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
6219 rte_spinlock_lock(&hw->lock);
6220 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
6221 dcb_info->nb_tcs = pf->local_max_tc;
6223 dcb_info->nb_tcs = 1;
6225 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
6226 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
6227 for (i = 0; i < dcb_info->nb_tcs; i++)
6228 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
6230 for (i = 0; i < hw->num_tc; i++) {
6231 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
6232 dcb_info->tc_queue.tc_txq[0][i].base =
6233 hw->tc_queue[i].tqp_offset;
6234 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
6235 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
6236 hw->tc_queue[i].tqp_count;
6238 rte_spinlock_unlock(&hw->lock);
6244 hns3_reinit_dev(struct hns3_adapter *hns)
6246 struct hns3_hw *hw = &hns->hw;
6249 ret = hns3_cmd_init(hw);
6251 hns3_err(hw, "Failed to init cmd: %d", ret);
6255 ret = hns3_reset_all_tqps(hns);
6257 hns3_err(hw, "Failed to reset all queues: %d", ret);
6261 ret = hns3_init_hardware(hns);
6263 hns3_err(hw, "Failed to init hardware: %d", ret);
6267 ret = hns3_enable_hw_error_intr(hns, true);
6269 hns3_err(hw, "fail to enable hw error interrupts: %d",
6273 hns3_info(hw, "Reset done, driver initialization finished.");
6279 is_pf_reset_done(struct hns3_hw *hw)
6281 uint32_t val, reg, reg_bit;
6283 switch (hw->reset.level) {
6284 case HNS3_IMP_RESET:
6285 reg = HNS3_GLOBAL_RESET_REG;
6286 reg_bit = HNS3_IMP_RESET_BIT;
6288 case HNS3_GLOBAL_RESET:
6289 reg = HNS3_GLOBAL_RESET_REG;
6290 reg_bit = HNS3_GLOBAL_RESET_BIT;
6292 case HNS3_FUNC_RESET:
6293 reg = HNS3_FUN_RST_ING;
6294 reg_bit = HNS3_FUN_RST_ING_B;
6296 case HNS3_FLR_RESET:
6298 hns3_err(hw, "Wait for unsupported reset level: %d",
6302 val = hns3_read_dev(hw, reg);
6303 if (hns3_get_bit(val, reg_bit))
6310 hns3_is_reset_pending(struct hns3_adapter *hns)
6312 struct hns3_hw *hw = &hns->hw;
6313 enum hns3_reset_level reset;
6315 hns3_check_event_cause(hns, NULL);
6316 reset = hns3_get_reset_level(hns, &hw->reset.pending);
6318 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6319 hw->reset.level < reset) {
6320 hns3_warn(hw, "High level reset %d is pending", reset);
6323 reset = hns3_get_reset_level(hns, &hw->reset.request);
6324 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6325 hw->reset.level < reset) {
6326 hns3_warn(hw, "High level reset %d is request", reset);
6333 hns3_wait_hardware_ready(struct hns3_adapter *hns)
6335 struct hns3_hw *hw = &hns->hw;
6336 struct hns3_wait_data *wait_data = hw->reset.wait_data;
6339 if (wait_data->result == HNS3_WAIT_SUCCESS)
6341 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
6342 gettimeofday(&tv, NULL);
6343 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
6344 tv.tv_sec, tv.tv_usec);
6346 } else if (wait_data->result == HNS3_WAIT_REQUEST)
6349 wait_data->hns = hns;
6350 wait_data->check_completion = is_pf_reset_done;
6351 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
6352 HNS3_RESET_WAIT_MS + get_timeofday_ms();
6353 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
6354 wait_data->count = HNS3_RESET_WAIT_CNT;
6355 wait_data->result = HNS3_WAIT_REQUEST;
6356 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
6361 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
6363 struct hns3_cmd_desc desc;
6364 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6366 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6367 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6368 req->fun_reset_vfid = func_id;
6370 return hns3_cmd_send(hw, &desc, 1);
6374 hns3_imp_reset_cmd(struct hns3_hw *hw)
6376 struct hns3_cmd_desc desc;
6378 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6379 desc.data[0] = 0xeedd;
6381 return hns3_cmd_send(hw, &desc, 1);
6385 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6387 struct hns3_hw *hw = &hns->hw;
6391 gettimeofday(&tv, NULL);
6392 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6393 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6394 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6395 tv.tv_sec, tv.tv_usec);
6399 switch (reset_level) {
6400 case HNS3_IMP_RESET:
6401 hns3_imp_reset_cmd(hw);
6402 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6403 tv.tv_sec, tv.tv_usec);
6405 case HNS3_GLOBAL_RESET:
6406 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6407 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6408 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6409 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6410 tv.tv_sec, tv.tv_usec);
6412 case HNS3_FUNC_RESET:
6413 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6414 tv.tv_sec, tv.tv_usec);
6415 /* schedule again to check later */
6416 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6417 hns3_schedule_reset(hns);
6420 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6423 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6426 static enum hns3_reset_level
6427 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6429 struct hns3_hw *hw = &hns->hw;
6430 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6432 /* Return the highest priority reset level amongst all */
6433 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6434 reset_level = HNS3_IMP_RESET;
6435 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6436 reset_level = HNS3_GLOBAL_RESET;
6437 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6438 reset_level = HNS3_FUNC_RESET;
6439 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6440 reset_level = HNS3_FLR_RESET;
6442 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6443 return HNS3_NONE_RESET;
6449 hns3_record_imp_error(struct hns3_adapter *hns)
6451 struct hns3_hw *hw = &hns->hw;
6454 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6455 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6456 hns3_warn(hw, "Detected IMP RD poison!");
6457 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6458 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6461 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6462 hns3_warn(hw, "Detected IMP CMDQ error!");
6463 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6464 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6469 hns3_prepare_reset(struct hns3_adapter *hns)
6471 struct hns3_hw *hw = &hns->hw;
6475 switch (hw->reset.level) {
6476 case HNS3_FUNC_RESET:
6477 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6482 * After performaning pf reset, it is not necessary to do the
6483 * mailbox handling or send any command to firmware, because
6484 * any mailbox handling or command to firmware is only valid
6485 * after hns3_cmd_init is called.
6487 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6488 hw->reset.stats.request_cnt++;
6490 case HNS3_IMP_RESET:
6491 hns3_record_imp_error(hns);
6492 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6493 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6494 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6503 hns3_set_rst_done(struct hns3_hw *hw)
6505 struct hns3_pf_rst_done_cmd *req;
6506 struct hns3_cmd_desc desc;
6508 req = (struct hns3_pf_rst_done_cmd *)desc.data;
6509 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6510 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6511 return hns3_cmd_send(hw, &desc, 1);
6515 hns3_stop_service(struct hns3_adapter *hns)
6517 struct hns3_hw *hw = &hns->hw;
6518 struct rte_eth_dev *eth_dev;
6520 eth_dev = &rte_eth_devices[hw->data->port_id];
6521 hw->mac.link_status = ETH_LINK_DOWN;
6522 if (hw->adapter_state == HNS3_NIC_STARTED) {
6523 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6524 hns3_update_linkstatus_and_event(hw, false);
6527 hns3_set_rxtx_function(eth_dev);
6529 /* Disable datapath on secondary process. */
6530 hns3_mp_req_stop_rxtx(eth_dev);
6531 rte_delay_ms(hw->tqps_num);
6533 rte_spinlock_lock(&hw->lock);
6534 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6535 hw->adapter_state == HNS3_NIC_STOPPING) {
6536 hns3_enable_all_queues(hw, false);
6538 hw->reset.mbuf_deferred_free = true;
6540 hw->reset.mbuf_deferred_free = false;
6543 * It is cumbersome for hardware to pick-and-choose entries for deletion
6544 * from table space. Hence, for function reset software intervention is
6545 * required to delete the entries
6547 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6548 hns3_configure_all_mc_mac_addr(hns, true);
6549 rte_spinlock_unlock(&hw->lock);
6555 hns3_start_service(struct hns3_adapter *hns)
6557 struct hns3_hw *hw = &hns->hw;
6558 struct rte_eth_dev *eth_dev;
6560 if (hw->reset.level == HNS3_IMP_RESET ||
6561 hw->reset.level == HNS3_GLOBAL_RESET)
6562 hns3_set_rst_done(hw);
6563 eth_dev = &rte_eth_devices[hw->data->port_id];
6564 hns3_set_rxtx_function(eth_dev);
6565 hns3_mp_req_start_rxtx(eth_dev);
6566 if (hw->adapter_state == HNS3_NIC_STARTED) {
6568 * This API parent function already hold the hns3_hw.lock, the
6569 * hns3_service_handler may report lse, in bonding application
6570 * it will call driver's ops which may acquire the hns3_hw.lock
6571 * again, thus lead to deadlock.
6572 * We defer calls hns3_service_handler to avoid the deadlock.
6574 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6575 hns3_service_handler, eth_dev);
6577 /* Enable interrupt of all rx queues before enabling queues */
6578 hns3_dev_all_rx_queue_intr_enable(hw, true);
6580 * Enable state of each rxq and txq will be recovered after
6581 * reset, so we need to restore them before enable all tqps;
6583 hns3_restore_tqp_enable_state(hw);
6585 * When finished the initialization, enable queues to receive
6586 * and transmit packets.
6588 hns3_enable_all_queues(hw, true);
6595 hns3_restore_conf(struct hns3_adapter *hns)
6597 struct hns3_hw *hw = &hns->hw;
6600 ret = hns3_configure_all_mac_addr(hns, false);
6604 ret = hns3_configure_all_mc_mac_addr(hns, false);
6608 ret = hns3_dev_promisc_restore(hns);
6612 ret = hns3_restore_vlan_table(hns);
6616 ret = hns3_restore_vlan_conf(hns);
6620 ret = hns3_restore_all_fdir_filter(hns);
6624 ret = hns3_restore_ptp(hns);
6628 ret = hns3_restore_rx_interrupt(hw);
6632 ret = hns3_restore_gro_conf(hw);
6636 ret = hns3_restore_fec(hw);
6640 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6641 ret = hns3_do_start(hns, false);
6644 hns3_info(hw, "hns3 dev restart successful!");
6645 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6646 hw->adapter_state = HNS3_NIC_CONFIGURED;
6650 hns3_configure_all_mc_mac_addr(hns, true);
6652 hns3_configure_all_mac_addr(hns, true);
6657 hns3_reset_service(void *param)
6659 struct hns3_adapter *hns = (struct hns3_adapter *)param;
6660 struct hns3_hw *hw = &hns->hw;
6661 enum hns3_reset_level reset_level;
6662 struct timeval tv_delta;
6663 struct timeval tv_start;
6669 * The interrupt is not triggered within the delay time.
6670 * The interrupt may have been lost. It is necessary to handle
6671 * the interrupt to recover from the error.
6673 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6674 SCHEDULE_DEFERRED) {
6675 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6677 hns3_err(hw, "Handling interrupts in delayed tasks");
6678 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6679 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6680 if (reset_level == HNS3_NONE_RESET) {
6681 hns3_err(hw, "No reset level is set, try IMP reset");
6682 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6685 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6688 * Check if there is any ongoing reset in the hardware. This status can
6689 * be checked from reset_pending. If there is then, we need to wait for
6690 * hardware to complete reset.
6691 * a. If we are able to figure out in reasonable time that hardware
6692 * has fully resetted then, we can proceed with driver, client
6694 * b. else, we can come back later to check this status so re-sched
6697 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6698 if (reset_level != HNS3_NONE_RESET) {
6699 gettimeofday(&tv_start, NULL);
6700 ret = hns3_reset_process(hns, reset_level);
6701 gettimeofday(&tv, NULL);
6702 timersub(&tv, &tv_start, &tv_delta);
6703 msec = tv_delta.tv_sec * MSEC_PER_SEC +
6704 tv_delta.tv_usec / USEC_PER_MSEC;
6705 if (msec > HNS3_RESET_PROCESS_MS)
6706 hns3_err(hw, "%d handle long time delta %" PRIx64
6707 " ms time=%ld.%.6ld",
6708 hw->reset.level, msec,
6709 tv.tv_sec, tv.tv_usec);
6714 /* Check if we got any *new* reset requests to be honored */
6715 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6716 if (reset_level != HNS3_NONE_RESET)
6717 hns3_msix_process(hns, reset_level);
6721 hns3_get_speed_capa_num(uint16_t device_id)
6725 switch (device_id) {
6726 case HNS3_DEV_ID_25GE:
6727 case HNS3_DEV_ID_25GE_RDMA:
6730 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6731 case HNS3_DEV_ID_200G_RDMA:
6743 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6746 switch (device_id) {
6747 case HNS3_DEV_ID_25GE:
6749 case HNS3_DEV_ID_25GE_RDMA:
6750 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6751 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6753 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6754 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6755 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6757 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6758 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6759 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6761 case HNS3_DEV_ID_200G_RDMA:
6762 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6763 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6773 hns3_fec_get_capability(struct rte_eth_dev *dev,
6774 struct rte_eth_fec_capa *speed_fec_capa,
6777 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6778 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6779 uint16_t device_id = pci_dev->id.device_id;
6780 unsigned int capa_num;
6783 capa_num = hns3_get_speed_capa_num(device_id);
6784 if (capa_num == 0) {
6785 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6790 if (speed_fec_capa == NULL || num < capa_num)
6793 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6801 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6803 struct hns3_config_fec_cmd *req;
6804 struct hns3_cmd_desc desc;
6808 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6809 * in device of link speed
6812 if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6817 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6818 req = (struct hns3_config_fec_cmd *)desc.data;
6819 ret = hns3_cmd_send(hw, &desc, 1);
6821 hns3_err(hw, "get current fec auto state failed, ret = %d",
6826 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6831 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6833 struct hns3_sfp_info_cmd *resp;
6834 uint32_t tmp_fec_capa;
6836 struct hns3_cmd_desc desc;
6840 * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6841 * configured FEC mode is returned.
6842 * If link is up, current FEC mode is returned.
6844 if (hw->mac.link_status == ETH_LINK_DOWN) {
6845 ret = get_current_fec_auto_state(hw, &auto_state);
6849 if (auto_state == 0x1) {
6850 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6855 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6856 resp = (struct hns3_sfp_info_cmd *)desc.data;
6857 resp->query_type = HNS3_ACTIVE_QUERY;
6859 ret = hns3_cmd_send(hw, &desc, 1);
6860 if (ret == -EOPNOTSUPP) {
6861 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6864 hns3_err(hw, "get FEC failed, ret = %d", ret);
6869 * FEC mode order defined in hns3 hardware is inconsistend with
6870 * that defined in the ethdev library. So the sequence needs
6873 switch (resp->active_fec) {
6874 case HNS3_HW_FEC_MODE_NOFEC:
6875 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6877 case HNS3_HW_FEC_MODE_BASER:
6878 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6880 case HNS3_HW_FEC_MODE_RS:
6881 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6884 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6888 *fec_capa = tmp_fec_capa;
6893 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6895 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6897 return hns3_fec_get_internal(hw, fec_capa);
6901 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6903 struct hns3_config_fec_cmd *req;
6904 struct hns3_cmd_desc desc;
6907 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6909 req = (struct hns3_config_fec_cmd *)desc.data;
6911 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6912 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6913 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6915 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6916 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6917 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6919 case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6920 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6921 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6923 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6924 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6929 ret = hns3_cmd_send(hw, &desc, 1);
6931 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6937 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6939 struct hns3_mac *mac = &hw->mac;
6942 switch (mac->link_speed) {
6943 case ETH_SPEED_NUM_10G:
6944 cur_capa = fec_capa[1].capa;
6946 case ETH_SPEED_NUM_25G:
6947 case ETH_SPEED_NUM_100G:
6948 case ETH_SPEED_NUM_200G:
6949 cur_capa = fec_capa[0].capa;
6960 is_fec_mode_one_bit_set(uint32_t mode)
6965 for (i = 0; i < sizeof(mode); i++)
6966 if (mode >> i & 0x1)
6969 return cnt == 1 ? true : false;
6973 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6975 #define FEC_CAPA_NUM 2
6976 struct hns3_adapter *hns = dev->data->dev_private;
6977 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6978 struct hns3_pf *pf = &hns->pf;
6980 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6982 uint32_t num = FEC_CAPA_NUM;
6985 ret = hns3_fec_get_capability(dev, fec_capa, num);
6989 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6990 if (!is_fec_mode_one_bit_set(mode))
6991 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6992 "FEC mode should be only one bit set", mode);
6995 * Check whether the configured mode is within the FEC capability.
6996 * If not, the configured mode will not be supported.
6998 cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6999 if (!(cur_capa & mode)) {
7000 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
7004 rte_spinlock_lock(&hw->lock);
7005 ret = hns3_set_fec_hw(hw, mode);
7007 rte_spinlock_unlock(&hw->lock);
7011 pf->fec_mode = mode;
7012 rte_spinlock_unlock(&hw->lock);
7018 hns3_restore_fec(struct hns3_hw *hw)
7020 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7021 struct hns3_pf *pf = &hns->pf;
7022 uint32_t mode = pf->fec_mode;
7025 ret = hns3_set_fec_hw(hw, mode);
7027 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
7034 hns3_query_dev_fec_info(struct hns3_hw *hw)
7036 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7037 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
7040 ret = hns3_fec_get_internal(hw, &pf->fec_mode);
7042 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
7048 hns3_optical_module_existed(struct hns3_hw *hw)
7050 struct hns3_cmd_desc desc;
7054 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
7055 ret = hns3_cmd_send(hw, &desc, 1);
7058 "fail to get optical module exist state, ret = %d.\n",
7062 existed = !!desc.data[0];
7068 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
7069 uint32_t len, uint8_t *data)
7071 #define HNS3_SFP_INFO_CMD_NUM 6
7072 #define HNS3_SFP_INFO_MAX_LEN \
7073 (HNS3_SFP_INFO_BD0_LEN + \
7074 (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
7075 struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
7076 struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
7082 for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7083 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
7085 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
7086 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
7089 sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
7090 sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
7091 read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
7092 sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
7094 ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
7096 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
7101 /* The data format in BD0 is different with the others. */
7102 copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
7103 memcpy(data, sfp_info_bd0->data, copy_len);
7104 read_len = copy_len;
7106 for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7107 if (read_len >= len)
7110 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
7111 memcpy(data + read_len, desc[i].data, copy_len);
7112 read_len += copy_len;
7115 return (int)read_len;
7119 hns3_get_module_eeprom(struct rte_eth_dev *dev,
7120 struct rte_dev_eeprom_info *info)
7122 struct hns3_adapter *hns = dev->data->dev_private;
7123 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7124 uint32_t offset = info->offset;
7125 uint32_t len = info->length;
7126 uint8_t *data = info->data;
7127 uint32_t read_len = 0;
7129 if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
7132 if (!hns3_optical_module_existed(hw)) {
7133 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
7137 while (read_len < len) {
7139 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
7151 hns3_get_module_info(struct rte_eth_dev *dev,
7152 struct rte_eth_dev_module_info *modinfo)
7154 #define HNS3_SFF8024_ID_SFP 0x03
7155 #define HNS3_SFF8024_ID_QSFP_8438 0x0c
7156 #define HNS3_SFF8024_ID_QSFP_8436_8636 0x0d
7157 #define HNS3_SFF8024_ID_QSFP28_8636 0x11
7158 #define HNS3_SFF_8636_V1_3 0x03
7159 struct hns3_adapter *hns = dev->data->dev_private;
7160 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7161 struct rte_dev_eeprom_info info;
7162 struct hns3_sfp_type sfp_type;
7165 memset(&sfp_type, 0, sizeof(sfp_type));
7166 memset(&info, 0, sizeof(info));
7167 info.data = (uint8_t *)&sfp_type;
7168 info.length = sizeof(sfp_type);
7169 ret = hns3_get_module_eeprom(dev, &info);
7173 switch (sfp_type.type) {
7174 case HNS3_SFF8024_ID_SFP:
7175 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7176 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7178 case HNS3_SFF8024_ID_QSFP_8438:
7179 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7180 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7182 case HNS3_SFF8024_ID_QSFP_8436_8636:
7183 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
7184 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7185 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7187 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7188 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7191 case HNS3_SFF8024_ID_QSFP28_8636:
7192 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7193 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7196 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
7197 sfp_type.type, sfp_type.ext_type);
7205 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
7207 uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
7211 if (strcmp(value, "vec") == 0)
7212 hint = HNS3_IO_FUNC_HINT_VEC;
7213 else if (strcmp(value, "sve") == 0)
7214 hint = HNS3_IO_FUNC_HINT_SVE;
7215 else if (strcmp(value, "simple") == 0)
7216 hint = HNS3_IO_FUNC_HINT_SIMPLE;
7217 else if (strcmp(value, "common") == 0)
7218 hint = HNS3_IO_FUNC_HINT_COMMON;
7220 /* If the hint is valid then update output parameters */
7221 if (hint != HNS3_IO_FUNC_HINT_NONE)
7222 *(uint32_t *)extra_args = hint;
7228 hns3_get_io_hint_func_name(uint32_t hint)
7231 case HNS3_IO_FUNC_HINT_VEC:
7233 case HNS3_IO_FUNC_HINT_SVE:
7235 case HNS3_IO_FUNC_HINT_SIMPLE:
7237 case HNS3_IO_FUNC_HINT_COMMON:
7245 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args)
7251 val = strtoull(value, NULL, 16);
7252 *(uint64_t *)extra_args = val;
7258 hns3_parse_devargs(struct rte_eth_dev *dev)
7260 struct hns3_adapter *hns = dev->data->dev_private;
7261 uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7262 uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7263 struct hns3_hw *hw = &hns->hw;
7264 uint64_t dev_caps_mask = 0;
7265 struct rte_kvargs *kvlist;
7267 if (dev->device->devargs == NULL)
7270 kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
7274 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
7275 &hns3_parse_io_hint_func, &rx_func_hint);
7276 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
7277 &hns3_parse_io_hint_func, &tx_func_hint);
7278 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK,
7279 &hns3_parse_dev_caps_mask, &dev_caps_mask);
7280 rte_kvargs_free(kvlist);
7282 if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7283 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
7284 hns3_get_io_hint_func_name(rx_func_hint));
7285 hns->rx_func_hint = rx_func_hint;
7286 if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7287 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
7288 hns3_get_io_hint_func_name(tx_func_hint));
7289 hns->tx_func_hint = tx_func_hint;
7291 if (dev_caps_mask != 0)
7292 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".",
7293 HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask);
7294 hns->dev_caps_mask = dev_caps_mask;
7297 static const struct eth_dev_ops hns3_eth_dev_ops = {
7298 .dev_configure = hns3_dev_configure,
7299 .dev_start = hns3_dev_start,
7300 .dev_stop = hns3_dev_stop,
7301 .dev_close = hns3_dev_close,
7302 .promiscuous_enable = hns3_dev_promiscuous_enable,
7303 .promiscuous_disable = hns3_dev_promiscuous_disable,
7304 .allmulticast_enable = hns3_dev_allmulticast_enable,
7305 .allmulticast_disable = hns3_dev_allmulticast_disable,
7306 .mtu_set = hns3_dev_mtu_set,
7307 .stats_get = hns3_stats_get,
7308 .stats_reset = hns3_stats_reset,
7309 .xstats_get = hns3_dev_xstats_get,
7310 .xstats_get_names = hns3_dev_xstats_get_names,
7311 .xstats_reset = hns3_dev_xstats_reset,
7312 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
7313 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
7314 .dev_infos_get = hns3_dev_infos_get,
7315 .fw_version_get = hns3_fw_version_get,
7316 .rx_queue_setup = hns3_rx_queue_setup,
7317 .tx_queue_setup = hns3_tx_queue_setup,
7318 .rx_queue_release = hns3_dev_rx_queue_release,
7319 .tx_queue_release = hns3_dev_tx_queue_release,
7320 .rx_queue_start = hns3_dev_rx_queue_start,
7321 .rx_queue_stop = hns3_dev_rx_queue_stop,
7322 .tx_queue_start = hns3_dev_tx_queue_start,
7323 .tx_queue_stop = hns3_dev_tx_queue_stop,
7324 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
7325 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
7326 .rxq_info_get = hns3_rxq_info_get,
7327 .txq_info_get = hns3_txq_info_get,
7328 .rx_burst_mode_get = hns3_rx_burst_mode_get,
7329 .tx_burst_mode_get = hns3_tx_burst_mode_get,
7330 .flow_ctrl_get = hns3_flow_ctrl_get,
7331 .flow_ctrl_set = hns3_flow_ctrl_set,
7332 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
7333 .mac_addr_add = hns3_add_mac_addr,
7334 .mac_addr_remove = hns3_remove_mac_addr,
7335 .mac_addr_set = hns3_set_default_mac_addr,
7336 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
7337 .link_update = hns3_dev_link_update,
7338 .rss_hash_update = hns3_dev_rss_hash_update,
7339 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
7340 .reta_update = hns3_dev_rss_reta_update,
7341 .reta_query = hns3_dev_rss_reta_query,
7342 .flow_ops_get = hns3_dev_flow_ops_get,
7343 .vlan_filter_set = hns3_vlan_filter_set,
7344 .vlan_tpid_set = hns3_vlan_tpid_set,
7345 .vlan_offload_set = hns3_vlan_offload_set,
7346 .vlan_pvid_set = hns3_vlan_pvid_set,
7347 .get_reg = hns3_get_regs,
7348 .get_module_info = hns3_get_module_info,
7349 .get_module_eeprom = hns3_get_module_eeprom,
7350 .get_dcb_info = hns3_get_dcb_info,
7351 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
7352 .fec_get_capability = hns3_fec_get_capability,
7353 .fec_get = hns3_fec_get,
7354 .fec_set = hns3_fec_set,
7355 .tm_ops_get = hns3_tm_ops_get,
7356 .tx_done_cleanup = hns3_tx_done_cleanup,
7357 .timesync_enable = hns3_timesync_enable,
7358 .timesync_disable = hns3_timesync_disable,
7359 .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
7360 .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
7361 .timesync_adjust_time = hns3_timesync_adjust_time,
7362 .timesync_read_time = hns3_timesync_read_time,
7363 .timesync_write_time = hns3_timesync_write_time,
7366 static const struct hns3_reset_ops hns3_reset_ops = {
7367 .reset_service = hns3_reset_service,
7368 .stop_service = hns3_stop_service,
7369 .prepare_reset = hns3_prepare_reset,
7370 .wait_hardware_ready = hns3_wait_hardware_ready,
7371 .reinit_dev = hns3_reinit_dev,
7372 .restore_conf = hns3_restore_conf,
7373 .start_service = hns3_start_service,
7377 hns3_dev_init(struct rte_eth_dev *eth_dev)
7379 struct hns3_adapter *hns = eth_dev->data->dev_private;
7380 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
7381 struct rte_ether_addr *eth_addr;
7382 struct hns3_hw *hw = &hns->hw;
7385 PMD_INIT_FUNC_TRACE();
7387 eth_dev->process_private = (struct hns3_process_private *)
7388 rte_zmalloc_socket("hns3_filter_list",
7389 sizeof(struct hns3_process_private),
7390 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
7391 if (eth_dev->process_private == NULL) {
7392 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
7396 hns3_flow_init(eth_dev);
7398 hns3_set_rxtx_function(eth_dev);
7399 eth_dev->dev_ops = &hns3_eth_dev_ops;
7400 eth_dev->rx_queue_count = hns3_rx_queue_count;
7401 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7402 ret = hns3_mp_init_secondary();
7404 PMD_INIT_LOG(ERR, "Failed to init for secondary "
7405 "process, ret = %d", ret);
7406 goto err_mp_init_secondary;
7409 hw->secondary_cnt++;
7413 ret = hns3_mp_init_primary();
7416 "Failed to init for primary process, ret = %d",
7418 goto err_mp_init_primary;
7421 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
7423 hw->data = eth_dev->data;
7424 hns3_parse_devargs(eth_dev);
7427 * Set default max packet size according to the mtu
7428 * default vale in DPDK frame.
7430 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
7432 ret = hns3_reset_init(hw);
7434 goto err_init_reset;
7435 hw->reset.ops = &hns3_reset_ops;
7437 ret = hns3_init_pf(eth_dev);
7439 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
7443 /* Allocate memory for storing MAC addresses */
7444 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
7445 sizeof(struct rte_ether_addr) *
7446 HNS3_UC_MACADDR_NUM, 0);
7447 if (eth_dev->data->mac_addrs == NULL) {
7448 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
7449 "to store MAC addresses",
7450 sizeof(struct rte_ether_addr) *
7451 HNS3_UC_MACADDR_NUM);
7453 goto err_rte_zmalloc;
7456 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
7457 if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
7458 rte_eth_random_addr(hw->mac.mac_addr);
7459 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
7460 (struct rte_ether_addr *)hw->mac.mac_addr);
7461 hns3_warn(hw, "default mac_addr from firmware is an invalid "
7462 "unicast address, using random MAC address %s",
7465 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7466 ð_dev->data->mac_addrs[0]);
7468 hw->adapter_state = HNS3_NIC_INITIALIZED;
7470 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7472 hns3_err(hw, "Reschedule reset service after dev_init");
7473 hns3_schedule_reset(hns);
7475 /* IMP will wait ready flag before reset */
7476 hns3_notify_reset_ready(hw, false);
7479 hns3_info(hw, "hns3 dev initialization successful!");
7483 hns3_uninit_pf(eth_dev);
7486 rte_free(hw->reset.wait_data);
7489 hns3_mp_uninit_primary();
7491 err_mp_init_primary:
7492 err_mp_init_secondary:
7493 eth_dev->dev_ops = NULL;
7494 eth_dev->rx_pkt_burst = NULL;
7495 eth_dev->rx_descriptor_status = NULL;
7496 eth_dev->tx_pkt_burst = NULL;
7497 eth_dev->tx_pkt_prepare = NULL;
7498 eth_dev->tx_descriptor_status = NULL;
7499 rte_free(eth_dev->process_private);
7500 eth_dev->process_private = NULL;
7505 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7507 struct hns3_adapter *hns = eth_dev->data->dev_private;
7508 struct hns3_hw *hw = &hns->hw;
7510 PMD_INIT_FUNC_TRACE();
7512 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7513 rte_free(eth_dev->process_private);
7514 eth_dev->process_private = NULL;
7518 if (hw->adapter_state < HNS3_NIC_CLOSING)
7519 hns3_dev_close(eth_dev);
7521 hw->adapter_state = HNS3_NIC_REMOVED;
7526 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7527 struct rte_pci_device *pci_dev)
7529 return rte_eth_dev_pci_generic_probe(pci_dev,
7530 sizeof(struct hns3_adapter),
7535 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7537 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7540 static const struct rte_pci_id pci_id_hns3_map[] = {
7541 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7542 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7543 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7544 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7545 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7546 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7547 { .vendor_id = 0, }, /* sentinel */
7550 static struct rte_pci_driver rte_hns3_pmd = {
7551 .id_table = pci_id_hns3_map,
7552 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7553 .probe = eth_hns3_pci_probe,
7554 .remove = eth_hns3_pci_remove,
7557 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7558 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7559 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7560 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7561 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7562 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
7563 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");
7564 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
7565 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);