1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
12 #include <rte_bus_pci.h>
13 #include <rte_common.h>
14 #include <rte_cycles.h>
17 #include <rte_ether.h>
18 #include <rte_ethdev_driver.h>
19 #include <rte_ethdev_pci.h>
24 #include "hns3_ethdev.h"
25 #include "hns3_logs.h"
26 #include "hns3_regs.h"
28 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
29 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
31 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
33 int hns3_logtype_init;
34 int hns3_logtype_driver;
37 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
38 unsigned int tso_mss_max)
40 struct hns3_cfg_tso_status_cmd *req;
41 struct hns3_cmd_desc desc;
44 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
46 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
49 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
51 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
54 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
56 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
58 return hns3_cmd_send(hw, &desc, 1);
62 hns3_config_gro(struct hns3_hw *hw, bool en)
64 struct hns3_cfg_gro_status_cmd *req;
65 struct hns3_cmd_desc desc;
68 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
69 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
71 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
73 ret = hns3_cmd_send(hw, &desc, 1);
75 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
81 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
82 uint16_t *allocated_size, bool is_alloc)
84 struct hns3_umv_spc_alc_cmd *req;
85 struct hns3_cmd_desc desc;
88 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
89 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
90 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
91 req->space_size = rte_cpu_to_le_32(space_size);
93 ret = hns3_cmd_send(hw, &desc, 1);
95 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
96 is_alloc ? "allocate" : "free", ret);
100 if (is_alloc && allocated_size)
101 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
107 hns3_init_umv_space(struct hns3_hw *hw)
109 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
110 struct hns3_pf *pf = &hns->pf;
111 uint16_t allocated_size = 0;
114 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
119 if (allocated_size < pf->wanted_umv_size)
120 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
121 pf->wanted_umv_size, allocated_size);
123 pf->max_umv_size = (!!allocated_size) ? allocated_size :
125 pf->used_umv_size = 0;
130 hns3_uninit_umv_space(struct hns3_hw *hw)
132 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
133 struct hns3_pf *pf = &hns->pf;
136 if (pf->max_umv_size == 0)
139 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
143 pf->max_umv_size = 0;
149 hns3_is_umv_space_full(struct hns3_hw *hw)
151 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
152 struct hns3_pf *pf = &hns->pf;
155 is_full = (pf->used_umv_size >= pf->max_umv_size);
161 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
163 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
164 struct hns3_pf *pf = &hns->pf;
167 if (pf->used_umv_size > 0)
174 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
175 const uint8_t *addr, bool is_mc)
177 const unsigned char *mac_addr = addr;
178 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
179 ((uint32_t)mac_addr[2] << 16) |
180 ((uint32_t)mac_addr[1] << 8) |
181 (uint32_t)mac_addr[0];
182 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
184 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
186 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
187 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
188 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
191 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
192 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
196 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
198 enum hns3_mac_vlan_tbl_opcode op)
201 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
206 if (op == HNS3_MAC_VLAN_ADD) {
207 if (resp_code == 0 || resp_code == 1) {
209 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
210 hns3_err(hw, "add mac addr failed for uc_overflow");
212 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
213 hns3_err(hw, "add mac addr failed for mc_overflow");
217 hns3_err(hw, "add mac addr failed for undefined, code=%u",
220 } else if (op == HNS3_MAC_VLAN_REMOVE) {
221 if (resp_code == 0) {
223 } else if (resp_code == 1) {
224 hns3_dbg(hw, "remove mac addr failed for miss");
228 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
231 } else if (op == HNS3_MAC_VLAN_LKUP) {
232 if (resp_code == 0) {
234 } else if (resp_code == 1) {
235 hns3_dbg(hw, "lookup mac addr failed for miss");
239 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
244 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
251 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
252 struct hns3_mac_vlan_tbl_entry_cmd *req,
253 struct hns3_cmd_desc *desc, bool is_mc)
259 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
261 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
262 memcpy(desc[0].data, req,
263 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
264 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
266 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
267 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
269 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
271 memcpy(desc[0].data, req,
272 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
273 ret = hns3_cmd_send(hw, desc, 1);
276 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
280 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
281 retval = rte_le_to_cpu_16(desc[0].retval);
283 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
288 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
289 struct hns3_mac_vlan_tbl_entry_cmd *req,
290 struct hns3_cmd_desc *mc_desc)
297 if (mc_desc == NULL) {
298 struct hns3_cmd_desc desc;
300 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
301 memcpy(desc.data, req,
302 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
303 ret = hns3_cmd_send(hw, &desc, 1);
304 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
305 retval = rte_le_to_cpu_16(desc.retval);
307 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
310 hns3_cmd_reuse_desc(&mc_desc[0], false);
311 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
312 hns3_cmd_reuse_desc(&mc_desc[1], false);
313 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
314 hns3_cmd_reuse_desc(&mc_desc[2], false);
315 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
316 memcpy(mc_desc[0].data, req,
317 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
318 mc_desc[0].retval = 0;
319 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
320 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
321 retval = rte_le_to_cpu_16(mc_desc[0].retval);
323 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
328 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
336 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
337 struct hns3_mac_vlan_tbl_entry_cmd *req)
339 struct hns3_cmd_desc desc;
344 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
346 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
348 ret = hns3_cmd_send(hw, &desc, 1);
350 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
353 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
354 retval = rte_le_to_cpu_16(desc.retval);
356 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
357 HNS3_MAC_VLAN_REMOVE);
361 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
363 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
364 struct hns3_mac_vlan_tbl_entry_cmd req;
365 struct hns3_pf *pf = &hns->pf;
366 struct hns3_cmd_desc desc;
367 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
368 uint16_t egress_port = 0;
372 /* check if mac addr is valid */
373 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
374 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
376 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
381 memset(&req, 0, sizeof(req));
384 * In current version VF is not supported when PF is driven by DPDK
385 * driver, the PF-related vf_id is 0, just need to configure parameters
389 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
390 HNS3_MAC_EPORT_VFID_S, vf_id);
392 req.egress_port = rte_cpu_to_le_16(egress_port);
394 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
397 * Lookup the mac address in the mac_vlan table, and add
398 * it if the entry is inexistent. Repeated unicast entry
399 * is not allowed in the mac vlan table.
401 ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
402 if (ret == -ENOENT) {
403 if (!hns3_is_umv_space_full(hw)) {
404 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
406 hns3_update_umv_space(hw, false);
410 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
415 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
417 /* check if we just hit the duplicate */
419 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
423 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
430 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
431 uint32_t idx, __attribute__ ((unused)) uint32_t pool)
433 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
434 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
437 rte_spinlock_lock(&hw->lock);
438 ret = hns3_add_uc_addr_common(hw, mac_addr);
440 rte_spinlock_unlock(&hw->lock);
441 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
443 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
448 hw->mac.default_addr_setted = true;
449 rte_spinlock_unlock(&hw->lock);
455 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
457 struct hns3_mac_vlan_tbl_entry_cmd req;
458 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
461 /* check if mac addr is valid */
462 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
463 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
465 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
470 memset(&req, 0, sizeof(req));
471 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
472 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
473 ret = hns3_remove_mac_vlan_tbl(hw, &req);
474 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
477 hns3_update_umv_space(hw, true);
483 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
485 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
486 /* index will be checked by upper level rte interface */
487 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
488 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
491 rte_spinlock_lock(&hw->lock);
492 ret = hns3_remove_uc_addr_common(hw, mac_addr);
494 rte_spinlock_unlock(&hw->lock);
495 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
497 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
502 hw->mac.default_addr_setted = false;
503 rte_spinlock_unlock(&hw->lock);
507 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
508 struct rte_ether_addr *mac_addr)
510 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
511 struct rte_ether_addr *oaddr;
512 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
513 bool default_addr_setted;
514 bool rm_succes = false;
517 /* check if mac addr is valid */
518 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
519 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
521 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
526 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
527 default_addr_setted = hw->mac.default_addr_setted;
528 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
531 rte_spinlock_lock(&hw->lock);
532 if (default_addr_setted) {
533 ret = hns3_remove_uc_addr_common(hw, oaddr);
535 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
537 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
544 ret = hns3_add_uc_addr_common(hw, mac_addr);
546 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
548 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
549 goto err_add_uc_addr;
552 rte_ether_addr_copy(mac_addr,
553 (struct rte_ether_addr *)hw->mac.mac_addr);
554 hw->mac.default_addr_setted = true;
555 rte_spinlock_unlock(&hw->lock);
561 ret_val = hns3_add_uc_addr_common(hw, oaddr);
563 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
566 "Failed to restore old uc mac addr(%s): %d",
568 hw->mac.default_addr_setted = false;
571 rte_spinlock_unlock(&hw->lock);
577 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
579 #define HNS3_VF_NUM_IN_FIRST_DESC 192
583 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
584 word_num = vfid / 32;
587 desc[1].data[word_num] &=
588 rte_cpu_to_le_32(~(1UL << bit_num));
590 desc[1].data[word_num] |=
591 rte_cpu_to_le_32(1UL << bit_num);
593 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
596 desc[2].data[word_num] &=
597 rte_cpu_to_le_32(~(1UL << bit_num));
599 desc[2].data[word_num] |=
600 rte_cpu_to_le_32(1UL << bit_num);
605 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
607 struct hns3_mac_vlan_tbl_entry_cmd req;
608 struct hns3_cmd_desc desc[3];
609 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
613 /* Check if mac addr is valid */
614 if (!rte_is_multicast_ether_addr(mac_addr)) {
615 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
617 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
622 memset(&req, 0, sizeof(req));
623 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
624 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
625 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
627 /* This mac addr do not exist, add new entry for it */
628 memset(desc[0].data, 0, sizeof(desc[0].data));
629 memset(desc[1].data, 0, sizeof(desc[0].data));
630 memset(desc[2].data, 0, sizeof(desc[0].data));
634 * In current version VF is not supported when PF is driven by DPDK
635 * driver, the PF-related vf_id is 0, just need to configure parameters
639 hns3_update_desc_vfid(desc, vf_id, false);
640 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
643 hns3_err(hw, "mc mac vlan table is full");
644 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
646 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
653 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
655 struct hns3_mac_vlan_tbl_entry_cmd req;
656 struct hns3_cmd_desc desc[3];
657 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
661 /* Check if mac addr is valid */
662 if (!rte_is_multicast_ether_addr(mac_addr)) {
663 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
665 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
670 memset(&req, 0, sizeof(req));
671 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
672 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
673 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
676 * This mac addr exist, remove this handle's VFID for it.
677 * In current version VF is not supported when PF is driven by
678 * DPDK driver, the PF-related vf_id is 0, just need to
679 * configure parameters for vf_id 0.
682 hns3_update_desc_vfid(desc, vf_id, true);
684 /* All the vfid is zero, so need to delete this entry */
685 ret = hns3_remove_mac_vlan_tbl(hw, &req);
686 } else if (ret == -ENOENT) {
687 /* This mac addr doesn't exist. */
692 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
694 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
701 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
702 struct rte_ether_addr *mc_addr_set,
705 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
706 struct rte_ether_addr *addr;
710 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
711 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
712 "invalid. valid range: 0~%d",
713 nb_mc_addr, HNS3_MC_MACADDR_NUM);
717 /* Check if input mac addresses are valid */
718 for (i = 0; i < nb_mc_addr; i++) {
719 addr = &mc_addr_set[i];
720 if (!rte_is_multicast_ether_addr(addr)) {
721 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
724 "Failed to set mc mac addr, addr(%s) invalid.",
729 /* Check if there are duplicate addresses */
730 for (j = i + 1; j < nb_mc_addr; j++) {
731 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
732 rte_ether_format_addr(mac_str,
733 RTE_ETHER_ADDR_FMT_SIZE,
735 hns3_err(hw, "Failed to set mc mac addr, "
736 "addrs invalid. two same addrs(%s).",
747 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
748 struct rte_ether_addr *mc_addr_set,
750 struct rte_ether_addr *reserved_addr_list,
751 int *reserved_addr_num,
752 struct rte_ether_addr *add_addr_list,
754 struct rte_ether_addr *rm_addr_list,
757 struct rte_ether_addr *addr;
758 int current_addr_num;
759 int reserved_num = 0;
767 /* Calculate the mc mac address list that should be removed */
768 current_addr_num = hw->mc_addrs_num;
769 for (i = 0; i < current_addr_num; i++) {
770 addr = &hw->mc_addrs[i];
772 for (j = 0; j < mc_addr_num; j++) {
773 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
780 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
783 rte_ether_addr_copy(addr,
784 &reserved_addr_list[reserved_num]);
789 /* Calculate the mc mac address list that should be added */
790 for (i = 0; i < mc_addr_num; i++) {
791 addr = &mc_addr_set[i];
793 for (j = 0; j < current_addr_num; j++) {
794 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
801 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
806 /* Reorder the mc mac address list maintained by driver */
807 for (i = 0; i < reserved_num; i++)
808 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
810 for (i = 0; i < rm_num; i++) {
811 num = reserved_num + i;
812 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
815 *reserved_addr_num = reserved_num;
816 *add_addr_num = add_num;
817 *rm_addr_num = rm_num;
821 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
822 struct rte_ether_addr *mc_addr_set,
825 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
826 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
827 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
828 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
829 struct rte_ether_addr *addr;
830 int reserved_addr_num;
838 /* Check if input parameters are valid */
839 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
843 rte_spinlock_lock(&hw->lock);
846 * Calculate the mc mac address lists those should be removed and be
847 * added, Reorder the mc mac address list maintained by driver.
849 mc_addr_num = (int)nb_mc_addr;
850 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
851 reserved_addr_list, &reserved_addr_num,
852 add_addr_list, &add_addr_num,
853 rm_addr_list, &rm_addr_num);
855 /* Remove mc mac addresses */
856 for (i = 0; i < rm_addr_num; i++) {
857 num = rm_addr_num - i - 1;
858 addr = &rm_addr_list[num];
859 ret = hns3_remove_mc_addr(hw, addr);
861 rte_spinlock_unlock(&hw->lock);
867 /* Add mc mac addresses */
868 for (i = 0; i < add_addr_num; i++) {
869 addr = &add_addr_list[i];
870 ret = hns3_add_mc_addr(hw, addr);
872 rte_spinlock_unlock(&hw->lock);
876 num = reserved_addr_num + i;
877 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
880 rte_spinlock_unlock(&hw->lock);
886 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
888 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
889 struct hns3_hw *hw = &hns->hw;
890 struct rte_ether_addr *addr;
895 for (i = 0; i < hw->mc_addrs_num; i++) {
896 addr = &hw->mc_addrs[i];
897 if (!rte_is_multicast_ether_addr(addr))
900 ret = hns3_remove_mc_addr(hw, addr);
902 ret = hns3_add_mc_addr(hw, addr);
905 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
907 hns3_dbg(hw, "%s mc mac addr: %s failed",
908 del ? "Remove" : "Restore", mac_str);
915 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
917 struct hns3_config_max_frm_size_cmd *req;
918 struct hns3_cmd_desc desc;
920 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
922 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
923 req->max_frm_size = rte_cpu_to_le_16(new_mps);
924 req->min_frm_size = HNS3_MIN_FRAME_LEN;
926 return hns3_cmd_send(hw, &desc, 1);
930 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
934 ret = hns3_set_mac_mtu(hw, mps);
936 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
940 ret = hns3_buffer_alloc(hw);
942 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
950 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
952 struct hns3_adapter *hns = dev->data->dev_private;
953 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
954 struct hns3_hw *hw = &hns->hw;
958 if (dev->data->dev_started) {
959 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
960 "before configuration", dev->data->port_id);
964 rte_spinlock_lock(&hw->lock);
965 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
966 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
969 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
970 * assign to "uint16_t" type variable.
972 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
974 rte_spinlock_unlock(&hw->lock);
975 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
976 dev->data->port_id, mtu, ret);
979 hns->pf.mps = (uint16_t)frame_size;
981 dev->data->dev_conf.rxmode.offloads |=
982 DEV_RX_OFFLOAD_JUMBO_FRAME;
984 dev->data->dev_conf.rxmode.offloads &=
985 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
986 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
987 rte_spinlock_unlock(&hw->lock);
993 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
995 struct hns3_adapter *hns = eth_dev->data->dev_private;
996 struct hns3_hw *hw = &hns->hw;
998 info->max_rx_queues = hw->tqps_num;
999 info->max_tx_queues = hw->tqps_num;
1000 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
1001 info->min_rx_bufsize = hw->rx_buf_len;
1002 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
1003 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
1004 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
1005 DEV_RX_OFFLOAD_TCP_CKSUM |
1006 DEV_RX_OFFLOAD_UDP_CKSUM |
1007 DEV_RX_OFFLOAD_SCTP_CKSUM |
1008 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1009 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1010 DEV_RX_OFFLOAD_KEEP_CRC |
1011 DEV_RX_OFFLOAD_SCATTER |
1012 DEV_RX_OFFLOAD_VLAN_STRIP |
1013 DEV_RX_OFFLOAD_QINQ_STRIP |
1014 DEV_RX_OFFLOAD_VLAN_FILTER |
1015 DEV_RX_OFFLOAD_VLAN_EXTEND |
1016 DEV_RX_OFFLOAD_JUMBO_FRAME);
1017 info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
1018 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1019 DEV_TX_OFFLOAD_IPV4_CKSUM |
1020 DEV_TX_OFFLOAD_TCP_CKSUM |
1021 DEV_TX_OFFLOAD_UDP_CKSUM |
1022 DEV_TX_OFFLOAD_SCTP_CKSUM |
1023 DEV_TX_OFFLOAD_VLAN_INSERT |
1024 DEV_TX_OFFLOAD_QINQ_INSERT |
1025 DEV_TX_OFFLOAD_MULTI_SEGS |
1026 info->tx_queue_offload_capa);
1028 info->vmdq_queue_num = 0;
1030 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1031 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1032 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1033 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1039 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1042 struct hns3_adapter *hns = eth_dev->data->dev_private;
1043 struct hns3_hw *hw = &hns->hw;
1046 ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
1047 ret += 1; /* add the size of '\0' */
1048 if (fw_size < (uint32_t)ret)
1055 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
1056 __rte_unused int wait_to_complete)
1058 struct hns3_adapter *hns = eth_dev->data->dev_private;
1059 struct hns3_hw *hw = &hns->hw;
1060 struct hns3_mac *mac = &hw->mac;
1061 struct rte_eth_link new_link;
1063 memset(&new_link, 0, sizeof(new_link));
1064 switch (mac->link_speed) {
1065 case ETH_SPEED_NUM_10M:
1066 case ETH_SPEED_NUM_100M:
1067 case ETH_SPEED_NUM_1G:
1068 case ETH_SPEED_NUM_10G:
1069 case ETH_SPEED_NUM_25G:
1070 case ETH_SPEED_NUM_40G:
1071 case ETH_SPEED_NUM_50G:
1072 case ETH_SPEED_NUM_100G:
1073 new_link.link_speed = mac->link_speed;
1076 new_link.link_speed = ETH_SPEED_NUM_100M;
1080 new_link.link_duplex = mac->link_duplex;
1081 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1082 new_link.link_autoneg =
1083 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1085 return rte_eth_linkstatus_set(eth_dev, &new_link);
1089 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
1091 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1092 struct hns3_pf *pf = &hns->pf;
1094 if (!(status->pf_state & HNS3_PF_STATE_DONE))
1097 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
1103 hns3_query_function_status(struct hns3_hw *hw)
1105 #define HNS3_QUERY_MAX_CNT 10
1106 #define HNS3_QUERY_SLEEP_MSCOEND 1
1107 struct hns3_func_status_cmd *req;
1108 struct hns3_cmd_desc desc;
1112 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
1113 req = (struct hns3_func_status_cmd *)desc.data;
1116 ret = hns3_cmd_send(hw, &desc, 1);
1118 PMD_INIT_LOG(ERR, "query function status failed %d",
1123 /* Check pf reset is done */
1127 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
1128 } while (timeout++ < HNS3_QUERY_MAX_CNT);
1130 return hns3_parse_func_status(hw, req);
1134 hns3_query_pf_resource(struct hns3_hw *hw)
1136 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1137 struct hns3_pf *pf = &hns->pf;
1138 struct hns3_pf_res_cmd *req;
1139 struct hns3_cmd_desc desc;
1142 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
1143 ret = hns3_cmd_send(hw, &desc, 1);
1145 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
1149 req = (struct hns3_pf_res_cmd *)desc.data;
1150 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
1151 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
1152 hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1154 if (req->tx_buf_size)
1156 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
1158 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
1160 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
1162 if (req->dv_buf_size)
1164 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
1166 pf->dv_buf_size = HNS3_DEFAULT_DV;
1168 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
1171 hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
1172 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
1178 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
1180 struct hns3_cfg_param_cmd *req;
1181 uint64_t mac_addr_tmp_high;
1182 uint64_t mac_addr_tmp;
1185 req = (struct hns3_cfg_param_cmd *)desc[0].data;
1187 /* get the configuration */
1188 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1189 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
1190 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1191 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
1192 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1193 HNS3_CFG_TQP_DESC_N_M,
1194 HNS3_CFG_TQP_DESC_N_S);
1196 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1197 HNS3_CFG_PHY_ADDR_M,
1198 HNS3_CFG_PHY_ADDR_S);
1199 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1200 HNS3_CFG_MEDIA_TP_M,
1201 HNS3_CFG_MEDIA_TP_S);
1202 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1203 HNS3_CFG_RX_BUF_LEN_M,
1204 HNS3_CFG_RX_BUF_LEN_S);
1205 /* get mac address */
1206 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
1207 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1208 HNS3_CFG_MAC_ADDR_H_M,
1209 HNS3_CFG_MAC_ADDR_H_S);
1211 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1213 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1214 HNS3_CFG_DEFAULT_SPEED_M,
1215 HNS3_CFG_DEFAULT_SPEED_S);
1216 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1217 HNS3_CFG_RSS_SIZE_M,
1218 HNS3_CFG_RSS_SIZE_S);
1220 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
1221 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1223 req = (struct hns3_cfg_param_cmd *)desc[1].data;
1224 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
1226 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1227 HNS3_CFG_SPEED_ABILITY_M,
1228 HNS3_CFG_SPEED_ABILITY_S);
1229 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1230 HNS3_CFG_UMV_TBL_SPACE_M,
1231 HNS3_CFG_UMV_TBL_SPACE_S);
1232 if (!cfg->umv_space)
1233 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
1236 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
1237 * @hw: pointer to struct hns3_hw
1238 * @hcfg: the config structure to be getted
1241 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
1243 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
1244 struct hns3_cfg_param_cmd *req;
1249 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
1251 req = (struct hns3_cfg_param_cmd *)desc[i].data;
1252 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
1254 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
1255 i * HNS3_CFG_RD_LEN_BYTES);
1256 /* Len should be divided by 4 when send to hardware */
1257 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
1258 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
1259 req->offset = rte_cpu_to_le_32(offset);
1262 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
1264 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
1268 hns3_parse_cfg(hcfg, desc);
1274 hns3_parse_speed(int speed_cmd, uint32_t *speed)
1276 switch (speed_cmd) {
1277 case HNS3_CFG_SPEED_10M:
1278 *speed = ETH_SPEED_NUM_10M;
1280 case HNS3_CFG_SPEED_100M:
1281 *speed = ETH_SPEED_NUM_100M;
1283 case HNS3_CFG_SPEED_1G:
1284 *speed = ETH_SPEED_NUM_1G;
1286 case HNS3_CFG_SPEED_10G:
1287 *speed = ETH_SPEED_NUM_10G;
1289 case HNS3_CFG_SPEED_25G:
1290 *speed = ETH_SPEED_NUM_25G;
1292 case HNS3_CFG_SPEED_40G:
1293 *speed = ETH_SPEED_NUM_40G;
1295 case HNS3_CFG_SPEED_50G:
1296 *speed = ETH_SPEED_NUM_50G;
1298 case HNS3_CFG_SPEED_100G:
1299 *speed = ETH_SPEED_NUM_100G;
1309 hns3_get_board_configuration(struct hns3_hw *hw)
1311 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1312 struct hns3_pf *pf = &hns->pf;
1313 struct hns3_cfg cfg;
1316 ret = hns3_get_board_cfg(hw, &cfg);
1318 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
1322 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
1323 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
1327 hw->mac.media_type = cfg.media_type;
1328 hw->rss_size_max = cfg.rss_size_max;
1329 hw->rx_buf_len = cfg.rx_buf_len;
1330 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
1331 hw->mac.phy_addr = cfg.phy_addr;
1332 hw->mac.default_addr_setted = false;
1333 hw->num_tx_desc = cfg.tqp_desc_num;
1334 hw->num_rx_desc = cfg.tqp_desc_num;
1335 hw->dcb_info.num_pg = 1;
1336 hw->dcb_info.hw_pfc_map = 0;
1338 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
1340 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
1341 cfg.default_speed, ret);
1345 pf->tc_max = cfg.tc_num;
1346 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
1347 PMD_INIT_LOG(WARNING,
1348 "Get TC num(%u) from flash, set TC num to 1",
1353 /* Dev does not support DCB */
1354 if (!hns3_dev_dcb_supported(hw)) {
1358 pf->pfc_max = pf->tc_max;
1360 hw->dcb_info.num_tc = 1;
1361 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
1362 hw->tqps_num / hw->dcb_info.num_tc);
1363 hns3_set_bit(hw->hw_tc_map, 0, 1);
1364 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
1366 pf->wanted_umv_size = cfg.umv_space;
1372 hns3_get_configuration(struct hns3_hw *hw)
1376 ret = hns3_query_function_status(hw);
1378 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
1382 /* Get pf resource */
1383 ret = hns3_query_pf_resource(hw);
1385 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
1389 ret = hns3_get_board_configuration(hw);
1391 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
1399 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
1400 uint16_t tqp_vid, bool is_pf)
1402 struct hns3_tqp_map_cmd *req;
1403 struct hns3_cmd_desc desc;
1406 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
1408 req = (struct hns3_tqp_map_cmd *)desc.data;
1409 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
1410 req->tqp_vf = func_id;
1411 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
1413 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
1414 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
1416 ret = hns3_cmd_send(hw, &desc, 1);
1418 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
1424 hns3_map_tqp(struct hns3_hw *hw)
1426 uint16_t tqps_num = hw->total_tqps_num;
1434 * In current version VF is not supported when PF is driven by DPDK
1435 * driver, so we allocate tqps to PF as much as possible.
1438 num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1439 for (func_id = 0; func_id < num; func_id++) {
1441 i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
1442 ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
1453 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
1455 struct hns3_config_mac_speed_dup_cmd *req;
1456 struct hns3_cmd_desc desc;
1459 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
1461 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
1463 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
1466 case ETH_SPEED_NUM_10M:
1467 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1468 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
1470 case ETH_SPEED_NUM_100M:
1471 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1472 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
1474 case ETH_SPEED_NUM_1G:
1475 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1476 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
1478 case ETH_SPEED_NUM_10G:
1479 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1480 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
1482 case ETH_SPEED_NUM_25G:
1483 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1484 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
1486 case ETH_SPEED_NUM_40G:
1487 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1488 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
1490 case ETH_SPEED_NUM_50G:
1491 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1492 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
1494 case ETH_SPEED_NUM_100G:
1495 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1496 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
1499 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
1503 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
1505 ret = hns3_cmd_send(hw, &desc, 1);
1507 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
1513 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1515 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1516 struct hns3_pf *pf = &hns->pf;
1517 struct hns3_priv_buf *priv;
1518 uint32_t i, total_size;
1520 total_size = pf->pkt_buf_size;
1522 /* alloc tx buffer for all enabled tc */
1523 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1524 priv = &buf_alloc->priv_buf[i];
1526 if (hw->hw_tc_map & BIT(i)) {
1527 if (total_size < pf->tx_buf_size)
1530 priv->tx_buf_size = pf->tx_buf_size;
1532 priv->tx_buf_size = 0;
1534 total_size -= priv->tx_buf_size;
1541 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1543 /* TX buffer size is unit by 128 byte */
1544 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
1545 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1546 struct hns3_tx_buff_alloc_cmd *req;
1547 struct hns3_cmd_desc desc;
1552 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
1554 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
1555 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1556 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1558 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
1559 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
1560 HNS3_BUF_SIZE_UPDATE_EN_MSK);
1563 ret = hns3_cmd_send(hw, &desc, 1);
1565 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
1571 hns3_get_tc_num(struct hns3_hw *hw)
1576 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1577 if (hw->hw_tc_map & BIT(i))
1583 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
1585 struct hns3_priv_buf *priv;
1586 uint32_t rx_priv = 0;
1589 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1590 priv = &buf_alloc->priv_buf[i];
1592 rx_priv += priv->buf_size;
1598 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
1600 uint32_t total_tx_size = 0;
1603 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1604 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1606 return total_tx_size;
1609 /* Get the number of pfc enabled TCs, which have private buffer */
1611 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1613 struct hns3_priv_buf *priv;
1617 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1618 priv = &buf_alloc->priv_buf[i];
1619 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
1626 /* Get the number of pfc disabled TCs, which have private buffer */
1628 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
1629 struct hns3_pkt_buf_alloc *buf_alloc)
1631 struct hns3_priv_buf *priv;
1635 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1636 priv = &buf_alloc->priv_buf[i];
1637 if (hw->hw_tc_map & BIT(i) &&
1638 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
1646 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
1649 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
1650 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1651 struct hns3_pf *pf = &hns->pf;
1652 uint32_t shared_buf, aligned_mps;
1657 tc_num = hns3_get_tc_num(hw);
1658 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
1660 if (hns3_dev_dcb_supported(hw))
1661 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
1664 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
1667 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
1668 shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
1669 HNS3_BUF_SIZE_UNIT);
1671 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
1672 if (rx_all < rx_priv + shared_std)
1675 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
1676 buf_alloc->s_buf.buf_size = shared_buf;
1677 if (hns3_dev_dcb_supported(hw)) {
1678 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
1679 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
1680 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
1681 HNS3_BUF_SIZE_UNIT);
1683 buf_alloc->s_buf.self.high =
1684 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
1685 buf_alloc->s_buf.self.low = aligned_mps;
1688 if (hns3_dev_dcb_supported(hw)) {
1689 hi_thrd = shared_buf - pf->dv_buf_size;
1691 if (tc_num <= NEED_RESERVE_TC_NUM)
1692 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
1696 hi_thrd = hi_thrd / tc_num;
1698 hi_thrd = max_t(uint32_t, hi_thrd,
1699 HNS3_BUF_MUL_BY * aligned_mps);
1700 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
1701 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
1703 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
1704 lo_thrd = aligned_mps;
1707 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1708 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
1709 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
1716 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
1717 struct hns3_pkt_buf_alloc *buf_alloc)
1719 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1720 struct hns3_pf *pf = &hns->pf;
1721 struct hns3_priv_buf *priv;
1722 uint32_t aligned_mps;
1726 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1727 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
1729 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1730 priv = &buf_alloc->priv_buf[i];
1737 if (!(hw->hw_tc_map & BIT(i)))
1741 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
1742 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
1743 priv->wl.high = roundup(priv->wl.low + aligned_mps,
1744 HNS3_BUF_SIZE_UNIT);
1747 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
1751 priv->buf_size = priv->wl.high + pf->dv_buf_size;
1754 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1758 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
1759 struct hns3_pkt_buf_alloc *buf_alloc)
1761 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1762 struct hns3_pf *pf = &hns->pf;
1763 struct hns3_priv_buf *priv;
1764 int no_pfc_priv_num;
1769 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1770 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
1772 /* let the last to be cleared first */
1773 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
1774 priv = &buf_alloc->priv_buf[i];
1775 mask = BIT((uint8_t)i);
1777 if (hw->hw_tc_map & mask &&
1778 !(hw->dcb_info.hw_pfc_map & mask)) {
1779 /* Clear the no pfc TC private buffer */
1787 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
1788 no_pfc_priv_num == 0)
1792 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1796 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
1797 struct hns3_pkt_buf_alloc *buf_alloc)
1799 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1800 struct hns3_pf *pf = &hns->pf;
1801 struct hns3_priv_buf *priv;
1807 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1808 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
1810 /* let the last to be cleared first */
1811 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
1812 priv = &buf_alloc->priv_buf[i];
1813 mask = BIT((uint8_t)i);
1815 if (hw->hw_tc_map & mask &&
1816 hw->dcb_info.hw_pfc_map & mask) {
1817 /* Reduce the number of pfc TC with private buffer */
1824 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
1829 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1833 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
1834 struct hns3_pkt_buf_alloc *buf_alloc)
1836 #define COMPENSATE_BUFFER 0x3C00
1837 #define COMPENSATE_HALF_MPS_NUM 5
1838 #define PRIV_WL_GAP 0x1800
1839 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1840 struct hns3_pf *pf = &hns->pf;
1841 uint32_t tc_num = hns3_get_tc_num(hw);
1842 uint32_t half_mps = pf->mps >> 1;
1843 struct hns3_priv_buf *priv;
1844 uint32_t min_rx_priv;
1848 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1850 rx_priv = rx_priv / tc_num;
1852 if (tc_num <= NEED_RESERVE_TC_NUM)
1853 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
1856 * Minimum value of private buffer in rx direction (min_rx_priv) is
1857 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
1858 * buffer if rx_priv is greater than min_rx_priv.
1860 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
1861 COMPENSATE_HALF_MPS_NUM * half_mps;
1862 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
1863 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
1865 if (rx_priv < min_rx_priv)
1868 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1869 priv = &buf_alloc->priv_buf[i];
1876 if (!(hw->hw_tc_map & BIT(i)))
1880 priv->buf_size = rx_priv;
1881 priv->wl.high = rx_priv - pf->dv_buf_size;
1882 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
1885 buf_alloc->s_buf.buf_size = 0;
1891 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
1892 * @hw: pointer to struct hns3_hw
1893 * @buf_alloc: pointer to buffer calculation data
1894 * @return: 0: calculate sucessful, negative: fail
1897 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1899 /* When DCB is not supported, rx private buffer is not allocated. */
1900 if (!hns3_dev_dcb_supported(hw)) {
1901 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1902 struct hns3_pf *pf = &hns->pf;
1903 uint32_t rx_all = pf->pkt_buf_size;
1905 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
1906 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
1913 * Try to allocate privated packet buffer for all TCs without share
1916 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
1920 * Try to allocate privated packet buffer for all TCs with share
1923 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
1927 * For different application scenes, the enabled port number, TC number
1928 * and no_drop TC number are different. In order to obtain the better
1929 * performance, software could allocate the buffer size and configure
1930 * the waterline by tring to decrease the private buffer size according
1931 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
1934 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
1937 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
1940 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
1947 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1949 struct hns3_rx_priv_buff_cmd *req;
1950 struct hns3_cmd_desc desc;
1955 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
1956 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
1958 /* Alloc private buffer TCs */
1959 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1960 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
1963 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
1964 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
1967 buf_size = buf_alloc->s_buf.buf_size;
1968 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
1969 (1 << HNS3_TC0_PRI_BUF_EN_B));
1971 ret = hns3_cmd_send(hw, &desc, 1);
1973 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
1979 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1981 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
1982 struct hns3_rx_priv_wl_buf *req;
1983 struct hns3_priv_buf *priv;
1984 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
1988 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
1989 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
1991 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
1993 /* The first descriptor set the NEXT bit to 1 */
1995 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1997 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1999 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
2000 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
2002 priv = &buf_alloc->priv_buf[idx];
2003 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
2005 req->tc_wl[j].high |=
2006 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2007 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
2009 req->tc_wl[j].low |=
2010 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2014 /* Send 2 descriptor at one time */
2015 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
2017 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
2023 hns3_common_thrd_config(struct hns3_hw *hw,
2024 struct hns3_pkt_buf_alloc *buf_alloc)
2026 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
2027 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
2028 struct hns3_rx_com_thrd *req;
2029 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
2030 struct hns3_tc_thrd *tc;
2035 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
2036 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
2038 req = (struct hns3_rx_com_thrd *)&desc[i].data;
2040 /* The first descriptor set the NEXT bit to 1 */
2042 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2044 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2046 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
2047 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
2048 tc = &s_buf->tc_thrd[tc_idx];
2050 req->com_thrd[j].high =
2051 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
2052 req->com_thrd[j].high |=
2053 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2054 req->com_thrd[j].low =
2055 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
2056 req->com_thrd[j].low |=
2057 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2061 /* Send 2 descriptors at one time */
2062 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
2064 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
2070 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2072 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
2073 struct hns3_rx_com_wl *req;
2074 struct hns3_cmd_desc desc;
2077 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
2079 req = (struct hns3_rx_com_wl *)desc.data;
2080 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
2081 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2083 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
2084 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2086 ret = hns3_cmd_send(hw, &desc, 1);
2088 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
2094 hns3_buffer_alloc(struct hns3_hw *hw)
2096 struct hns3_pkt_buf_alloc pkt_buf;
2099 memset(&pkt_buf, 0, sizeof(pkt_buf));
2100 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
2103 "could not calc tx buffer size for all TCs %d",
2108 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
2110 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
2114 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
2117 "could not calc rx priv buffer size for all TCs %d",
2122 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
2124 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
2128 if (hns3_dev_dcb_supported(hw)) {
2129 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
2132 "could not configure rx private waterline %d",
2137 ret = hns3_common_thrd_config(hw, &pkt_buf);
2140 "could not configure common threshold %d",
2146 ret = hns3_common_wl_config(hw, &pkt_buf);
2148 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
2155 hns3_mac_init(struct hns3_hw *hw)
2157 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2158 struct hns3_mac *mac = &hw->mac;
2159 struct hns3_pf *pf = &hns->pf;
2162 pf->support_sfp_query = true;
2163 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
2164 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
2166 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
2170 mac->link_status = ETH_LINK_DOWN;
2172 return hns3_config_mtu(hw, pf->mps);
2176 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
2178 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
2179 #define HNS3_ETHERTYPE_ALREADY_ADD 1
2180 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
2181 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
2186 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
2191 switch (resp_code) {
2192 case HNS3_ETHERTYPE_SUCCESS_ADD:
2193 case HNS3_ETHERTYPE_ALREADY_ADD:
2196 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
2198 "add mac ethertype failed for manager table overflow.");
2199 return_status = -EIO;
2201 case HNS3_ETHERTYPE_KEY_CONFLICT:
2202 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
2203 return_status = -EIO;
2207 "add mac ethertype failed for undefined, code=%d.",
2209 return_status = -EIO;
2212 return return_status;
2216 hns3_add_mgr_tbl(struct hns3_hw *hw,
2217 const struct hns3_mac_mgr_tbl_entry_cmd *req)
2219 struct hns3_cmd_desc desc;
2224 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
2225 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
2227 ret = hns3_cmd_send(hw, &desc, 1);
2230 "add mac ethertype failed for cmd_send, ret =%d.",
2235 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
2236 retval = rte_le_to_cpu_16(desc.retval);
2238 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
2242 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
2243 int *table_item_num)
2245 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
2248 * In current version, we add one item in management table as below:
2249 * 0x0180C200000E -- LLDP MC address
2252 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
2253 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
2254 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
2255 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
2256 tbl->i_port_bitmap = 0x1;
2257 *table_item_num = 1;
2261 hns3_init_mgr_tbl(struct hns3_hw *hw)
2263 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
2264 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
2269 memset(mgr_table, 0, sizeof(mgr_table));
2270 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
2271 for (i = 0; i < table_item_num; i++) {
2272 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
2274 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
2284 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
2285 bool en_mc, bool en_bc, int vport_id)
2290 memset(param, 0, sizeof(struct hns3_promisc_param));
2292 param->enable = HNS3_PROMISC_EN_UC;
2294 param->enable |= HNS3_PROMISC_EN_MC;
2296 param->enable |= HNS3_PROMISC_EN_BC;
2297 param->vf_id = vport_id;
2301 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
2303 struct hns3_promisc_cfg_cmd *req;
2304 struct hns3_cmd_desc desc;
2307 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
2309 req = (struct hns3_promisc_cfg_cmd *)desc.data;
2310 req->vf_id = param->vf_id;
2311 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
2312 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
2314 ret = hns3_cmd_send(hw, &desc, 1);
2316 PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret);
2322 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
2324 struct hns3_promisc_param param;
2325 bool en_bc_pmc = true;
2330 * In current version VF is not supported when PF is driven by DPDK
2331 * driver, the PF-related vf_id is 0, just need to configure parameters
2336 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
2337 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
2345 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
2347 struct hns3_sfp_speed_cmd *resp;
2348 struct hns3_cmd_desc desc;
2351 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
2352 resp = (struct hns3_sfp_speed_cmd *)desc.data;
2353 ret = hns3_cmd_send(hw, &desc, 1);
2354 if (ret == -EOPNOTSUPP) {
2355 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
2358 hns3_err(hw, "get sfp speed failed %d", ret);
2362 *speed = resp->sfp_speed;
2368 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
2370 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
2371 duplex = ETH_LINK_FULL_DUPLEX;
2377 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2379 struct hns3_mac *mac = &hw->mac;
2382 duplex = hns3_check_speed_dup(duplex, speed);
2383 if (mac->link_speed == speed && mac->link_duplex == duplex)
2386 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
2390 mac->link_speed = speed;
2391 mac->link_duplex = duplex;
2397 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
2399 struct hns3_adapter *hns = eth_dev->data->dev_private;
2400 struct hns3_hw *hw = &hns->hw;
2401 struct hns3_pf *pf = &hns->pf;
2405 /* If IMP do not support get SFP/qSFP speed, return directly */
2406 if (!pf->support_sfp_query)
2409 ret = hns3_get_sfp_speed(hw, &speed);
2410 if (ret == -EOPNOTSUPP) {
2411 pf->support_sfp_query = false;
2416 if (speed == ETH_SPEED_NUM_NONE)
2417 return 0; /* do nothing if no SFP */
2419 /* Config full duplex for SFP */
2420 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
2424 hns3_get_mac_link_status(struct hns3_hw *hw)
2426 struct hns3_link_status_cmd *req;
2427 struct hns3_cmd_desc desc;
2431 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
2432 ret = hns3_cmd_send(hw, &desc, 1);
2434 hns3_err(hw, "get link status cmd failed %d", ret);
2438 req = (struct hns3_link_status_cmd *)desc.data;
2439 link_status = req->status & HNS3_LINK_STATUS_UP_M;
2441 return !!link_status;
2445 hns3_update_link_status(struct hns3_hw *hw)
2449 state = hns3_get_mac_link_status(hw);
2450 if (state != hw->mac.link_status)
2451 hw->mac.link_status = state;
2455 hns3_service_handler(void *param)
2457 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
2458 struct hns3_adapter *hns = eth_dev->data->dev_private;
2459 struct hns3_hw *hw = &hns->hw;
2461 hns3_update_speed_duplex(eth_dev);
2462 hns3_update_link_status(hw);
2464 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
2468 hns3_init_hardware(struct hns3_adapter *hns)
2470 struct hns3_hw *hw = &hns->hw;
2473 ret = hns3_map_tqp(hw);
2475 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
2479 ret = hns3_init_umv_space(hw);
2481 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
2485 ret = hns3_mac_init(hw);
2487 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
2491 ret = hns3_init_mgr_tbl(hw);
2493 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
2497 ret = hns3_set_promisc_mode(hw, false, false);
2499 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
2503 ret = hns3_init_fd_config(hns);
2505 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
2509 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
2511 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
2515 ret = hns3_config_gro(hw, false);
2517 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
2523 hns3_uninit_umv_space(hw);
2528 hns3_init_pf(struct rte_eth_dev *eth_dev)
2530 struct rte_device *dev = eth_dev->device;
2531 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
2532 struct hns3_adapter *hns = eth_dev->data->dev_private;
2533 struct hns3_hw *hw = &hns->hw;
2536 PMD_INIT_FUNC_TRACE();
2538 /* Get hardware io base address from pcie BAR2 IO space */
2539 hw->io_base = pci_dev->mem_resource[2].addr;
2541 /* Firmware command queue initialize */
2542 ret = hns3_cmd_init_queue(hw);
2544 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
2545 goto err_cmd_init_queue;
2548 /* Firmware command initialize */
2549 ret = hns3_cmd_init(hw);
2551 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
2555 /* Get configuration */
2556 ret = hns3_get_configuration(hw);
2558 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
2559 goto err_get_config;
2562 ret = hns3_init_hardware(hns);
2564 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
2565 goto err_get_config;
2568 /* Initialize flow director filter list & hash */
2569 ret = hns3_fdir_filter_init(hns);
2571 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
2578 hns3_uninit_umv_space(hw);
2581 hns3_cmd_uninit(hw);
2584 hns3_cmd_destroy_queue(hw);
2593 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
2595 struct hns3_adapter *hns = eth_dev->data->dev_private;
2596 struct hns3_hw *hw = &hns->hw;
2598 PMD_INIT_FUNC_TRACE();
2600 hns3_fdir_filter_uninit(hns);
2601 hns3_uninit_umv_space(hw);
2602 hns3_cmd_uninit(hw);
2603 hns3_cmd_destroy_queue(hw);
2608 hns3_dev_close(struct rte_eth_dev *eth_dev)
2610 struct hns3_adapter *hns = eth_dev->data->dev_private;
2611 struct hns3_hw *hw = &hns->hw;
2613 hw->adapter_state = HNS3_NIC_CLOSING;
2614 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
2616 hns3_configure_all_mc_mac_addr(hns, true);
2617 hns3_uninit_pf(eth_dev);
2618 rte_free(eth_dev->process_private);
2619 eth_dev->process_private = NULL;
2620 hw->adapter_state = HNS3_NIC_CLOSED;
2623 static const struct eth_dev_ops hns3_eth_dev_ops = {
2624 .dev_close = hns3_dev_close,
2625 .mtu_set = hns3_dev_mtu_set,
2626 .dev_infos_get = hns3_dev_infos_get,
2627 .fw_version_get = hns3_fw_version_get,
2628 .mac_addr_add = hns3_add_mac_addr,
2629 .mac_addr_remove = hns3_remove_mac_addr,
2630 .mac_addr_set = hns3_set_default_mac_addr,
2631 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
2632 .link_update = hns3_dev_link_update,
2633 .filter_ctrl = hns3_dev_filter_ctrl,
2637 hns3_dev_init(struct rte_eth_dev *eth_dev)
2639 struct hns3_adapter *hns = eth_dev->data->dev_private;
2640 struct hns3_hw *hw = &hns->hw;
2643 PMD_INIT_FUNC_TRACE();
2644 eth_dev->process_private = (struct hns3_process_private *)
2645 rte_zmalloc_socket("hns3_filter_list",
2646 sizeof(struct hns3_process_private),
2647 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2648 if (eth_dev->process_private == NULL) {
2649 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2652 /* initialize flow filter lists */
2653 hns3_filterlist_init(eth_dev);
2655 eth_dev->dev_ops = &hns3_eth_dev_ops;
2656 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2659 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2661 hw->data = eth_dev->data;
2664 * Set default max packet size according to the mtu
2665 * default vale in DPDK frame.
2667 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
2669 ret = hns3_init_pf(eth_dev);
2671 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
2675 /* Allocate memory for storing MAC addresses */
2676 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
2677 sizeof(struct rte_ether_addr) *
2678 HNS3_UC_MACADDR_NUM, 0);
2679 if (eth_dev->data->mac_addrs == NULL) {
2680 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2681 "to store MAC addresses",
2682 sizeof(struct rte_ether_addr) *
2683 HNS3_UC_MACADDR_NUM);
2685 goto err_rte_zmalloc;
2688 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2689 ð_dev->data->mac_addrs[0]);
2691 hw->adapter_state = HNS3_NIC_INITIALIZED;
2693 * Pass the information to the rte_eth_dev_close() that it should also
2694 * release the private port resources.
2696 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2698 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
2699 hns3_info(hw, "hns3 dev initialization successful!");
2703 hns3_uninit_pf(eth_dev);
2706 eth_dev->dev_ops = NULL;
2707 eth_dev->rx_pkt_burst = NULL;
2708 eth_dev->tx_pkt_burst = NULL;
2709 eth_dev->tx_pkt_prepare = NULL;
2710 rte_free(eth_dev->process_private);
2711 eth_dev->process_private = NULL;
2716 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
2718 struct hns3_adapter *hns = eth_dev->data->dev_private;
2719 struct hns3_hw *hw = &hns->hw;
2721 PMD_INIT_FUNC_TRACE();
2723 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2726 eth_dev->dev_ops = NULL;
2727 eth_dev->rx_pkt_burst = NULL;
2728 eth_dev->tx_pkt_burst = NULL;
2729 eth_dev->tx_pkt_prepare = NULL;
2730 if (hw->adapter_state < HNS3_NIC_CLOSING)
2731 hns3_dev_close(eth_dev);
2733 hw->adapter_state = HNS3_NIC_REMOVED;
2738 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2739 struct rte_pci_device *pci_dev)
2741 return rte_eth_dev_pci_generic_probe(pci_dev,
2742 sizeof(struct hns3_adapter),
2747 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
2749 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
2752 static const struct rte_pci_id pci_id_hns3_map[] = {
2753 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
2754 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
2755 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
2756 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
2757 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
2758 { .vendor_id = 0, /* sentinel */ },
2761 static struct rte_pci_driver rte_hns3_pmd = {
2762 .id_table = pci_id_hns3_map,
2763 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2764 .probe = eth_hns3_pci_probe,
2765 .remove = eth_hns3_pci_remove,
2768 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
2769 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
2770 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
2772 RTE_INIT(hns3_init_log)
2774 hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
2775 if (hns3_logtype_init >= 0)
2776 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
2777 hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
2778 if (hns3_logtype_driver >= 0)
2779 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);