1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
6 #include <rte_bus_pci.h>
7 #include <ethdev_pci.h>
9 #include <rte_kvargs.h>
11 #include "hns3_ethdev.h"
12 #include "hns3_logs.h"
13 #include "hns3_rxtx.h"
14 #include "hns3_intr.h"
15 #include "hns3_regs.h"
19 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
20 #define HNS3_SERVICE_QUICK_INTERVAL 10
21 #define HNS3_INVALID_PVID 0xFFFF
23 #define HNS3_FILTER_TYPE_VF 0
24 #define HNS3_FILTER_TYPE_PORT 1
25 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
26 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
27 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
28 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
29 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
30 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
31 | HNS3_FILTER_FE_ROCE_EGRESS_B)
32 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
33 | HNS3_FILTER_FE_ROCE_INGRESS_B)
35 /* Reset related Registers */
36 #define HNS3_GLOBAL_RESET_BIT 0
37 #define HNS3_CORE_RESET_BIT 1
38 #define HNS3_IMP_RESET_BIT 2
39 #define HNS3_FUN_RST_ING_B 0
41 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
42 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
43 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U
44 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
46 #define HNS3_RESET_WAIT_MS 100
47 #define HNS3_RESET_WAIT_CNT 200
49 /* FEC mode order defined in HNS3 hardware */
50 #define HNS3_HW_FEC_MODE_NOFEC 0
51 #define HNS3_HW_FEC_MODE_BASER 1
52 #define HNS3_HW_FEC_MODE_RS 2
55 HNS3_VECTOR0_EVENT_RST,
56 HNS3_VECTOR0_EVENT_MBX,
57 HNS3_VECTOR0_EVENT_ERR,
58 HNS3_VECTOR0_EVENT_PTP,
59 HNS3_VECTOR0_EVENT_OTHER,
62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
63 { RTE_ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
64 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
65 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
67 { RTE_ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
68 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
69 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
70 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
72 { RTE_ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
73 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
74 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
76 { RTE_ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
77 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
78 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
79 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
81 { RTE_ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
82 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
83 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
85 { RTE_ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
86 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
87 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
95 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
96 static bool hns3_update_link_status(struct hns3_hw *hw);
98 static int hns3_add_mc_mac_addr(struct hns3_hw *hw,
99 struct rte_ether_addr *mac_addr);
100 static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
101 struct rte_ether_addr *mac_addr);
102 static int hns3_restore_fec(struct hns3_hw *hw);
103 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
104 static int hns3_do_stop(struct hns3_adapter *hns);
105 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
106 static int hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable);
108 void hns3_ether_format_addr(char *buf, uint16_t size,
109 const struct rte_ether_addr *ether_addr)
111 snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
112 ether_addr->addr_bytes[0],
113 ether_addr->addr_bytes[4],
114 ether_addr->addr_bytes[5]);
118 hns3_pf_disable_irq0(struct hns3_hw *hw)
120 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
124 hns3_pf_enable_irq0(struct hns3_hw *hw)
126 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
129 static enum hns3_evt_cause
130 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
133 struct hns3_hw *hw = &hns->hw;
135 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
136 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
137 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
139 hw->reset.stats.imp_cnt++;
140 hns3_warn(hw, "IMP reset detected, clear reset status");
142 hns3_schedule_delayed_reset(hns);
143 hns3_warn(hw, "IMP reset detected, don't clear reset status");
146 return HNS3_VECTOR0_EVENT_RST;
149 static enum hns3_evt_cause
150 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
153 struct hns3_hw *hw = &hns->hw;
155 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
156 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
157 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
159 hw->reset.stats.global_cnt++;
160 hns3_warn(hw, "Global reset detected, clear reset status");
162 hns3_schedule_delayed_reset(hns);
164 "Global reset detected, don't clear reset status");
167 return HNS3_VECTOR0_EVENT_RST;
170 static enum hns3_evt_cause
171 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
173 struct hns3_hw *hw = &hns->hw;
174 uint32_t vector0_int_stats;
175 uint32_t cmdq_src_val;
176 uint32_t hw_err_src_reg;
178 enum hns3_evt_cause ret;
181 /* fetch the events from their corresponding regs */
182 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
183 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
184 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
186 is_delay = clearval == NULL ? true : false;
188 * Assumption: If by any chance reset and mailbox events are reported
189 * together then we will only process reset event and defer the
190 * processing of the mailbox events. Since, we would have not cleared
191 * RX CMDQ event this time we would receive again another interrupt
192 * from H/W just for the mailbox.
194 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
195 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
200 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
201 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
205 /* Check for vector0 1588 event source */
206 if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
207 val = BIT(HNS3_VECTOR0_1588_INT_B);
208 ret = HNS3_VECTOR0_EVENT_PTP;
212 /* check for vector0 msix event source */
213 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
214 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
215 val = vector0_int_stats | hw_err_src_reg;
216 ret = HNS3_VECTOR0_EVENT_ERR;
220 /* check for vector0 mailbox(=CMDQ RX) event source */
221 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
222 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
224 ret = HNS3_VECTOR0_EVENT_MBX;
228 val = vector0_int_stats;
229 ret = HNS3_VECTOR0_EVENT_OTHER;
238 hns3_is_1588_event_type(uint32_t event_type)
240 return (event_type == HNS3_VECTOR0_EVENT_PTP);
244 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
246 if (event_type == HNS3_VECTOR0_EVENT_RST ||
247 hns3_is_1588_event_type(event_type))
248 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
249 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
250 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
254 hns3_clear_all_event_cause(struct hns3_hw *hw)
256 uint32_t vector0_int_stats;
258 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
259 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
260 hns3_warn(hw, "Probe during IMP reset interrupt");
262 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
263 hns3_warn(hw, "Probe during Global reset interrupt");
265 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
266 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
267 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
268 BIT(HNS3_VECTOR0_CORERESET_INT_B));
269 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
270 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
271 BIT(HNS3_VECTOR0_1588_INT_B));
275 hns3_handle_mac_tnl(struct hns3_hw *hw)
277 struct hns3_cmd_desc desc;
281 /* query and clear mac tnl interrupt */
282 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
283 ret = hns3_cmd_send(hw, &desc, 1);
285 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
289 status = rte_le_to_cpu_32(desc.data[0]);
291 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
292 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
294 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
295 ret = hns3_cmd_send(hw, &desc, 1);
297 hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
303 hns3_interrupt_handler(void *param)
305 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
306 struct hns3_adapter *hns = dev->data->dev_private;
307 struct hns3_hw *hw = &hns->hw;
308 enum hns3_evt_cause event_cause;
309 uint32_t clearval = 0;
310 uint32_t vector0_int;
314 /* Disable interrupt */
315 hns3_pf_disable_irq0(hw);
317 event_cause = hns3_check_event_cause(hns, &clearval);
318 vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
319 ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
320 cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
321 hns3_clear_event_cause(hw, event_cause, clearval);
322 /* vector 0 interrupt is shared with reset and mailbox source events. */
323 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
324 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
325 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
326 vector0_int, ras_int, cmdq_int);
327 hns3_handle_mac_tnl(hw);
328 hns3_handle_error(hns);
329 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
330 hns3_warn(hw, "received reset interrupt");
331 hns3_schedule_reset(hns);
332 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
333 hns3_dev_handle_mbx_msg(hw);
335 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
336 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
337 vector0_int, ras_int, cmdq_int);
340 /* Enable interrupt if it is not cause by reset */
341 hns3_pf_enable_irq0(hw);
345 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
347 #define HNS3_VLAN_ID_OFFSET_STEP 160
348 #define HNS3_VLAN_BYTE_SIZE 8
349 struct hns3_vlan_filter_pf_cfg_cmd *req;
350 struct hns3_hw *hw = &hns->hw;
351 uint8_t vlan_offset_byte_val;
352 struct hns3_cmd_desc desc;
353 uint8_t vlan_offset_byte;
354 uint8_t vlan_offset_base;
357 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
359 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
360 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
362 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
364 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
365 req->vlan_offset = vlan_offset_base;
366 req->vlan_cfg = on ? 0 : 1;
367 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
369 ret = hns3_cmd_send(hw, &desc, 1);
371 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
378 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
380 struct hns3_user_vlan_table *vlan_entry;
381 struct hns3_pf *pf = &hns->pf;
383 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
384 if (vlan_entry->vlan_id == vlan_id) {
385 if (vlan_entry->hd_tbl_status)
386 hns3_set_port_vlan_filter(hns, vlan_id, 0);
387 LIST_REMOVE(vlan_entry, next);
388 rte_free(vlan_entry);
395 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
398 struct hns3_user_vlan_table *vlan_entry;
399 struct hns3_hw *hw = &hns->hw;
400 struct hns3_pf *pf = &hns->pf;
402 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
403 if (vlan_entry->vlan_id == vlan_id)
407 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
408 if (vlan_entry == NULL) {
409 hns3_err(hw, "Failed to malloc hns3 vlan table");
413 vlan_entry->hd_tbl_status = writen_to_tbl;
414 vlan_entry->vlan_id = vlan_id;
416 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
420 hns3_restore_vlan_table(struct hns3_adapter *hns)
422 struct hns3_user_vlan_table *vlan_entry;
423 struct hns3_hw *hw = &hns->hw;
424 struct hns3_pf *pf = &hns->pf;
428 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
429 return hns3_vlan_pvid_configure(hns,
430 hw->port_base_vlan_cfg.pvid, 1);
432 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
433 if (vlan_entry->hd_tbl_status) {
434 vlan_id = vlan_entry->vlan_id;
435 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
445 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
447 struct hns3_hw *hw = &hns->hw;
448 bool writen_to_tbl = false;
452 * When vlan filter is enabled, hardware regards packets without vlan
453 * as packets with vlan 0. So, to receive packets without vlan, vlan id
454 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
456 if (on == 0 && vlan_id == 0)
460 * When port base vlan enabled, we use port base vlan as the vlan
461 * filter condition. In this case, we don't update vlan filter table
462 * when user add new vlan or remove exist vlan, just update the
463 * vlan list. The vlan id in vlan list will be written in vlan filter
464 * table until port base vlan disabled
466 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
467 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
468 writen_to_tbl = true;
473 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
475 hns3_rm_dev_vlan_table(hns, vlan_id);
481 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
483 struct hns3_adapter *hns = dev->data->dev_private;
484 struct hns3_hw *hw = &hns->hw;
487 rte_spinlock_lock(&hw->lock);
488 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
489 rte_spinlock_unlock(&hw->lock);
494 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
497 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
498 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
499 struct hns3_hw *hw = &hns->hw;
500 struct hns3_cmd_desc desc;
503 if ((vlan_type != RTE_ETH_VLAN_TYPE_INNER &&
504 vlan_type != RTE_ETH_VLAN_TYPE_OUTER)) {
505 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
509 if (tpid != RTE_ETHER_TYPE_VLAN) {
510 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
514 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
515 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
517 if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) {
518 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
519 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
520 } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) {
521 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
522 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
523 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
524 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
527 ret = hns3_cmd_send(hw, &desc, 1);
529 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
534 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
536 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
537 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
538 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
540 ret = hns3_cmd_send(hw, &desc, 1);
542 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
548 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
551 struct hns3_adapter *hns = dev->data->dev_private;
552 struct hns3_hw *hw = &hns->hw;
555 rte_spinlock_lock(&hw->lock);
556 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
557 rte_spinlock_unlock(&hw->lock);
562 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
563 struct hns3_rx_vtag_cfg *vcfg)
565 struct hns3_vport_vtag_rx_cfg_cmd *req;
566 struct hns3_hw *hw = &hns->hw;
567 struct hns3_cmd_desc desc;
572 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
574 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
575 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
576 vcfg->strip_tag1_en ? 1 : 0);
577 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
578 vcfg->strip_tag2_en ? 1 : 0);
579 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
580 vcfg->vlan1_vlan_prionly ? 1 : 0);
581 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
582 vcfg->vlan2_vlan_prionly ? 1 : 0);
584 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
585 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
586 vcfg->strip_tag1_discard_en ? 1 : 0);
587 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
588 vcfg->strip_tag2_discard_en ? 1 : 0);
590 * In current version VF is not supported when PF is driven by DPDK
591 * driver, just need to configure parameters for PF vport.
593 vport_id = HNS3_PF_FUNC_ID;
594 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
595 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
596 req->vf_bitmap[req->vf_offset] = bitmap;
598 ret = hns3_cmd_send(hw, &desc, 1);
600 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
605 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
606 struct hns3_rx_vtag_cfg *vcfg)
608 struct hns3_pf *pf = &hns->pf;
609 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
613 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
614 struct hns3_tx_vtag_cfg *vcfg)
616 struct hns3_pf *pf = &hns->pf;
617 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
621 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
623 struct hns3_rx_vtag_cfg rxvlan_cfg;
624 struct hns3_hw *hw = &hns->hw;
627 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
628 rxvlan_cfg.strip_tag1_en = false;
629 rxvlan_cfg.strip_tag2_en = enable;
630 rxvlan_cfg.strip_tag2_discard_en = false;
632 rxvlan_cfg.strip_tag1_en = enable;
633 rxvlan_cfg.strip_tag2_en = true;
634 rxvlan_cfg.strip_tag2_discard_en = true;
637 rxvlan_cfg.strip_tag1_discard_en = false;
638 rxvlan_cfg.vlan1_vlan_prionly = false;
639 rxvlan_cfg.vlan2_vlan_prionly = false;
640 rxvlan_cfg.rx_vlan_offload_en = enable;
642 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
644 hns3_err(hw, "%s strip rx vtag failed, ret = %d.",
645 enable ? "enable" : "disable", ret);
649 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
655 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
656 uint8_t fe_type, bool filter_en, uint8_t vf_id)
658 struct hns3_vlan_filter_ctrl_cmd *req;
659 struct hns3_cmd_desc desc;
662 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
664 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
665 req->vlan_type = vlan_type;
666 req->vlan_fe = filter_en ? fe_type : 0;
669 ret = hns3_cmd_send(hw, &desc, 1);
671 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
677 hns3_vlan_filter_init(struct hns3_adapter *hns)
679 struct hns3_hw *hw = &hns->hw;
682 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
683 HNS3_FILTER_FE_EGRESS, false,
686 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
690 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
691 HNS3_FILTER_FE_INGRESS, false,
694 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
700 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
702 struct hns3_hw *hw = &hns->hw;
705 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
706 HNS3_FILTER_FE_INGRESS, enable,
709 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
710 enable ? "enable" : "disable", ret);
716 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
718 struct hns3_adapter *hns = dev->data->dev_private;
719 struct hns3_hw *hw = &hns->hw;
720 struct rte_eth_rxmode *rxmode;
721 unsigned int tmp_mask;
725 rte_spinlock_lock(&hw->lock);
726 rxmode = &dev->data->dev_conf.rxmode;
727 tmp_mask = (unsigned int)mask;
728 if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
729 /* ignore vlan filter configuration during promiscuous mode */
730 if (!dev->data->promiscuous) {
731 /* Enable or disable VLAN filter */
732 enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ?
735 ret = hns3_enable_vlan_filter(hns, enable);
737 rte_spinlock_unlock(&hw->lock);
738 hns3_err(hw, "failed to %s rx filter, ret = %d",
739 enable ? "enable" : "disable", ret);
745 if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
746 /* Enable or disable VLAN stripping */
747 enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ?
750 ret = hns3_en_hw_strip_rxvtag(hns, enable);
752 rte_spinlock_unlock(&hw->lock);
753 hns3_err(hw, "failed to %s rx strip, ret = %d",
754 enable ? "enable" : "disable", ret);
759 rte_spinlock_unlock(&hw->lock);
765 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
766 struct hns3_tx_vtag_cfg *vcfg)
768 struct hns3_vport_vtag_tx_cfg_cmd *req;
769 struct hns3_cmd_desc desc;
770 struct hns3_hw *hw = &hns->hw;
775 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
777 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
778 req->def_vlan_tag1 = vcfg->default_tag1;
779 req->def_vlan_tag2 = vcfg->default_tag2;
780 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
781 vcfg->accept_tag1 ? 1 : 0);
782 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
783 vcfg->accept_untag1 ? 1 : 0);
784 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
785 vcfg->accept_tag2 ? 1 : 0);
786 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
787 vcfg->accept_untag2 ? 1 : 0);
788 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
789 vcfg->insert_tag1_en ? 1 : 0);
790 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
791 vcfg->insert_tag2_en ? 1 : 0);
792 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
794 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
795 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
796 vcfg->tag_shift_mode_en ? 1 : 0);
799 * In current version VF is not supported when PF is driven by DPDK
800 * driver, just need to configure parameters for PF vport.
802 vport_id = HNS3_PF_FUNC_ID;
803 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
804 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
805 req->vf_bitmap[req->vf_offset] = bitmap;
807 ret = hns3_cmd_send(hw, &desc, 1);
809 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
815 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
818 struct hns3_hw *hw = &hns->hw;
819 struct hns3_tx_vtag_cfg txvlan_cfg;
822 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
823 txvlan_cfg.accept_tag1 = true;
824 txvlan_cfg.insert_tag1_en = false;
825 txvlan_cfg.default_tag1 = 0;
827 txvlan_cfg.accept_tag1 =
828 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
829 txvlan_cfg.insert_tag1_en = true;
830 txvlan_cfg.default_tag1 = pvid;
833 txvlan_cfg.accept_untag1 = true;
834 txvlan_cfg.accept_tag2 = true;
835 txvlan_cfg.accept_untag2 = true;
836 txvlan_cfg.insert_tag2_en = false;
837 txvlan_cfg.default_tag2 = 0;
838 txvlan_cfg.tag_shift_mode_en = true;
840 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
842 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
847 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
853 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
855 struct hns3_user_vlan_table *vlan_entry;
856 struct hns3_pf *pf = &hns->pf;
858 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
859 if (vlan_entry->hd_tbl_status) {
860 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
861 vlan_entry->hd_tbl_status = false;
866 vlan_entry = LIST_FIRST(&pf->vlan_list);
868 LIST_REMOVE(vlan_entry, next);
869 rte_free(vlan_entry);
870 vlan_entry = LIST_FIRST(&pf->vlan_list);
876 hns3_add_all_vlan_table(struct hns3_adapter *hns)
878 struct hns3_user_vlan_table *vlan_entry;
879 struct hns3_pf *pf = &hns->pf;
881 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
882 if (!vlan_entry->hd_tbl_status) {
883 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
884 vlan_entry->hd_tbl_status = true;
890 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
892 struct hns3_hw *hw = &hns->hw;
895 hns3_rm_all_vlan_table(hns, true);
896 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
897 ret = hns3_set_port_vlan_filter(hns,
898 hw->port_base_vlan_cfg.pvid, 0);
900 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
908 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
909 uint16_t port_base_vlan_state, uint16_t new_pvid)
911 struct hns3_hw *hw = &hns->hw;
915 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
916 old_pvid = hw->port_base_vlan_cfg.pvid;
917 if (old_pvid != HNS3_INVALID_PVID) {
918 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
920 hns3_err(hw, "failed to remove old pvid %u, "
921 "ret = %d", old_pvid, ret);
926 hns3_rm_all_vlan_table(hns, false);
927 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
929 hns3_err(hw, "failed to add new pvid %u, ret = %d",
934 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
936 hns3_err(hw, "failed to remove pvid %u, ret = %d",
941 hns3_add_all_vlan_table(hns);
947 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
949 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
950 struct hns3_rx_vtag_cfg rx_vlan_cfg;
954 rx_strip_en = old_cfg->rx_vlan_offload_en;
956 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
957 rx_vlan_cfg.strip_tag2_en = true;
958 rx_vlan_cfg.strip_tag2_discard_en = true;
960 rx_vlan_cfg.strip_tag1_en = false;
961 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
962 rx_vlan_cfg.strip_tag2_discard_en = false;
964 rx_vlan_cfg.strip_tag1_discard_en = false;
965 rx_vlan_cfg.vlan1_vlan_prionly = false;
966 rx_vlan_cfg.vlan2_vlan_prionly = false;
967 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
969 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
973 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
978 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
980 struct hns3_hw *hw = &hns->hw;
981 uint16_t port_base_vlan_state;
984 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
985 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
986 hns3_warn(hw, "Invalid operation! As current pvid set "
987 "is %u, disable pvid %u is invalid",
988 hw->port_base_vlan_cfg.pvid, pvid);
992 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
993 HNS3_PORT_BASE_VLAN_DISABLE;
994 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
996 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
1001 ret = hns3_en_pvid_strip(hns, on);
1003 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1005 goto pvid_vlan_strip_fail;
1008 if (pvid == HNS3_INVALID_PVID)
1010 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1012 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1014 goto vlan_filter_set_fail;
1018 hw->port_base_vlan_cfg.state = port_base_vlan_state;
1019 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1022 vlan_filter_set_fail:
1023 err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1024 HNS3_PORT_BASE_VLAN_ENABLE);
1026 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1028 pvid_vlan_strip_fail:
1029 err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1030 hw->port_base_vlan_cfg.pvid);
1032 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1038 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1040 struct hns3_adapter *hns = dev->data->dev_private;
1041 struct hns3_hw *hw = &hns->hw;
1042 bool pvid_en_state_change;
1043 uint16_t pvid_state;
1046 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1047 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1048 RTE_ETHER_MAX_VLAN_ID);
1053 * If PVID configuration state change, should refresh the PVID
1054 * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1056 pvid_state = hw->port_base_vlan_cfg.state;
1057 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1058 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1059 pvid_en_state_change = false;
1061 pvid_en_state_change = true;
1063 rte_spinlock_lock(&hw->lock);
1064 ret = hns3_vlan_pvid_configure(hns, pvid, on);
1065 rte_spinlock_unlock(&hw->lock);
1069 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1070 * need be processed by PMD driver.
1072 if (pvid_en_state_change &&
1073 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1074 hns3_update_all_queues_pvid_proc_en(hw);
1080 hns3_default_vlan_config(struct hns3_adapter *hns)
1082 struct hns3_hw *hw = &hns->hw;
1086 * When vlan filter is enabled, hardware regards packets without vlan
1087 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1088 * table, packets without vlan won't be received. So, add vlan 0 as
1091 ret = hns3_vlan_filter_configure(hns, 0, 1);
1093 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1098 hns3_init_vlan_config(struct hns3_adapter *hns)
1100 struct hns3_hw *hw = &hns->hw;
1104 * This function can be called in the initialization and reset process,
1105 * when in reset process, it means that hardware had been reseted
1106 * successfully and we need to restore the hardware configuration to
1107 * ensure that the hardware configuration remains unchanged before and
1110 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1111 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1112 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1115 ret = hns3_vlan_filter_init(hns);
1117 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1121 ret = hns3_vlan_tpid_configure(hns, RTE_ETH_VLAN_TYPE_INNER,
1122 RTE_ETHER_TYPE_VLAN);
1124 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1129 * When in the reinit dev stage of the reset process, the following
1130 * vlan-related configurations may differ from those at initialization,
1131 * we will restore configurations to hardware in hns3_restore_vlan_table
1132 * and hns3_restore_vlan_conf later.
1134 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1135 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1137 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1141 ret = hns3_en_hw_strip_rxvtag(hns, false);
1143 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1149 return hns3_default_vlan_config(hns);
1153 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1155 struct hns3_pf *pf = &hns->pf;
1156 struct hns3_hw *hw = &hns->hw;
1161 if (!hw->data->promiscuous) {
1162 /* restore vlan filter states */
1163 offloads = hw->data->dev_conf.rxmode.offloads;
1164 enable = offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ? true : false;
1165 ret = hns3_enable_vlan_filter(hns, enable);
1167 hns3_err(hw, "failed to restore vlan rx filter conf, "
1173 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1175 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1179 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1181 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1187 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1189 struct hns3_adapter *hns = dev->data->dev_private;
1190 struct rte_eth_dev_data *data = dev->data;
1191 struct rte_eth_txmode *txmode;
1192 struct hns3_hw *hw = &hns->hw;
1196 txmode = &data->dev_conf.txmode;
1197 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1199 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1200 "configuration is not supported! Ignore these two "
1201 "parameters: hw_vlan_reject_tagged(%u), "
1202 "hw_vlan_reject_untagged(%u)",
1203 txmode->hw_vlan_reject_tagged,
1204 txmode->hw_vlan_reject_untagged);
1206 /* Apply vlan offload setting */
1207 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK;
1208 ret = hns3_vlan_offload_set(dev, mask);
1210 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1216 * If pvid config is not set in rte_eth_conf, driver needn't to set
1217 * VLAN pvid related configuration to hardware.
1219 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1222 /* Apply pvid setting */
1223 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1224 txmode->hw_vlan_insert_pvid);
1226 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1233 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1234 unsigned int tso_mss_max)
1236 struct hns3_cfg_tso_status_cmd *req;
1237 struct hns3_cmd_desc desc;
1240 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1242 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1245 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1247 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1250 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1252 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1254 return hns3_cmd_send(hw, &desc, 1);
1258 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1259 uint16_t *allocated_size, bool is_alloc)
1261 struct hns3_umv_spc_alc_cmd *req;
1262 struct hns3_cmd_desc desc;
1265 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1266 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1267 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1268 req->space_size = rte_cpu_to_le_32(space_size);
1270 ret = hns3_cmd_send(hw, &desc, 1);
1272 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1273 is_alloc ? "allocate" : "free", ret);
1277 if (is_alloc && allocated_size)
1278 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1284 hns3_init_umv_space(struct hns3_hw *hw)
1286 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1287 struct hns3_pf *pf = &hns->pf;
1288 uint16_t allocated_size = 0;
1291 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1296 if (allocated_size < pf->wanted_umv_size)
1297 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1298 pf->wanted_umv_size, allocated_size);
1300 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1301 pf->wanted_umv_size;
1302 pf->used_umv_size = 0;
1307 hns3_uninit_umv_space(struct hns3_hw *hw)
1309 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1310 struct hns3_pf *pf = &hns->pf;
1313 if (pf->max_umv_size == 0)
1316 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1320 pf->max_umv_size = 0;
1326 hns3_is_umv_space_full(struct hns3_hw *hw)
1328 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1329 struct hns3_pf *pf = &hns->pf;
1332 is_full = (pf->used_umv_size >= pf->max_umv_size);
1338 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1340 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1341 struct hns3_pf *pf = &hns->pf;
1344 if (pf->used_umv_size > 0)
1345 pf->used_umv_size--;
1347 pf->used_umv_size++;
1351 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1352 const uint8_t *addr, bool is_mc)
1354 const unsigned char *mac_addr = addr;
1355 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1356 ((uint32_t)mac_addr[2] << 16) |
1357 ((uint32_t)mac_addr[1] << 8) |
1358 (uint32_t)mac_addr[0];
1359 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1361 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1363 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1364 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1365 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1368 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1369 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1373 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1375 enum hns3_mac_vlan_tbl_opcode op)
1378 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1383 if (op == HNS3_MAC_VLAN_ADD) {
1384 if (resp_code == 0 || resp_code == 1) {
1386 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1387 hns3_err(hw, "add mac addr failed for uc_overflow");
1389 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1390 hns3_err(hw, "add mac addr failed for mc_overflow");
1394 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1397 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1398 if (resp_code == 0) {
1400 } else if (resp_code == 1) {
1401 hns3_dbg(hw, "remove mac addr failed for miss");
1405 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1408 } else if (op == HNS3_MAC_VLAN_LKUP) {
1409 if (resp_code == 0) {
1411 } else if (resp_code == 1) {
1412 hns3_dbg(hw, "lookup mac addr failed for miss");
1416 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1421 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1428 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1429 struct hns3_mac_vlan_tbl_entry_cmd *req,
1430 struct hns3_cmd_desc *desc, uint8_t desc_num)
1437 if (desc_num == HNS3_MC_MAC_VLAN_OPS_DESC_NUM) {
1438 for (i = 0; i < desc_num - 1; i++) {
1439 hns3_cmd_setup_basic_desc(&desc[i],
1440 HNS3_OPC_MAC_VLAN_ADD, true);
1441 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1443 memcpy(desc[i].data, req,
1444 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1446 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_MAC_VLAN_ADD,
1449 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD,
1451 memcpy(desc[0].data, req,
1452 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1454 ret = hns3_cmd_send(hw, desc, desc_num);
1456 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1460 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1461 retval = rte_le_to_cpu_16(desc[0].retval);
1463 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1464 HNS3_MAC_VLAN_LKUP);
1468 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1469 struct hns3_mac_vlan_tbl_entry_cmd *req,
1470 struct hns3_cmd_desc *desc, uint8_t desc_num)
1478 if (desc_num == HNS3_UC_MAC_VLAN_OPS_DESC_NUM) {
1479 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_MAC_VLAN_ADD, false);
1480 memcpy(desc->data, req,
1481 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1482 ret = hns3_cmd_send(hw, desc, desc_num);
1483 resp_code = (rte_le_to_cpu_32(desc->data[0]) >> 8) & 0xff;
1484 retval = rte_le_to_cpu_16(desc->retval);
1486 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1489 for (i = 0; i < desc_num; i++) {
1490 hns3_cmd_reuse_desc(&desc[i], false);
1491 if (i == desc_num - 1)
1493 rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1496 rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1498 memcpy(desc[0].data, req,
1499 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1501 ret = hns3_cmd_send(hw, desc, desc_num);
1502 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1503 retval = rte_le_to_cpu_16(desc[0].retval);
1505 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1510 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1518 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1519 struct hns3_mac_vlan_tbl_entry_cmd *req)
1521 struct hns3_cmd_desc desc;
1526 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1528 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1530 ret = hns3_cmd_send(hw, &desc, 1);
1532 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1535 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1536 retval = rte_le_to_cpu_16(desc.retval);
1538 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1539 HNS3_MAC_VLAN_REMOVE);
1543 hns3_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1545 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1546 struct hns3_mac_vlan_tbl_entry_cmd req;
1547 struct hns3_pf *pf = &hns->pf;
1548 struct hns3_cmd_desc desc;
1549 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1550 uint16_t egress_port = 0;
1554 /* check if mac addr is valid */
1555 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1556 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1558 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1563 memset(&req, 0, sizeof(req));
1566 * In current version VF is not supported when PF is driven by DPDK
1567 * driver, just need to configure parameters for PF vport.
1569 vf_id = HNS3_PF_FUNC_ID;
1570 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1571 HNS3_MAC_EPORT_VFID_S, vf_id);
1573 req.egress_port = rte_cpu_to_le_16(egress_port);
1575 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1578 * Lookup the mac address in the mac_vlan table, and add
1579 * it if the entry is inexistent. Repeated unicast entry
1580 * is not allowed in the mac vlan table.
1582 ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc,
1583 HNS3_UC_MAC_VLAN_OPS_DESC_NUM);
1584 if (ret == -ENOENT) {
1585 if (!hns3_is_umv_space_full(hw)) {
1586 ret = hns3_add_mac_vlan_tbl(hw, &req, &desc,
1587 HNS3_UC_MAC_VLAN_OPS_DESC_NUM);
1589 hns3_update_umv_space(hw, false);
1593 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1598 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1600 /* check if we just hit the duplicate */
1602 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1606 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1613 hns3_find_duplicate_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mc_addr)
1615 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1616 struct rte_ether_addr *addr;
1619 for (i = 0; i < hw->mc_addrs_num; i++) {
1620 addr = &hw->mc_addrs[i];
1621 /* Check if there are duplicate addresses in mc_addrs[] */
1622 if (rte_is_same_ether_addr(addr, mc_addr)) {
1623 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1625 hns3_err(hw, "failed to add mc mac addr, same addrs"
1626 "(%s) is added by the set_mc_mac_addr_list "
1636 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1638 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1641 if (hns3_find_duplicate_mc_addr(hw, mac_addr))
1644 ret = hns3_add_mc_mac_addr(hw, mac_addr);
1646 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1648 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1655 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1657 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1660 ret = hns3_remove_mc_mac_addr(hw, mac_addr);
1662 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1664 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1671 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1672 __rte_unused uint32_t idx, __rte_unused uint32_t pool)
1674 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1675 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1678 rte_spinlock_lock(&hw->lock);
1681 * In hns3 network engine adding UC and MC mac address with different
1682 * commands with firmware. We need to determine whether the input
1683 * address is a UC or a MC address to call different commands.
1684 * By the way, it is recommended calling the API function named
1685 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1686 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1687 * may affect the specifications of UC mac addresses.
1689 if (rte_is_multicast_ether_addr(mac_addr))
1690 ret = hns3_add_mc_addr_common(hw, mac_addr);
1692 ret = hns3_add_uc_mac_addr(hw, mac_addr);
1695 rte_spinlock_unlock(&hw->lock);
1696 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1698 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1703 rte_spinlock_unlock(&hw->lock);
1709 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1711 struct hns3_mac_vlan_tbl_entry_cmd req;
1712 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1715 /* check if mac addr is valid */
1716 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1717 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1719 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1724 memset(&req, 0, sizeof(req));
1725 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1726 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1727 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1728 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1731 hns3_update_umv_space(hw, true);
1737 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1739 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1740 /* index will be checked by upper level rte interface */
1741 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1742 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1745 rte_spinlock_lock(&hw->lock);
1747 if (rte_is_multicast_ether_addr(mac_addr))
1748 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1750 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1751 rte_spinlock_unlock(&hw->lock);
1753 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1755 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1761 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1762 struct rte_ether_addr *mac_addr)
1764 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1765 struct rte_ether_addr *oaddr;
1766 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1769 rte_spinlock_lock(&hw->lock);
1770 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1771 ret = hns3_remove_uc_addr_common(hw, oaddr);
1773 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1775 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1778 rte_spinlock_unlock(&hw->lock);
1782 ret = hns3_add_uc_mac_addr(hw, mac_addr);
1784 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1786 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1787 goto err_add_uc_addr;
1790 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1792 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1793 goto err_pause_addr_cfg;
1796 rte_ether_addr_copy(mac_addr,
1797 (struct rte_ether_addr *)hw->mac.mac_addr);
1798 rte_spinlock_unlock(&hw->lock);
1803 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1805 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1808 "Failed to roll back to del setted mac addr(%s): %d",
1813 ret_val = hns3_add_uc_mac_addr(hw, oaddr);
1815 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, oaddr);
1816 hns3_warn(hw, "Failed to restore old uc mac addr(%s): %d",
1819 rte_spinlock_unlock(&hw->lock);
1825 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1827 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1828 struct hns3_hw *hw = &hns->hw;
1829 struct rte_ether_addr *addr;
1834 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1835 addr = &hw->data->mac_addrs[i];
1836 if (rte_is_zero_ether_addr(addr))
1838 if (rte_is_multicast_ether_addr(addr))
1839 ret = del ? hns3_remove_mc_mac_addr(hw, addr) :
1840 hns3_add_mc_mac_addr(hw, addr);
1842 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1843 hns3_add_uc_mac_addr(hw, addr);
1847 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1849 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1850 "ret = %d.", del ? "remove" : "restore",
1858 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1860 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1864 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1865 word_num = vfid / 32;
1866 bit_num = vfid % 32;
1868 desc[1].data[word_num] &=
1869 rte_cpu_to_le_32(~(1UL << bit_num));
1871 desc[1].data[word_num] |=
1872 rte_cpu_to_le_32(1UL << bit_num);
1874 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1875 bit_num = vfid % 32;
1877 desc[2].data[word_num] &=
1878 rte_cpu_to_le_32(~(1UL << bit_num));
1880 desc[2].data[word_num] |=
1881 rte_cpu_to_le_32(1UL << bit_num);
1886 hns3_add_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1888 struct hns3_cmd_desc desc[HNS3_MC_MAC_VLAN_OPS_DESC_NUM];
1889 struct hns3_mac_vlan_tbl_entry_cmd req;
1890 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1894 /* Check if mac addr is valid */
1895 if (!rte_is_multicast_ether_addr(mac_addr)) {
1896 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1898 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1903 memset(&req, 0, sizeof(req));
1904 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1905 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1906 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc,
1907 HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1909 /* This mac addr do not exist, add new entry for it */
1910 memset(desc[0].data, 0, sizeof(desc[0].data));
1911 memset(desc[1].data, 0, sizeof(desc[0].data));
1912 memset(desc[2].data, 0, sizeof(desc[0].data));
1916 * In current version VF is not supported when PF is driven by DPDK
1917 * driver, just need to configure parameters for PF vport.
1919 vf_id = HNS3_PF_FUNC_ID;
1920 hns3_update_desc_vfid(desc, vf_id, false);
1921 ret = hns3_add_mac_vlan_tbl(hw, &req, desc,
1922 HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1925 hns3_err(hw, "mc mac vlan table is full");
1926 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1928 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1935 hns3_remove_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1937 struct hns3_mac_vlan_tbl_entry_cmd req;
1938 struct hns3_cmd_desc desc[3];
1939 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1943 /* Check if mac addr is valid */
1944 if (!rte_is_multicast_ether_addr(mac_addr)) {
1945 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1947 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1952 memset(&req, 0, sizeof(req));
1953 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1954 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1955 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc,
1956 HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1959 * This mac addr exist, remove this handle's VFID for it.
1960 * In current version VF is not supported when PF is driven by
1961 * DPDK driver, just need to configure parameters for PF vport.
1963 vf_id = HNS3_PF_FUNC_ID;
1964 hns3_update_desc_vfid(desc, vf_id, true);
1966 /* All the vfid is zero, so need to delete this entry */
1967 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1968 } else if (ret == -ENOENT) {
1969 /* This mac addr doesn't exist. */
1974 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1976 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1983 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1984 struct rte_ether_addr *mc_addr_set,
1985 uint32_t nb_mc_addr)
1987 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1988 struct rte_ether_addr *addr;
1992 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1993 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1994 "invalid. valid range: 0~%d",
1995 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1999 /* Check if input mac addresses are valid */
2000 for (i = 0; i < nb_mc_addr; i++) {
2001 addr = &mc_addr_set[i];
2002 if (!rte_is_multicast_ether_addr(addr)) {
2003 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2006 "failed to set mc mac addr, addr(%s) invalid.",
2011 /* Check if there are duplicate addresses */
2012 for (j = i + 1; j < nb_mc_addr; j++) {
2013 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2014 hns3_ether_format_addr(mac_str,
2015 RTE_ETHER_ADDR_FMT_SIZE,
2017 hns3_err(hw, "failed to set mc mac addr, "
2018 "addrs invalid. two same addrs(%s).",
2025 * Check if there are duplicate addresses between mac_addrs
2028 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2029 if (rte_is_same_ether_addr(addr,
2030 &hw->data->mac_addrs[j])) {
2031 hns3_ether_format_addr(mac_str,
2032 RTE_ETHER_ADDR_FMT_SIZE,
2034 hns3_err(hw, "failed to set mc mac addr, "
2035 "addrs invalid. addrs(%s) has already "
2036 "configured in mac_addr add API",
2047 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2048 struct rte_ether_addr *mc_addr_set,
2050 struct rte_ether_addr *reserved_addr_list,
2051 int *reserved_addr_num,
2052 struct rte_ether_addr *add_addr_list,
2054 struct rte_ether_addr *rm_addr_list,
2057 struct rte_ether_addr *addr;
2058 int current_addr_num;
2059 int reserved_num = 0;
2067 /* Calculate the mc mac address list that should be removed */
2068 current_addr_num = hw->mc_addrs_num;
2069 for (i = 0; i < current_addr_num; i++) {
2070 addr = &hw->mc_addrs[i];
2072 for (j = 0; j < mc_addr_num; j++) {
2073 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2080 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2083 rte_ether_addr_copy(addr,
2084 &reserved_addr_list[reserved_num]);
2089 /* Calculate the mc mac address list that should be added */
2090 for (i = 0; i < mc_addr_num; i++) {
2091 addr = &mc_addr_set[i];
2093 for (j = 0; j < current_addr_num; j++) {
2094 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2101 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2106 /* Reorder the mc mac address list maintained by driver */
2107 for (i = 0; i < reserved_num; i++)
2108 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2110 for (i = 0; i < rm_num; i++) {
2111 num = reserved_num + i;
2112 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2115 *reserved_addr_num = reserved_num;
2116 *add_addr_num = add_num;
2117 *rm_addr_num = rm_num;
2121 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2122 struct rte_ether_addr *mc_addr_set,
2123 uint32_t nb_mc_addr)
2125 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2126 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2127 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2128 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2129 struct rte_ether_addr *addr;
2130 int reserved_addr_num;
2138 /* Check if input parameters are valid */
2139 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2143 rte_spinlock_lock(&hw->lock);
2146 * Calculate the mc mac address lists those should be removed and be
2147 * added, Reorder the mc mac address list maintained by driver.
2149 mc_addr_num = (int)nb_mc_addr;
2150 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2151 reserved_addr_list, &reserved_addr_num,
2152 add_addr_list, &add_addr_num,
2153 rm_addr_list, &rm_addr_num);
2155 /* Remove mc mac addresses */
2156 for (i = 0; i < rm_addr_num; i++) {
2157 num = rm_addr_num - i - 1;
2158 addr = &rm_addr_list[num];
2159 ret = hns3_remove_mc_mac_addr(hw, addr);
2161 rte_spinlock_unlock(&hw->lock);
2167 /* Add mc mac addresses */
2168 for (i = 0; i < add_addr_num; i++) {
2169 addr = &add_addr_list[i];
2170 ret = hns3_add_mc_mac_addr(hw, addr);
2172 rte_spinlock_unlock(&hw->lock);
2176 num = reserved_addr_num + i;
2177 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2180 rte_spinlock_unlock(&hw->lock);
2186 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2188 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2189 struct hns3_hw *hw = &hns->hw;
2190 struct rte_ether_addr *addr;
2195 for (i = 0; i < hw->mc_addrs_num; i++) {
2196 addr = &hw->mc_addrs[i];
2197 if (!rte_is_multicast_ether_addr(addr))
2200 ret = hns3_remove_mc_mac_addr(hw, addr);
2202 ret = hns3_add_mc_mac_addr(hw, addr);
2205 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2207 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2208 del ? "Remove" : "Restore", mac_str, ret);
2215 hns3_check_mq_mode(struct rte_eth_dev *dev)
2217 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2218 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2219 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2220 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2221 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2222 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2227 if ((rx_mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) ||
2228 (tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB ||
2229 tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_ONLY)) {
2230 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
2231 rx_mq_mode, tx_mq_mode);
2235 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2236 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2237 if (rx_mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
2238 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2239 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2240 dcb_rx_conf->nb_tcs, pf->tc_max);
2244 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2245 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2246 hns3_err(hw, "on RTE_ETH_MQ_RX_DCB_RSS mode, "
2247 "nb_tcs(%d) != %d or %d in rx direction.",
2248 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2252 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2253 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2254 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2258 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2259 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2260 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2261 "is not equal to one in tx direction.",
2262 i, dcb_rx_conf->dcb_tc[i]);
2265 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2266 max_tc = dcb_rx_conf->dcb_tc[i];
2269 num_tc = max_tc + 1;
2270 if (num_tc > dcb_rx_conf->nb_tcs) {
2271 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2272 num_tc, dcb_rx_conf->nb_tcs);
2281 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2282 enum hns3_ring_type queue_type, uint16_t queue_id)
2284 struct hns3_cmd_desc desc;
2285 struct hns3_ctrl_vector_chain_cmd *req =
2286 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2287 enum hns3_opcode_type op;
2288 uint16_t tqp_type_and_id = 0;
2293 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2294 hns3_cmd_setup_basic_desc(&desc, op, false);
2295 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2296 HNS3_TQP_INT_ID_L_S);
2297 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2298 HNS3_TQP_INT_ID_H_S);
2300 if (queue_type == HNS3_RING_TYPE_RX)
2301 gl = HNS3_RING_GL_RX;
2303 gl = HNS3_RING_GL_TX;
2307 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2309 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2310 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2312 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2313 req->int_cause_num = 1;
2314 ret = hns3_cmd_send(hw, &desc, 1);
2316 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2317 en ? "Map" : "Unmap", queue_id, vector_id, ret);
2325 hns3_init_ring_with_vector(struct hns3_hw *hw)
2332 * In hns3 network engine, vector 0 is always the misc interrupt of this
2333 * function, vector 1~N can be used respectively for the queues of the
2334 * function. Tx and Rx queues with the same number share the interrupt
2335 * vector. In the initialization clearing the all hardware mapping
2336 * relationship configurations between queues and interrupt vectors is
2337 * needed, so some error caused by the residual configurations, such as
2338 * the unexpected Tx interrupt, can be avoid.
2340 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2341 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2342 vec = vec - 1; /* the last interrupt is reserved */
2343 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2344 for (i = 0; i < hw->intr_tqps_num; i++) {
2346 * Set gap limiter/rate limiter/quanity limiter algorithm
2347 * configuration for interrupt coalesce of queue's interrupt.
2349 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2350 HNS3_TQP_INTR_GL_DEFAULT);
2351 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2352 HNS3_TQP_INTR_GL_DEFAULT);
2353 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2355 * QL(quantity limiter) is not used currently, just set 0 to
2358 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2360 ret = hns3_bind_ring_with_vector(hw, vec, false,
2361 HNS3_RING_TYPE_TX, i);
2363 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2364 "vector: %u, ret=%d", i, vec, ret);
2368 ret = hns3_bind_ring_with_vector(hw, vec, false,
2369 HNS3_RING_TYPE_RX, i);
2371 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2372 "vector: %u, ret=%d", i, vec, ret);
2381 hns3_setup_dcb(struct rte_eth_dev *dev)
2383 struct hns3_adapter *hns = dev->data->dev_private;
2384 struct hns3_hw *hw = &hns->hw;
2387 if (!hns3_dev_get_support(hw, DCB)) {
2388 hns3_err(hw, "this port does not support dcb configurations.");
2392 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2393 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2397 ret = hns3_dcb_configure(hns);
2399 hns3_err(hw, "failed to config dcb: %d", ret);
2405 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
2410 * Some hardware doesn't support auto-negotiation, but users may not
2411 * configure link_speeds (default 0), which means auto-negotiation.
2412 * In this case, it should return success.
2414 if (link_speeds == RTE_ETH_LINK_SPEED_AUTONEG &&
2415 hw->mac.support_autoneg == 0)
2418 if (link_speeds != RTE_ETH_LINK_SPEED_AUTONEG) {
2419 ret = hns3_check_port_speed(hw, link_speeds);
2428 hns3_check_dev_conf(struct rte_eth_dev *dev)
2430 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2431 struct rte_eth_conf *conf = &dev->data->dev_conf;
2434 ret = hns3_check_mq_mode(dev);
2438 return hns3_check_link_speed(hw, conf->link_speeds);
2442 hns3_dev_configure(struct rte_eth_dev *dev)
2444 struct hns3_adapter *hns = dev->data->dev_private;
2445 struct rte_eth_conf *conf = &dev->data->dev_conf;
2446 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2447 struct hns3_hw *hw = &hns->hw;
2448 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2449 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2450 struct rte_eth_rss_conf rss_conf;
2454 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2457 * Some versions of hardware network engine does not support
2458 * individually enable/disable/reset the Tx or Rx queue. These devices
2459 * must enable/disable/reset Tx and Rx queues at the same time. When the
2460 * numbers of Tx queues allocated by upper applications are not equal to
2461 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2462 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2463 * work as usual. But these fake queues are imperceptible, and can not
2464 * be used by upper applications.
2466 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2468 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
2469 hw->cfg_max_queues = 0;
2473 hw->adapter_state = HNS3_NIC_CONFIGURING;
2474 ret = hns3_check_dev_conf(dev);
2478 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
2479 ret = hns3_setup_dcb(dev);
2484 /* When RSS is not configured, redirect the packet queue 0 */
2485 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
2486 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2487 rss_conf = conf->rx_adv_conf.rss_conf;
2488 hw->rss_dis_flag = false;
2489 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2494 ret = hns3_dev_mtu_set(dev, conf->rxmode.mtu);
2498 ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2502 ret = hns3_dev_configure_vlan(dev);
2506 /* config hardware GRO */
2507 gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
2508 ret = hns3_config_gro(hw, gro_en);
2512 hns3_init_rx_ptype_tble(dev);
2513 hw->adapter_state = HNS3_NIC_CONFIGURED;
2518 hw->cfg_max_queues = 0;
2519 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2520 hw->adapter_state = HNS3_NIC_INITIALIZED;
2526 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2528 struct hns3_config_max_frm_size_cmd *req;
2529 struct hns3_cmd_desc desc;
2531 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2533 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2534 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2535 req->min_frm_size = RTE_ETHER_MIN_LEN;
2537 return hns3_cmd_send(hw, &desc, 1);
2541 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2543 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2544 uint16_t original_mps = hns->pf.mps;
2548 ret = hns3_set_mac_mtu(hw, mps);
2550 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2555 ret = hns3_buffer_alloc(hw);
2557 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2564 err = hns3_set_mac_mtu(hw, original_mps);
2566 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2569 hns->pf.mps = original_mps;
2575 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2577 struct hns3_adapter *hns = dev->data->dev_private;
2578 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2579 struct hns3_hw *hw = &hns->hw;
2582 if (dev->data->dev_started) {
2583 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2584 "before configuration", dev->data->port_id);
2588 rte_spinlock_lock(&hw->lock);
2589 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2592 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2593 * assign to "uint16_t" type variable.
2595 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2597 rte_spinlock_unlock(&hw->lock);
2598 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2599 dev->data->port_id, mtu, ret);
2603 rte_spinlock_unlock(&hw->lock);
2609 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2611 uint32_t speed_capa = 0;
2613 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2614 speed_capa |= RTE_ETH_LINK_SPEED_10M_HD;
2615 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2616 speed_capa |= RTE_ETH_LINK_SPEED_10M;
2617 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2618 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD;
2619 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2620 speed_capa |= RTE_ETH_LINK_SPEED_100M;
2621 if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2622 speed_capa |= RTE_ETH_LINK_SPEED_1G;
2628 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2630 uint32_t speed_capa = 0;
2632 if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2633 speed_capa |= RTE_ETH_LINK_SPEED_1G;
2634 if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2635 speed_capa |= RTE_ETH_LINK_SPEED_10G;
2636 if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2637 speed_capa |= RTE_ETH_LINK_SPEED_25G;
2638 if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2639 speed_capa |= RTE_ETH_LINK_SPEED_40G;
2640 if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2641 speed_capa |= RTE_ETH_LINK_SPEED_50G;
2642 if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2643 speed_capa |= RTE_ETH_LINK_SPEED_100G;
2644 if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2645 speed_capa |= RTE_ETH_LINK_SPEED_200G;
2651 hns3_get_speed_capa(struct hns3_hw *hw)
2653 struct hns3_mac *mac = &hw->mac;
2654 uint32_t speed_capa;
2656 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2658 hns3_get_copper_port_speed_capa(mac->supported_speed);
2661 hns3_get_firber_port_speed_capa(mac->supported_speed);
2663 if (mac->support_autoneg == 0)
2664 speed_capa |= RTE_ETH_LINK_SPEED_FIXED;
2670 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2672 struct hns3_adapter *hns = eth_dev->data->dev_private;
2673 struct hns3_hw *hw = &hns->hw;
2674 uint16_t queue_num = hw->tqps_num;
2677 * In interrupt mode, 'max_rx_queues' is set based on the number of
2678 * MSI-X interrupt resources of the hardware.
2680 if (hw->data->dev_conf.intr_conf.rxq == 1)
2681 queue_num = hw->intr_tqps_num;
2683 info->max_rx_queues = queue_num;
2684 info->max_tx_queues = hw->tqps_num;
2685 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2686 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2687 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2688 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2689 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2690 info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
2691 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
2692 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
2693 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
2694 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2695 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
2696 RTE_ETH_RX_OFFLOAD_KEEP_CRC |
2697 RTE_ETH_RX_OFFLOAD_SCATTER |
2698 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
2699 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
2700 RTE_ETH_RX_OFFLOAD_RSS_HASH |
2701 RTE_ETH_RX_OFFLOAD_TCP_LRO);
2702 info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2703 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
2704 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
2705 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
2706 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
2707 RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
2708 RTE_ETH_TX_OFFLOAD_TCP_TSO |
2709 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
2710 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
2711 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
2712 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
2713 hns3_txvlan_cap_get(hw));
2715 if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
2716 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
2718 if (hns3_dev_get_support(hw, INDEP_TXRX))
2719 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2720 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2722 if (hns3_dev_get_support(hw, PTP))
2723 info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP;
2725 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2726 .nb_max = HNS3_MAX_RING_DESC,
2727 .nb_min = HNS3_MIN_RING_DESC,
2728 .nb_align = HNS3_ALIGN_RING_DESC,
2731 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2732 .nb_max = HNS3_MAX_RING_DESC,
2733 .nb_min = HNS3_MIN_RING_DESC,
2734 .nb_align = HNS3_ALIGN_RING_DESC,
2735 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2736 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2739 info->speed_capa = hns3_get_speed_capa(hw);
2740 info->default_rxconf = (struct rte_eth_rxconf) {
2741 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2743 * If there are no available Rx buffer descriptors, incoming
2744 * packets are always dropped by hardware based on hns3 network
2750 info->default_txconf = (struct rte_eth_txconf) {
2751 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2755 info->reta_size = hw->rss_ind_tbl_size;
2756 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2757 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2759 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2760 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2761 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2762 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2763 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2764 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2770 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2773 struct hns3_adapter *hns = eth_dev->data->dev_private;
2774 struct hns3_hw *hw = &hns->hw;
2775 uint32_t version = hw->fw_version;
2778 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2779 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2780 HNS3_FW_VERSION_BYTE3_S),
2781 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2782 HNS3_FW_VERSION_BYTE2_S),
2783 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2784 HNS3_FW_VERSION_BYTE1_S),
2785 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2786 HNS3_FW_VERSION_BYTE0_S));
2790 ret += 1; /* add the size of '\0' */
2791 if (fw_size < (size_t)ret)
2798 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2800 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2803 (void)hns3_update_link_status(hw);
2805 ret = hns3_update_link_info(eth_dev);
2807 hw->mac.link_status = RTE_ETH_LINK_DOWN;
2813 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2814 struct rte_eth_link *new_link)
2816 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2817 struct hns3_mac *mac = &hw->mac;
2819 switch (mac->link_speed) {
2820 case RTE_ETH_SPEED_NUM_10M:
2821 case RTE_ETH_SPEED_NUM_100M:
2822 case RTE_ETH_SPEED_NUM_1G:
2823 case RTE_ETH_SPEED_NUM_10G:
2824 case RTE_ETH_SPEED_NUM_25G:
2825 case RTE_ETH_SPEED_NUM_40G:
2826 case RTE_ETH_SPEED_NUM_50G:
2827 case RTE_ETH_SPEED_NUM_100G:
2828 case RTE_ETH_SPEED_NUM_200G:
2829 if (mac->link_status)
2830 new_link->link_speed = mac->link_speed;
2833 if (mac->link_status)
2834 new_link->link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2838 if (!mac->link_status)
2839 new_link->link_speed = RTE_ETH_SPEED_NUM_NONE;
2841 new_link->link_duplex = mac->link_duplex;
2842 new_link->link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2843 new_link->link_autoneg = mac->link_autoneg;
2847 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2849 #define HNS3_LINK_CHECK_INTERVAL 100 /* 100ms */
2850 #define HNS3_MAX_LINK_CHECK_TIMES 20 /* 2s (100 * 20ms) in total */
2852 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2853 uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2854 struct hns3_mac *mac = &hw->mac;
2855 struct rte_eth_link new_link;
2858 /* When port is stopped, report link down. */
2859 if (eth_dev->data->dev_started == 0) {
2860 new_link.link_autoneg = mac->link_autoneg;
2861 new_link.link_duplex = mac->link_duplex;
2862 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2863 new_link.link_status = RTE_ETH_LINK_DOWN;
2868 ret = hns3_update_port_link_info(eth_dev);
2870 hns3_err(hw, "failed to get port link info, ret = %d.",
2875 if (!wait_to_complete || mac->link_status == RTE_ETH_LINK_UP)
2878 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2879 } while (retry_cnt--);
2881 memset(&new_link, 0, sizeof(new_link));
2882 hns3_setup_linkstatus(eth_dev, &new_link);
2885 return rte_eth_linkstatus_set(eth_dev, &new_link);
2889 hns3_dev_set_link_up(struct rte_eth_dev *dev)
2891 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2895 * The "tx_pkt_burst" will be restored. But the secondary process does
2896 * not support the mechanism for notifying the primary process.
2898 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2899 hns3_err(hw, "secondary process does not support to set link up.");
2904 * If device isn't started Rx/Tx function is still disabled, setting
2905 * link up is not allowed. But it is probably better to return success
2906 * to reduce the impact on the upper layer.
2908 if (hw->adapter_state != HNS3_NIC_STARTED) {
2909 hns3_info(hw, "device isn't started, can't set link up.");
2913 if (!hw->set_link_down)
2916 rte_spinlock_lock(&hw->lock);
2917 ret = hns3_cfg_mac_mode(hw, true);
2919 rte_spinlock_unlock(&hw->lock);
2920 hns3_err(hw, "failed to set link up, ret = %d", ret);
2924 hw->set_link_down = false;
2925 hns3_start_tx_datapath(dev);
2926 rte_spinlock_unlock(&hw->lock);
2932 hns3_dev_set_link_down(struct rte_eth_dev *dev)
2934 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2938 * The "tx_pkt_burst" will be set to dummy function. But the secondary
2939 * process does not support the mechanism for notifying the primary
2942 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2943 hns3_err(hw, "secondary process does not support to set link down.");
2948 * If device isn't started or the API has been called, link status is
2949 * down, return success.
2951 if (hw->adapter_state != HNS3_NIC_STARTED || hw->set_link_down)
2954 rte_spinlock_lock(&hw->lock);
2955 hns3_stop_tx_datapath(dev);
2956 ret = hns3_cfg_mac_mode(hw, false);
2958 hns3_start_tx_datapath(dev);
2959 rte_spinlock_unlock(&hw->lock);
2960 hns3_err(hw, "failed to set link down, ret = %d", ret);
2964 hw->set_link_down = true;
2965 rte_spinlock_unlock(&hw->lock);
2971 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2973 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2974 struct hns3_pf *pf = &hns->pf;
2976 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2979 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2985 hns3_query_function_status(struct hns3_hw *hw)
2987 #define HNS3_QUERY_MAX_CNT 10
2988 #define HNS3_QUERY_SLEEP_MSCOEND 1
2989 struct hns3_func_status_cmd *req;
2990 struct hns3_cmd_desc desc;
2994 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2995 req = (struct hns3_func_status_cmd *)desc.data;
2998 ret = hns3_cmd_send(hw, &desc, 1);
3000 PMD_INIT_LOG(ERR, "query function status failed %d",
3005 /* Check pf reset is done */
3009 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
3010 } while (timeout++ < HNS3_QUERY_MAX_CNT);
3012 return hns3_parse_func_status(hw, req);
3016 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
3018 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3019 struct hns3_pf *pf = &hns->pf;
3021 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
3023 * The total_tqps_num obtained from firmware is maximum tqp
3024 * numbers of this port, which should be used for PF and VFs.
3025 * There is no need for pf to have so many tqp numbers in
3026 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
3027 * coming from config file, is assigned to maximum queue number
3028 * for the PF of this port by user. So users can modify the
3029 * maximum queue number of PF according to their own application
3030 * scenarios, which is more flexible to use. In addition, many
3031 * memories can be saved due to allocating queue statistics
3032 * room according to the actual number of queues required. The
3033 * maximum queue number of PF for network engine with
3034 * revision_id greater than 0x30 is assigned by config file.
3036 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
3037 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
3038 "must be greater than 0.",
3039 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
3043 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
3044 hw->total_tqps_num);
3047 * Due to the limitation on the number of PF interrupts
3048 * available, the maximum queue number assigned to PF on
3049 * the network engine with revision_id 0x21 is 64.
3051 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
3052 HNS3_MAX_TQP_NUM_HIP08_PF);
3059 hns3_query_pf_resource(struct hns3_hw *hw)
3061 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3062 struct hns3_pf *pf = &hns->pf;
3063 struct hns3_pf_res_cmd *req;
3064 struct hns3_cmd_desc desc;
3067 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
3068 ret = hns3_cmd_send(hw, &desc, 1);
3070 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
3074 req = (struct hns3_pf_res_cmd *)desc.data;
3075 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
3076 rte_le_to_cpu_16(req->ext_tqp_num);
3077 ret = hns3_get_pf_max_tqp_num(hw);
3081 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
3082 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
3084 if (req->tx_buf_size)
3086 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
3088 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
3090 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
3092 if (req->dv_buf_size)
3094 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3096 pf->dv_buf_size = HNS3_DEFAULT_DV;
3098 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3101 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3102 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3108 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3110 struct hns3_cfg_param_cmd *req;
3111 uint64_t mac_addr_tmp_high;
3112 uint8_t ext_rss_size_max;
3113 uint64_t mac_addr_tmp;
3116 req = (struct hns3_cfg_param_cmd *)desc[0].data;
3118 /* get the configuration */
3119 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3120 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3121 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3122 HNS3_CFG_TQP_DESC_N_M,
3123 HNS3_CFG_TQP_DESC_N_S);
3125 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3126 HNS3_CFG_PHY_ADDR_M,
3127 HNS3_CFG_PHY_ADDR_S);
3128 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3129 HNS3_CFG_MEDIA_TP_M,
3130 HNS3_CFG_MEDIA_TP_S);
3131 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3132 HNS3_CFG_RX_BUF_LEN_M,
3133 HNS3_CFG_RX_BUF_LEN_S);
3134 /* get mac address */
3135 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3136 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3137 HNS3_CFG_MAC_ADDR_H_M,
3138 HNS3_CFG_MAC_ADDR_H_S);
3140 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3142 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3143 HNS3_CFG_DEFAULT_SPEED_M,
3144 HNS3_CFG_DEFAULT_SPEED_S);
3145 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3146 HNS3_CFG_RSS_SIZE_M,
3147 HNS3_CFG_RSS_SIZE_S);
3149 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3150 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3152 req = (struct hns3_cfg_param_cmd *)desc[1].data;
3153 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3155 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3156 HNS3_CFG_SPEED_ABILITY_M,
3157 HNS3_CFG_SPEED_ABILITY_S);
3158 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3159 HNS3_CFG_UMV_TBL_SPACE_M,
3160 HNS3_CFG_UMV_TBL_SPACE_S);
3161 if (!cfg->umv_space)
3162 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3164 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3165 HNS3_CFG_EXT_RSS_SIZE_M,
3166 HNS3_CFG_EXT_RSS_SIZE_S);
3168 * Field ext_rss_size_max obtained from firmware will be more flexible
3169 * for future changes and expansions, which is an exponent of 2, instead
3170 * of reading out directly. If this field is not zero, hns3 PF PMD
3171 * driver uses it as rss_size_max under one TC. Device, whose revision
3172 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3173 * maximum number of queues supported under a TC through this field.
3175 if (ext_rss_size_max)
3176 cfg->rss_size_max = 1U << ext_rss_size_max;
3179 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3180 * @hw: pointer to struct hns3_hw
3181 * @hcfg: the config structure to be getted
3184 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3186 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3187 struct hns3_cfg_param_cmd *req;
3192 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3194 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3195 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3197 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3198 i * HNS3_CFG_RD_LEN_BYTES);
3199 /* Len should be divided by 4 when send to hardware */
3200 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3201 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3202 req->offset = rte_cpu_to_le_32(offset);
3205 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3207 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3211 hns3_parse_cfg(hcfg, desc);
3217 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3219 switch (speed_cmd) {
3220 case HNS3_CFG_SPEED_10M:
3221 *speed = RTE_ETH_SPEED_NUM_10M;
3223 case HNS3_CFG_SPEED_100M:
3224 *speed = RTE_ETH_SPEED_NUM_100M;
3226 case HNS3_CFG_SPEED_1G:
3227 *speed = RTE_ETH_SPEED_NUM_1G;
3229 case HNS3_CFG_SPEED_10G:
3230 *speed = RTE_ETH_SPEED_NUM_10G;
3232 case HNS3_CFG_SPEED_25G:
3233 *speed = RTE_ETH_SPEED_NUM_25G;
3235 case HNS3_CFG_SPEED_40G:
3236 *speed = RTE_ETH_SPEED_NUM_40G;
3238 case HNS3_CFG_SPEED_50G:
3239 *speed = RTE_ETH_SPEED_NUM_50G;
3241 case HNS3_CFG_SPEED_100G:
3242 *speed = RTE_ETH_SPEED_NUM_100G;
3244 case HNS3_CFG_SPEED_200G:
3245 *speed = RTE_ETH_SPEED_NUM_200G;
3255 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3257 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3258 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3259 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3260 hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3261 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3265 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3267 struct hns3_dev_specs_0_cmd *req0;
3269 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3271 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3272 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3273 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3274 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3275 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3279 hns3_check_dev_specifications(struct hns3_hw *hw)
3281 if (hw->rss_ind_tbl_size == 0 ||
3282 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3283 hns3_err(hw, "the size of hash lookup table configured (%u)"
3284 " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3285 HNS3_RSS_IND_TBL_SIZE_MAX);
3293 hns3_query_dev_specifications(struct hns3_hw *hw)
3295 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3299 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3300 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3302 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3304 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3306 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3310 hns3_parse_dev_specifications(hw, desc);
3312 return hns3_check_dev_specifications(hw);
3316 hns3_get_capability(struct hns3_hw *hw)
3318 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3319 struct rte_pci_device *pci_dev;
3320 struct hns3_pf *pf = &hns->pf;
3321 struct rte_eth_dev *eth_dev;
3326 eth_dev = &rte_eth_devices[hw->data->port_id];
3327 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3328 device_id = pci_dev->id.device_id;
3330 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3331 device_id == HNS3_DEV_ID_50GE_RDMA ||
3332 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3333 device_id == HNS3_DEV_ID_200G_RDMA)
3334 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3336 /* Get PCI revision id */
3337 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3338 HNS3_PCI_REVISION_ID);
3339 if (ret != HNS3_PCI_REVISION_ID_LEN) {
3340 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3344 hw->revision = revision;
3346 if (revision < PCI_REVISION_ID_HIP09_A) {
3347 hns3_set_default_dev_specifications(hw);
3348 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3349 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3350 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3351 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3352 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3353 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3354 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3355 hw->rss_info.ipv6_sctp_offload_supported = false;
3356 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3357 pf->support_multi_tc_pause = false;
3361 ret = hns3_query_dev_specifications(hw);
3364 "failed to query dev specifications, ret = %d",
3369 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3370 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3371 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3372 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3373 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3374 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3375 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3376 hw->rss_info.ipv6_sctp_offload_supported = true;
3377 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3378 pf->support_multi_tc_pause = true;
3384 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3388 switch (media_type) {
3389 case HNS3_MEDIA_TYPE_COPPER:
3390 if (!hns3_dev_get_support(hw, COPPER)) {
3392 "Media type is copper, not supported.");
3398 case HNS3_MEDIA_TYPE_FIBER:
3401 case HNS3_MEDIA_TYPE_BACKPLANE:
3402 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3406 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3415 hns3_get_board_configuration(struct hns3_hw *hw)
3417 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3418 struct hns3_pf *pf = &hns->pf;
3419 struct hns3_cfg cfg;
3422 ret = hns3_get_board_cfg(hw, &cfg);
3424 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3428 ret = hns3_check_media_type(hw, cfg.media_type);
3432 hw->mac.media_type = cfg.media_type;
3433 hw->rss_size_max = cfg.rss_size_max;
3434 hw->rss_dis_flag = false;
3435 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3436 hw->mac.phy_addr = cfg.phy_addr;
3437 hw->num_tx_desc = cfg.tqp_desc_num;
3438 hw->num_rx_desc = cfg.tqp_desc_num;
3439 hw->dcb_info.num_pg = 1;
3440 hw->dcb_info.hw_pfc_map = 0;
3442 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3444 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3445 cfg.default_speed, ret);
3449 pf->tc_max = cfg.tc_num;
3450 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3451 PMD_INIT_LOG(WARNING,
3452 "Get TC num(%u) from flash, set TC num to 1",
3457 /* Dev does not support DCB */
3458 if (!hns3_dev_get_support(hw, DCB)) {
3462 pf->pfc_max = pf->tc_max;
3464 hw->dcb_info.num_tc = 1;
3465 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3466 hw->tqps_num / hw->dcb_info.num_tc);
3467 hns3_set_bit(hw->hw_tc_map, 0, 1);
3468 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3470 pf->wanted_umv_size = cfg.umv_space;
3476 hns3_get_configuration(struct hns3_hw *hw)
3480 ret = hns3_query_function_status(hw);
3482 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3486 /* Get device capability */
3487 ret = hns3_get_capability(hw);
3489 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3493 /* Get pf resource */
3494 ret = hns3_query_pf_resource(hw);
3496 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3500 ret = hns3_get_board_configuration(hw);
3502 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3506 ret = hns3_query_dev_fec_info(hw);
3509 "failed to query FEC information, ret = %d", ret);
3515 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3516 uint16_t tqp_vid, bool is_pf)
3518 struct hns3_tqp_map_cmd *req;
3519 struct hns3_cmd_desc desc;
3522 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3524 req = (struct hns3_tqp_map_cmd *)desc.data;
3525 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3526 req->tqp_vf = func_id;
3527 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3529 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3530 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3532 ret = hns3_cmd_send(hw, &desc, 1);
3534 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3540 hns3_map_tqp(struct hns3_hw *hw)
3546 * In current version, VF is not supported when PF is driven by DPDK
3547 * driver, so we assign total tqps_num tqps allocated to this port
3550 for (i = 0; i < hw->total_tqps_num; i++) {
3551 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3560 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3562 struct hns3_config_mac_speed_dup_cmd *req;
3563 struct hns3_cmd_desc desc;
3566 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3568 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3570 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3573 case RTE_ETH_SPEED_NUM_10M:
3574 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3575 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3577 case RTE_ETH_SPEED_NUM_100M:
3578 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3579 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3581 case RTE_ETH_SPEED_NUM_1G:
3582 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3583 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3585 case RTE_ETH_SPEED_NUM_10G:
3586 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3587 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3589 case RTE_ETH_SPEED_NUM_25G:
3590 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3591 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3593 case RTE_ETH_SPEED_NUM_40G:
3594 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3595 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3597 case RTE_ETH_SPEED_NUM_50G:
3598 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3599 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3601 case RTE_ETH_SPEED_NUM_100G:
3602 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3603 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3605 case RTE_ETH_SPEED_NUM_200G:
3606 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3607 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3610 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3614 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3616 ret = hns3_cmd_send(hw, &desc, 1);
3618 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3624 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3626 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3627 struct hns3_pf *pf = &hns->pf;
3628 struct hns3_priv_buf *priv;
3629 uint32_t i, total_size;
3631 total_size = pf->pkt_buf_size;
3633 /* alloc tx buffer for all enabled tc */
3634 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3635 priv = &buf_alloc->priv_buf[i];
3637 if (hw->hw_tc_map & BIT(i)) {
3638 if (total_size < pf->tx_buf_size)
3641 priv->tx_buf_size = pf->tx_buf_size;
3643 priv->tx_buf_size = 0;
3645 total_size -= priv->tx_buf_size;
3652 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3654 /* TX buffer size is unit by 128 byte */
3655 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3656 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3657 struct hns3_tx_buff_alloc_cmd *req;
3658 struct hns3_cmd_desc desc;
3663 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3665 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3666 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3667 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3669 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3670 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3671 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3674 ret = hns3_cmd_send(hw, &desc, 1);
3676 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3682 hns3_get_tc_num(struct hns3_hw *hw)
3687 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3688 if (hw->hw_tc_map & BIT(i))
3694 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3696 struct hns3_priv_buf *priv;
3697 uint32_t rx_priv = 0;
3700 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3701 priv = &buf_alloc->priv_buf[i];
3703 rx_priv += priv->buf_size;
3709 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3711 uint32_t total_tx_size = 0;
3714 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3715 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3717 return total_tx_size;
3720 /* Get the number of pfc enabled TCs, which have private buffer */
3722 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3724 struct hns3_priv_buf *priv;
3728 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3729 priv = &buf_alloc->priv_buf[i];
3730 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3737 /* Get the number of pfc disabled TCs, which have private buffer */
3739 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3740 struct hns3_pkt_buf_alloc *buf_alloc)
3742 struct hns3_priv_buf *priv;
3746 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3747 priv = &buf_alloc->priv_buf[i];
3748 if (hw->hw_tc_map & BIT(i) &&
3749 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3757 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3760 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3761 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3762 struct hns3_pf *pf = &hns->pf;
3763 uint32_t shared_buf, aligned_mps;
3768 tc_num = hns3_get_tc_num(hw);
3769 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3771 if (hns3_dev_get_support(hw, DCB))
3772 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3775 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3778 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3779 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3780 HNS3_BUF_SIZE_UNIT);
3782 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3783 if (rx_all < rx_priv + shared_std)
3786 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3787 buf_alloc->s_buf.buf_size = shared_buf;
3788 if (hns3_dev_get_support(hw, DCB)) {
3789 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3790 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3791 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3792 HNS3_BUF_SIZE_UNIT);
3794 buf_alloc->s_buf.self.high =
3795 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3796 buf_alloc->s_buf.self.low = aligned_mps;
3799 if (hns3_dev_get_support(hw, DCB)) {
3800 hi_thrd = shared_buf - pf->dv_buf_size;
3802 if (tc_num <= NEED_RESERVE_TC_NUM)
3803 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3807 hi_thrd = hi_thrd / tc_num;
3809 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3810 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3811 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3813 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3814 lo_thrd = aligned_mps;
3817 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3818 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3819 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3826 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3827 struct hns3_pkt_buf_alloc *buf_alloc)
3829 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3830 struct hns3_pf *pf = &hns->pf;
3831 struct hns3_priv_buf *priv;
3832 uint32_t aligned_mps;
3836 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3837 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3839 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3840 priv = &buf_alloc->priv_buf[i];
3847 if (!(hw->hw_tc_map & BIT(i)))
3851 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3852 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3853 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3854 HNS3_BUF_SIZE_UNIT);
3857 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3861 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3864 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3868 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3869 struct hns3_pkt_buf_alloc *buf_alloc)
3871 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3872 struct hns3_pf *pf = &hns->pf;
3873 struct hns3_priv_buf *priv;
3874 int no_pfc_priv_num;
3879 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3880 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3882 /* let the last to be cleared first */
3883 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3884 priv = &buf_alloc->priv_buf[i];
3885 mask = BIT((uint8_t)i);
3886 if (hw->hw_tc_map & mask &&
3887 !(hw->dcb_info.hw_pfc_map & mask)) {
3888 /* Clear the no pfc TC private buffer */
3896 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3897 no_pfc_priv_num == 0)
3901 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3905 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3906 struct hns3_pkt_buf_alloc *buf_alloc)
3908 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3909 struct hns3_pf *pf = &hns->pf;
3910 struct hns3_priv_buf *priv;
3916 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3917 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3919 /* let the last to be cleared first */
3920 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3921 priv = &buf_alloc->priv_buf[i];
3922 mask = BIT((uint8_t)i);
3923 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3924 /* Reduce the number of pfc TC with private buffer */
3931 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3936 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3940 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3941 struct hns3_pkt_buf_alloc *buf_alloc)
3943 #define COMPENSATE_BUFFER 0x3C00
3944 #define COMPENSATE_HALF_MPS_NUM 5
3945 #define PRIV_WL_GAP 0x1800
3946 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3947 struct hns3_pf *pf = &hns->pf;
3948 uint32_t tc_num = hns3_get_tc_num(hw);
3949 uint32_t half_mps = pf->mps >> 1;
3950 struct hns3_priv_buf *priv;
3951 uint32_t min_rx_priv;
3955 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3957 rx_priv = rx_priv / tc_num;
3959 if (tc_num <= NEED_RESERVE_TC_NUM)
3960 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3963 * Minimum value of private buffer in rx direction (min_rx_priv) is
3964 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3965 * buffer if rx_priv is greater than min_rx_priv.
3967 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3968 COMPENSATE_HALF_MPS_NUM * half_mps;
3969 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3970 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3971 if (rx_priv < min_rx_priv)
3974 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3975 priv = &buf_alloc->priv_buf[i];
3981 if (!(hw->hw_tc_map & BIT(i)))
3985 priv->buf_size = rx_priv;
3986 priv->wl.high = rx_priv - pf->dv_buf_size;
3987 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3990 buf_alloc->s_buf.buf_size = 0;
3996 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3997 * @hw: pointer to struct hns3_hw
3998 * @buf_alloc: pointer to buffer calculation data
3999 * @return: 0: calculate sucessful, negative: fail
4002 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4004 /* When DCB is not supported, rx private buffer is not allocated. */
4005 if (!hns3_dev_get_support(hw, DCB)) {
4006 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4007 struct hns3_pf *pf = &hns->pf;
4008 uint32_t rx_all = pf->pkt_buf_size;
4010 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
4011 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
4018 * Try to allocate privated packet buffer for all TCs without share
4021 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
4025 * Try to allocate privated packet buffer for all TCs with share
4028 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
4032 * For different application scenes, the enabled port number, TC number
4033 * and no_drop TC number are different. In order to obtain the better
4034 * performance, software could allocate the buffer size and configure
4035 * the waterline by trying to decrease the private buffer size according
4036 * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
4039 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
4042 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
4045 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
4052 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4054 struct hns3_rx_priv_buff_cmd *req;
4055 struct hns3_cmd_desc desc;
4060 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
4061 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
4063 /* Alloc private buffer TCs */
4064 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4065 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
4068 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
4069 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
4072 buf_size = buf_alloc->s_buf.buf_size;
4073 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
4074 (1 << HNS3_TC0_PRI_BUF_EN_B));
4076 ret = hns3_cmd_send(hw, &desc, 1);
4078 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
4084 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4086 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
4087 struct hns3_rx_priv_wl_buf *req;
4088 struct hns3_priv_buf *priv;
4089 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4093 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4094 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4096 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4098 /* The first descriptor set the NEXT bit to 1 */
4100 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4102 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4104 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4105 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4107 priv = &buf_alloc->priv_buf[idx];
4108 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4110 req->tc_wl[j].high |=
4111 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4112 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4114 req->tc_wl[j].low |=
4115 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4119 /* Send 2 descriptor at one time */
4120 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4122 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4128 hns3_common_thrd_config(struct hns3_hw *hw,
4129 struct hns3_pkt_buf_alloc *buf_alloc)
4131 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4132 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4133 struct hns3_rx_com_thrd *req;
4134 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4135 struct hns3_tc_thrd *tc;
4140 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4141 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4143 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4145 /* The first descriptor set the NEXT bit to 1 */
4147 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4149 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4151 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4152 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4153 tc = &s_buf->tc_thrd[tc_idx];
4155 req->com_thrd[j].high =
4156 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4157 req->com_thrd[j].high |=
4158 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4159 req->com_thrd[j].low =
4160 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4161 req->com_thrd[j].low |=
4162 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4166 /* Send 2 descriptors at one time */
4167 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4169 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4175 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4177 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4178 struct hns3_rx_com_wl *req;
4179 struct hns3_cmd_desc desc;
4182 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4184 req = (struct hns3_rx_com_wl *)desc.data;
4185 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4186 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4188 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4189 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4191 ret = hns3_cmd_send(hw, &desc, 1);
4193 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4199 hns3_buffer_alloc(struct hns3_hw *hw)
4201 struct hns3_pkt_buf_alloc pkt_buf;
4204 memset(&pkt_buf, 0, sizeof(pkt_buf));
4205 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4208 "could not calc tx buffer size for all TCs %d",
4213 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4215 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4219 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4222 "could not calc rx priv buffer size for all TCs %d",
4227 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4229 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4233 if (hns3_dev_get_support(hw, DCB)) {
4234 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4237 "could not configure rx private waterline %d",
4242 ret = hns3_common_thrd_config(hw, &pkt_buf);
4245 "could not configure common threshold %d",
4251 ret = hns3_common_wl_config(hw, &pkt_buf);
4253 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4260 hns3_mac_init(struct hns3_hw *hw)
4262 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4263 struct hns3_mac *mac = &hw->mac;
4264 struct hns3_pf *pf = &hns->pf;
4267 pf->support_sfp_query = true;
4268 mac->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
4269 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4271 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4275 mac->link_status = RTE_ETH_LINK_DOWN;
4277 return hns3_config_mtu(hw, pf->mps);
4281 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4283 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
4284 #define HNS3_ETHERTYPE_ALREADY_ADD 1
4285 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
4286 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
4291 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4296 switch (resp_code) {
4297 case HNS3_ETHERTYPE_SUCCESS_ADD:
4298 case HNS3_ETHERTYPE_ALREADY_ADD:
4301 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4303 "add mac ethertype failed for manager table overflow.");
4304 return_status = -EIO;
4306 case HNS3_ETHERTYPE_KEY_CONFLICT:
4307 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4308 return_status = -EIO;
4312 "add mac ethertype failed for undefined, code=%u.",
4314 return_status = -EIO;
4318 return return_status;
4322 hns3_add_mgr_tbl(struct hns3_hw *hw,
4323 const struct hns3_mac_mgr_tbl_entry_cmd *req)
4325 struct hns3_cmd_desc desc;
4330 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4331 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4333 ret = hns3_cmd_send(hw, &desc, 1);
4336 "add mac ethertype failed for cmd_send, ret =%d.",
4341 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4342 retval = rte_le_to_cpu_16(desc.retval);
4344 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4348 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4349 int *table_item_num)
4351 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4354 * In current version, we add one item in management table as below:
4355 * 0x0180C200000E -- LLDP MC address
4358 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4359 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4360 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4361 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4362 tbl->i_port_bitmap = 0x1;
4363 *table_item_num = 1;
4367 hns3_init_mgr_tbl(struct hns3_hw *hw)
4369 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
4370 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4375 memset(mgr_table, 0, sizeof(mgr_table));
4376 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4377 for (i = 0; i < table_item_num; i++) {
4378 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4380 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4390 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4391 bool en_mc, bool en_bc, int vport_id)
4396 memset(param, 0, sizeof(struct hns3_promisc_param));
4398 param->enable = HNS3_PROMISC_EN_UC;
4400 param->enable |= HNS3_PROMISC_EN_MC;
4402 param->enable |= HNS3_PROMISC_EN_BC;
4403 param->vf_id = vport_id;
4407 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4409 struct hns3_promisc_cfg_cmd *req;
4410 struct hns3_cmd_desc desc;
4413 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4415 req = (struct hns3_promisc_cfg_cmd *)desc.data;
4416 req->vf_id = param->vf_id;
4417 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4418 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4420 ret = hns3_cmd_send(hw, &desc, 1);
4422 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4428 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4430 struct hns3_promisc_param param;
4431 bool en_bc_pmc = true;
4435 * In current version VF is not supported when PF is driven by DPDK
4436 * driver, just need to configure parameters for PF vport.
4438 vf_id = HNS3_PF_FUNC_ID;
4440 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4441 return hns3_cmd_set_promisc_mode(hw, ¶m);
4445 hns3_promisc_init(struct hns3_hw *hw)
4447 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4448 struct hns3_pf *pf = &hns->pf;
4449 struct hns3_promisc_param param;
4453 ret = hns3_set_promisc_mode(hw, false, false);
4455 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4460 * In current version VFs are not supported when PF is driven by DPDK
4461 * driver. After PF has been taken over by DPDK, the original VF will
4462 * be invalid. So, there is a possibility of entry residues. It should
4463 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4466 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4467 hns3_promisc_param_init(¶m, false, false, false, func_id);
4468 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4470 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4471 " ret = %d", func_id, ret);
4480 hns3_promisc_uninit(struct hns3_hw *hw)
4482 struct hns3_promisc_param param;
4486 func_id = HNS3_PF_FUNC_ID;
4489 * In current version VFs are not supported when PF is driven by
4490 * DPDK driver, and VFs' promisc mode status has been cleared during
4491 * init and their status will not change. So just clear PF's promisc
4492 * mode status during uninit.
4494 hns3_promisc_param_init(¶m, false, false, false, func_id);
4495 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4497 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4498 " uninit, ret = %d", ret);
4502 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4504 bool allmulti = dev->data->all_multicast ? true : false;
4505 struct hns3_adapter *hns = dev->data->dev_private;
4506 struct hns3_hw *hw = &hns->hw;
4511 rte_spinlock_lock(&hw->lock);
4512 ret = hns3_set_promisc_mode(hw, true, true);
4514 rte_spinlock_unlock(&hw->lock);
4515 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4521 * When promiscuous mode was enabled, disable the vlan filter to let
4522 * all packets coming in in the receiving direction.
4524 offloads = dev->data->dev_conf.rxmode.offloads;
4525 if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
4526 ret = hns3_enable_vlan_filter(hns, false);
4528 hns3_err(hw, "failed to enable promiscuous mode due to "
4529 "failure to disable vlan filter, ret = %d",
4531 err = hns3_set_promisc_mode(hw, false, allmulti);
4533 hns3_err(hw, "failed to restore promiscuous "
4534 "status after disable vlan filter "
4535 "failed during enabling promiscuous "
4536 "mode, ret = %d", ret);
4540 rte_spinlock_unlock(&hw->lock);
4546 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4548 bool allmulti = dev->data->all_multicast ? true : false;
4549 struct hns3_adapter *hns = dev->data->dev_private;
4550 struct hns3_hw *hw = &hns->hw;
4555 /* If now in all_multicast mode, must remain in all_multicast mode. */
4556 rte_spinlock_lock(&hw->lock);
4557 ret = hns3_set_promisc_mode(hw, false, allmulti);
4559 rte_spinlock_unlock(&hw->lock);
4560 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4564 /* when promiscuous mode was disabled, restore the vlan filter status */
4565 offloads = dev->data->dev_conf.rxmode.offloads;
4566 if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
4567 ret = hns3_enable_vlan_filter(hns, true);
4569 hns3_err(hw, "failed to disable promiscuous mode due to"
4570 " failure to restore vlan filter, ret = %d",
4572 err = hns3_set_promisc_mode(hw, true, true);
4574 hns3_err(hw, "failed to restore promiscuous "
4575 "status after enabling vlan filter "
4576 "failed during disabling promiscuous "
4577 "mode, ret = %d", ret);
4580 rte_spinlock_unlock(&hw->lock);
4586 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4588 struct hns3_adapter *hns = dev->data->dev_private;
4589 struct hns3_hw *hw = &hns->hw;
4592 if (dev->data->promiscuous)
4595 rte_spinlock_lock(&hw->lock);
4596 ret = hns3_set_promisc_mode(hw, false, true);
4597 rte_spinlock_unlock(&hw->lock);
4599 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4606 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4608 struct hns3_adapter *hns = dev->data->dev_private;
4609 struct hns3_hw *hw = &hns->hw;
4612 /* If now in promiscuous mode, must remain in all_multicast mode. */
4613 if (dev->data->promiscuous)
4616 rte_spinlock_lock(&hw->lock);
4617 ret = hns3_set_promisc_mode(hw, false, false);
4618 rte_spinlock_unlock(&hw->lock);
4620 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4627 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4629 struct hns3_hw *hw = &hns->hw;
4630 bool allmulti = hw->data->all_multicast ? true : false;
4633 if (hw->data->promiscuous) {
4634 ret = hns3_set_promisc_mode(hw, true, true);
4636 hns3_err(hw, "failed to restore promiscuous mode, "
4641 ret = hns3_set_promisc_mode(hw, false, allmulti);
4643 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4649 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4651 struct hns3_sfp_info_cmd *resp;
4652 struct hns3_cmd_desc desc;
4655 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4656 resp = (struct hns3_sfp_info_cmd *)desc.data;
4657 resp->query_type = HNS3_ACTIVE_QUERY;
4659 ret = hns3_cmd_send(hw, &desc, 1);
4660 if (ret == -EOPNOTSUPP) {
4661 hns3_warn(hw, "firmware does not support get SFP info,"
4665 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4670 * In some case, the speed of MAC obtained from firmware may be 0, it
4671 * shouldn't be set to mac->speed.
4673 if (!rte_le_to_cpu_32(resp->sfp_speed))
4676 mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4678 * if resp->supported_speed is 0, it means it's an old version
4679 * firmware, do not update these params.
4681 if (resp->supported_speed) {
4682 mac_info->query_type = HNS3_ACTIVE_QUERY;
4683 mac_info->supported_speed =
4684 rte_le_to_cpu_32(resp->supported_speed);
4685 mac_info->support_autoneg = resp->autoneg_ability;
4686 mac_info->link_autoneg = (resp->autoneg == 0) ? RTE_ETH_LINK_FIXED
4687 : RTE_ETH_LINK_AUTONEG;
4689 mac_info->query_type = HNS3_DEFAULT_QUERY;
4696 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4698 if (!(speed == RTE_ETH_SPEED_NUM_10M || speed == RTE_ETH_SPEED_NUM_100M))
4699 duplex = RTE_ETH_LINK_FULL_DUPLEX;
4705 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4707 struct hns3_mac *mac = &hw->mac;
4710 duplex = hns3_check_speed_dup(duplex, speed);
4711 if (mac->link_speed == speed && mac->link_duplex == duplex)
4714 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4718 ret = hns3_port_shaper_update(hw, speed);
4722 mac->link_speed = speed;
4723 mac->link_duplex = duplex;
4729 hns3_update_fiber_link_info(struct hns3_hw *hw)
4731 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4732 struct hns3_mac *mac = &hw->mac;
4733 struct hns3_mac mac_info;
4736 /* If firmware do not support get SFP/qSFP speed, return directly */
4737 if (!pf->support_sfp_query)
4740 memset(&mac_info, 0, sizeof(struct hns3_mac));
4741 ret = hns3_get_sfp_info(hw, &mac_info);
4742 if (ret == -EOPNOTSUPP) {
4743 pf->support_sfp_query = false;
4748 /* Do nothing if no SFP */
4749 if (mac_info.link_speed == RTE_ETH_SPEED_NUM_NONE)
4753 * If query_type is HNS3_ACTIVE_QUERY, it is no need
4754 * to reconfigure the speed of MAC. Otherwise, it indicates
4755 * that the current firmware only supports to obtain the
4756 * speed of the SFP, and the speed of MAC needs to reconfigure.
4758 mac->query_type = mac_info.query_type;
4759 if (mac->query_type == HNS3_ACTIVE_QUERY) {
4760 if (mac_info.link_speed != mac->link_speed) {
4761 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4766 mac->link_speed = mac_info.link_speed;
4767 mac->supported_speed = mac_info.supported_speed;
4768 mac->support_autoneg = mac_info.support_autoneg;
4769 mac->link_autoneg = mac_info.link_autoneg;
4774 /* Config full duplex for SFP */
4775 return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4776 RTE_ETH_LINK_FULL_DUPLEX);
4780 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4782 #define HNS3_PHY_SUPPORTED_SPEED_MASK 0x2f
4784 struct hns3_phy_params_bd0_cmd *req;
4787 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4788 mac->link_speed = rte_le_to_cpu_32(req->speed);
4789 mac->link_duplex = hns3_get_bit(req->duplex,
4790 HNS3_PHY_DUPLEX_CFG_B);
4791 mac->link_autoneg = hns3_get_bit(req->autoneg,
4792 HNS3_PHY_AUTONEG_CFG_B);
4793 mac->advertising = rte_le_to_cpu_32(req->advertising);
4794 mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4795 supported = rte_le_to_cpu_32(req->supported);
4796 mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4797 mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4801 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4803 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4807 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4808 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4810 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4812 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4814 ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4816 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4820 hns3_parse_copper_phy_params(desc, mac);
4826 hns3_update_copper_link_info(struct hns3_hw *hw)
4828 struct hns3_mac *mac = &hw->mac;
4829 struct hns3_mac mac_info;
4832 memset(&mac_info, 0, sizeof(struct hns3_mac));
4833 ret = hns3_get_copper_phy_params(hw, &mac_info);
4837 if (mac_info.link_speed != mac->link_speed) {
4838 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4843 mac->link_speed = mac_info.link_speed;
4844 mac->link_duplex = mac_info.link_duplex;
4845 mac->link_autoneg = mac_info.link_autoneg;
4846 mac->supported_speed = mac_info.supported_speed;
4847 mac->advertising = mac_info.advertising;
4848 mac->lp_advertising = mac_info.lp_advertising;
4849 mac->support_autoneg = mac_info.support_autoneg;
4855 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4857 struct hns3_adapter *hns = eth_dev->data->dev_private;
4858 struct hns3_hw *hw = &hns->hw;
4861 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4862 ret = hns3_update_copper_link_info(hw);
4863 else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4864 ret = hns3_update_fiber_link_info(hw);
4870 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4872 struct hns3_config_mac_mode_cmd *req;
4873 struct hns3_cmd_desc desc;
4874 uint32_t loop_en = 0;
4878 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4880 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4883 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4884 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4885 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4886 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4887 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4888 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4889 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4890 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4891 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4892 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4895 * If RTE_ETH_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4896 * when receiving frames. Otherwise, CRC will be stripped.
4898 if (hw->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
4899 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4901 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4902 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4903 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4904 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4905 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4907 ret = hns3_cmd_send(hw, &desc, 1);
4909 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4915 hns3_get_mac_link_status(struct hns3_hw *hw)
4917 struct hns3_link_status_cmd *req;
4918 struct hns3_cmd_desc desc;
4922 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4923 ret = hns3_cmd_send(hw, &desc, 1);
4925 hns3_err(hw, "get link status cmd failed %d", ret);
4926 return RTE_ETH_LINK_DOWN;
4929 req = (struct hns3_link_status_cmd *)desc.data;
4930 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4932 return !!link_status;
4936 hns3_update_link_status(struct hns3_hw *hw)
4940 state = hns3_get_mac_link_status(hw);
4941 if (state != hw->mac.link_status) {
4942 hw->mac.link_status = state;
4943 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4951 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4953 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4954 struct rte_eth_link new_link;
4958 hns3_update_port_link_info(dev);
4960 memset(&new_link, 0, sizeof(new_link));
4961 hns3_setup_linkstatus(dev, &new_link);
4963 ret = rte_eth_linkstatus_set(dev, &new_link);
4964 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4965 hns3_start_report_lse(dev);
4969 hns3_service_handler(void *param)
4971 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4972 struct hns3_adapter *hns = eth_dev->data->dev_private;
4973 struct hns3_hw *hw = &hns->hw;
4975 if (!hns3_is_reset_pending(hns))
4976 hns3_update_linkstatus_and_event(hw, true);
4978 hns3_warn(hw, "Cancel the query when reset is pending");
4980 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4984 hns3_init_hardware(struct hns3_adapter *hns)
4986 struct hns3_hw *hw = &hns->hw;
4989 ret = hns3_map_tqp(hw);
4991 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4995 ret = hns3_init_umv_space(hw);
4997 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
5001 ret = hns3_mac_init(hw);
5003 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
5007 ret = hns3_init_mgr_tbl(hw);
5009 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
5013 ret = hns3_promisc_init(hw);
5015 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
5020 ret = hns3_init_vlan_config(hns);
5022 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
5026 ret = hns3_dcb_init(hw);
5028 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
5032 ret = hns3_init_fd_config(hns);
5034 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
5038 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
5040 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
5044 ret = hns3_config_gro(hw, false);
5046 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
5051 * In the initialization clearing the all hardware mapping relationship
5052 * configurations between queues and interrupt vectors is needed, so
5053 * some error caused by the residual configurations, such as the
5054 * unexpected interrupt, can be avoid.
5056 ret = hns3_init_ring_with_vector(hw);
5058 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
5065 hns3_uninit_umv_space(hw);
5070 hns3_clear_hw(struct hns3_hw *hw)
5072 struct hns3_cmd_desc desc;
5075 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
5077 ret = hns3_cmd_send(hw, &desc, 1);
5078 if (ret && ret != -EOPNOTSUPP)
5085 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
5090 * The new firmware support report more hardware error types by
5091 * msix mode. These errors are defined as RAS errors in hardware
5092 * and belong to a different type from the MSI-x errors processed
5093 * by the network driver.
5095 * Network driver should open the new error report on initialization.
5097 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5098 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5099 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5103 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5105 struct hns3_mac *mac = &hw->mac;
5107 switch (mac->link_speed) {
5108 case RTE_ETH_SPEED_NUM_1G:
5109 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5110 case RTE_ETH_SPEED_NUM_10G:
5111 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5112 case RTE_ETH_SPEED_NUM_25G:
5113 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5114 case RTE_ETH_SPEED_NUM_40G:
5115 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5116 case RTE_ETH_SPEED_NUM_50G:
5117 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5118 case RTE_ETH_SPEED_NUM_100G:
5119 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5120 case RTE_ETH_SPEED_NUM_200G:
5121 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5123 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5129 * Validity of supported_speed for firber and copper media type can be
5130 * guaranteed by the following policy:
5132 * Although the initialization of the phy in the firmware may not be
5133 * completed, the firmware can guarantees that the supported_speed is
5136 * If the version of firmware supports the acitive query way of the
5137 * HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5138 * through it. If unsupported, use the SFP's speed as the value of the
5142 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5144 struct hns3_adapter *hns = eth_dev->data->dev_private;
5145 struct hns3_hw *hw = &hns->hw;
5146 struct hns3_mac *mac = &hw->mac;
5149 ret = hns3_update_link_info(eth_dev);
5153 if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5155 * Some firmware does not support the report of supported_speed,
5156 * and only report the effective speed of SFP. In this case, it
5157 * is necessary to use the SFP's speed as the supported_speed.
5159 if (mac->supported_speed == 0)
5160 mac->supported_speed =
5161 hns3_set_firber_default_support_speed(hw);
5168 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
5170 struct hns3_mac *mac = &hns->hw.mac;
5172 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
5173 hns->pf.support_fc_autoneg = true;
5178 * Flow control auto-negotiation requires the cooperation of the driver
5179 * and firmware. Currently, the optical port does not support flow
5180 * control auto-negotiation.
5182 hns->pf.support_fc_autoneg = false;
5186 hns3_init_pf(struct rte_eth_dev *eth_dev)
5188 struct rte_device *dev = eth_dev->device;
5189 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5190 struct hns3_adapter *hns = eth_dev->data->dev_private;
5191 struct hns3_hw *hw = &hns->hw;
5194 PMD_INIT_FUNC_TRACE();
5196 /* Get hardware io base address from pcie BAR2 IO space */
5197 hw->io_base = pci_dev->mem_resource[2].addr;
5199 /* Firmware command queue initialize */
5200 ret = hns3_cmd_init_queue(hw);
5202 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5203 goto err_cmd_init_queue;
5206 hns3_clear_all_event_cause(hw);
5208 /* Firmware command initialize */
5209 ret = hns3_cmd_init(hw);
5211 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5215 hns3_tx_push_init(eth_dev);
5218 * To ensure that the hardware environment is clean during
5219 * initialization, the driver actively clear the hardware environment
5220 * during initialization, including PF and corresponding VFs' vlan, mac,
5221 * flow table configurations, etc.
5223 ret = hns3_clear_hw(hw);
5225 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5229 /* Hardware statistics of imissed registers cleared. */
5230 ret = hns3_update_imissed_stats(hw, true);
5232 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5236 hns3_config_all_msix_error(hw, true);
5238 ret = rte_intr_callback_register(pci_dev->intr_handle,
5239 hns3_interrupt_handler,
5242 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5243 goto err_intr_callback_register;
5246 ret = hns3_ptp_init(hw);
5248 goto err_get_config;
5250 /* Enable interrupt */
5251 rte_intr_enable(pci_dev->intr_handle);
5252 hns3_pf_enable_irq0(hw);
5254 /* Get configuration */
5255 ret = hns3_get_configuration(hw);
5257 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5258 goto err_get_config;
5261 ret = hns3_tqp_stats_init(hw);
5263 goto err_get_config;
5265 ret = hns3_init_hardware(hns);
5267 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5271 /* Initialize flow director filter list & hash */
5272 ret = hns3_fdir_filter_init(hns);
5274 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5278 hns3_rss_set_default_args(hw);
5280 ret = hns3_enable_hw_error_intr(hns, true);
5282 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5284 goto err_enable_intr;
5287 ret = hns3_get_port_supported_speed(eth_dev);
5289 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5290 "by device, ret = %d.", ret);
5291 goto err_supported_speed;
5294 hns3_get_fc_autoneg_capability(hns);
5296 hns3_tm_conf_init(eth_dev);
5300 err_supported_speed:
5301 (void)hns3_enable_hw_error_intr(hns, false);
5303 hns3_fdir_filter_uninit(hns);
5305 hns3_uninit_umv_space(hw);
5307 hns3_tqp_stats_uninit(hw);
5309 hns3_pf_disable_irq0(hw);
5310 rte_intr_disable(pci_dev->intr_handle);
5311 hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
5313 err_intr_callback_register:
5315 hns3_cmd_uninit(hw);
5316 hns3_cmd_destroy_queue(hw);
5324 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5326 struct hns3_adapter *hns = eth_dev->data->dev_private;
5327 struct rte_device *dev = eth_dev->device;
5328 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5329 struct hns3_hw *hw = &hns->hw;
5331 PMD_INIT_FUNC_TRACE();
5333 hns3_tm_conf_uninit(eth_dev);
5334 hns3_enable_hw_error_intr(hns, false);
5335 hns3_rss_uninit(hns);
5336 (void)hns3_config_gro(hw, false);
5337 hns3_promisc_uninit(hw);
5338 hns3_flow_uninit(eth_dev);
5339 hns3_fdir_filter_uninit(hns);
5340 hns3_uninit_umv_space(hw);
5341 hns3_tqp_stats_uninit(hw);
5342 hns3_config_mac_tnl_int(hw, false);
5343 hns3_pf_disable_irq0(hw);
5344 rte_intr_disable(pci_dev->intr_handle);
5345 hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
5347 hns3_config_all_msix_error(hw, false);
5348 hns3_cmd_uninit(hw);
5349 hns3_cmd_destroy_queue(hw);
5354 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
5358 switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) {
5359 case RTE_ETH_LINK_SPEED_10M:
5360 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
5362 case RTE_ETH_LINK_SPEED_10M_HD:
5363 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
5365 case RTE_ETH_LINK_SPEED_100M:
5366 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
5368 case RTE_ETH_LINK_SPEED_100M_HD:
5369 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
5371 case RTE_ETH_LINK_SPEED_1G:
5372 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
5383 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
5387 switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) {
5388 case RTE_ETH_LINK_SPEED_1G:
5389 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
5391 case RTE_ETH_LINK_SPEED_10G:
5392 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
5394 case RTE_ETH_LINK_SPEED_25G:
5395 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
5397 case RTE_ETH_LINK_SPEED_40G:
5398 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
5400 case RTE_ETH_LINK_SPEED_50G:
5401 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
5403 case RTE_ETH_LINK_SPEED_100G:
5404 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
5406 case RTE_ETH_LINK_SPEED_200G:
5407 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
5418 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
5420 struct hns3_mac *mac = &hw->mac;
5421 uint32_t supported_speed = mac->supported_speed;
5422 uint32_t speed_bit = 0;
5424 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
5425 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
5426 else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
5427 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
5429 if (!(speed_bit & supported_speed)) {
5430 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
5438 static inline uint32_t
5439 hns3_get_link_speed(uint32_t link_speeds)
5441 uint32_t speed = RTE_ETH_SPEED_NUM_NONE;
5443 if (link_speeds & RTE_ETH_LINK_SPEED_10M ||
5444 link_speeds & RTE_ETH_LINK_SPEED_10M_HD)
5445 speed = RTE_ETH_SPEED_NUM_10M;
5446 if (link_speeds & RTE_ETH_LINK_SPEED_100M ||
5447 link_speeds & RTE_ETH_LINK_SPEED_100M_HD)
5448 speed = RTE_ETH_SPEED_NUM_100M;
5449 if (link_speeds & RTE_ETH_LINK_SPEED_1G)
5450 speed = RTE_ETH_SPEED_NUM_1G;
5451 if (link_speeds & RTE_ETH_LINK_SPEED_10G)
5452 speed = RTE_ETH_SPEED_NUM_10G;
5453 if (link_speeds & RTE_ETH_LINK_SPEED_25G)
5454 speed = RTE_ETH_SPEED_NUM_25G;
5455 if (link_speeds & RTE_ETH_LINK_SPEED_40G)
5456 speed = RTE_ETH_SPEED_NUM_40G;
5457 if (link_speeds & RTE_ETH_LINK_SPEED_50G)
5458 speed = RTE_ETH_SPEED_NUM_50G;
5459 if (link_speeds & RTE_ETH_LINK_SPEED_100G)
5460 speed = RTE_ETH_SPEED_NUM_100G;
5461 if (link_speeds & RTE_ETH_LINK_SPEED_200G)
5462 speed = RTE_ETH_SPEED_NUM_200G;
5468 hns3_get_link_duplex(uint32_t link_speeds)
5470 if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) ||
5471 (link_speeds & RTE_ETH_LINK_SPEED_100M_HD))
5472 return RTE_ETH_LINK_HALF_DUPLEX;
5474 return RTE_ETH_LINK_FULL_DUPLEX;
5478 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5479 struct hns3_set_link_speed_cfg *cfg)
5481 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5482 struct hns3_phy_params_bd0_cmd *req;
5485 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5486 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5488 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5490 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5491 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5492 req->autoneg = cfg->autoneg;
5495 * The full speed capability is used to negotiate when
5496 * auto-negotiation is enabled.
5499 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5500 HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5501 HNS3_PHY_LINK_SPEED_100M_BIT |
5502 HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5503 HNS3_PHY_LINK_SPEED_1000M_BIT;
5505 req->speed = cfg->speed;
5506 req->duplex = cfg->duplex;
5509 return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5513 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5515 struct hns3_config_auto_neg_cmd *req;
5516 struct hns3_cmd_desc desc;
5520 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5522 req = (struct hns3_config_auto_neg_cmd *)desc.data;
5524 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5525 req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5527 ret = hns3_cmd_send(hw, &desc, 1);
5529 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5535 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5536 struct hns3_set_link_speed_cfg *cfg)
5540 if (hw->mac.support_autoneg) {
5541 ret = hns3_set_autoneg(hw, cfg->autoneg);
5543 hns3_err(hw, "failed to configure auto-negotiation.");
5548 * To enable auto-negotiation, we only need to open the switch
5549 * of auto-negotiation, then firmware sets all speed
5557 * Some hardware doesn't support auto-negotiation, but users may not
5558 * configure link_speeds (default 0), which means auto-negotiation.
5559 * In this case, a warning message need to be printed, instead of
5563 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
5567 return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
5571 hns3_set_port_link_speed(struct hns3_hw *hw,
5572 struct hns3_set_link_speed_cfg *cfg)
5576 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5577 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5578 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5583 ret = hns3_set_copper_port_link_speed(hw, cfg);
5585 hns3_err(hw, "failed to set copper port link speed,"
5589 } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5590 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5592 hns3_err(hw, "failed to set fiber port link speed,"
5602 hns3_apply_link_speed(struct hns3_hw *hw)
5604 struct rte_eth_conf *conf = &hw->data->dev_conf;
5605 struct hns3_set_link_speed_cfg cfg;
5607 memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5608 cfg.autoneg = (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) ?
5609 RTE_ETH_LINK_AUTONEG : RTE_ETH_LINK_FIXED;
5610 if (cfg.autoneg != RTE_ETH_LINK_AUTONEG) {
5611 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5612 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5615 return hns3_set_port_link_speed(hw, &cfg);
5619 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5621 struct hns3_hw *hw = &hns->hw;
5625 ret = hns3_update_queue_map_configure(hns);
5627 hns3_err(hw, "failed to update queue mapping configuration, ret = %d",
5632 /* Note: hns3_tm_conf_update must be called after configuring DCB. */
5633 ret = hns3_tm_conf_update(hw);
5635 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5639 hns3_enable_rxd_adv_layout(hw);
5641 ret = hns3_init_queues(hns, reset_queue);
5643 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5647 link_en = hw->set_link_down ? false : true;
5648 ret = hns3_cfg_mac_mode(hw, link_en);
5650 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5651 goto err_config_mac_mode;
5654 ret = hns3_apply_link_speed(hw);
5656 goto err_set_link_speed;
5661 (void)hns3_cfg_mac_mode(hw, false);
5663 err_config_mac_mode:
5664 hns3_dev_release_mbufs(hns);
5666 * Here is exception handling, hns3_reset_all_tqps will have the
5667 * corresponding error message if it is handled incorrectly, so it is
5668 * not necessary to check hns3_reset_all_tqps return value, here keep
5669 * ret as the error code causing the exception.
5671 (void)hns3_reset_all_tqps(hns);
5676 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5678 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5679 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5680 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5681 uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5682 uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5683 uint32_t intr_vector;
5688 * hns3 needs a separate interrupt to be used as event interrupt which
5689 * could not be shared with task queue pair, so KERNEL drivers need
5690 * support multiple interrupt vectors.
5692 if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5693 !rte_intr_cap_multiple(intr_handle))
5696 rte_intr_disable(intr_handle);
5697 intr_vector = hw->used_rx_queues;
5698 /* creates event fd for each intr vector when MSIX is used */
5699 if (rte_intr_efd_enable(intr_handle, intr_vector))
5702 /* Allocate vector list */
5703 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
5704 hw->used_rx_queues)) {
5705 hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5706 hw->used_rx_queues);
5708 goto alloc_intr_vec_error;
5711 if (rte_intr_allow_others(intr_handle)) {
5712 vec = RTE_INTR_VEC_RXTX_OFFSET;
5713 base = RTE_INTR_VEC_RXTX_OFFSET;
5716 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5717 ret = hns3_bind_ring_with_vector(hw, vec, true,
5718 HNS3_RING_TYPE_RX, q_id);
5720 goto bind_vector_error;
5722 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
5723 goto bind_vector_error;
5725 * If there are not enough efds (e.g. not enough interrupt),
5726 * remaining queues will be bond to the last interrupt.
5728 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
5731 rte_intr_enable(intr_handle);
5735 rte_intr_vec_list_free(intr_handle);
5736 alloc_intr_vec_error:
5737 rte_intr_efd_disable(intr_handle);
5742 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5744 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5745 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5746 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5750 if (dev->data->dev_conf.intr_conf.rxq == 0)
5753 if (rte_intr_dp_is_en(intr_handle)) {
5754 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5755 ret = hns3_bind_ring_with_vector(hw,
5756 rte_intr_vec_list_index_get(intr_handle,
5758 true, HNS3_RING_TYPE_RX, q_id);
5768 hns3_restore_filter(struct rte_eth_dev *dev)
5770 hns3_restore_rss_filter(dev);
5774 hns3_dev_start(struct rte_eth_dev *dev)
5776 struct hns3_adapter *hns = dev->data->dev_private;
5777 struct hns3_hw *hw = &hns->hw;
5778 bool old_state = hw->set_link_down;
5781 PMD_INIT_FUNC_TRACE();
5782 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5785 rte_spinlock_lock(&hw->lock);
5786 hw->adapter_state = HNS3_NIC_STARTING;
5789 * If the dev_set_link_down() API has been called, the "set_link_down"
5790 * flag can be cleared by dev_start() API. In addition, the flag should
5791 * also be cleared before calling hns3_do_start() so that MAC can be
5792 * enabled in dev_start stage.
5794 hw->set_link_down = false;
5795 ret = hns3_do_start(hns, true);
5799 ret = hns3_map_rx_interrupt(dev);
5801 goto map_rx_inter_err;
5804 * There are three register used to control the status of a TQP
5805 * (contains a pair of Tx queue and Rx queue) in the new version network
5806 * engine. One is used to control the enabling of Tx queue, the other is
5807 * used to control the enabling of Rx queue, and the last is the master
5808 * switch used to control the enabling of the tqp. The Tx register and
5809 * TQP register must be enabled at the same time to enable a Tx queue.
5810 * The same applies to the Rx queue. For the older network engine, this
5811 * function only refresh the enabled flag, and it is used to update the
5812 * status of queue in the dpdk framework.
5814 ret = hns3_start_all_txqs(dev);
5816 goto map_rx_inter_err;
5818 ret = hns3_start_all_rxqs(dev);
5820 goto start_all_rxqs_fail;
5822 hw->adapter_state = HNS3_NIC_STARTED;
5823 rte_spinlock_unlock(&hw->lock);
5825 hns3_rx_scattered_calc(dev);
5826 hns3_set_rxtx_function(dev);
5827 hns3_mp_req_start_rxtx(dev);
5829 hns3_restore_filter(dev);
5831 /* Enable interrupt of all rx queues before enabling queues */
5832 hns3_dev_all_rx_queue_intr_enable(hw, true);
5835 * After finished the initialization, enable tqps to receive/transmit
5836 * packets and refresh all queue status.
5838 hns3_start_tqps(hw);
5840 hns3_tm_dev_start_proc(hw);
5842 if (dev->data->dev_conf.intr_conf.lsc != 0)
5843 hns3_dev_link_update(dev, 0);
5844 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5846 hns3_info(hw, "hns3 dev start successful!");
5850 start_all_rxqs_fail:
5851 hns3_stop_all_txqs(dev);
5853 (void)hns3_do_stop(hns);
5855 hw->set_link_down = old_state;
5856 hw->adapter_state = HNS3_NIC_CONFIGURED;
5857 rte_spinlock_unlock(&hw->lock);
5863 hns3_do_stop(struct hns3_adapter *hns)
5865 struct hns3_hw *hw = &hns->hw;
5869 * The "hns3_do_stop" function will also be called by .stop_service to
5870 * prepare reset. At the time of global or IMP reset, the command cannot
5871 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5872 * accessed during the reset process. So the mbuf can not be released
5873 * during reset and is required to be released after the reset is
5876 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)
5877 hns3_dev_release_mbufs(hns);
5879 ret = hns3_cfg_mac_mode(hw, false);
5882 hw->mac.link_status = RTE_ETH_LINK_DOWN;
5884 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5885 hns3_configure_all_mac_addr(hns, true);
5886 ret = hns3_reset_all_tqps(hns);
5888 hns3_err(hw, "failed to reset all queues ret = %d.",
5898 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5900 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5901 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5902 struct hns3_adapter *hns = dev->data->dev_private;
5903 struct hns3_hw *hw = &hns->hw;
5904 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5905 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5908 if (dev->data->dev_conf.intr_conf.rxq == 0)
5911 /* unmap the ring with vector */
5912 if (rte_intr_allow_others(intr_handle)) {
5913 vec = RTE_INTR_VEC_RXTX_OFFSET;
5914 base = RTE_INTR_VEC_RXTX_OFFSET;
5916 if (rte_intr_dp_is_en(intr_handle)) {
5917 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5918 (void)hns3_bind_ring_with_vector(hw, vec, false,
5921 if (vec < base + rte_intr_nb_efd_get(intr_handle)
5926 /* Clean datapath event and queue/vec mapping */
5927 rte_intr_efd_disable(intr_handle);
5928 rte_intr_vec_list_free(intr_handle);
5932 hns3_dev_stop(struct rte_eth_dev *dev)
5934 struct hns3_adapter *hns = dev->data->dev_private;
5935 struct hns3_hw *hw = &hns->hw;
5937 PMD_INIT_FUNC_TRACE();
5938 dev->data->dev_started = 0;
5940 hw->adapter_state = HNS3_NIC_STOPPING;
5941 hns3_set_rxtx_function(dev);
5943 /* Disable datapath on secondary process. */
5944 hns3_mp_req_stop_rxtx(dev);
5945 /* Prevent crashes when queues are still in use. */
5946 rte_delay_ms(hw->cfg_max_queues);
5948 rte_spinlock_lock(&hw->lock);
5949 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5950 hns3_tm_dev_stop_proc(hw);
5951 hns3_config_mac_tnl_int(hw, false);
5954 hns3_unmap_rx_interrupt(dev);
5955 hw->adapter_state = HNS3_NIC_CONFIGURED;
5957 hns3_rx_scattered_reset(dev);
5958 rte_eal_alarm_cancel(hns3_service_handler, dev);
5959 hns3_stop_report_lse(dev);
5960 rte_spinlock_unlock(&hw->lock);
5966 hns3_dev_close(struct rte_eth_dev *eth_dev)
5968 struct hns3_adapter *hns = eth_dev->data->dev_private;
5969 struct hns3_hw *hw = &hns->hw;
5972 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5975 if (hw->adapter_state == HNS3_NIC_STARTED)
5976 ret = hns3_dev_stop(eth_dev);
5978 hw->adapter_state = HNS3_NIC_CLOSING;
5979 hns3_reset_abort(hns);
5980 hw->adapter_state = HNS3_NIC_CLOSED;
5982 hns3_configure_all_mc_mac_addr(hns, true);
5983 hns3_remove_all_vlan_table(hns);
5984 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5985 hns3_uninit_pf(eth_dev);
5986 hns3_free_all_queues(eth_dev);
5987 rte_free(hw->reset.wait_data);
5988 hns3_mp_uninit_primary();
5989 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5995 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5998 struct hns3_mac *mac = &hw->mac;
5999 uint32_t advertising = mac->advertising;
6000 uint32_t lp_advertising = mac->lp_advertising;
6004 if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
6007 } else if (advertising & lp_advertising &
6008 HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
6009 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
6011 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
6016 static enum hns3_fc_mode
6017 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
6019 enum hns3_fc_mode current_mode;
6020 bool rx_pause = false;
6021 bool tx_pause = false;
6023 switch (hw->mac.media_type) {
6024 case HNS3_MEDIA_TYPE_COPPER:
6025 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
6029 * Flow control auto-negotiation is not supported for fiber and
6030 * backpalne media type.
6032 case HNS3_MEDIA_TYPE_FIBER:
6033 case HNS3_MEDIA_TYPE_BACKPLANE:
6034 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
6035 current_mode = hw->requested_fc_mode;
6038 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
6039 hw->mac.media_type);
6040 current_mode = HNS3_FC_NONE;
6044 if (rx_pause && tx_pause)
6045 current_mode = HNS3_FC_FULL;
6047 current_mode = HNS3_FC_RX_PAUSE;
6049 current_mode = HNS3_FC_TX_PAUSE;
6051 current_mode = HNS3_FC_NONE;
6054 return current_mode;
6057 static enum hns3_fc_mode
6058 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
6060 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6061 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6062 struct hns3_mac *mac = &hw->mac;
6065 * When the flow control mode is obtained, the device may not complete
6066 * auto-negotiation. It is necessary to wait for link establishment.
6068 (void)hns3_dev_link_update(dev, 1);
6071 * If the link auto-negotiation of the nic is disabled, or the flow
6072 * control auto-negotiation is not supported, the forced flow control
6075 if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
6076 return hw->requested_fc_mode;
6078 return hns3_get_autoneg_fc_mode(hw);
6082 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6084 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6085 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6086 enum hns3_fc_mode current_mode;
6088 current_mode = hns3_get_current_fc_mode(dev);
6089 switch (current_mode) {
6091 fc_conf->mode = RTE_ETH_FC_FULL;
6093 case HNS3_FC_TX_PAUSE:
6094 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
6096 case HNS3_FC_RX_PAUSE:
6097 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
6101 fc_conf->mode = RTE_ETH_FC_NONE;
6105 fc_conf->pause_time = pf->pause_time;
6106 fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
6112 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
6114 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
6116 if (!pf->support_fc_autoneg) {
6118 hns3_err(hw, "unsupported fc auto-negotiation setting.");
6123 * Flow control auto-negotiation of the NIC is not supported,
6124 * but other auto-negotiation features may be supported.
6126 if (autoneg != hw->mac.link_autoneg) {
6127 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
6135 * If flow control auto-negotiation of the NIC is supported, all
6136 * auto-negotiation features are supported.
6138 if (autoneg != hw->mac.link_autoneg) {
6139 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
6147 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6149 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6150 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6153 if (fc_conf->high_water || fc_conf->low_water ||
6154 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
6155 hns3_err(hw, "Unsupported flow control settings specified, "
6156 "high_water(%u), low_water(%u), send_xon(%u) and "
6157 "mac_ctrl_frame_fwd(%u) must be set to '0'",
6158 fc_conf->high_water, fc_conf->low_water,
6159 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
6163 ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
6167 if (!fc_conf->pause_time) {
6168 hns3_err(hw, "Invalid pause time %u setting.",
6169 fc_conf->pause_time);
6173 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6174 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
6175 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
6176 "current_fc_status = %d", hw->current_fc_status);
6180 if (hw->num_tc > 1 && !pf->support_multi_tc_pause) {
6181 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
6185 rte_spinlock_lock(&hw->lock);
6186 ret = hns3_fc_enable(dev, fc_conf);
6187 rte_spinlock_unlock(&hw->lock);
6193 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
6194 struct rte_eth_pfc_conf *pfc_conf)
6196 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6199 if (!hns3_dev_get_support(hw, DCB)) {
6200 hns3_err(hw, "This port does not support dcb configurations.");
6204 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
6205 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
6206 hns3_err(hw, "Unsupported flow control settings specified, "
6207 "high_water(%u), low_water(%u), send_xon(%u) and "
6208 "mac_ctrl_frame_fwd(%u) must be set to '0'",
6209 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
6210 pfc_conf->fc.send_xon,
6211 pfc_conf->fc.mac_ctrl_frame_fwd);
6214 if (pfc_conf->fc.autoneg) {
6215 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
6218 if (pfc_conf->fc.pause_time == 0) {
6219 hns3_err(hw, "Invalid pause time %u setting.",
6220 pfc_conf->fc.pause_time);
6224 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6225 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
6226 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
6227 "current_fc_status = %d", hw->current_fc_status);
6231 rte_spinlock_lock(&hw->lock);
6232 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
6233 rte_spinlock_unlock(&hw->lock);
6239 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
6241 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6242 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6243 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
6246 rte_spinlock_lock(&hw->lock);
6247 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG)
6248 dcb_info->nb_tcs = pf->local_max_tc;
6250 dcb_info->nb_tcs = 1;
6252 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
6253 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
6254 for (i = 0; i < dcb_info->nb_tcs; i++)
6255 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
6257 for (i = 0; i < hw->num_tc; i++) {
6258 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
6259 dcb_info->tc_queue.tc_txq[0][i].base =
6260 hw->tc_queue[i].tqp_offset;
6261 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
6262 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
6263 hw->tc_queue[i].tqp_count;
6265 rte_spinlock_unlock(&hw->lock);
6271 hns3_reinit_dev(struct hns3_adapter *hns)
6273 struct hns3_hw *hw = &hns->hw;
6276 ret = hns3_cmd_init(hw);
6278 hns3_err(hw, "Failed to init cmd: %d", ret);
6282 ret = hns3_reset_all_tqps(hns);
6284 hns3_err(hw, "Failed to reset all queues: %d", ret);
6288 ret = hns3_init_hardware(hns);
6290 hns3_err(hw, "Failed to init hardware: %d", ret);
6294 ret = hns3_enable_hw_error_intr(hns, true);
6296 hns3_err(hw, "fail to enable hw error interrupts: %d",
6300 hns3_info(hw, "Reset done, driver initialization finished.");
6306 is_pf_reset_done(struct hns3_hw *hw)
6308 uint32_t val, reg, reg_bit;
6310 switch (hw->reset.level) {
6311 case HNS3_IMP_RESET:
6312 reg = HNS3_GLOBAL_RESET_REG;
6313 reg_bit = HNS3_IMP_RESET_BIT;
6315 case HNS3_GLOBAL_RESET:
6316 reg = HNS3_GLOBAL_RESET_REG;
6317 reg_bit = HNS3_GLOBAL_RESET_BIT;
6319 case HNS3_FUNC_RESET:
6320 reg = HNS3_FUN_RST_ING;
6321 reg_bit = HNS3_FUN_RST_ING_B;
6323 case HNS3_FLR_RESET:
6325 hns3_err(hw, "Wait for unsupported reset level: %d",
6329 val = hns3_read_dev(hw, reg);
6330 if (hns3_get_bit(val, reg_bit))
6337 hns3_is_reset_pending(struct hns3_adapter *hns)
6339 struct hns3_hw *hw = &hns->hw;
6340 enum hns3_reset_level reset;
6342 hns3_check_event_cause(hns, NULL);
6343 reset = hns3_get_reset_level(hns, &hw->reset.pending);
6344 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6345 hw->reset.level < reset) {
6346 hns3_warn(hw, "High level reset %d is pending", reset);
6349 reset = hns3_get_reset_level(hns, &hw->reset.request);
6350 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6351 hw->reset.level < reset) {
6352 hns3_warn(hw, "High level reset %d is request", reset);
6359 hns3_wait_hardware_ready(struct hns3_adapter *hns)
6361 struct hns3_hw *hw = &hns->hw;
6362 struct hns3_wait_data *wait_data = hw->reset.wait_data;
6365 if (wait_data->result == HNS3_WAIT_SUCCESS)
6367 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
6368 hns3_clock_gettime(&tv);
6369 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
6370 tv.tv_sec, tv.tv_usec);
6372 } else if (wait_data->result == HNS3_WAIT_REQUEST)
6375 wait_data->hns = hns;
6376 wait_data->check_completion = is_pf_reset_done;
6377 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
6378 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms();
6379 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
6380 wait_data->count = HNS3_RESET_WAIT_CNT;
6381 wait_data->result = HNS3_WAIT_REQUEST;
6382 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
6387 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
6389 struct hns3_cmd_desc desc;
6390 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6392 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6393 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6394 req->fun_reset_vfid = func_id;
6396 return hns3_cmd_send(hw, &desc, 1);
6400 hns3_imp_reset_cmd(struct hns3_hw *hw)
6402 struct hns3_cmd_desc desc;
6404 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6405 desc.data[0] = 0xeedd;
6407 return hns3_cmd_send(hw, &desc, 1);
6411 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6413 struct hns3_hw *hw = &hns->hw;
6417 hns3_clock_gettime(&tv);
6418 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6419 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6420 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6421 tv.tv_sec, tv.tv_usec);
6425 switch (reset_level) {
6426 case HNS3_IMP_RESET:
6427 hns3_imp_reset_cmd(hw);
6428 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6429 tv.tv_sec, tv.tv_usec);
6431 case HNS3_GLOBAL_RESET:
6432 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6433 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6434 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6435 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6436 tv.tv_sec, tv.tv_usec);
6438 case HNS3_FUNC_RESET:
6439 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6440 tv.tv_sec, tv.tv_usec);
6441 /* schedule again to check later */
6442 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6443 hns3_schedule_reset(hns);
6446 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6449 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6452 static enum hns3_reset_level
6453 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6455 struct hns3_hw *hw = &hns->hw;
6456 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6458 /* Return the highest priority reset level amongst all */
6459 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6460 reset_level = HNS3_IMP_RESET;
6461 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6462 reset_level = HNS3_GLOBAL_RESET;
6463 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6464 reset_level = HNS3_FUNC_RESET;
6465 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6466 reset_level = HNS3_FLR_RESET;
6468 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6469 return HNS3_NONE_RESET;
6475 hns3_record_imp_error(struct hns3_adapter *hns)
6477 struct hns3_hw *hw = &hns->hw;
6480 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6481 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6482 hns3_warn(hw, "Detected IMP RD poison!");
6483 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6484 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6487 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6488 hns3_warn(hw, "Detected IMP CMDQ error!");
6489 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6490 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6495 hns3_prepare_reset(struct hns3_adapter *hns)
6497 struct hns3_hw *hw = &hns->hw;
6501 switch (hw->reset.level) {
6502 case HNS3_FUNC_RESET:
6503 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6508 * After performaning pf reset, it is not necessary to do the
6509 * mailbox handling or send any command to firmware, because
6510 * any mailbox handling or command to firmware is only valid
6511 * after hns3_cmd_init is called.
6513 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6514 hw->reset.stats.request_cnt++;
6516 case HNS3_IMP_RESET:
6517 hns3_record_imp_error(hns);
6518 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6519 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6520 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6529 hns3_set_rst_done(struct hns3_hw *hw)
6531 struct hns3_pf_rst_done_cmd *req;
6532 struct hns3_cmd_desc desc;
6534 req = (struct hns3_pf_rst_done_cmd *)desc.data;
6535 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6536 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6537 return hns3_cmd_send(hw, &desc, 1);
6541 hns3_stop_service(struct hns3_adapter *hns)
6543 struct hns3_hw *hw = &hns->hw;
6544 struct rte_eth_dev *eth_dev;
6546 eth_dev = &rte_eth_devices[hw->data->port_id];
6547 hw->mac.link_status = RTE_ETH_LINK_DOWN;
6548 if (hw->adapter_state == HNS3_NIC_STARTED) {
6549 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6550 hns3_update_linkstatus_and_event(hw, false);
6553 hns3_set_rxtx_function(eth_dev);
6555 /* Disable datapath on secondary process. */
6556 hns3_mp_req_stop_rxtx(eth_dev);
6557 rte_delay_ms(hw->cfg_max_queues);
6559 rte_spinlock_lock(&hw->lock);
6560 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6561 hw->adapter_state == HNS3_NIC_STOPPING) {
6562 hns3_enable_all_queues(hw, false);
6564 hw->reset.mbuf_deferred_free = true;
6566 hw->reset.mbuf_deferred_free = false;
6569 * It is cumbersome for hardware to pick-and-choose entries for deletion
6570 * from table space. Hence, for function reset software intervention is
6571 * required to delete the entries
6573 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6574 hns3_configure_all_mc_mac_addr(hns, true);
6575 rte_spinlock_unlock(&hw->lock);
6581 hns3_start_service(struct hns3_adapter *hns)
6583 struct hns3_hw *hw = &hns->hw;
6584 struct rte_eth_dev *eth_dev;
6586 if (hw->reset.level == HNS3_IMP_RESET ||
6587 hw->reset.level == HNS3_GLOBAL_RESET)
6588 hns3_set_rst_done(hw);
6589 eth_dev = &rte_eth_devices[hw->data->port_id];
6590 hns3_set_rxtx_function(eth_dev);
6591 hns3_mp_req_start_rxtx(eth_dev);
6592 if (hw->adapter_state == HNS3_NIC_STARTED) {
6594 * This API parent function already hold the hns3_hw.lock, the
6595 * hns3_service_handler may report lse, in bonding application
6596 * it will call driver's ops which may acquire the hns3_hw.lock
6597 * again, thus lead to deadlock.
6598 * We defer calls hns3_service_handler to avoid the deadlock.
6600 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6601 hns3_service_handler, eth_dev);
6603 /* Enable interrupt of all rx queues before enabling queues */
6604 hns3_dev_all_rx_queue_intr_enable(hw, true);
6606 * Enable state of each rxq and txq will be recovered after
6607 * reset, so we need to restore them before enable all tqps;
6609 hns3_restore_tqp_enable_state(hw);
6611 * When finished the initialization, enable queues to receive
6612 * and transmit packets.
6614 hns3_enable_all_queues(hw, true);
6621 hns3_restore_conf(struct hns3_adapter *hns)
6623 struct hns3_hw *hw = &hns->hw;
6626 ret = hns3_configure_all_mac_addr(hns, false);
6630 ret = hns3_configure_all_mc_mac_addr(hns, false);
6634 ret = hns3_dev_promisc_restore(hns);
6638 ret = hns3_restore_vlan_table(hns);
6642 ret = hns3_restore_vlan_conf(hns);
6646 ret = hns3_restore_all_fdir_filter(hns);
6650 ret = hns3_restore_ptp(hns);
6654 ret = hns3_restore_rx_interrupt(hw);
6658 ret = hns3_restore_gro_conf(hw);
6662 ret = hns3_restore_fec(hw);
6666 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6667 ret = hns3_do_start(hns, false);
6670 hns3_info(hw, "hns3 dev restart successful!");
6671 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6672 hw->adapter_state = HNS3_NIC_CONFIGURED;
6676 hns3_configure_all_mc_mac_addr(hns, true);
6678 hns3_configure_all_mac_addr(hns, true);
6683 hns3_reset_service(void *param)
6685 struct hns3_adapter *hns = (struct hns3_adapter *)param;
6686 struct hns3_hw *hw = &hns->hw;
6687 enum hns3_reset_level reset_level;
6688 struct timeval tv_delta;
6689 struct timeval tv_start;
6695 * The interrupt is not triggered within the delay time.
6696 * The interrupt may have been lost. It is necessary to handle
6697 * the interrupt to recover from the error.
6699 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6700 SCHEDULE_DEFERRED) {
6701 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6703 hns3_err(hw, "Handling interrupts in delayed tasks");
6704 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6705 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6706 if (reset_level == HNS3_NONE_RESET) {
6707 hns3_err(hw, "No reset level is set, try IMP reset");
6708 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6711 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6714 * Check if there is any ongoing reset in the hardware. This status can
6715 * be checked from reset_pending. If there is then, we need to wait for
6716 * hardware to complete reset.
6717 * a. If we are able to figure out in reasonable time that hardware
6718 * has fully resetted then, we can proceed with driver, client
6720 * b. else, we can come back later to check this status so re-sched
6723 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6724 if (reset_level != HNS3_NONE_RESET) {
6725 hns3_clock_gettime(&tv_start);
6726 ret = hns3_reset_process(hns, reset_level);
6727 hns3_clock_gettime(&tv);
6728 timersub(&tv, &tv_start, &tv_delta);
6729 msec = hns3_clock_calctime_ms(&tv_delta);
6730 if (msec > HNS3_RESET_PROCESS_MS)
6731 hns3_err(hw, "%d handle long time delta %" PRIu64
6732 " ms time=%ld.%.6ld",
6733 hw->reset.level, msec,
6734 tv.tv_sec, tv.tv_usec);
6739 /* Check if we got any *new* reset requests to be honored */
6740 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6741 if (reset_level != HNS3_NONE_RESET)
6742 hns3_msix_process(hns, reset_level);
6746 hns3_get_speed_capa_num(uint16_t device_id)
6750 switch (device_id) {
6751 case HNS3_DEV_ID_25GE:
6752 case HNS3_DEV_ID_25GE_RDMA:
6755 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6756 case HNS3_DEV_ID_200G_RDMA:
6768 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6771 switch (device_id) {
6772 case HNS3_DEV_ID_25GE:
6774 case HNS3_DEV_ID_25GE_RDMA:
6775 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6776 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6778 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6779 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6780 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6782 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6783 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6784 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6786 case HNS3_DEV_ID_200G_RDMA:
6787 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6788 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6798 hns3_fec_get_capability(struct rte_eth_dev *dev,
6799 struct rte_eth_fec_capa *speed_fec_capa,
6802 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6803 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6804 uint16_t device_id = pci_dev->id.device_id;
6805 unsigned int capa_num;
6808 capa_num = hns3_get_speed_capa_num(device_id);
6809 if (capa_num == 0) {
6810 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6815 if (speed_fec_capa == NULL || num < capa_num)
6818 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6826 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6828 struct hns3_config_fec_cmd *req;
6829 struct hns3_cmd_desc desc;
6833 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6834 * in device of link speed
6837 if (hw->mac.link_speed < RTE_ETH_SPEED_NUM_10G) {
6842 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6843 req = (struct hns3_config_fec_cmd *)desc.data;
6844 ret = hns3_cmd_send(hw, &desc, 1);
6846 hns3_err(hw, "get current fec auto state failed, ret = %d",
6851 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6856 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6858 struct hns3_sfp_info_cmd *resp;
6859 uint32_t tmp_fec_capa;
6861 struct hns3_cmd_desc desc;
6865 * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6866 * configured FEC mode is returned.
6867 * If link is up, current FEC mode is returned.
6869 if (hw->mac.link_status == RTE_ETH_LINK_DOWN) {
6870 ret = get_current_fec_auto_state(hw, &auto_state);
6874 if (auto_state == 0x1) {
6875 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6880 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6881 resp = (struct hns3_sfp_info_cmd *)desc.data;
6882 resp->query_type = HNS3_ACTIVE_QUERY;
6884 ret = hns3_cmd_send(hw, &desc, 1);
6885 if (ret == -EOPNOTSUPP) {
6886 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6889 hns3_err(hw, "get FEC failed, ret = %d", ret);
6894 * FEC mode order defined in hns3 hardware is inconsistend with
6895 * that defined in the ethdev library. So the sequence needs
6898 switch (resp->active_fec) {
6899 case HNS3_HW_FEC_MODE_NOFEC:
6900 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6902 case HNS3_HW_FEC_MODE_BASER:
6903 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6905 case HNS3_HW_FEC_MODE_RS:
6906 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6909 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6913 *fec_capa = tmp_fec_capa;
6918 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6920 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6922 return hns3_fec_get_internal(hw, fec_capa);
6926 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6928 struct hns3_config_fec_cmd *req;
6929 struct hns3_cmd_desc desc;
6932 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6934 req = (struct hns3_config_fec_cmd *)desc.data;
6936 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6937 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6938 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6940 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6941 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6942 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6944 case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6945 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6946 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6948 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6949 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6954 ret = hns3_cmd_send(hw, &desc, 1);
6956 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6962 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6964 struct hns3_mac *mac = &hw->mac;
6967 switch (mac->link_speed) {
6968 case RTE_ETH_SPEED_NUM_10G:
6969 cur_capa = fec_capa[1].capa;
6971 case RTE_ETH_SPEED_NUM_25G:
6972 case RTE_ETH_SPEED_NUM_100G:
6973 case RTE_ETH_SPEED_NUM_200G:
6974 cur_capa = fec_capa[0].capa;
6985 is_fec_mode_one_bit_set(uint32_t mode)
6990 for (i = 0; i < sizeof(mode); i++)
6991 if (mode >> i & 0x1)
6994 return cnt == 1 ? true : false;
6998 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
7000 #define FEC_CAPA_NUM 2
7001 struct hns3_adapter *hns = dev->data->dev_private;
7002 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7003 struct hns3_pf *pf = &hns->pf;
7005 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
7007 uint32_t num = FEC_CAPA_NUM;
7010 ret = hns3_fec_get_capability(dev, fec_capa, num);
7014 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
7015 if (!is_fec_mode_one_bit_set(mode)) {
7016 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, "
7017 "FEC mode should be only one bit set", mode);
7022 * Check whether the configured mode is within the FEC capability.
7023 * If not, the configured mode will not be supported.
7025 cur_capa = get_current_speed_fec_cap(hw, fec_capa);
7026 if (!(cur_capa & mode)) {
7027 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
7031 rte_spinlock_lock(&hw->lock);
7032 ret = hns3_set_fec_hw(hw, mode);
7034 rte_spinlock_unlock(&hw->lock);
7038 pf->fec_mode = mode;
7039 rte_spinlock_unlock(&hw->lock);
7045 hns3_restore_fec(struct hns3_hw *hw)
7047 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7048 struct hns3_pf *pf = &hns->pf;
7049 uint32_t mode = pf->fec_mode;
7052 ret = hns3_set_fec_hw(hw, mode);
7054 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
7061 hns3_query_dev_fec_info(struct hns3_hw *hw)
7063 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7064 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
7067 ret = hns3_fec_get_internal(hw, &pf->fec_mode);
7069 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
7075 hns3_optical_module_existed(struct hns3_hw *hw)
7077 struct hns3_cmd_desc desc;
7081 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
7082 ret = hns3_cmd_send(hw, &desc, 1);
7085 "fail to get optical module exist state, ret = %d.\n",
7089 existed = !!desc.data[0];
7095 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
7096 uint32_t len, uint8_t *data)
7098 #define HNS3_SFP_INFO_CMD_NUM 6
7099 #define HNS3_SFP_INFO_MAX_LEN \
7100 (HNS3_SFP_INFO_BD0_LEN + \
7101 (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
7102 struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
7103 struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
7109 for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7110 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
7112 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
7113 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
7116 sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
7117 sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
7118 read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
7119 sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
7121 ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
7123 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
7128 /* The data format in BD0 is different with the others. */
7129 copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
7130 memcpy(data, sfp_info_bd0->data, copy_len);
7131 read_len = copy_len;
7133 for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7134 if (read_len >= len)
7137 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
7138 memcpy(data + read_len, desc[i].data, copy_len);
7139 read_len += copy_len;
7142 return (int)read_len;
7146 hns3_get_module_eeprom(struct rte_eth_dev *dev,
7147 struct rte_dev_eeprom_info *info)
7149 struct hns3_adapter *hns = dev->data->dev_private;
7150 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7151 uint32_t offset = info->offset;
7152 uint32_t len = info->length;
7153 uint8_t *data = info->data;
7154 uint32_t read_len = 0;
7156 if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
7159 if (!hns3_optical_module_existed(hw)) {
7160 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
7164 while (read_len < len) {
7166 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
7178 hns3_get_module_info(struct rte_eth_dev *dev,
7179 struct rte_eth_dev_module_info *modinfo)
7181 #define HNS3_SFF8024_ID_SFP 0x03
7182 #define HNS3_SFF8024_ID_QSFP_8438 0x0c
7183 #define HNS3_SFF8024_ID_QSFP_8436_8636 0x0d
7184 #define HNS3_SFF8024_ID_QSFP28_8636 0x11
7185 #define HNS3_SFF_8636_V1_3 0x03
7186 struct hns3_adapter *hns = dev->data->dev_private;
7187 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7188 struct rte_dev_eeprom_info info;
7189 struct hns3_sfp_type sfp_type;
7192 memset(&sfp_type, 0, sizeof(sfp_type));
7193 memset(&info, 0, sizeof(info));
7194 info.data = (uint8_t *)&sfp_type;
7195 info.length = sizeof(sfp_type);
7196 ret = hns3_get_module_eeprom(dev, &info);
7200 switch (sfp_type.type) {
7201 case HNS3_SFF8024_ID_SFP:
7202 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7203 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7205 case HNS3_SFF8024_ID_QSFP_8438:
7206 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7207 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7209 case HNS3_SFF8024_ID_QSFP_8436_8636:
7210 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
7211 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7212 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7214 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7215 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7218 case HNS3_SFF8024_ID_QSFP28_8636:
7219 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7220 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7223 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
7224 sfp_type.type, sfp_type.ext_type);
7232 hns3_clock_gettime(struct timeval *tv)
7234 #ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */
7235 #define CLOCK_TYPE CLOCK_MONOTONIC_RAW
7237 #define CLOCK_TYPE CLOCK_MONOTONIC
7239 #define NSEC_TO_USEC_DIV 1000
7241 struct timespec spec;
7242 (void)clock_gettime(CLOCK_TYPE, &spec);
7244 tv->tv_sec = spec.tv_sec;
7245 tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV;
7249 hns3_clock_calctime_ms(struct timeval *tv)
7251 return (uint64_t)tv->tv_sec * MSEC_PER_SEC +
7252 tv->tv_usec / USEC_PER_MSEC;
7256 hns3_clock_gettime_ms(void)
7260 hns3_clock_gettime(&tv);
7261 return hns3_clock_calctime_ms(&tv);
7265 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
7267 uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
7271 if (strcmp(value, "vec") == 0)
7272 hint = HNS3_IO_FUNC_HINT_VEC;
7273 else if (strcmp(value, "sve") == 0)
7274 hint = HNS3_IO_FUNC_HINT_SVE;
7275 else if (strcmp(value, "simple") == 0)
7276 hint = HNS3_IO_FUNC_HINT_SIMPLE;
7277 else if (strcmp(value, "common") == 0)
7278 hint = HNS3_IO_FUNC_HINT_COMMON;
7280 /* If the hint is valid then update output parameters */
7281 if (hint != HNS3_IO_FUNC_HINT_NONE)
7282 *(uint32_t *)extra_args = hint;
7288 hns3_get_io_hint_func_name(uint32_t hint)
7291 case HNS3_IO_FUNC_HINT_VEC:
7293 case HNS3_IO_FUNC_HINT_SVE:
7295 case HNS3_IO_FUNC_HINT_SIMPLE:
7297 case HNS3_IO_FUNC_HINT_COMMON:
7305 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args)
7311 val = strtoull(value, NULL, 16);
7312 *(uint64_t *)extra_args = val;
7318 hns3_parse_mbx_time_limit(const char *key, const char *value, void *extra_args)
7324 val = strtoul(value, NULL, 10);
7327 * 500ms is empirical value in process of mailbox communication. If
7328 * the delay value is set to one lower thanthe empirical value, mailbox
7329 * communication may fail.
7331 if (val > HNS3_MBX_DEF_TIME_LIMIT_MS && val <= UINT16_MAX)
7332 *(uint16_t *)extra_args = val;
7338 hns3_parse_devargs(struct rte_eth_dev *dev)
7340 uint16_t mbx_time_limit_ms = HNS3_MBX_DEF_TIME_LIMIT_MS;
7341 struct hns3_adapter *hns = dev->data->dev_private;
7342 uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7343 uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7344 struct hns3_hw *hw = &hns->hw;
7345 uint64_t dev_caps_mask = 0;
7346 struct rte_kvargs *kvlist;
7348 if (dev->device->devargs == NULL)
7351 kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
7355 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
7356 &hns3_parse_io_hint_func, &rx_func_hint);
7357 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
7358 &hns3_parse_io_hint_func, &tx_func_hint);
7359 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK,
7360 &hns3_parse_dev_caps_mask, &dev_caps_mask);
7361 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_MBX_TIME_LIMIT_MS,
7362 &hns3_parse_mbx_time_limit, &mbx_time_limit_ms);
7364 rte_kvargs_free(kvlist);
7366 if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7367 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
7368 hns3_get_io_hint_func_name(rx_func_hint));
7369 hns->rx_func_hint = rx_func_hint;
7370 if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7371 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
7372 hns3_get_io_hint_func_name(tx_func_hint));
7373 hns->tx_func_hint = tx_func_hint;
7375 if (dev_caps_mask != 0)
7376 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".",
7377 HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask);
7378 hns->dev_caps_mask = dev_caps_mask;
7380 if (mbx_time_limit_ms != HNS3_MBX_DEF_TIME_LIMIT_MS)
7381 hns3_warn(hw, "parsed %s = %u.", HNS3_DEVARG_MBX_TIME_LIMIT_MS,
7383 hns->mbx_time_limit_ms = mbx_time_limit_ms;
7386 static const struct eth_dev_ops hns3_eth_dev_ops = {
7387 .dev_configure = hns3_dev_configure,
7388 .dev_start = hns3_dev_start,
7389 .dev_stop = hns3_dev_stop,
7390 .dev_close = hns3_dev_close,
7391 .promiscuous_enable = hns3_dev_promiscuous_enable,
7392 .promiscuous_disable = hns3_dev_promiscuous_disable,
7393 .allmulticast_enable = hns3_dev_allmulticast_enable,
7394 .allmulticast_disable = hns3_dev_allmulticast_disable,
7395 .mtu_set = hns3_dev_mtu_set,
7396 .stats_get = hns3_stats_get,
7397 .stats_reset = hns3_stats_reset,
7398 .xstats_get = hns3_dev_xstats_get,
7399 .xstats_get_names = hns3_dev_xstats_get_names,
7400 .xstats_reset = hns3_dev_xstats_reset,
7401 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
7402 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
7403 .dev_infos_get = hns3_dev_infos_get,
7404 .fw_version_get = hns3_fw_version_get,
7405 .rx_queue_setup = hns3_rx_queue_setup,
7406 .tx_queue_setup = hns3_tx_queue_setup,
7407 .rx_queue_release = hns3_dev_rx_queue_release,
7408 .tx_queue_release = hns3_dev_tx_queue_release,
7409 .rx_queue_start = hns3_dev_rx_queue_start,
7410 .rx_queue_stop = hns3_dev_rx_queue_stop,
7411 .tx_queue_start = hns3_dev_tx_queue_start,
7412 .tx_queue_stop = hns3_dev_tx_queue_stop,
7413 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
7414 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
7415 .rxq_info_get = hns3_rxq_info_get,
7416 .txq_info_get = hns3_txq_info_get,
7417 .rx_burst_mode_get = hns3_rx_burst_mode_get,
7418 .tx_burst_mode_get = hns3_tx_burst_mode_get,
7419 .flow_ctrl_get = hns3_flow_ctrl_get,
7420 .flow_ctrl_set = hns3_flow_ctrl_set,
7421 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
7422 .mac_addr_add = hns3_add_mac_addr,
7423 .mac_addr_remove = hns3_remove_mac_addr,
7424 .mac_addr_set = hns3_set_default_mac_addr,
7425 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
7426 .link_update = hns3_dev_link_update,
7427 .dev_set_link_up = hns3_dev_set_link_up,
7428 .dev_set_link_down = hns3_dev_set_link_down,
7429 .rss_hash_update = hns3_dev_rss_hash_update,
7430 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
7431 .reta_update = hns3_dev_rss_reta_update,
7432 .reta_query = hns3_dev_rss_reta_query,
7433 .flow_ops_get = hns3_dev_flow_ops_get,
7434 .vlan_filter_set = hns3_vlan_filter_set,
7435 .vlan_tpid_set = hns3_vlan_tpid_set,
7436 .vlan_offload_set = hns3_vlan_offload_set,
7437 .vlan_pvid_set = hns3_vlan_pvid_set,
7438 .get_reg = hns3_get_regs,
7439 .get_module_info = hns3_get_module_info,
7440 .get_module_eeprom = hns3_get_module_eeprom,
7441 .get_dcb_info = hns3_get_dcb_info,
7442 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
7443 .fec_get_capability = hns3_fec_get_capability,
7444 .fec_get = hns3_fec_get,
7445 .fec_set = hns3_fec_set,
7446 .tm_ops_get = hns3_tm_ops_get,
7447 .tx_done_cleanup = hns3_tx_done_cleanup,
7448 .timesync_enable = hns3_timesync_enable,
7449 .timesync_disable = hns3_timesync_disable,
7450 .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
7451 .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
7452 .timesync_adjust_time = hns3_timesync_adjust_time,
7453 .timesync_read_time = hns3_timesync_read_time,
7454 .timesync_write_time = hns3_timesync_write_time,
7457 static const struct hns3_reset_ops hns3_reset_ops = {
7458 .reset_service = hns3_reset_service,
7459 .stop_service = hns3_stop_service,
7460 .prepare_reset = hns3_prepare_reset,
7461 .wait_hardware_ready = hns3_wait_hardware_ready,
7462 .reinit_dev = hns3_reinit_dev,
7463 .restore_conf = hns3_restore_conf,
7464 .start_service = hns3_start_service,
7468 hns3_dev_init(struct rte_eth_dev *eth_dev)
7470 struct hns3_adapter *hns = eth_dev->data->dev_private;
7471 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
7472 struct rte_ether_addr *eth_addr;
7473 struct hns3_hw *hw = &hns->hw;
7476 PMD_INIT_FUNC_TRACE();
7478 hns3_flow_init(eth_dev);
7480 hns3_set_rxtx_function(eth_dev);
7481 eth_dev->dev_ops = &hns3_eth_dev_ops;
7482 eth_dev->rx_queue_count = hns3_rx_queue_count;
7483 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7484 ret = hns3_mp_init_secondary();
7486 PMD_INIT_LOG(ERR, "Failed to init for secondary "
7487 "process, ret = %d", ret);
7488 goto err_mp_init_secondary;
7490 hw->secondary_cnt++;
7491 hns3_tx_push_init(eth_dev);
7495 ret = hns3_mp_init_primary();
7498 "Failed to init for primary process, ret = %d",
7500 goto err_mp_init_primary;
7503 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
7505 hw->data = eth_dev->data;
7506 hns3_parse_devargs(eth_dev);
7509 * Set default max packet size according to the mtu
7510 * default vale in DPDK frame.
7512 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
7514 ret = hns3_reset_init(hw);
7516 goto err_init_reset;
7517 hw->reset.ops = &hns3_reset_ops;
7519 ret = hns3_init_pf(eth_dev);
7521 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
7525 /* Allocate memory for storing MAC addresses */
7526 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
7527 sizeof(struct rte_ether_addr) *
7528 HNS3_UC_MACADDR_NUM, 0);
7529 if (eth_dev->data->mac_addrs == NULL) {
7530 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
7531 "to store MAC addresses",
7532 sizeof(struct rte_ether_addr) *
7533 HNS3_UC_MACADDR_NUM);
7535 goto err_rte_zmalloc;
7538 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
7539 if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
7540 rte_eth_random_addr(hw->mac.mac_addr);
7541 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
7542 (struct rte_ether_addr *)hw->mac.mac_addr);
7543 hns3_warn(hw, "default mac_addr from firmware is an invalid "
7544 "unicast address, using random MAC address %s",
7547 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7548 ð_dev->data->mac_addrs[0]);
7550 hw->adapter_state = HNS3_NIC_INITIALIZED;
7552 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7554 hns3_err(hw, "Reschedule reset service after dev_init");
7555 hns3_schedule_reset(hns);
7557 /* IMP will wait ready flag before reset */
7558 hns3_notify_reset_ready(hw, false);
7561 hns3_info(hw, "hns3 dev initialization successful!");
7565 hns3_uninit_pf(eth_dev);
7568 rte_free(hw->reset.wait_data);
7571 hns3_mp_uninit_primary();
7573 err_mp_init_primary:
7574 err_mp_init_secondary:
7575 eth_dev->dev_ops = NULL;
7576 eth_dev->rx_pkt_burst = NULL;
7577 eth_dev->rx_descriptor_status = NULL;
7578 eth_dev->tx_pkt_burst = NULL;
7579 eth_dev->tx_pkt_prepare = NULL;
7580 eth_dev->tx_descriptor_status = NULL;
7585 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7587 struct hns3_adapter *hns = eth_dev->data->dev_private;
7588 struct hns3_hw *hw = &hns->hw;
7590 PMD_INIT_FUNC_TRACE();
7592 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
7595 if (hw->adapter_state < HNS3_NIC_CLOSING)
7596 hns3_dev_close(eth_dev);
7598 hw->adapter_state = HNS3_NIC_REMOVED;
7603 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7604 struct rte_pci_device *pci_dev)
7606 return rte_eth_dev_pci_generic_probe(pci_dev,
7607 sizeof(struct hns3_adapter),
7612 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7614 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7617 static const struct rte_pci_id pci_id_hns3_map[] = {
7618 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7619 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7620 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7621 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7622 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7623 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7624 { .vendor_id = 0, }, /* sentinel */
7627 static struct rte_pci_driver rte_hns3_pmd = {
7628 .id_table = pci_id_hns3_map,
7629 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7630 .probe = eth_hns3_pci_probe,
7631 .remove = eth_hns3_pci_remove,
7634 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7635 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7636 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7637 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7638 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7639 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
7640 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
7641 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16> ");
7642 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE);
7643 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE);