drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9
  10 #include "hns3_ethdev.h"
  11 #include "hns3_logs.h"
  12 #include "hns3_rxtx.h"
  13 #include "hns3_intr.h"
  14 #include "hns3_regs.h"
  15 #include "hns3_dcb.h"
  16 #include "hns3_mp.h"
  17
  18 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  19 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  20
  21 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  22 #define HNS3_SERVICE_QUICK_INTERVAL     10
  23 #define HNS3_INVALID_PVID               0xFFFF
  24
  25 #define HNS3_FILTER_TYPE_VF             0
  26 #define HNS3_FILTER_TYPE_PORT           1
  27 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  28 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  29 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  30 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  31 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  32 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  33                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  34 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  35                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  36
  37 /* Reset related Registers */
  38 #define HNS3_GLOBAL_RESET_BIT           0
  39 #define HNS3_CORE_RESET_BIT             1
  40 #define HNS3_IMP_RESET_BIT              2
  41 #define HNS3_FUN_RST_ING_B              0
  42
  43 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  44 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  45 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  46 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  47
  48 #define HNS3_RESET_WAIT_MS      100
  49 #define HNS3_RESET_WAIT_CNT     200
  50
  51 /* FEC mode order defined in HNS3 hardware */
  52 #define HNS3_HW_FEC_MODE_NOFEC  0
  53 #define HNS3_HW_FEC_MODE_BASER  1
  54 #define HNS3_HW_FEC_MODE_RS     2
  55
  56 enum hns3_evt_cause {
  57         HNS3_VECTOR0_EVENT_RST,
  58         HNS3_VECTOR0_EVENT_MBX,
  59         HNS3_VECTOR0_EVENT_ERR,
  60         HNS3_VECTOR0_EVENT_OTHER,
  61 };
  62
  63 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  64         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  66                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  67
  68         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  72
  73         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  75                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  76
  77         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  81
  82         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  84                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  85
  86         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  88                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  89 };
  90
  91 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  92                                                  uint64_t *levels);
  93 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  94 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  95                                     int on);
  96 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  97 static bool hns3_update_link_status(struct hns3_hw *hw);
  98
  99 static int hns3_add_mc_addr(struct hns3_hw *hw,
 100                             struct rte_ether_addr *mac_addr);
 101 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 102                             struct rte_ether_addr *mac_addr);
 103 static int hns3_restore_fec(struct hns3_hw *hw);
 104 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 105
 106 void hns3_ether_format_addr(char *buf, uint16_t size,
 107                             const struct rte_ether_addr *ether_addr)
 108 {
 109         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 110                 ether_addr->addr_bytes[0],
 111                 ether_addr->addr_bytes[4],
 112                 ether_addr->addr_bytes[5]);
 113 }
 114
 115 static void
 116 hns3_pf_disable_irq0(struct hns3_hw *hw)
 117 {
 118         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 119 }
 120
 121 static void
 122 hns3_pf_enable_irq0(struct hns3_hw *hw)
 123 {
 124         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 125 }
 126
 127 static enum hns3_evt_cause
 128 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 129                           uint32_t *vec_val)
 130 {
 131         struct hns3_hw *hw = &hns->hw;
 132
 133         rte_atomic16_set(&hw->reset.disable_cmd, 1);
 134         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 135         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 136         if (!is_delay) {
 137                 hw->reset.stats.imp_cnt++;
 138                 hns3_warn(hw, "IMP reset detected, clear reset status");
 139         } else {
 140                 hns3_schedule_delayed_reset(hns);
 141                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 142         }
 143
 144         return HNS3_VECTOR0_EVENT_RST;
 145 }
 146
 147 static enum hns3_evt_cause
 148 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 149                              uint32_t *vec_val)
 150 {
 151         struct hns3_hw *hw = &hns->hw;
 152
 153         rte_atomic16_set(&hw->reset.disable_cmd, 1);
 154         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 155         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 156         if (!is_delay) {
 157                 hw->reset.stats.global_cnt++;
 158                 hns3_warn(hw, "Global reset detected, clear reset status");
 159         } else {
 160                 hns3_schedule_delayed_reset(hns);
 161                 hns3_warn(hw,
 162                           "Global reset detected, don't clear reset status");
 163         }
 164
 165         return HNS3_VECTOR0_EVENT_RST;
 166 }
 167
 168 static enum hns3_evt_cause
 169 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 170 {
 171         struct hns3_hw *hw = &hns->hw;
 172         uint32_t vector0_int_stats;
 173         uint32_t cmdq_src_val;
 174         uint32_t hw_err_src_reg;
 175         uint32_t val;
 176         enum hns3_evt_cause ret;
 177         bool is_delay;
 178
 179         /* fetch the events from their corresponding regs */
 180         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 181         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 182         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 183
 184         is_delay = clearval == NULL ? true : false;
 185         /*
 186          * Assumption: If by any chance reset and mailbox events are reported
 187          * together then we will only process reset event and defer the
 188          * processing of the mailbox events. Since, we would have not cleared
 189          * RX CMDQ event this time we would receive again another interrupt
 190          * from H/W just for the mailbox.
 191          */
 192         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 193                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 194                 goto out;
 195         }
 196
 197         /* Global reset */
 198         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 199                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 200                 goto out;
 201         }
 202
 203         /* check for vector0 msix event source */
 204         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 205             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 206                 val = vector0_int_stats | hw_err_src_reg;
 207                 ret = HNS3_VECTOR0_EVENT_ERR;
 208                 goto out;
 209         }
 210
 211         /* check for vector0 mailbox(=CMDQ RX) event source */
 212         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 213                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 214                 val = cmdq_src_val;
 215                 ret = HNS3_VECTOR0_EVENT_MBX;
 216                 goto out;
 217         }
 218
 219         if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
 220                 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
 221                           vector0_int_stats, cmdq_src_val, hw_err_src_reg);
 222         val = vector0_int_stats;
 223         ret = HNS3_VECTOR0_EVENT_OTHER;
 224 out:
 225
 226         if (clearval)
 227                 *clearval = val;
 228         return ret;
 229 }
 230
 231 static void
 232 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 233 {
 234         if (event_type == HNS3_VECTOR0_EVENT_RST)
 235                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 236         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 237                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 238 }
 239
 240 static void
 241 hns3_clear_all_event_cause(struct hns3_hw *hw)
 242 {
 243         uint32_t vector0_int_stats;
 244         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 245
 246         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 247                 hns3_warn(hw, "Probe during IMP reset interrupt");
 248
 249         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 250                 hns3_warn(hw, "Probe during Global reset interrupt");
 251
 252         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 253                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 254                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 255                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 256         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 257 }
 258
 259 static void
 260 hns3_interrupt_handler(void *param)
 261 {
 262         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 263         struct hns3_adapter *hns = dev->data->dev_private;
 264         struct hns3_hw *hw = &hns->hw;
 265         enum hns3_evt_cause event_cause;
 266         uint32_t clearval = 0;
 267
 268         /* Disable interrupt */
 269         hns3_pf_disable_irq0(hw);
 270
 271         event_cause = hns3_check_event_cause(hns, &clearval);
 272         /* vector 0 interrupt is shared with reset and mailbox source events. */
 273         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 274                 hns3_warn(hw, "Received err interrupt");
 275                 hns3_handle_msix_error(hns, &hw->reset.request);
 276                 hns3_handle_ras_error(hns, &hw->reset.request);
 277                 hns3_schedule_reset(hns);
 278         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 279                 hns3_warn(hw, "Received reset interrupt");
 280                 hns3_schedule_reset(hns);
 281         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 282                 hns3_dev_handle_mbx_msg(hw);
 283         else
 284                 hns3_err(hw, "Received unknown event");
 285
 286         hns3_clear_event_cause(hw, event_cause, clearval);
 287         /* Enable interrupt if it is not cause by reset */
 288         hns3_pf_enable_irq0(hw);
 289 }
 290
 291 static int
 292 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 293 {
 294 #define HNS3_VLAN_ID_OFFSET_STEP        160
 295 #define HNS3_VLAN_BYTE_SIZE             8
 296         struct hns3_vlan_filter_pf_cfg_cmd *req;
 297         struct hns3_hw *hw = &hns->hw;
 298         uint8_t vlan_offset_byte_val;
 299         struct hns3_cmd_desc desc;
 300         uint8_t vlan_offset_byte;
 301         uint8_t vlan_offset_base;
 302         int ret;
 303
 304         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 305
 306         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 307         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 308                            HNS3_VLAN_BYTE_SIZE;
 309         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 310
 311         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 312         req->vlan_offset = vlan_offset_base;
 313         req->vlan_cfg = on ? 0 : 1;
 314         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 315
 316         ret = hns3_cmd_send(hw, &desc, 1);
 317         if (ret)
 318                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 319                          vlan_id, ret);
 320
 321         return ret;
 322 }
 323
 324 static void
 325 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 326 {
 327         struct hns3_user_vlan_table *vlan_entry;
 328         struct hns3_pf *pf = &hns->pf;
 329
 330         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 331                 if (vlan_entry->vlan_id == vlan_id) {
 332                         if (vlan_entry->hd_tbl_status)
 333                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 334                         LIST_REMOVE(vlan_entry, next);
 335                         rte_free(vlan_entry);
 336                         break;
 337                 }
 338         }
 339 }
 340
 341 static void
 342 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 343                         bool writen_to_tbl)
 344 {
 345         struct hns3_user_vlan_table *vlan_entry;
 346         struct hns3_hw *hw = &hns->hw;
 347         struct hns3_pf *pf = &hns->pf;
 348
 349         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 350                 if (vlan_entry->vlan_id == vlan_id)
 351                         return;
 352         }
 353
 354         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 355         if (vlan_entry == NULL) {
 356                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 357                 return;
 358         }
 359
 360         vlan_entry->hd_tbl_status = writen_to_tbl;
 361         vlan_entry->vlan_id = vlan_id;
 362
 363         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 364 }
 365
 366 static int
 367 hns3_restore_vlan_table(struct hns3_adapter *hns)
 368 {
 369         struct hns3_user_vlan_table *vlan_entry;
 370         struct hns3_hw *hw = &hns->hw;
 371         struct hns3_pf *pf = &hns->pf;
 372         uint16_t vlan_id;
 373         int ret = 0;
 374
 375         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 376                 return hns3_vlan_pvid_configure(hns,
 377                                                 hw->port_base_vlan_cfg.pvid, 1);
 378
 379         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 380                 if (vlan_entry->hd_tbl_status) {
 381                         vlan_id = vlan_entry->vlan_id;
 382                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 383                         if (ret)
 384                                 break;
 385                 }
 386         }
 387
 388         return ret;
 389 }
 390
 391 static int
 392 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 393 {
 394         struct hns3_hw *hw = &hns->hw;
 395         bool writen_to_tbl = false;
 396         int ret = 0;
 397
 398         /*
 399          * When vlan filter is enabled, hardware regards packets without vlan
 400          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 401          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 402          */
 403         if (on == 0 && vlan_id == 0)
 404                 return 0;
 405
 406         /*
 407          * When port base vlan enabled, we use port base vlan as the vlan
 408          * filter condition. In this case, we don't update vlan filter table
 409          * when user add new vlan or remove exist vlan, just update the
 410          * vlan list. The vlan id in vlan list will be writen in vlan filter
 411          * table until port base vlan disabled
 412          */
 413         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 414                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 415                 writen_to_tbl = true;
 416         }
 417
 418         if (ret == 0) {
 419                 if (on)
 420                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 421                 else
 422                         hns3_rm_dev_vlan_table(hns, vlan_id);
 423         }
 424         return ret;
 425 }
 426
 427 static int
 428 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 429 {
 430         struct hns3_adapter *hns = dev->data->dev_private;
 431         struct hns3_hw *hw = &hns->hw;
 432         int ret;
 433
 434         rte_spinlock_lock(&hw->lock);
 435         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 436         rte_spinlock_unlock(&hw->lock);
 437         return ret;
 438 }
 439
 440 static int
 441 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 442                          uint16_t tpid)
 443 {
 444         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 445         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 446         struct hns3_hw *hw = &hns->hw;
 447         struct hns3_cmd_desc desc;
 448         int ret;
 449
 450         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 451              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 452                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 453                 return -EINVAL;
 454         }
 455
 456         if (tpid != RTE_ETHER_TYPE_VLAN) {
 457                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 458                 return -EINVAL;
 459         }
 460
 461         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 462         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 463
 464         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 465                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 466                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 467         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 468                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 469                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 470                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 471                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 472         }
 473
 474         ret = hns3_cmd_send(hw, &desc, 1);
 475         if (ret) {
 476                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 477                          ret);
 478                 return ret;
 479         }
 480
 481         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 482
 483         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 484         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 485         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 486
 487         ret = hns3_cmd_send(hw, &desc, 1);
 488         if (ret)
 489                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 490                          ret);
 491         return ret;
 492 }
 493
 494 static int
 495 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 496                    uint16_t tpid)
 497 {
 498         struct hns3_adapter *hns = dev->data->dev_private;
 499         struct hns3_hw *hw = &hns->hw;
 500         int ret;
 501
 502         rte_spinlock_lock(&hw->lock);
 503         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 504         rte_spinlock_unlock(&hw->lock);
 505         return ret;
 506 }
 507
 508 static int
 509 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 510                              struct hns3_rx_vtag_cfg *vcfg)
 511 {
 512         struct hns3_vport_vtag_rx_cfg_cmd *req;
 513         struct hns3_hw *hw = &hns->hw;
 514         struct hns3_cmd_desc desc;
 515         uint16_t vport_id;
 516         uint8_t bitmap;
 517         int ret;
 518
 519         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 520
 521         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 522         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 523                      vcfg->strip_tag1_en ? 1 : 0);
 524         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 525                      vcfg->strip_tag2_en ? 1 : 0);
 526         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 527                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 528         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 529                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 530
 531         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 532         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 533                      vcfg->strip_tag1_discard_en ? 1 : 0);
 534         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 535                      vcfg->strip_tag2_discard_en ? 1 : 0);
 536         /*
 537          * In current version VF is not supported when PF is driven by DPDK
 538          * driver, just need to configure parameters for PF vport.
 539          */
 540         vport_id = HNS3_PF_FUNC_ID;
 541         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 542         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 543         req->vf_bitmap[req->vf_offset] = bitmap;
 544
 545         ret = hns3_cmd_send(hw, &desc, 1);
 546         if (ret)
 547                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 548         return ret;
 549 }
 550
 551 static void
 552 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 553                            struct hns3_rx_vtag_cfg *vcfg)
 554 {
 555         struct hns3_pf *pf = &hns->pf;
 556         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 557 }
 558
 559 static void
 560 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 561                            struct hns3_tx_vtag_cfg *vcfg)
 562 {
 563         struct hns3_pf *pf = &hns->pf;
 564         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 565 }
 566
 567 static int
 568 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 569 {
 570         struct hns3_rx_vtag_cfg rxvlan_cfg;
 571         struct hns3_hw *hw = &hns->hw;
 572         int ret;
 573
 574         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 575                 rxvlan_cfg.strip_tag1_en = false;
 576                 rxvlan_cfg.strip_tag2_en = enable;
 577                 rxvlan_cfg.strip_tag2_discard_en = false;
 578         } else {
 579                 rxvlan_cfg.strip_tag1_en = enable;
 580                 rxvlan_cfg.strip_tag2_en = true;
 581                 rxvlan_cfg.strip_tag2_discard_en = true;
 582         }
 583
 584         rxvlan_cfg.strip_tag1_discard_en = false;
 585         rxvlan_cfg.vlan1_vlan_prionly = false;
 586         rxvlan_cfg.vlan2_vlan_prionly = false;
 587         rxvlan_cfg.rx_vlan_offload_en = enable;
 588
 589         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 590         if (ret) {
 591                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 592                 return ret;
 593         }
 594
 595         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 596
 597         return ret;
 598 }
 599
 600 static int
 601 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 602                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 603 {
 604         struct hns3_vlan_filter_ctrl_cmd *req;
 605         struct hns3_cmd_desc desc;
 606         int ret;
 607
 608         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 609
 610         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 611         req->vlan_type = vlan_type;
 612         req->vlan_fe = filter_en ? fe_type : 0;
 613         req->vf_id = vf_id;
 614
 615         ret = hns3_cmd_send(hw, &desc, 1);
 616         if (ret)
 617                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 618
 619         return ret;
 620 }
 621
 622 static int
 623 hns3_vlan_filter_init(struct hns3_adapter *hns)
 624 {
 625         struct hns3_hw *hw = &hns->hw;
 626         int ret;
 627
 628         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 629                                         HNS3_FILTER_FE_EGRESS, false,
 630                                         HNS3_PF_FUNC_ID);
 631         if (ret) {
 632                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 633                 return ret;
 634         }
 635
 636         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 637                                         HNS3_FILTER_FE_INGRESS, false,
 638                                         HNS3_PF_FUNC_ID);
 639         if (ret)
 640                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 641
 642         return ret;
 643 }
 644
 645 static int
 646 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 647 {
 648         struct hns3_hw *hw = &hns->hw;
 649         int ret;
 650
 651         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 652                                         HNS3_FILTER_FE_INGRESS, enable,
 653                                         HNS3_PF_FUNC_ID);
 654         if (ret)
 655                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 656                          enable ? "enable" : "disable", ret);
 657
 658         return ret;
 659 }
 660
 661 static int
 662 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 663 {
 664         struct hns3_adapter *hns = dev->data->dev_private;
 665         struct hns3_hw *hw = &hns->hw;
 666         struct rte_eth_rxmode *rxmode;
 667         unsigned int tmp_mask;
 668         bool enable;
 669         int ret = 0;
 670
 671         rte_spinlock_lock(&hw->lock);
 672         rxmode = &dev->data->dev_conf.rxmode;
 673         tmp_mask = (unsigned int)mask;
 674         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 675                 /* ignore vlan filter configuration during promiscuous mode */
 676                 if (!dev->data->promiscuous) {
 677                         /* Enable or disable VLAN filter */
 678                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 679                                  true : false;
 680
 681                         ret = hns3_enable_vlan_filter(hns, enable);
 682                         if (ret) {
 683                                 rte_spinlock_unlock(&hw->lock);
 684                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 685                                          enable ? "enable" : "disable", ret);
 686                                 return ret;
 687                         }
 688                 }
 689         }
 690
 691         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 692                 /* Enable or disable VLAN stripping */
 693                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 694                     true : false;
 695
 696                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 697                 if (ret) {
 698                         rte_spinlock_unlock(&hw->lock);
 699                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 700                                  enable ? "enable" : "disable", ret);
 701                         return ret;
 702                 }
 703         }
 704
 705         rte_spinlock_unlock(&hw->lock);
 706
 707         return ret;
 708 }
 709
 710 static int
 711 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 712                              struct hns3_tx_vtag_cfg *vcfg)
 713 {
 714         struct hns3_vport_vtag_tx_cfg_cmd *req;
 715         struct hns3_cmd_desc desc;
 716         struct hns3_hw *hw = &hns->hw;
 717         uint16_t vport_id;
 718         uint8_t bitmap;
 719         int ret;
 720
 721         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 722
 723         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 724         req->def_vlan_tag1 = vcfg->default_tag1;
 725         req->def_vlan_tag2 = vcfg->default_tag2;
 726         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 727                      vcfg->accept_tag1 ? 1 : 0);
 728         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 729                      vcfg->accept_untag1 ? 1 : 0);
 730         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 731                      vcfg->accept_tag2 ? 1 : 0);
 732         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 733                      vcfg->accept_untag2 ? 1 : 0);
 734         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 735                      vcfg->insert_tag1_en ? 1 : 0);
 736         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 737                      vcfg->insert_tag2_en ? 1 : 0);
 738         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 739
 740         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 741         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 742                      vcfg->tag_shift_mode_en ? 1 : 0);
 743
 744         /*
 745          * In current version VF is not supported when PF is driven by DPDK
 746          * driver, just need to configure parameters for PF vport.
 747          */
 748         vport_id = HNS3_PF_FUNC_ID;
 749         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 750         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 751         req->vf_bitmap[req->vf_offset] = bitmap;
 752
 753         ret = hns3_cmd_send(hw, &desc, 1);
 754         if (ret)
 755                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 756
 757         return ret;
 758 }
 759
 760 static int
 761 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 762                      uint16_t pvid)
 763 {
 764         struct hns3_hw *hw = &hns->hw;
 765         struct hns3_tx_vtag_cfg txvlan_cfg;
 766         int ret;
 767
 768         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 769                 txvlan_cfg.accept_tag1 = true;
 770                 txvlan_cfg.insert_tag1_en = false;
 771                 txvlan_cfg.default_tag1 = 0;
 772         } else {
 773                 txvlan_cfg.accept_tag1 =
 774                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 775                 txvlan_cfg.insert_tag1_en = true;
 776                 txvlan_cfg.default_tag1 = pvid;
 777         }
 778
 779         txvlan_cfg.accept_untag1 = true;
 780         txvlan_cfg.accept_tag2 = true;
 781         txvlan_cfg.accept_untag2 = true;
 782         txvlan_cfg.insert_tag2_en = false;
 783         txvlan_cfg.default_tag2 = 0;
 784         txvlan_cfg.tag_shift_mode_en = true;
 785
 786         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 787         if (ret) {
 788                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 789                          ret);
 790                 return ret;
 791         }
 792
 793         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 794         return ret;
 795 }
 796
 797
 798 static void
 799 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 800 {
 801         struct hns3_user_vlan_table *vlan_entry;
 802         struct hns3_pf *pf = &hns->pf;
 803
 804         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 805                 if (vlan_entry->hd_tbl_status) {
 806                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 807                         vlan_entry->hd_tbl_status = false;
 808                 }
 809         }
 810
 811         if (is_del_list) {
 812                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 813                 while (vlan_entry) {
 814                         LIST_REMOVE(vlan_entry, next);
 815                         rte_free(vlan_entry);
 816                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 817                 }
 818         }
 819 }
 820
 821 static void
 822 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 823 {
 824         struct hns3_user_vlan_table *vlan_entry;
 825         struct hns3_pf *pf = &hns->pf;
 826
 827         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 828                 if (!vlan_entry->hd_tbl_status) {
 829                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 830                         vlan_entry->hd_tbl_status = true;
 831                 }
 832         }
 833 }
 834
 835 static void
 836 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 837 {
 838         struct hns3_hw *hw = &hns->hw;
 839         int ret;
 840
 841         hns3_rm_all_vlan_table(hns, true);
 842         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 843                 ret = hns3_set_port_vlan_filter(hns,
 844                                                 hw->port_base_vlan_cfg.pvid, 0);
 845                 if (ret) {
 846                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 847                                  ret);
 848                         return;
 849                 }
 850         }
 851 }
 852
 853 static int
 854 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 855                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 856 {
 857         struct hns3_hw *hw = &hns->hw;
 858         uint16_t old_pvid;
 859         int ret;
 860
 861         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 862                 old_pvid = hw->port_base_vlan_cfg.pvid;
 863                 if (old_pvid != HNS3_INVALID_PVID) {
 864                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 865                         if (ret) {
 866                                 hns3_err(hw, "failed to remove old pvid %u, "
 867                                                 "ret = %d", old_pvid, ret);
 868                                 return ret;
 869                         }
 870                 }
 871
 872                 hns3_rm_all_vlan_table(hns, false);
 873                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 874                 if (ret) {
 875                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 876                                         new_pvid, ret);
 877                         return ret;
 878                 }
 879         } else {
 880                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 881                 if (ret) {
 882                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 883                                         new_pvid, ret);
 884                         return ret;
 885                 }
 886
 887                 hns3_add_all_vlan_table(hns);
 888         }
 889         return 0;
 890 }
 891
 892 static int
 893 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 894 {
 895         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 896         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 897         bool rx_strip_en;
 898         int ret;
 899
 900         rx_strip_en = old_cfg->rx_vlan_offload_en;
 901         if (on) {
 902                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 903                 rx_vlan_cfg.strip_tag2_en = true;
 904                 rx_vlan_cfg.strip_tag2_discard_en = true;
 905         } else {
 906                 rx_vlan_cfg.strip_tag1_en = false;
 907                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 908                 rx_vlan_cfg.strip_tag2_discard_en = false;
 909         }
 910         rx_vlan_cfg.strip_tag1_discard_en = false;
 911         rx_vlan_cfg.vlan1_vlan_prionly = false;
 912         rx_vlan_cfg.vlan2_vlan_prionly = false;
 913         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 914
 915         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 916         if (ret)
 917                 return ret;
 918
 919         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 920         return ret;
 921 }
 922
 923 static int
 924 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 925 {
 926         struct hns3_hw *hw = &hns->hw;
 927         uint16_t port_base_vlan_state;
 928         int ret;
 929
 930         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 931                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 932                         hns3_warn(hw, "Invalid operation! As current pvid set "
 933                                   "is %u, disable pvid %u is invalid",
 934                                   hw->port_base_vlan_cfg.pvid, pvid);
 935                 return 0;
 936         }
 937
 938         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 939                                     HNS3_PORT_BASE_VLAN_DISABLE;
 940         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 941         if (ret) {
 942                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 943                          ret);
 944                 return ret;
 945         }
 946
 947         ret = hns3_en_pvid_strip(hns, on);
 948         if (ret) {
 949                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 950                          "ret = %d", ret);
 951                 return ret;
 952         }
 953
 954         if (pvid == HNS3_INVALID_PVID)
 955                 goto out;
 956         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 957         if (ret) {
 958                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 959                          ret);
 960                 return ret;
 961         }
 962
 963 out:
 964         hw->port_base_vlan_cfg.state = port_base_vlan_state;
 965         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
 966         return ret;
 967 }
 968
 969 static int
 970 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 971 {
 972         struct hns3_adapter *hns = dev->data->dev_private;
 973         struct hns3_hw *hw = &hns->hw;
 974         bool pvid_en_state_change;
 975         uint16_t pvid_state;
 976         int ret;
 977
 978         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 979                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 980                          RTE_ETHER_MAX_VLAN_ID);
 981                 return -EINVAL;
 982         }
 983
 984         /*
 985          * If PVID configuration state change, should refresh the PVID
 986          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
 987          */
 988         pvid_state = hw->port_base_vlan_cfg.state;
 989         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
 990             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
 991                 pvid_en_state_change = false;
 992         else
 993                 pvid_en_state_change = true;
 994
 995         rte_spinlock_lock(&hw->lock);
 996         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 997         rte_spinlock_unlock(&hw->lock);
 998         if (ret)
 999                 return ret;
1000         /*
1001          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1002          * need be processed by PMD driver.
1003          */
1004         if (pvid_en_state_change &&
1005             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1006                 hns3_update_all_queues_pvid_proc_en(hw);
1007
1008         return 0;
1009 }
1010
1011 static int
1012 hns3_default_vlan_config(struct hns3_adapter *hns)
1013 {
1014         struct hns3_hw *hw = &hns->hw;
1015         int ret;
1016
1017         /*
1018          * When vlan filter is enabled, hardware regards packets without vlan
1019          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1020          * table, packets without vlan won't be received. So, add vlan 0 as
1021          * the default vlan.
1022          */
1023         ret = hns3_vlan_filter_configure(hns, 0, 1);
1024         if (ret)
1025                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1026         return ret;
1027 }
1028
1029 static int
1030 hns3_init_vlan_config(struct hns3_adapter *hns)
1031 {
1032         struct hns3_hw *hw = &hns->hw;
1033         int ret;
1034
1035         /*
1036          * This function can be called in the initialization and reset process,
1037          * when in reset process, it means that hardware had been reseted
1038          * successfully and we need to restore the hardware configuration to
1039          * ensure that the hardware configuration remains unchanged before and
1040          * after reset.
1041          */
1042         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1043                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1044                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1045         }
1046
1047         ret = hns3_vlan_filter_init(hns);
1048         if (ret) {
1049                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1050                 return ret;
1051         }
1052
1053         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1054                                        RTE_ETHER_TYPE_VLAN);
1055         if (ret) {
1056                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1057                 return ret;
1058         }
1059
1060         /*
1061          * When in the reinit dev stage of the reset process, the following
1062          * vlan-related configurations may differ from those at initialization,
1063          * we will restore configurations to hardware in hns3_restore_vlan_table
1064          * and hns3_restore_vlan_conf later.
1065          */
1066         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1067                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1068                 if (ret) {
1069                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1070                         return ret;
1071                 }
1072
1073                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1074                 if (ret) {
1075                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1076                                  ret);
1077                         return ret;
1078                 }
1079         }
1080
1081         return hns3_default_vlan_config(hns);
1082 }
1083
1084 static int
1085 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1086 {
1087         struct hns3_pf *pf = &hns->pf;
1088         struct hns3_hw *hw = &hns->hw;
1089         uint64_t offloads;
1090         bool enable;
1091         int ret;
1092
1093         if (!hw->data->promiscuous) {
1094                 /* restore vlan filter states */
1095                 offloads = hw->data->dev_conf.rxmode.offloads;
1096                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1097                 ret = hns3_enable_vlan_filter(hns, enable);
1098                 if (ret) {
1099                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1100                                  "ret = %d", ret);
1101                         return ret;
1102                 }
1103         }
1104
1105         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1106         if (ret) {
1107                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1108                 return ret;
1109         }
1110
1111         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1112         if (ret)
1113                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1114
1115         return ret;
1116 }
1117
1118 static int
1119 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1120 {
1121         struct hns3_adapter *hns = dev->data->dev_private;
1122         struct rte_eth_dev_data *data = dev->data;
1123         struct rte_eth_txmode *txmode;
1124         struct hns3_hw *hw = &hns->hw;
1125         int mask;
1126         int ret;
1127
1128         txmode = &data->dev_conf.txmode;
1129         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1130                 hns3_warn(hw,
1131                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1132                           "configuration is not supported! Ignore these two "
1133                           "parameters: hw_vlan_reject_tagged(%u), "
1134                           "hw_vlan_reject_untagged(%u)",
1135                           txmode->hw_vlan_reject_tagged,
1136                           txmode->hw_vlan_reject_untagged);
1137
1138         /* Apply vlan offload setting */
1139         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1140         ret = hns3_vlan_offload_set(dev, mask);
1141         if (ret) {
1142                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1143                          ret);
1144                 return ret;
1145         }
1146
1147         /*
1148          * If pvid config is not set in rte_eth_conf, driver needn't to set
1149          * VLAN pvid related configuration to hardware.
1150          */
1151         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1152                 return 0;
1153
1154         /* Apply pvid setting */
1155         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1156                                  txmode->hw_vlan_insert_pvid);
1157         if (ret)
1158                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1159                          txmode->pvid, ret);
1160
1161         return ret;
1162 }
1163
1164 static int
1165 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1166                 unsigned int tso_mss_max)
1167 {
1168         struct hns3_cfg_tso_status_cmd *req;
1169         struct hns3_cmd_desc desc;
1170         uint16_t tso_mss;
1171
1172         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1173
1174         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1175
1176         tso_mss = 0;
1177         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1178                        tso_mss_min);
1179         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1180
1181         tso_mss = 0;
1182         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1183                        tso_mss_max);
1184         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1185
1186         return hns3_cmd_send(hw, &desc, 1);
1187 }
1188
1189 static int
1190 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1191                    uint16_t *allocated_size, bool is_alloc)
1192 {
1193         struct hns3_umv_spc_alc_cmd *req;
1194         struct hns3_cmd_desc desc;
1195         int ret;
1196
1197         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1198         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1199         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1200         req->space_size = rte_cpu_to_le_32(space_size);
1201
1202         ret = hns3_cmd_send(hw, &desc, 1);
1203         if (ret) {
1204                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1205                              is_alloc ? "allocate" : "free", ret);
1206                 return ret;
1207         }
1208
1209         if (is_alloc && allocated_size)
1210                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1211
1212         return 0;
1213 }
1214
1215 static int
1216 hns3_init_umv_space(struct hns3_hw *hw)
1217 {
1218         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1219         struct hns3_pf *pf = &hns->pf;
1220         uint16_t allocated_size = 0;
1221         int ret;
1222
1223         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1224                                  true);
1225         if (ret)
1226                 return ret;
1227
1228         if (allocated_size < pf->wanted_umv_size)
1229                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1230                              pf->wanted_umv_size, allocated_size);
1231
1232         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1233                                                 pf->wanted_umv_size;
1234         pf->used_umv_size = 0;
1235         return 0;
1236 }
1237
1238 static int
1239 hns3_uninit_umv_space(struct hns3_hw *hw)
1240 {
1241         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1242         struct hns3_pf *pf = &hns->pf;
1243         int ret;
1244
1245         if (pf->max_umv_size == 0)
1246                 return 0;
1247
1248         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1249         if (ret)
1250                 return ret;
1251
1252         pf->max_umv_size = 0;
1253
1254         return 0;
1255 }
1256
1257 static bool
1258 hns3_is_umv_space_full(struct hns3_hw *hw)
1259 {
1260         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1261         struct hns3_pf *pf = &hns->pf;
1262         bool is_full;
1263
1264         is_full = (pf->used_umv_size >= pf->max_umv_size);
1265
1266         return is_full;
1267 }
1268
1269 static void
1270 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1271 {
1272         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1273         struct hns3_pf *pf = &hns->pf;
1274
1275         if (is_free) {
1276                 if (pf->used_umv_size > 0)
1277                         pf->used_umv_size--;
1278         } else
1279                 pf->used_umv_size++;
1280 }
1281
1282 static void
1283 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1284                       const uint8_t *addr, bool is_mc)
1285 {
1286         const unsigned char *mac_addr = addr;
1287         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1288                             ((uint32_t)mac_addr[2] << 16) |
1289                             ((uint32_t)mac_addr[1] << 8) |
1290                             (uint32_t)mac_addr[0];
1291         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1292
1293         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1294         if (is_mc) {
1295                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1296                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1297                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1298         }
1299
1300         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1301         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1302 }
1303
1304 static int
1305 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1306                              uint8_t resp_code,
1307                              enum hns3_mac_vlan_tbl_opcode op)
1308 {
1309         if (cmdq_resp) {
1310                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1311                          cmdq_resp);
1312                 return -EIO;
1313         }
1314
1315         if (op == HNS3_MAC_VLAN_ADD) {
1316                 if (resp_code == 0 || resp_code == 1) {
1317                         return 0;
1318                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1319                         hns3_err(hw, "add mac addr failed for uc_overflow");
1320                         return -ENOSPC;
1321                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1322                         hns3_err(hw, "add mac addr failed for mc_overflow");
1323                         return -ENOSPC;
1324                 }
1325
1326                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1327                          resp_code);
1328                 return -EIO;
1329         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1330                 if (resp_code == 0) {
1331                         return 0;
1332                 } else if (resp_code == 1) {
1333                         hns3_dbg(hw, "remove mac addr failed for miss");
1334                         return -ENOENT;
1335                 }
1336
1337                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1338                          resp_code);
1339                 return -EIO;
1340         } else if (op == HNS3_MAC_VLAN_LKUP) {
1341                 if (resp_code == 0) {
1342                         return 0;
1343                 } else if (resp_code == 1) {
1344                         hns3_dbg(hw, "lookup mac addr failed for miss");
1345                         return -ENOENT;
1346                 }
1347
1348                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1349                          resp_code);
1350                 return -EIO;
1351         }
1352
1353         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1354                  op);
1355
1356         return -EINVAL;
1357 }
1358
1359 static int
1360 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1361                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1362                          struct hns3_cmd_desc *desc, bool is_mc)
1363 {
1364         uint8_t resp_code;
1365         uint16_t retval;
1366         int ret;
1367
1368         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1369         if (is_mc) {
1370                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1371                 memcpy(desc[0].data, req,
1372                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1373                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1374                                           true);
1375                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1376                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1377                                           true);
1378                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1379         } else {
1380                 memcpy(desc[0].data, req,
1381                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1382                 ret = hns3_cmd_send(hw, desc, 1);
1383         }
1384         if (ret) {
1385                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1386                          ret);
1387                 return ret;
1388         }
1389         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1390         retval = rte_le_to_cpu_16(desc[0].retval);
1391
1392         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1393                                             HNS3_MAC_VLAN_LKUP);
1394 }
1395
1396 static int
1397 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1398                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1399                       struct hns3_cmd_desc *mc_desc)
1400 {
1401         uint8_t resp_code;
1402         uint16_t retval;
1403         int cfg_status;
1404         int ret;
1405
1406         if (mc_desc == NULL) {
1407                 struct hns3_cmd_desc desc;
1408
1409                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1410                 memcpy(desc.data, req,
1411                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1412                 ret = hns3_cmd_send(hw, &desc, 1);
1413                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1414                 retval = rte_le_to_cpu_16(desc.retval);
1415
1416                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1417                                                           HNS3_MAC_VLAN_ADD);
1418         } else {
1419                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1420                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1421                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1422                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1423                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1424                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1425                 memcpy(mc_desc[0].data, req,
1426                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1427                 mc_desc[0].retval = 0;
1428                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1429                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1430                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1431
1432                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1433                                                           HNS3_MAC_VLAN_ADD);
1434         }
1435
1436         if (ret) {
1437                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1438                 return ret;
1439         }
1440
1441         return cfg_status;
1442 }
1443
1444 static int
1445 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1446                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1447 {
1448         struct hns3_cmd_desc desc;
1449         uint8_t resp_code;
1450         uint16_t retval;
1451         int ret;
1452
1453         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1454
1455         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1456
1457         ret = hns3_cmd_send(hw, &desc, 1);
1458         if (ret) {
1459                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1460                 return ret;
1461         }
1462         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1463         retval = rte_le_to_cpu_16(desc.retval);
1464
1465         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1466                                             HNS3_MAC_VLAN_REMOVE);
1467 }
1468
1469 static int
1470 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1471 {
1472         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1473         struct hns3_mac_vlan_tbl_entry_cmd req;
1474         struct hns3_pf *pf = &hns->pf;
1475         struct hns3_cmd_desc desc[3];
1476         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1477         uint16_t egress_port = 0;
1478         uint8_t vf_id;
1479         int ret;
1480
1481         /* check if mac addr is valid */
1482         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1483                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1484                                       mac_addr);
1485                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1486                          mac_str);
1487                 return -EINVAL;
1488         }
1489
1490         memset(&req, 0, sizeof(req));
1491
1492         /*
1493          * In current version VF is not supported when PF is driven by DPDK
1494          * driver, just need to configure parameters for PF vport.
1495          */
1496         vf_id = HNS3_PF_FUNC_ID;
1497         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1498                        HNS3_MAC_EPORT_VFID_S, vf_id);
1499
1500         req.egress_port = rte_cpu_to_le_16(egress_port);
1501
1502         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1503
1504         /*
1505          * Lookup the mac address in the mac_vlan table, and add
1506          * it if the entry is inexistent. Repeated unicast entry
1507          * is not allowed in the mac vlan table.
1508          */
1509         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1510         if (ret == -ENOENT) {
1511                 if (!hns3_is_umv_space_full(hw)) {
1512                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1513                         if (!ret)
1514                                 hns3_update_umv_space(hw, false);
1515                         return ret;
1516                 }
1517
1518                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1519
1520                 return -ENOSPC;
1521         }
1522
1523         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1524
1525         /* check if we just hit the duplicate */
1526         if (ret == 0) {
1527                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1528                 return 0;
1529         }
1530
1531         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1532                  mac_str);
1533
1534         return ret;
1535 }
1536
1537 static int
1538 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1539 {
1540         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1541         struct rte_ether_addr *addr;
1542         int ret;
1543         int i;
1544
1545         for (i = 0; i < hw->mc_addrs_num; i++) {
1546                 addr = &hw->mc_addrs[i];
1547                 /* Check if there are duplicate addresses */
1548                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1549                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1550                                               addr);
1551                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1552                                  "(%s) is added by the set_mc_mac_addr_list "
1553                                  "API", mac_str);
1554                         return -EINVAL;
1555                 }
1556         }
1557
1558         ret = hns3_add_mc_addr(hw, mac_addr);
1559         if (ret) {
1560                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1561                                       mac_addr);
1562                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1563                          mac_str, ret);
1564         }
1565         return ret;
1566 }
1567
1568 static int
1569 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1570 {
1571         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1572         int ret;
1573
1574         ret = hns3_remove_mc_addr(hw, mac_addr);
1575         if (ret) {
1576                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1577                                       mac_addr);
1578                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1579                          mac_str, ret);
1580         }
1581         return ret;
1582 }
1583
1584 static int
1585 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1586                   uint32_t idx, __rte_unused uint32_t pool)
1587 {
1588         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1589         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1590         int ret;
1591
1592         rte_spinlock_lock(&hw->lock);
1593
1594         /*
1595          * In hns3 network engine adding UC and MC mac address with different
1596          * commands with firmware. We need to determine whether the input
1597          * address is a UC or a MC address to call different commands.
1598          * By the way, it is recommended calling the API function named
1599          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1600          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1601          * may affect the specifications of UC mac addresses.
1602          */
1603         if (rte_is_multicast_ether_addr(mac_addr))
1604                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1605         else
1606                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1607
1608         if (ret) {
1609                 rte_spinlock_unlock(&hw->lock);
1610                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1611                                       mac_addr);
1612                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1613                          ret);
1614                 return ret;
1615         }
1616
1617         if (idx == 0)
1618                 hw->mac.default_addr_setted = true;
1619         rte_spinlock_unlock(&hw->lock);
1620
1621         return ret;
1622 }
1623
1624 static int
1625 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1626 {
1627         struct hns3_mac_vlan_tbl_entry_cmd req;
1628         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1629         int ret;
1630
1631         /* check if mac addr is valid */
1632         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1633                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1634                                       mac_addr);
1635                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1636                          mac_str);
1637                 return -EINVAL;
1638         }
1639
1640         memset(&req, 0, sizeof(req));
1641         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1642         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1643         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1644         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1645                 return 0;
1646         else if (ret == 0)
1647                 hns3_update_umv_space(hw, true);
1648
1649         return ret;
1650 }
1651
1652 static void
1653 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1654 {
1655         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1656         /* index will be checked by upper level rte interface */
1657         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1658         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1659         int ret;
1660
1661         rte_spinlock_lock(&hw->lock);
1662
1663         if (rte_is_multicast_ether_addr(mac_addr))
1664                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1665         else
1666                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1667         rte_spinlock_unlock(&hw->lock);
1668         if (ret) {
1669                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1670                                       mac_addr);
1671                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1672                          ret);
1673         }
1674 }
1675
1676 static int
1677 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1678                           struct rte_ether_addr *mac_addr)
1679 {
1680         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1681         struct rte_ether_addr *oaddr;
1682         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1683         bool default_addr_setted;
1684         bool rm_succes = false;
1685         int ret, ret_val;
1686
1687         /*
1688          * It has been guaranteed that input parameter named mac_addr is valid
1689          * address in the rte layer of DPDK framework.
1690          */
1691         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1692         default_addr_setted = hw->mac.default_addr_setted;
1693         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1694                 return 0;
1695
1696         rte_spinlock_lock(&hw->lock);
1697         if (default_addr_setted) {
1698                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1699                 if (ret) {
1700                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1701                                               oaddr);
1702                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1703                                   mac_str, ret);
1704                         rm_succes = false;
1705                 } else
1706                         rm_succes = true;
1707         }
1708
1709         ret = hns3_add_uc_addr_common(hw, mac_addr);
1710         if (ret) {
1711                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1712                                       mac_addr);
1713                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1714                 goto err_add_uc_addr;
1715         }
1716
1717         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1718         if (ret) {
1719                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1720                 goto err_pause_addr_cfg;
1721         }
1722
1723         rte_ether_addr_copy(mac_addr,
1724                             (struct rte_ether_addr *)hw->mac.mac_addr);
1725         hw->mac.default_addr_setted = true;
1726         rte_spinlock_unlock(&hw->lock);
1727
1728         return 0;
1729
1730 err_pause_addr_cfg:
1731         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1732         if (ret_val) {
1733                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1734                                       mac_addr);
1735                 hns3_warn(hw,
1736                           "Failed to roll back to del setted mac addr(%s): %d",
1737                           mac_str, ret_val);
1738         }
1739
1740 err_add_uc_addr:
1741         if (rm_succes) {
1742                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1743                 if (ret_val) {
1744                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1745                                               oaddr);
1746                         hns3_warn(hw,
1747                                   "Failed to restore old uc mac addr(%s): %d",
1748                                   mac_str, ret_val);
1749                         hw->mac.default_addr_setted = false;
1750                 }
1751         }
1752         rte_spinlock_unlock(&hw->lock);
1753
1754         return ret;
1755 }
1756
1757 static int
1758 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1759 {
1760         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1761         struct hns3_hw *hw = &hns->hw;
1762         struct rte_ether_addr *addr;
1763         int err = 0;
1764         int ret;
1765         int i;
1766
1767         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1768                 addr = &hw->data->mac_addrs[i];
1769                 if (rte_is_zero_ether_addr(addr))
1770                         continue;
1771                 if (rte_is_multicast_ether_addr(addr))
1772                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1773                               hns3_add_mc_addr(hw, addr);
1774                 else
1775                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1776                               hns3_add_uc_addr_common(hw, addr);
1777
1778                 if (ret) {
1779                         err = ret;
1780                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1781                                               addr);
1782                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1783                                  "ret = %d.", del ? "remove" : "restore",
1784                                  mac_str, i, ret);
1785                 }
1786         }
1787         return err;
1788 }
1789
1790 static void
1791 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1792 {
1793 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1794         uint8_t word_num;
1795         uint8_t bit_num;
1796
1797         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1798                 word_num = vfid / 32;
1799                 bit_num = vfid % 32;
1800                 if (clr)
1801                         desc[1].data[word_num] &=
1802                             rte_cpu_to_le_32(~(1UL << bit_num));
1803                 else
1804                         desc[1].data[word_num] |=
1805                             rte_cpu_to_le_32(1UL << bit_num);
1806         } else {
1807                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1808                 bit_num = vfid % 32;
1809                 if (clr)
1810                         desc[2].data[word_num] &=
1811                             rte_cpu_to_le_32(~(1UL << bit_num));
1812                 else
1813                         desc[2].data[word_num] |=
1814                             rte_cpu_to_le_32(1UL << bit_num);
1815         }
1816 }
1817
1818 static int
1819 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1820 {
1821         struct hns3_mac_vlan_tbl_entry_cmd req;
1822         struct hns3_cmd_desc desc[3];
1823         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1824         uint8_t vf_id;
1825         int ret;
1826
1827         /* Check if mac addr is valid */
1828         if (!rte_is_multicast_ether_addr(mac_addr)) {
1829                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1830                                       mac_addr);
1831                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1832                          mac_str);
1833                 return -EINVAL;
1834         }
1835
1836         memset(&req, 0, sizeof(req));
1837         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1838         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1839         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1840         if (ret) {
1841                 /* This mac addr do not exist, add new entry for it */
1842                 memset(desc[0].data, 0, sizeof(desc[0].data));
1843                 memset(desc[1].data, 0, sizeof(desc[0].data));
1844                 memset(desc[2].data, 0, sizeof(desc[0].data));
1845         }
1846
1847         /*
1848          * In current version VF is not supported when PF is driven by DPDK
1849          * driver, just need to configure parameters for PF vport.
1850          */
1851         vf_id = HNS3_PF_FUNC_ID;
1852         hns3_update_desc_vfid(desc, vf_id, false);
1853         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1854         if (ret) {
1855                 if (ret == -ENOSPC)
1856                         hns3_err(hw, "mc mac vlan table is full");
1857                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1858                                       mac_addr);
1859                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1860         }
1861
1862         return ret;
1863 }
1864
1865 static int
1866 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1867 {
1868         struct hns3_mac_vlan_tbl_entry_cmd req;
1869         struct hns3_cmd_desc desc[3];
1870         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1871         uint8_t vf_id;
1872         int ret;
1873
1874         /* Check if mac addr is valid */
1875         if (!rte_is_multicast_ether_addr(mac_addr)) {
1876                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1877                                       mac_addr);
1878                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1879                          mac_str);
1880                 return -EINVAL;
1881         }
1882
1883         memset(&req, 0, sizeof(req));
1884         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1885         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1886         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1887         if (ret == 0) {
1888                 /*
1889                  * This mac addr exist, remove this handle's VFID for it.
1890                  * In current version VF is not supported when PF is driven by
1891                  * DPDK driver, just need to configure parameters for PF vport.
1892                  */
1893                 vf_id = HNS3_PF_FUNC_ID;
1894                 hns3_update_desc_vfid(desc, vf_id, true);
1895
1896                 /* All the vfid is zero, so need to delete this entry */
1897                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1898         } else if (ret == -ENOENT) {
1899                 /* This mac addr doesn't exist. */
1900                 return 0;
1901         }
1902
1903         if (ret) {
1904                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1905                                       mac_addr);
1906                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1907         }
1908
1909         return ret;
1910 }
1911
1912 static int
1913 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1914                            struct rte_ether_addr *mc_addr_set,
1915                            uint32_t nb_mc_addr)
1916 {
1917         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1918         struct rte_ether_addr *addr;
1919         uint32_t i;
1920         uint32_t j;
1921
1922         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1923                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1924                          "invalid. valid range: 0~%d",
1925                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1926                 return -EINVAL;
1927         }
1928
1929         /* Check if input mac addresses are valid */
1930         for (i = 0; i < nb_mc_addr; i++) {
1931                 addr = &mc_addr_set[i];
1932                 if (!rte_is_multicast_ether_addr(addr)) {
1933                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1934                                               addr);
1935                         hns3_err(hw,
1936                                  "failed to set mc mac addr, addr(%s) invalid.",
1937                                  mac_str);
1938                         return -EINVAL;
1939                 }
1940
1941                 /* Check if there are duplicate addresses */
1942                 for (j = i + 1; j < nb_mc_addr; j++) {
1943                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1944                                 hns3_ether_format_addr(mac_str,
1945                                                       RTE_ETHER_ADDR_FMT_SIZE,
1946                                                       addr);
1947                                 hns3_err(hw, "failed to set mc mac addr, "
1948                                          "addrs invalid. two same addrs(%s).",
1949                                          mac_str);
1950                                 return -EINVAL;
1951                         }
1952                 }
1953
1954                 /*
1955                  * Check if there are duplicate addresses between mac_addrs
1956                  * and mc_addr_set
1957                  */
1958                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1959                         if (rte_is_same_ether_addr(addr,
1960                                                    &hw->data->mac_addrs[j])) {
1961                                 hns3_ether_format_addr(mac_str,
1962                                                       RTE_ETHER_ADDR_FMT_SIZE,
1963                                                       addr);
1964                                 hns3_err(hw, "failed to set mc mac addr, "
1965                                          "addrs invalid. addrs(%s) has already "
1966                                          "configured in mac_addr add API",
1967                                          mac_str);
1968                                 return -EINVAL;
1969                         }
1970                 }
1971         }
1972
1973         return 0;
1974 }
1975
1976 static void
1977 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1978                            struct rte_ether_addr *mc_addr_set,
1979                            int mc_addr_num,
1980                            struct rte_ether_addr *reserved_addr_list,
1981                            int *reserved_addr_num,
1982                            struct rte_ether_addr *add_addr_list,
1983                            int *add_addr_num,
1984                            struct rte_ether_addr *rm_addr_list,
1985                            int *rm_addr_num)
1986 {
1987         struct rte_ether_addr *addr;
1988         int current_addr_num;
1989         int reserved_num = 0;
1990         int add_num = 0;
1991         int rm_num = 0;
1992         int num;
1993         int i;
1994         int j;
1995         bool same_addr;
1996
1997         /* Calculate the mc mac address list that should be removed */
1998         current_addr_num = hw->mc_addrs_num;
1999         for (i = 0; i < current_addr_num; i++) {
2000                 addr = &hw->mc_addrs[i];
2001                 same_addr = false;
2002                 for (j = 0; j < mc_addr_num; j++) {
2003                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2004                                 same_addr = true;
2005                                 break;
2006                         }
2007                 }
2008
2009                 if (!same_addr) {
2010                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2011                         rm_num++;
2012                 } else {
2013                         rte_ether_addr_copy(addr,
2014                                             &reserved_addr_list[reserved_num]);
2015                         reserved_num++;
2016                 }
2017         }
2018
2019         /* Calculate the mc mac address list that should be added */
2020         for (i = 0; i < mc_addr_num; i++) {
2021                 addr = &mc_addr_set[i];
2022                 same_addr = false;
2023                 for (j = 0; j < current_addr_num; j++) {
2024                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2025                                 same_addr = true;
2026                                 break;
2027                         }
2028                 }
2029
2030                 if (!same_addr) {
2031                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2032                         add_num++;
2033                 }
2034         }
2035
2036         /* Reorder the mc mac address list maintained by driver */
2037         for (i = 0; i < reserved_num; i++)
2038                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2039
2040         for (i = 0; i < rm_num; i++) {
2041                 num = reserved_num + i;
2042                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2043         }
2044
2045         *reserved_addr_num = reserved_num;
2046         *add_addr_num = add_num;
2047         *rm_addr_num = rm_num;
2048 }
2049
2050 static int
2051 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2052                           struct rte_ether_addr *mc_addr_set,
2053                           uint32_t nb_mc_addr)
2054 {
2055         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2056         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2057         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2058         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2059         struct rte_ether_addr *addr;
2060         int reserved_addr_num;
2061         int add_addr_num;
2062         int rm_addr_num;
2063         int mc_addr_num;
2064         int num;
2065         int ret;
2066         int i;
2067
2068         /* Check if input parameters are valid */
2069         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2070         if (ret)
2071                 return ret;
2072
2073         rte_spinlock_lock(&hw->lock);
2074
2075         /*
2076          * Calculate the mc mac address lists those should be removed and be
2077          * added, Reorder the mc mac address list maintained by driver.
2078          */
2079         mc_addr_num = (int)nb_mc_addr;
2080         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2081                                    reserved_addr_list, &reserved_addr_num,
2082                                    add_addr_list, &add_addr_num,
2083                                    rm_addr_list, &rm_addr_num);
2084
2085         /* Remove mc mac addresses */
2086         for (i = 0; i < rm_addr_num; i++) {
2087                 num = rm_addr_num - i - 1;
2088                 addr = &rm_addr_list[num];
2089                 ret = hns3_remove_mc_addr(hw, addr);
2090                 if (ret) {
2091                         rte_spinlock_unlock(&hw->lock);
2092                         return ret;
2093                 }
2094                 hw->mc_addrs_num--;
2095         }
2096
2097         /* Add mc mac addresses */
2098         for (i = 0; i < add_addr_num; i++) {
2099                 addr = &add_addr_list[i];
2100                 ret = hns3_add_mc_addr(hw, addr);
2101                 if (ret) {
2102                         rte_spinlock_unlock(&hw->lock);
2103                         return ret;
2104                 }
2105
2106                 num = reserved_addr_num + i;
2107                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2108                 hw->mc_addrs_num++;
2109         }
2110         rte_spinlock_unlock(&hw->lock);
2111
2112         return 0;
2113 }
2114
2115 static int
2116 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2117 {
2118         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2119         struct hns3_hw *hw = &hns->hw;
2120         struct rte_ether_addr *addr;
2121         int err = 0;
2122         int ret;
2123         int i;
2124
2125         for (i = 0; i < hw->mc_addrs_num; i++) {
2126                 addr = &hw->mc_addrs[i];
2127                 if (!rte_is_multicast_ether_addr(addr))
2128                         continue;
2129                 if (del)
2130                         ret = hns3_remove_mc_addr(hw, addr);
2131                 else
2132                         ret = hns3_add_mc_addr(hw, addr);
2133                 if (ret) {
2134                         err = ret;
2135                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2136                                               addr);
2137                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2138                                  del ? "Remove" : "Restore", mac_str, ret);
2139                 }
2140         }
2141         return err;
2142 }
2143
2144 static int
2145 hns3_check_mq_mode(struct rte_eth_dev *dev)
2146 {
2147         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2148         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2149         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2151         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2152         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2153         uint8_t num_tc;
2154         int max_tc = 0;
2155         int i;
2156
2157         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2158         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2159
2160         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2161                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2162                          "rx_mq_mode = %d", rx_mq_mode);
2163                 return -EINVAL;
2164         }
2165
2166         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2167             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2168                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2169                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2170                          rx_mq_mode, tx_mq_mode);
2171                 return -EINVAL;
2172         }
2173
2174         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2175                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2176                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2177                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2178                         return -EINVAL;
2179                 }
2180
2181                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2182                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2183                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2184                                  "nb_tcs(%d) != %d or %d in rx direction.",
2185                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2186                         return -EINVAL;
2187                 }
2188
2189                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2190                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2191                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2192                         return -EINVAL;
2193                 }
2194
2195                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2196                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2197                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2198                                          "is not equal to one in tx direction.",
2199                                          i, dcb_rx_conf->dcb_tc[i]);
2200                                 return -EINVAL;
2201                         }
2202                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2203                                 max_tc = dcb_rx_conf->dcb_tc[i];
2204                 }
2205
2206                 num_tc = max_tc + 1;
2207                 if (num_tc > dcb_rx_conf->nb_tcs) {
2208                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2209                                  num_tc, dcb_rx_conf->nb_tcs);
2210                         return -EINVAL;
2211                 }
2212         }
2213
2214         return 0;
2215 }
2216
2217 static int
2218 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2219 {
2220         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2221
2222         if (!hns3_dev_dcb_supported(hw)) {
2223                 hns3_err(hw, "this port does not support dcb configurations.");
2224                 return -EOPNOTSUPP;
2225         }
2226
2227         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2228                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2229                 return -EOPNOTSUPP;
2230         }
2231
2232         /* Check multiple queue mode */
2233         return hns3_check_mq_mode(dev);
2234 }
2235
2236 static int
2237 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2238                            enum hns3_ring_type queue_type, uint16_t queue_id)
2239 {
2240         struct hns3_cmd_desc desc;
2241         struct hns3_ctrl_vector_chain_cmd *req =
2242                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2243         enum hns3_cmd_status status;
2244         enum hns3_opcode_type op;
2245         uint16_t tqp_type_and_id = 0;
2246         uint16_t type;
2247         uint16_t gl;
2248
2249         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2250         hns3_cmd_setup_basic_desc(&desc, op, false);
2251         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2252                                               HNS3_TQP_INT_ID_L_S);
2253         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2254                                               HNS3_TQP_INT_ID_H_S);
2255
2256         if (queue_type == HNS3_RING_TYPE_RX)
2257                 gl = HNS3_RING_GL_RX;
2258         else
2259                 gl = HNS3_RING_GL_TX;
2260
2261         type = queue_type;
2262
2263         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2264                        type);
2265         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2266         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2267                        gl);
2268         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2269         req->int_cause_num = 1;
2270         status = hns3_cmd_send(hw, &desc, 1);
2271         if (status) {
2272                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2273                          en ? "Map" : "Unmap", queue_id, vector_id, status);
2274                 return status;
2275         }
2276
2277         return 0;
2278 }
2279
2280 static int
2281 hns3_init_ring_with_vector(struct hns3_hw *hw)
2282 {
2283         uint16_t vec;
2284         int ret;
2285         int i;
2286
2287         /*
2288          * In hns3 network engine, vector 0 is always the misc interrupt of this
2289          * function, vector 1~N can be used respectively for the queues of the
2290          * function. Tx and Rx queues with the same number share the interrupt
2291          * vector. In the initialization clearing the all hardware mapping
2292          * relationship configurations between queues and interrupt vectors is
2293          * needed, so some error caused by the residual configurations, such as
2294          * the unexpected Tx interrupt, can be avoid.
2295          */
2296         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2297         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2298                 vec = vec - 1; /* the last interrupt is reserved */
2299         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2300         for (i = 0; i < hw->intr_tqps_num; i++) {
2301                 /*
2302                  * Set gap limiter/rate limiter/quanity limiter algorithm
2303                  * configuration for interrupt coalesce of queue's interrupt.
2304                  */
2305                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2306                                        HNS3_TQP_INTR_GL_DEFAULT);
2307                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2308                                        HNS3_TQP_INTR_GL_DEFAULT);
2309                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2310                 /*
2311                  * QL(quantity limiter) is not used currently, just set 0 to
2312                  * close it.
2313                  */
2314                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2315
2316                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2317                                                  HNS3_RING_TYPE_TX, i);
2318                 if (ret) {
2319                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2320                                           "vector: %u, ret=%d", i, vec, ret);
2321                         return ret;
2322                 }
2323
2324                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2325                                                  HNS3_RING_TYPE_RX, i);
2326                 if (ret) {
2327                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2328                                           "vector: %u, ret=%d", i, vec, ret);
2329                         return ret;
2330                 }
2331         }
2332
2333         return 0;
2334 }
2335
2336 static int
2337 hns3_dev_configure(struct rte_eth_dev *dev)
2338 {
2339         struct hns3_adapter *hns = dev->data->dev_private;
2340         struct rte_eth_conf *conf = &dev->data->dev_conf;
2341         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2342         struct hns3_hw *hw = &hns->hw;
2343         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2344         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2345         struct rte_eth_rss_conf rss_conf;
2346         uint16_t mtu;
2347         bool gro_en;
2348         int ret;
2349
2350         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2351
2352         /*
2353          * Some versions of hardware network engine does not support
2354          * individually enable/disable/reset the Tx or Rx queue. These devices
2355          * must enable/disable/reset Tx and Rx queues at the same time. When the
2356          * numbers of Tx queues allocated by upper applications are not equal to
2357          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2358          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2359          * work as usual. But these fake queues are imperceptible, and can not
2360          * be used by upper applications.
2361          */
2362         if (!hns3_dev_indep_txrx_supported(hw)) {
2363                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2364                 if (ret) {
2365                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2366                                  ret);
2367                         return ret;
2368                 }
2369         }
2370
2371         hw->adapter_state = HNS3_NIC_CONFIGURING;
2372         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2373                 hns3_err(hw, "setting link speed/duplex not supported");
2374                 ret = -EINVAL;
2375                 goto cfg_err;
2376         }
2377
2378         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2379                 ret = hns3_check_dcb_cfg(dev);
2380                 if (ret)
2381                         goto cfg_err;
2382         }
2383
2384         /* When RSS is not configured, redirect the packet queue 0 */
2385         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2386                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2387                 rss_conf = conf->rx_adv_conf.rss_conf;
2388                 hw->rss_dis_flag = false;
2389                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2390                 if (ret)
2391                         goto cfg_err;
2392         }
2393
2394         /*
2395          * If jumbo frames are enabled, MTU needs to be refreshed
2396          * according to the maximum RX packet length.
2397          */
2398         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2399                 /*
2400                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2401                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2402                  * can safely assign to "uint16_t" type variable.
2403                  */
2404                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2405                 ret = hns3_dev_mtu_set(dev, mtu);
2406                 if (ret)
2407                         goto cfg_err;
2408                 dev->data->mtu = mtu;
2409         }
2410
2411         ret = hns3_dev_configure_vlan(dev);
2412         if (ret)
2413                 goto cfg_err;
2414
2415         /* config hardware GRO */
2416         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2417         ret = hns3_config_gro(hw, gro_en);
2418         if (ret)
2419                 goto cfg_err;
2420
2421         hns->rx_simple_allowed = true;
2422         hns->rx_vec_allowed = true;
2423         hns->tx_simple_allowed = true;
2424         hns->tx_vec_allowed = true;
2425
2426         hns3_init_rx_ptype_tble(dev);
2427         hw->adapter_state = HNS3_NIC_CONFIGURED;
2428
2429         return 0;
2430
2431 cfg_err:
2432         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2433         hw->adapter_state = HNS3_NIC_INITIALIZED;
2434
2435         return ret;
2436 }
2437
2438 static int
2439 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2440 {
2441         struct hns3_config_max_frm_size_cmd *req;
2442         struct hns3_cmd_desc desc;
2443
2444         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2445
2446         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2447         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2448         req->min_frm_size = RTE_ETHER_MIN_LEN;
2449
2450         return hns3_cmd_send(hw, &desc, 1);
2451 }
2452
2453 static int
2454 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2455 {
2456         int ret;
2457
2458         ret = hns3_set_mac_mtu(hw, mps);
2459         if (ret) {
2460                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2461                 return ret;
2462         }
2463
2464         ret = hns3_buffer_alloc(hw);
2465         if (ret)
2466                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2467
2468         return ret;
2469 }
2470
2471 static int
2472 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2473 {
2474         struct hns3_adapter *hns = dev->data->dev_private;
2475         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2476         struct hns3_hw *hw = &hns->hw;
2477         bool is_jumbo_frame;
2478         int ret;
2479
2480         if (dev->data->dev_started) {
2481                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2482                          "before configuration", dev->data->port_id);
2483                 return -EBUSY;
2484         }
2485
2486         rte_spinlock_lock(&hw->lock);
2487         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2488         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2489
2490         /*
2491          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2492          * assign to "uint16_t" type variable.
2493          */
2494         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2495         if (ret) {
2496                 rte_spinlock_unlock(&hw->lock);
2497                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2498                          dev->data->port_id, mtu, ret);
2499                 return ret;
2500         }
2501         hns->pf.mps = (uint16_t)frame_size;
2502         if (is_jumbo_frame)
2503                 dev->data->dev_conf.rxmode.offloads |=
2504                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2505         else
2506                 dev->data->dev_conf.rxmode.offloads &=
2507                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2508         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2509         rte_spinlock_unlock(&hw->lock);
2510
2511         return 0;
2512 }
2513
2514 int
2515 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2516 {
2517         struct hns3_adapter *hns = eth_dev->data->dev_private;
2518         struct hns3_hw *hw = &hns->hw;
2519         uint16_t queue_num = hw->tqps_num;
2520
2521         /*
2522          * In interrupt mode, 'max_rx_queues' is set based on the number of
2523          * MSI-X interrupt resources of the hardware.
2524          */
2525         if (hw->data->dev_conf.intr_conf.rxq == 1)
2526                 queue_num = hw->intr_tqps_num;
2527
2528         info->max_rx_queues = queue_num;
2529         info->max_tx_queues = hw->tqps_num;
2530         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2531         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2532         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2533         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2534         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2535         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2536                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2537                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2538                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2539                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2540                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2541                                  DEV_RX_OFFLOAD_KEEP_CRC |
2542                                  DEV_RX_OFFLOAD_SCATTER |
2543                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2544                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2545                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2546                                  DEV_RX_OFFLOAD_RSS_HASH |
2547                                  DEV_RX_OFFLOAD_TCP_LRO);
2548         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2549                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2550                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2551                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2552                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2553                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2554                                  DEV_TX_OFFLOAD_TCP_TSO |
2555                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2556                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2557                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2558                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2559                                  hns3_txvlan_cap_get(hw));
2560
2561         if (hns3_dev_indep_txrx_supported(hw))
2562                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2563                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2564
2565         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2566                 .nb_max = HNS3_MAX_RING_DESC,
2567                 .nb_min = HNS3_MIN_RING_DESC,
2568                 .nb_align = HNS3_ALIGN_RING_DESC,
2569         };
2570
2571         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2572                 .nb_max = HNS3_MAX_RING_DESC,
2573                 .nb_min = HNS3_MIN_RING_DESC,
2574                 .nb_align = HNS3_ALIGN_RING_DESC,
2575                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2576                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2577         };
2578
2579         info->default_rxconf = (struct rte_eth_rxconf) {
2580                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2581                 /*
2582                  * If there are no available Rx buffer descriptors, incoming
2583                  * packets are always dropped by hardware based on hns3 network
2584                  * engine.
2585                  */
2586                 .rx_drop_en = 1,
2587                 .offloads = 0,
2588         };
2589         info->default_txconf = (struct rte_eth_txconf) {
2590                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2591                 .offloads = 0,
2592         };
2593
2594         info->vmdq_queue_num = 0;
2595
2596         info->reta_size = hw->rss_ind_tbl_size;
2597         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2598         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2599
2600         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2601         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2602         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2603         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2604         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2605         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2606
2607         return 0;
2608 }
2609
2610 static int
2611 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2612                     size_t fw_size)
2613 {
2614         struct hns3_adapter *hns = eth_dev->data->dev_private;
2615         struct hns3_hw *hw = &hns->hw;
2616         uint32_t version = hw->fw_version;
2617         int ret;
2618
2619         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2620                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2621                                       HNS3_FW_VERSION_BYTE3_S),
2622                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2623                                       HNS3_FW_VERSION_BYTE2_S),
2624                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2625                                       HNS3_FW_VERSION_BYTE1_S),
2626                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2627                                       HNS3_FW_VERSION_BYTE0_S));
2628         ret += 1; /* add the size of '\0' */
2629         if (fw_size < (uint32_t)ret)
2630                 return ret;
2631         else
2632                 return 0;
2633 }
2634
2635 static int
2636 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2637                      __rte_unused int wait_to_complete)
2638 {
2639         struct hns3_adapter *hns = eth_dev->data->dev_private;
2640         struct hns3_hw *hw = &hns->hw;
2641         struct hns3_mac *mac = &hw->mac;
2642         struct rte_eth_link new_link;
2643
2644         if (!hns3_is_reset_pending(hns)) {
2645                 hns3_update_link_status(hw);
2646                 hns3_update_link_info(eth_dev);
2647         }
2648
2649         memset(&new_link, 0, sizeof(new_link));
2650         switch (mac->link_speed) {
2651         case ETH_SPEED_NUM_10M:
2652         case ETH_SPEED_NUM_100M:
2653         case ETH_SPEED_NUM_1G:
2654         case ETH_SPEED_NUM_10G:
2655         case ETH_SPEED_NUM_25G:
2656         case ETH_SPEED_NUM_40G:
2657         case ETH_SPEED_NUM_50G:
2658         case ETH_SPEED_NUM_100G:
2659         case ETH_SPEED_NUM_200G:
2660                 new_link.link_speed = mac->link_speed;
2661                 break;
2662         default:
2663                 new_link.link_speed = ETH_SPEED_NUM_100M;
2664                 break;
2665         }
2666
2667         new_link.link_duplex = mac->link_duplex;
2668         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2669         new_link.link_autoneg =
2670             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2671
2672         return rte_eth_linkstatus_set(eth_dev, &new_link);
2673 }
2674
2675 static int
2676 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2677 {
2678         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2679         struct hns3_pf *pf = &hns->pf;
2680
2681         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2682                 return -EINVAL;
2683
2684         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2685
2686         return 0;
2687 }
2688
2689 static int
2690 hns3_query_function_status(struct hns3_hw *hw)
2691 {
2692 #define HNS3_QUERY_MAX_CNT              10
2693 #define HNS3_QUERY_SLEEP_MSCOEND        1
2694         struct hns3_func_status_cmd *req;
2695         struct hns3_cmd_desc desc;
2696         int timeout = 0;
2697         int ret;
2698
2699         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2700         req = (struct hns3_func_status_cmd *)desc.data;
2701
2702         do {
2703                 ret = hns3_cmd_send(hw, &desc, 1);
2704                 if (ret) {
2705                         PMD_INIT_LOG(ERR, "query function status failed %d",
2706                                      ret);
2707                         return ret;
2708                 }
2709
2710                 /* Check pf reset is done */
2711                 if (req->pf_state)
2712                         break;
2713
2714                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2715         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2716
2717         return hns3_parse_func_status(hw, req);
2718 }
2719
2720 static int
2721 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2722 {
2723         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2724         struct hns3_pf *pf = &hns->pf;
2725
2726         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2727                 /*
2728                  * The total_tqps_num obtained from firmware is maximum tqp
2729                  * numbers of this port, which should be used for PF and VFs.
2730                  * There is no need for pf to have so many tqp numbers in
2731                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2732                  * coming from config file, is assigned to maximum queue number
2733                  * for the PF of this port by user. So users can modify the
2734                  * maximum queue number of PF according to their own application
2735                  * scenarios, which is more flexible to use. In addition, many
2736                  * memories can be saved due to allocating queue statistics
2737                  * room according to the actual number of queues required. The
2738                  * maximum queue number of PF for network engine with
2739                  * revision_id greater than 0x30 is assigned by config file.
2740                  */
2741                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2742                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2743                                  "must be greater than 0.",
2744                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2745                         return -EINVAL;
2746                 }
2747
2748                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2749                                        hw->total_tqps_num);
2750         } else {
2751                 /*
2752                  * Due to the limitation on the number of PF interrupts
2753                  * available, the maximum queue number assigned to PF on
2754                  * the network engine with revision_id 0x21 is 64.
2755                  */
2756                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2757                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2758         }
2759
2760         return 0;
2761 }
2762
2763 static int
2764 hns3_query_pf_resource(struct hns3_hw *hw)
2765 {
2766         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2767         struct hns3_pf *pf = &hns->pf;
2768         struct hns3_pf_res_cmd *req;
2769         struct hns3_cmd_desc desc;
2770         int ret;
2771
2772         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2773         ret = hns3_cmd_send(hw, &desc, 1);
2774         if (ret) {
2775                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2776                 return ret;
2777         }
2778
2779         req = (struct hns3_pf_res_cmd *)desc.data;
2780         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2781                              rte_le_to_cpu_16(req->ext_tqp_num);
2782         ret = hns3_get_pf_max_tqp_num(hw);
2783         if (ret)
2784                 return ret;
2785
2786         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2787         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2788
2789         if (req->tx_buf_size)
2790                 pf->tx_buf_size =
2791                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2792         else
2793                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2794
2795         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2796
2797         if (req->dv_buf_size)
2798                 pf->dv_buf_size =
2799                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2800         else
2801                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2802
2803         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2804
2805         hw->num_msi =
2806                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2807                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2808
2809         return 0;
2810 }
2811
2812 static void
2813 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2814 {
2815         struct hns3_cfg_param_cmd *req;
2816         uint64_t mac_addr_tmp_high;
2817         uint8_t ext_rss_size_max;
2818         uint64_t mac_addr_tmp;
2819         uint32_t i;
2820
2821         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2822
2823         /* get the configuration */
2824         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2825                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2826         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2827                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2828         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2829                                            HNS3_CFG_TQP_DESC_N_M,
2830                                            HNS3_CFG_TQP_DESC_N_S);
2831
2832         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2833                                        HNS3_CFG_PHY_ADDR_M,
2834                                        HNS3_CFG_PHY_ADDR_S);
2835         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2836                                          HNS3_CFG_MEDIA_TP_M,
2837                                          HNS3_CFG_MEDIA_TP_S);
2838         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2839                                          HNS3_CFG_RX_BUF_LEN_M,
2840                                          HNS3_CFG_RX_BUF_LEN_S);
2841         /* get mac address */
2842         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2843         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2844                                            HNS3_CFG_MAC_ADDR_H_M,
2845                                            HNS3_CFG_MAC_ADDR_H_S);
2846
2847         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2848
2849         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2850                                             HNS3_CFG_DEFAULT_SPEED_M,
2851                                             HNS3_CFG_DEFAULT_SPEED_S);
2852         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2853                                            HNS3_CFG_RSS_SIZE_M,
2854                                            HNS3_CFG_RSS_SIZE_S);
2855
2856         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2857                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2858
2859         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2860         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2861
2862         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2863                                             HNS3_CFG_SPEED_ABILITY_M,
2864                                             HNS3_CFG_SPEED_ABILITY_S);
2865         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2866                                         HNS3_CFG_UMV_TBL_SPACE_M,
2867                                         HNS3_CFG_UMV_TBL_SPACE_S);
2868         if (!cfg->umv_space)
2869                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2870
2871         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2872                                                HNS3_CFG_EXT_RSS_SIZE_M,
2873                                                HNS3_CFG_EXT_RSS_SIZE_S);
2874
2875         /*
2876          * Field ext_rss_size_max obtained from firmware will be more flexible
2877          * for future changes and expansions, which is an exponent of 2, instead
2878          * of reading out directly. If this field is not zero, hns3 PF PMD
2879          * driver uses it as rss_size_max under one TC. Device, whose revision
2880          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2881          * maximum number of queues supported under a TC through this field.
2882          */
2883         if (ext_rss_size_max)
2884                 cfg->rss_size_max = 1U << ext_rss_size_max;
2885 }
2886
2887 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2888  * @hw: pointer to struct hns3_hw
2889  * @hcfg: the config structure to be getted
2890  */
2891 static int
2892 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2893 {
2894         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2895         struct hns3_cfg_param_cmd *req;
2896         uint32_t offset;
2897         uint32_t i;
2898         int ret;
2899
2900         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2901                 offset = 0;
2902                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2903                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2904                                           true);
2905                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2906                                i * HNS3_CFG_RD_LEN_BYTES);
2907                 /* Len should be divided by 4 when send to hardware */
2908                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2909                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2910                 req->offset = rte_cpu_to_le_32(offset);
2911         }
2912
2913         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2914         if (ret) {
2915                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2916                 return ret;
2917         }
2918
2919         hns3_parse_cfg(hcfg, desc);
2920
2921         return 0;
2922 }
2923
2924 static int
2925 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2926 {
2927         switch (speed_cmd) {
2928         case HNS3_CFG_SPEED_10M:
2929                 *speed = ETH_SPEED_NUM_10M;
2930                 break;
2931         case HNS3_CFG_SPEED_100M:
2932                 *speed = ETH_SPEED_NUM_100M;
2933                 break;
2934         case HNS3_CFG_SPEED_1G:
2935                 *speed = ETH_SPEED_NUM_1G;
2936                 break;
2937         case HNS3_CFG_SPEED_10G:
2938                 *speed = ETH_SPEED_NUM_10G;
2939                 break;
2940         case HNS3_CFG_SPEED_25G:
2941                 *speed = ETH_SPEED_NUM_25G;
2942                 break;
2943         case HNS3_CFG_SPEED_40G:
2944                 *speed = ETH_SPEED_NUM_40G;
2945                 break;
2946         case HNS3_CFG_SPEED_50G:
2947                 *speed = ETH_SPEED_NUM_50G;
2948                 break;
2949         case HNS3_CFG_SPEED_100G:
2950                 *speed = ETH_SPEED_NUM_100G;
2951                 break;
2952         case HNS3_CFG_SPEED_200G:
2953                 *speed = ETH_SPEED_NUM_200G;
2954                 break;
2955         default:
2956                 return -EINVAL;
2957         }
2958
2959         return 0;
2960 }
2961
2962 static void
2963 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2964 {
2965         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2966         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2967         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2968         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2969         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2970 }
2971
2972 static void
2973 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2974 {
2975         struct hns3_dev_specs_0_cmd *req0;
2976
2977         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2978
2979         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2980         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2981         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2982         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2983         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
2984 }
2985
2986 static int
2987 hns3_check_dev_specifications(struct hns3_hw *hw)
2988 {
2989         if (hw->rss_ind_tbl_size == 0 ||
2990             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
2991                 hns3_err(hw, "the size of hash lookup table configured (%u)"
2992                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
2993                               HNS3_RSS_IND_TBL_SIZE_MAX);
2994                 return -EINVAL;
2995         }
2996
2997         return 0;
2998 }
2999
3000 static int
3001 hns3_query_dev_specifications(struct hns3_hw *hw)
3002 {
3003         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3004         int ret;
3005         int i;
3006
3007         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3008                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3009                                           true);
3010                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3011         }
3012         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3013
3014         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3015         if (ret)
3016                 return ret;
3017
3018         hns3_parse_dev_specifications(hw, desc);
3019
3020         return hns3_check_dev_specifications(hw);
3021 }
3022
3023 static int
3024 hns3_get_capability(struct hns3_hw *hw)
3025 {
3026         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3027         struct rte_pci_device *pci_dev;
3028         struct hns3_pf *pf = &hns->pf;
3029         struct rte_eth_dev *eth_dev;
3030         uint16_t device_id;
3031         uint8_t revision;
3032         int ret;
3033
3034         eth_dev = &rte_eth_devices[hw->data->port_id];
3035         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3036         device_id = pci_dev->id.device_id;
3037
3038         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3039             device_id == HNS3_DEV_ID_50GE_RDMA ||
3040             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3041             device_id == HNS3_DEV_ID_200G_RDMA)
3042                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3043
3044         /* Get PCI revision id */
3045         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3046                                   HNS3_PCI_REVISION_ID);
3047         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3048                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3049                              ret);
3050                 return -EIO;
3051         }
3052         hw->revision = revision;
3053
3054         if (revision < PCI_REVISION_ID_HIP09_A) {
3055                 hns3_set_default_dev_specifications(hw);
3056                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3057                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3058                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3059                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3060                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3061                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3062                 hw->rss_info.ipv6_sctp_offload_supported = false;
3063                 return 0;
3064         }
3065
3066         ret = hns3_query_dev_specifications(hw);
3067         if (ret) {
3068                 PMD_INIT_LOG(ERR,
3069                              "failed to query dev specifications, ret = %d",
3070                              ret);
3071                 return ret;
3072         }
3073
3074         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3075         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3076         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3077         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3078         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3079         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3080         hw->rss_info.ipv6_sctp_offload_supported = true;
3081
3082         return 0;
3083 }
3084
3085 static int
3086 hns3_get_board_configuration(struct hns3_hw *hw)
3087 {
3088         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3089         struct hns3_pf *pf = &hns->pf;
3090         struct hns3_cfg cfg;
3091         int ret;
3092
3093         ret = hns3_get_board_cfg(hw, &cfg);
3094         if (ret) {
3095                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3096                 return ret;
3097         }
3098
3099         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
3100             !hns3_dev_copper_supported(hw)) {
3101                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
3102                 return -EOPNOTSUPP;
3103         }
3104
3105         hw->mac.media_type = cfg.media_type;
3106         hw->rss_size_max = cfg.rss_size_max;
3107         hw->rss_dis_flag = false;
3108         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3109         hw->mac.phy_addr = cfg.phy_addr;
3110         hw->mac.default_addr_setted = false;
3111         hw->num_tx_desc = cfg.tqp_desc_num;
3112         hw->num_rx_desc = cfg.tqp_desc_num;
3113         hw->dcb_info.num_pg = 1;
3114         hw->dcb_info.hw_pfc_map = 0;
3115
3116         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3117         if (ret) {
3118                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3119                              cfg.default_speed, ret);
3120                 return ret;
3121         }
3122
3123         pf->tc_max = cfg.tc_num;
3124         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3125                 PMD_INIT_LOG(WARNING,
3126                              "Get TC num(%u) from flash, set TC num to 1",
3127                              pf->tc_max);
3128                 pf->tc_max = 1;
3129         }
3130
3131         /* Dev does not support DCB */
3132         if (!hns3_dev_dcb_supported(hw)) {
3133                 pf->tc_max = 1;
3134                 pf->pfc_max = 0;
3135         } else
3136                 pf->pfc_max = pf->tc_max;
3137
3138         hw->dcb_info.num_tc = 1;
3139         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3140                                      hw->tqps_num / hw->dcb_info.num_tc);
3141         hns3_set_bit(hw->hw_tc_map, 0, 1);
3142         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3143
3144         pf->wanted_umv_size = cfg.umv_space;
3145
3146         return ret;
3147 }
3148
3149 static int
3150 hns3_get_configuration(struct hns3_hw *hw)
3151 {
3152         int ret;
3153
3154         ret = hns3_query_function_status(hw);
3155         if (ret) {
3156                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3157                 return ret;
3158         }
3159
3160         /* Get device capability */
3161         ret = hns3_get_capability(hw);
3162         if (ret) {
3163                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3164                 return ret;
3165         }
3166
3167         /* Get pf resource */
3168         ret = hns3_query_pf_resource(hw);
3169         if (ret) {
3170                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3171                 return ret;
3172         }
3173
3174         ret = hns3_get_board_configuration(hw);
3175         if (ret) {
3176                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3177                 return ret;
3178         }
3179
3180         ret = hns3_query_dev_fec_info(hw);
3181         if (ret)
3182                 PMD_INIT_LOG(ERR,
3183                              "failed to query FEC information, ret = %d", ret);
3184
3185         return ret;
3186 }
3187
3188 static int
3189 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3190                       uint16_t tqp_vid, bool is_pf)
3191 {
3192         struct hns3_tqp_map_cmd *req;
3193         struct hns3_cmd_desc desc;
3194         int ret;
3195
3196         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3197
3198         req = (struct hns3_tqp_map_cmd *)desc.data;
3199         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3200         req->tqp_vf = func_id;
3201         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3202         if (!is_pf)
3203                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3204         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3205
3206         ret = hns3_cmd_send(hw, &desc, 1);
3207         if (ret)
3208                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3209
3210         return ret;
3211 }
3212
3213 static int
3214 hns3_map_tqp(struct hns3_hw *hw)
3215 {
3216         int ret;
3217         int i;
3218
3219         /*
3220          * In current version, VF is not supported when PF is driven by DPDK
3221          * driver, so we assign total tqps_num tqps allocated to this port
3222          * to PF.
3223          */
3224         for (i = 0; i < hw->total_tqps_num; i++) {
3225                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3226                 if (ret)
3227                         return ret;
3228         }
3229
3230         return 0;
3231 }
3232
3233 static int
3234 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3235 {
3236         struct hns3_config_mac_speed_dup_cmd *req;
3237         struct hns3_cmd_desc desc;
3238         int ret;
3239
3240         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3241
3242         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3243
3244         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3245
3246         switch (speed) {
3247         case ETH_SPEED_NUM_10M:
3248                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3249                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3250                 break;
3251         case ETH_SPEED_NUM_100M:
3252                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3253                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3254                 break;
3255         case ETH_SPEED_NUM_1G:
3256                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3257                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3258                 break;
3259         case ETH_SPEED_NUM_10G:
3260                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3261                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3262                 break;
3263         case ETH_SPEED_NUM_25G:
3264                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3265                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3266                 break;
3267         case ETH_SPEED_NUM_40G:
3268                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3269                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3270                 break;
3271         case ETH_SPEED_NUM_50G:
3272                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3273                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3274                 break;
3275         case ETH_SPEED_NUM_100G:
3276                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3277                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3278                 break;
3279         case ETH_SPEED_NUM_200G:
3280                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3281                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3282                 break;
3283         default:
3284                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3285                 return -EINVAL;
3286         }
3287
3288         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3289
3290         ret = hns3_cmd_send(hw, &desc, 1);
3291         if (ret)
3292                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3293
3294         return ret;
3295 }
3296
3297 static int
3298 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3299 {
3300         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3301         struct hns3_pf *pf = &hns->pf;
3302         struct hns3_priv_buf *priv;
3303         uint32_t i, total_size;
3304
3305         total_size = pf->pkt_buf_size;
3306
3307         /* alloc tx buffer for all enabled tc */
3308         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3309                 priv = &buf_alloc->priv_buf[i];
3310
3311                 if (hw->hw_tc_map & BIT(i)) {
3312                         if (total_size < pf->tx_buf_size)
3313                                 return -ENOMEM;
3314
3315                         priv->tx_buf_size = pf->tx_buf_size;
3316                 } else
3317                         priv->tx_buf_size = 0;
3318
3319                 total_size -= priv->tx_buf_size;
3320         }
3321
3322         return 0;
3323 }
3324
3325 static int
3326 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3327 {
3328 /* TX buffer size is unit by 128 byte */
3329 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3330 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3331         struct hns3_tx_buff_alloc_cmd *req;
3332         struct hns3_cmd_desc desc;
3333         uint32_t buf_size;
3334         uint32_t i;
3335         int ret;
3336
3337         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3338
3339         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3340         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3341                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3342
3343                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3344                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3345                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3346         }
3347
3348         ret = hns3_cmd_send(hw, &desc, 1);
3349         if (ret)
3350                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3351
3352         return ret;
3353 }
3354
3355 static int
3356 hns3_get_tc_num(struct hns3_hw *hw)
3357 {
3358         int cnt = 0;
3359         uint8_t i;
3360
3361         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3362                 if (hw->hw_tc_map & BIT(i))
3363                         cnt++;
3364         return cnt;
3365 }
3366
3367 static uint32_t
3368 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3369 {
3370         struct hns3_priv_buf *priv;
3371         uint32_t rx_priv = 0;
3372         int i;
3373
3374         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3375                 priv = &buf_alloc->priv_buf[i];
3376                 if (priv->enable)
3377                         rx_priv += priv->buf_size;
3378         }
3379         return rx_priv;
3380 }
3381
3382 static uint32_t
3383 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3384 {
3385         uint32_t total_tx_size = 0;
3386         uint32_t i;
3387
3388         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3389                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3390
3391         return total_tx_size;
3392 }
3393
3394 /* Get the number of pfc enabled TCs, which have private buffer */
3395 static int
3396 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3397 {
3398         struct hns3_priv_buf *priv;
3399         int cnt = 0;
3400         uint8_t i;
3401
3402         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3403                 priv = &buf_alloc->priv_buf[i];
3404                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3405                         cnt++;
3406         }
3407
3408         return cnt;
3409 }
3410
3411 /* Get the number of pfc disabled TCs, which have private buffer */
3412 static int
3413 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3414                          struct hns3_pkt_buf_alloc *buf_alloc)
3415 {
3416         struct hns3_priv_buf *priv;
3417         int cnt = 0;
3418         uint8_t i;
3419
3420         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3421                 priv = &buf_alloc->priv_buf[i];
3422                 if (hw->hw_tc_map & BIT(i) &&
3423                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3424                         cnt++;
3425         }
3426
3427         return cnt;
3428 }
3429
3430 static bool
3431 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3432                   uint32_t rx_all)
3433 {
3434         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3435         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3436         struct hns3_pf *pf = &hns->pf;
3437         uint32_t shared_buf, aligned_mps;
3438         uint32_t rx_priv;
3439         uint8_t tc_num;
3440         uint8_t i;
3441
3442         tc_num = hns3_get_tc_num(hw);
3443         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3444
3445         if (hns3_dev_dcb_supported(hw))
3446                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3447                                         pf->dv_buf_size;
3448         else
3449                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3450                                         + pf->dv_buf_size;
3451
3452         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3453         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3454                              HNS3_BUF_SIZE_UNIT);
3455
3456         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3457         if (rx_all < rx_priv + shared_std)
3458                 return false;
3459
3460         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3461         buf_alloc->s_buf.buf_size = shared_buf;
3462         if (hns3_dev_dcb_supported(hw)) {
3463                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3464                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3465                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3466                                   HNS3_BUF_SIZE_UNIT);
3467         } else {
3468                 buf_alloc->s_buf.self.high =
3469                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3470                 buf_alloc->s_buf.self.low = aligned_mps;
3471         }
3472
3473         if (hns3_dev_dcb_supported(hw)) {
3474                 hi_thrd = shared_buf - pf->dv_buf_size;
3475
3476                 if (tc_num <= NEED_RESERVE_TC_NUM)
3477                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3478                                   BUF_MAX_PERCENT;
3479
3480                 if (tc_num)
3481                         hi_thrd = hi_thrd / tc_num;
3482
3483                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3484                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3485                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3486         } else {
3487                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3488                 lo_thrd = aligned_mps;
3489         }
3490
3491         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3492                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3493                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3494         }
3495
3496         return true;
3497 }
3498
3499 static bool
3500 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3501                      struct hns3_pkt_buf_alloc *buf_alloc)
3502 {
3503         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3504         struct hns3_pf *pf = &hns->pf;
3505         struct hns3_priv_buf *priv;
3506         uint32_t aligned_mps;
3507         uint32_t rx_all;
3508         uint8_t i;
3509
3510         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3511         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3512
3513         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3514                 priv = &buf_alloc->priv_buf[i];
3515
3516                 priv->enable = 0;
3517                 priv->wl.low = 0;
3518                 priv->wl.high = 0;
3519                 priv->buf_size = 0;
3520
3521                 if (!(hw->hw_tc_map & BIT(i)))
3522                         continue;
3523
3524                 priv->enable = 1;
3525                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3526                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3527                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3528                                                 HNS3_BUF_SIZE_UNIT);
3529                 } else {
3530                         priv->wl.low = 0;
3531                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3532                                         aligned_mps;
3533                 }
3534
3535                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3536         }
3537
3538         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3539 }
3540
3541 static bool
3542 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3543                              struct hns3_pkt_buf_alloc *buf_alloc)
3544 {
3545         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3546         struct hns3_pf *pf = &hns->pf;
3547         struct hns3_priv_buf *priv;
3548         int no_pfc_priv_num;
3549         uint32_t rx_all;
3550         uint8_t mask;
3551         int i;
3552
3553         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3554         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3555
3556         /* let the last to be cleared first */
3557         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3558                 priv = &buf_alloc->priv_buf[i];
3559                 mask = BIT((uint8_t)i);
3560
3561                 if (hw->hw_tc_map & mask &&
3562                     !(hw->dcb_info.hw_pfc_map & mask)) {
3563                         /* Clear the no pfc TC private buffer */
3564                         priv->wl.low = 0;
3565                         priv->wl.high = 0;
3566                         priv->buf_size = 0;
3567                         priv->enable = 0;
3568                         no_pfc_priv_num--;
3569                 }
3570
3571                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3572                     no_pfc_priv_num == 0)
3573                         break;
3574         }
3575
3576         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3577 }
3578
3579 static bool
3580 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3581                            struct hns3_pkt_buf_alloc *buf_alloc)
3582 {
3583         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3584         struct hns3_pf *pf = &hns->pf;
3585         struct hns3_priv_buf *priv;
3586         uint32_t rx_all;
3587         int pfc_priv_num;
3588         uint8_t mask;
3589         int i;
3590
3591         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3592         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3593
3594         /* let the last to be cleared first */
3595         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3596                 priv = &buf_alloc->priv_buf[i];
3597                 mask = BIT((uint8_t)i);
3598                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3599                         /* Reduce the number of pfc TC with private buffer */
3600                         priv->wl.low = 0;
3601                         priv->enable = 0;
3602                         priv->wl.high = 0;
3603                         priv->buf_size = 0;
3604                         pfc_priv_num--;
3605                 }
3606                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3607                     pfc_priv_num == 0)
3608                         break;
3609         }
3610
3611         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3612 }
3613
3614 static bool
3615 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3616                           struct hns3_pkt_buf_alloc *buf_alloc)
3617 {
3618 #define COMPENSATE_BUFFER       0x3C00
3619 #define COMPENSATE_HALF_MPS_NUM 5
3620 #define PRIV_WL_GAP             0x1800
3621         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3622         struct hns3_pf *pf = &hns->pf;
3623         uint32_t tc_num = hns3_get_tc_num(hw);
3624         uint32_t half_mps = pf->mps >> 1;
3625         struct hns3_priv_buf *priv;
3626         uint32_t min_rx_priv;
3627         uint32_t rx_priv;
3628         uint8_t i;
3629
3630         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3631         if (tc_num)
3632                 rx_priv = rx_priv / tc_num;
3633
3634         if (tc_num <= NEED_RESERVE_TC_NUM)
3635                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3636
3637         /*
3638          * Minimum value of private buffer in rx direction (min_rx_priv) is
3639          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3640          * buffer if rx_priv is greater than min_rx_priv.
3641          */
3642         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3643                         COMPENSATE_HALF_MPS_NUM * half_mps;
3644         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3645         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3646
3647         if (rx_priv < min_rx_priv)
3648                 return false;
3649
3650         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3651                 priv = &buf_alloc->priv_buf[i];
3652                 priv->enable = 0;
3653                 priv->wl.low = 0;
3654                 priv->wl.high = 0;
3655                 priv->buf_size = 0;
3656
3657                 if (!(hw->hw_tc_map & BIT(i)))
3658                         continue;
3659
3660                 priv->enable = 1;
3661                 priv->buf_size = rx_priv;
3662                 priv->wl.high = rx_priv - pf->dv_buf_size;
3663                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3664         }
3665
3666         buf_alloc->s_buf.buf_size = 0;
3667
3668         return true;
3669 }
3670
3671 /*
3672  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3673  * @hw: pointer to struct hns3_hw
3674  * @buf_alloc: pointer to buffer calculation data
3675  * @return: 0: calculate sucessful, negative: fail
3676  */
3677 static int
3678 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3679 {
3680         /* When DCB is not supported, rx private buffer is not allocated. */
3681         if (!hns3_dev_dcb_supported(hw)) {
3682                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3683                 struct hns3_pf *pf = &hns->pf;
3684                 uint32_t rx_all = pf->pkt_buf_size;
3685
3686                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3687                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3688                         return -ENOMEM;
3689
3690                 return 0;
3691         }
3692
3693         /*
3694          * Try to allocate privated packet buffer for all TCs without share
3695          * buffer.
3696          */
3697         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3698                 return 0;
3699
3700         /*
3701          * Try to allocate privated packet buffer for all TCs with share
3702          * buffer.
3703          */
3704         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3705                 return 0;
3706
3707         /*
3708          * For different application scenes, the enabled port number, TC number
3709          * and no_drop TC number are different. In order to obtain the better
3710          * performance, software could allocate the buffer size and configure
3711          * the waterline by tring to decrease the private buffer size according
3712          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3713          * enabled tc.
3714          */
3715         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3716                 return 0;
3717
3718         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3719                 return 0;
3720
3721         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3722                 return 0;
3723
3724         return -ENOMEM;
3725 }
3726
3727 static int
3728 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3729 {
3730         struct hns3_rx_priv_buff_cmd *req;
3731         struct hns3_cmd_desc desc;
3732         uint32_t buf_size;
3733         int ret;
3734         int i;
3735
3736         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3737         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3738
3739         /* Alloc private buffer TCs */
3740         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3741                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3742
3743                 req->buf_num[i] =
3744                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3745                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3746         }
3747
3748         buf_size = buf_alloc->s_buf.buf_size;
3749         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3750                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3751
3752         ret = hns3_cmd_send(hw, &desc, 1);
3753         if (ret)
3754                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3755
3756         return ret;
3757 }
3758
3759 static int
3760 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3761 {
3762 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3763         struct hns3_rx_priv_wl_buf *req;
3764         struct hns3_priv_buf *priv;
3765         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3766         int i, j;
3767         int ret;
3768
3769         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3770                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3771                                           false);
3772                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3773
3774                 /* The first descriptor set the NEXT bit to 1 */
3775                 if (i == 0)
3776                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3777                 else
3778                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3779
3780                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3781                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3782
3783                         priv = &buf_alloc->priv_buf[idx];
3784                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3785                                                         HNS3_BUF_UNIT_S);
3786                         req->tc_wl[j].high |=
3787                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3788                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3789                                                         HNS3_BUF_UNIT_S);
3790                         req->tc_wl[j].low |=
3791                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3792                 }
3793         }
3794
3795         /* Send 2 descriptor at one time */
3796         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3797         if (ret)
3798                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3799                              ret);
3800         return ret;
3801 }
3802
3803 static int
3804 hns3_common_thrd_config(struct hns3_hw *hw,
3805                         struct hns3_pkt_buf_alloc *buf_alloc)
3806 {
3807 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3808         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3809         struct hns3_rx_com_thrd *req;
3810         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3811         struct hns3_tc_thrd *tc;
3812         int tc_idx;
3813         int i, j;
3814         int ret;
3815
3816         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3817                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3818                                           false);
3819                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3820
3821                 /* The first descriptor set the NEXT bit to 1 */
3822                 if (i == 0)
3823                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3824                 else
3825                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3826
3827                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3828                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3829                         tc = &s_buf->tc_thrd[tc_idx];
3830
3831                         req->com_thrd[j].high =
3832                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3833                         req->com_thrd[j].high |=
3834                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3835                         req->com_thrd[j].low =
3836                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3837                         req->com_thrd[j].low |=
3838                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3839                 }
3840         }
3841
3842         /* Send 2 descriptors at one time */
3843         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3844         if (ret)
3845                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3846
3847         return ret;
3848 }
3849
3850 static int
3851 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3852 {
3853         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3854         struct hns3_rx_com_wl *req;
3855         struct hns3_cmd_desc desc;
3856         int ret;
3857
3858         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3859
3860         req = (struct hns3_rx_com_wl *)desc.data;
3861         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3862         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3863
3864         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3865         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3866
3867         ret = hns3_cmd_send(hw, &desc, 1);
3868         if (ret)
3869                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3870
3871         return ret;
3872 }
3873
3874 int
3875 hns3_buffer_alloc(struct hns3_hw *hw)
3876 {
3877         struct hns3_pkt_buf_alloc pkt_buf;
3878         int ret;
3879
3880         memset(&pkt_buf, 0, sizeof(pkt_buf));
3881         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3882         if (ret) {
3883                 PMD_INIT_LOG(ERR,
3884                              "could not calc tx buffer size for all TCs %d",
3885                              ret);
3886                 return ret;
3887         }
3888
3889         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3890         if (ret) {
3891                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3892                 return ret;
3893         }
3894
3895         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3896         if (ret) {
3897                 PMD_INIT_LOG(ERR,
3898                              "could not calc rx priv buffer size for all TCs %d",
3899                              ret);
3900                 return ret;
3901         }
3902
3903         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3904         if (ret) {
3905                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3906                 return ret;
3907         }
3908
3909         if (hns3_dev_dcb_supported(hw)) {
3910                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3911                 if (ret) {
3912                         PMD_INIT_LOG(ERR,
3913                                      "could not configure rx private waterline %d",
3914                                      ret);
3915                         return ret;
3916                 }
3917
3918                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3919                 if (ret) {
3920                         PMD_INIT_LOG(ERR,
3921                                      "could not configure common threshold %d",
3922                                      ret);
3923                         return ret;
3924                 }
3925         }
3926
3927         ret = hns3_common_wl_config(hw, &pkt_buf);
3928         if (ret)
3929                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3930                              ret);
3931
3932         return ret;
3933 }
3934
3935 static int
3936 hns3_firmware_compat_config(struct hns3_hw *hw, bool is_init)
3937 {
3938         struct hns3_firmware_compat_cmd *req;
3939         struct hns3_cmd_desc desc;
3940         uint32_t compat = 0;
3941
3942         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_FIRMWARE_COMPAT_CFG, false);
3943         req = (struct hns3_firmware_compat_cmd *)desc.data;
3944
3945         if (is_init) {
3946                 hns3_set_bit(compat, HNS3_LINK_EVENT_REPORT_EN_B, 1);
3947                 hns3_set_bit(compat, HNS3_NCSI_ERROR_REPORT_EN_B, 0);
3948         }
3949
3950         req->compat = rte_cpu_to_le_32(compat);
3951
3952         return hns3_cmd_send(hw, &desc, 1);
3953 }
3954
3955 static int
3956 hns3_mac_init(struct hns3_hw *hw)
3957 {
3958         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3959         struct hns3_mac *mac = &hw->mac;
3960         struct hns3_pf *pf = &hns->pf;
3961         int ret;
3962
3963         pf->support_sfp_query = true;
3964         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3965         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3966         if (ret) {
3967                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3968                 return ret;
3969         }
3970
3971         mac->link_status = ETH_LINK_DOWN;
3972
3973         return hns3_config_mtu(hw, pf->mps);
3974 }
3975
3976 static int
3977 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3978 {
3979 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3980 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3981 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3982 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3983         int return_status;
3984
3985         if (cmdq_resp) {
3986                 PMD_INIT_LOG(ERR,
3987                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
3988                              cmdq_resp);
3989                 return -EIO;
3990         }
3991
3992         switch (resp_code) {
3993         case HNS3_ETHERTYPE_SUCCESS_ADD:
3994         case HNS3_ETHERTYPE_ALREADY_ADD:
3995                 return_status = 0;
3996                 break;
3997         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3998                 PMD_INIT_LOG(ERR,
3999                              "add mac ethertype failed for manager table overflow.");
4000                 return_status = -EIO;
4001                 break;
4002         case HNS3_ETHERTYPE_KEY_CONFLICT:
4003                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4004                 return_status = -EIO;
4005                 break;
4006         default:
4007                 PMD_INIT_LOG(ERR,
4008                              "add mac ethertype failed for undefined, code=%u.",
4009                              resp_code);
4010                 return_status = -EIO;
4011                 break;
4012         }
4013
4014         return return_status;
4015 }
4016
4017 static int
4018 hns3_add_mgr_tbl(struct hns3_hw *hw,
4019                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4020 {
4021         struct hns3_cmd_desc desc;
4022         uint8_t resp_code;
4023         uint16_t retval;
4024         int ret;
4025
4026         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4027         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4028
4029         ret = hns3_cmd_send(hw, &desc, 1);
4030         if (ret) {
4031                 PMD_INIT_LOG(ERR,
4032                              "add mac ethertype failed for cmd_send, ret =%d.",
4033                              ret);
4034                 return ret;
4035         }
4036
4037         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4038         retval = rte_le_to_cpu_16(desc.retval);
4039
4040         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4041 }
4042
4043 static void
4044 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4045                      int *table_item_num)
4046 {
4047         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4048
4049         /*
4050          * In current version, we add one item in management table as below:
4051          * 0x0180C200000E -- LLDP MC address
4052          */
4053         tbl = mgr_table;
4054         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4055         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4056         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4057         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4058         tbl->i_port_bitmap = 0x1;
4059         *table_item_num = 1;
4060 }
4061
4062 static int
4063 hns3_init_mgr_tbl(struct hns3_hw *hw)
4064 {
4065 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4066         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4067         int table_item_num;
4068         int ret;
4069         int i;
4070
4071         memset(mgr_table, 0, sizeof(mgr_table));
4072         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4073         for (i = 0; i < table_item_num; i++) {
4074                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4075                 if (ret) {
4076                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4077                                      ret);
4078                         return ret;
4079                 }
4080         }
4081
4082         return 0;
4083 }
4084
4085 static void
4086 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4087                         bool en_mc, bool en_bc, int vport_id)
4088 {
4089         if (!param)
4090                 return;
4091
4092         memset(param, 0, sizeof(struct hns3_promisc_param));
4093         if (en_uc)
4094                 param->enable = HNS3_PROMISC_EN_UC;
4095         if (en_mc)
4096                 param->enable |= HNS3_PROMISC_EN_MC;
4097         if (en_bc)
4098                 param->enable |= HNS3_PROMISC_EN_BC;
4099         param->vf_id = vport_id;
4100 }
4101
4102 static int
4103 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4104 {
4105         struct hns3_promisc_cfg_cmd *req;
4106         struct hns3_cmd_desc desc;
4107         int ret;
4108
4109         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4110
4111         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4112         req->vf_id = param->vf_id;
4113         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4114             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4115
4116         ret = hns3_cmd_send(hw, &desc, 1);
4117         if (ret)
4118                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4119
4120         return ret;
4121 }
4122
4123 static int
4124 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4125 {
4126         struct hns3_promisc_param param;
4127         bool en_bc_pmc = true;
4128         uint8_t vf_id;
4129
4130         /*
4131          * In current version VF is not supported when PF is driven by DPDK
4132          * driver, just need to configure parameters for PF vport.
4133          */
4134         vf_id = HNS3_PF_FUNC_ID;
4135
4136         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4137         return hns3_cmd_set_promisc_mode(hw, &param);
4138 }
4139
4140 static int
4141 hns3_promisc_init(struct hns3_hw *hw)
4142 {
4143         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4144         struct hns3_pf *pf = &hns->pf;
4145         struct hns3_promisc_param param;
4146         uint16_t func_id;
4147         int ret;
4148
4149         ret = hns3_set_promisc_mode(hw, false, false);
4150         if (ret) {
4151                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4152                 return ret;
4153         }
4154
4155         /*
4156          * In current version VFs are not supported when PF is driven by DPDK
4157          * driver. After PF has been taken over by DPDK, the original VF will
4158          * be invalid. So, there is a possibility of entry residues. It should
4159          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4160          * during init.
4161          */
4162         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4163                 hns3_promisc_param_init(&param, false, false, false, func_id);
4164                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4165                 if (ret) {
4166                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4167                                         " ret = %d", func_id, ret);
4168                         return ret;
4169                 }
4170         }
4171
4172         return 0;
4173 }
4174
4175 static void
4176 hns3_promisc_uninit(struct hns3_hw *hw)
4177 {
4178         struct hns3_promisc_param param;
4179         uint16_t func_id;
4180         int ret;
4181
4182         func_id = HNS3_PF_FUNC_ID;
4183
4184         /*
4185          * In current version VFs are not supported when PF is driven by
4186          * DPDK driver, and VFs' promisc mode status has been cleared during
4187          * init and their status will not change. So just clear PF's promisc
4188          * mode status during uninit.
4189          */
4190         hns3_promisc_param_init(&param, false, false, false, func_id);
4191         ret = hns3_cmd_set_promisc_mode(hw, &param);
4192         if (ret)
4193                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4194                                 " uninit, ret = %d", ret);
4195 }
4196
4197 static int
4198 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4199 {
4200         bool allmulti = dev->data->all_multicast ? true : false;
4201         struct hns3_adapter *hns = dev->data->dev_private;
4202         struct hns3_hw *hw = &hns->hw;
4203         uint64_t offloads;
4204         int err;
4205         int ret;
4206
4207         rte_spinlock_lock(&hw->lock);
4208         ret = hns3_set_promisc_mode(hw, true, true);
4209         if (ret) {
4210                 rte_spinlock_unlock(&hw->lock);
4211                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4212                          ret);
4213                 return ret;
4214         }
4215
4216         /*
4217          * When promiscuous mode was enabled, disable the vlan filter to let
4218          * all packets coming in in the receiving direction.
4219          */
4220         offloads = dev->data->dev_conf.rxmode.offloads;
4221         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4222                 ret = hns3_enable_vlan_filter(hns, false);
4223                 if (ret) {
4224                         hns3_err(hw, "failed to enable promiscuous mode due to "
4225                                      "failure to disable vlan filter, ret = %d",
4226                                  ret);
4227                         err = hns3_set_promisc_mode(hw, false, allmulti);
4228                         if (err)
4229                                 hns3_err(hw, "failed to restore promiscuous "
4230                                          "status after disable vlan filter "
4231                                          "failed during enabling promiscuous "
4232                                          "mode, ret = %d", ret);
4233                 }
4234         }
4235
4236         rte_spinlock_unlock(&hw->lock);
4237
4238         return ret;
4239 }
4240
4241 static int
4242 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4243 {
4244         bool allmulti = dev->data->all_multicast ? true : false;
4245         struct hns3_adapter *hns = dev->data->dev_private;
4246         struct hns3_hw *hw = &hns->hw;
4247         uint64_t offloads;
4248         int err;
4249         int ret;
4250
4251         /* If now in all_multicast mode, must remain in all_multicast mode. */
4252         rte_spinlock_lock(&hw->lock);
4253         ret = hns3_set_promisc_mode(hw, false, allmulti);
4254         if (ret) {
4255                 rte_spinlock_unlock(&hw->lock);
4256                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4257                          ret);
4258                 return ret;
4259         }
4260         /* when promiscuous mode was disabled, restore the vlan filter status */
4261         offloads = dev->data->dev_conf.rxmode.offloads;
4262         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4263                 ret = hns3_enable_vlan_filter(hns, true);
4264                 if (ret) {
4265                         hns3_err(hw, "failed to disable promiscuous mode due to"
4266                                  " failure to restore vlan filter, ret = %d",
4267                                  ret);
4268                         err = hns3_set_promisc_mode(hw, true, true);
4269                         if (err)
4270                                 hns3_err(hw, "failed to restore promiscuous "
4271                                          "status after enabling vlan filter "
4272                                          "failed during disabling promiscuous "
4273                                          "mode, ret = %d", ret);
4274                 }
4275         }
4276         rte_spinlock_unlock(&hw->lock);
4277
4278         return ret;
4279 }
4280
4281 static int
4282 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4283 {
4284         struct hns3_adapter *hns = dev->data->dev_private;
4285         struct hns3_hw *hw = &hns->hw;
4286         int ret;
4287
4288         if (dev->data->promiscuous)
4289                 return 0;
4290
4291         rte_spinlock_lock(&hw->lock);
4292         ret = hns3_set_promisc_mode(hw, false, true);
4293         rte_spinlock_unlock(&hw->lock);
4294         if (ret)
4295                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4296                          ret);
4297
4298         return ret;
4299 }
4300
4301 static int
4302 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4303 {
4304         struct hns3_adapter *hns = dev->data->dev_private;
4305         struct hns3_hw *hw = &hns->hw;
4306         int ret;
4307
4308         /* If now in promiscuous mode, must remain in all_multicast mode. */
4309         if (dev->data->promiscuous)
4310                 return 0;
4311
4312         rte_spinlock_lock(&hw->lock);
4313         ret = hns3_set_promisc_mode(hw, false, false);
4314         rte_spinlock_unlock(&hw->lock);
4315         if (ret)
4316                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4317                          ret);
4318
4319         return ret;
4320 }
4321
4322 static int
4323 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4324 {
4325         struct hns3_hw *hw = &hns->hw;
4326         bool allmulti = hw->data->all_multicast ? true : false;
4327         int ret;
4328
4329         if (hw->data->promiscuous) {
4330                 ret = hns3_set_promisc_mode(hw, true, true);
4331                 if (ret)
4332                         hns3_err(hw, "failed to restore promiscuous mode, "
4333                                  "ret = %d", ret);
4334                 return ret;
4335         }
4336
4337         ret = hns3_set_promisc_mode(hw, false, allmulti);
4338         if (ret)
4339                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4340                          ret);
4341         return ret;
4342 }
4343
4344 static int
4345 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4346 {
4347         struct hns3_sfp_speed_cmd *resp;
4348         struct hns3_cmd_desc desc;
4349         int ret;
4350
4351         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4352         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4353         ret = hns3_cmd_send(hw, &desc, 1);
4354         if (ret == -EOPNOTSUPP) {
4355                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4356                 return ret;
4357         } else if (ret) {
4358                 hns3_err(hw, "get sfp speed failed %d", ret);
4359                 return ret;
4360         }
4361
4362         *speed = resp->sfp_speed;
4363
4364         return 0;
4365 }
4366
4367 static uint8_t
4368 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4369 {
4370         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4371                 duplex = ETH_LINK_FULL_DUPLEX;
4372
4373         return duplex;
4374 }
4375
4376 static int
4377 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4378 {
4379         struct hns3_mac *mac = &hw->mac;
4380         uint32_t cur_speed = mac->link_speed;
4381         int ret;
4382
4383         duplex = hns3_check_speed_dup(duplex, speed);
4384         if (mac->link_speed == speed && mac->link_duplex == duplex)
4385                 return 0;
4386
4387         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4388         if (ret)
4389                 return ret;
4390
4391         mac->link_speed = speed;
4392         ret = hns3_dcb_port_shaper_cfg(hw);
4393         if (ret) {
4394                 hns3_err(hw, "failed to configure port shaper, ret = %d.", ret);
4395                 mac->link_speed = cur_speed;
4396                 return ret;
4397         }
4398
4399         mac->link_duplex = duplex;
4400
4401         return 0;
4402 }
4403
4404 static int
4405 hns3_update_fiber_link_info(struct hns3_hw *hw)
4406 {
4407         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4408         uint32_t speed;
4409         int ret;
4410
4411         /* If IMP do not support get SFP/qSFP speed, return directly */
4412         if (!pf->support_sfp_query)
4413                 return 0;
4414
4415         ret = hns3_get_sfp_speed(hw, &speed);
4416         if (ret == -EOPNOTSUPP) {
4417                 pf->support_sfp_query = false;
4418                 return ret;
4419         } else if (ret)
4420                 return ret;
4421
4422         if (speed == ETH_SPEED_NUM_NONE)
4423                 return 0; /* do nothing if no SFP */
4424
4425         /* Config full duplex for SFP */
4426         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4427 }
4428
4429 static int
4430 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4431 {
4432         struct hns3_adapter *hns = eth_dev->data->dev_private;
4433         struct hns3_hw *hw = &hns->hw;
4434         int ret = 0;
4435
4436         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4437                 return 0;
4438         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4439                 ret = hns3_update_fiber_link_info(hw);
4440
4441         return ret;
4442 }
4443
4444 static int
4445 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4446 {
4447         struct hns3_config_mac_mode_cmd *req;
4448         struct hns3_cmd_desc desc;
4449         uint32_t loop_en = 0;
4450         uint8_t val = 0;
4451         int ret;
4452
4453         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4454
4455         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4456         if (enable)
4457                 val = 1;
4458         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4459         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4460         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4461         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4462         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4463         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4464         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4465         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4466         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4467         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4468
4469         /*
4470          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4471          * when receiving frames. Otherwise, CRC will be stripped.
4472          */
4473         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4474                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4475         else
4476                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4477         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4478         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4479         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4480         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4481
4482         ret = hns3_cmd_send(hw, &desc, 1);
4483         if (ret)
4484                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4485
4486         return ret;
4487 }
4488
4489 static int
4490 hns3_get_mac_link_status(struct hns3_hw *hw)
4491 {
4492         struct hns3_link_status_cmd *req;
4493         struct hns3_cmd_desc desc;
4494         int link_status;
4495         int ret;
4496
4497         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4498         ret = hns3_cmd_send(hw, &desc, 1);
4499         if (ret) {
4500                 hns3_err(hw, "get link status cmd failed %d", ret);
4501                 return ETH_LINK_DOWN;
4502         }
4503
4504         req = (struct hns3_link_status_cmd *)desc.data;
4505         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4506
4507         return !!link_status;
4508 }
4509
4510 static bool
4511 hns3_update_link_status(struct hns3_hw *hw)
4512 {
4513         int state;
4514
4515         state = hns3_get_mac_link_status(hw);
4516         if (state != hw->mac.link_status) {
4517                 hw->mac.link_status = state;
4518                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4519                 return true;
4520         }
4521
4522         return false;
4523 }
4524
4525 /*
4526  * Current, the PF driver get link status by two ways:
4527  * 1) Periodic polling in the intr thread context, driver call
4528  *    hns3_update_link_status to update link status.
4529  * 2) Firmware report async interrupt, driver process the event in the intr
4530  *    thread context, and call hns3_update_link_status to update link status.
4531  *
4532  * If detect link status changed, driver need report LSE. One method is add the
4533  * report LSE logic in hns3_update_link_status.
4534  *
4535  * But the PF driver ops(link_update) also call hns3_update_link_status to
4536  * update link status.
4537  * If we report LSE in hns3_update_link_status, it may lead to deadlock in the
4538  * bonding application.
4539  *
4540  * So add the one new API which used only in intr thread context.
4541  */
4542 void
4543 hns3_update_link_status_and_event(struct hns3_hw *hw)
4544 {
4545         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4546         bool changed = hns3_update_link_status(hw);
4547         if (changed)
4548                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4549 }
4550
4551 static void
4552 hns3_service_handler(void *param)
4553 {
4554         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4555         struct hns3_adapter *hns = eth_dev->data->dev_private;
4556         struct hns3_hw *hw = &hns->hw;
4557
4558         if (!hns3_is_reset_pending(hns)) {
4559                 hns3_update_link_status_and_event(hw);
4560                 hns3_update_link_info(eth_dev);
4561         } else {
4562                 hns3_warn(hw, "Cancel the query when reset is pending");
4563         }
4564
4565         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4566 }
4567
4568 static int
4569 hns3_init_hardware(struct hns3_adapter *hns)
4570 {
4571         struct hns3_hw *hw = &hns->hw;
4572         int ret;
4573
4574         ret = hns3_map_tqp(hw);
4575         if (ret) {
4576                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4577                 return ret;
4578         }
4579
4580         ret = hns3_init_umv_space(hw);
4581         if (ret) {
4582                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4583                 return ret;
4584         }
4585
4586         ret = hns3_mac_init(hw);
4587         if (ret) {
4588                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4589                 goto err_mac_init;
4590         }
4591
4592         ret = hns3_init_mgr_tbl(hw);
4593         if (ret) {
4594                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4595                 goto err_mac_init;
4596         }
4597
4598         ret = hns3_promisc_init(hw);
4599         if (ret) {
4600                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4601                              ret);
4602                 goto err_mac_init;
4603         }
4604
4605         ret = hns3_init_vlan_config(hns);
4606         if (ret) {
4607                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4608                 goto err_mac_init;
4609         }
4610
4611         ret = hns3_dcb_init(hw);
4612         if (ret) {
4613                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4614                 goto err_mac_init;
4615         }
4616
4617         ret = hns3_init_fd_config(hns);
4618         if (ret) {
4619                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4620                 goto err_mac_init;
4621         }
4622
4623         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4624         if (ret) {
4625                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4626                 goto err_mac_init;
4627         }
4628
4629         ret = hns3_config_gro(hw, false);
4630         if (ret) {
4631                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4632                 goto err_mac_init;
4633         }
4634
4635         /*
4636          * In the initialization clearing the all hardware mapping relationship
4637          * configurations between queues and interrupt vectors is needed, so
4638          * some error caused by the residual configurations, such as the
4639          * unexpected interrupt, can be avoid.
4640          */
4641         ret = hns3_init_ring_with_vector(hw);
4642         if (ret) {
4643                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4644                 goto err_mac_init;
4645         }
4646
4647         /*
4648          * Requiring firmware to enable some features, driver can
4649          * still work without it.
4650          */
4651         ret = hns3_firmware_compat_config(hw, true);
4652         if (ret)
4653                 PMD_INIT_LOG(WARNING, "firmware compatible features not "
4654                              "supported, ret = %d.", ret);
4655
4656         return 0;
4657
4658 err_mac_init:
4659         hns3_uninit_umv_space(hw);
4660         return ret;
4661 }
4662
4663 static int
4664 hns3_clear_hw(struct hns3_hw *hw)
4665 {
4666         struct hns3_cmd_desc desc;
4667         int ret;
4668
4669         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4670
4671         ret = hns3_cmd_send(hw, &desc, 1);
4672         if (ret && ret != -EOPNOTSUPP)
4673                 return ret;
4674
4675         return 0;
4676 }
4677
4678 static void
4679 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4680 {
4681         uint32_t val;
4682
4683         /*
4684          * The new firmware support report more hardware error types by
4685          * msix mode. These errors are defined as RAS errors in hardware
4686          * and belong to a different type from the MSI-x errors processed
4687          * by the network driver.
4688          *
4689          * Network driver should open the new error report on initialition
4690          */
4691         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4692         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4693         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4694 }
4695
4696 static int
4697 hns3_init_pf(struct rte_eth_dev *eth_dev)
4698 {
4699         struct rte_device *dev = eth_dev->device;
4700         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4701         struct hns3_adapter *hns = eth_dev->data->dev_private;
4702         struct hns3_hw *hw = &hns->hw;
4703         int ret;
4704
4705         PMD_INIT_FUNC_TRACE();
4706
4707         /* Get hardware io base address from pcie BAR2 IO space */
4708         hw->io_base = pci_dev->mem_resource[2].addr;
4709
4710         /* Firmware command queue initialize */
4711         ret = hns3_cmd_init_queue(hw);
4712         if (ret) {
4713                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4714                 goto err_cmd_init_queue;
4715         }
4716
4717         hns3_clear_all_event_cause(hw);
4718
4719         /* Firmware command initialize */
4720         ret = hns3_cmd_init(hw);
4721         if (ret) {
4722                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4723                 goto err_cmd_init;
4724         }
4725
4726         /*
4727          * To ensure that the hardware environment is clean during
4728          * initialization, the driver actively clear the hardware environment
4729          * during initialization, including PF and corresponding VFs' vlan, mac,
4730          * flow table configurations, etc.
4731          */
4732         ret = hns3_clear_hw(hw);
4733         if (ret) {
4734                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4735                 goto err_cmd_init;
4736         }
4737
4738         hns3_config_all_msix_error(hw, true);
4739
4740         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4741                                          hns3_interrupt_handler,
4742                                          eth_dev);
4743         if (ret) {
4744                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4745                 goto err_intr_callback_register;
4746         }
4747
4748         /* Enable interrupt */
4749         rte_intr_enable(&pci_dev->intr_handle);
4750         hns3_pf_enable_irq0(hw);
4751
4752         /* Get configuration */
4753         ret = hns3_get_configuration(hw);
4754         if (ret) {
4755                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4756                 goto err_get_config;
4757         }
4758
4759         ret = hns3_tqp_stats_init(hw);
4760         if (ret)
4761                 goto err_get_config;
4762
4763         ret = hns3_init_hardware(hns);
4764         if (ret) {
4765                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4766                 goto err_init_hw;
4767         }
4768
4769         /* Initialize flow director filter list & hash */
4770         ret = hns3_fdir_filter_init(hns);
4771         if (ret) {
4772                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4773                 goto err_fdir;
4774         }
4775
4776         hns3_rss_set_default_args(hw);
4777
4778         ret = hns3_enable_hw_error_intr(hns, true);
4779         if (ret) {
4780                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4781                              ret);
4782                 goto err_enable_intr;
4783         }
4784
4785         hns3_tm_conf_init(eth_dev);
4786
4787         return 0;
4788
4789 err_enable_intr:
4790         hns3_fdir_filter_uninit(hns);
4791 err_fdir:
4792         (void)hns3_firmware_compat_config(hw, false);
4793         hns3_uninit_umv_space(hw);
4794 err_init_hw:
4795         hns3_tqp_stats_uninit(hw);
4796 err_get_config:
4797         hns3_pf_disable_irq0(hw);
4798         rte_intr_disable(&pci_dev->intr_handle);
4799         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4800                              eth_dev);
4801 err_intr_callback_register:
4802 err_cmd_init:
4803         hns3_cmd_uninit(hw);
4804         hns3_cmd_destroy_queue(hw);
4805 err_cmd_init_queue:
4806         hw->io_base = NULL;
4807
4808         return ret;
4809 }
4810
4811 static void
4812 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4813 {
4814         struct hns3_adapter *hns = eth_dev->data->dev_private;
4815         struct rte_device *dev = eth_dev->device;
4816         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4817         struct hns3_hw *hw = &hns->hw;
4818
4819         PMD_INIT_FUNC_TRACE();
4820
4821         hns3_tm_conf_uninit(eth_dev);
4822         hns3_enable_hw_error_intr(hns, false);
4823         hns3_rss_uninit(hns);
4824         (void)hns3_config_gro(hw, false);
4825         hns3_promisc_uninit(hw);
4826         hns3_fdir_filter_uninit(hns);
4827         (void)hns3_firmware_compat_config(hw, false);
4828         hns3_uninit_umv_space(hw);
4829         hns3_tqp_stats_uninit(hw);
4830         hns3_pf_disable_irq0(hw);
4831         rte_intr_disable(&pci_dev->intr_handle);
4832         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4833                              eth_dev);
4834         hns3_config_all_msix_error(hw, false);
4835         hns3_cmd_uninit(hw);
4836         hns3_cmd_destroy_queue(hw);
4837         hw->io_base = NULL;
4838 }
4839
4840 static int
4841 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4842 {
4843         struct hns3_hw *hw = &hns->hw;
4844         int ret;
4845
4846         ret = hns3_dcb_cfg_update(hns);
4847         if (ret)
4848                 return ret;
4849
4850         /*
4851          * The hns3_dcb_cfg_update may configure TM module, so
4852          * hns3_tm_conf_update must called later.
4853          */
4854         ret = hns3_tm_conf_update(hw);
4855         if (ret) {
4856                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
4857                 return ret;
4858         }
4859
4860         ret = hns3_init_queues(hns, reset_queue);
4861         if (ret) {
4862                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
4863                 return ret;
4864         }
4865
4866         ret = hns3_cfg_mac_mode(hw, true);
4867         if (ret) {
4868                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
4869                 goto err_config_mac_mode;
4870         }
4871         return 0;
4872
4873 err_config_mac_mode:
4874         hns3_dev_release_mbufs(hns);
4875         /*
4876          * Here is exception handling, hns3_reset_all_tqps will have the
4877          * corresponding error message if it is handled incorrectly, so it is
4878          * not necessary to check hns3_reset_all_tqps return value, here keep
4879          * ret as the error code causing the exception.
4880          */
4881         (void)hns3_reset_all_tqps(hns);
4882         return ret;
4883 }
4884
4885 static int
4886 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4887 {
4888         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4889         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4890         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4891         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
4892         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4893         uint32_t intr_vector;
4894         uint16_t q_id;
4895         int ret;
4896
4897         /*
4898          * hns3 needs a separate interrupt to be used as event interrupt which
4899          * could not be shared with task queue pair, so KERNEL drivers need
4900          * support multiple interrupt vectors.
4901          */
4902         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
4903             !rte_intr_cap_multiple(intr_handle))
4904                 return 0;
4905
4906         rte_intr_disable(intr_handle);
4907         intr_vector = hw->used_rx_queues;
4908         /* creates event fd for each intr vector when MSIX is used */
4909         if (rte_intr_efd_enable(intr_handle, intr_vector))
4910                 return -EINVAL;
4911
4912         if (intr_handle->intr_vec == NULL) {
4913                 intr_handle->intr_vec =
4914                         rte_zmalloc("intr_vec",
4915                                     hw->used_rx_queues * sizeof(int), 0);
4916                 if (intr_handle->intr_vec == NULL) {
4917                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
4918                                         hw->used_rx_queues);
4919                         ret = -ENOMEM;
4920                         goto alloc_intr_vec_error;
4921                 }
4922         }
4923
4924         if (rte_intr_allow_others(intr_handle)) {
4925                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4926                 base = RTE_INTR_VEC_RXTX_OFFSET;
4927         }
4928
4929         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4930                 ret = hns3_bind_ring_with_vector(hw, vec, true,
4931                                                  HNS3_RING_TYPE_RX, q_id);
4932                 if (ret)
4933                         goto bind_vector_error;
4934                 intr_handle->intr_vec[q_id] = vec;
4935                 /*
4936                  * If there are not enough efds (e.g. not enough interrupt),
4937                  * remaining queues will be bond to the last interrupt.
4938                  */
4939                 if (vec < base + intr_handle->nb_efd - 1)
4940                         vec++;
4941         }
4942         rte_intr_enable(intr_handle);
4943         return 0;
4944
4945 bind_vector_error:
4946         rte_free(intr_handle->intr_vec);
4947         intr_handle->intr_vec = NULL;
4948 alloc_intr_vec_error:
4949         rte_intr_efd_disable(intr_handle);
4950         return ret;
4951 }
4952
4953 static int
4954 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4955 {
4956         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4957         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4958         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4959         uint16_t q_id;
4960         int ret;
4961
4962         if (dev->data->dev_conf.intr_conf.rxq == 0)
4963                 return 0;
4964
4965         if (rte_intr_dp_is_en(intr_handle)) {
4966                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4967                         ret = hns3_bind_ring_with_vector(hw,
4968                                         intr_handle->intr_vec[q_id], true,
4969                                         HNS3_RING_TYPE_RX, q_id);
4970                         if (ret)
4971                                 return ret;
4972                 }
4973         }
4974
4975         return 0;
4976 }
4977
4978 static void
4979 hns3_restore_filter(struct rte_eth_dev *dev)
4980 {
4981         hns3_restore_rss_filter(dev);
4982 }
4983
4984 static int
4985 hns3_dev_start(struct rte_eth_dev *dev)
4986 {
4987         struct hns3_adapter *hns = dev->data->dev_private;
4988         struct hns3_hw *hw = &hns->hw;
4989         int ret;
4990
4991         PMD_INIT_FUNC_TRACE();
4992         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
4993                 return -EBUSY;
4994
4995         rte_spinlock_lock(&hw->lock);
4996         hw->adapter_state = HNS3_NIC_STARTING;
4997
4998         ret = hns3_do_start(hns, true);
4999         if (ret) {
5000                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5001                 rte_spinlock_unlock(&hw->lock);
5002                 return ret;
5003         }
5004         ret = hns3_map_rx_interrupt(dev);
5005         if (ret) {
5006                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5007                 rte_spinlock_unlock(&hw->lock);
5008                 return ret;
5009         }
5010
5011         /*
5012          * There are three register used to control the status of a TQP
5013          * (contains a pair of Tx queue and Rx queue) in the new version network
5014          * engine. One is used to control the enabling of Tx queue, the other is
5015          * used to control the enabling of Rx queue, and the last is the master
5016          * switch used to control the enabling of the tqp. The Tx register and
5017          * TQP register must be enabled at the same time to enable a Tx queue.
5018          * The same applies to the Rx queue. For the older network engine, this
5019          * function only refresh the enabled flag, and it is used to update the
5020          * status of queue in the dpdk framework.
5021          */
5022         ret = hns3_start_all_txqs(dev);
5023         if (ret) {
5024                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5025                 rte_spinlock_unlock(&hw->lock);
5026                 return ret;
5027         }
5028
5029         ret = hns3_start_all_rxqs(dev);
5030         if (ret) {
5031                 hns3_stop_all_txqs(dev);
5032                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5033                 rte_spinlock_unlock(&hw->lock);
5034                 return ret;
5035         }
5036
5037         hw->adapter_state = HNS3_NIC_STARTED;
5038         rte_spinlock_unlock(&hw->lock);
5039
5040         hns3_rx_scattered_calc(dev);
5041         hns3_set_rxtx_function(dev);
5042         hns3_mp_req_start_rxtx(dev);
5043         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5044
5045         hns3_restore_filter(dev);
5046
5047         /* Enable interrupt of all rx queues before enabling queues */
5048         hns3_dev_all_rx_queue_intr_enable(hw, true);
5049
5050         /*
5051          * After finished the initialization, enable tqps to receive/transmit
5052          * packets and refresh all queue status.
5053          */
5054         hns3_start_tqps(hw);
5055
5056         hns3_tm_dev_start_proc(hw);
5057
5058         hns3_info(hw, "hns3 dev start successful!");
5059         return 0;
5060 }
5061
5062 static int
5063 hns3_do_stop(struct hns3_adapter *hns)
5064 {
5065         struct hns3_hw *hw = &hns->hw;
5066         int ret;
5067
5068         ret = hns3_cfg_mac_mode(hw, false);
5069         if (ret)
5070                 return ret;
5071         hw->mac.link_status = ETH_LINK_DOWN;
5072
5073         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
5074                 hns3_configure_all_mac_addr(hns, true);
5075                 ret = hns3_reset_all_tqps(hns);
5076                 if (ret) {
5077                         hns3_err(hw, "failed to reset all queues ret = %d.",
5078                                  ret);
5079                         return ret;
5080                 }
5081         }
5082         hw->mac.default_addr_setted = false;
5083         return 0;
5084 }
5085
5086 static void
5087 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5088 {
5089         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5090         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5091         struct hns3_adapter *hns = dev->data->dev_private;
5092         struct hns3_hw *hw = &hns->hw;
5093         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5094         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5095         uint16_t q_id;
5096
5097         if (dev->data->dev_conf.intr_conf.rxq == 0)
5098                 return;
5099
5100         /* unmap the ring with vector */
5101         if (rte_intr_allow_others(intr_handle)) {
5102                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5103                 base = RTE_INTR_VEC_RXTX_OFFSET;
5104         }
5105         if (rte_intr_dp_is_en(intr_handle)) {
5106                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5107                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5108                                                          HNS3_RING_TYPE_RX,
5109                                                          q_id);
5110                         if (vec < base + intr_handle->nb_efd - 1)
5111                                 vec++;
5112                 }
5113         }
5114         /* Clean datapath event and queue/vec mapping */
5115         rte_intr_efd_disable(intr_handle);
5116         if (intr_handle->intr_vec) {
5117                 rte_free(intr_handle->intr_vec);
5118                 intr_handle->intr_vec = NULL;
5119         }
5120 }
5121
5122 static int
5123 hns3_dev_stop(struct rte_eth_dev *dev)
5124 {
5125         struct hns3_adapter *hns = dev->data->dev_private;
5126         struct hns3_hw *hw = &hns->hw;
5127
5128         PMD_INIT_FUNC_TRACE();
5129         dev->data->dev_started = 0;
5130
5131         hw->adapter_state = HNS3_NIC_STOPPING;
5132         hns3_set_rxtx_function(dev);
5133         rte_wmb();
5134         /* Disable datapath on secondary process. */
5135         hns3_mp_req_stop_rxtx(dev);
5136         /* Prevent crashes when queues are still in use. */
5137         rte_delay_ms(hw->tqps_num);
5138
5139         rte_spinlock_lock(&hw->lock);
5140         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5141                 hns3_tm_dev_stop_proc(hw);
5142                 hns3_stop_tqps(hw);
5143                 hns3_do_stop(hns);
5144                 hns3_unmap_rx_interrupt(dev);
5145                 hns3_dev_release_mbufs(hns);
5146                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5147         }
5148         hns3_rx_scattered_reset(dev);
5149         rte_eal_alarm_cancel(hns3_service_handler, dev);
5150         rte_spinlock_unlock(&hw->lock);
5151
5152         return 0;
5153 }
5154
5155 static int
5156 hns3_dev_close(struct rte_eth_dev *eth_dev)
5157 {
5158         struct hns3_adapter *hns = eth_dev->data->dev_private;
5159         struct hns3_hw *hw = &hns->hw;
5160         int ret = 0;
5161
5162         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5163                 rte_free(eth_dev->process_private);
5164                 eth_dev->process_private = NULL;
5165                 return 0;
5166         }
5167
5168         if (hw->adapter_state == HNS3_NIC_STARTED)
5169                 ret = hns3_dev_stop(eth_dev);
5170
5171         hw->adapter_state = HNS3_NIC_CLOSING;
5172         hns3_reset_abort(hns);
5173         hw->adapter_state = HNS3_NIC_CLOSED;
5174
5175         hns3_configure_all_mc_mac_addr(hns, true);
5176         hns3_remove_all_vlan_table(hns);
5177         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5178         hns3_uninit_pf(eth_dev);
5179         hns3_free_all_queues(eth_dev);
5180         rte_free(hw->reset.wait_data);
5181         rte_free(eth_dev->process_private);
5182         eth_dev->process_private = NULL;
5183         hns3_mp_uninit_primary();
5184         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5185
5186         return ret;
5187 }
5188
5189 static int
5190 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5191 {
5192         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5193         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5194
5195         fc_conf->pause_time = pf->pause_time;
5196
5197         /* return fc current mode */
5198         switch (hw->current_mode) {
5199         case HNS3_FC_FULL:
5200                 fc_conf->mode = RTE_FC_FULL;
5201                 break;
5202         case HNS3_FC_TX_PAUSE:
5203                 fc_conf->mode = RTE_FC_TX_PAUSE;
5204                 break;
5205         case HNS3_FC_RX_PAUSE:
5206                 fc_conf->mode = RTE_FC_RX_PAUSE;
5207                 break;
5208         case HNS3_FC_NONE:
5209         default:
5210                 fc_conf->mode = RTE_FC_NONE;
5211                 break;
5212         }
5213
5214         return 0;
5215 }
5216
5217 static void
5218 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5219 {
5220         switch (mode) {
5221         case RTE_FC_NONE:
5222                 hw->requested_mode = HNS3_FC_NONE;
5223                 break;
5224         case RTE_FC_RX_PAUSE:
5225                 hw->requested_mode = HNS3_FC_RX_PAUSE;
5226                 break;
5227         case RTE_FC_TX_PAUSE:
5228                 hw->requested_mode = HNS3_FC_TX_PAUSE;
5229                 break;
5230         case RTE_FC_FULL:
5231                 hw->requested_mode = HNS3_FC_FULL;
5232                 break;
5233         default:
5234                 hw->requested_mode = HNS3_FC_NONE;
5235                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5236                           "configured to RTE_FC_NONE", mode);
5237                 break;
5238         }
5239 }
5240
5241 static int
5242 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5243 {
5244         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5245         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5246         int ret;
5247
5248         if (fc_conf->high_water || fc_conf->low_water ||
5249             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5250                 hns3_err(hw, "Unsupported flow control settings specified, "
5251                          "high_water(%u), low_water(%u), send_xon(%u) and "
5252                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5253                          fc_conf->high_water, fc_conf->low_water,
5254                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5255                 return -EINVAL;
5256         }
5257         if (fc_conf->autoneg) {
5258                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5259                 return -EINVAL;
5260         }
5261         if (!fc_conf->pause_time) {
5262                 hns3_err(hw, "Invalid pause time %u setting.",
5263                          fc_conf->pause_time);
5264                 return -EINVAL;
5265         }
5266
5267         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5268             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5269                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5270                          "current_fc_status = %d", hw->current_fc_status);
5271                 return -EOPNOTSUPP;
5272         }
5273
5274         hns3_get_fc_mode(hw, fc_conf->mode);
5275         if (hw->requested_mode == hw->current_mode &&
5276             pf->pause_time == fc_conf->pause_time)
5277                 return 0;
5278
5279         rte_spinlock_lock(&hw->lock);
5280         ret = hns3_fc_enable(dev, fc_conf);
5281         rte_spinlock_unlock(&hw->lock);
5282
5283         return ret;
5284 }
5285
5286 static int
5287 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5288                             struct rte_eth_pfc_conf *pfc_conf)
5289 {
5290         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5291         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5292         uint8_t priority;
5293         int ret;
5294
5295         if (!hns3_dev_dcb_supported(hw)) {
5296                 hns3_err(hw, "This port does not support dcb configurations.");
5297                 return -EOPNOTSUPP;
5298         }
5299
5300         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5301             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5302                 hns3_err(hw, "Unsupported flow control settings specified, "
5303                          "high_water(%u), low_water(%u), send_xon(%u) and "
5304                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5305                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5306                          pfc_conf->fc.send_xon,
5307                          pfc_conf->fc.mac_ctrl_frame_fwd);
5308                 return -EINVAL;
5309         }
5310         if (pfc_conf->fc.autoneg) {
5311                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5312                 return -EINVAL;
5313         }
5314         if (pfc_conf->fc.pause_time == 0) {
5315                 hns3_err(hw, "Invalid pause time %u setting.",
5316                          pfc_conf->fc.pause_time);
5317                 return -EINVAL;
5318         }
5319
5320         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5321             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5322                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5323                              "current_fc_status = %d", hw->current_fc_status);
5324                 return -EOPNOTSUPP;
5325         }
5326
5327         priority = pfc_conf->priority;
5328         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5329         if (hw->dcb_info.pfc_en & BIT(priority) &&
5330             hw->requested_mode == hw->current_mode &&
5331             pfc_conf->fc.pause_time == pf->pause_time)
5332                 return 0;
5333
5334         rte_spinlock_lock(&hw->lock);
5335         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5336         rte_spinlock_unlock(&hw->lock);
5337
5338         return ret;
5339 }
5340
5341 static int
5342 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5343 {
5344         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5345         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5346         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5347         int i;
5348
5349         rte_spinlock_lock(&hw->lock);
5350         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5351                 dcb_info->nb_tcs = pf->local_max_tc;
5352         else
5353                 dcb_info->nb_tcs = 1;
5354
5355         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5356                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5357         for (i = 0; i < dcb_info->nb_tcs; i++)
5358                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5359
5360         for (i = 0; i < hw->num_tc; i++) {
5361                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5362                 dcb_info->tc_queue.tc_txq[0][i].base =
5363                                                 hw->tc_queue[i].tqp_offset;
5364                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5365                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5366                                                 hw->tc_queue[i].tqp_count;
5367         }
5368         rte_spinlock_unlock(&hw->lock);
5369
5370         return 0;
5371 }
5372
5373 static int
5374 hns3_reinit_dev(struct hns3_adapter *hns)
5375 {
5376         struct hns3_hw *hw = &hns->hw;
5377         int ret;
5378
5379         ret = hns3_cmd_init(hw);
5380         if (ret) {
5381                 hns3_err(hw, "Failed to init cmd: %d", ret);
5382                 return ret;
5383         }
5384
5385         ret = hns3_reset_all_tqps(hns);
5386         if (ret) {
5387                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5388                 return ret;
5389         }
5390
5391         ret = hns3_init_hardware(hns);
5392         if (ret) {
5393                 hns3_err(hw, "Failed to init hardware: %d", ret);
5394                 return ret;
5395         }
5396
5397         ret = hns3_enable_hw_error_intr(hns, true);
5398         if (ret) {
5399                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5400                              ret);
5401                 return ret;
5402         }
5403         hns3_info(hw, "Reset done, driver initialization finished.");
5404
5405         return 0;
5406 }
5407
5408 static bool
5409 is_pf_reset_done(struct hns3_hw *hw)
5410 {
5411         uint32_t val, reg, reg_bit;
5412
5413         switch (hw->reset.level) {
5414         case HNS3_IMP_RESET:
5415                 reg = HNS3_GLOBAL_RESET_REG;
5416                 reg_bit = HNS3_IMP_RESET_BIT;
5417                 break;
5418         case HNS3_GLOBAL_RESET:
5419                 reg = HNS3_GLOBAL_RESET_REG;
5420                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5421                 break;
5422         case HNS3_FUNC_RESET:
5423                 reg = HNS3_FUN_RST_ING;
5424                 reg_bit = HNS3_FUN_RST_ING_B;
5425                 break;
5426         case HNS3_FLR_RESET:
5427         default:
5428                 hns3_err(hw, "Wait for unsupported reset level: %d",
5429                          hw->reset.level);
5430                 return true;
5431         }
5432         val = hns3_read_dev(hw, reg);
5433         if (hns3_get_bit(val, reg_bit))
5434                 return false;
5435         else
5436                 return true;
5437 }
5438
5439 bool
5440 hns3_is_reset_pending(struct hns3_adapter *hns)
5441 {
5442         struct hns3_hw *hw = &hns->hw;
5443         enum hns3_reset_level reset;
5444
5445         hns3_check_event_cause(hns, NULL);
5446         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5447         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5448                 hns3_warn(hw, "High level reset %d is pending", reset);
5449                 return true;
5450         }
5451         reset = hns3_get_reset_level(hns, &hw->reset.request);
5452         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5453                 hns3_warn(hw, "High level reset %d is request", reset);
5454                 return true;
5455         }
5456         return false;
5457 }
5458
5459 static int
5460 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5461 {
5462         struct hns3_hw *hw = &hns->hw;
5463         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5464         struct timeval tv;
5465
5466         if (wait_data->result == HNS3_WAIT_SUCCESS)
5467                 return 0;
5468         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5469                 gettimeofday(&tv, NULL);
5470                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5471                           tv.tv_sec, tv.tv_usec);
5472                 return -ETIME;
5473         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5474                 return -EAGAIN;
5475
5476         wait_data->hns = hns;
5477         wait_data->check_completion = is_pf_reset_done;
5478         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5479                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5480         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5481         wait_data->count = HNS3_RESET_WAIT_CNT;
5482         wait_data->result = HNS3_WAIT_REQUEST;
5483         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5484         return -EAGAIN;
5485 }
5486
5487 static int
5488 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5489 {
5490         struct hns3_cmd_desc desc;
5491         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5492
5493         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5494         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5495         req->fun_reset_vfid = func_id;
5496
5497         return hns3_cmd_send(hw, &desc, 1);
5498 }
5499
5500 static int
5501 hns3_imp_reset_cmd(struct hns3_hw *hw)
5502 {
5503         struct hns3_cmd_desc desc;
5504
5505         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5506         desc.data[0] = 0xeedd;
5507
5508         return hns3_cmd_send(hw, &desc, 1);
5509 }
5510
5511 static void
5512 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5513 {
5514         struct hns3_hw *hw = &hns->hw;
5515         struct timeval tv;
5516         uint32_t val;
5517
5518         gettimeofday(&tv, NULL);
5519         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5520             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5521                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5522                           tv.tv_sec, tv.tv_usec);
5523                 return;
5524         }
5525
5526         switch (reset_level) {
5527         case HNS3_IMP_RESET:
5528                 hns3_imp_reset_cmd(hw);
5529                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5530                           tv.tv_sec, tv.tv_usec);
5531                 break;
5532         case HNS3_GLOBAL_RESET:
5533                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5534                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5535                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5536                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5537                           tv.tv_sec, tv.tv_usec);
5538                 break;
5539         case HNS3_FUNC_RESET:
5540                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5541                           tv.tv_sec, tv.tv_usec);
5542                 /* schedule again to check later */
5543                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5544                 hns3_schedule_reset(hns);
5545                 break;
5546         default:
5547                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5548                 return;
5549         }
5550         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5551 }
5552
5553 static enum hns3_reset_level
5554 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5555 {
5556         struct hns3_hw *hw = &hns->hw;
5557         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5558
5559         /* Return the highest priority reset level amongst all */
5560         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5561                 reset_level = HNS3_IMP_RESET;
5562         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5563                 reset_level = HNS3_GLOBAL_RESET;
5564         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5565                 reset_level = HNS3_FUNC_RESET;
5566         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5567                 reset_level = HNS3_FLR_RESET;
5568
5569         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5570                 return HNS3_NONE_RESET;
5571
5572         return reset_level;
5573 }
5574
5575 static void
5576 hns3_record_imp_error(struct hns3_adapter *hns)
5577 {
5578         struct hns3_hw *hw = &hns->hw;
5579         uint32_t reg_val;
5580
5581         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5582         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5583                 hns3_warn(hw, "Detected IMP RD poison!");
5584                 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5585                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5586                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5587         }
5588
5589         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5590                 hns3_warn(hw, "Detected IMP CMDQ error!");
5591                 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5592                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5593                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5594         }
5595 }
5596
5597 static int
5598 hns3_prepare_reset(struct hns3_adapter *hns)
5599 {
5600         struct hns3_hw *hw = &hns->hw;
5601         uint32_t reg_val;
5602         int ret;
5603
5604         switch (hw->reset.level) {
5605         case HNS3_FUNC_RESET:
5606                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5607                 if (ret)
5608                         return ret;
5609
5610                 /*
5611                  * After performaning pf reset, it is not necessary to do the
5612                  * mailbox handling or send any command to firmware, because
5613                  * any mailbox handling or command to firmware is only valid
5614                  * after hns3_cmd_init is called.
5615                  */
5616                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5617                 hw->reset.stats.request_cnt++;
5618                 break;
5619         case HNS3_IMP_RESET:
5620                 hns3_record_imp_error(hns);
5621                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5622                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5623                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5624                 break;
5625         default:
5626                 break;
5627         }
5628         return 0;
5629 }
5630
5631 static int
5632 hns3_set_rst_done(struct hns3_hw *hw)
5633 {
5634         struct hns3_pf_rst_done_cmd *req;
5635         struct hns3_cmd_desc desc;
5636
5637         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5638         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5639         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5640         return hns3_cmd_send(hw, &desc, 1);
5641 }
5642
5643 static int
5644 hns3_stop_service(struct hns3_adapter *hns)
5645 {
5646         struct hns3_hw *hw = &hns->hw;
5647         struct rte_eth_dev *eth_dev;
5648
5649         eth_dev = &rte_eth_devices[hw->data->port_id];
5650         if (hw->adapter_state == HNS3_NIC_STARTED) {
5651                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5652                 hns3_update_link_status_and_event(hw);
5653         }
5654         hw->mac.link_status = ETH_LINK_DOWN;
5655
5656         hns3_set_rxtx_function(eth_dev);
5657         rte_wmb();
5658         /* Disable datapath on secondary process. */
5659         hns3_mp_req_stop_rxtx(eth_dev);
5660         rte_delay_ms(hw->tqps_num);
5661
5662         rte_spinlock_lock(&hw->lock);
5663         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5664             hw->adapter_state == HNS3_NIC_STOPPING) {
5665                 hns3_enable_all_queues(hw, false);
5666                 hns3_do_stop(hns);
5667                 hw->reset.mbuf_deferred_free = true;
5668         } else
5669                 hw->reset.mbuf_deferred_free = false;
5670
5671         /*
5672          * It is cumbersome for hardware to pick-and-choose entries for deletion
5673          * from table space. Hence, for function reset software intervention is
5674          * required to delete the entries
5675          */
5676         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5677                 hns3_configure_all_mc_mac_addr(hns, true);
5678         rte_spinlock_unlock(&hw->lock);
5679
5680         return 0;
5681 }
5682
5683 static int
5684 hns3_start_service(struct hns3_adapter *hns)
5685 {
5686         struct hns3_hw *hw = &hns->hw;
5687         struct rte_eth_dev *eth_dev;
5688
5689         if (hw->reset.level == HNS3_IMP_RESET ||
5690             hw->reset.level == HNS3_GLOBAL_RESET)
5691                 hns3_set_rst_done(hw);
5692         eth_dev = &rte_eth_devices[hw->data->port_id];
5693         hns3_set_rxtx_function(eth_dev);
5694         hns3_mp_req_start_rxtx(eth_dev);
5695         if (hw->adapter_state == HNS3_NIC_STARTED) {
5696                 /*
5697                  * This API parent function already hold the hns3_hw.lock, the
5698                  * hns3_service_handler may report lse, in bonding application
5699                  * it will call driver's ops which may acquire the hns3_hw.lock
5700                  * again, thus lead to deadlock.
5701                  * We defer calls hns3_service_handler to avoid the deadlock.
5702                  */
5703                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
5704                                   hns3_service_handler, eth_dev);
5705
5706                 /* Enable interrupt of all rx queues before enabling queues */
5707                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5708                 /*
5709                  * Enable state of each rxq and txq will be recovered after
5710                  * reset, so we need to restore them before enable all tqps;
5711                  */
5712                 hns3_restore_tqp_enable_state(hw);
5713                 /*
5714                  * When finished the initialization, enable queues to receive
5715                  * and transmit packets.
5716                  */
5717                 hns3_enable_all_queues(hw, true);
5718         }
5719
5720         return 0;
5721 }
5722
5723 static int
5724 hns3_restore_conf(struct hns3_adapter *hns)
5725 {
5726         struct hns3_hw *hw = &hns->hw;
5727         int ret;
5728
5729         ret = hns3_configure_all_mac_addr(hns, false);
5730         if (ret)
5731                 return ret;
5732
5733         ret = hns3_configure_all_mc_mac_addr(hns, false);
5734         if (ret)
5735                 goto err_mc_mac;
5736
5737         ret = hns3_dev_promisc_restore(hns);
5738         if (ret)
5739                 goto err_promisc;
5740
5741         ret = hns3_restore_vlan_table(hns);
5742         if (ret)
5743                 goto err_promisc;
5744
5745         ret = hns3_restore_vlan_conf(hns);
5746         if (ret)
5747                 goto err_promisc;
5748
5749         ret = hns3_restore_all_fdir_filter(hns);
5750         if (ret)
5751                 goto err_promisc;
5752
5753         ret = hns3_restore_rx_interrupt(hw);
5754         if (ret)
5755                 goto err_promisc;
5756
5757         ret = hns3_restore_gro_conf(hw);
5758         if (ret)
5759                 goto err_promisc;
5760
5761         ret = hns3_restore_fec(hw);
5762         if (ret)
5763                 goto err_promisc;
5764
5765         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5766                 ret = hns3_do_start(hns, false);
5767                 if (ret)
5768                         goto err_promisc;
5769                 hns3_info(hw, "hns3 dev restart successful!");
5770         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5771                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5772         return 0;
5773
5774 err_promisc:
5775         hns3_configure_all_mc_mac_addr(hns, true);
5776 err_mc_mac:
5777         hns3_configure_all_mac_addr(hns, true);
5778         return ret;
5779 }
5780
5781 static void
5782 hns3_reset_service(void *param)
5783 {
5784         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5785         struct hns3_hw *hw = &hns->hw;
5786         enum hns3_reset_level reset_level;
5787         struct timeval tv_delta;
5788         struct timeval tv_start;
5789         struct timeval tv;
5790         uint64_t msec;
5791         int ret;
5792
5793         /*
5794          * The interrupt is not triggered within the delay time.
5795          * The interrupt may have been lost. It is necessary to handle
5796          * the interrupt to recover from the error.
5797          */
5798         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5799                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5800                 hns3_err(hw, "Handling interrupts in delayed tasks");
5801                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5802                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5803                 if (reset_level == HNS3_NONE_RESET) {
5804                         hns3_err(hw, "No reset level is set, try IMP reset");
5805                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5806                 }
5807         }
5808         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5809
5810         /*
5811          * Check if there is any ongoing reset in the hardware. This status can
5812          * be checked from reset_pending. If there is then, we need to wait for
5813          * hardware to complete reset.
5814          *    a. If we are able to figure out in reasonable time that hardware
5815          *       has fully resetted then, we can proceed with driver, client
5816          *       reset.
5817          *    b. else, we can come back later to check this status so re-sched
5818          *       now.
5819          */
5820         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5821         if (reset_level != HNS3_NONE_RESET) {
5822                 gettimeofday(&tv_start, NULL);
5823                 ret = hns3_reset_process(hns, reset_level);
5824                 gettimeofday(&tv, NULL);
5825                 timersub(&tv, &tv_start, &tv_delta);
5826                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5827                        tv_delta.tv_usec / USEC_PER_MSEC;
5828                 if (msec > HNS3_RESET_PROCESS_MS)
5829                         hns3_err(hw, "%d handle long time delta %" PRIx64
5830                                      " ms time=%ld.%.6ld",
5831                                  hw->reset.level, msec,
5832                                  tv.tv_sec, tv.tv_usec);
5833                 if (ret == -EAGAIN)
5834                         return;
5835         }
5836
5837         /* Check if we got any *new* reset requests to be honored */
5838         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5839         if (reset_level != HNS3_NONE_RESET)
5840                 hns3_msix_process(hns, reset_level);
5841 }
5842
5843 static unsigned int
5844 hns3_get_speed_capa_num(uint16_t device_id)
5845 {
5846         unsigned int num;
5847
5848         switch (device_id) {
5849         case HNS3_DEV_ID_25GE:
5850         case HNS3_DEV_ID_25GE_RDMA:
5851                 num = 2;
5852                 break;
5853         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5854         case HNS3_DEV_ID_200G_RDMA:
5855                 num = 1;
5856                 break;
5857         default:
5858                 num = 0;
5859                 break;
5860         }
5861
5862         return num;
5863 }
5864
5865 static int
5866 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
5867                         uint16_t device_id)
5868 {
5869         switch (device_id) {
5870         case HNS3_DEV_ID_25GE:
5871         /* fallthrough */
5872         case HNS3_DEV_ID_25GE_RDMA:
5873                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
5874                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
5875
5876                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
5877                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
5878                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
5879                 break;
5880         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5881                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
5882                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
5883                 break;
5884         case HNS3_DEV_ID_200G_RDMA:
5885                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
5886                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
5887                 break;
5888         default:
5889                 return -ENOTSUP;
5890         }
5891
5892         return 0;
5893 }
5894
5895 static int
5896 hns3_fec_get_capability(struct rte_eth_dev *dev,
5897                         struct rte_eth_fec_capa *speed_fec_capa,
5898                         unsigned int num)
5899 {
5900         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5901         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5902         uint16_t device_id = pci_dev->id.device_id;
5903         unsigned int capa_num;
5904         int ret;
5905
5906         capa_num = hns3_get_speed_capa_num(device_id);
5907         if (capa_num == 0) {
5908                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
5909                          device_id);
5910                 return -ENOTSUP;
5911         }
5912
5913         if (speed_fec_capa == NULL || num < capa_num)
5914                 return capa_num;
5915
5916         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
5917         if (ret)
5918                 return -ENOTSUP;
5919
5920         return capa_num;
5921 }
5922
5923 static int
5924 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
5925 {
5926         struct hns3_config_fec_cmd *req;
5927         struct hns3_cmd_desc desc;
5928         int ret;
5929
5930         /*
5931          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
5932          * in device of link speed
5933          * below 10 Gbps.
5934          */
5935         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
5936                 *state = 0;
5937                 return 0;
5938         }
5939
5940         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
5941         req = (struct hns3_config_fec_cmd *)desc.data;
5942         ret = hns3_cmd_send(hw, &desc, 1);
5943         if (ret) {
5944                 hns3_err(hw, "get current fec auto state failed, ret = %d",
5945                          ret);
5946                 return ret;
5947         }
5948
5949         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
5950         return 0;
5951 }
5952
5953 static int
5954 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
5955 {
5956 #define QUERY_ACTIVE_SPEED      1
5957         struct hns3_sfp_speed_cmd *resp;
5958         uint32_t tmp_fec_capa;
5959         uint8_t auto_state;
5960         struct hns3_cmd_desc desc;
5961         int ret;
5962
5963         /*
5964          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
5965          * configured FEC mode is returned.
5966          * If link is up, current FEC mode is returned.
5967          */
5968         if (hw->mac.link_status == ETH_LINK_DOWN) {
5969                 ret = get_current_fec_auto_state(hw, &auto_state);
5970                 if (ret)
5971                         return ret;
5972
5973                 if (auto_state == 0x1) {
5974                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
5975                         return 0;
5976                 }
5977         }
5978
5979         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
5980         resp = (struct hns3_sfp_speed_cmd *)desc.data;
5981         resp->query_type = QUERY_ACTIVE_SPEED;
5982
5983         ret = hns3_cmd_send(hw, &desc, 1);
5984         if (ret == -EOPNOTSUPP) {
5985                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
5986                 return ret;
5987         } else if (ret) {
5988                 hns3_err(hw, "get FEC failed, ret = %d", ret);
5989                 return ret;
5990         }
5991
5992         /*
5993          * FEC mode order defined in hns3 hardware is inconsistend with
5994          * that defined in the ethdev library. So the sequence needs
5995          * to be converted.
5996          */
5997         switch (resp->active_fec) {
5998         case HNS3_HW_FEC_MODE_NOFEC:
5999                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6000                 break;
6001         case HNS3_HW_FEC_MODE_BASER:
6002                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6003                 break;
6004         case HNS3_HW_FEC_MODE_RS:
6005                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6006                 break;
6007         default:
6008                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6009                 break;
6010         }
6011
6012         *fec_capa = tmp_fec_capa;
6013         return 0;
6014 }
6015
6016 static int
6017 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6018 {
6019         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6020
6021         return hns3_fec_get_internal(hw, fec_capa);
6022 }
6023
6024 static int
6025 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6026 {
6027         struct hns3_config_fec_cmd *req;
6028         struct hns3_cmd_desc desc;
6029         int ret;
6030
6031         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6032
6033         req = (struct hns3_config_fec_cmd *)desc.data;
6034         switch (mode) {
6035         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6036                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6037                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6038                 break;
6039         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6040                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6041                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6042                 break;
6043         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6044                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6045                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6046                 break;
6047         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6048                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6049                 break;
6050         default:
6051                 return 0;
6052         }
6053         ret = hns3_cmd_send(hw, &desc, 1);
6054         if (ret)
6055                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6056
6057         return ret;
6058 }
6059
6060 static uint32_t
6061 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6062 {
6063         struct hns3_mac *mac = &hw->mac;
6064         uint32_t cur_capa;
6065
6066         switch (mac->link_speed) {
6067         case ETH_SPEED_NUM_10G:
6068                 cur_capa = fec_capa[1].capa;
6069                 break;
6070         case ETH_SPEED_NUM_25G:
6071         case ETH_SPEED_NUM_100G:
6072         case ETH_SPEED_NUM_200G:
6073                 cur_capa = fec_capa[0].capa;
6074                 break;
6075         default:
6076                 cur_capa = 0;
6077                 break;
6078         }
6079
6080         return cur_capa;
6081 }
6082
6083 static bool
6084 is_fec_mode_one_bit_set(uint32_t mode)
6085 {
6086         int cnt = 0;
6087         uint8_t i;
6088
6089         for (i = 0; i < sizeof(mode); i++)
6090                 if (mode >> i & 0x1)
6091                         cnt++;
6092
6093         return cnt == 1 ? true : false;
6094 }
6095
6096 static int
6097 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6098 {
6099 #define FEC_CAPA_NUM 2
6100         struct hns3_adapter *hns = dev->data->dev_private;
6101         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6102         struct hns3_pf *pf = &hns->pf;
6103
6104         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6105         uint32_t cur_capa;
6106         uint32_t num = FEC_CAPA_NUM;
6107         int ret;
6108
6109         ret = hns3_fec_get_capability(dev, fec_capa, num);
6110         if (ret < 0)
6111                 return ret;
6112
6113         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6114         if (!is_fec_mode_one_bit_set(mode))
6115                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6116                              "FEC mode should be only one bit set", mode);
6117
6118         /*
6119          * Check whether the configured mode is within the FEC capability.
6120          * If not, the configured mode will not be supported.
6121          */
6122         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6123         if (!(cur_capa & mode)) {
6124                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6125                 return -EINVAL;
6126         }
6127
6128         ret = hns3_set_fec_hw(hw, mode);
6129         if (ret)
6130                 return ret;
6131
6132         pf->fec_mode = mode;
6133         return 0;
6134 }
6135
6136 static int
6137 hns3_restore_fec(struct hns3_hw *hw)
6138 {
6139         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6140         struct hns3_pf *pf = &hns->pf;
6141         uint32_t mode = pf->fec_mode;
6142         int ret;
6143
6144         ret = hns3_set_fec_hw(hw, mode);
6145         if (ret)
6146                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6147                          mode, ret);
6148
6149         return ret;
6150 }
6151
6152 static int
6153 hns3_query_dev_fec_info(struct hns3_hw *hw)
6154 {
6155         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6156         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6157         int ret;
6158
6159         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6160         if (ret)
6161                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6162
6163         return ret;
6164 }
6165
6166 static const struct eth_dev_ops hns3_eth_dev_ops = {
6167         .dev_configure      = hns3_dev_configure,
6168         .dev_start          = hns3_dev_start,
6169         .dev_stop           = hns3_dev_stop,
6170         .dev_close          = hns3_dev_close,
6171         .promiscuous_enable = hns3_dev_promiscuous_enable,
6172         .promiscuous_disable = hns3_dev_promiscuous_disable,
6173         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6174         .allmulticast_disable = hns3_dev_allmulticast_disable,
6175         .mtu_set            = hns3_dev_mtu_set,
6176         .stats_get          = hns3_stats_get,
6177         .stats_reset        = hns3_stats_reset,
6178         .xstats_get         = hns3_dev_xstats_get,
6179         .xstats_get_names   = hns3_dev_xstats_get_names,
6180         .xstats_reset       = hns3_dev_xstats_reset,
6181         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6182         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6183         .dev_infos_get          = hns3_dev_infos_get,
6184         .fw_version_get         = hns3_fw_version_get,
6185         .rx_queue_setup         = hns3_rx_queue_setup,
6186         .tx_queue_setup         = hns3_tx_queue_setup,
6187         .rx_queue_release       = hns3_dev_rx_queue_release,
6188         .tx_queue_release       = hns3_dev_tx_queue_release,
6189         .rx_queue_start         = hns3_dev_rx_queue_start,
6190         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6191         .tx_queue_start         = hns3_dev_tx_queue_start,
6192         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6193         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6194         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6195         .rxq_info_get           = hns3_rxq_info_get,
6196         .txq_info_get           = hns3_txq_info_get,
6197         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6198         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6199         .flow_ctrl_get          = hns3_flow_ctrl_get,
6200         .flow_ctrl_set          = hns3_flow_ctrl_set,
6201         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6202         .mac_addr_add           = hns3_add_mac_addr,
6203         .mac_addr_remove        = hns3_remove_mac_addr,
6204         .mac_addr_set           = hns3_set_default_mac_addr,
6205         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6206         .link_update            = hns3_dev_link_update,
6207         .rss_hash_update        = hns3_dev_rss_hash_update,
6208         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6209         .reta_update            = hns3_dev_rss_reta_update,
6210         .reta_query             = hns3_dev_rss_reta_query,
6211         .filter_ctrl            = hns3_dev_filter_ctrl,
6212         .vlan_filter_set        = hns3_vlan_filter_set,
6213         .vlan_tpid_set          = hns3_vlan_tpid_set,
6214         .vlan_offload_set       = hns3_vlan_offload_set,
6215         .vlan_pvid_set          = hns3_vlan_pvid_set,
6216         .get_reg                = hns3_get_regs,
6217         .get_dcb_info           = hns3_get_dcb_info,
6218         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6219         .fec_get_capability     = hns3_fec_get_capability,
6220         .fec_get                = hns3_fec_get,
6221         .fec_set                = hns3_fec_set,
6222         .tm_ops_get             = hns3_tm_ops_get,
6223 };
6224
6225 static const struct hns3_reset_ops hns3_reset_ops = {
6226         .reset_service       = hns3_reset_service,
6227         .stop_service        = hns3_stop_service,
6228         .prepare_reset       = hns3_prepare_reset,
6229         .wait_hardware_ready = hns3_wait_hardware_ready,
6230         .reinit_dev          = hns3_reinit_dev,
6231         .restore_conf        = hns3_restore_conf,
6232         .start_service       = hns3_start_service,
6233 };
6234
6235 static int
6236 hns3_dev_init(struct rte_eth_dev *eth_dev)
6237 {
6238         struct hns3_adapter *hns = eth_dev->data->dev_private;
6239         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6240         struct rte_ether_addr *eth_addr;
6241         struct hns3_hw *hw = &hns->hw;
6242         int ret;
6243
6244         PMD_INIT_FUNC_TRACE();
6245
6246         eth_dev->process_private = (struct hns3_process_private *)
6247             rte_zmalloc_socket("hns3_filter_list",
6248                                sizeof(struct hns3_process_private),
6249                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6250         if (eth_dev->process_private == NULL) {
6251                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6252                 return -ENOMEM;
6253         }
6254         /* initialize flow filter lists */
6255         hns3_filterlist_init(eth_dev);
6256
6257         hns3_set_rxtx_function(eth_dev);
6258         eth_dev->dev_ops = &hns3_eth_dev_ops;
6259         eth_dev->rx_queue_count = hns3_rx_queue_count;
6260         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6261                 ret = hns3_mp_init_secondary();
6262                 if (ret) {
6263                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
6264                                      "process, ret = %d", ret);
6265                         goto err_mp_init_secondary;
6266                 }
6267
6268                 hw->secondary_cnt++;
6269                 return 0;
6270         }
6271
6272         ret = hns3_mp_init_primary();
6273         if (ret) {
6274                 PMD_INIT_LOG(ERR,
6275                              "Failed to init for primary process, ret = %d",
6276                              ret);
6277                 goto err_mp_init_primary;
6278         }
6279
6280         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6281         hns->is_vf = false;
6282         hw->data = eth_dev->data;
6283
6284         /*
6285          * Set default max packet size according to the mtu
6286          * default vale in DPDK frame.
6287          */
6288         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6289
6290         ret = hns3_reset_init(hw);
6291         if (ret)
6292                 goto err_init_reset;
6293         hw->reset.ops = &hns3_reset_ops;
6294
6295         ret = hns3_init_pf(eth_dev);
6296         if (ret) {
6297                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6298                 goto err_init_pf;
6299         }
6300
6301         /* Allocate memory for storing MAC addresses */
6302         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6303                                                sizeof(struct rte_ether_addr) *
6304                                                HNS3_UC_MACADDR_NUM, 0);
6305         if (eth_dev->data->mac_addrs == NULL) {
6306                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6307                              "to store MAC addresses",
6308                              sizeof(struct rte_ether_addr) *
6309                              HNS3_UC_MACADDR_NUM);
6310                 ret = -ENOMEM;
6311                 goto err_rte_zmalloc;
6312         }
6313
6314         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6315         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6316                 rte_eth_random_addr(hw->mac.mac_addr);
6317                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6318                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6319                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6320                           "unicast address, using random MAC address %s",
6321                           mac_str);
6322         }
6323         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6324                             &eth_dev->data->mac_addrs[0]);
6325
6326         hw->adapter_state = HNS3_NIC_INITIALIZED;
6327
6328         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
6329                 hns3_err(hw, "Reschedule reset service after dev_init");
6330                 hns3_schedule_reset(hns);
6331         } else {
6332                 /* IMP will wait ready flag before reset */
6333                 hns3_notify_reset_ready(hw, false);
6334         }
6335
6336         hns3_info(hw, "hns3 dev initialization successful!");
6337         return 0;
6338
6339 err_rte_zmalloc:
6340         hns3_uninit_pf(eth_dev);
6341
6342 err_init_pf:
6343         rte_free(hw->reset.wait_data);
6344
6345 err_init_reset:
6346         hns3_mp_uninit_primary();
6347
6348 err_mp_init_primary:
6349 err_mp_init_secondary:
6350         eth_dev->dev_ops = NULL;
6351         eth_dev->rx_pkt_burst = NULL;
6352         eth_dev->tx_pkt_burst = NULL;
6353         eth_dev->tx_pkt_prepare = NULL;
6354         rte_free(eth_dev->process_private);
6355         eth_dev->process_private = NULL;
6356         return ret;
6357 }
6358
6359 static int
6360 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6361 {
6362         struct hns3_adapter *hns = eth_dev->data->dev_private;
6363         struct hns3_hw *hw = &hns->hw;
6364
6365         PMD_INIT_FUNC_TRACE();
6366
6367         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6368                 rte_free(eth_dev->process_private);
6369                 eth_dev->process_private = NULL;
6370                 return 0;
6371         }
6372
6373         if (hw->adapter_state < HNS3_NIC_CLOSING)
6374                 hns3_dev_close(eth_dev);
6375
6376         hw->adapter_state = HNS3_NIC_REMOVED;
6377         return 0;
6378 }
6379
6380 static int
6381 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6382                    struct rte_pci_device *pci_dev)
6383 {
6384         return rte_eth_dev_pci_generic_probe(pci_dev,
6385                                              sizeof(struct hns3_adapter),
6386                                              hns3_dev_init);
6387 }
6388
6389 static int
6390 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6391 {
6392         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6393 }
6394
6395 static const struct rte_pci_id pci_id_hns3_map[] = {
6396         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6397         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6398         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6399         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6400         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6401         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6402         { .vendor_id = 0, }, /* sentinel */
6403 };
6404
6405 static struct rte_pci_driver rte_hns3_pmd = {
6406         .id_table = pci_id_hns3_map,
6407         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6408         .probe = eth_hns3_pci_probe,
6409         .remove = eth_hns3_pci_remove,
6410 };
6411
6412 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6413 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6414 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6415 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6416 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);