1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
6 #include <rte_bus_pci.h>
7 #include <ethdev_pci.h>
9 #include <rte_kvargs.h>
11 #include "hns3_ethdev.h"
12 #include "hns3_logs.h"
13 #include "hns3_rxtx.h"
14 #include "hns3_intr.h"
15 #include "hns3_regs.h"
19 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
20 #define HNS3_SERVICE_QUICK_INTERVAL 10
21 #define HNS3_INVALID_PVID 0xFFFF
23 #define HNS3_FILTER_TYPE_VF 0
24 #define HNS3_FILTER_TYPE_PORT 1
25 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
26 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
27 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
28 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
29 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
30 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
31 | HNS3_FILTER_FE_ROCE_EGRESS_B)
32 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
33 | HNS3_FILTER_FE_ROCE_INGRESS_B)
35 /* Reset related Registers */
36 #define HNS3_GLOBAL_RESET_BIT 0
37 #define HNS3_CORE_RESET_BIT 1
38 #define HNS3_IMP_RESET_BIT 2
39 #define HNS3_FUN_RST_ING_B 0
41 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
42 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
43 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U
44 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
46 #define HNS3_RESET_WAIT_MS 100
47 #define HNS3_RESET_WAIT_CNT 200
49 /* FEC mode order defined in HNS3 hardware */
50 #define HNS3_HW_FEC_MODE_NOFEC 0
51 #define HNS3_HW_FEC_MODE_BASER 1
52 #define HNS3_HW_FEC_MODE_RS 2
55 HNS3_VECTOR0_EVENT_RST,
56 HNS3_VECTOR0_EVENT_MBX,
57 HNS3_VECTOR0_EVENT_ERR,
58 HNS3_VECTOR0_EVENT_PTP,
59 HNS3_VECTOR0_EVENT_OTHER,
62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
63 { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
64 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
65 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
67 { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
68 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
69 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
70 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
72 { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
73 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
74 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
76 { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
77 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
78 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
79 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
81 { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
82 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
83 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
85 { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
86 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
87 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
95 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
96 static bool hns3_update_link_status(struct hns3_hw *hw);
98 static int hns3_add_mc_addr(struct hns3_hw *hw,
99 struct rte_ether_addr *mac_addr);
100 static int hns3_remove_mc_addr(struct hns3_hw *hw,
101 struct rte_ether_addr *mac_addr);
102 static int hns3_restore_fec(struct hns3_hw *hw);
103 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
104 static int hns3_do_stop(struct hns3_adapter *hns);
105 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
107 void hns3_ether_format_addr(char *buf, uint16_t size,
108 const struct rte_ether_addr *ether_addr)
110 snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
111 ether_addr->addr_bytes[0],
112 ether_addr->addr_bytes[4],
113 ether_addr->addr_bytes[5]);
117 hns3_pf_disable_irq0(struct hns3_hw *hw)
119 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
123 hns3_pf_enable_irq0(struct hns3_hw *hw)
125 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
128 static enum hns3_evt_cause
129 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
132 struct hns3_hw *hw = &hns->hw;
134 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
135 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
136 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
138 hw->reset.stats.imp_cnt++;
139 hns3_warn(hw, "IMP reset detected, clear reset status");
141 hns3_schedule_delayed_reset(hns);
142 hns3_warn(hw, "IMP reset detected, don't clear reset status");
145 return HNS3_VECTOR0_EVENT_RST;
148 static enum hns3_evt_cause
149 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
152 struct hns3_hw *hw = &hns->hw;
154 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
155 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
156 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
158 hw->reset.stats.global_cnt++;
159 hns3_warn(hw, "Global reset detected, clear reset status");
161 hns3_schedule_delayed_reset(hns);
163 "Global reset detected, don't clear reset status");
166 return HNS3_VECTOR0_EVENT_RST;
169 static enum hns3_evt_cause
170 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
172 struct hns3_hw *hw = &hns->hw;
173 uint32_t vector0_int_stats;
174 uint32_t cmdq_src_val;
175 uint32_t hw_err_src_reg;
177 enum hns3_evt_cause ret;
180 /* fetch the events from their corresponding regs */
181 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
182 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
183 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
185 is_delay = clearval == NULL ? true : false;
187 * Assumption: If by any chance reset and mailbox events are reported
188 * together then we will only process reset event and defer the
189 * processing of the mailbox events. Since, we would have not cleared
190 * RX CMDQ event this time we would receive again another interrupt
191 * from H/W just for the mailbox.
193 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
194 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
199 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
200 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
204 /* Check for vector0 1588 event source */
205 if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
206 val = BIT(HNS3_VECTOR0_1588_INT_B);
207 ret = HNS3_VECTOR0_EVENT_PTP;
211 /* check for vector0 msix event source */
212 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
213 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
214 val = vector0_int_stats | hw_err_src_reg;
215 ret = HNS3_VECTOR0_EVENT_ERR;
219 /* check for vector0 mailbox(=CMDQ RX) event source */
220 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
221 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
223 ret = HNS3_VECTOR0_EVENT_MBX;
227 val = vector0_int_stats;
228 ret = HNS3_VECTOR0_EVENT_OTHER;
237 hns3_is_1588_event_type(uint32_t event_type)
239 return (event_type == HNS3_VECTOR0_EVENT_PTP);
243 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
245 if (event_type == HNS3_VECTOR0_EVENT_RST ||
246 hns3_is_1588_event_type(event_type))
247 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
248 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
249 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
253 hns3_clear_all_event_cause(struct hns3_hw *hw)
255 uint32_t vector0_int_stats;
256 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
258 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
259 hns3_warn(hw, "Probe during IMP reset interrupt");
261 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
262 hns3_warn(hw, "Probe during Global reset interrupt");
264 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
265 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
266 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
267 BIT(HNS3_VECTOR0_CORERESET_INT_B));
268 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
269 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
270 BIT(HNS3_VECTOR0_1588_INT_B));
274 hns3_handle_mac_tnl(struct hns3_hw *hw)
276 struct hns3_cmd_desc desc;
280 /* query and clear mac tnl interrupt */
281 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
282 ret = hns3_cmd_send(hw, &desc, 1);
284 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
288 status = rte_le_to_cpu_32(desc.data[0]);
290 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
291 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
293 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
294 ret = hns3_cmd_send(hw, &desc, 1);
296 hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
302 hns3_interrupt_handler(void *param)
304 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
305 struct hns3_adapter *hns = dev->data->dev_private;
306 struct hns3_hw *hw = &hns->hw;
307 enum hns3_evt_cause event_cause;
308 uint32_t clearval = 0;
309 uint32_t vector0_int;
313 /* Disable interrupt */
314 hns3_pf_disable_irq0(hw);
316 event_cause = hns3_check_event_cause(hns, &clearval);
317 vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
318 ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
319 cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
320 /* vector 0 interrupt is shared with reset and mailbox source events. */
321 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
322 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
323 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
324 vector0_int, ras_int, cmdq_int);
325 hns3_handle_mac_tnl(hw);
326 hns3_handle_error(hns);
327 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
328 hns3_warn(hw, "received reset interrupt");
329 hns3_schedule_reset(hns);
330 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
331 hns3_dev_handle_mbx_msg(hw);
333 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
334 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
335 vector0_int, ras_int, cmdq_int);
338 hns3_clear_event_cause(hw, event_cause, clearval);
339 /* Enable interrupt if it is not cause by reset */
340 hns3_pf_enable_irq0(hw);
344 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
346 #define HNS3_VLAN_ID_OFFSET_STEP 160
347 #define HNS3_VLAN_BYTE_SIZE 8
348 struct hns3_vlan_filter_pf_cfg_cmd *req;
349 struct hns3_hw *hw = &hns->hw;
350 uint8_t vlan_offset_byte_val;
351 struct hns3_cmd_desc desc;
352 uint8_t vlan_offset_byte;
353 uint8_t vlan_offset_base;
356 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
358 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
359 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
361 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
363 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
364 req->vlan_offset = vlan_offset_base;
365 req->vlan_cfg = on ? 0 : 1;
366 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
368 ret = hns3_cmd_send(hw, &desc, 1);
370 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
377 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
379 struct hns3_user_vlan_table *vlan_entry;
380 struct hns3_pf *pf = &hns->pf;
382 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
383 if (vlan_entry->vlan_id == vlan_id) {
384 if (vlan_entry->hd_tbl_status)
385 hns3_set_port_vlan_filter(hns, vlan_id, 0);
386 LIST_REMOVE(vlan_entry, next);
387 rte_free(vlan_entry);
394 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
397 struct hns3_user_vlan_table *vlan_entry;
398 struct hns3_hw *hw = &hns->hw;
399 struct hns3_pf *pf = &hns->pf;
401 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
402 if (vlan_entry->vlan_id == vlan_id)
406 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
407 if (vlan_entry == NULL) {
408 hns3_err(hw, "Failed to malloc hns3 vlan table");
412 vlan_entry->hd_tbl_status = writen_to_tbl;
413 vlan_entry->vlan_id = vlan_id;
415 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
419 hns3_restore_vlan_table(struct hns3_adapter *hns)
421 struct hns3_user_vlan_table *vlan_entry;
422 struct hns3_hw *hw = &hns->hw;
423 struct hns3_pf *pf = &hns->pf;
427 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
428 return hns3_vlan_pvid_configure(hns,
429 hw->port_base_vlan_cfg.pvid, 1);
431 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
432 if (vlan_entry->hd_tbl_status) {
433 vlan_id = vlan_entry->vlan_id;
434 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
444 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
446 struct hns3_hw *hw = &hns->hw;
447 bool writen_to_tbl = false;
451 * When vlan filter is enabled, hardware regards packets without vlan
452 * as packets with vlan 0. So, to receive packets without vlan, vlan id
453 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
455 if (on == 0 && vlan_id == 0)
459 * When port base vlan enabled, we use port base vlan as the vlan
460 * filter condition. In this case, we don't update vlan filter table
461 * when user add new vlan or remove exist vlan, just update the
462 * vlan list. The vlan id in vlan list will be written in vlan filter
463 * table until port base vlan disabled
465 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
466 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
467 writen_to_tbl = true;
472 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
474 hns3_rm_dev_vlan_table(hns, vlan_id);
480 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
482 struct hns3_adapter *hns = dev->data->dev_private;
483 struct hns3_hw *hw = &hns->hw;
486 rte_spinlock_lock(&hw->lock);
487 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
488 rte_spinlock_unlock(&hw->lock);
493 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
496 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
497 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
498 struct hns3_hw *hw = &hns->hw;
499 struct hns3_cmd_desc desc;
502 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
503 vlan_type != ETH_VLAN_TYPE_OUTER)) {
504 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
508 if (tpid != RTE_ETHER_TYPE_VLAN) {
509 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
513 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
514 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
516 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
517 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
518 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
519 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
520 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
521 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
522 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
523 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
526 ret = hns3_cmd_send(hw, &desc, 1);
528 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
533 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
535 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
536 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
537 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
539 ret = hns3_cmd_send(hw, &desc, 1);
541 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
547 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
550 struct hns3_adapter *hns = dev->data->dev_private;
551 struct hns3_hw *hw = &hns->hw;
554 rte_spinlock_lock(&hw->lock);
555 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
556 rte_spinlock_unlock(&hw->lock);
561 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
562 struct hns3_rx_vtag_cfg *vcfg)
564 struct hns3_vport_vtag_rx_cfg_cmd *req;
565 struct hns3_hw *hw = &hns->hw;
566 struct hns3_cmd_desc desc;
571 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
573 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
574 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
575 vcfg->strip_tag1_en ? 1 : 0);
576 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
577 vcfg->strip_tag2_en ? 1 : 0);
578 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
579 vcfg->vlan1_vlan_prionly ? 1 : 0);
580 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
581 vcfg->vlan2_vlan_prionly ? 1 : 0);
583 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
584 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
585 vcfg->strip_tag1_discard_en ? 1 : 0);
586 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
587 vcfg->strip_tag2_discard_en ? 1 : 0);
589 * In current version VF is not supported when PF is driven by DPDK
590 * driver, just need to configure parameters for PF vport.
592 vport_id = HNS3_PF_FUNC_ID;
593 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
594 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
595 req->vf_bitmap[req->vf_offset] = bitmap;
597 ret = hns3_cmd_send(hw, &desc, 1);
599 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
604 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
605 struct hns3_rx_vtag_cfg *vcfg)
607 struct hns3_pf *pf = &hns->pf;
608 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
612 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
613 struct hns3_tx_vtag_cfg *vcfg)
615 struct hns3_pf *pf = &hns->pf;
616 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
620 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
622 struct hns3_rx_vtag_cfg rxvlan_cfg;
623 struct hns3_hw *hw = &hns->hw;
626 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
627 rxvlan_cfg.strip_tag1_en = false;
628 rxvlan_cfg.strip_tag2_en = enable;
629 rxvlan_cfg.strip_tag2_discard_en = false;
631 rxvlan_cfg.strip_tag1_en = enable;
632 rxvlan_cfg.strip_tag2_en = true;
633 rxvlan_cfg.strip_tag2_discard_en = true;
636 rxvlan_cfg.strip_tag1_discard_en = false;
637 rxvlan_cfg.vlan1_vlan_prionly = false;
638 rxvlan_cfg.vlan2_vlan_prionly = false;
639 rxvlan_cfg.rx_vlan_offload_en = enable;
641 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
643 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
647 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
653 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
654 uint8_t fe_type, bool filter_en, uint8_t vf_id)
656 struct hns3_vlan_filter_ctrl_cmd *req;
657 struct hns3_cmd_desc desc;
660 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
662 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
663 req->vlan_type = vlan_type;
664 req->vlan_fe = filter_en ? fe_type : 0;
667 ret = hns3_cmd_send(hw, &desc, 1);
669 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
675 hns3_vlan_filter_init(struct hns3_adapter *hns)
677 struct hns3_hw *hw = &hns->hw;
680 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
681 HNS3_FILTER_FE_EGRESS, false,
684 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
688 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
689 HNS3_FILTER_FE_INGRESS, false,
692 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
698 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
700 struct hns3_hw *hw = &hns->hw;
703 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
704 HNS3_FILTER_FE_INGRESS, enable,
707 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
708 enable ? "enable" : "disable", ret);
714 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
716 struct hns3_adapter *hns = dev->data->dev_private;
717 struct hns3_hw *hw = &hns->hw;
718 struct rte_eth_rxmode *rxmode;
719 unsigned int tmp_mask;
723 rte_spinlock_lock(&hw->lock);
724 rxmode = &dev->data->dev_conf.rxmode;
725 tmp_mask = (unsigned int)mask;
726 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
727 /* ignore vlan filter configuration during promiscuous mode */
728 if (!dev->data->promiscuous) {
729 /* Enable or disable VLAN filter */
730 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
733 ret = hns3_enable_vlan_filter(hns, enable);
735 rte_spinlock_unlock(&hw->lock);
736 hns3_err(hw, "failed to %s rx filter, ret = %d",
737 enable ? "enable" : "disable", ret);
743 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
744 /* Enable or disable VLAN stripping */
745 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
748 ret = hns3_en_hw_strip_rxvtag(hns, enable);
750 rte_spinlock_unlock(&hw->lock);
751 hns3_err(hw, "failed to %s rx strip, ret = %d",
752 enable ? "enable" : "disable", ret);
757 rte_spinlock_unlock(&hw->lock);
763 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
764 struct hns3_tx_vtag_cfg *vcfg)
766 struct hns3_vport_vtag_tx_cfg_cmd *req;
767 struct hns3_cmd_desc desc;
768 struct hns3_hw *hw = &hns->hw;
773 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
775 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
776 req->def_vlan_tag1 = vcfg->default_tag1;
777 req->def_vlan_tag2 = vcfg->default_tag2;
778 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
779 vcfg->accept_tag1 ? 1 : 0);
780 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
781 vcfg->accept_untag1 ? 1 : 0);
782 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
783 vcfg->accept_tag2 ? 1 : 0);
784 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
785 vcfg->accept_untag2 ? 1 : 0);
786 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
787 vcfg->insert_tag1_en ? 1 : 0);
788 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
789 vcfg->insert_tag2_en ? 1 : 0);
790 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
792 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
793 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
794 vcfg->tag_shift_mode_en ? 1 : 0);
797 * In current version VF is not supported when PF is driven by DPDK
798 * driver, just need to configure parameters for PF vport.
800 vport_id = HNS3_PF_FUNC_ID;
801 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
802 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
803 req->vf_bitmap[req->vf_offset] = bitmap;
805 ret = hns3_cmd_send(hw, &desc, 1);
807 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
813 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
816 struct hns3_hw *hw = &hns->hw;
817 struct hns3_tx_vtag_cfg txvlan_cfg;
820 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
821 txvlan_cfg.accept_tag1 = true;
822 txvlan_cfg.insert_tag1_en = false;
823 txvlan_cfg.default_tag1 = 0;
825 txvlan_cfg.accept_tag1 =
826 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
827 txvlan_cfg.insert_tag1_en = true;
828 txvlan_cfg.default_tag1 = pvid;
831 txvlan_cfg.accept_untag1 = true;
832 txvlan_cfg.accept_tag2 = true;
833 txvlan_cfg.accept_untag2 = true;
834 txvlan_cfg.insert_tag2_en = false;
835 txvlan_cfg.default_tag2 = 0;
836 txvlan_cfg.tag_shift_mode_en = true;
838 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
840 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
845 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
851 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
853 struct hns3_user_vlan_table *vlan_entry;
854 struct hns3_pf *pf = &hns->pf;
856 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
857 if (vlan_entry->hd_tbl_status) {
858 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
859 vlan_entry->hd_tbl_status = false;
864 vlan_entry = LIST_FIRST(&pf->vlan_list);
866 LIST_REMOVE(vlan_entry, next);
867 rte_free(vlan_entry);
868 vlan_entry = LIST_FIRST(&pf->vlan_list);
874 hns3_add_all_vlan_table(struct hns3_adapter *hns)
876 struct hns3_user_vlan_table *vlan_entry;
877 struct hns3_pf *pf = &hns->pf;
879 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
880 if (!vlan_entry->hd_tbl_status) {
881 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
882 vlan_entry->hd_tbl_status = true;
888 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
890 struct hns3_hw *hw = &hns->hw;
893 hns3_rm_all_vlan_table(hns, true);
894 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
895 ret = hns3_set_port_vlan_filter(hns,
896 hw->port_base_vlan_cfg.pvid, 0);
898 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
906 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
907 uint16_t port_base_vlan_state, uint16_t new_pvid)
909 struct hns3_hw *hw = &hns->hw;
913 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
914 old_pvid = hw->port_base_vlan_cfg.pvid;
915 if (old_pvid != HNS3_INVALID_PVID) {
916 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
918 hns3_err(hw, "failed to remove old pvid %u, "
919 "ret = %d", old_pvid, ret);
924 hns3_rm_all_vlan_table(hns, false);
925 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
927 hns3_err(hw, "failed to add new pvid %u, ret = %d",
932 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
934 hns3_err(hw, "failed to remove pvid %u, ret = %d",
939 hns3_add_all_vlan_table(hns);
945 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
947 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
948 struct hns3_rx_vtag_cfg rx_vlan_cfg;
952 rx_strip_en = old_cfg->rx_vlan_offload_en;
954 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
955 rx_vlan_cfg.strip_tag2_en = true;
956 rx_vlan_cfg.strip_tag2_discard_en = true;
958 rx_vlan_cfg.strip_tag1_en = false;
959 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
960 rx_vlan_cfg.strip_tag2_discard_en = false;
962 rx_vlan_cfg.strip_tag1_discard_en = false;
963 rx_vlan_cfg.vlan1_vlan_prionly = false;
964 rx_vlan_cfg.vlan2_vlan_prionly = false;
965 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
967 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
971 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
976 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
978 struct hns3_hw *hw = &hns->hw;
979 uint16_t port_base_vlan_state;
982 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
983 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
984 hns3_warn(hw, "Invalid operation! As current pvid set "
985 "is %u, disable pvid %u is invalid",
986 hw->port_base_vlan_cfg.pvid, pvid);
990 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
991 HNS3_PORT_BASE_VLAN_DISABLE;
992 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
994 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
999 ret = hns3_en_pvid_strip(hns, on);
1001 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1003 goto pvid_vlan_strip_fail;
1006 if (pvid == HNS3_INVALID_PVID)
1008 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1010 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1012 goto vlan_filter_set_fail;
1016 hw->port_base_vlan_cfg.state = port_base_vlan_state;
1017 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1020 vlan_filter_set_fail:
1021 err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1022 HNS3_PORT_BASE_VLAN_ENABLE);
1024 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1026 pvid_vlan_strip_fail:
1027 err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1028 hw->port_base_vlan_cfg.pvid);
1030 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1036 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1038 struct hns3_adapter *hns = dev->data->dev_private;
1039 struct hns3_hw *hw = &hns->hw;
1040 bool pvid_en_state_change;
1041 uint16_t pvid_state;
1044 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1045 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1046 RTE_ETHER_MAX_VLAN_ID);
1051 * If PVID configuration state change, should refresh the PVID
1052 * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1054 pvid_state = hw->port_base_vlan_cfg.state;
1055 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1056 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1057 pvid_en_state_change = false;
1059 pvid_en_state_change = true;
1061 rte_spinlock_lock(&hw->lock);
1062 ret = hns3_vlan_pvid_configure(hns, pvid, on);
1063 rte_spinlock_unlock(&hw->lock);
1067 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1068 * need be processed by PMD driver.
1070 if (pvid_en_state_change &&
1071 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1072 hns3_update_all_queues_pvid_proc_en(hw);
1078 hns3_default_vlan_config(struct hns3_adapter *hns)
1080 struct hns3_hw *hw = &hns->hw;
1084 * When vlan filter is enabled, hardware regards packets without vlan
1085 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1086 * table, packets without vlan won't be received. So, add vlan 0 as
1089 ret = hns3_vlan_filter_configure(hns, 0, 1);
1091 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1096 hns3_init_vlan_config(struct hns3_adapter *hns)
1098 struct hns3_hw *hw = &hns->hw;
1102 * This function can be called in the initialization and reset process,
1103 * when in reset process, it means that hardware had been reseted
1104 * successfully and we need to restore the hardware configuration to
1105 * ensure that the hardware configuration remains unchanged before and
1108 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1109 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1110 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1113 ret = hns3_vlan_filter_init(hns);
1115 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1119 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1120 RTE_ETHER_TYPE_VLAN);
1122 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1127 * When in the reinit dev stage of the reset process, the following
1128 * vlan-related configurations may differ from those at initialization,
1129 * we will restore configurations to hardware in hns3_restore_vlan_table
1130 * and hns3_restore_vlan_conf later.
1132 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1133 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1135 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1139 ret = hns3_en_hw_strip_rxvtag(hns, false);
1141 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1147 return hns3_default_vlan_config(hns);
1151 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1153 struct hns3_pf *pf = &hns->pf;
1154 struct hns3_hw *hw = &hns->hw;
1159 if (!hw->data->promiscuous) {
1160 /* restore vlan filter states */
1161 offloads = hw->data->dev_conf.rxmode.offloads;
1162 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1163 ret = hns3_enable_vlan_filter(hns, enable);
1165 hns3_err(hw, "failed to restore vlan rx filter conf, "
1171 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1173 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1177 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1179 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1185 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1187 struct hns3_adapter *hns = dev->data->dev_private;
1188 struct rte_eth_dev_data *data = dev->data;
1189 struct rte_eth_txmode *txmode;
1190 struct hns3_hw *hw = &hns->hw;
1194 txmode = &data->dev_conf.txmode;
1195 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1197 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1198 "configuration is not supported! Ignore these two "
1199 "parameters: hw_vlan_reject_tagged(%u), "
1200 "hw_vlan_reject_untagged(%u)",
1201 txmode->hw_vlan_reject_tagged,
1202 txmode->hw_vlan_reject_untagged);
1204 /* Apply vlan offload setting */
1205 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1206 ret = hns3_vlan_offload_set(dev, mask);
1208 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1214 * If pvid config is not set in rte_eth_conf, driver needn't to set
1215 * VLAN pvid related configuration to hardware.
1217 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1220 /* Apply pvid setting */
1221 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1222 txmode->hw_vlan_insert_pvid);
1224 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1231 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1232 unsigned int tso_mss_max)
1234 struct hns3_cfg_tso_status_cmd *req;
1235 struct hns3_cmd_desc desc;
1238 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1240 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1243 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1245 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1248 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1250 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1252 return hns3_cmd_send(hw, &desc, 1);
1256 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1257 uint16_t *allocated_size, bool is_alloc)
1259 struct hns3_umv_spc_alc_cmd *req;
1260 struct hns3_cmd_desc desc;
1263 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1264 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1265 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1266 req->space_size = rte_cpu_to_le_32(space_size);
1268 ret = hns3_cmd_send(hw, &desc, 1);
1270 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1271 is_alloc ? "allocate" : "free", ret);
1275 if (is_alloc && allocated_size)
1276 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1282 hns3_init_umv_space(struct hns3_hw *hw)
1284 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1285 struct hns3_pf *pf = &hns->pf;
1286 uint16_t allocated_size = 0;
1289 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1294 if (allocated_size < pf->wanted_umv_size)
1295 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1296 pf->wanted_umv_size, allocated_size);
1298 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1299 pf->wanted_umv_size;
1300 pf->used_umv_size = 0;
1305 hns3_uninit_umv_space(struct hns3_hw *hw)
1307 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1308 struct hns3_pf *pf = &hns->pf;
1311 if (pf->max_umv_size == 0)
1314 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1318 pf->max_umv_size = 0;
1324 hns3_is_umv_space_full(struct hns3_hw *hw)
1326 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1327 struct hns3_pf *pf = &hns->pf;
1330 is_full = (pf->used_umv_size >= pf->max_umv_size);
1336 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1338 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1339 struct hns3_pf *pf = &hns->pf;
1342 if (pf->used_umv_size > 0)
1343 pf->used_umv_size--;
1345 pf->used_umv_size++;
1349 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1350 const uint8_t *addr, bool is_mc)
1352 const unsigned char *mac_addr = addr;
1353 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1354 ((uint32_t)mac_addr[2] << 16) |
1355 ((uint32_t)mac_addr[1] << 8) |
1356 (uint32_t)mac_addr[0];
1357 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1359 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1361 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1362 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1363 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1366 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1367 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1371 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1373 enum hns3_mac_vlan_tbl_opcode op)
1376 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1381 if (op == HNS3_MAC_VLAN_ADD) {
1382 if (resp_code == 0 || resp_code == 1) {
1384 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1385 hns3_err(hw, "add mac addr failed for uc_overflow");
1387 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1388 hns3_err(hw, "add mac addr failed for mc_overflow");
1392 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1395 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1396 if (resp_code == 0) {
1398 } else if (resp_code == 1) {
1399 hns3_dbg(hw, "remove mac addr failed for miss");
1403 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1406 } else if (op == HNS3_MAC_VLAN_LKUP) {
1407 if (resp_code == 0) {
1409 } else if (resp_code == 1) {
1410 hns3_dbg(hw, "lookup mac addr failed for miss");
1414 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1419 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1426 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1427 struct hns3_mac_vlan_tbl_entry_cmd *req,
1428 struct hns3_cmd_desc *desc, bool is_mc)
1434 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1436 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1437 memcpy(desc[0].data, req,
1438 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1439 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1441 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1442 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1444 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1446 memcpy(desc[0].data, req,
1447 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1448 ret = hns3_cmd_send(hw, desc, 1);
1451 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1455 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1456 retval = rte_le_to_cpu_16(desc[0].retval);
1458 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1459 HNS3_MAC_VLAN_LKUP);
1463 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1464 struct hns3_mac_vlan_tbl_entry_cmd *req,
1465 struct hns3_cmd_desc *mc_desc)
1472 if (mc_desc == NULL) {
1473 struct hns3_cmd_desc desc;
1475 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1476 memcpy(desc.data, req,
1477 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1478 ret = hns3_cmd_send(hw, &desc, 1);
1479 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1480 retval = rte_le_to_cpu_16(desc.retval);
1482 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1485 hns3_cmd_reuse_desc(&mc_desc[0], false);
1486 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1487 hns3_cmd_reuse_desc(&mc_desc[1], false);
1488 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1489 hns3_cmd_reuse_desc(&mc_desc[2], false);
1490 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1491 memcpy(mc_desc[0].data, req,
1492 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1493 mc_desc[0].retval = 0;
1494 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1495 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1496 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1498 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1503 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1511 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1512 struct hns3_mac_vlan_tbl_entry_cmd *req)
1514 struct hns3_cmd_desc desc;
1519 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1521 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1523 ret = hns3_cmd_send(hw, &desc, 1);
1525 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1528 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1529 retval = rte_le_to_cpu_16(desc.retval);
1531 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1532 HNS3_MAC_VLAN_REMOVE);
1536 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1538 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1539 struct hns3_mac_vlan_tbl_entry_cmd req;
1540 struct hns3_pf *pf = &hns->pf;
1541 struct hns3_cmd_desc desc[3];
1542 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1543 uint16_t egress_port = 0;
1547 /* check if mac addr is valid */
1548 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1549 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1551 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1556 memset(&req, 0, sizeof(req));
1559 * In current version VF is not supported when PF is driven by DPDK
1560 * driver, just need to configure parameters for PF vport.
1562 vf_id = HNS3_PF_FUNC_ID;
1563 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1564 HNS3_MAC_EPORT_VFID_S, vf_id);
1566 req.egress_port = rte_cpu_to_le_16(egress_port);
1568 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1571 * Lookup the mac address in the mac_vlan table, and add
1572 * it if the entry is inexistent. Repeated unicast entry
1573 * is not allowed in the mac vlan table.
1575 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1576 if (ret == -ENOENT) {
1577 if (!hns3_is_umv_space_full(hw)) {
1578 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1580 hns3_update_umv_space(hw, false);
1584 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1589 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1591 /* check if we just hit the duplicate */
1593 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1597 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1604 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1606 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1607 struct rte_ether_addr *addr;
1611 for (i = 0; i < hw->mc_addrs_num; i++) {
1612 addr = &hw->mc_addrs[i];
1613 /* Check if there are duplicate addresses */
1614 if (rte_is_same_ether_addr(addr, mac_addr)) {
1615 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1617 hns3_err(hw, "failed to add mc mac addr, same addrs"
1618 "(%s) is added by the set_mc_mac_addr_list "
1624 ret = hns3_add_mc_addr(hw, mac_addr);
1626 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1628 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1635 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1637 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1640 ret = hns3_remove_mc_addr(hw, mac_addr);
1642 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1644 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1651 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1652 uint32_t idx, __rte_unused uint32_t pool)
1654 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1658 rte_spinlock_lock(&hw->lock);
1661 * In hns3 network engine adding UC and MC mac address with different
1662 * commands with firmware. We need to determine whether the input
1663 * address is a UC or a MC address to call different commands.
1664 * By the way, it is recommended calling the API function named
1665 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1666 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1667 * may affect the specifications of UC mac addresses.
1669 if (rte_is_multicast_ether_addr(mac_addr))
1670 ret = hns3_add_mc_addr_common(hw, mac_addr);
1672 ret = hns3_add_uc_addr_common(hw, mac_addr);
1675 rte_spinlock_unlock(&hw->lock);
1676 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1678 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1684 hw->mac.default_addr_setted = true;
1685 rte_spinlock_unlock(&hw->lock);
1691 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1693 struct hns3_mac_vlan_tbl_entry_cmd req;
1694 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1697 /* check if mac addr is valid */
1698 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1699 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1701 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1706 memset(&req, 0, sizeof(req));
1707 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1708 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1709 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1710 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1713 hns3_update_umv_space(hw, true);
1719 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1721 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1722 /* index will be checked by upper level rte interface */
1723 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1724 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1727 rte_spinlock_lock(&hw->lock);
1729 if (rte_is_multicast_ether_addr(mac_addr))
1730 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1732 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1733 rte_spinlock_unlock(&hw->lock);
1735 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1737 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1743 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1744 struct rte_ether_addr *mac_addr)
1746 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1747 struct rte_ether_addr *oaddr;
1748 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1749 bool default_addr_setted;
1750 bool rm_succes = false;
1754 * It has been guaranteed that input parameter named mac_addr is valid
1755 * address in the rte layer of DPDK framework.
1757 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1758 default_addr_setted = hw->mac.default_addr_setted;
1759 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1762 rte_spinlock_lock(&hw->lock);
1763 if (default_addr_setted) {
1764 ret = hns3_remove_uc_addr_common(hw, oaddr);
1766 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1768 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1775 ret = hns3_add_uc_addr_common(hw, mac_addr);
1777 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1779 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1780 goto err_add_uc_addr;
1783 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1785 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1786 goto err_pause_addr_cfg;
1789 rte_ether_addr_copy(mac_addr,
1790 (struct rte_ether_addr *)hw->mac.mac_addr);
1791 hw->mac.default_addr_setted = true;
1792 rte_spinlock_unlock(&hw->lock);
1797 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1799 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1802 "Failed to roll back to del setted mac addr(%s): %d",
1808 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1810 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1813 "Failed to restore old uc mac addr(%s): %d",
1815 hw->mac.default_addr_setted = false;
1818 rte_spinlock_unlock(&hw->lock);
1824 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1826 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1827 struct hns3_hw *hw = &hns->hw;
1828 struct rte_ether_addr *addr;
1833 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1834 addr = &hw->data->mac_addrs[i];
1835 if (rte_is_zero_ether_addr(addr))
1837 if (rte_is_multicast_ether_addr(addr))
1838 ret = del ? hns3_remove_mc_addr(hw, addr) :
1839 hns3_add_mc_addr(hw, addr);
1841 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1842 hns3_add_uc_addr_common(hw, addr);
1846 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1848 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1849 "ret = %d.", del ? "remove" : "restore",
1857 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1859 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1863 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1864 word_num = vfid / 32;
1865 bit_num = vfid % 32;
1867 desc[1].data[word_num] &=
1868 rte_cpu_to_le_32(~(1UL << bit_num));
1870 desc[1].data[word_num] |=
1871 rte_cpu_to_le_32(1UL << bit_num);
1873 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1874 bit_num = vfid % 32;
1876 desc[2].data[word_num] &=
1877 rte_cpu_to_le_32(~(1UL << bit_num));
1879 desc[2].data[word_num] |=
1880 rte_cpu_to_le_32(1UL << bit_num);
1885 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1887 struct hns3_mac_vlan_tbl_entry_cmd req;
1888 struct hns3_cmd_desc desc[3];
1889 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1893 /* Check if mac addr is valid */
1894 if (!rte_is_multicast_ether_addr(mac_addr)) {
1895 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1897 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1902 memset(&req, 0, sizeof(req));
1903 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1904 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1905 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1907 /* This mac addr do not exist, add new entry for it */
1908 memset(desc[0].data, 0, sizeof(desc[0].data));
1909 memset(desc[1].data, 0, sizeof(desc[0].data));
1910 memset(desc[2].data, 0, sizeof(desc[0].data));
1914 * In current version VF is not supported when PF is driven by DPDK
1915 * driver, just need to configure parameters for PF vport.
1917 vf_id = HNS3_PF_FUNC_ID;
1918 hns3_update_desc_vfid(desc, vf_id, false);
1919 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1922 hns3_err(hw, "mc mac vlan table is full");
1923 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1925 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1932 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1934 struct hns3_mac_vlan_tbl_entry_cmd req;
1935 struct hns3_cmd_desc desc[3];
1936 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1940 /* Check if mac addr is valid */
1941 if (!rte_is_multicast_ether_addr(mac_addr)) {
1942 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1944 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1949 memset(&req, 0, sizeof(req));
1950 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1951 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1952 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1955 * This mac addr exist, remove this handle's VFID for it.
1956 * In current version VF is not supported when PF is driven by
1957 * DPDK driver, just need to configure parameters for PF vport.
1959 vf_id = HNS3_PF_FUNC_ID;
1960 hns3_update_desc_vfid(desc, vf_id, true);
1962 /* All the vfid is zero, so need to delete this entry */
1963 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1964 } else if (ret == -ENOENT) {
1965 /* This mac addr doesn't exist. */
1970 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1972 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1979 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1980 struct rte_ether_addr *mc_addr_set,
1981 uint32_t nb_mc_addr)
1983 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1984 struct rte_ether_addr *addr;
1988 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1989 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1990 "invalid. valid range: 0~%d",
1991 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1995 /* Check if input mac addresses are valid */
1996 for (i = 0; i < nb_mc_addr; i++) {
1997 addr = &mc_addr_set[i];
1998 if (!rte_is_multicast_ether_addr(addr)) {
1999 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2002 "failed to set mc mac addr, addr(%s) invalid.",
2007 /* Check if there are duplicate addresses */
2008 for (j = i + 1; j < nb_mc_addr; j++) {
2009 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2010 hns3_ether_format_addr(mac_str,
2011 RTE_ETHER_ADDR_FMT_SIZE,
2013 hns3_err(hw, "failed to set mc mac addr, "
2014 "addrs invalid. two same addrs(%s).",
2021 * Check if there are duplicate addresses between mac_addrs
2024 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2025 if (rte_is_same_ether_addr(addr,
2026 &hw->data->mac_addrs[j])) {
2027 hns3_ether_format_addr(mac_str,
2028 RTE_ETHER_ADDR_FMT_SIZE,
2030 hns3_err(hw, "failed to set mc mac addr, "
2031 "addrs invalid. addrs(%s) has already "
2032 "configured in mac_addr add API",
2043 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2044 struct rte_ether_addr *mc_addr_set,
2046 struct rte_ether_addr *reserved_addr_list,
2047 int *reserved_addr_num,
2048 struct rte_ether_addr *add_addr_list,
2050 struct rte_ether_addr *rm_addr_list,
2053 struct rte_ether_addr *addr;
2054 int current_addr_num;
2055 int reserved_num = 0;
2063 /* Calculate the mc mac address list that should be removed */
2064 current_addr_num = hw->mc_addrs_num;
2065 for (i = 0; i < current_addr_num; i++) {
2066 addr = &hw->mc_addrs[i];
2068 for (j = 0; j < mc_addr_num; j++) {
2069 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2076 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2079 rte_ether_addr_copy(addr,
2080 &reserved_addr_list[reserved_num]);
2085 /* Calculate the mc mac address list that should be added */
2086 for (i = 0; i < mc_addr_num; i++) {
2087 addr = &mc_addr_set[i];
2089 for (j = 0; j < current_addr_num; j++) {
2090 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2097 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2102 /* Reorder the mc mac address list maintained by driver */
2103 for (i = 0; i < reserved_num; i++)
2104 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2106 for (i = 0; i < rm_num; i++) {
2107 num = reserved_num + i;
2108 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2111 *reserved_addr_num = reserved_num;
2112 *add_addr_num = add_num;
2113 *rm_addr_num = rm_num;
2117 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2118 struct rte_ether_addr *mc_addr_set,
2119 uint32_t nb_mc_addr)
2121 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2122 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2123 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2124 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2125 struct rte_ether_addr *addr;
2126 int reserved_addr_num;
2134 /* Check if input parameters are valid */
2135 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2139 rte_spinlock_lock(&hw->lock);
2142 * Calculate the mc mac address lists those should be removed and be
2143 * added, Reorder the mc mac address list maintained by driver.
2145 mc_addr_num = (int)nb_mc_addr;
2146 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2147 reserved_addr_list, &reserved_addr_num,
2148 add_addr_list, &add_addr_num,
2149 rm_addr_list, &rm_addr_num);
2151 /* Remove mc mac addresses */
2152 for (i = 0; i < rm_addr_num; i++) {
2153 num = rm_addr_num - i - 1;
2154 addr = &rm_addr_list[num];
2155 ret = hns3_remove_mc_addr(hw, addr);
2157 rte_spinlock_unlock(&hw->lock);
2163 /* Add mc mac addresses */
2164 for (i = 0; i < add_addr_num; i++) {
2165 addr = &add_addr_list[i];
2166 ret = hns3_add_mc_addr(hw, addr);
2168 rte_spinlock_unlock(&hw->lock);
2172 num = reserved_addr_num + i;
2173 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2176 rte_spinlock_unlock(&hw->lock);
2182 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2184 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2185 struct hns3_hw *hw = &hns->hw;
2186 struct rte_ether_addr *addr;
2191 for (i = 0; i < hw->mc_addrs_num; i++) {
2192 addr = &hw->mc_addrs[i];
2193 if (!rte_is_multicast_ether_addr(addr))
2196 ret = hns3_remove_mc_addr(hw, addr);
2198 ret = hns3_add_mc_addr(hw, addr);
2201 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2203 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2204 del ? "Remove" : "Restore", mac_str, ret);
2211 hns3_check_mq_mode(struct rte_eth_dev *dev)
2213 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2214 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2215 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2217 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2218 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2223 if ((rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG) ||
2224 (tx_mq_mode == ETH_MQ_TX_VMDQ_DCB ||
2225 tx_mq_mode == ETH_MQ_TX_VMDQ_ONLY)) {
2226 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
2227 rx_mq_mode, tx_mq_mode);
2231 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2232 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2233 if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
2234 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2235 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2236 dcb_rx_conf->nb_tcs, pf->tc_max);
2240 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2241 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2242 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2243 "nb_tcs(%d) != %d or %d in rx direction.",
2244 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2248 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2249 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2250 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2254 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2255 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2256 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2257 "is not equal to one in tx direction.",
2258 i, dcb_rx_conf->dcb_tc[i]);
2261 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2262 max_tc = dcb_rx_conf->dcb_tc[i];
2265 num_tc = max_tc + 1;
2266 if (num_tc > dcb_rx_conf->nb_tcs) {
2267 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2268 num_tc, dcb_rx_conf->nb_tcs);
2277 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2279 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2281 if (!hns3_dev_dcb_supported(hw)) {
2282 hns3_err(hw, "this port does not support dcb configurations.");
2286 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2287 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2295 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2296 enum hns3_ring_type queue_type, uint16_t queue_id)
2298 struct hns3_cmd_desc desc;
2299 struct hns3_ctrl_vector_chain_cmd *req =
2300 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2301 enum hns3_opcode_type op;
2302 uint16_t tqp_type_and_id = 0;
2307 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2308 hns3_cmd_setup_basic_desc(&desc, op, false);
2309 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2310 HNS3_TQP_INT_ID_L_S);
2311 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2312 HNS3_TQP_INT_ID_H_S);
2314 if (queue_type == HNS3_RING_TYPE_RX)
2315 gl = HNS3_RING_GL_RX;
2317 gl = HNS3_RING_GL_TX;
2321 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2323 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2324 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2326 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2327 req->int_cause_num = 1;
2328 ret = hns3_cmd_send(hw, &desc, 1);
2330 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2331 en ? "Map" : "Unmap", queue_id, vector_id, ret);
2339 hns3_init_ring_with_vector(struct hns3_hw *hw)
2346 * In hns3 network engine, vector 0 is always the misc interrupt of this
2347 * function, vector 1~N can be used respectively for the queues of the
2348 * function. Tx and Rx queues with the same number share the interrupt
2349 * vector. In the initialization clearing the all hardware mapping
2350 * relationship configurations between queues and interrupt vectors is
2351 * needed, so some error caused by the residual configurations, such as
2352 * the unexpected Tx interrupt, can be avoid.
2354 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2355 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2356 vec = vec - 1; /* the last interrupt is reserved */
2357 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2358 for (i = 0; i < hw->intr_tqps_num; i++) {
2360 * Set gap limiter/rate limiter/quanity limiter algorithm
2361 * configuration for interrupt coalesce of queue's interrupt.
2363 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2364 HNS3_TQP_INTR_GL_DEFAULT);
2365 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2366 HNS3_TQP_INTR_GL_DEFAULT);
2367 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2369 * QL(quantity limiter) is not used currently, just set 0 to
2372 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2374 ret = hns3_bind_ring_with_vector(hw, vec, false,
2375 HNS3_RING_TYPE_TX, i);
2377 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2378 "vector: %u, ret=%d", i, vec, ret);
2382 ret = hns3_bind_ring_with_vector(hw, vec, false,
2383 HNS3_RING_TYPE_RX, i);
2385 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2386 "vector: %u, ret=%d", i, vec, ret);
2395 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2397 struct hns3_adapter *hns = dev->data->dev_private;
2398 struct hns3_hw *hw = &hns->hw;
2399 uint32_t max_rx_pkt_len;
2403 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2407 * If jumbo frames are enabled, MTU needs to be refreshed
2408 * according to the maximum RX packet length.
2410 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2411 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2412 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2413 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2414 "and no more than %u when jumbo frame enabled.",
2415 (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2416 (uint16_t)HNS3_MAX_FRAME_LEN);
2420 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2421 ret = hns3_dev_mtu_set(dev, mtu);
2424 dev->data->mtu = mtu;
2430 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
2435 * Some hardware doesn't support auto-negotiation, but users may not
2436 * configure link_speeds (default 0), which means auto-negotiation.
2437 * In this case, a warning message need to be printed, instead of
2440 if (link_speeds == ETH_LINK_SPEED_AUTONEG &&
2441 hw->mac.support_autoneg == 0) {
2442 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
2446 if (link_speeds != ETH_LINK_SPEED_AUTONEG) {
2447 ret = hns3_check_port_speed(hw, link_speeds);
2456 hns3_check_dev_conf(struct rte_eth_dev *dev)
2458 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2459 struct rte_eth_conf *conf = &dev->data->dev_conf;
2462 ret = hns3_check_mq_mode(dev);
2466 return hns3_check_link_speed(hw, conf->link_speeds);
2470 hns3_dev_configure(struct rte_eth_dev *dev)
2472 struct hns3_adapter *hns = dev->data->dev_private;
2473 struct rte_eth_conf *conf = &dev->data->dev_conf;
2474 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2475 struct hns3_hw *hw = &hns->hw;
2476 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2477 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2478 struct rte_eth_rss_conf rss_conf;
2482 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2485 * Some versions of hardware network engine does not support
2486 * individually enable/disable/reset the Tx or Rx queue. These devices
2487 * must enable/disable/reset Tx and Rx queues at the same time. When the
2488 * numbers of Tx queues allocated by upper applications are not equal to
2489 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2490 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2491 * work as usual. But these fake queues are imperceptible, and can not
2492 * be used by upper applications.
2494 if (!hns3_dev_indep_txrx_supported(hw)) {
2495 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2497 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2503 hw->adapter_state = HNS3_NIC_CONFIGURING;
2504 ret = hns3_check_dev_conf(dev);
2508 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2509 ret = hns3_check_dcb_cfg(dev);
2514 /* When RSS is not configured, redirect the packet queue 0 */
2515 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2516 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2517 rss_conf = conf->rx_adv_conf.rss_conf;
2518 hw->rss_dis_flag = false;
2519 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2524 ret = hns3_refresh_mtu(dev, conf);
2528 ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2532 ret = hns3_dev_configure_vlan(dev);
2536 /* config hardware GRO */
2537 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2538 ret = hns3_config_gro(hw, gro_en);
2542 hns3_init_rx_ptype_tble(dev);
2543 hw->adapter_state = HNS3_NIC_CONFIGURED;
2548 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2549 hw->adapter_state = HNS3_NIC_INITIALIZED;
2555 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2557 struct hns3_config_max_frm_size_cmd *req;
2558 struct hns3_cmd_desc desc;
2560 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2562 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2563 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2564 req->min_frm_size = RTE_ETHER_MIN_LEN;
2566 return hns3_cmd_send(hw, &desc, 1);
2570 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2572 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2573 uint16_t original_mps = hns->pf.mps;
2577 ret = hns3_set_mac_mtu(hw, mps);
2579 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2584 ret = hns3_buffer_alloc(hw);
2586 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2593 err = hns3_set_mac_mtu(hw, original_mps);
2595 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2598 hns->pf.mps = original_mps;
2604 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2606 struct hns3_adapter *hns = dev->data->dev_private;
2607 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2608 struct hns3_hw *hw = &hns->hw;
2609 bool is_jumbo_frame;
2612 if (dev->data->dev_started) {
2613 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2614 "before configuration", dev->data->port_id);
2618 rte_spinlock_lock(&hw->lock);
2619 is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2620 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2623 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2624 * assign to "uint16_t" type variable.
2626 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2628 rte_spinlock_unlock(&hw->lock);
2629 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2630 dev->data->port_id, mtu, ret);
2635 dev->data->dev_conf.rxmode.offloads |=
2636 DEV_RX_OFFLOAD_JUMBO_FRAME;
2638 dev->data->dev_conf.rxmode.offloads &=
2639 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2640 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2641 rte_spinlock_unlock(&hw->lock);
2647 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2649 uint32_t speed_capa = 0;
2651 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2652 speed_capa |= ETH_LINK_SPEED_10M_HD;
2653 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2654 speed_capa |= ETH_LINK_SPEED_10M;
2655 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2656 speed_capa |= ETH_LINK_SPEED_100M_HD;
2657 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2658 speed_capa |= ETH_LINK_SPEED_100M;
2659 if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2660 speed_capa |= ETH_LINK_SPEED_1G;
2666 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2668 uint32_t speed_capa = 0;
2670 if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2671 speed_capa |= ETH_LINK_SPEED_1G;
2672 if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2673 speed_capa |= ETH_LINK_SPEED_10G;
2674 if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2675 speed_capa |= ETH_LINK_SPEED_25G;
2676 if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2677 speed_capa |= ETH_LINK_SPEED_40G;
2678 if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2679 speed_capa |= ETH_LINK_SPEED_50G;
2680 if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2681 speed_capa |= ETH_LINK_SPEED_100G;
2682 if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2683 speed_capa |= ETH_LINK_SPEED_200G;
2689 hns3_get_speed_capa(struct hns3_hw *hw)
2691 struct hns3_mac *mac = &hw->mac;
2692 uint32_t speed_capa;
2694 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2696 hns3_get_copper_port_speed_capa(mac->supported_speed);
2699 hns3_get_firber_port_speed_capa(mac->supported_speed);
2701 if (mac->support_autoneg == 0)
2702 speed_capa |= ETH_LINK_SPEED_FIXED;
2708 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2710 struct hns3_adapter *hns = eth_dev->data->dev_private;
2711 struct hns3_hw *hw = &hns->hw;
2712 uint16_t queue_num = hw->tqps_num;
2715 * In interrupt mode, 'max_rx_queues' is set based on the number of
2716 * MSI-X interrupt resources of the hardware.
2718 if (hw->data->dev_conf.intr_conf.rxq == 1)
2719 queue_num = hw->intr_tqps_num;
2721 info->max_rx_queues = queue_num;
2722 info->max_tx_queues = hw->tqps_num;
2723 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2724 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2725 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2726 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2727 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2728 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2729 DEV_RX_OFFLOAD_TCP_CKSUM |
2730 DEV_RX_OFFLOAD_UDP_CKSUM |
2731 DEV_RX_OFFLOAD_SCTP_CKSUM |
2732 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2733 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2734 DEV_RX_OFFLOAD_KEEP_CRC |
2735 DEV_RX_OFFLOAD_SCATTER |
2736 DEV_RX_OFFLOAD_VLAN_STRIP |
2737 DEV_RX_OFFLOAD_VLAN_FILTER |
2738 DEV_RX_OFFLOAD_JUMBO_FRAME |
2739 DEV_RX_OFFLOAD_RSS_HASH |
2740 DEV_RX_OFFLOAD_TCP_LRO);
2741 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2742 DEV_TX_OFFLOAD_IPV4_CKSUM |
2743 DEV_TX_OFFLOAD_TCP_CKSUM |
2744 DEV_TX_OFFLOAD_UDP_CKSUM |
2745 DEV_TX_OFFLOAD_SCTP_CKSUM |
2746 DEV_TX_OFFLOAD_MULTI_SEGS |
2747 DEV_TX_OFFLOAD_TCP_TSO |
2748 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2749 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2750 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2751 DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2752 hns3_txvlan_cap_get(hw));
2754 if (hns3_dev_outer_udp_cksum_supported(hw))
2755 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2757 if (hns3_dev_indep_txrx_supported(hw))
2758 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2759 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2761 if (hns3_dev_ptp_supported(hw))
2762 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2764 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2765 .nb_max = HNS3_MAX_RING_DESC,
2766 .nb_min = HNS3_MIN_RING_DESC,
2767 .nb_align = HNS3_ALIGN_RING_DESC,
2770 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2771 .nb_max = HNS3_MAX_RING_DESC,
2772 .nb_min = HNS3_MIN_RING_DESC,
2773 .nb_align = HNS3_ALIGN_RING_DESC,
2774 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2775 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2778 info->speed_capa = hns3_get_speed_capa(hw);
2779 info->default_rxconf = (struct rte_eth_rxconf) {
2780 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2782 * If there are no available Rx buffer descriptors, incoming
2783 * packets are always dropped by hardware based on hns3 network
2789 info->default_txconf = (struct rte_eth_txconf) {
2790 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2794 info->vmdq_queue_num = 0;
2796 info->reta_size = hw->rss_ind_tbl_size;
2797 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2798 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2800 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2801 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2802 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2803 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2804 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2805 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2811 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2814 struct hns3_adapter *hns = eth_dev->data->dev_private;
2815 struct hns3_hw *hw = &hns->hw;
2816 uint32_t version = hw->fw_version;
2819 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2820 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2821 HNS3_FW_VERSION_BYTE3_S),
2822 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2823 HNS3_FW_VERSION_BYTE2_S),
2824 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2825 HNS3_FW_VERSION_BYTE1_S),
2826 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2827 HNS3_FW_VERSION_BYTE0_S));
2831 ret += 1; /* add the size of '\0' */
2832 if (fw_size < (size_t)ret)
2839 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2841 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2844 (void)hns3_update_link_status(hw);
2846 ret = hns3_update_link_info(eth_dev);
2848 hw->mac.link_status = ETH_LINK_DOWN;
2854 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2855 struct rte_eth_link *new_link)
2857 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2858 struct hns3_mac *mac = &hw->mac;
2860 switch (mac->link_speed) {
2861 case ETH_SPEED_NUM_10M:
2862 case ETH_SPEED_NUM_100M:
2863 case ETH_SPEED_NUM_1G:
2864 case ETH_SPEED_NUM_10G:
2865 case ETH_SPEED_NUM_25G:
2866 case ETH_SPEED_NUM_40G:
2867 case ETH_SPEED_NUM_50G:
2868 case ETH_SPEED_NUM_100G:
2869 case ETH_SPEED_NUM_200G:
2870 if (mac->link_status)
2871 new_link->link_speed = mac->link_speed;
2874 if (mac->link_status)
2875 new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2879 if (!mac->link_status)
2880 new_link->link_speed = ETH_SPEED_NUM_NONE;
2882 new_link->link_duplex = mac->link_duplex;
2883 new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2884 new_link->link_autoneg = mac->link_autoneg;
2888 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2890 #define HNS3_LINK_CHECK_INTERVAL 100 /* 100ms */
2891 #define HNS3_MAX_LINK_CHECK_TIMES 20 /* 2s (100 * 20ms) in total */
2893 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2894 uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2895 struct hns3_mac *mac = &hw->mac;
2896 struct rte_eth_link new_link;
2899 /* When port is stopped, report link down. */
2900 if (eth_dev->data->dev_started == 0) {
2901 new_link.link_autoneg = mac->link_autoneg;
2902 new_link.link_duplex = mac->link_duplex;
2903 new_link.link_speed = ETH_SPEED_NUM_NONE;
2904 new_link.link_status = ETH_LINK_DOWN;
2909 ret = hns3_update_port_link_info(eth_dev);
2911 hns3_err(hw, "failed to get port link info, ret = %d.",
2916 if (!wait_to_complete || mac->link_status == ETH_LINK_UP)
2919 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2920 } while (retry_cnt--);
2922 memset(&new_link, 0, sizeof(new_link));
2923 hns3_setup_linkstatus(eth_dev, &new_link);
2926 return rte_eth_linkstatus_set(eth_dev, &new_link);
2930 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2932 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2933 struct hns3_pf *pf = &hns->pf;
2935 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2938 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2944 hns3_query_function_status(struct hns3_hw *hw)
2946 #define HNS3_QUERY_MAX_CNT 10
2947 #define HNS3_QUERY_SLEEP_MSCOEND 1
2948 struct hns3_func_status_cmd *req;
2949 struct hns3_cmd_desc desc;
2953 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2954 req = (struct hns3_func_status_cmd *)desc.data;
2957 ret = hns3_cmd_send(hw, &desc, 1);
2959 PMD_INIT_LOG(ERR, "query function status failed %d",
2964 /* Check pf reset is done */
2968 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2969 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2971 return hns3_parse_func_status(hw, req);
2975 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2977 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2978 struct hns3_pf *pf = &hns->pf;
2980 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2982 * The total_tqps_num obtained from firmware is maximum tqp
2983 * numbers of this port, which should be used for PF and VFs.
2984 * There is no need for pf to have so many tqp numbers in
2985 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2986 * coming from config file, is assigned to maximum queue number
2987 * for the PF of this port by user. So users can modify the
2988 * maximum queue number of PF according to their own application
2989 * scenarios, which is more flexible to use. In addition, many
2990 * memories can be saved due to allocating queue statistics
2991 * room according to the actual number of queues required. The
2992 * maximum queue number of PF for network engine with
2993 * revision_id greater than 0x30 is assigned by config file.
2995 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2996 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2997 "must be greater than 0.",
2998 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
3002 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
3003 hw->total_tqps_num);
3006 * Due to the limitation on the number of PF interrupts
3007 * available, the maximum queue number assigned to PF on
3008 * the network engine with revision_id 0x21 is 64.
3010 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
3011 HNS3_MAX_TQP_NUM_HIP08_PF);
3018 hns3_query_pf_resource(struct hns3_hw *hw)
3020 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3021 struct hns3_pf *pf = &hns->pf;
3022 struct hns3_pf_res_cmd *req;
3023 struct hns3_cmd_desc desc;
3026 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
3027 ret = hns3_cmd_send(hw, &desc, 1);
3029 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
3033 req = (struct hns3_pf_res_cmd *)desc.data;
3034 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
3035 rte_le_to_cpu_16(req->ext_tqp_num);
3036 ret = hns3_get_pf_max_tqp_num(hw);
3040 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
3041 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
3043 if (req->tx_buf_size)
3045 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
3047 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
3049 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
3051 if (req->dv_buf_size)
3053 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3055 pf->dv_buf_size = HNS3_DEFAULT_DV;
3057 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3060 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3061 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3067 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3069 struct hns3_cfg_param_cmd *req;
3070 uint64_t mac_addr_tmp_high;
3071 uint8_t ext_rss_size_max;
3072 uint64_t mac_addr_tmp;
3075 req = (struct hns3_cfg_param_cmd *)desc[0].data;
3077 /* get the configuration */
3078 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3079 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
3080 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3081 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3082 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3083 HNS3_CFG_TQP_DESC_N_M,
3084 HNS3_CFG_TQP_DESC_N_S);
3086 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3087 HNS3_CFG_PHY_ADDR_M,
3088 HNS3_CFG_PHY_ADDR_S);
3089 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3090 HNS3_CFG_MEDIA_TP_M,
3091 HNS3_CFG_MEDIA_TP_S);
3092 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3093 HNS3_CFG_RX_BUF_LEN_M,
3094 HNS3_CFG_RX_BUF_LEN_S);
3095 /* get mac address */
3096 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3097 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3098 HNS3_CFG_MAC_ADDR_H_M,
3099 HNS3_CFG_MAC_ADDR_H_S);
3101 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3103 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3104 HNS3_CFG_DEFAULT_SPEED_M,
3105 HNS3_CFG_DEFAULT_SPEED_S);
3106 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3107 HNS3_CFG_RSS_SIZE_M,
3108 HNS3_CFG_RSS_SIZE_S);
3110 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3111 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3113 req = (struct hns3_cfg_param_cmd *)desc[1].data;
3114 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3116 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3117 HNS3_CFG_SPEED_ABILITY_M,
3118 HNS3_CFG_SPEED_ABILITY_S);
3119 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3120 HNS3_CFG_UMV_TBL_SPACE_M,
3121 HNS3_CFG_UMV_TBL_SPACE_S);
3122 if (!cfg->umv_space)
3123 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3125 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3126 HNS3_CFG_EXT_RSS_SIZE_M,
3127 HNS3_CFG_EXT_RSS_SIZE_S);
3130 * Field ext_rss_size_max obtained from firmware will be more flexible
3131 * for future changes and expansions, which is an exponent of 2, instead
3132 * of reading out directly. If this field is not zero, hns3 PF PMD
3133 * driver uses it as rss_size_max under one TC. Device, whose revision
3134 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3135 * maximum number of queues supported under a TC through this field.
3137 if (ext_rss_size_max)
3138 cfg->rss_size_max = 1U << ext_rss_size_max;
3141 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3142 * @hw: pointer to struct hns3_hw
3143 * @hcfg: the config structure to be getted
3146 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3148 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3149 struct hns3_cfg_param_cmd *req;
3154 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3156 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3157 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3159 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3160 i * HNS3_CFG_RD_LEN_BYTES);
3161 /* Len should be divided by 4 when send to hardware */
3162 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3163 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3164 req->offset = rte_cpu_to_le_32(offset);
3167 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3169 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3173 hns3_parse_cfg(hcfg, desc);
3179 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3181 switch (speed_cmd) {
3182 case HNS3_CFG_SPEED_10M:
3183 *speed = ETH_SPEED_NUM_10M;
3185 case HNS3_CFG_SPEED_100M:
3186 *speed = ETH_SPEED_NUM_100M;
3188 case HNS3_CFG_SPEED_1G:
3189 *speed = ETH_SPEED_NUM_1G;
3191 case HNS3_CFG_SPEED_10G:
3192 *speed = ETH_SPEED_NUM_10G;
3194 case HNS3_CFG_SPEED_25G:
3195 *speed = ETH_SPEED_NUM_25G;
3197 case HNS3_CFG_SPEED_40G:
3198 *speed = ETH_SPEED_NUM_40G;
3200 case HNS3_CFG_SPEED_50G:
3201 *speed = ETH_SPEED_NUM_50G;
3203 case HNS3_CFG_SPEED_100G:
3204 *speed = ETH_SPEED_NUM_100G;
3206 case HNS3_CFG_SPEED_200G:
3207 *speed = ETH_SPEED_NUM_200G;
3217 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3219 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3220 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3221 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3222 hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3223 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3227 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3229 struct hns3_dev_specs_0_cmd *req0;
3231 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3233 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3234 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3235 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3236 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3237 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3241 hns3_check_dev_specifications(struct hns3_hw *hw)
3243 if (hw->rss_ind_tbl_size == 0 ||
3244 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3245 hns3_err(hw, "the size of hash lookup table configured (%u)"
3246 " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3247 HNS3_RSS_IND_TBL_SIZE_MAX);
3255 hns3_query_dev_specifications(struct hns3_hw *hw)
3257 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3261 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3262 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3264 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3266 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3268 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3272 hns3_parse_dev_specifications(hw, desc);
3274 return hns3_check_dev_specifications(hw);
3278 hns3_get_capability(struct hns3_hw *hw)
3280 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3281 struct rte_pci_device *pci_dev;
3282 struct hns3_pf *pf = &hns->pf;
3283 struct rte_eth_dev *eth_dev;
3288 eth_dev = &rte_eth_devices[hw->data->port_id];
3289 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3290 device_id = pci_dev->id.device_id;
3292 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3293 device_id == HNS3_DEV_ID_50GE_RDMA ||
3294 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3295 device_id == HNS3_DEV_ID_200G_RDMA)
3296 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3298 /* Get PCI revision id */
3299 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3300 HNS3_PCI_REVISION_ID);
3301 if (ret != HNS3_PCI_REVISION_ID_LEN) {
3302 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3306 hw->revision = revision;
3308 if (revision < PCI_REVISION_ID_HIP09_A) {
3309 hns3_set_default_dev_specifications(hw);
3310 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3311 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3312 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3313 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3314 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3315 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3316 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3317 hw->rss_info.ipv6_sctp_offload_supported = false;
3318 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3322 ret = hns3_query_dev_specifications(hw);
3325 "failed to query dev specifications, ret = %d",
3330 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3331 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3332 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3333 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3334 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3335 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3336 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3337 hw->rss_info.ipv6_sctp_offload_supported = true;
3338 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3344 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3348 switch (media_type) {
3349 case HNS3_MEDIA_TYPE_COPPER:
3350 if (!hns3_dev_copper_supported(hw)) {
3352 "Media type is copper, not supported.");
3358 case HNS3_MEDIA_TYPE_FIBER:
3361 case HNS3_MEDIA_TYPE_BACKPLANE:
3362 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3366 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3375 hns3_get_board_configuration(struct hns3_hw *hw)
3377 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3378 struct hns3_pf *pf = &hns->pf;
3379 struct hns3_cfg cfg;
3382 ret = hns3_get_board_cfg(hw, &cfg);
3384 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3388 ret = hns3_check_media_type(hw, cfg.media_type);
3392 hw->mac.media_type = cfg.media_type;
3393 hw->rss_size_max = cfg.rss_size_max;
3394 hw->rss_dis_flag = false;
3395 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3396 hw->mac.phy_addr = cfg.phy_addr;
3397 hw->mac.default_addr_setted = false;
3398 hw->num_tx_desc = cfg.tqp_desc_num;
3399 hw->num_rx_desc = cfg.tqp_desc_num;
3400 hw->dcb_info.num_pg = 1;
3401 hw->dcb_info.hw_pfc_map = 0;
3403 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3405 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3406 cfg.default_speed, ret);
3410 pf->tc_max = cfg.tc_num;
3411 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3412 PMD_INIT_LOG(WARNING,
3413 "Get TC num(%u) from flash, set TC num to 1",
3418 /* Dev does not support DCB */
3419 if (!hns3_dev_dcb_supported(hw)) {
3423 pf->pfc_max = pf->tc_max;
3425 hw->dcb_info.num_tc = 1;
3426 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3427 hw->tqps_num / hw->dcb_info.num_tc);
3428 hns3_set_bit(hw->hw_tc_map, 0, 1);
3429 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3431 pf->wanted_umv_size = cfg.umv_space;
3437 hns3_get_configuration(struct hns3_hw *hw)
3441 ret = hns3_query_function_status(hw);
3443 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3447 /* Get device capability */
3448 ret = hns3_get_capability(hw);
3450 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3454 /* Get pf resource */
3455 ret = hns3_query_pf_resource(hw);
3457 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3461 ret = hns3_get_board_configuration(hw);
3463 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3467 ret = hns3_query_dev_fec_info(hw);
3470 "failed to query FEC information, ret = %d", ret);
3476 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3477 uint16_t tqp_vid, bool is_pf)
3479 struct hns3_tqp_map_cmd *req;
3480 struct hns3_cmd_desc desc;
3483 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3485 req = (struct hns3_tqp_map_cmd *)desc.data;
3486 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3487 req->tqp_vf = func_id;
3488 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3490 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3491 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3493 ret = hns3_cmd_send(hw, &desc, 1);
3495 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3501 hns3_map_tqp(struct hns3_hw *hw)
3507 * In current version, VF is not supported when PF is driven by DPDK
3508 * driver, so we assign total tqps_num tqps allocated to this port
3511 for (i = 0; i < hw->total_tqps_num; i++) {
3512 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3521 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3523 struct hns3_config_mac_speed_dup_cmd *req;
3524 struct hns3_cmd_desc desc;
3527 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3529 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3531 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3534 case ETH_SPEED_NUM_10M:
3535 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3536 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3538 case ETH_SPEED_NUM_100M:
3539 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3540 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3542 case ETH_SPEED_NUM_1G:
3543 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3544 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3546 case ETH_SPEED_NUM_10G:
3547 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3548 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3550 case ETH_SPEED_NUM_25G:
3551 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3552 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3554 case ETH_SPEED_NUM_40G:
3555 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3556 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3558 case ETH_SPEED_NUM_50G:
3559 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3560 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3562 case ETH_SPEED_NUM_100G:
3563 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3564 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3566 case ETH_SPEED_NUM_200G:
3567 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3568 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3571 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3575 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3577 ret = hns3_cmd_send(hw, &desc, 1);
3579 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3585 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3587 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3588 struct hns3_pf *pf = &hns->pf;
3589 struct hns3_priv_buf *priv;
3590 uint32_t i, total_size;
3592 total_size = pf->pkt_buf_size;
3594 /* alloc tx buffer for all enabled tc */
3595 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3596 priv = &buf_alloc->priv_buf[i];
3598 if (hw->hw_tc_map & BIT(i)) {
3599 if (total_size < pf->tx_buf_size)
3602 priv->tx_buf_size = pf->tx_buf_size;
3604 priv->tx_buf_size = 0;
3606 total_size -= priv->tx_buf_size;
3613 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3615 /* TX buffer size is unit by 128 byte */
3616 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3617 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3618 struct hns3_tx_buff_alloc_cmd *req;
3619 struct hns3_cmd_desc desc;
3624 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3626 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3627 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3628 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3630 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3631 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3632 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3635 ret = hns3_cmd_send(hw, &desc, 1);
3637 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3643 hns3_get_tc_num(struct hns3_hw *hw)
3648 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3649 if (hw->hw_tc_map & BIT(i))
3655 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3657 struct hns3_priv_buf *priv;
3658 uint32_t rx_priv = 0;
3661 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3662 priv = &buf_alloc->priv_buf[i];
3664 rx_priv += priv->buf_size;
3670 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3672 uint32_t total_tx_size = 0;
3675 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3676 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3678 return total_tx_size;
3681 /* Get the number of pfc enabled TCs, which have private buffer */
3683 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3685 struct hns3_priv_buf *priv;
3689 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3690 priv = &buf_alloc->priv_buf[i];
3691 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3698 /* Get the number of pfc disabled TCs, which have private buffer */
3700 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3701 struct hns3_pkt_buf_alloc *buf_alloc)
3703 struct hns3_priv_buf *priv;
3707 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3708 priv = &buf_alloc->priv_buf[i];
3709 if (hw->hw_tc_map & BIT(i) &&
3710 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3718 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3721 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3722 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3723 struct hns3_pf *pf = &hns->pf;
3724 uint32_t shared_buf, aligned_mps;
3729 tc_num = hns3_get_tc_num(hw);
3730 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3732 if (hns3_dev_dcb_supported(hw))
3733 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3736 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3739 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3740 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3741 HNS3_BUF_SIZE_UNIT);
3743 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3744 if (rx_all < rx_priv + shared_std)
3747 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3748 buf_alloc->s_buf.buf_size = shared_buf;
3749 if (hns3_dev_dcb_supported(hw)) {
3750 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3751 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3752 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3753 HNS3_BUF_SIZE_UNIT);
3755 buf_alloc->s_buf.self.high =
3756 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3757 buf_alloc->s_buf.self.low = aligned_mps;
3760 if (hns3_dev_dcb_supported(hw)) {
3761 hi_thrd = shared_buf - pf->dv_buf_size;
3763 if (tc_num <= NEED_RESERVE_TC_NUM)
3764 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3768 hi_thrd = hi_thrd / tc_num;
3770 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3771 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3772 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3774 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3775 lo_thrd = aligned_mps;
3778 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3779 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3780 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3787 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3788 struct hns3_pkt_buf_alloc *buf_alloc)
3790 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3791 struct hns3_pf *pf = &hns->pf;
3792 struct hns3_priv_buf *priv;
3793 uint32_t aligned_mps;
3797 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3798 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3800 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3801 priv = &buf_alloc->priv_buf[i];
3808 if (!(hw->hw_tc_map & BIT(i)))
3812 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3813 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3814 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3815 HNS3_BUF_SIZE_UNIT);
3818 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3822 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3825 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3829 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3830 struct hns3_pkt_buf_alloc *buf_alloc)
3832 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3833 struct hns3_pf *pf = &hns->pf;
3834 struct hns3_priv_buf *priv;
3835 int no_pfc_priv_num;
3840 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3841 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3843 /* let the last to be cleared first */
3844 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3845 priv = &buf_alloc->priv_buf[i];
3846 mask = BIT((uint8_t)i);
3848 if (hw->hw_tc_map & mask &&
3849 !(hw->dcb_info.hw_pfc_map & mask)) {
3850 /* Clear the no pfc TC private buffer */
3858 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3859 no_pfc_priv_num == 0)
3863 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3867 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3868 struct hns3_pkt_buf_alloc *buf_alloc)
3870 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3871 struct hns3_pf *pf = &hns->pf;
3872 struct hns3_priv_buf *priv;
3878 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3879 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3881 /* let the last to be cleared first */
3882 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3883 priv = &buf_alloc->priv_buf[i];
3884 mask = BIT((uint8_t)i);
3885 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3886 /* Reduce the number of pfc TC with private buffer */
3893 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3898 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3902 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3903 struct hns3_pkt_buf_alloc *buf_alloc)
3905 #define COMPENSATE_BUFFER 0x3C00
3906 #define COMPENSATE_HALF_MPS_NUM 5
3907 #define PRIV_WL_GAP 0x1800
3908 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3909 struct hns3_pf *pf = &hns->pf;
3910 uint32_t tc_num = hns3_get_tc_num(hw);
3911 uint32_t half_mps = pf->mps >> 1;
3912 struct hns3_priv_buf *priv;
3913 uint32_t min_rx_priv;
3917 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3919 rx_priv = rx_priv / tc_num;
3921 if (tc_num <= NEED_RESERVE_TC_NUM)
3922 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3925 * Minimum value of private buffer in rx direction (min_rx_priv) is
3926 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3927 * buffer if rx_priv is greater than min_rx_priv.
3929 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3930 COMPENSATE_HALF_MPS_NUM * half_mps;
3931 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3932 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3934 if (rx_priv < min_rx_priv)
3937 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3938 priv = &buf_alloc->priv_buf[i];
3944 if (!(hw->hw_tc_map & BIT(i)))
3948 priv->buf_size = rx_priv;
3949 priv->wl.high = rx_priv - pf->dv_buf_size;
3950 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3953 buf_alloc->s_buf.buf_size = 0;
3959 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3960 * @hw: pointer to struct hns3_hw
3961 * @buf_alloc: pointer to buffer calculation data
3962 * @return: 0: calculate sucessful, negative: fail
3965 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3967 /* When DCB is not supported, rx private buffer is not allocated. */
3968 if (!hns3_dev_dcb_supported(hw)) {
3969 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3970 struct hns3_pf *pf = &hns->pf;
3971 uint32_t rx_all = pf->pkt_buf_size;
3973 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3974 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3981 * Try to allocate privated packet buffer for all TCs without share
3984 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3988 * Try to allocate privated packet buffer for all TCs with share
3991 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3995 * For different application scenes, the enabled port number, TC number
3996 * and no_drop TC number are different. In order to obtain the better
3997 * performance, software could allocate the buffer size and configure
3998 * the waterline by trying to decrease the private buffer size according
3999 * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
4002 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
4005 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
4008 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
4015 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4017 struct hns3_rx_priv_buff_cmd *req;
4018 struct hns3_cmd_desc desc;
4023 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
4024 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
4026 /* Alloc private buffer TCs */
4027 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4028 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
4031 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
4032 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
4035 buf_size = buf_alloc->s_buf.buf_size;
4036 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
4037 (1 << HNS3_TC0_PRI_BUF_EN_B));
4039 ret = hns3_cmd_send(hw, &desc, 1);
4041 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
4047 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4049 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
4050 struct hns3_rx_priv_wl_buf *req;
4051 struct hns3_priv_buf *priv;
4052 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4056 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4057 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4059 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4061 /* The first descriptor set the NEXT bit to 1 */
4063 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4065 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4067 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4068 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4070 priv = &buf_alloc->priv_buf[idx];
4071 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4073 req->tc_wl[j].high |=
4074 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4075 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4077 req->tc_wl[j].low |=
4078 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4082 /* Send 2 descriptor at one time */
4083 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4085 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4091 hns3_common_thrd_config(struct hns3_hw *hw,
4092 struct hns3_pkt_buf_alloc *buf_alloc)
4094 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4095 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4096 struct hns3_rx_com_thrd *req;
4097 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4098 struct hns3_tc_thrd *tc;
4103 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4104 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4106 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4108 /* The first descriptor set the NEXT bit to 1 */
4110 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4112 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4114 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4115 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4116 tc = &s_buf->tc_thrd[tc_idx];
4118 req->com_thrd[j].high =
4119 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4120 req->com_thrd[j].high |=
4121 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4122 req->com_thrd[j].low =
4123 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4124 req->com_thrd[j].low |=
4125 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4129 /* Send 2 descriptors at one time */
4130 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4132 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4138 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4140 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4141 struct hns3_rx_com_wl *req;
4142 struct hns3_cmd_desc desc;
4145 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4147 req = (struct hns3_rx_com_wl *)desc.data;
4148 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4149 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4151 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4152 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4154 ret = hns3_cmd_send(hw, &desc, 1);
4156 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4162 hns3_buffer_alloc(struct hns3_hw *hw)
4164 struct hns3_pkt_buf_alloc pkt_buf;
4167 memset(&pkt_buf, 0, sizeof(pkt_buf));
4168 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4171 "could not calc tx buffer size for all TCs %d",
4176 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4178 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4182 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4185 "could not calc rx priv buffer size for all TCs %d",
4190 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4192 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4196 if (hns3_dev_dcb_supported(hw)) {
4197 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4200 "could not configure rx private waterline %d",
4205 ret = hns3_common_thrd_config(hw, &pkt_buf);
4208 "could not configure common threshold %d",
4214 ret = hns3_common_wl_config(hw, &pkt_buf);
4216 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4223 hns3_mac_init(struct hns3_hw *hw)
4225 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4226 struct hns3_mac *mac = &hw->mac;
4227 struct hns3_pf *pf = &hns->pf;
4230 pf->support_sfp_query = true;
4231 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4232 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4234 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4238 mac->link_status = ETH_LINK_DOWN;
4240 return hns3_config_mtu(hw, pf->mps);
4244 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4246 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
4247 #define HNS3_ETHERTYPE_ALREADY_ADD 1
4248 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
4249 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
4254 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4259 switch (resp_code) {
4260 case HNS3_ETHERTYPE_SUCCESS_ADD:
4261 case HNS3_ETHERTYPE_ALREADY_ADD:
4264 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4266 "add mac ethertype failed for manager table overflow.");
4267 return_status = -EIO;
4269 case HNS3_ETHERTYPE_KEY_CONFLICT:
4270 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4271 return_status = -EIO;
4275 "add mac ethertype failed for undefined, code=%u.",
4277 return_status = -EIO;
4281 return return_status;
4285 hns3_add_mgr_tbl(struct hns3_hw *hw,
4286 const struct hns3_mac_mgr_tbl_entry_cmd *req)
4288 struct hns3_cmd_desc desc;
4293 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4294 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4296 ret = hns3_cmd_send(hw, &desc, 1);
4299 "add mac ethertype failed for cmd_send, ret =%d.",
4304 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4305 retval = rte_le_to_cpu_16(desc.retval);
4307 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4311 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4312 int *table_item_num)
4314 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4317 * In current version, we add one item in management table as below:
4318 * 0x0180C200000E -- LLDP MC address
4321 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4322 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4323 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4324 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4325 tbl->i_port_bitmap = 0x1;
4326 *table_item_num = 1;
4330 hns3_init_mgr_tbl(struct hns3_hw *hw)
4332 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
4333 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4338 memset(mgr_table, 0, sizeof(mgr_table));
4339 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4340 for (i = 0; i < table_item_num; i++) {
4341 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4343 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4353 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4354 bool en_mc, bool en_bc, int vport_id)
4359 memset(param, 0, sizeof(struct hns3_promisc_param));
4361 param->enable = HNS3_PROMISC_EN_UC;
4363 param->enable |= HNS3_PROMISC_EN_MC;
4365 param->enable |= HNS3_PROMISC_EN_BC;
4366 param->vf_id = vport_id;
4370 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4372 struct hns3_promisc_cfg_cmd *req;
4373 struct hns3_cmd_desc desc;
4376 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4378 req = (struct hns3_promisc_cfg_cmd *)desc.data;
4379 req->vf_id = param->vf_id;
4380 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4381 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4383 ret = hns3_cmd_send(hw, &desc, 1);
4385 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4391 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4393 struct hns3_promisc_param param;
4394 bool en_bc_pmc = true;
4398 * In current version VF is not supported when PF is driven by DPDK
4399 * driver, just need to configure parameters for PF vport.
4401 vf_id = HNS3_PF_FUNC_ID;
4403 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4404 return hns3_cmd_set_promisc_mode(hw, ¶m);
4408 hns3_promisc_init(struct hns3_hw *hw)
4410 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4411 struct hns3_pf *pf = &hns->pf;
4412 struct hns3_promisc_param param;
4416 ret = hns3_set_promisc_mode(hw, false, false);
4418 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4423 * In current version VFs are not supported when PF is driven by DPDK
4424 * driver. After PF has been taken over by DPDK, the original VF will
4425 * be invalid. So, there is a possibility of entry residues. It should
4426 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4429 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4430 hns3_promisc_param_init(¶m, false, false, false, func_id);
4431 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4433 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4434 " ret = %d", func_id, ret);
4443 hns3_promisc_uninit(struct hns3_hw *hw)
4445 struct hns3_promisc_param param;
4449 func_id = HNS3_PF_FUNC_ID;
4452 * In current version VFs are not supported when PF is driven by
4453 * DPDK driver, and VFs' promisc mode status has been cleared during
4454 * init and their status will not change. So just clear PF's promisc
4455 * mode status during uninit.
4457 hns3_promisc_param_init(¶m, false, false, false, func_id);
4458 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4460 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4461 " uninit, ret = %d", ret);
4465 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4467 bool allmulti = dev->data->all_multicast ? true : false;
4468 struct hns3_adapter *hns = dev->data->dev_private;
4469 struct hns3_hw *hw = &hns->hw;
4474 rte_spinlock_lock(&hw->lock);
4475 ret = hns3_set_promisc_mode(hw, true, true);
4477 rte_spinlock_unlock(&hw->lock);
4478 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4484 * When promiscuous mode was enabled, disable the vlan filter to let
4485 * all packets coming in in the receiving direction.
4487 offloads = dev->data->dev_conf.rxmode.offloads;
4488 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4489 ret = hns3_enable_vlan_filter(hns, false);
4491 hns3_err(hw, "failed to enable promiscuous mode due to "
4492 "failure to disable vlan filter, ret = %d",
4494 err = hns3_set_promisc_mode(hw, false, allmulti);
4496 hns3_err(hw, "failed to restore promiscuous "
4497 "status after disable vlan filter "
4498 "failed during enabling promiscuous "
4499 "mode, ret = %d", ret);
4503 rte_spinlock_unlock(&hw->lock);
4509 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4511 bool allmulti = dev->data->all_multicast ? true : false;
4512 struct hns3_adapter *hns = dev->data->dev_private;
4513 struct hns3_hw *hw = &hns->hw;
4518 /* If now in all_multicast mode, must remain in all_multicast mode. */
4519 rte_spinlock_lock(&hw->lock);
4520 ret = hns3_set_promisc_mode(hw, false, allmulti);
4522 rte_spinlock_unlock(&hw->lock);
4523 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4527 /* when promiscuous mode was disabled, restore the vlan filter status */
4528 offloads = dev->data->dev_conf.rxmode.offloads;
4529 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4530 ret = hns3_enable_vlan_filter(hns, true);
4532 hns3_err(hw, "failed to disable promiscuous mode due to"
4533 " failure to restore vlan filter, ret = %d",
4535 err = hns3_set_promisc_mode(hw, true, true);
4537 hns3_err(hw, "failed to restore promiscuous "
4538 "status after enabling vlan filter "
4539 "failed during disabling promiscuous "
4540 "mode, ret = %d", ret);
4543 rte_spinlock_unlock(&hw->lock);
4549 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4551 struct hns3_adapter *hns = dev->data->dev_private;
4552 struct hns3_hw *hw = &hns->hw;
4555 if (dev->data->promiscuous)
4558 rte_spinlock_lock(&hw->lock);
4559 ret = hns3_set_promisc_mode(hw, false, true);
4560 rte_spinlock_unlock(&hw->lock);
4562 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4569 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4571 struct hns3_adapter *hns = dev->data->dev_private;
4572 struct hns3_hw *hw = &hns->hw;
4575 /* If now in promiscuous mode, must remain in all_multicast mode. */
4576 if (dev->data->promiscuous)
4579 rte_spinlock_lock(&hw->lock);
4580 ret = hns3_set_promisc_mode(hw, false, false);
4581 rte_spinlock_unlock(&hw->lock);
4583 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4590 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4592 struct hns3_hw *hw = &hns->hw;
4593 bool allmulti = hw->data->all_multicast ? true : false;
4596 if (hw->data->promiscuous) {
4597 ret = hns3_set_promisc_mode(hw, true, true);
4599 hns3_err(hw, "failed to restore promiscuous mode, "
4604 ret = hns3_set_promisc_mode(hw, false, allmulti);
4606 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4612 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4614 struct hns3_sfp_info_cmd *resp;
4615 struct hns3_cmd_desc desc;
4618 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4619 resp = (struct hns3_sfp_info_cmd *)desc.data;
4620 resp->query_type = HNS3_ACTIVE_QUERY;
4622 ret = hns3_cmd_send(hw, &desc, 1);
4623 if (ret == -EOPNOTSUPP) {
4624 hns3_warn(hw, "firmware does not support get SFP info,"
4628 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4633 * In some case, the speed of MAC obtained from firmware may be 0, it
4634 * shouldn't be set to mac->speed.
4636 if (!rte_le_to_cpu_32(resp->sfp_speed))
4639 mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4641 * if resp->supported_speed is 0, it means it's an old version
4642 * firmware, do not update these params.
4644 if (resp->supported_speed) {
4645 mac_info->query_type = HNS3_ACTIVE_QUERY;
4646 mac_info->supported_speed =
4647 rte_le_to_cpu_32(resp->supported_speed);
4648 mac_info->support_autoneg = resp->autoneg_ability;
4649 mac_info->link_autoneg = (resp->autoneg == 0) ? ETH_LINK_FIXED
4652 mac_info->query_type = HNS3_DEFAULT_QUERY;
4659 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4661 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4662 duplex = ETH_LINK_FULL_DUPLEX;
4668 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4670 struct hns3_mac *mac = &hw->mac;
4673 duplex = hns3_check_speed_dup(duplex, speed);
4674 if (mac->link_speed == speed && mac->link_duplex == duplex)
4677 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4681 ret = hns3_port_shaper_update(hw, speed);
4685 mac->link_speed = speed;
4686 mac->link_duplex = duplex;
4692 hns3_update_fiber_link_info(struct hns3_hw *hw)
4694 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4695 struct hns3_mac *mac = &hw->mac;
4696 struct hns3_mac mac_info;
4699 /* If firmware do not support get SFP/qSFP speed, return directly */
4700 if (!pf->support_sfp_query)
4703 memset(&mac_info, 0, sizeof(struct hns3_mac));
4704 ret = hns3_get_sfp_info(hw, &mac_info);
4705 if (ret == -EOPNOTSUPP) {
4706 pf->support_sfp_query = false;
4711 /* Do nothing if no SFP */
4712 if (mac_info.link_speed == ETH_SPEED_NUM_NONE)
4716 * If query_type is HNS3_ACTIVE_QUERY, it is no need
4717 * to reconfigure the speed of MAC. Otherwise, it indicates
4718 * that the current firmware only supports to obtain the
4719 * speed of the SFP, and the speed of MAC needs to reconfigure.
4721 mac->query_type = mac_info.query_type;
4722 if (mac->query_type == HNS3_ACTIVE_QUERY) {
4723 if (mac_info.link_speed != mac->link_speed) {
4724 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4729 mac->link_speed = mac_info.link_speed;
4730 mac->supported_speed = mac_info.supported_speed;
4731 mac->support_autoneg = mac_info.support_autoneg;
4732 mac->link_autoneg = mac_info.link_autoneg;
4737 /* Config full duplex for SFP */
4738 return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4739 ETH_LINK_FULL_DUPLEX);
4743 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4745 #define HNS3_PHY_SUPPORTED_SPEED_MASK 0x2f
4747 struct hns3_phy_params_bd0_cmd *req;
4750 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4751 mac->link_speed = rte_le_to_cpu_32(req->speed);
4752 mac->link_duplex = hns3_get_bit(req->duplex,
4753 HNS3_PHY_DUPLEX_CFG_B);
4754 mac->link_autoneg = hns3_get_bit(req->autoneg,
4755 HNS3_PHY_AUTONEG_CFG_B);
4756 mac->advertising = rte_le_to_cpu_32(req->advertising);
4757 mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4758 supported = rte_le_to_cpu_32(req->supported);
4759 mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4760 mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4764 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4766 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4770 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4771 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4773 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4775 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4777 ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4779 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4783 hns3_parse_copper_phy_params(desc, mac);
4789 hns3_update_copper_link_info(struct hns3_hw *hw)
4791 struct hns3_mac *mac = &hw->mac;
4792 struct hns3_mac mac_info;
4795 memset(&mac_info, 0, sizeof(struct hns3_mac));
4796 ret = hns3_get_copper_phy_params(hw, &mac_info);
4800 if (mac_info.link_speed != mac->link_speed) {
4801 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4806 mac->link_speed = mac_info.link_speed;
4807 mac->link_duplex = mac_info.link_duplex;
4808 mac->link_autoneg = mac_info.link_autoneg;
4809 mac->supported_speed = mac_info.supported_speed;
4810 mac->advertising = mac_info.advertising;
4811 mac->lp_advertising = mac_info.lp_advertising;
4812 mac->support_autoneg = mac_info.support_autoneg;
4818 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4820 struct hns3_adapter *hns = eth_dev->data->dev_private;
4821 struct hns3_hw *hw = &hns->hw;
4824 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4825 ret = hns3_update_copper_link_info(hw);
4826 else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4827 ret = hns3_update_fiber_link_info(hw);
4833 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4835 struct hns3_config_mac_mode_cmd *req;
4836 struct hns3_cmd_desc desc;
4837 uint32_t loop_en = 0;
4841 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4843 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4846 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4847 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4848 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4849 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4850 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4851 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4852 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4853 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4854 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4855 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4858 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4859 * when receiving frames. Otherwise, CRC will be stripped.
4861 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4862 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4864 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4865 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4866 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4867 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4868 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4870 ret = hns3_cmd_send(hw, &desc, 1);
4872 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4878 hns3_get_mac_link_status(struct hns3_hw *hw)
4880 struct hns3_link_status_cmd *req;
4881 struct hns3_cmd_desc desc;
4885 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4886 ret = hns3_cmd_send(hw, &desc, 1);
4888 hns3_err(hw, "get link status cmd failed %d", ret);
4889 return ETH_LINK_DOWN;
4892 req = (struct hns3_link_status_cmd *)desc.data;
4893 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4895 return !!link_status;
4899 hns3_update_link_status(struct hns3_hw *hw)
4903 state = hns3_get_mac_link_status(hw);
4904 if (state != hw->mac.link_status) {
4905 hw->mac.link_status = state;
4906 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4914 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4916 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4917 struct rte_eth_link new_link;
4921 hns3_update_port_link_info(dev);
4923 memset(&new_link, 0, sizeof(new_link));
4924 hns3_setup_linkstatus(dev, &new_link);
4926 ret = rte_eth_linkstatus_set(dev, &new_link);
4927 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4928 hns3_start_report_lse(dev);
4932 hns3_service_handler(void *param)
4934 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4935 struct hns3_adapter *hns = eth_dev->data->dev_private;
4936 struct hns3_hw *hw = &hns->hw;
4938 if (!hns3_is_reset_pending(hns))
4939 hns3_update_linkstatus_and_event(hw, true);
4941 hns3_warn(hw, "Cancel the query when reset is pending");
4943 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4947 hns3_init_hardware(struct hns3_adapter *hns)
4949 struct hns3_hw *hw = &hns->hw;
4952 ret = hns3_map_tqp(hw);
4954 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4958 ret = hns3_init_umv_space(hw);
4960 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4964 ret = hns3_mac_init(hw);
4966 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4970 ret = hns3_init_mgr_tbl(hw);
4972 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4976 ret = hns3_promisc_init(hw);
4978 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4983 ret = hns3_init_vlan_config(hns);
4985 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4989 ret = hns3_dcb_init(hw);
4991 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4995 ret = hns3_init_fd_config(hns);
4997 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
5001 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
5003 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
5007 ret = hns3_config_gro(hw, false);
5009 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
5014 * In the initialization clearing the all hardware mapping relationship
5015 * configurations between queues and interrupt vectors is needed, so
5016 * some error caused by the residual configurations, such as the
5017 * unexpected interrupt, can be avoid.
5019 ret = hns3_init_ring_with_vector(hw);
5021 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
5028 hns3_uninit_umv_space(hw);
5033 hns3_clear_hw(struct hns3_hw *hw)
5035 struct hns3_cmd_desc desc;
5038 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
5040 ret = hns3_cmd_send(hw, &desc, 1);
5041 if (ret && ret != -EOPNOTSUPP)
5048 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
5053 * The new firmware support report more hardware error types by
5054 * msix mode. These errors are defined as RAS errors in hardware
5055 * and belong to a different type from the MSI-x errors processed
5056 * by the network driver.
5058 * Network driver should open the new error report on initialization.
5060 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5061 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5062 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5066 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5068 struct hns3_mac *mac = &hw->mac;
5070 switch (mac->link_speed) {
5071 case ETH_SPEED_NUM_1G:
5072 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5073 case ETH_SPEED_NUM_10G:
5074 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5075 case ETH_SPEED_NUM_25G:
5076 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5077 case ETH_SPEED_NUM_40G:
5078 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5079 case ETH_SPEED_NUM_50G:
5080 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5081 case ETH_SPEED_NUM_100G:
5082 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5083 case ETH_SPEED_NUM_200G:
5084 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5086 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5092 * Validity of supported_speed for firber and copper media type can be
5093 * guaranteed by the following policy:
5095 * Although the initialization of the phy in the firmware may not be
5096 * completed, the firmware can guarantees that the supported_speed is
5099 * If the version of firmware supports the acitive query way of the
5100 * HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5101 * through it. If unsupported, use the SFP's speed as the value of the
5105 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5107 struct hns3_adapter *hns = eth_dev->data->dev_private;
5108 struct hns3_hw *hw = &hns->hw;
5109 struct hns3_mac *mac = &hw->mac;
5112 ret = hns3_update_link_info(eth_dev);
5116 if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5118 * Some firmware does not support the report of supported_speed,
5119 * and only report the effective speed of SFP. In this case, it
5120 * is necessary to use the SFP's speed as the supported_speed.
5122 if (mac->supported_speed == 0)
5123 mac->supported_speed =
5124 hns3_set_firber_default_support_speed(hw);
5131 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
5133 struct hns3_mac *mac = &hns->hw.mac;
5135 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
5136 hns->pf.support_fc_autoneg = true;
5141 * Flow control auto-negotiation requires the cooperation of the driver
5142 * and firmware. Currently, the optical port does not support flow
5143 * control auto-negotiation.
5145 hns->pf.support_fc_autoneg = false;
5149 hns3_init_pf(struct rte_eth_dev *eth_dev)
5151 struct rte_device *dev = eth_dev->device;
5152 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5153 struct hns3_adapter *hns = eth_dev->data->dev_private;
5154 struct hns3_hw *hw = &hns->hw;
5157 PMD_INIT_FUNC_TRACE();
5159 /* Get hardware io base address from pcie BAR2 IO space */
5160 hw->io_base = pci_dev->mem_resource[2].addr;
5162 /* Firmware command queue initialize */
5163 ret = hns3_cmd_init_queue(hw);
5165 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5166 goto err_cmd_init_queue;
5169 hns3_clear_all_event_cause(hw);
5171 /* Firmware command initialize */
5172 ret = hns3_cmd_init(hw);
5174 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5179 * To ensure that the hardware environment is clean during
5180 * initialization, the driver actively clear the hardware environment
5181 * during initialization, including PF and corresponding VFs' vlan, mac,
5182 * flow table configurations, etc.
5184 ret = hns3_clear_hw(hw);
5186 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5190 /* Hardware statistics of imissed registers cleared. */
5191 ret = hns3_update_imissed_stats(hw, true);
5193 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5197 hns3_config_all_msix_error(hw, true);
5199 ret = rte_intr_callback_register(&pci_dev->intr_handle,
5200 hns3_interrupt_handler,
5203 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5204 goto err_intr_callback_register;
5207 ret = hns3_ptp_init(hw);
5209 goto err_get_config;
5211 /* Enable interrupt */
5212 rte_intr_enable(&pci_dev->intr_handle);
5213 hns3_pf_enable_irq0(hw);
5215 /* Get configuration */
5216 ret = hns3_get_configuration(hw);
5218 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5219 goto err_get_config;
5222 ret = hns3_tqp_stats_init(hw);
5224 goto err_get_config;
5226 ret = hns3_init_hardware(hns);
5228 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5232 /* Initialize flow director filter list & hash */
5233 ret = hns3_fdir_filter_init(hns);
5235 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5239 hns3_rss_set_default_args(hw);
5241 ret = hns3_enable_hw_error_intr(hns, true);
5243 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5245 goto err_enable_intr;
5248 ret = hns3_get_port_supported_speed(eth_dev);
5250 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5251 "by device, ret = %d.", ret);
5252 goto err_supported_speed;
5255 hns3_get_fc_autoneg_capability(hns);
5257 hns3_tm_conf_init(eth_dev);
5261 err_supported_speed:
5262 (void)hns3_enable_hw_error_intr(hns, false);
5264 hns3_fdir_filter_uninit(hns);
5266 hns3_uninit_umv_space(hw);
5268 hns3_tqp_stats_uninit(hw);
5270 hns3_pf_disable_irq0(hw);
5271 rte_intr_disable(&pci_dev->intr_handle);
5272 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5274 err_intr_callback_register:
5276 hns3_cmd_uninit(hw);
5277 hns3_cmd_destroy_queue(hw);
5285 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5287 struct hns3_adapter *hns = eth_dev->data->dev_private;
5288 struct rte_device *dev = eth_dev->device;
5289 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5290 struct hns3_hw *hw = &hns->hw;
5292 PMD_INIT_FUNC_TRACE();
5294 hns3_tm_conf_uninit(eth_dev);
5295 hns3_enable_hw_error_intr(hns, false);
5296 hns3_rss_uninit(hns);
5297 (void)hns3_config_gro(hw, false);
5298 hns3_promisc_uninit(hw);
5299 hns3_fdir_filter_uninit(hns);
5300 hns3_uninit_umv_space(hw);
5301 hns3_tqp_stats_uninit(hw);
5302 hns3_config_mac_tnl_int(hw, false);
5303 hns3_pf_disable_irq0(hw);
5304 rte_intr_disable(&pci_dev->intr_handle);
5305 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5307 hns3_config_all_msix_error(hw, false);
5308 hns3_cmd_uninit(hw);
5309 hns3_cmd_destroy_queue(hw);
5314 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
5318 switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5319 case ETH_LINK_SPEED_10M:
5320 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
5322 case ETH_LINK_SPEED_10M_HD:
5323 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
5325 case ETH_LINK_SPEED_100M:
5326 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
5328 case ETH_LINK_SPEED_100M_HD:
5329 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
5331 case ETH_LINK_SPEED_1G:
5332 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
5343 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
5347 switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5348 case ETH_LINK_SPEED_1G:
5349 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
5351 case ETH_LINK_SPEED_10G:
5352 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
5354 case ETH_LINK_SPEED_25G:
5355 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
5357 case ETH_LINK_SPEED_40G:
5358 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
5360 case ETH_LINK_SPEED_50G:
5361 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
5363 case ETH_LINK_SPEED_100G:
5364 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
5366 case ETH_LINK_SPEED_200G:
5367 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
5378 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
5380 struct hns3_mac *mac = &hw->mac;
5381 uint32_t supported_speed = mac->supported_speed;
5382 uint32_t speed_bit = 0;
5384 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
5385 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
5386 else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
5387 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
5389 if (!(speed_bit & supported_speed)) {
5390 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
5398 static inline uint32_t
5399 hns3_get_link_speed(uint32_t link_speeds)
5401 uint32_t speed = ETH_SPEED_NUM_NONE;
5403 if (link_speeds & ETH_LINK_SPEED_10M ||
5404 link_speeds & ETH_LINK_SPEED_10M_HD)
5405 speed = ETH_SPEED_NUM_10M;
5406 if (link_speeds & ETH_LINK_SPEED_100M ||
5407 link_speeds & ETH_LINK_SPEED_100M_HD)
5408 speed = ETH_SPEED_NUM_100M;
5409 if (link_speeds & ETH_LINK_SPEED_1G)
5410 speed = ETH_SPEED_NUM_1G;
5411 if (link_speeds & ETH_LINK_SPEED_10G)
5412 speed = ETH_SPEED_NUM_10G;
5413 if (link_speeds & ETH_LINK_SPEED_25G)
5414 speed = ETH_SPEED_NUM_25G;
5415 if (link_speeds & ETH_LINK_SPEED_40G)
5416 speed = ETH_SPEED_NUM_40G;
5417 if (link_speeds & ETH_LINK_SPEED_50G)
5418 speed = ETH_SPEED_NUM_50G;
5419 if (link_speeds & ETH_LINK_SPEED_100G)
5420 speed = ETH_SPEED_NUM_100G;
5421 if (link_speeds & ETH_LINK_SPEED_200G)
5422 speed = ETH_SPEED_NUM_200G;
5428 hns3_get_link_duplex(uint32_t link_speeds)
5430 if ((link_speeds & ETH_LINK_SPEED_10M_HD) ||
5431 (link_speeds & ETH_LINK_SPEED_100M_HD))
5432 return ETH_LINK_HALF_DUPLEX;
5434 return ETH_LINK_FULL_DUPLEX;
5438 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5439 struct hns3_set_link_speed_cfg *cfg)
5441 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5442 struct hns3_phy_params_bd0_cmd *req;
5445 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5446 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5448 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5450 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5451 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5452 req->autoneg = cfg->autoneg;
5455 * The full speed capability is used to negotiate when
5456 * auto-negotiation is enabled.
5459 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5460 HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5461 HNS3_PHY_LINK_SPEED_100M_BIT |
5462 HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5463 HNS3_PHY_LINK_SPEED_1000M_BIT;
5465 req->speed = cfg->speed;
5466 req->duplex = cfg->duplex;
5469 return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5473 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5475 struct hns3_config_auto_neg_cmd *req;
5476 struct hns3_cmd_desc desc;
5480 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5482 req = (struct hns3_config_auto_neg_cmd *)desc.data;
5484 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5485 req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5487 ret = hns3_cmd_send(hw, &desc, 1);
5489 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5495 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5496 struct hns3_set_link_speed_cfg *cfg)
5500 if (hw->mac.support_autoneg) {
5501 ret = hns3_set_autoneg(hw, cfg->autoneg);
5503 hns3_err(hw, "failed to configure auto-negotiation.");
5508 * To enable auto-negotiation, we only need to open the switch
5509 * of auto-negotiation, then firmware sets all speed
5517 * Some hardware doesn't support auto-negotiation, but users may not
5518 * configure link_speeds (default 0), which means auto-negotiation.
5519 * In this case, it should return success.
5524 return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
5528 hns3_set_port_link_speed(struct hns3_hw *hw,
5529 struct hns3_set_link_speed_cfg *cfg)
5533 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5534 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5535 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5540 ret = hns3_set_copper_port_link_speed(hw, cfg);
5542 hns3_err(hw, "failed to set copper port link speed,"
5546 } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5547 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5549 hns3_err(hw, "failed to set fiber port link speed,"
5559 hns3_apply_link_speed(struct hns3_hw *hw)
5561 struct rte_eth_conf *conf = &hw->data->dev_conf;
5562 struct hns3_set_link_speed_cfg cfg;
5564 memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5565 cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ?
5566 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
5567 if (cfg.autoneg != ETH_LINK_AUTONEG) {
5568 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5569 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5572 return hns3_set_port_link_speed(hw, &cfg);
5576 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5578 struct hns3_hw *hw = &hns->hw;
5581 ret = hns3_dcb_cfg_update(hns);
5586 * The hns3_dcb_cfg_update may configure TM module, so
5587 * hns3_tm_conf_update must called later.
5589 ret = hns3_tm_conf_update(hw);
5591 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5595 hns3_enable_rxd_adv_layout(hw);
5597 ret = hns3_init_queues(hns, reset_queue);
5599 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5603 ret = hns3_cfg_mac_mode(hw, true);
5605 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5606 goto err_config_mac_mode;
5609 ret = hns3_apply_link_speed(hw);
5611 goto err_set_link_speed;
5616 (void)hns3_cfg_mac_mode(hw, false);
5618 err_config_mac_mode:
5619 hns3_dev_release_mbufs(hns);
5621 * Here is exception handling, hns3_reset_all_tqps will have the
5622 * corresponding error message if it is handled incorrectly, so it is
5623 * not necessary to check hns3_reset_all_tqps return value, here keep
5624 * ret as the error code causing the exception.
5626 (void)hns3_reset_all_tqps(hns);
5631 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5633 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5634 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5635 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5636 uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5637 uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5638 uint32_t intr_vector;
5643 * hns3 needs a separate interrupt to be used as event interrupt which
5644 * could not be shared with task queue pair, so KERNEL drivers need
5645 * support multiple interrupt vectors.
5647 if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5648 !rte_intr_cap_multiple(intr_handle))
5651 rte_intr_disable(intr_handle);
5652 intr_vector = hw->used_rx_queues;
5653 /* creates event fd for each intr vector when MSIX is used */
5654 if (rte_intr_efd_enable(intr_handle, intr_vector))
5657 if (intr_handle->intr_vec == NULL) {
5658 intr_handle->intr_vec =
5659 rte_zmalloc("intr_vec",
5660 hw->used_rx_queues * sizeof(int), 0);
5661 if (intr_handle->intr_vec == NULL) {
5662 hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5663 hw->used_rx_queues);
5665 goto alloc_intr_vec_error;
5669 if (rte_intr_allow_others(intr_handle)) {
5670 vec = RTE_INTR_VEC_RXTX_OFFSET;
5671 base = RTE_INTR_VEC_RXTX_OFFSET;
5674 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5675 ret = hns3_bind_ring_with_vector(hw, vec, true,
5676 HNS3_RING_TYPE_RX, q_id);
5678 goto bind_vector_error;
5679 intr_handle->intr_vec[q_id] = vec;
5681 * If there are not enough efds (e.g. not enough interrupt),
5682 * remaining queues will be bond to the last interrupt.
5684 if (vec < base + intr_handle->nb_efd - 1)
5687 rte_intr_enable(intr_handle);
5691 rte_free(intr_handle->intr_vec);
5692 intr_handle->intr_vec = NULL;
5693 alloc_intr_vec_error:
5694 rte_intr_efd_disable(intr_handle);
5699 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5701 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5702 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5703 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5707 if (dev->data->dev_conf.intr_conf.rxq == 0)
5710 if (rte_intr_dp_is_en(intr_handle)) {
5711 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5712 ret = hns3_bind_ring_with_vector(hw,
5713 intr_handle->intr_vec[q_id], true,
5714 HNS3_RING_TYPE_RX, q_id);
5724 hns3_restore_filter(struct rte_eth_dev *dev)
5726 hns3_restore_rss_filter(dev);
5730 hns3_dev_start(struct rte_eth_dev *dev)
5732 struct hns3_adapter *hns = dev->data->dev_private;
5733 struct hns3_hw *hw = &hns->hw;
5736 PMD_INIT_FUNC_TRACE();
5737 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5740 rte_spinlock_lock(&hw->lock);
5741 hw->adapter_state = HNS3_NIC_STARTING;
5743 ret = hns3_do_start(hns, true);
5745 hw->adapter_state = HNS3_NIC_CONFIGURED;
5746 rte_spinlock_unlock(&hw->lock);
5749 ret = hns3_map_rx_interrupt(dev);
5751 goto map_rx_inter_err;
5754 * There are three register used to control the status of a TQP
5755 * (contains a pair of Tx queue and Rx queue) in the new version network
5756 * engine. One is used to control the enabling of Tx queue, the other is
5757 * used to control the enabling of Rx queue, and the last is the master
5758 * switch used to control the enabling of the tqp. The Tx register and
5759 * TQP register must be enabled at the same time to enable a Tx queue.
5760 * The same applies to the Rx queue. For the older network engine, this
5761 * function only refresh the enabled flag, and it is used to update the
5762 * status of queue in the dpdk framework.
5764 ret = hns3_start_all_txqs(dev);
5766 goto map_rx_inter_err;
5768 ret = hns3_start_all_rxqs(dev);
5770 goto start_all_rxqs_fail;
5772 hw->adapter_state = HNS3_NIC_STARTED;
5773 rte_spinlock_unlock(&hw->lock);
5775 hns3_rx_scattered_calc(dev);
5776 hns3_set_rxtx_function(dev);
5777 hns3_mp_req_start_rxtx(dev);
5779 hns3_restore_filter(dev);
5781 /* Enable interrupt of all rx queues before enabling queues */
5782 hns3_dev_all_rx_queue_intr_enable(hw, true);
5785 * After finished the initialization, enable tqps to receive/transmit
5786 * packets and refresh all queue status.
5788 hns3_start_tqps(hw);
5790 hns3_tm_dev_start_proc(hw);
5792 if (dev->data->dev_conf.intr_conf.lsc != 0)
5793 hns3_dev_link_update(dev, 0);
5794 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5796 hns3_info(hw, "hns3 dev start successful!");
5800 start_all_rxqs_fail:
5801 hns3_stop_all_txqs(dev);
5803 (void)hns3_do_stop(hns);
5804 hw->adapter_state = HNS3_NIC_CONFIGURED;
5805 rte_spinlock_unlock(&hw->lock);
5811 hns3_do_stop(struct hns3_adapter *hns)
5813 struct hns3_hw *hw = &hns->hw;
5817 * The "hns3_do_stop" function will also be called by .stop_service to
5818 * prepare reset. At the time of global or IMP reset, the command cannot
5819 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5820 * accessed during the reset process. So the mbuf can not be released
5821 * during reset and is required to be released after the reset is
5824 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)
5825 hns3_dev_release_mbufs(hns);
5827 ret = hns3_cfg_mac_mode(hw, false);
5830 hw->mac.link_status = ETH_LINK_DOWN;
5832 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5833 hns3_configure_all_mac_addr(hns, true);
5834 ret = hns3_reset_all_tqps(hns);
5836 hns3_err(hw, "failed to reset all queues ret = %d.",
5841 hw->mac.default_addr_setted = false;
5846 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5848 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5849 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5850 struct hns3_adapter *hns = dev->data->dev_private;
5851 struct hns3_hw *hw = &hns->hw;
5852 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5853 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5856 if (dev->data->dev_conf.intr_conf.rxq == 0)
5859 /* unmap the ring with vector */
5860 if (rte_intr_allow_others(intr_handle)) {
5861 vec = RTE_INTR_VEC_RXTX_OFFSET;
5862 base = RTE_INTR_VEC_RXTX_OFFSET;
5864 if (rte_intr_dp_is_en(intr_handle)) {
5865 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5866 (void)hns3_bind_ring_with_vector(hw, vec, false,
5869 if (vec < base + intr_handle->nb_efd - 1)
5873 /* Clean datapath event and queue/vec mapping */
5874 rte_intr_efd_disable(intr_handle);
5875 if (intr_handle->intr_vec) {
5876 rte_free(intr_handle->intr_vec);
5877 intr_handle->intr_vec = NULL;
5882 hns3_dev_stop(struct rte_eth_dev *dev)
5884 struct hns3_adapter *hns = dev->data->dev_private;
5885 struct hns3_hw *hw = &hns->hw;
5887 PMD_INIT_FUNC_TRACE();
5888 dev->data->dev_started = 0;
5890 hw->adapter_state = HNS3_NIC_STOPPING;
5891 hns3_set_rxtx_function(dev);
5893 /* Disable datapath on secondary process. */
5894 hns3_mp_req_stop_rxtx(dev);
5895 /* Prevent crashes when queues are still in use. */
5896 rte_delay_ms(hw->tqps_num);
5898 rte_spinlock_lock(&hw->lock);
5899 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5900 hns3_tm_dev_stop_proc(hw);
5901 hns3_config_mac_tnl_int(hw, false);
5904 hns3_unmap_rx_interrupt(dev);
5905 hw->adapter_state = HNS3_NIC_CONFIGURED;
5907 hns3_rx_scattered_reset(dev);
5908 rte_eal_alarm_cancel(hns3_service_handler, dev);
5909 hns3_stop_report_lse(dev);
5910 rte_spinlock_unlock(&hw->lock);
5916 hns3_dev_close(struct rte_eth_dev *eth_dev)
5918 struct hns3_adapter *hns = eth_dev->data->dev_private;
5919 struct hns3_hw *hw = &hns->hw;
5922 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5923 rte_free(eth_dev->process_private);
5924 eth_dev->process_private = NULL;
5928 if (hw->adapter_state == HNS3_NIC_STARTED)
5929 ret = hns3_dev_stop(eth_dev);
5931 hw->adapter_state = HNS3_NIC_CLOSING;
5932 hns3_reset_abort(hns);
5933 hw->adapter_state = HNS3_NIC_CLOSED;
5935 hns3_configure_all_mc_mac_addr(hns, true);
5936 hns3_remove_all_vlan_table(hns);
5937 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5938 hns3_uninit_pf(eth_dev);
5939 hns3_free_all_queues(eth_dev);
5940 rte_free(hw->reset.wait_data);
5941 rte_free(eth_dev->process_private);
5942 eth_dev->process_private = NULL;
5943 hns3_mp_uninit_primary();
5944 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5950 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5953 struct hns3_mac *mac = &hw->mac;
5954 uint32_t advertising = mac->advertising;
5955 uint32_t lp_advertising = mac->lp_advertising;
5959 if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5962 } else if (advertising & lp_advertising &
5963 HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5964 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5966 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5971 static enum hns3_fc_mode
5972 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5974 enum hns3_fc_mode current_mode;
5975 bool rx_pause = false;
5976 bool tx_pause = false;
5978 switch (hw->mac.media_type) {
5979 case HNS3_MEDIA_TYPE_COPPER:
5980 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5984 * Flow control auto-negotiation is not supported for fiber and
5985 * backpalne media type.
5987 case HNS3_MEDIA_TYPE_FIBER:
5988 case HNS3_MEDIA_TYPE_BACKPLANE:
5989 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
5990 current_mode = hw->requested_fc_mode;
5993 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
5994 hw->mac.media_type);
5995 current_mode = HNS3_FC_NONE;
5999 if (rx_pause && tx_pause)
6000 current_mode = HNS3_FC_FULL;
6002 current_mode = HNS3_FC_RX_PAUSE;
6004 current_mode = HNS3_FC_TX_PAUSE;
6006 current_mode = HNS3_FC_NONE;
6009 return current_mode;
6012 static enum hns3_fc_mode
6013 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
6015 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6016 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6017 struct hns3_mac *mac = &hw->mac;
6020 * When the flow control mode is obtained, the device may not complete
6021 * auto-negotiation. It is necessary to wait for link establishment.
6023 (void)hns3_dev_link_update(dev, 1);
6026 * If the link auto-negotiation of the nic is disabled, or the flow
6027 * control auto-negotiation is not supported, the forced flow control
6030 if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
6031 return hw->requested_fc_mode;
6033 return hns3_get_autoneg_fc_mode(hw);
6037 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6039 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6040 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6041 enum hns3_fc_mode current_mode;
6043 current_mode = hns3_get_current_fc_mode(dev);
6044 switch (current_mode) {
6046 fc_conf->mode = RTE_FC_FULL;
6048 case HNS3_FC_TX_PAUSE:
6049 fc_conf->mode = RTE_FC_TX_PAUSE;
6051 case HNS3_FC_RX_PAUSE:
6052 fc_conf->mode = RTE_FC_RX_PAUSE;
6056 fc_conf->mode = RTE_FC_NONE;
6060 fc_conf->pause_time = pf->pause_time;
6061 fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
6067 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
6071 hw->requested_fc_mode = HNS3_FC_NONE;
6073 case RTE_FC_RX_PAUSE:
6074 hw->requested_fc_mode = HNS3_FC_RX_PAUSE;
6076 case RTE_FC_TX_PAUSE:
6077 hw->requested_fc_mode = HNS3_FC_TX_PAUSE;
6080 hw->requested_fc_mode = HNS3_FC_FULL;
6083 hw->requested_fc_mode = HNS3_FC_NONE;
6084 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
6085 "configured to RTE_FC_NONE", mode);
6091 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
6093 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
6095 if (!pf->support_fc_autoneg) {
6097 hns3_err(hw, "unsupported fc auto-negotiation setting.");
6102 * Flow control auto-negotiation of the NIC is not supported,
6103 * but other auto-negotiation features may be supported.
6105 if (autoneg != hw->mac.link_autoneg) {
6106 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
6114 * If flow control auto-negotiation of the NIC is supported, all
6115 * auto-negotiation features are supported.
6117 if (autoneg != hw->mac.link_autoneg) {
6118 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
6126 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6128 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6131 if (fc_conf->high_water || fc_conf->low_water ||
6132 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
6133 hns3_err(hw, "Unsupported flow control settings specified, "
6134 "high_water(%u), low_water(%u), send_xon(%u) and "
6135 "mac_ctrl_frame_fwd(%u) must be set to '0'",
6136 fc_conf->high_water, fc_conf->low_water,
6137 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
6141 ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
6145 if (!fc_conf->pause_time) {
6146 hns3_err(hw, "Invalid pause time %u setting.",
6147 fc_conf->pause_time);
6151 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6152 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
6153 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
6154 "current_fc_status = %d", hw->current_fc_status);
6158 if (hw->num_tc > 1) {
6159 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
6163 hns3_get_fc_mode(hw, fc_conf->mode);
6165 rte_spinlock_lock(&hw->lock);
6166 ret = hns3_fc_enable(dev, fc_conf);
6167 rte_spinlock_unlock(&hw->lock);
6173 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
6174 struct rte_eth_pfc_conf *pfc_conf)
6176 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6179 if (!hns3_dev_dcb_supported(hw)) {
6180 hns3_err(hw, "This port does not support dcb configurations.");
6184 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
6185 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
6186 hns3_err(hw, "Unsupported flow control settings specified, "
6187 "high_water(%u), low_water(%u), send_xon(%u) and "
6188 "mac_ctrl_frame_fwd(%u) must be set to '0'",
6189 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
6190 pfc_conf->fc.send_xon,
6191 pfc_conf->fc.mac_ctrl_frame_fwd);
6194 if (pfc_conf->fc.autoneg) {
6195 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
6198 if (pfc_conf->fc.pause_time == 0) {
6199 hns3_err(hw, "Invalid pause time %u setting.",
6200 pfc_conf->fc.pause_time);
6204 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6205 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
6206 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
6207 "current_fc_status = %d", hw->current_fc_status);
6211 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
6213 rte_spinlock_lock(&hw->lock);
6214 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
6215 rte_spinlock_unlock(&hw->lock);
6221 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
6223 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6224 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6225 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
6228 rte_spinlock_lock(&hw->lock);
6229 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
6230 dcb_info->nb_tcs = pf->local_max_tc;
6232 dcb_info->nb_tcs = 1;
6234 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
6235 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
6236 for (i = 0; i < dcb_info->nb_tcs; i++)
6237 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
6239 for (i = 0; i < hw->num_tc; i++) {
6240 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
6241 dcb_info->tc_queue.tc_txq[0][i].base =
6242 hw->tc_queue[i].tqp_offset;
6243 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
6244 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
6245 hw->tc_queue[i].tqp_count;
6247 rte_spinlock_unlock(&hw->lock);
6253 hns3_reinit_dev(struct hns3_adapter *hns)
6255 struct hns3_hw *hw = &hns->hw;
6258 ret = hns3_cmd_init(hw);
6260 hns3_err(hw, "Failed to init cmd: %d", ret);
6264 ret = hns3_reset_all_tqps(hns);
6266 hns3_err(hw, "Failed to reset all queues: %d", ret);
6270 ret = hns3_init_hardware(hns);
6272 hns3_err(hw, "Failed to init hardware: %d", ret);
6276 ret = hns3_enable_hw_error_intr(hns, true);
6278 hns3_err(hw, "fail to enable hw error interrupts: %d",
6282 hns3_info(hw, "Reset done, driver initialization finished.");
6288 is_pf_reset_done(struct hns3_hw *hw)
6290 uint32_t val, reg, reg_bit;
6292 switch (hw->reset.level) {
6293 case HNS3_IMP_RESET:
6294 reg = HNS3_GLOBAL_RESET_REG;
6295 reg_bit = HNS3_IMP_RESET_BIT;
6297 case HNS3_GLOBAL_RESET:
6298 reg = HNS3_GLOBAL_RESET_REG;
6299 reg_bit = HNS3_GLOBAL_RESET_BIT;
6301 case HNS3_FUNC_RESET:
6302 reg = HNS3_FUN_RST_ING;
6303 reg_bit = HNS3_FUN_RST_ING_B;
6305 case HNS3_FLR_RESET:
6307 hns3_err(hw, "Wait for unsupported reset level: %d",
6311 val = hns3_read_dev(hw, reg);
6312 if (hns3_get_bit(val, reg_bit))
6319 hns3_is_reset_pending(struct hns3_adapter *hns)
6321 struct hns3_hw *hw = &hns->hw;
6322 enum hns3_reset_level reset;
6324 hns3_check_event_cause(hns, NULL);
6325 reset = hns3_get_reset_level(hns, &hw->reset.pending);
6327 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6328 hw->reset.level < reset) {
6329 hns3_warn(hw, "High level reset %d is pending", reset);
6332 reset = hns3_get_reset_level(hns, &hw->reset.request);
6333 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6334 hw->reset.level < reset) {
6335 hns3_warn(hw, "High level reset %d is request", reset);
6342 hns3_wait_hardware_ready(struct hns3_adapter *hns)
6344 struct hns3_hw *hw = &hns->hw;
6345 struct hns3_wait_data *wait_data = hw->reset.wait_data;
6348 if (wait_data->result == HNS3_WAIT_SUCCESS)
6350 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
6351 hns3_clock_gettime(&tv);
6352 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
6353 tv.tv_sec, tv.tv_usec);
6355 } else if (wait_data->result == HNS3_WAIT_REQUEST)
6358 wait_data->hns = hns;
6359 wait_data->check_completion = is_pf_reset_done;
6360 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
6361 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms();
6362 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
6363 wait_data->count = HNS3_RESET_WAIT_CNT;
6364 wait_data->result = HNS3_WAIT_REQUEST;
6365 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
6370 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
6372 struct hns3_cmd_desc desc;
6373 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6375 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6376 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6377 req->fun_reset_vfid = func_id;
6379 return hns3_cmd_send(hw, &desc, 1);
6383 hns3_imp_reset_cmd(struct hns3_hw *hw)
6385 struct hns3_cmd_desc desc;
6387 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6388 desc.data[0] = 0xeedd;
6390 return hns3_cmd_send(hw, &desc, 1);
6394 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6396 struct hns3_hw *hw = &hns->hw;
6400 hns3_clock_gettime(&tv);
6401 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6402 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6403 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6404 tv.tv_sec, tv.tv_usec);
6408 switch (reset_level) {
6409 case HNS3_IMP_RESET:
6410 hns3_imp_reset_cmd(hw);
6411 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6412 tv.tv_sec, tv.tv_usec);
6414 case HNS3_GLOBAL_RESET:
6415 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6416 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6417 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6418 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6419 tv.tv_sec, tv.tv_usec);
6421 case HNS3_FUNC_RESET:
6422 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6423 tv.tv_sec, tv.tv_usec);
6424 /* schedule again to check later */
6425 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6426 hns3_schedule_reset(hns);
6429 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6432 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6435 static enum hns3_reset_level
6436 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6438 struct hns3_hw *hw = &hns->hw;
6439 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6441 /* Return the highest priority reset level amongst all */
6442 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6443 reset_level = HNS3_IMP_RESET;
6444 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6445 reset_level = HNS3_GLOBAL_RESET;
6446 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6447 reset_level = HNS3_FUNC_RESET;
6448 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6449 reset_level = HNS3_FLR_RESET;
6451 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6452 return HNS3_NONE_RESET;
6458 hns3_record_imp_error(struct hns3_adapter *hns)
6460 struct hns3_hw *hw = &hns->hw;
6463 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6464 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6465 hns3_warn(hw, "Detected IMP RD poison!");
6466 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6467 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6470 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6471 hns3_warn(hw, "Detected IMP CMDQ error!");
6472 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6473 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6478 hns3_prepare_reset(struct hns3_adapter *hns)
6480 struct hns3_hw *hw = &hns->hw;
6484 switch (hw->reset.level) {
6485 case HNS3_FUNC_RESET:
6486 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6491 * After performaning pf reset, it is not necessary to do the
6492 * mailbox handling or send any command to firmware, because
6493 * any mailbox handling or command to firmware is only valid
6494 * after hns3_cmd_init is called.
6496 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6497 hw->reset.stats.request_cnt++;
6499 case HNS3_IMP_RESET:
6500 hns3_record_imp_error(hns);
6501 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6502 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6503 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6512 hns3_set_rst_done(struct hns3_hw *hw)
6514 struct hns3_pf_rst_done_cmd *req;
6515 struct hns3_cmd_desc desc;
6517 req = (struct hns3_pf_rst_done_cmd *)desc.data;
6518 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6519 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6520 return hns3_cmd_send(hw, &desc, 1);
6524 hns3_stop_service(struct hns3_adapter *hns)
6526 struct hns3_hw *hw = &hns->hw;
6527 struct rte_eth_dev *eth_dev;
6529 eth_dev = &rte_eth_devices[hw->data->port_id];
6530 hw->mac.link_status = ETH_LINK_DOWN;
6531 if (hw->adapter_state == HNS3_NIC_STARTED) {
6532 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6533 hns3_update_linkstatus_and_event(hw, false);
6536 hns3_set_rxtx_function(eth_dev);
6538 /* Disable datapath on secondary process. */
6539 hns3_mp_req_stop_rxtx(eth_dev);
6540 rte_delay_ms(hw->tqps_num);
6542 rte_spinlock_lock(&hw->lock);
6543 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6544 hw->adapter_state == HNS3_NIC_STOPPING) {
6545 hns3_enable_all_queues(hw, false);
6547 hw->reset.mbuf_deferred_free = true;
6549 hw->reset.mbuf_deferred_free = false;
6552 * It is cumbersome for hardware to pick-and-choose entries for deletion
6553 * from table space. Hence, for function reset software intervention is
6554 * required to delete the entries
6556 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6557 hns3_configure_all_mc_mac_addr(hns, true);
6558 rte_spinlock_unlock(&hw->lock);
6564 hns3_start_service(struct hns3_adapter *hns)
6566 struct hns3_hw *hw = &hns->hw;
6567 struct rte_eth_dev *eth_dev;
6569 if (hw->reset.level == HNS3_IMP_RESET ||
6570 hw->reset.level == HNS3_GLOBAL_RESET)
6571 hns3_set_rst_done(hw);
6572 eth_dev = &rte_eth_devices[hw->data->port_id];
6573 hns3_set_rxtx_function(eth_dev);
6574 hns3_mp_req_start_rxtx(eth_dev);
6575 if (hw->adapter_state == HNS3_NIC_STARTED) {
6577 * This API parent function already hold the hns3_hw.lock, the
6578 * hns3_service_handler may report lse, in bonding application
6579 * it will call driver's ops which may acquire the hns3_hw.lock
6580 * again, thus lead to deadlock.
6581 * We defer calls hns3_service_handler to avoid the deadlock.
6583 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6584 hns3_service_handler, eth_dev);
6586 /* Enable interrupt of all rx queues before enabling queues */
6587 hns3_dev_all_rx_queue_intr_enable(hw, true);
6589 * Enable state of each rxq and txq will be recovered after
6590 * reset, so we need to restore them before enable all tqps;
6592 hns3_restore_tqp_enable_state(hw);
6594 * When finished the initialization, enable queues to receive
6595 * and transmit packets.
6597 hns3_enable_all_queues(hw, true);
6604 hns3_restore_conf(struct hns3_adapter *hns)
6606 struct hns3_hw *hw = &hns->hw;
6609 ret = hns3_configure_all_mac_addr(hns, false);
6613 ret = hns3_configure_all_mc_mac_addr(hns, false);
6617 ret = hns3_dev_promisc_restore(hns);
6621 ret = hns3_restore_vlan_table(hns);
6625 ret = hns3_restore_vlan_conf(hns);
6629 ret = hns3_restore_all_fdir_filter(hns);
6633 ret = hns3_restore_ptp(hns);
6637 ret = hns3_restore_rx_interrupt(hw);
6641 ret = hns3_restore_gro_conf(hw);
6645 ret = hns3_restore_fec(hw);
6649 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6650 ret = hns3_do_start(hns, false);
6653 hns3_info(hw, "hns3 dev restart successful!");
6654 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6655 hw->adapter_state = HNS3_NIC_CONFIGURED;
6659 hns3_configure_all_mc_mac_addr(hns, true);
6661 hns3_configure_all_mac_addr(hns, true);
6666 hns3_reset_service(void *param)
6668 struct hns3_adapter *hns = (struct hns3_adapter *)param;
6669 struct hns3_hw *hw = &hns->hw;
6670 enum hns3_reset_level reset_level;
6671 struct timeval tv_delta;
6672 struct timeval tv_start;
6678 * The interrupt is not triggered within the delay time.
6679 * The interrupt may have been lost. It is necessary to handle
6680 * the interrupt to recover from the error.
6682 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6683 SCHEDULE_DEFERRED) {
6684 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6686 hns3_err(hw, "Handling interrupts in delayed tasks");
6687 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6688 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6689 if (reset_level == HNS3_NONE_RESET) {
6690 hns3_err(hw, "No reset level is set, try IMP reset");
6691 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6694 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6697 * Check if there is any ongoing reset in the hardware. This status can
6698 * be checked from reset_pending. If there is then, we need to wait for
6699 * hardware to complete reset.
6700 * a. If we are able to figure out in reasonable time that hardware
6701 * has fully resetted then, we can proceed with driver, client
6703 * b. else, we can come back later to check this status so re-sched
6706 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6707 if (reset_level != HNS3_NONE_RESET) {
6708 hns3_clock_gettime(&tv_start);
6709 ret = hns3_reset_process(hns, reset_level);
6710 hns3_clock_gettime(&tv);
6711 timersub(&tv, &tv_start, &tv_delta);
6712 msec = hns3_clock_calctime_ms(&tv_delta);
6713 if (msec > HNS3_RESET_PROCESS_MS)
6714 hns3_err(hw, "%d handle long time delta %" PRIu64
6715 " ms time=%ld.%.6ld",
6716 hw->reset.level, msec,
6717 tv.tv_sec, tv.tv_usec);
6722 /* Check if we got any *new* reset requests to be honored */
6723 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6724 if (reset_level != HNS3_NONE_RESET)
6725 hns3_msix_process(hns, reset_level);
6729 hns3_get_speed_capa_num(uint16_t device_id)
6733 switch (device_id) {
6734 case HNS3_DEV_ID_25GE:
6735 case HNS3_DEV_ID_25GE_RDMA:
6738 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6739 case HNS3_DEV_ID_200G_RDMA:
6751 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6754 switch (device_id) {
6755 case HNS3_DEV_ID_25GE:
6757 case HNS3_DEV_ID_25GE_RDMA:
6758 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6759 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6761 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6762 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6763 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6765 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6766 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6767 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6769 case HNS3_DEV_ID_200G_RDMA:
6770 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6771 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6781 hns3_fec_get_capability(struct rte_eth_dev *dev,
6782 struct rte_eth_fec_capa *speed_fec_capa,
6785 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6786 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6787 uint16_t device_id = pci_dev->id.device_id;
6788 unsigned int capa_num;
6791 capa_num = hns3_get_speed_capa_num(device_id);
6792 if (capa_num == 0) {
6793 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6798 if (speed_fec_capa == NULL || num < capa_num)
6801 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6809 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6811 struct hns3_config_fec_cmd *req;
6812 struct hns3_cmd_desc desc;
6816 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6817 * in device of link speed
6820 if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6825 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6826 req = (struct hns3_config_fec_cmd *)desc.data;
6827 ret = hns3_cmd_send(hw, &desc, 1);
6829 hns3_err(hw, "get current fec auto state failed, ret = %d",
6834 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6839 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6841 struct hns3_sfp_info_cmd *resp;
6842 uint32_t tmp_fec_capa;
6844 struct hns3_cmd_desc desc;
6848 * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6849 * configured FEC mode is returned.
6850 * If link is up, current FEC mode is returned.
6852 if (hw->mac.link_status == ETH_LINK_DOWN) {
6853 ret = get_current_fec_auto_state(hw, &auto_state);
6857 if (auto_state == 0x1) {
6858 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6863 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6864 resp = (struct hns3_sfp_info_cmd *)desc.data;
6865 resp->query_type = HNS3_ACTIVE_QUERY;
6867 ret = hns3_cmd_send(hw, &desc, 1);
6868 if (ret == -EOPNOTSUPP) {
6869 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6872 hns3_err(hw, "get FEC failed, ret = %d", ret);
6877 * FEC mode order defined in hns3 hardware is inconsistend with
6878 * that defined in the ethdev library. So the sequence needs
6881 switch (resp->active_fec) {
6882 case HNS3_HW_FEC_MODE_NOFEC:
6883 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6885 case HNS3_HW_FEC_MODE_BASER:
6886 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6888 case HNS3_HW_FEC_MODE_RS:
6889 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6892 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6896 *fec_capa = tmp_fec_capa;
6901 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6903 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6905 return hns3_fec_get_internal(hw, fec_capa);
6909 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6911 struct hns3_config_fec_cmd *req;
6912 struct hns3_cmd_desc desc;
6915 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6917 req = (struct hns3_config_fec_cmd *)desc.data;
6919 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6920 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6921 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6923 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6924 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6925 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6927 case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6928 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6929 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6931 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6932 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6937 ret = hns3_cmd_send(hw, &desc, 1);
6939 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6945 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6947 struct hns3_mac *mac = &hw->mac;
6950 switch (mac->link_speed) {
6951 case ETH_SPEED_NUM_10G:
6952 cur_capa = fec_capa[1].capa;
6954 case ETH_SPEED_NUM_25G:
6955 case ETH_SPEED_NUM_100G:
6956 case ETH_SPEED_NUM_200G:
6957 cur_capa = fec_capa[0].capa;
6968 is_fec_mode_one_bit_set(uint32_t mode)
6973 for (i = 0; i < sizeof(mode); i++)
6974 if (mode >> i & 0x1)
6977 return cnt == 1 ? true : false;
6981 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6983 #define FEC_CAPA_NUM 2
6984 struct hns3_adapter *hns = dev->data->dev_private;
6985 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6986 struct hns3_pf *pf = &hns->pf;
6988 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6990 uint32_t num = FEC_CAPA_NUM;
6993 ret = hns3_fec_get_capability(dev, fec_capa, num);
6997 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6998 if (!is_fec_mode_one_bit_set(mode))
6999 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
7000 "FEC mode should be only one bit set", mode);
7003 * Check whether the configured mode is within the FEC capability.
7004 * If not, the configured mode will not be supported.
7006 cur_capa = get_current_speed_fec_cap(hw, fec_capa);
7007 if (!(cur_capa & mode)) {
7008 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
7012 rte_spinlock_lock(&hw->lock);
7013 ret = hns3_set_fec_hw(hw, mode);
7015 rte_spinlock_unlock(&hw->lock);
7019 pf->fec_mode = mode;
7020 rte_spinlock_unlock(&hw->lock);
7026 hns3_restore_fec(struct hns3_hw *hw)
7028 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7029 struct hns3_pf *pf = &hns->pf;
7030 uint32_t mode = pf->fec_mode;
7033 ret = hns3_set_fec_hw(hw, mode);
7035 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
7042 hns3_query_dev_fec_info(struct hns3_hw *hw)
7044 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7045 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
7048 ret = hns3_fec_get_internal(hw, &pf->fec_mode);
7050 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
7056 hns3_optical_module_existed(struct hns3_hw *hw)
7058 struct hns3_cmd_desc desc;
7062 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
7063 ret = hns3_cmd_send(hw, &desc, 1);
7066 "fail to get optical module exist state, ret = %d.\n",
7070 existed = !!desc.data[0];
7076 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
7077 uint32_t len, uint8_t *data)
7079 #define HNS3_SFP_INFO_CMD_NUM 6
7080 #define HNS3_SFP_INFO_MAX_LEN \
7081 (HNS3_SFP_INFO_BD0_LEN + \
7082 (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
7083 struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
7084 struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
7090 for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7091 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
7093 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
7094 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
7097 sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
7098 sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
7099 read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
7100 sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
7102 ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
7104 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
7109 /* The data format in BD0 is different with the others. */
7110 copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
7111 memcpy(data, sfp_info_bd0->data, copy_len);
7112 read_len = copy_len;
7114 for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7115 if (read_len >= len)
7118 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
7119 memcpy(data + read_len, desc[i].data, copy_len);
7120 read_len += copy_len;
7123 return (int)read_len;
7127 hns3_get_module_eeprom(struct rte_eth_dev *dev,
7128 struct rte_dev_eeprom_info *info)
7130 struct hns3_adapter *hns = dev->data->dev_private;
7131 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7132 uint32_t offset = info->offset;
7133 uint32_t len = info->length;
7134 uint8_t *data = info->data;
7135 uint32_t read_len = 0;
7137 if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
7140 if (!hns3_optical_module_existed(hw)) {
7141 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
7145 while (read_len < len) {
7147 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
7159 hns3_get_module_info(struct rte_eth_dev *dev,
7160 struct rte_eth_dev_module_info *modinfo)
7162 #define HNS3_SFF8024_ID_SFP 0x03
7163 #define HNS3_SFF8024_ID_QSFP_8438 0x0c
7164 #define HNS3_SFF8024_ID_QSFP_8436_8636 0x0d
7165 #define HNS3_SFF8024_ID_QSFP28_8636 0x11
7166 #define HNS3_SFF_8636_V1_3 0x03
7167 struct hns3_adapter *hns = dev->data->dev_private;
7168 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7169 struct rte_dev_eeprom_info info;
7170 struct hns3_sfp_type sfp_type;
7173 memset(&sfp_type, 0, sizeof(sfp_type));
7174 memset(&info, 0, sizeof(info));
7175 info.data = (uint8_t *)&sfp_type;
7176 info.length = sizeof(sfp_type);
7177 ret = hns3_get_module_eeprom(dev, &info);
7181 switch (sfp_type.type) {
7182 case HNS3_SFF8024_ID_SFP:
7183 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7184 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7186 case HNS3_SFF8024_ID_QSFP_8438:
7187 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7188 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7190 case HNS3_SFF8024_ID_QSFP_8436_8636:
7191 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
7192 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7193 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7195 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7196 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7199 case HNS3_SFF8024_ID_QSFP28_8636:
7200 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7201 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7204 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
7205 sfp_type.type, sfp_type.ext_type);
7213 hns3_clock_gettime(struct timeval *tv)
7215 #ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */
7216 #define CLOCK_TYPE CLOCK_MONOTONIC_RAW
7218 #define CLOCK_TYPE CLOCK_MONOTONIC
7220 #define NSEC_TO_USEC_DIV 1000
7222 struct timespec spec;
7223 (void)clock_gettime(CLOCK_TYPE, &spec);
7225 tv->tv_sec = spec.tv_sec;
7226 tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV;
7230 hns3_clock_calctime_ms(struct timeval *tv)
7232 return (uint64_t)tv->tv_sec * MSEC_PER_SEC +
7233 tv->tv_usec / USEC_PER_MSEC;
7237 hns3_clock_gettime_ms(void)
7241 hns3_clock_gettime(&tv);
7242 return hns3_clock_calctime_ms(&tv);
7246 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
7248 uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
7252 if (strcmp(value, "vec") == 0)
7253 hint = HNS3_IO_FUNC_HINT_VEC;
7254 else if (strcmp(value, "sve") == 0)
7255 hint = HNS3_IO_FUNC_HINT_SVE;
7256 else if (strcmp(value, "simple") == 0)
7257 hint = HNS3_IO_FUNC_HINT_SIMPLE;
7258 else if (strcmp(value, "common") == 0)
7259 hint = HNS3_IO_FUNC_HINT_COMMON;
7261 /* If the hint is valid then update output parameters */
7262 if (hint != HNS3_IO_FUNC_HINT_NONE)
7263 *(uint32_t *)extra_args = hint;
7269 hns3_get_io_hint_func_name(uint32_t hint)
7272 case HNS3_IO_FUNC_HINT_VEC:
7274 case HNS3_IO_FUNC_HINT_SVE:
7276 case HNS3_IO_FUNC_HINT_SIMPLE:
7278 case HNS3_IO_FUNC_HINT_COMMON:
7286 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args)
7292 val = strtoull(value, NULL, 16);
7293 *(uint64_t *)extra_args = val;
7299 hns3_parse_devargs(struct rte_eth_dev *dev)
7301 struct hns3_adapter *hns = dev->data->dev_private;
7302 uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7303 uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7304 struct hns3_hw *hw = &hns->hw;
7305 uint64_t dev_caps_mask = 0;
7306 struct rte_kvargs *kvlist;
7308 if (dev->device->devargs == NULL)
7311 kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
7315 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
7316 &hns3_parse_io_hint_func, &rx_func_hint);
7317 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
7318 &hns3_parse_io_hint_func, &tx_func_hint);
7319 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK,
7320 &hns3_parse_dev_caps_mask, &dev_caps_mask);
7321 rte_kvargs_free(kvlist);
7323 if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7324 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
7325 hns3_get_io_hint_func_name(rx_func_hint));
7326 hns->rx_func_hint = rx_func_hint;
7327 if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7328 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
7329 hns3_get_io_hint_func_name(tx_func_hint));
7330 hns->tx_func_hint = tx_func_hint;
7332 if (dev_caps_mask != 0)
7333 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".",
7334 HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask);
7335 hns->dev_caps_mask = dev_caps_mask;
7338 static const struct eth_dev_ops hns3_eth_dev_ops = {
7339 .dev_configure = hns3_dev_configure,
7340 .dev_start = hns3_dev_start,
7341 .dev_stop = hns3_dev_stop,
7342 .dev_close = hns3_dev_close,
7343 .promiscuous_enable = hns3_dev_promiscuous_enable,
7344 .promiscuous_disable = hns3_dev_promiscuous_disable,
7345 .allmulticast_enable = hns3_dev_allmulticast_enable,
7346 .allmulticast_disable = hns3_dev_allmulticast_disable,
7347 .mtu_set = hns3_dev_mtu_set,
7348 .stats_get = hns3_stats_get,
7349 .stats_reset = hns3_stats_reset,
7350 .xstats_get = hns3_dev_xstats_get,
7351 .xstats_get_names = hns3_dev_xstats_get_names,
7352 .xstats_reset = hns3_dev_xstats_reset,
7353 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
7354 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
7355 .dev_infos_get = hns3_dev_infos_get,
7356 .fw_version_get = hns3_fw_version_get,
7357 .rx_queue_setup = hns3_rx_queue_setup,
7358 .tx_queue_setup = hns3_tx_queue_setup,
7359 .rx_queue_release = hns3_dev_rx_queue_release,
7360 .tx_queue_release = hns3_dev_tx_queue_release,
7361 .rx_queue_start = hns3_dev_rx_queue_start,
7362 .rx_queue_stop = hns3_dev_rx_queue_stop,
7363 .tx_queue_start = hns3_dev_tx_queue_start,
7364 .tx_queue_stop = hns3_dev_tx_queue_stop,
7365 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
7366 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
7367 .rxq_info_get = hns3_rxq_info_get,
7368 .txq_info_get = hns3_txq_info_get,
7369 .rx_burst_mode_get = hns3_rx_burst_mode_get,
7370 .tx_burst_mode_get = hns3_tx_burst_mode_get,
7371 .flow_ctrl_get = hns3_flow_ctrl_get,
7372 .flow_ctrl_set = hns3_flow_ctrl_set,
7373 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
7374 .mac_addr_add = hns3_add_mac_addr,
7375 .mac_addr_remove = hns3_remove_mac_addr,
7376 .mac_addr_set = hns3_set_default_mac_addr,
7377 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
7378 .link_update = hns3_dev_link_update,
7379 .rss_hash_update = hns3_dev_rss_hash_update,
7380 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
7381 .reta_update = hns3_dev_rss_reta_update,
7382 .reta_query = hns3_dev_rss_reta_query,
7383 .flow_ops_get = hns3_dev_flow_ops_get,
7384 .vlan_filter_set = hns3_vlan_filter_set,
7385 .vlan_tpid_set = hns3_vlan_tpid_set,
7386 .vlan_offload_set = hns3_vlan_offload_set,
7387 .vlan_pvid_set = hns3_vlan_pvid_set,
7388 .get_reg = hns3_get_regs,
7389 .get_module_info = hns3_get_module_info,
7390 .get_module_eeprom = hns3_get_module_eeprom,
7391 .get_dcb_info = hns3_get_dcb_info,
7392 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
7393 .fec_get_capability = hns3_fec_get_capability,
7394 .fec_get = hns3_fec_get,
7395 .fec_set = hns3_fec_set,
7396 .tm_ops_get = hns3_tm_ops_get,
7397 .tx_done_cleanup = hns3_tx_done_cleanup,
7398 .timesync_enable = hns3_timesync_enable,
7399 .timesync_disable = hns3_timesync_disable,
7400 .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
7401 .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
7402 .timesync_adjust_time = hns3_timesync_adjust_time,
7403 .timesync_read_time = hns3_timesync_read_time,
7404 .timesync_write_time = hns3_timesync_write_time,
7407 static const struct hns3_reset_ops hns3_reset_ops = {
7408 .reset_service = hns3_reset_service,
7409 .stop_service = hns3_stop_service,
7410 .prepare_reset = hns3_prepare_reset,
7411 .wait_hardware_ready = hns3_wait_hardware_ready,
7412 .reinit_dev = hns3_reinit_dev,
7413 .restore_conf = hns3_restore_conf,
7414 .start_service = hns3_start_service,
7418 hns3_dev_init(struct rte_eth_dev *eth_dev)
7420 struct hns3_adapter *hns = eth_dev->data->dev_private;
7421 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
7422 struct rte_ether_addr *eth_addr;
7423 struct hns3_hw *hw = &hns->hw;
7426 PMD_INIT_FUNC_TRACE();
7428 eth_dev->process_private = (struct hns3_process_private *)
7429 rte_zmalloc_socket("hns3_filter_list",
7430 sizeof(struct hns3_process_private),
7431 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
7432 if (eth_dev->process_private == NULL) {
7433 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
7437 hns3_flow_init(eth_dev);
7439 hns3_set_rxtx_function(eth_dev);
7440 eth_dev->dev_ops = &hns3_eth_dev_ops;
7441 eth_dev->rx_queue_count = hns3_rx_queue_count;
7442 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7443 ret = hns3_mp_init_secondary();
7445 PMD_INIT_LOG(ERR, "Failed to init for secondary "
7446 "process, ret = %d", ret);
7447 goto err_mp_init_secondary;
7450 hw->secondary_cnt++;
7454 ret = hns3_mp_init_primary();
7457 "Failed to init for primary process, ret = %d",
7459 goto err_mp_init_primary;
7462 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
7464 hw->data = eth_dev->data;
7465 hns3_parse_devargs(eth_dev);
7468 * Set default max packet size according to the mtu
7469 * default vale in DPDK frame.
7471 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
7473 ret = hns3_reset_init(hw);
7475 goto err_init_reset;
7476 hw->reset.ops = &hns3_reset_ops;
7478 ret = hns3_init_pf(eth_dev);
7480 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
7484 /* Allocate memory for storing MAC addresses */
7485 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
7486 sizeof(struct rte_ether_addr) *
7487 HNS3_UC_MACADDR_NUM, 0);
7488 if (eth_dev->data->mac_addrs == NULL) {
7489 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
7490 "to store MAC addresses",
7491 sizeof(struct rte_ether_addr) *
7492 HNS3_UC_MACADDR_NUM);
7494 goto err_rte_zmalloc;
7497 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
7498 if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
7499 rte_eth_random_addr(hw->mac.mac_addr);
7500 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
7501 (struct rte_ether_addr *)hw->mac.mac_addr);
7502 hns3_warn(hw, "default mac_addr from firmware is an invalid "
7503 "unicast address, using random MAC address %s",
7506 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7507 ð_dev->data->mac_addrs[0]);
7509 hw->adapter_state = HNS3_NIC_INITIALIZED;
7511 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7513 hns3_err(hw, "Reschedule reset service after dev_init");
7514 hns3_schedule_reset(hns);
7516 /* IMP will wait ready flag before reset */
7517 hns3_notify_reset_ready(hw, false);
7520 hns3_info(hw, "hns3 dev initialization successful!");
7524 hns3_uninit_pf(eth_dev);
7527 rte_free(hw->reset.wait_data);
7530 hns3_mp_uninit_primary();
7532 err_mp_init_primary:
7533 err_mp_init_secondary:
7534 eth_dev->dev_ops = NULL;
7535 eth_dev->rx_pkt_burst = NULL;
7536 eth_dev->rx_descriptor_status = NULL;
7537 eth_dev->tx_pkt_burst = NULL;
7538 eth_dev->tx_pkt_prepare = NULL;
7539 eth_dev->tx_descriptor_status = NULL;
7540 rte_free(eth_dev->process_private);
7541 eth_dev->process_private = NULL;
7546 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7548 struct hns3_adapter *hns = eth_dev->data->dev_private;
7549 struct hns3_hw *hw = &hns->hw;
7551 PMD_INIT_FUNC_TRACE();
7553 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7554 rte_free(eth_dev->process_private);
7555 eth_dev->process_private = NULL;
7559 if (hw->adapter_state < HNS3_NIC_CLOSING)
7560 hns3_dev_close(eth_dev);
7562 hw->adapter_state = HNS3_NIC_REMOVED;
7567 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7568 struct rte_pci_device *pci_dev)
7570 return rte_eth_dev_pci_generic_probe(pci_dev,
7571 sizeof(struct hns3_adapter),
7576 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7578 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7581 static const struct rte_pci_id pci_id_hns3_map[] = {
7582 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7583 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7584 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7585 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7586 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7587 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7588 { .vendor_id = 0, }, /* sentinel */
7591 static struct rte_pci_driver rte_hns3_pmd = {
7592 .id_table = pci_id_hns3_map,
7593 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7594 .probe = eth_hns3_pci_probe,
7595 .remove = eth_hns3_pci_remove,
7598 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7599 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7600 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7601 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7602 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7603 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
7604 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");
7605 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
7606 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);