1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
6 #include <rte_bus_pci.h>
7 #include <ethdev_pci.h>
9 #include <rte_kvargs.h>
11 #include "hns3_ethdev.h"
12 #include "hns3_logs.h"
13 #include "hns3_rxtx.h"
14 #include "hns3_intr.h"
15 #include "hns3_regs.h"
19 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
20 #define HNS3_SERVICE_QUICK_INTERVAL 10
21 #define HNS3_INVALID_PVID 0xFFFF
23 #define HNS3_FILTER_TYPE_VF 0
24 #define HNS3_FILTER_TYPE_PORT 1
25 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
26 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
27 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
28 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
29 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
30 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
31 | HNS3_FILTER_FE_ROCE_EGRESS_B)
32 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
33 | HNS3_FILTER_FE_ROCE_INGRESS_B)
35 /* Reset related Registers */
36 #define HNS3_GLOBAL_RESET_BIT 0
37 #define HNS3_CORE_RESET_BIT 1
38 #define HNS3_IMP_RESET_BIT 2
39 #define HNS3_FUN_RST_ING_B 0
41 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
42 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
43 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U
44 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
46 #define HNS3_RESET_WAIT_MS 100
47 #define HNS3_RESET_WAIT_CNT 200
49 /* FEC mode order defined in HNS3 hardware */
50 #define HNS3_HW_FEC_MODE_NOFEC 0
51 #define HNS3_HW_FEC_MODE_BASER 1
52 #define HNS3_HW_FEC_MODE_RS 2
55 HNS3_VECTOR0_EVENT_RST,
56 HNS3_VECTOR0_EVENT_MBX,
57 HNS3_VECTOR0_EVENT_ERR,
58 HNS3_VECTOR0_EVENT_PTP,
59 HNS3_VECTOR0_EVENT_OTHER,
62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
63 { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
64 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
65 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
67 { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
68 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
69 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
70 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
72 { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
73 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
74 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
76 { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
77 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
78 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
79 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
81 { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
82 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
83 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
85 { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
86 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
87 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
95 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
96 static bool hns3_update_link_status(struct hns3_hw *hw);
98 static int hns3_add_mc_addr(struct hns3_hw *hw,
99 struct rte_ether_addr *mac_addr);
100 static int hns3_remove_mc_addr(struct hns3_hw *hw,
101 struct rte_ether_addr *mac_addr);
102 static int hns3_restore_fec(struct hns3_hw *hw);
103 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
104 static int hns3_do_stop(struct hns3_adapter *hns);
105 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
107 void hns3_ether_format_addr(char *buf, uint16_t size,
108 const struct rte_ether_addr *ether_addr)
110 snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
111 ether_addr->addr_bytes[0],
112 ether_addr->addr_bytes[4],
113 ether_addr->addr_bytes[5]);
117 hns3_pf_disable_irq0(struct hns3_hw *hw)
119 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
123 hns3_pf_enable_irq0(struct hns3_hw *hw)
125 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
128 static enum hns3_evt_cause
129 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
132 struct hns3_hw *hw = &hns->hw;
134 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
135 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
136 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
138 hw->reset.stats.imp_cnt++;
139 hns3_warn(hw, "IMP reset detected, clear reset status");
141 hns3_schedule_delayed_reset(hns);
142 hns3_warn(hw, "IMP reset detected, don't clear reset status");
145 return HNS3_VECTOR0_EVENT_RST;
148 static enum hns3_evt_cause
149 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
152 struct hns3_hw *hw = &hns->hw;
154 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
155 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
156 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
158 hw->reset.stats.global_cnt++;
159 hns3_warn(hw, "Global reset detected, clear reset status");
161 hns3_schedule_delayed_reset(hns);
163 "Global reset detected, don't clear reset status");
166 return HNS3_VECTOR0_EVENT_RST;
169 static enum hns3_evt_cause
170 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
172 struct hns3_hw *hw = &hns->hw;
173 uint32_t vector0_int_stats;
174 uint32_t cmdq_src_val;
175 uint32_t hw_err_src_reg;
177 enum hns3_evt_cause ret;
180 /* fetch the events from their corresponding regs */
181 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
182 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
183 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
185 is_delay = clearval == NULL ? true : false;
187 * Assumption: If by any chance reset and mailbox events are reported
188 * together then we will only process reset event and defer the
189 * processing of the mailbox events. Since, we would have not cleared
190 * RX CMDQ event this time we would receive again another interrupt
191 * from H/W just for the mailbox.
193 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
194 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
199 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
200 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
204 /* Check for vector0 1588 event source */
205 if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
206 val = BIT(HNS3_VECTOR0_1588_INT_B);
207 ret = HNS3_VECTOR0_EVENT_PTP;
211 /* check for vector0 msix event source */
212 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
213 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
214 val = vector0_int_stats | hw_err_src_reg;
215 ret = HNS3_VECTOR0_EVENT_ERR;
219 /* check for vector0 mailbox(=CMDQ RX) event source */
220 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
221 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
223 ret = HNS3_VECTOR0_EVENT_MBX;
227 val = vector0_int_stats;
228 ret = HNS3_VECTOR0_EVENT_OTHER;
237 hns3_is_1588_event_type(uint32_t event_type)
239 return (event_type == HNS3_VECTOR0_EVENT_PTP);
243 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
245 if (event_type == HNS3_VECTOR0_EVENT_RST ||
246 hns3_is_1588_event_type(event_type))
247 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
248 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
249 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
253 hns3_clear_all_event_cause(struct hns3_hw *hw)
255 uint32_t vector0_int_stats;
256 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
258 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
259 hns3_warn(hw, "Probe during IMP reset interrupt");
261 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
262 hns3_warn(hw, "Probe during Global reset interrupt");
264 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
265 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
266 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
267 BIT(HNS3_VECTOR0_CORERESET_INT_B));
268 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
269 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
270 BIT(HNS3_VECTOR0_1588_INT_B));
274 hns3_handle_mac_tnl(struct hns3_hw *hw)
276 struct hns3_cmd_desc desc;
280 /* query and clear mac tnl interrupt */
281 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
282 ret = hns3_cmd_send(hw, &desc, 1);
284 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
288 status = rte_le_to_cpu_32(desc.data[0]);
290 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
291 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
293 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
294 ret = hns3_cmd_send(hw, &desc, 1);
296 hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
302 hns3_interrupt_handler(void *param)
304 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
305 struct hns3_adapter *hns = dev->data->dev_private;
306 struct hns3_hw *hw = &hns->hw;
307 enum hns3_evt_cause event_cause;
308 uint32_t clearval = 0;
309 uint32_t vector0_int;
313 /* Disable interrupt */
314 hns3_pf_disable_irq0(hw);
316 event_cause = hns3_check_event_cause(hns, &clearval);
317 vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
318 ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
319 cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
320 /* vector 0 interrupt is shared with reset and mailbox source events. */
321 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
322 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
323 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
324 vector0_int, ras_int, cmdq_int);
325 hns3_handle_mac_tnl(hw);
326 hns3_handle_error(hns);
327 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
328 hns3_warn(hw, "received reset interrupt");
329 hns3_schedule_reset(hns);
330 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
331 hns3_dev_handle_mbx_msg(hw);
333 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
334 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
335 vector0_int, ras_int, cmdq_int);
338 hns3_clear_event_cause(hw, event_cause, clearval);
339 /* Enable interrupt if it is not cause by reset */
340 hns3_pf_enable_irq0(hw);
344 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
346 #define HNS3_VLAN_ID_OFFSET_STEP 160
347 #define HNS3_VLAN_BYTE_SIZE 8
348 struct hns3_vlan_filter_pf_cfg_cmd *req;
349 struct hns3_hw *hw = &hns->hw;
350 uint8_t vlan_offset_byte_val;
351 struct hns3_cmd_desc desc;
352 uint8_t vlan_offset_byte;
353 uint8_t vlan_offset_base;
356 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
358 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
359 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
361 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
363 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
364 req->vlan_offset = vlan_offset_base;
365 req->vlan_cfg = on ? 0 : 1;
366 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
368 ret = hns3_cmd_send(hw, &desc, 1);
370 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
377 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
379 struct hns3_user_vlan_table *vlan_entry;
380 struct hns3_pf *pf = &hns->pf;
382 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
383 if (vlan_entry->vlan_id == vlan_id) {
384 if (vlan_entry->hd_tbl_status)
385 hns3_set_port_vlan_filter(hns, vlan_id, 0);
386 LIST_REMOVE(vlan_entry, next);
387 rte_free(vlan_entry);
394 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
397 struct hns3_user_vlan_table *vlan_entry;
398 struct hns3_hw *hw = &hns->hw;
399 struct hns3_pf *pf = &hns->pf;
401 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
402 if (vlan_entry->vlan_id == vlan_id)
406 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
407 if (vlan_entry == NULL) {
408 hns3_err(hw, "Failed to malloc hns3 vlan table");
412 vlan_entry->hd_tbl_status = writen_to_tbl;
413 vlan_entry->vlan_id = vlan_id;
415 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
419 hns3_restore_vlan_table(struct hns3_adapter *hns)
421 struct hns3_user_vlan_table *vlan_entry;
422 struct hns3_hw *hw = &hns->hw;
423 struct hns3_pf *pf = &hns->pf;
427 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
428 return hns3_vlan_pvid_configure(hns,
429 hw->port_base_vlan_cfg.pvid, 1);
431 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
432 if (vlan_entry->hd_tbl_status) {
433 vlan_id = vlan_entry->vlan_id;
434 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
444 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
446 struct hns3_hw *hw = &hns->hw;
447 bool writen_to_tbl = false;
451 * When vlan filter is enabled, hardware regards packets without vlan
452 * as packets with vlan 0. So, to receive packets without vlan, vlan id
453 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
455 if (on == 0 && vlan_id == 0)
459 * When port base vlan enabled, we use port base vlan as the vlan
460 * filter condition. In this case, we don't update vlan filter table
461 * when user add new vlan or remove exist vlan, just update the
462 * vlan list. The vlan id in vlan list will be written in vlan filter
463 * table until port base vlan disabled
465 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
466 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
467 writen_to_tbl = true;
472 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
474 hns3_rm_dev_vlan_table(hns, vlan_id);
480 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
482 struct hns3_adapter *hns = dev->data->dev_private;
483 struct hns3_hw *hw = &hns->hw;
486 rte_spinlock_lock(&hw->lock);
487 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
488 rte_spinlock_unlock(&hw->lock);
493 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
496 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
497 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
498 struct hns3_hw *hw = &hns->hw;
499 struct hns3_cmd_desc desc;
502 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
503 vlan_type != ETH_VLAN_TYPE_OUTER)) {
504 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
508 if (tpid != RTE_ETHER_TYPE_VLAN) {
509 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
513 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
514 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
516 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
517 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
518 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
519 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
520 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
521 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
522 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
523 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
526 ret = hns3_cmd_send(hw, &desc, 1);
528 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
533 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
535 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
536 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
537 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
539 ret = hns3_cmd_send(hw, &desc, 1);
541 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
547 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
550 struct hns3_adapter *hns = dev->data->dev_private;
551 struct hns3_hw *hw = &hns->hw;
554 rte_spinlock_lock(&hw->lock);
555 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
556 rte_spinlock_unlock(&hw->lock);
561 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
562 struct hns3_rx_vtag_cfg *vcfg)
564 struct hns3_vport_vtag_rx_cfg_cmd *req;
565 struct hns3_hw *hw = &hns->hw;
566 struct hns3_cmd_desc desc;
571 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
573 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
574 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
575 vcfg->strip_tag1_en ? 1 : 0);
576 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
577 vcfg->strip_tag2_en ? 1 : 0);
578 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
579 vcfg->vlan1_vlan_prionly ? 1 : 0);
580 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
581 vcfg->vlan2_vlan_prionly ? 1 : 0);
583 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
584 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
585 vcfg->strip_tag1_discard_en ? 1 : 0);
586 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
587 vcfg->strip_tag2_discard_en ? 1 : 0);
589 * In current version VF is not supported when PF is driven by DPDK
590 * driver, just need to configure parameters for PF vport.
592 vport_id = HNS3_PF_FUNC_ID;
593 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
594 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
595 req->vf_bitmap[req->vf_offset] = bitmap;
597 ret = hns3_cmd_send(hw, &desc, 1);
599 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
604 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
605 struct hns3_rx_vtag_cfg *vcfg)
607 struct hns3_pf *pf = &hns->pf;
608 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
612 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
613 struct hns3_tx_vtag_cfg *vcfg)
615 struct hns3_pf *pf = &hns->pf;
616 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
620 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
622 struct hns3_rx_vtag_cfg rxvlan_cfg;
623 struct hns3_hw *hw = &hns->hw;
626 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
627 rxvlan_cfg.strip_tag1_en = false;
628 rxvlan_cfg.strip_tag2_en = enable;
629 rxvlan_cfg.strip_tag2_discard_en = false;
631 rxvlan_cfg.strip_tag1_en = enable;
632 rxvlan_cfg.strip_tag2_en = true;
633 rxvlan_cfg.strip_tag2_discard_en = true;
636 rxvlan_cfg.strip_tag1_discard_en = false;
637 rxvlan_cfg.vlan1_vlan_prionly = false;
638 rxvlan_cfg.vlan2_vlan_prionly = false;
639 rxvlan_cfg.rx_vlan_offload_en = enable;
641 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
643 hns3_err(hw, "%s strip rx vtag failed, ret = %d.",
644 enable ? "enable" : "disable", ret);
648 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
654 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
655 uint8_t fe_type, bool filter_en, uint8_t vf_id)
657 struct hns3_vlan_filter_ctrl_cmd *req;
658 struct hns3_cmd_desc desc;
661 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
663 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
664 req->vlan_type = vlan_type;
665 req->vlan_fe = filter_en ? fe_type : 0;
668 ret = hns3_cmd_send(hw, &desc, 1);
670 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
676 hns3_vlan_filter_init(struct hns3_adapter *hns)
678 struct hns3_hw *hw = &hns->hw;
681 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
682 HNS3_FILTER_FE_EGRESS, false,
685 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
689 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
690 HNS3_FILTER_FE_INGRESS, false,
693 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
699 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
701 struct hns3_hw *hw = &hns->hw;
704 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
705 HNS3_FILTER_FE_INGRESS, enable,
708 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
709 enable ? "enable" : "disable", ret);
715 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
717 struct hns3_adapter *hns = dev->data->dev_private;
718 struct hns3_hw *hw = &hns->hw;
719 struct rte_eth_rxmode *rxmode;
720 unsigned int tmp_mask;
724 rte_spinlock_lock(&hw->lock);
725 rxmode = &dev->data->dev_conf.rxmode;
726 tmp_mask = (unsigned int)mask;
727 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
728 /* ignore vlan filter configuration during promiscuous mode */
729 if (!dev->data->promiscuous) {
730 /* Enable or disable VLAN filter */
731 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
734 ret = hns3_enable_vlan_filter(hns, enable);
736 rte_spinlock_unlock(&hw->lock);
737 hns3_err(hw, "failed to %s rx filter, ret = %d",
738 enable ? "enable" : "disable", ret);
744 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
745 /* Enable or disable VLAN stripping */
746 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
749 ret = hns3_en_hw_strip_rxvtag(hns, enable);
751 rte_spinlock_unlock(&hw->lock);
752 hns3_err(hw, "failed to %s rx strip, ret = %d",
753 enable ? "enable" : "disable", ret);
758 rte_spinlock_unlock(&hw->lock);
764 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
765 struct hns3_tx_vtag_cfg *vcfg)
767 struct hns3_vport_vtag_tx_cfg_cmd *req;
768 struct hns3_cmd_desc desc;
769 struct hns3_hw *hw = &hns->hw;
774 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
776 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
777 req->def_vlan_tag1 = vcfg->default_tag1;
778 req->def_vlan_tag2 = vcfg->default_tag2;
779 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
780 vcfg->accept_tag1 ? 1 : 0);
781 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
782 vcfg->accept_untag1 ? 1 : 0);
783 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
784 vcfg->accept_tag2 ? 1 : 0);
785 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
786 vcfg->accept_untag2 ? 1 : 0);
787 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
788 vcfg->insert_tag1_en ? 1 : 0);
789 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
790 vcfg->insert_tag2_en ? 1 : 0);
791 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
793 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
794 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
795 vcfg->tag_shift_mode_en ? 1 : 0);
798 * In current version VF is not supported when PF is driven by DPDK
799 * driver, just need to configure parameters for PF vport.
801 vport_id = HNS3_PF_FUNC_ID;
802 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
803 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
804 req->vf_bitmap[req->vf_offset] = bitmap;
806 ret = hns3_cmd_send(hw, &desc, 1);
808 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
814 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
817 struct hns3_hw *hw = &hns->hw;
818 struct hns3_tx_vtag_cfg txvlan_cfg;
821 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
822 txvlan_cfg.accept_tag1 = true;
823 txvlan_cfg.insert_tag1_en = false;
824 txvlan_cfg.default_tag1 = 0;
826 txvlan_cfg.accept_tag1 =
827 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
828 txvlan_cfg.insert_tag1_en = true;
829 txvlan_cfg.default_tag1 = pvid;
832 txvlan_cfg.accept_untag1 = true;
833 txvlan_cfg.accept_tag2 = true;
834 txvlan_cfg.accept_untag2 = true;
835 txvlan_cfg.insert_tag2_en = false;
836 txvlan_cfg.default_tag2 = 0;
837 txvlan_cfg.tag_shift_mode_en = true;
839 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
841 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
846 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
852 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
854 struct hns3_user_vlan_table *vlan_entry;
855 struct hns3_pf *pf = &hns->pf;
857 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
858 if (vlan_entry->hd_tbl_status) {
859 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
860 vlan_entry->hd_tbl_status = false;
865 vlan_entry = LIST_FIRST(&pf->vlan_list);
867 LIST_REMOVE(vlan_entry, next);
868 rte_free(vlan_entry);
869 vlan_entry = LIST_FIRST(&pf->vlan_list);
875 hns3_add_all_vlan_table(struct hns3_adapter *hns)
877 struct hns3_user_vlan_table *vlan_entry;
878 struct hns3_pf *pf = &hns->pf;
880 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
881 if (!vlan_entry->hd_tbl_status) {
882 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
883 vlan_entry->hd_tbl_status = true;
889 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
891 struct hns3_hw *hw = &hns->hw;
894 hns3_rm_all_vlan_table(hns, true);
895 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
896 ret = hns3_set_port_vlan_filter(hns,
897 hw->port_base_vlan_cfg.pvid, 0);
899 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
907 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
908 uint16_t port_base_vlan_state, uint16_t new_pvid)
910 struct hns3_hw *hw = &hns->hw;
914 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
915 old_pvid = hw->port_base_vlan_cfg.pvid;
916 if (old_pvid != HNS3_INVALID_PVID) {
917 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
919 hns3_err(hw, "failed to remove old pvid %u, "
920 "ret = %d", old_pvid, ret);
925 hns3_rm_all_vlan_table(hns, false);
926 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
928 hns3_err(hw, "failed to add new pvid %u, ret = %d",
933 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
935 hns3_err(hw, "failed to remove pvid %u, ret = %d",
940 hns3_add_all_vlan_table(hns);
946 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
948 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
949 struct hns3_rx_vtag_cfg rx_vlan_cfg;
953 rx_strip_en = old_cfg->rx_vlan_offload_en;
955 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
956 rx_vlan_cfg.strip_tag2_en = true;
957 rx_vlan_cfg.strip_tag2_discard_en = true;
959 rx_vlan_cfg.strip_tag1_en = false;
960 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
961 rx_vlan_cfg.strip_tag2_discard_en = false;
963 rx_vlan_cfg.strip_tag1_discard_en = false;
964 rx_vlan_cfg.vlan1_vlan_prionly = false;
965 rx_vlan_cfg.vlan2_vlan_prionly = false;
966 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
968 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
972 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
977 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
979 struct hns3_hw *hw = &hns->hw;
980 uint16_t port_base_vlan_state;
983 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
984 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
985 hns3_warn(hw, "Invalid operation! As current pvid set "
986 "is %u, disable pvid %u is invalid",
987 hw->port_base_vlan_cfg.pvid, pvid);
991 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
992 HNS3_PORT_BASE_VLAN_DISABLE;
993 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
995 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
1000 ret = hns3_en_pvid_strip(hns, on);
1002 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1004 goto pvid_vlan_strip_fail;
1007 if (pvid == HNS3_INVALID_PVID)
1009 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1011 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1013 goto vlan_filter_set_fail;
1017 hw->port_base_vlan_cfg.state = port_base_vlan_state;
1018 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1021 vlan_filter_set_fail:
1022 err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1023 HNS3_PORT_BASE_VLAN_ENABLE);
1025 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1027 pvid_vlan_strip_fail:
1028 err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1029 hw->port_base_vlan_cfg.pvid);
1031 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1037 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1039 struct hns3_adapter *hns = dev->data->dev_private;
1040 struct hns3_hw *hw = &hns->hw;
1041 bool pvid_en_state_change;
1042 uint16_t pvid_state;
1045 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1046 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1047 RTE_ETHER_MAX_VLAN_ID);
1052 * If PVID configuration state change, should refresh the PVID
1053 * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1055 pvid_state = hw->port_base_vlan_cfg.state;
1056 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1057 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1058 pvid_en_state_change = false;
1060 pvid_en_state_change = true;
1062 rte_spinlock_lock(&hw->lock);
1063 ret = hns3_vlan_pvid_configure(hns, pvid, on);
1064 rte_spinlock_unlock(&hw->lock);
1068 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1069 * need be processed by PMD driver.
1071 if (pvid_en_state_change &&
1072 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1073 hns3_update_all_queues_pvid_proc_en(hw);
1079 hns3_default_vlan_config(struct hns3_adapter *hns)
1081 struct hns3_hw *hw = &hns->hw;
1085 * When vlan filter is enabled, hardware regards packets without vlan
1086 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1087 * table, packets without vlan won't be received. So, add vlan 0 as
1090 ret = hns3_vlan_filter_configure(hns, 0, 1);
1092 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1097 hns3_init_vlan_config(struct hns3_adapter *hns)
1099 struct hns3_hw *hw = &hns->hw;
1103 * This function can be called in the initialization and reset process,
1104 * when in reset process, it means that hardware had been reseted
1105 * successfully and we need to restore the hardware configuration to
1106 * ensure that the hardware configuration remains unchanged before and
1109 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1110 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1111 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1114 ret = hns3_vlan_filter_init(hns);
1116 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1120 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1121 RTE_ETHER_TYPE_VLAN);
1123 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1128 * When in the reinit dev stage of the reset process, the following
1129 * vlan-related configurations may differ from those at initialization,
1130 * we will restore configurations to hardware in hns3_restore_vlan_table
1131 * and hns3_restore_vlan_conf later.
1133 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1134 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1136 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1140 ret = hns3_en_hw_strip_rxvtag(hns, false);
1142 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1148 return hns3_default_vlan_config(hns);
1152 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1154 struct hns3_pf *pf = &hns->pf;
1155 struct hns3_hw *hw = &hns->hw;
1160 if (!hw->data->promiscuous) {
1161 /* restore vlan filter states */
1162 offloads = hw->data->dev_conf.rxmode.offloads;
1163 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1164 ret = hns3_enable_vlan_filter(hns, enable);
1166 hns3_err(hw, "failed to restore vlan rx filter conf, "
1172 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1174 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1178 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1180 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1186 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1188 struct hns3_adapter *hns = dev->data->dev_private;
1189 struct rte_eth_dev_data *data = dev->data;
1190 struct rte_eth_txmode *txmode;
1191 struct hns3_hw *hw = &hns->hw;
1195 txmode = &data->dev_conf.txmode;
1196 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1198 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1199 "configuration is not supported! Ignore these two "
1200 "parameters: hw_vlan_reject_tagged(%u), "
1201 "hw_vlan_reject_untagged(%u)",
1202 txmode->hw_vlan_reject_tagged,
1203 txmode->hw_vlan_reject_untagged);
1205 /* Apply vlan offload setting */
1206 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1207 ret = hns3_vlan_offload_set(dev, mask);
1209 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1215 * If pvid config is not set in rte_eth_conf, driver needn't to set
1216 * VLAN pvid related configuration to hardware.
1218 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1221 /* Apply pvid setting */
1222 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1223 txmode->hw_vlan_insert_pvid);
1225 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1232 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1233 unsigned int tso_mss_max)
1235 struct hns3_cfg_tso_status_cmd *req;
1236 struct hns3_cmd_desc desc;
1239 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1241 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1244 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1246 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1249 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1251 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1253 return hns3_cmd_send(hw, &desc, 1);
1257 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1258 uint16_t *allocated_size, bool is_alloc)
1260 struct hns3_umv_spc_alc_cmd *req;
1261 struct hns3_cmd_desc desc;
1264 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1265 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1266 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1267 req->space_size = rte_cpu_to_le_32(space_size);
1269 ret = hns3_cmd_send(hw, &desc, 1);
1271 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1272 is_alloc ? "allocate" : "free", ret);
1276 if (is_alloc && allocated_size)
1277 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1283 hns3_init_umv_space(struct hns3_hw *hw)
1285 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1286 struct hns3_pf *pf = &hns->pf;
1287 uint16_t allocated_size = 0;
1290 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1295 if (allocated_size < pf->wanted_umv_size)
1296 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1297 pf->wanted_umv_size, allocated_size);
1299 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1300 pf->wanted_umv_size;
1301 pf->used_umv_size = 0;
1306 hns3_uninit_umv_space(struct hns3_hw *hw)
1308 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1309 struct hns3_pf *pf = &hns->pf;
1312 if (pf->max_umv_size == 0)
1315 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1319 pf->max_umv_size = 0;
1325 hns3_is_umv_space_full(struct hns3_hw *hw)
1327 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1328 struct hns3_pf *pf = &hns->pf;
1331 is_full = (pf->used_umv_size >= pf->max_umv_size);
1337 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1339 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1340 struct hns3_pf *pf = &hns->pf;
1343 if (pf->used_umv_size > 0)
1344 pf->used_umv_size--;
1346 pf->used_umv_size++;
1350 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1351 const uint8_t *addr, bool is_mc)
1353 const unsigned char *mac_addr = addr;
1354 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1355 ((uint32_t)mac_addr[2] << 16) |
1356 ((uint32_t)mac_addr[1] << 8) |
1357 (uint32_t)mac_addr[0];
1358 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1360 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1362 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1363 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1364 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1367 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1368 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1372 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1374 enum hns3_mac_vlan_tbl_opcode op)
1377 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1382 if (op == HNS3_MAC_VLAN_ADD) {
1383 if (resp_code == 0 || resp_code == 1) {
1385 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1386 hns3_err(hw, "add mac addr failed for uc_overflow");
1388 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1389 hns3_err(hw, "add mac addr failed for mc_overflow");
1393 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1396 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1397 if (resp_code == 0) {
1399 } else if (resp_code == 1) {
1400 hns3_dbg(hw, "remove mac addr failed for miss");
1404 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1407 } else if (op == HNS3_MAC_VLAN_LKUP) {
1408 if (resp_code == 0) {
1410 } else if (resp_code == 1) {
1411 hns3_dbg(hw, "lookup mac addr failed for miss");
1415 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1420 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1427 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1428 struct hns3_mac_vlan_tbl_entry_cmd *req,
1429 struct hns3_cmd_desc *desc, bool is_mc)
1435 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1437 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1438 memcpy(desc[0].data, req,
1439 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1440 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1442 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1443 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1445 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1447 memcpy(desc[0].data, req,
1448 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1449 ret = hns3_cmd_send(hw, desc, 1);
1452 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1456 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1457 retval = rte_le_to_cpu_16(desc[0].retval);
1459 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1460 HNS3_MAC_VLAN_LKUP);
1464 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1465 struct hns3_mac_vlan_tbl_entry_cmd *req,
1466 struct hns3_cmd_desc *mc_desc)
1473 if (mc_desc == NULL) {
1474 struct hns3_cmd_desc desc;
1476 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1477 memcpy(desc.data, req,
1478 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1479 ret = hns3_cmd_send(hw, &desc, 1);
1480 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1481 retval = rte_le_to_cpu_16(desc.retval);
1483 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1486 hns3_cmd_reuse_desc(&mc_desc[0], false);
1487 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1488 hns3_cmd_reuse_desc(&mc_desc[1], false);
1489 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1490 hns3_cmd_reuse_desc(&mc_desc[2], false);
1491 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1492 memcpy(mc_desc[0].data, req,
1493 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1494 mc_desc[0].retval = 0;
1495 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1496 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1497 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1499 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1504 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1512 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1513 struct hns3_mac_vlan_tbl_entry_cmd *req)
1515 struct hns3_cmd_desc desc;
1520 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1522 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1524 ret = hns3_cmd_send(hw, &desc, 1);
1526 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1529 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1530 retval = rte_le_to_cpu_16(desc.retval);
1532 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1533 HNS3_MAC_VLAN_REMOVE);
1537 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1539 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1540 struct hns3_mac_vlan_tbl_entry_cmd req;
1541 struct hns3_pf *pf = &hns->pf;
1542 struct hns3_cmd_desc desc[3];
1543 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1544 uint16_t egress_port = 0;
1548 /* check if mac addr is valid */
1549 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1550 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1552 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1557 memset(&req, 0, sizeof(req));
1560 * In current version VF is not supported when PF is driven by DPDK
1561 * driver, just need to configure parameters for PF vport.
1563 vf_id = HNS3_PF_FUNC_ID;
1564 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1565 HNS3_MAC_EPORT_VFID_S, vf_id);
1567 req.egress_port = rte_cpu_to_le_16(egress_port);
1569 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1572 * Lookup the mac address in the mac_vlan table, and add
1573 * it if the entry is inexistent. Repeated unicast entry
1574 * is not allowed in the mac vlan table.
1576 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1577 if (ret == -ENOENT) {
1578 if (!hns3_is_umv_space_full(hw)) {
1579 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1581 hns3_update_umv_space(hw, false);
1585 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1590 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1592 /* check if we just hit the duplicate */
1594 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1598 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1605 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1607 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1608 struct rte_ether_addr *addr;
1612 for (i = 0; i < hw->mc_addrs_num; i++) {
1613 addr = &hw->mc_addrs[i];
1614 /* Check if there are duplicate addresses */
1615 if (rte_is_same_ether_addr(addr, mac_addr)) {
1616 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1618 hns3_err(hw, "failed to add mc mac addr, same addrs"
1619 "(%s) is added by the set_mc_mac_addr_list "
1625 ret = hns3_add_mc_addr(hw, mac_addr);
1627 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1629 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1636 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1638 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1641 ret = hns3_remove_mc_addr(hw, mac_addr);
1643 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1645 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1652 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1653 uint32_t idx, __rte_unused uint32_t pool)
1655 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1656 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1659 rte_spinlock_lock(&hw->lock);
1662 * In hns3 network engine adding UC and MC mac address with different
1663 * commands with firmware. We need to determine whether the input
1664 * address is a UC or a MC address to call different commands.
1665 * By the way, it is recommended calling the API function named
1666 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1667 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1668 * may affect the specifications of UC mac addresses.
1670 if (rte_is_multicast_ether_addr(mac_addr))
1671 ret = hns3_add_mc_addr_common(hw, mac_addr);
1673 ret = hns3_add_uc_addr_common(hw, mac_addr);
1676 rte_spinlock_unlock(&hw->lock);
1677 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1679 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1685 hw->mac.default_addr_setted = true;
1686 rte_spinlock_unlock(&hw->lock);
1692 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1694 struct hns3_mac_vlan_tbl_entry_cmd req;
1695 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1698 /* check if mac addr is valid */
1699 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1700 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1702 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1707 memset(&req, 0, sizeof(req));
1708 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1709 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1710 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1711 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1714 hns3_update_umv_space(hw, true);
1720 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1722 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1723 /* index will be checked by upper level rte interface */
1724 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1725 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1728 rte_spinlock_lock(&hw->lock);
1730 if (rte_is_multicast_ether_addr(mac_addr))
1731 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1733 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1734 rte_spinlock_unlock(&hw->lock);
1736 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1738 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1744 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1745 struct rte_ether_addr *mac_addr)
1747 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1748 struct rte_ether_addr *oaddr;
1749 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1750 bool default_addr_setted;
1751 bool rm_succes = false;
1755 * It has been guaranteed that input parameter named mac_addr is valid
1756 * address in the rte layer of DPDK framework.
1758 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1759 default_addr_setted = hw->mac.default_addr_setted;
1760 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1763 rte_spinlock_lock(&hw->lock);
1764 if (default_addr_setted) {
1765 ret = hns3_remove_uc_addr_common(hw, oaddr);
1767 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1769 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1776 ret = hns3_add_uc_addr_common(hw, mac_addr);
1778 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1780 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1781 goto err_add_uc_addr;
1784 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1786 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1787 goto err_pause_addr_cfg;
1790 rte_ether_addr_copy(mac_addr,
1791 (struct rte_ether_addr *)hw->mac.mac_addr);
1792 hw->mac.default_addr_setted = true;
1793 rte_spinlock_unlock(&hw->lock);
1798 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1800 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1803 "Failed to roll back to del setted mac addr(%s): %d",
1809 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1811 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1814 "Failed to restore old uc mac addr(%s): %d",
1816 hw->mac.default_addr_setted = false;
1819 rte_spinlock_unlock(&hw->lock);
1825 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1827 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1828 struct hns3_hw *hw = &hns->hw;
1829 struct rte_ether_addr *addr;
1834 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1835 addr = &hw->data->mac_addrs[i];
1836 if (rte_is_zero_ether_addr(addr))
1838 if (rte_is_multicast_ether_addr(addr))
1839 ret = del ? hns3_remove_mc_addr(hw, addr) :
1840 hns3_add_mc_addr(hw, addr);
1842 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1843 hns3_add_uc_addr_common(hw, addr);
1847 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1849 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1850 "ret = %d.", del ? "remove" : "restore",
1858 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1860 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1864 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1865 word_num = vfid / 32;
1866 bit_num = vfid % 32;
1868 desc[1].data[word_num] &=
1869 rte_cpu_to_le_32(~(1UL << bit_num));
1871 desc[1].data[word_num] |=
1872 rte_cpu_to_le_32(1UL << bit_num);
1874 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1875 bit_num = vfid % 32;
1877 desc[2].data[word_num] &=
1878 rte_cpu_to_le_32(~(1UL << bit_num));
1880 desc[2].data[word_num] |=
1881 rte_cpu_to_le_32(1UL << bit_num);
1886 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1888 struct hns3_mac_vlan_tbl_entry_cmd req;
1889 struct hns3_cmd_desc desc[3];
1890 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1894 /* Check if mac addr is valid */
1895 if (!rte_is_multicast_ether_addr(mac_addr)) {
1896 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1898 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1903 memset(&req, 0, sizeof(req));
1904 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1905 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1906 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1908 /* This mac addr do not exist, add new entry for it */
1909 memset(desc[0].data, 0, sizeof(desc[0].data));
1910 memset(desc[1].data, 0, sizeof(desc[0].data));
1911 memset(desc[2].data, 0, sizeof(desc[0].data));
1915 * In current version VF is not supported when PF is driven by DPDK
1916 * driver, just need to configure parameters for PF vport.
1918 vf_id = HNS3_PF_FUNC_ID;
1919 hns3_update_desc_vfid(desc, vf_id, false);
1920 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1923 hns3_err(hw, "mc mac vlan table is full");
1924 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1926 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1933 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1935 struct hns3_mac_vlan_tbl_entry_cmd req;
1936 struct hns3_cmd_desc desc[3];
1937 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1941 /* Check if mac addr is valid */
1942 if (!rte_is_multicast_ether_addr(mac_addr)) {
1943 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1945 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1950 memset(&req, 0, sizeof(req));
1951 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1952 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1953 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1956 * This mac addr exist, remove this handle's VFID for it.
1957 * In current version VF is not supported when PF is driven by
1958 * DPDK driver, just need to configure parameters for PF vport.
1960 vf_id = HNS3_PF_FUNC_ID;
1961 hns3_update_desc_vfid(desc, vf_id, true);
1963 /* All the vfid is zero, so need to delete this entry */
1964 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1965 } else if (ret == -ENOENT) {
1966 /* This mac addr doesn't exist. */
1971 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1973 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1980 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1981 struct rte_ether_addr *mc_addr_set,
1982 uint32_t nb_mc_addr)
1984 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1985 struct rte_ether_addr *addr;
1989 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1990 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1991 "invalid. valid range: 0~%d",
1992 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1996 /* Check if input mac addresses are valid */
1997 for (i = 0; i < nb_mc_addr; i++) {
1998 addr = &mc_addr_set[i];
1999 if (!rte_is_multicast_ether_addr(addr)) {
2000 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2003 "failed to set mc mac addr, addr(%s) invalid.",
2008 /* Check if there are duplicate addresses */
2009 for (j = i + 1; j < nb_mc_addr; j++) {
2010 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2011 hns3_ether_format_addr(mac_str,
2012 RTE_ETHER_ADDR_FMT_SIZE,
2014 hns3_err(hw, "failed to set mc mac addr, "
2015 "addrs invalid. two same addrs(%s).",
2022 * Check if there are duplicate addresses between mac_addrs
2025 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2026 if (rte_is_same_ether_addr(addr,
2027 &hw->data->mac_addrs[j])) {
2028 hns3_ether_format_addr(mac_str,
2029 RTE_ETHER_ADDR_FMT_SIZE,
2031 hns3_err(hw, "failed to set mc mac addr, "
2032 "addrs invalid. addrs(%s) has already "
2033 "configured in mac_addr add API",
2044 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2045 struct rte_ether_addr *mc_addr_set,
2047 struct rte_ether_addr *reserved_addr_list,
2048 int *reserved_addr_num,
2049 struct rte_ether_addr *add_addr_list,
2051 struct rte_ether_addr *rm_addr_list,
2054 struct rte_ether_addr *addr;
2055 int current_addr_num;
2056 int reserved_num = 0;
2064 /* Calculate the mc mac address list that should be removed */
2065 current_addr_num = hw->mc_addrs_num;
2066 for (i = 0; i < current_addr_num; i++) {
2067 addr = &hw->mc_addrs[i];
2069 for (j = 0; j < mc_addr_num; j++) {
2070 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2077 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2080 rte_ether_addr_copy(addr,
2081 &reserved_addr_list[reserved_num]);
2086 /* Calculate the mc mac address list that should be added */
2087 for (i = 0; i < mc_addr_num; i++) {
2088 addr = &mc_addr_set[i];
2090 for (j = 0; j < current_addr_num; j++) {
2091 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2098 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2103 /* Reorder the mc mac address list maintained by driver */
2104 for (i = 0; i < reserved_num; i++)
2105 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2107 for (i = 0; i < rm_num; i++) {
2108 num = reserved_num + i;
2109 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2112 *reserved_addr_num = reserved_num;
2113 *add_addr_num = add_num;
2114 *rm_addr_num = rm_num;
2118 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2119 struct rte_ether_addr *mc_addr_set,
2120 uint32_t nb_mc_addr)
2122 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2123 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2124 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2125 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2126 struct rte_ether_addr *addr;
2127 int reserved_addr_num;
2135 /* Check if input parameters are valid */
2136 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2140 rte_spinlock_lock(&hw->lock);
2143 * Calculate the mc mac address lists those should be removed and be
2144 * added, Reorder the mc mac address list maintained by driver.
2146 mc_addr_num = (int)nb_mc_addr;
2147 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2148 reserved_addr_list, &reserved_addr_num,
2149 add_addr_list, &add_addr_num,
2150 rm_addr_list, &rm_addr_num);
2152 /* Remove mc mac addresses */
2153 for (i = 0; i < rm_addr_num; i++) {
2154 num = rm_addr_num - i - 1;
2155 addr = &rm_addr_list[num];
2156 ret = hns3_remove_mc_addr(hw, addr);
2158 rte_spinlock_unlock(&hw->lock);
2164 /* Add mc mac addresses */
2165 for (i = 0; i < add_addr_num; i++) {
2166 addr = &add_addr_list[i];
2167 ret = hns3_add_mc_addr(hw, addr);
2169 rte_spinlock_unlock(&hw->lock);
2173 num = reserved_addr_num + i;
2174 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2177 rte_spinlock_unlock(&hw->lock);
2183 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2185 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2186 struct hns3_hw *hw = &hns->hw;
2187 struct rte_ether_addr *addr;
2192 for (i = 0; i < hw->mc_addrs_num; i++) {
2193 addr = &hw->mc_addrs[i];
2194 if (!rte_is_multicast_ether_addr(addr))
2197 ret = hns3_remove_mc_addr(hw, addr);
2199 ret = hns3_add_mc_addr(hw, addr);
2202 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2204 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2205 del ? "Remove" : "Restore", mac_str, ret);
2212 hns3_check_mq_mode(struct rte_eth_dev *dev)
2214 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2215 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2216 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2217 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2218 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2219 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2224 if ((rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG) ||
2225 (tx_mq_mode == ETH_MQ_TX_VMDQ_DCB ||
2226 tx_mq_mode == ETH_MQ_TX_VMDQ_ONLY)) {
2227 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
2228 rx_mq_mode, tx_mq_mode);
2232 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2233 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2234 if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
2235 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2236 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2237 dcb_rx_conf->nb_tcs, pf->tc_max);
2241 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2242 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2243 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2244 "nb_tcs(%d) != %d or %d in rx direction.",
2245 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2249 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2250 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2251 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2255 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2256 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2257 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2258 "is not equal to one in tx direction.",
2259 i, dcb_rx_conf->dcb_tc[i]);
2262 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2263 max_tc = dcb_rx_conf->dcb_tc[i];
2266 num_tc = max_tc + 1;
2267 if (num_tc > dcb_rx_conf->nb_tcs) {
2268 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2269 num_tc, dcb_rx_conf->nb_tcs);
2278 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2279 enum hns3_ring_type queue_type, uint16_t queue_id)
2281 struct hns3_cmd_desc desc;
2282 struct hns3_ctrl_vector_chain_cmd *req =
2283 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2284 enum hns3_opcode_type op;
2285 uint16_t tqp_type_and_id = 0;
2290 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2291 hns3_cmd_setup_basic_desc(&desc, op, false);
2292 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2293 HNS3_TQP_INT_ID_L_S);
2294 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2295 HNS3_TQP_INT_ID_H_S);
2297 if (queue_type == HNS3_RING_TYPE_RX)
2298 gl = HNS3_RING_GL_RX;
2300 gl = HNS3_RING_GL_TX;
2304 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2306 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2307 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2309 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2310 req->int_cause_num = 1;
2311 ret = hns3_cmd_send(hw, &desc, 1);
2313 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2314 en ? "Map" : "Unmap", queue_id, vector_id, ret);
2322 hns3_init_ring_with_vector(struct hns3_hw *hw)
2329 * In hns3 network engine, vector 0 is always the misc interrupt of this
2330 * function, vector 1~N can be used respectively for the queues of the
2331 * function. Tx and Rx queues with the same number share the interrupt
2332 * vector. In the initialization clearing the all hardware mapping
2333 * relationship configurations between queues and interrupt vectors is
2334 * needed, so some error caused by the residual configurations, such as
2335 * the unexpected Tx interrupt, can be avoid.
2337 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2338 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2339 vec = vec - 1; /* the last interrupt is reserved */
2340 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2341 for (i = 0; i < hw->intr_tqps_num; i++) {
2343 * Set gap limiter/rate limiter/quanity limiter algorithm
2344 * configuration for interrupt coalesce of queue's interrupt.
2346 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2347 HNS3_TQP_INTR_GL_DEFAULT);
2348 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2349 HNS3_TQP_INTR_GL_DEFAULT);
2350 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2352 * QL(quantity limiter) is not used currently, just set 0 to
2355 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2357 ret = hns3_bind_ring_with_vector(hw, vec, false,
2358 HNS3_RING_TYPE_TX, i);
2360 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2361 "vector: %u, ret=%d", i, vec, ret);
2365 ret = hns3_bind_ring_with_vector(hw, vec, false,
2366 HNS3_RING_TYPE_RX, i);
2368 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2369 "vector: %u, ret=%d", i, vec, ret);
2378 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2380 struct hns3_adapter *hns = dev->data->dev_private;
2381 struct hns3_hw *hw = &hns->hw;
2382 uint32_t max_rx_pkt_len;
2386 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2390 * If jumbo frames are enabled, MTU needs to be refreshed
2391 * according to the maximum RX packet length.
2393 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2394 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2395 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2396 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2397 "and no more than %u when jumbo frame enabled.",
2398 (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2399 (uint16_t)HNS3_MAX_FRAME_LEN);
2403 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2404 ret = hns3_dev_mtu_set(dev, mtu);
2407 dev->data->mtu = mtu;
2413 hns3_setup_dcb(struct rte_eth_dev *dev)
2415 struct hns3_adapter *hns = dev->data->dev_private;
2416 struct hns3_hw *hw = &hns->hw;
2419 if (!hns3_dev_dcb_supported(hw)) {
2420 hns3_err(hw, "this port does not support dcb configurations.");
2424 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2425 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2429 ret = hns3_dcb_configure(hns);
2431 hns3_err(hw, "failed to config dcb: %d", ret);
2437 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
2442 * Some hardware doesn't support auto-negotiation, but users may not
2443 * configure link_speeds (default 0), which means auto-negotiation.
2444 * In this case, a warning message need to be printed, instead of
2447 if (link_speeds == ETH_LINK_SPEED_AUTONEG &&
2448 hw->mac.support_autoneg == 0) {
2449 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
2453 if (link_speeds != ETH_LINK_SPEED_AUTONEG) {
2454 ret = hns3_check_port_speed(hw, link_speeds);
2463 hns3_check_dev_conf(struct rte_eth_dev *dev)
2465 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466 struct rte_eth_conf *conf = &dev->data->dev_conf;
2469 ret = hns3_check_mq_mode(dev);
2473 return hns3_check_link_speed(hw, conf->link_speeds);
2477 hns3_dev_configure(struct rte_eth_dev *dev)
2479 struct hns3_adapter *hns = dev->data->dev_private;
2480 struct rte_eth_conf *conf = &dev->data->dev_conf;
2481 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2482 struct hns3_hw *hw = &hns->hw;
2483 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2484 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2485 struct rte_eth_rss_conf rss_conf;
2489 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2492 * Some versions of hardware network engine does not support
2493 * individually enable/disable/reset the Tx or Rx queue. These devices
2494 * must enable/disable/reset Tx and Rx queues at the same time. When the
2495 * numbers of Tx queues allocated by upper applications are not equal to
2496 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2497 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2498 * work as usual. But these fake queues are imperceptible, and can not
2499 * be used by upper applications.
2501 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2503 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
2504 hw->cfg_max_queues = 0;
2508 hw->adapter_state = HNS3_NIC_CONFIGURING;
2509 ret = hns3_check_dev_conf(dev);
2513 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2514 ret = hns3_setup_dcb(dev);
2519 /* When RSS is not configured, redirect the packet queue 0 */
2520 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2521 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2522 rss_conf = conf->rx_adv_conf.rss_conf;
2523 hw->rss_dis_flag = false;
2524 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2529 ret = hns3_refresh_mtu(dev, conf);
2533 ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2537 ret = hns3_dev_configure_vlan(dev);
2541 /* config hardware GRO */
2542 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2543 ret = hns3_config_gro(hw, gro_en);
2547 hns3_init_rx_ptype_tble(dev);
2548 hw->adapter_state = HNS3_NIC_CONFIGURED;
2553 hw->cfg_max_queues = 0;
2554 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2555 hw->adapter_state = HNS3_NIC_INITIALIZED;
2561 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2563 struct hns3_config_max_frm_size_cmd *req;
2564 struct hns3_cmd_desc desc;
2566 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2568 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2569 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2570 req->min_frm_size = RTE_ETHER_MIN_LEN;
2572 return hns3_cmd_send(hw, &desc, 1);
2576 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2578 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2579 uint16_t original_mps = hns->pf.mps;
2583 ret = hns3_set_mac_mtu(hw, mps);
2585 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2590 ret = hns3_buffer_alloc(hw);
2592 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2599 err = hns3_set_mac_mtu(hw, original_mps);
2601 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2604 hns->pf.mps = original_mps;
2610 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2612 struct hns3_adapter *hns = dev->data->dev_private;
2613 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2614 struct hns3_hw *hw = &hns->hw;
2615 bool is_jumbo_frame;
2618 if (dev->data->dev_started) {
2619 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2620 "before configuration", dev->data->port_id);
2624 rte_spinlock_lock(&hw->lock);
2625 is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2626 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2629 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2630 * assign to "uint16_t" type variable.
2632 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2634 rte_spinlock_unlock(&hw->lock);
2635 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2636 dev->data->port_id, mtu, ret);
2641 dev->data->dev_conf.rxmode.offloads |=
2642 DEV_RX_OFFLOAD_JUMBO_FRAME;
2644 dev->data->dev_conf.rxmode.offloads &=
2645 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2646 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2647 rte_spinlock_unlock(&hw->lock);
2653 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2655 uint32_t speed_capa = 0;
2657 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2658 speed_capa |= ETH_LINK_SPEED_10M_HD;
2659 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2660 speed_capa |= ETH_LINK_SPEED_10M;
2661 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2662 speed_capa |= ETH_LINK_SPEED_100M_HD;
2663 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2664 speed_capa |= ETH_LINK_SPEED_100M;
2665 if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2666 speed_capa |= ETH_LINK_SPEED_1G;
2672 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2674 uint32_t speed_capa = 0;
2676 if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2677 speed_capa |= ETH_LINK_SPEED_1G;
2678 if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2679 speed_capa |= ETH_LINK_SPEED_10G;
2680 if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2681 speed_capa |= ETH_LINK_SPEED_25G;
2682 if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2683 speed_capa |= ETH_LINK_SPEED_40G;
2684 if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2685 speed_capa |= ETH_LINK_SPEED_50G;
2686 if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2687 speed_capa |= ETH_LINK_SPEED_100G;
2688 if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2689 speed_capa |= ETH_LINK_SPEED_200G;
2695 hns3_get_speed_capa(struct hns3_hw *hw)
2697 struct hns3_mac *mac = &hw->mac;
2698 uint32_t speed_capa;
2700 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2702 hns3_get_copper_port_speed_capa(mac->supported_speed);
2705 hns3_get_firber_port_speed_capa(mac->supported_speed);
2707 if (mac->support_autoneg == 0)
2708 speed_capa |= ETH_LINK_SPEED_FIXED;
2714 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2716 struct hns3_adapter *hns = eth_dev->data->dev_private;
2717 struct hns3_hw *hw = &hns->hw;
2718 uint16_t queue_num = hw->tqps_num;
2721 * In interrupt mode, 'max_rx_queues' is set based on the number of
2722 * MSI-X interrupt resources of the hardware.
2724 if (hw->data->dev_conf.intr_conf.rxq == 1)
2725 queue_num = hw->intr_tqps_num;
2727 info->max_rx_queues = queue_num;
2728 info->max_tx_queues = hw->tqps_num;
2729 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2730 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2731 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2732 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2733 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2734 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2735 DEV_RX_OFFLOAD_TCP_CKSUM |
2736 DEV_RX_OFFLOAD_UDP_CKSUM |
2737 DEV_RX_OFFLOAD_SCTP_CKSUM |
2738 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2739 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2740 DEV_RX_OFFLOAD_KEEP_CRC |
2741 DEV_RX_OFFLOAD_SCATTER |
2742 DEV_RX_OFFLOAD_VLAN_STRIP |
2743 DEV_RX_OFFLOAD_VLAN_FILTER |
2744 DEV_RX_OFFLOAD_JUMBO_FRAME |
2745 DEV_RX_OFFLOAD_RSS_HASH |
2746 DEV_RX_OFFLOAD_TCP_LRO);
2747 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2748 DEV_TX_OFFLOAD_IPV4_CKSUM |
2749 DEV_TX_OFFLOAD_TCP_CKSUM |
2750 DEV_TX_OFFLOAD_UDP_CKSUM |
2751 DEV_TX_OFFLOAD_SCTP_CKSUM |
2752 DEV_TX_OFFLOAD_MULTI_SEGS |
2753 DEV_TX_OFFLOAD_TCP_TSO |
2754 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2755 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2756 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2757 DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2758 hns3_txvlan_cap_get(hw));
2760 if (hns3_dev_outer_udp_cksum_supported(hw))
2761 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2763 if (hns3_dev_indep_txrx_supported(hw))
2764 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2765 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2767 if (hns3_dev_ptp_supported(hw))
2768 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2770 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2771 .nb_max = HNS3_MAX_RING_DESC,
2772 .nb_min = HNS3_MIN_RING_DESC,
2773 .nb_align = HNS3_ALIGN_RING_DESC,
2776 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2777 .nb_max = HNS3_MAX_RING_DESC,
2778 .nb_min = HNS3_MIN_RING_DESC,
2779 .nb_align = HNS3_ALIGN_RING_DESC,
2780 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2781 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2784 info->speed_capa = hns3_get_speed_capa(hw);
2785 info->default_rxconf = (struct rte_eth_rxconf) {
2786 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2788 * If there are no available Rx buffer descriptors, incoming
2789 * packets are always dropped by hardware based on hns3 network
2795 info->default_txconf = (struct rte_eth_txconf) {
2796 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2800 info->reta_size = hw->rss_ind_tbl_size;
2801 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2802 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2804 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2805 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2806 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2807 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2808 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2809 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2815 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2818 struct hns3_adapter *hns = eth_dev->data->dev_private;
2819 struct hns3_hw *hw = &hns->hw;
2820 uint32_t version = hw->fw_version;
2823 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2824 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2825 HNS3_FW_VERSION_BYTE3_S),
2826 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2827 HNS3_FW_VERSION_BYTE2_S),
2828 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2829 HNS3_FW_VERSION_BYTE1_S),
2830 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2831 HNS3_FW_VERSION_BYTE0_S));
2835 ret += 1; /* add the size of '\0' */
2836 if (fw_size < (size_t)ret)
2843 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2845 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2848 (void)hns3_update_link_status(hw);
2850 ret = hns3_update_link_info(eth_dev);
2852 hw->mac.link_status = ETH_LINK_DOWN;
2858 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2859 struct rte_eth_link *new_link)
2861 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2862 struct hns3_mac *mac = &hw->mac;
2864 switch (mac->link_speed) {
2865 case ETH_SPEED_NUM_10M:
2866 case ETH_SPEED_NUM_100M:
2867 case ETH_SPEED_NUM_1G:
2868 case ETH_SPEED_NUM_10G:
2869 case ETH_SPEED_NUM_25G:
2870 case ETH_SPEED_NUM_40G:
2871 case ETH_SPEED_NUM_50G:
2872 case ETH_SPEED_NUM_100G:
2873 case ETH_SPEED_NUM_200G:
2874 if (mac->link_status)
2875 new_link->link_speed = mac->link_speed;
2878 if (mac->link_status)
2879 new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2883 if (!mac->link_status)
2884 new_link->link_speed = ETH_SPEED_NUM_NONE;
2886 new_link->link_duplex = mac->link_duplex;
2887 new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2888 new_link->link_autoneg = mac->link_autoneg;
2892 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2894 #define HNS3_LINK_CHECK_INTERVAL 100 /* 100ms */
2895 #define HNS3_MAX_LINK_CHECK_TIMES 20 /* 2s (100 * 20ms) in total */
2897 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2898 uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2899 struct hns3_mac *mac = &hw->mac;
2900 struct rte_eth_link new_link;
2903 /* When port is stopped, report link down. */
2904 if (eth_dev->data->dev_started == 0) {
2905 new_link.link_autoneg = mac->link_autoneg;
2906 new_link.link_duplex = mac->link_duplex;
2907 new_link.link_speed = ETH_SPEED_NUM_NONE;
2908 new_link.link_status = ETH_LINK_DOWN;
2913 ret = hns3_update_port_link_info(eth_dev);
2915 hns3_err(hw, "failed to get port link info, ret = %d.",
2920 if (!wait_to_complete || mac->link_status == ETH_LINK_UP)
2923 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2924 } while (retry_cnt--);
2926 memset(&new_link, 0, sizeof(new_link));
2927 hns3_setup_linkstatus(eth_dev, &new_link);
2930 return rte_eth_linkstatus_set(eth_dev, &new_link);
2934 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2936 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2937 struct hns3_pf *pf = &hns->pf;
2939 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2942 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2948 hns3_query_function_status(struct hns3_hw *hw)
2950 #define HNS3_QUERY_MAX_CNT 10
2951 #define HNS3_QUERY_SLEEP_MSCOEND 1
2952 struct hns3_func_status_cmd *req;
2953 struct hns3_cmd_desc desc;
2957 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2958 req = (struct hns3_func_status_cmd *)desc.data;
2961 ret = hns3_cmd_send(hw, &desc, 1);
2963 PMD_INIT_LOG(ERR, "query function status failed %d",
2968 /* Check pf reset is done */
2972 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2973 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2975 return hns3_parse_func_status(hw, req);
2979 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2981 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2982 struct hns3_pf *pf = &hns->pf;
2984 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2986 * The total_tqps_num obtained from firmware is maximum tqp
2987 * numbers of this port, which should be used for PF and VFs.
2988 * There is no need for pf to have so many tqp numbers in
2989 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2990 * coming from config file, is assigned to maximum queue number
2991 * for the PF of this port by user. So users can modify the
2992 * maximum queue number of PF according to their own application
2993 * scenarios, which is more flexible to use. In addition, many
2994 * memories can be saved due to allocating queue statistics
2995 * room according to the actual number of queues required. The
2996 * maximum queue number of PF for network engine with
2997 * revision_id greater than 0x30 is assigned by config file.
2999 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
3000 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
3001 "must be greater than 0.",
3002 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
3006 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
3007 hw->total_tqps_num);
3010 * Due to the limitation on the number of PF interrupts
3011 * available, the maximum queue number assigned to PF on
3012 * the network engine with revision_id 0x21 is 64.
3014 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
3015 HNS3_MAX_TQP_NUM_HIP08_PF);
3022 hns3_query_pf_resource(struct hns3_hw *hw)
3024 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3025 struct hns3_pf *pf = &hns->pf;
3026 struct hns3_pf_res_cmd *req;
3027 struct hns3_cmd_desc desc;
3030 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
3031 ret = hns3_cmd_send(hw, &desc, 1);
3033 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
3037 req = (struct hns3_pf_res_cmd *)desc.data;
3038 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
3039 rte_le_to_cpu_16(req->ext_tqp_num);
3040 ret = hns3_get_pf_max_tqp_num(hw);
3044 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
3045 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
3047 if (req->tx_buf_size)
3049 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
3051 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
3053 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
3055 if (req->dv_buf_size)
3057 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3059 pf->dv_buf_size = HNS3_DEFAULT_DV;
3061 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3064 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3065 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3071 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3073 struct hns3_cfg_param_cmd *req;
3074 uint64_t mac_addr_tmp_high;
3075 uint8_t ext_rss_size_max;
3076 uint64_t mac_addr_tmp;
3079 req = (struct hns3_cfg_param_cmd *)desc[0].data;
3081 /* get the configuration */
3082 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3083 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3084 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3085 HNS3_CFG_TQP_DESC_N_M,
3086 HNS3_CFG_TQP_DESC_N_S);
3088 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3089 HNS3_CFG_PHY_ADDR_M,
3090 HNS3_CFG_PHY_ADDR_S);
3091 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3092 HNS3_CFG_MEDIA_TP_M,
3093 HNS3_CFG_MEDIA_TP_S);
3094 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3095 HNS3_CFG_RX_BUF_LEN_M,
3096 HNS3_CFG_RX_BUF_LEN_S);
3097 /* get mac address */
3098 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3099 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3100 HNS3_CFG_MAC_ADDR_H_M,
3101 HNS3_CFG_MAC_ADDR_H_S);
3103 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3105 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3106 HNS3_CFG_DEFAULT_SPEED_M,
3107 HNS3_CFG_DEFAULT_SPEED_S);
3108 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3109 HNS3_CFG_RSS_SIZE_M,
3110 HNS3_CFG_RSS_SIZE_S);
3112 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3113 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3115 req = (struct hns3_cfg_param_cmd *)desc[1].data;
3116 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3118 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3119 HNS3_CFG_SPEED_ABILITY_M,
3120 HNS3_CFG_SPEED_ABILITY_S);
3121 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3122 HNS3_CFG_UMV_TBL_SPACE_M,
3123 HNS3_CFG_UMV_TBL_SPACE_S);
3124 if (!cfg->umv_space)
3125 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3127 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3128 HNS3_CFG_EXT_RSS_SIZE_M,
3129 HNS3_CFG_EXT_RSS_SIZE_S);
3132 * Field ext_rss_size_max obtained from firmware will be more flexible
3133 * for future changes and expansions, which is an exponent of 2, instead
3134 * of reading out directly. If this field is not zero, hns3 PF PMD
3135 * driver uses it as rss_size_max under one TC. Device, whose revision
3136 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3137 * maximum number of queues supported under a TC through this field.
3139 if (ext_rss_size_max)
3140 cfg->rss_size_max = 1U << ext_rss_size_max;
3143 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3144 * @hw: pointer to struct hns3_hw
3145 * @hcfg: the config structure to be getted
3148 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3150 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3151 struct hns3_cfg_param_cmd *req;
3156 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3158 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3159 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3161 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3162 i * HNS3_CFG_RD_LEN_BYTES);
3163 /* Len should be divided by 4 when send to hardware */
3164 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3165 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3166 req->offset = rte_cpu_to_le_32(offset);
3169 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3171 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3175 hns3_parse_cfg(hcfg, desc);
3181 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3183 switch (speed_cmd) {
3184 case HNS3_CFG_SPEED_10M:
3185 *speed = ETH_SPEED_NUM_10M;
3187 case HNS3_CFG_SPEED_100M:
3188 *speed = ETH_SPEED_NUM_100M;
3190 case HNS3_CFG_SPEED_1G:
3191 *speed = ETH_SPEED_NUM_1G;
3193 case HNS3_CFG_SPEED_10G:
3194 *speed = ETH_SPEED_NUM_10G;
3196 case HNS3_CFG_SPEED_25G:
3197 *speed = ETH_SPEED_NUM_25G;
3199 case HNS3_CFG_SPEED_40G:
3200 *speed = ETH_SPEED_NUM_40G;
3202 case HNS3_CFG_SPEED_50G:
3203 *speed = ETH_SPEED_NUM_50G;
3205 case HNS3_CFG_SPEED_100G:
3206 *speed = ETH_SPEED_NUM_100G;
3208 case HNS3_CFG_SPEED_200G:
3209 *speed = ETH_SPEED_NUM_200G;
3219 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3221 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3222 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3223 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3224 hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3225 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3229 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3231 struct hns3_dev_specs_0_cmd *req0;
3233 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3235 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3236 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3237 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3238 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3239 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3243 hns3_check_dev_specifications(struct hns3_hw *hw)
3245 if (hw->rss_ind_tbl_size == 0 ||
3246 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3247 hns3_err(hw, "the size of hash lookup table configured (%u)"
3248 " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3249 HNS3_RSS_IND_TBL_SIZE_MAX);
3257 hns3_query_dev_specifications(struct hns3_hw *hw)
3259 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3263 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3264 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3266 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3268 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3270 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3274 hns3_parse_dev_specifications(hw, desc);
3276 return hns3_check_dev_specifications(hw);
3280 hns3_get_capability(struct hns3_hw *hw)
3282 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3283 struct rte_pci_device *pci_dev;
3284 struct hns3_pf *pf = &hns->pf;
3285 struct rte_eth_dev *eth_dev;
3290 eth_dev = &rte_eth_devices[hw->data->port_id];
3291 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3292 device_id = pci_dev->id.device_id;
3294 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3295 device_id == HNS3_DEV_ID_50GE_RDMA ||
3296 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3297 device_id == HNS3_DEV_ID_200G_RDMA)
3298 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3300 /* Get PCI revision id */
3301 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3302 HNS3_PCI_REVISION_ID);
3303 if (ret != HNS3_PCI_REVISION_ID_LEN) {
3304 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3308 hw->revision = revision;
3310 if (revision < PCI_REVISION_ID_HIP09_A) {
3311 hns3_set_default_dev_specifications(hw);
3312 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3313 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3314 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3315 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3316 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3317 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3318 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3319 hw->rss_info.ipv6_sctp_offload_supported = false;
3320 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3324 ret = hns3_query_dev_specifications(hw);
3327 "failed to query dev specifications, ret = %d",
3332 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3333 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3334 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3335 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3336 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3337 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3338 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3339 hw->rss_info.ipv6_sctp_offload_supported = true;
3340 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3346 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3350 switch (media_type) {
3351 case HNS3_MEDIA_TYPE_COPPER:
3352 if (!hns3_dev_copper_supported(hw)) {
3354 "Media type is copper, not supported.");
3360 case HNS3_MEDIA_TYPE_FIBER:
3363 case HNS3_MEDIA_TYPE_BACKPLANE:
3364 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3368 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3377 hns3_get_board_configuration(struct hns3_hw *hw)
3379 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3380 struct hns3_pf *pf = &hns->pf;
3381 struct hns3_cfg cfg;
3384 ret = hns3_get_board_cfg(hw, &cfg);
3386 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3390 ret = hns3_check_media_type(hw, cfg.media_type);
3394 hw->mac.media_type = cfg.media_type;
3395 hw->rss_size_max = cfg.rss_size_max;
3396 hw->rss_dis_flag = false;
3397 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3398 hw->mac.phy_addr = cfg.phy_addr;
3399 hw->mac.default_addr_setted = false;
3400 hw->num_tx_desc = cfg.tqp_desc_num;
3401 hw->num_rx_desc = cfg.tqp_desc_num;
3402 hw->dcb_info.num_pg = 1;
3403 hw->dcb_info.hw_pfc_map = 0;
3405 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3407 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3408 cfg.default_speed, ret);
3412 pf->tc_max = cfg.tc_num;
3413 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3414 PMD_INIT_LOG(WARNING,
3415 "Get TC num(%u) from flash, set TC num to 1",
3420 /* Dev does not support DCB */
3421 if (!hns3_dev_dcb_supported(hw)) {
3425 pf->pfc_max = pf->tc_max;
3427 hw->dcb_info.num_tc = 1;
3428 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3429 hw->tqps_num / hw->dcb_info.num_tc);
3430 hns3_set_bit(hw->hw_tc_map, 0, 1);
3431 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3433 pf->wanted_umv_size = cfg.umv_space;
3439 hns3_get_configuration(struct hns3_hw *hw)
3443 ret = hns3_query_function_status(hw);
3445 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3449 /* Get device capability */
3450 ret = hns3_get_capability(hw);
3452 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3456 /* Get pf resource */
3457 ret = hns3_query_pf_resource(hw);
3459 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3463 ret = hns3_get_board_configuration(hw);
3465 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3469 ret = hns3_query_dev_fec_info(hw);
3472 "failed to query FEC information, ret = %d", ret);
3478 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3479 uint16_t tqp_vid, bool is_pf)
3481 struct hns3_tqp_map_cmd *req;
3482 struct hns3_cmd_desc desc;
3485 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3487 req = (struct hns3_tqp_map_cmd *)desc.data;
3488 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3489 req->tqp_vf = func_id;
3490 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3492 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3493 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3495 ret = hns3_cmd_send(hw, &desc, 1);
3497 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3503 hns3_map_tqp(struct hns3_hw *hw)
3509 * In current version, VF is not supported when PF is driven by DPDK
3510 * driver, so we assign total tqps_num tqps allocated to this port
3513 for (i = 0; i < hw->total_tqps_num; i++) {
3514 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3523 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3525 struct hns3_config_mac_speed_dup_cmd *req;
3526 struct hns3_cmd_desc desc;
3529 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3531 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3533 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3536 case ETH_SPEED_NUM_10M:
3537 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3538 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3540 case ETH_SPEED_NUM_100M:
3541 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3542 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3544 case ETH_SPEED_NUM_1G:
3545 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3546 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3548 case ETH_SPEED_NUM_10G:
3549 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3550 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3552 case ETH_SPEED_NUM_25G:
3553 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3554 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3556 case ETH_SPEED_NUM_40G:
3557 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3558 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3560 case ETH_SPEED_NUM_50G:
3561 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3562 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3564 case ETH_SPEED_NUM_100G:
3565 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3566 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3568 case ETH_SPEED_NUM_200G:
3569 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3570 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3573 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3577 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3579 ret = hns3_cmd_send(hw, &desc, 1);
3581 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3587 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3589 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3590 struct hns3_pf *pf = &hns->pf;
3591 struct hns3_priv_buf *priv;
3592 uint32_t i, total_size;
3594 total_size = pf->pkt_buf_size;
3596 /* alloc tx buffer for all enabled tc */
3597 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3598 priv = &buf_alloc->priv_buf[i];
3600 if (hw->hw_tc_map & BIT(i)) {
3601 if (total_size < pf->tx_buf_size)
3604 priv->tx_buf_size = pf->tx_buf_size;
3606 priv->tx_buf_size = 0;
3608 total_size -= priv->tx_buf_size;
3615 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3617 /* TX buffer size is unit by 128 byte */
3618 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3619 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3620 struct hns3_tx_buff_alloc_cmd *req;
3621 struct hns3_cmd_desc desc;
3626 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3628 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3629 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3630 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3632 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3633 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3634 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3637 ret = hns3_cmd_send(hw, &desc, 1);
3639 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3645 hns3_get_tc_num(struct hns3_hw *hw)
3650 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3651 if (hw->hw_tc_map & BIT(i))
3657 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3659 struct hns3_priv_buf *priv;
3660 uint32_t rx_priv = 0;
3663 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3664 priv = &buf_alloc->priv_buf[i];
3666 rx_priv += priv->buf_size;
3672 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3674 uint32_t total_tx_size = 0;
3677 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3678 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3680 return total_tx_size;
3683 /* Get the number of pfc enabled TCs, which have private buffer */
3685 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3687 struct hns3_priv_buf *priv;
3691 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3692 priv = &buf_alloc->priv_buf[i];
3693 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3700 /* Get the number of pfc disabled TCs, which have private buffer */
3702 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3703 struct hns3_pkt_buf_alloc *buf_alloc)
3705 struct hns3_priv_buf *priv;
3709 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3710 priv = &buf_alloc->priv_buf[i];
3711 if (hw->hw_tc_map & BIT(i) &&
3712 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3720 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3723 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3724 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3725 struct hns3_pf *pf = &hns->pf;
3726 uint32_t shared_buf, aligned_mps;
3731 tc_num = hns3_get_tc_num(hw);
3732 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3734 if (hns3_dev_dcb_supported(hw))
3735 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3738 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3741 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3742 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3743 HNS3_BUF_SIZE_UNIT);
3745 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3746 if (rx_all < rx_priv + shared_std)
3749 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3750 buf_alloc->s_buf.buf_size = shared_buf;
3751 if (hns3_dev_dcb_supported(hw)) {
3752 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3753 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3754 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3755 HNS3_BUF_SIZE_UNIT);
3757 buf_alloc->s_buf.self.high =
3758 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3759 buf_alloc->s_buf.self.low = aligned_mps;
3762 if (hns3_dev_dcb_supported(hw)) {
3763 hi_thrd = shared_buf - pf->dv_buf_size;
3765 if (tc_num <= NEED_RESERVE_TC_NUM)
3766 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3770 hi_thrd = hi_thrd / tc_num;
3772 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3773 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3774 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3776 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3777 lo_thrd = aligned_mps;
3780 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3781 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3782 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3789 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3790 struct hns3_pkt_buf_alloc *buf_alloc)
3792 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3793 struct hns3_pf *pf = &hns->pf;
3794 struct hns3_priv_buf *priv;
3795 uint32_t aligned_mps;
3799 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3800 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3802 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3803 priv = &buf_alloc->priv_buf[i];
3810 if (!(hw->hw_tc_map & BIT(i)))
3814 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3815 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3816 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3817 HNS3_BUF_SIZE_UNIT);
3820 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3824 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3827 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3831 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3832 struct hns3_pkt_buf_alloc *buf_alloc)
3834 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3835 struct hns3_pf *pf = &hns->pf;
3836 struct hns3_priv_buf *priv;
3837 int no_pfc_priv_num;
3842 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3843 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3845 /* let the last to be cleared first */
3846 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3847 priv = &buf_alloc->priv_buf[i];
3848 mask = BIT((uint8_t)i);
3850 if (hw->hw_tc_map & mask &&
3851 !(hw->dcb_info.hw_pfc_map & mask)) {
3852 /* Clear the no pfc TC private buffer */
3860 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3861 no_pfc_priv_num == 0)
3865 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3869 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3870 struct hns3_pkt_buf_alloc *buf_alloc)
3872 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3873 struct hns3_pf *pf = &hns->pf;
3874 struct hns3_priv_buf *priv;
3880 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3881 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3883 /* let the last to be cleared first */
3884 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3885 priv = &buf_alloc->priv_buf[i];
3886 mask = BIT((uint8_t)i);
3887 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3888 /* Reduce the number of pfc TC with private buffer */
3895 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3900 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3904 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3905 struct hns3_pkt_buf_alloc *buf_alloc)
3907 #define COMPENSATE_BUFFER 0x3C00
3908 #define COMPENSATE_HALF_MPS_NUM 5
3909 #define PRIV_WL_GAP 0x1800
3910 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3911 struct hns3_pf *pf = &hns->pf;
3912 uint32_t tc_num = hns3_get_tc_num(hw);
3913 uint32_t half_mps = pf->mps >> 1;
3914 struct hns3_priv_buf *priv;
3915 uint32_t min_rx_priv;
3919 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3921 rx_priv = rx_priv / tc_num;
3923 if (tc_num <= NEED_RESERVE_TC_NUM)
3924 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3927 * Minimum value of private buffer in rx direction (min_rx_priv) is
3928 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3929 * buffer if rx_priv is greater than min_rx_priv.
3931 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3932 COMPENSATE_HALF_MPS_NUM * half_mps;
3933 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3934 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3936 if (rx_priv < min_rx_priv)
3939 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3940 priv = &buf_alloc->priv_buf[i];
3946 if (!(hw->hw_tc_map & BIT(i)))
3950 priv->buf_size = rx_priv;
3951 priv->wl.high = rx_priv - pf->dv_buf_size;
3952 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3955 buf_alloc->s_buf.buf_size = 0;
3961 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3962 * @hw: pointer to struct hns3_hw
3963 * @buf_alloc: pointer to buffer calculation data
3964 * @return: 0: calculate sucessful, negative: fail
3967 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3969 /* When DCB is not supported, rx private buffer is not allocated. */
3970 if (!hns3_dev_dcb_supported(hw)) {
3971 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3972 struct hns3_pf *pf = &hns->pf;
3973 uint32_t rx_all = pf->pkt_buf_size;
3975 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3976 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3983 * Try to allocate privated packet buffer for all TCs without share
3986 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3990 * Try to allocate privated packet buffer for all TCs with share
3993 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3997 * For different application scenes, the enabled port number, TC number
3998 * and no_drop TC number are different. In order to obtain the better
3999 * performance, software could allocate the buffer size and configure
4000 * the waterline by trying to decrease the private buffer size according
4001 * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
4004 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
4007 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
4010 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
4017 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4019 struct hns3_rx_priv_buff_cmd *req;
4020 struct hns3_cmd_desc desc;
4025 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
4026 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
4028 /* Alloc private buffer TCs */
4029 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4030 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
4033 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
4034 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
4037 buf_size = buf_alloc->s_buf.buf_size;
4038 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
4039 (1 << HNS3_TC0_PRI_BUF_EN_B));
4041 ret = hns3_cmd_send(hw, &desc, 1);
4043 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
4049 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4051 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
4052 struct hns3_rx_priv_wl_buf *req;
4053 struct hns3_priv_buf *priv;
4054 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4058 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4059 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4061 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4063 /* The first descriptor set the NEXT bit to 1 */
4065 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4067 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4069 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4070 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4072 priv = &buf_alloc->priv_buf[idx];
4073 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4075 req->tc_wl[j].high |=
4076 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4077 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4079 req->tc_wl[j].low |=
4080 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4084 /* Send 2 descriptor at one time */
4085 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4087 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4093 hns3_common_thrd_config(struct hns3_hw *hw,
4094 struct hns3_pkt_buf_alloc *buf_alloc)
4096 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4097 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4098 struct hns3_rx_com_thrd *req;
4099 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4100 struct hns3_tc_thrd *tc;
4105 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4106 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4108 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4110 /* The first descriptor set the NEXT bit to 1 */
4112 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4114 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4116 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4117 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4118 tc = &s_buf->tc_thrd[tc_idx];
4120 req->com_thrd[j].high =
4121 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4122 req->com_thrd[j].high |=
4123 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4124 req->com_thrd[j].low =
4125 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4126 req->com_thrd[j].low |=
4127 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4131 /* Send 2 descriptors at one time */
4132 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4134 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4140 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4142 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4143 struct hns3_rx_com_wl *req;
4144 struct hns3_cmd_desc desc;
4147 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4149 req = (struct hns3_rx_com_wl *)desc.data;
4150 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4151 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4153 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4154 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4156 ret = hns3_cmd_send(hw, &desc, 1);
4158 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4164 hns3_buffer_alloc(struct hns3_hw *hw)
4166 struct hns3_pkt_buf_alloc pkt_buf;
4169 memset(&pkt_buf, 0, sizeof(pkt_buf));
4170 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4173 "could not calc tx buffer size for all TCs %d",
4178 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4180 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4184 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4187 "could not calc rx priv buffer size for all TCs %d",
4192 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4194 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4198 if (hns3_dev_dcb_supported(hw)) {
4199 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4202 "could not configure rx private waterline %d",
4207 ret = hns3_common_thrd_config(hw, &pkt_buf);
4210 "could not configure common threshold %d",
4216 ret = hns3_common_wl_config(hw, &pkt_buf);
4218 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4225 hns3_mac_init(struct hns3_hw *hw)
4227 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4228 struct hns3_mac *mac = &hw->mac;
4229 struct hns3_pf *pf = &hns->pf;
4232 pf->support_sfp_query = true;
4233 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4234 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4236 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4240 mac->link_status = ETH_LINK_DOWN;
4242 return hns3_config_mtu(hw, pf->mps);
4246 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4248 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
4249 #define HNS3_ETHERTYPE_ALREADY_ADD 1
4250 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
4251 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
4256 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4261 switch (resp_code) {
4262 case HNS3_ETHERTYPE_SUCCESS_ADD:
4263 case HNS3_ETHERTYPE_ALREADY_ADD:
4266 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4268 "add mac ethertype failed for manager table overflow.");
4269 return_status = -EIO;
4271 case HNS3_ETHERTYPE_KEY_CONFLICT:
4272 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4273 return_status = -EIO;
4277 "add mac ethertype failed for undefined, code=%u.",
4279 return_status = -EIO;
4283 return return_status;
4287 hns3_add_mgr_tbl(struct hns3_hw *hw,
4288 const struct hns3_mac_mgr_tbl_entry_cmd *req)
4290 struct hns3_cmd_desc desc;
4295 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4296 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4298 ret = hns3_cmd_send(hw, &desc, 1);
4301 "add mac ethertype failed for cmd_send, ret =%d.",
4306 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4307 retval = rte_le_to_cpu_16(desc.retval);
4309 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4313 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4314 int *table_item_num)
4316 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4319 * In current version, we add one item in management table as below:
4320 * 0x0180C200000E -- LLDP MC address
4323 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4324 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4325 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4326 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4327 tbl->i_port_bitmap = 0x1;
4328 *table_item_num = 1;
4332 hns3_init_mgr_tbl(struct hns3_hw *hw)
4334 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
4335 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4340 memset(mgr_table, 0, sizeof(mgr_table));
4341 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4342 for (i = 0; i < table_item_num; i++) {
4343 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4345 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4355 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4356 bool en_mc, bool en_bc, int vport_id)
4361 memset(param, 0, sizeof(struct hns3_promisc_param));
4363 param->enable = HNS3_PROMISC_EN_UC;
4365 param->enable |= HNS3_PROMISC_EN_MC;
4367 param->enable |= HNS3_PROMISC_EN_BC;
4368 param->vf_id = vport_id;
4372 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4374 struct hns3_promisc_cfg_cmd *req;
4375 struct hns3_cmd_desc desc;
4378 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4380 req = (struct hns3_promisc_cfg_cmd *)desc.data;
4381 req->vf_id = param->vf_id;
4382 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4383 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4385 ret = hns3_cmd_send(hw, &desc, 1);
4387 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4393 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4395 struct hns3_promisc_param param;
4396 bool en_bc_pmc = true;
4400 * In current version VF is not supported when PF is driven by DPDK
4401 * driver, just need to configure parameters for PF vport.
4403 vf_id = HNS3_PF_FUNC_ID;
4405 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4406 return hns3_cmd_set_promisc_mode(hw, ¶m);
4410 hns3_promisc_init(struct hns3_hw *hw)
4412 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4413 struct hns3_pf *pf = &hns->pf;
4414 struct hns3_promisc_param param;
4418 ret = hns3_set_promisc_mode(hw, false, false);
4420 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4425 * In current version VFs are not supported when PF is driven by DPDK
4426 * driver. After PF has been taken over by DPDK, the original VF will
4427 * be invalid. So, there is a possibility of entry residues. It should
4428 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4431 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4432 hns3_promisc_param_init(¶m, false, false, false, func_id);
4433 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4435 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4436 " ret = %d", func_id, ret);
4445 hns3_promisc_uninit(struct hns3_hw *hw)
4447 struct hns3_promisc_param param;
4451 func_id = HNS3_PF_FUNC_ID;
4454 * In current version VFs are not supported when PF is driven by
4455 * DPDK driver, and VFs' promisc mode status has been cleared during
4456 * init and their status will not change. So just clear PF's promisc
4457 * mode status during uninit.
4459 hns3_promisc_param_init(¶m, false, false, false, func_id);
4460 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4462 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4463 " uninit, ret = %d", ret);
4467 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4469 bool allmulti = dev->data->all_multicast ? true : false;
4470 struct hns3_adapter *hns = dev->data->dev_private;
4471 struct hns3_hw *hw = &hns->hw;
4476 rte_spinlock_lock(&hw->lock);
4477 ret = hns3_set_promisc_mode(hw, true, true);
4479 rte_spinlock_unlock(&hw->lock);
4480 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4486 * When promiscuous mode was enabled, disable the vlan filter to let
4487 * all packets coming in in the receiving direction.
4489 offloads = dev->data->dev_conf.rxmode.offloads;
4490 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4491 ret = hns3_enable_vlan_filter(hns, false);
4493 hns3_err(hw, "failed to enable promiscuous mode due to "
4494 "failure to disable vlan filter, ret = %d",
4496 err = hns3_set_promisc_mode(hw, false, allmulti);
4498 hns3_err(hw, "failed to restore promiscuous "
4499 "status after disable vlan filter "
4500 "failed during enabling promiscuous "
4501 "mode, ret = %d", ret);
4505 rte_spinlock_unlock(&hw->lock);
4511 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4513 bool allmulti = dev->data->all_multicast ? true : false;
4514 struct hns3_adapter *hns = dev->data->dev_private;
4515 struct hns3_hw *hw = &hns->hw;
4520 /* If now in all_multicast mode, must remain in all_multicast mode. */
4521 rte_spinlock_lock(&hw->lock);
4522 ret = hns3_set_promisc_mode(hw, false, allmulti);
4524 rte_spinlock_unlock(&hw->lock);
4525 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4529 /* when promiscuous mode was disabled, restore the vlan filter status */
4530 offloads = dev->data->dev_conf.rxmode.offloads;
4531 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4532 ret = hns3_enable_vlan_filter(hns, true);
4534 hns3_err(hw, "failed to disable promiscuous mode due to"
4535 " failure to restore vlan filter, ret = %d",
4537 err = hns3_set_promisc_mode(hw, true, true);
4539 hns3_err(hw, "failed to restore promiscuous "
4540 "status after enabling vlan filter "
4541 "failed during disabling promiscuous "
4542 "mode, ret = %d", ret);
4545 rte_spinlock_unlock(&hw->lock);
4551 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4553 struct hns3_adapter *hns = dev->data->dev_private;
4554 struct hns3_hw *hw = &hns->hw;
4557 if (dev->data->promiscuous)
4560 rte_spinlock_lock(&hw->lock);
4561 ret = hns3_set_promisc_mode(hw, false, true);
4562 rte_spinlock_unlock(&hw->lock);
4564 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4571 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4573 struct hns3_adapter *hns = dev->data->dev_private;
4574 struct hns3_hw *hw = &hns->hw;
4577 /* If now in promiscuous mode, must remain in all_multicast mode. */
4578 if (dev->data->promiscuous)
4581 rte_spinlock_lock(&hw->lock);
4582 ret = hns3_set_promisc_mode(hw, false, false);
4583 rte_spinlock_unlock(&hw->lock);
4585 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4592 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4594 struct hns3_hw *hw = &hns->hw;
4595 bool allmulti = hw->data->all_multicast ? true : false;
4598 if (hw->data->promiscuous) {
4599 ret = hns3_set_promisc_mode(hw, true, true);
4601 hns3_err(hw, "failed to restore promiscuous mode, "
4606 ret = hns3_set_promisc_mode(hw, false, allmulti);
4608 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4614 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4616 struct hns3_sfp_info_cmd *resp;
4617 struct hns3_cmd_desc desc;
4620 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4621 resp = (struct hns3_sfp_info_cmd *)desc.data;
4622 resp->query_type = HNS3_ACTIVE_QUERY;
4624 ret = hns3_cmd_send(hw, &desc, 1);
4625 if (ret == -EOPNOTSUPP) {
4626 hns3_warn(hw, "firmware does not support get SFP info,"
4630 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4635 * In some case, the speed of MAC obtained from firmware may be 0, it
4636 * shouldn't be set to mac->speed.
4638 if (!rte_le_to_cpu_32(resp->sfp_speed))
4641 mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4643 * if resp->supported_speed is 0, it means it's an old version
4644 * firmware, do not update these params.
4646 if (resp->supported_speed) {
4647 mac_info->query_type = HNS3_ACTIVE_QUERY;
4648 mac_info->supported_speed =
4649 rte_le_to_cpu_32(resp->supported_speed);
4650 mac_info->support_autoneg = resp->autoneg_ability;
4651 mac_info->link_autoneg = (resp->autoneg == 0) ? ETH_LINK_FIXED
4654 mac_info->query_type = HNS3_DEFAULT_QUERY;
4661 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4663 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4664 duplex = ETH_LINK_FULL_DUPLEX;
4670 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4672 struct hns3_mac *mac = &hw->mac;
4675 duplex = hns3_check_speed_dup(duplex, speed);
4676 if (mac->link_speed == speed && mac->link_duplex == duplex)
4679 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4683 ret = hns3_port_shaper_update(hw, speed);
4687 mac->link_speed = speed;
4688 mac->link_duplex = duplex;
4694 hns3_update_fiber_link_info(struct hns3_hw *hw)
4696 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4697 struct hns3_mac *mac = &hw->mac;
4698 struct hns3_mac mac_info;
4701 /* If firmware do not support get SFP/qSFP speed, return directly */
4702 if (!pf->support_sfp_query)
4705 memset(&mac_info, 0, sizeof(struct hns3_mac));
4706 ret = hns3_get_sfp_info(hw, &mac_info);
4707 if (ret == -EOPNOTSUPP) {
4708 pf->support_sfp_query = false;
4713 /* Do nothing if no SFP */
4714 if (mac_info.link_speed == ETH_SPEED_NUM_NONE)
4718 * If query_type is HNS3_ACTIVE_QUERY, it is no need
4719 * to reconfigure the speed of MAC. Otherwise, it indicates
4720 * that the current firmware only supports to obtain the
4721 * speed of the SFP, and the speed of MAC needs to reconfigure.
4723 mac->query_type = mac_info.query_type;
4724 if (mac->query_type == HNS3_ACTIVE_QUERY) {
4725 if (mac_info.link_speed != mac->link_speed) {
4726 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4731 mac->link_speed = mac_info.link_speed;
4732 mac->supported_speed = mac_info.supported_speed;
4733 mac->support_autoneg = mac_info.support_autoneg;
4734 mac->link_autoneg = mac_info.link_autoneg;
4739 /* Config full duplex for SFP */
4740 return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4741 ETH_LINK_FULL_DUPLEX);
4745 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4747 #define HNS3_PHY_SUPPORTED_SPEED_MASK 0x2f
4749 struct hns3_phy_params_bd0_cmd *req;
4752 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4753 mac->link_speed = rte_le_to_cpu_32(req->speed);
4754 mac->link_duplex = hns3_get_bit(req->duplex,
4755 HNS3_PHY_DUPLEX_CFG_B);
4756 mac->link_autoneg = hns3_get_bit(req->autoneg,
4757 HNS3_PHY_AUTONEG_CFG_B);
4758 mac->advertising = rte_le_to_cpu_32(req->advertising);
4759 mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4760 supported = rte_le_to_cpu_32(req->supported);
4761 mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4762 mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4766 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4768 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4772 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4773 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4775 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4777 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4779 ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4781 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4785 hns3_parse_copper_phy_params(desc, mac);
4791 hns3_update_copper_link_info(struct hns3_hw *hw)
4793 struct hns3_mac *mac = &hw->mac;
4794 struct hns3_mac mac_info;
4797 memset(&mac_info, 0, sizeof(struct hns3_mac));
4798 ret = hns3_get_copper_phy_params(hw, &mac_info);
4802 if (mac_info.link_speed != mac->link_speed) {
4803 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4808 mac->link_speed = mac_info.link_speed;
4809 mac->link_duplex = mac_info.link_duplex;
4810 mac->link_autoneg = mac_info.link_autoneg;
4811 mac->supported_speed = mac_info.supported_speed;
4812 mac->advertising = mac_info.advertising;
4813 mac->lp_advertising = mac_info.lp_advertising;
4814 mac->support_autoneg = mac_info.support_autoneg;
4820 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4822 struct hns3_adapter *hns = eth_dev->data->dev_private;
4823 struct hns3_hw *hw = &hns->hw;
4826 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4827 ret = hns3_update_copper_link_info(hw);
4828 else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4829 ret = hns3_update_fiber_link_info(hw);
4835 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4837 struct hns3_config_mac_mode_cmd *req;
4838 struct hns3_cmd_desc desc;
4839 uint32_t loop_en = 0;
4843 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4845 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4848 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4849 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4850 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4851 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4852 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4853 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4854 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4855 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4856 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4857 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4860 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4861 * when receiving frames. Otherwise, CRC will be stripped.
4863 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4864 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4866 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4867 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4868 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4869 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4870 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4872 ret = hns3_cmd_send(hw, &desc, 1);
4874 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4880 hns3_get_mac_link_status(struct hns3_hw *hw)
4882 struct hns3_link_status_cmd *req;
4883 struct hns3_cmd_desc desc;
4887 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4888 ret = hns3_cmd_send(hw, &desc, 1);
4890 hns3_err(hw, "get link status cmd failed %d", ret);
4891 return ETH_LINK_DOWN;
4894 req = (struct hns3_link_status_cmd *)desc.data;
4895 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4897 return !!link_status;
4901 hns3_update_link_status(struct hns3_hw *hw)
4905 state = hns3_get_mac_link_status(hw);
4906 if (state != hw->mac.link_status) {
4907 hw->mac.link_status = state;
4908 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4916 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4918 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4919 struct rte_eth_link new_link;
4923 hns3_update_port_link_info(dev);
4925 memset(&new_link, 0, sizeof(new_link));
4926 hns3_setup_linkstatus(dev, &new_link);
4928 ret = rte_eth_linkstatus_set(dev, &new_link);
4929 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4930 hns3_start_report_lse(dev);
4934 hns3_service_handler(void *param)
4936 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4937 struct hns3_adapter *hns = eth_dev->data->dev_private;
4938 struct hns3_hw *hw = &hns->hw;
4940 if (!hns3_is_reset_pending(hns))
4941 hns3_update_linkstatus_and_event(hw, true);
4943 hns3_warn(hw, "Cancel the query when reset is pending");
4945 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4949 hns3_init_hardware(struct hns3_adapter *hns)
4951 struct hns3_hw *hw = &hns->hw;
4954 ret = hns3_map_tqp(hw);
4956 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4960 ret = hns3_init_umv_space(hw);
4962 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4966 ret = hns3_mac_init(hw);
4968 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4972 ret = hns3_init_mgr_tbl(hw);
4974 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4978 ret = hns3_promisc_init(hw);
4980 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4985 ret = hns3_init_vlan_config(hns);
4987 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4991 ret = hns3_dcb_init(hw);
4993 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4997 ret = hns3_init_fd_config(hns);
4999 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
5003 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
5005 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
5009 ret = hns3_config_gro(hw, false);
5011 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
5016 * In the initialization clearing the all hardware mapping relationship
5017 * configurations between queues and interrupt vectors is needed, so
5018 * some error caused by the residual configurations, such as the
5019 * unexpected interrupt, can be avoid.
5021 ret = hns3_init_ring_with_vector(hw);
5023 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
5030 hns3_uninit_umv_space(hw);
5035 hns3_clear_hw(struct hns3_hw *hw)
5037 struct hns3_cmd_desc desc;
5040 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
5042 ret = hns3_cmd_send(hw, &desc, 1);
5043 if (ret && ret != -EOPNOTSUPP)
5050 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
5055 * The new firmware support report more hardware error types by
5056 * msix mode. These errors are defined as RAS errors in hardware
5057 * and belong to a different type from the MSI-x errors processed
5058 * by the network driver.
5060 * Network driver should open the new error report on initialization.
5062 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5063 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5064 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5068 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5070 struct hns3_mac *mac = &hw->mac;
5072 switch (mac->link_speed) {
5073 case ETH_SPEED_NUM_1G:
5074 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5075 case ETH_SPEED_NUM_10G:
5076 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5077 case ETH_SPEED_NUM_25G:
5078 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5079 case ETH_SPEED_NUM_40G:
5080 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5081 case ETH_SPEED_NUM_50G:
5082 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5083 case ETH_SPEED_NUM_100G:
5084 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5085 case ETH_SPEED_NUM_200G:
5086 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5088 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5094 * Validity of supported_speed for firber and copper media type can be
5095 * guaranteed by the following policy:
5097 * Although the initialization of the phy in the firmware may not be
5098 * completed, the firmware can guarantees that the supported_speed is
5101 * If the version of firmware supports the acitive query way of the
5102 * HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5103 * through it. If unsupported, use the SFP's speed as the value of the
5107 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5109 struct hns3_adapter *hns = eth_dev->data->dev_private;
5110 struct hns3_hw *hw = &hns->hw;
5111 struct hns3_mac *mac = &hw->mac;
5114 ret = hns3_update_link_info(eth_dev);
5118 if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5120 * Some firmware does not support the report of supported_speed,
5121 * and only report the effective speed of SFP. In this case, it
5122 * is necessary to use the SFP's speed as the supported_speed.
5124 if (mac->supported_speed == 0)
5125 mac->supported_speed =
5126 hns3_set_firber_default_support_speed(hw);
5133 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
5135 struct hns3_mac *mac = &hns->hw.mac;
5137 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
5138 hns->pf.support_fc_autoneg = true;
5143 * Flow control auto-negotiation requires the cooperation of the driver
5144 * and firmware. Currently, the optical port does not support flow
5145 * control auto-negotiation.
5147 hns->pf.support_fc_autoneg = false;
5151 hns3_init_pf(struct rte_eth_dev *eth_dev)
5153 struct rte_device *dev = eth_dev->device;
5154 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5155 struct hns3_adapter *hns = eth_dev->data->dev_private;
5156 struct hns3_hw *hw = &hns->hw;
5159 PMD_INIT_FUNC_TRACE();
5161 /* Get hardware io base address from pcie BAR2 IO space */
5162 hw->io_base = pci_dev->mem_resource[2].addr;
5164 /* Firmware command queue initialize */
5165 ret = hns3_cmd_init_queue(hw);
5167 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5168 goto err_cmd_init_queue;
5171 hns3_clear_all_event_cause(hw);
5173 /* Firmware command initialize */
5174 ret = hns3_cmd_init(hw);
5176 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5181 * To ensure that the hardware environment is clean during
5182 * initialization, the driver actively clear the hardware environment
5183 * during initialization, including PF and corresponding VFs' vlan, mac,
5184 * flow table configurations, etc.
5186 ret = hns3_clear_hw(hw);
5188 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5192 /* Hardware statistics of imissed registers cleared. */
5193 ret = hns3_update_imissed_stats(hw, true);
5195 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5199 hns3_config_all_msix_error(hw, true);
5201 ret = rte_intr_callback_register(&pci_dev->intr_handle,
5202 hns3_interrupt_handler,
5205 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5206 goto err_intr_callback_register;
5209 ret = hns3_ptp_init(hw);
5211 goto err_get_config;
5213 /* Enable interrupt */
5214 rte_intr_enable(&pci_dev->intr_handle);
5215 hns3_pf_enable_irq0(hw);
5217 /* Get configuration */
5218 ret = hns3_get_configuration(hw);
5220 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5221 goto err_get_config;
5224 ret = hns3_tqp_stats_init(hw);
5226 goto err_get_config;
5228 ret = hns3_init_hardware(hns);
5230 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5234 /* Initialize flow director filter list & hash */
5235 ret = hns3_fdir_filter_init(hns);
5237 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5241 hns3_rss_set_default_args(hw);
5243 ret = hns3_enable_hw_error_intr(hns, true);
5245 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5247 goto err_enable_intr;
5250 ret = hns3_get_port_supported_speed(eth_dev);
5252 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5253 "by device, ret = %d.", ret);
5254 goto err_supported_speed;
5257 hns3_get_fc_autoneg_capability(hns);
5259 hns3_tm_conf_init(eth_dev);
5263 err_supported_speed:
5264 (void)hns3_enable_hw_error_intr(hns, false);
5266 hns3_fdir_filter_uninit(hns);
5268 hns3_uninit_umv_space(hw);
5270 hns3_tqp_stats_uninit(hw);
5272 hns3_pf_disable_irq0(hw);
5273 rte_intr_disable(&pci_dev->intr_handle);
5274 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5276 err_intr_callback_register:
5278 hns3_cmd_uninit(hw);
5279 hns3_cmd_destroy_queue(hw);
5287 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5289 struct hns3_adapter *hns = eth_dev->data->dev_private;
5290 struct rte_device *dev = eth_dev->device;
5291 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5292 struct hns3_hw *hw = &hns->hw;
5294 PMD_INIT_FUNC_TRACE();
5296 hns3_tm_conf_uninit(eth_dev);
5297 hns3_enable_hw_error_intr(hns, false);
5298 hns3_rss_uninit(hns);
5299 (void)hns3_config_gro(hw, false);
5300 hns3_promisc_uninit(hw);
5301 hns3_fdir_filter_uninit(hns);
5302 hns3_uninit_umv_space(hw);
5303 hns3_tqp_stats_uninit(hw);
5304 hns3_config_mac_tnl_int(hw, false);
5305 hns3_pf_disable_irq0(hw);
5306 rte_intr_disable(&pci_dev->intr_handle);
5307 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5309 hns3_config_all_msix_error(hw, false);
5310 hns3_cmd_uninit(hw);
5311 hns3_cmd_destroy_queue(hw);
5316 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
5320 switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5321 case ETH_LINK_SPEED_10M:
5322 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
5324 case ETH_LINK_SPEED_10M_HD:
5325 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
5327 case ETH_LINK_SPEED_100M:
5328 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
5330 case ETH_LINK_SPEED_100M_HD:
5331 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
5333 case ETH_LINK_SPEED_1G:
5334 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
5345 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
5349 switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5350 case ETH_LINK_SPEED_1G:
5351 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
5353 case ETH_LINK_SPEED_10G:
5354 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
5356 case ETH_LINK_SPEED_25G:
5357 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
5359 case ETH_LINK_SPEED_40G:
5360 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
5362 case ETH_LINK_SPEED_50G:
5363 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
5365 case ETH_LINK_SPEED_100G:
5366 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
5368 case ETH_LINK_SPEED_200G:
5369 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
5380 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
5382 struct hns3_mac *mac = &hw->mac;
5383 uint32_t supported_speed = mac->supported_speed;
5384 uint32_t speed_bit = 0;
5386 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
5387 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
5388 else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
5389 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
5391 if (!(speed_bit & supported_speed)) {
5392 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
5400 static inline uint32_t
5401 hns3_get_link_speed(uint32_t link_speeds)
5403 uint32_t speed = ETH_SPEED_NUM_NONE;
5405 if (link_speeds & ETH_LINK_SPEED_10M ||
5406 link_speeds & ETH_LINK_SPEED_10M_HD)
5407 speed = ETH_SPEED_NUM_10M;
5408 if (link_speeds & ETH_LINK_SPEED_100M ||
5409 link_speeds & ETH_LINK_SPEED_100M_HD)
5410 speed = ETH_SPEED_NUM_100M;
5411 if (link_speeds & ETH_LINK_SPEED_1G)
5412 speed = ETH_SPEED_NUM_1G;
5413 if (link_speeds & ETH_LINK_SPEED_10G)
5414 speed = ETH_SPEED_NUM_10G;
5415 if (link_speeds & ETH_LINK_SPEED_25G)
5416 speed = ETH_SPEED_NUM_25G;
5417 if (link_speeds & ETH_LINK_SPEED_40G)
5418 speed = ETH_SPEED_NUM_40G;
5419 if (link_speeds & ETH_LINK_SPEED_50G)
5420 speed = ETH_SPEED_NUM_50G;
5421 if (link_speeds & ETH_LINK_SPEED_100G)
5422 speed = ETH_SPEED_NUM_100G;
5423 if (link_speeds & ETH_LINK_SPEED_200G)
5424 speed = ETH_SPEED_NUM_200G;
5430 hns3_get_link_duplex(uint32_t link_speeds)
5432 if ((link_speeds & ETH_LINK_SPEED_10M_HD) ||
5433 (link_speeds & ETH_LINK_SPEED_100M_HD))
5434 return ETH_LINK_HALF_DUPLEX;
5436 return ETH_LINK_FULL_DUPLEX;
5440 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5441 struct hns3_set_link_speed_cfg *cfg)
5443 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5444 struct hns3_phy_params_bd0_cmd *req;
5447 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5448 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5450 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5452 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5453 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5454 req->autoneg = cfg->autoneg;
5457 * The full speed capability is used to negotiate when
5458 * auto-negotiation is enabled.
5461 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5462 HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5463 HNS3_PHY_LINK_SPEED_100M_BIT |
5464 HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5465 HNS3_PHY_LINK_SPEED_1000M_BIT;
5467 req->speed = cfg->speed;
5468 req->duplex = cfg->duplex;
5471 return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5475 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5477 struct hns3_config_auto_neg_cmd *req;
5478 struct hns3_cmd_desc desc;
5482 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5484 req = (struct hns3_config_auto_neg_cmd *)desc.data;
5486 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5487 req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5489 ret = hns3_cmd_send(hw, &desc, 1);
5491 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5497 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5498 struct hns3_set_link_speed_cfg *cfg)
5502 if (hw->mac.support_autoneg) {
5503 ret = hns3_set_autoneg(hw, cfg->autoneg);
5505 hns3_err(hw, "failed to configure auto-negotiation.");
5510 * To enable auto-negotiation, we only need to open the switch
5511 * of auto-negotiation, then firmware sets all speed
5519 * Some hardware doesn't support auto-negotiation, but users may not
5520 * configure link_speeds (default 0), which means auto-negotiation.
5521 * In this case, it should return success.
5526 return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
5530 hns3_set_port_link_speed(struct hns3_hw *hw,
5531 struct hns3_set_link_speed_cfg *cfg)
5535 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5536 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5537 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5542 ret = hns3_set_copper_port_link_speed(hw, cfg);
5544 hns3_err(hw, "failed to set copper port link speed,"
5548 } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5549 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5551 hns3_err(hw, "failed to set fiber port link speed,"
5561 hns3_apply_link_speed(struct hns3_hw *hw)
5563 struct rte_eth_conf *conf = &hw->data->dev_conf;
5564 struct hns3_set_link_speed_cfg cfg;
5566 memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5567 cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ?
5568 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
5569 if (cfg.autoneg != ETH_LINK_AUTONEG) {
5570 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5571 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5574 return hns3_set_port_link_speed(hw, &cfg);
5578 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5580 struct hns3_hw *hw = &hns->hw;
5583 ret = hns3_update_queue_map_configure(hns);
5585 hns3_err(hw, "failed to update queue mapping configuration, ret = %d",
5590 /* Note: hns3_tm_conf_update must be called after configuring DCB. */
5591 ret = hns3_tm_conf_update(hw);
5593 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5597 hns3_enable_rxd_adv_layout(hw);
5599 ret = hns3_init_queues(hns, reset_queue);
5601 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5605 ret = hns3_cfg_mac_mode(hw, true);
5607 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5608 goto err_config_mac_mode;
5611 ret = hns3_apply_link_speed(hw);
5613 goto err_set_link_speed;
5618 (void)hns3_cfg_mac_mode(hw, false);
5620 err_config_mac_mode:
5621 hns3_dev_release_mbufs(hns);
5623 * Here is exception handling, hns3_reset_all_tqps will have the
5624 * corresponding error message if it is handled incorrectly, so it is
5625 * not necessary to check hns3_reset_all_tqps return value, here keep
5626 * ret as the error code causing the exception.
5628 (void)hns3_reset_all_tqps(hns);
5633 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5635 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5636 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5637 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5638 uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5639 uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5640 uint32_t intr_vector;
5645 * hns3 needs a separate interrupt to be used as event interrupt which
5646 * could not be shared with task queue pair, so KERNEL drivers need
5647 * support multiple interrupt vectors.
5649 if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5650 !rte_intr_cap_multiple(intr_handle))
5653 rte_intr_disable(intr_handle);
5654 intr_vector = hw->used_rx_queues;
5655 /* creates event fd for each intr vector when MSIX is used */
5656 if (rte_intr_efd_enable(intr_handle, intr_vector))
5659 if (intr_handle->intr_vec == NULL) {
5660 intr_handle->intr_vec =
5661 rte_zmalloc("intr_vec",
5662 hw->used_rx_queues * sizeof(int), 0);
5663 if (intr_handle->intr_vec == NULL) {
5664 hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5665 hw->used_rx_queues);
5667 goto alloc_intr_vec_error;
5671 if (rte_intr_allow_others(intr_handle)) {
5672 vec = RTE_INTR_VEC_RXTX_OFFSET;
5673 base = RTE_INTR_VEC_RXTX_OFFSET;
5676 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5677 ret = hns3_bind_ring_with_vector(hw, vec, true,
5678 HNS3_RING_TYPE_RX, q_id);
5680 goto bind_vector_error;
5681 intr_handle->intr_vec[q_id] = vec;
5683 * If there are not enough efds (e.g. not enough interrupt),
5684 * remaining queues will be bond to the last interrupt.
5686 if (vec < base + intr_handle->nb_efd - 1)
5689 rte_intr_enable(intr_handle);
5693 rte_free(intr_handle->intr_vec);
5694 intr_handle->intr_vec = NULL;
5695 alloc_intr_vec_error:
5696 rte_intr_efd_disable(intr_handle);
5701 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5703 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5704 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5705 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5709 if (dev->data->dev_conf.intr_conf.rxq == 0)
5712 if (rte_intr_dp_is_en(intr_handle)) {
5713 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5714 ret = hns3_bind_ring_with_vector(hw,
5715 intr_handle->intr_vec[q_id], true,
5716 HNS3_RING_TYPE_RX, q_id);
5726 hns3_restore_filter(struct rte_eth_dev *dev)
5728 hns3_restore_rss_filter(dev);
5732 hns3_dev_start(struct rte_eth_dev *dev)
5734 struct hns3_adapter *hns = dev->data->dev_private;
5735 struct hns3_hw *hw = &hns->hw;
5738 PMD_INIT_FUNC_TRACE();
5739 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5742 rte_spinlock_lock(&hw->lock);
5743 hw->adapter_state = HNS3_NIC_STARTING;
5745 ret = hns3_do_start(hns, true);
5747 hw->adapter_state = HNS3_NIC_CONFIGURED;
5748 rte_spinlock_unlock(&hw->lock);
5751 ret = hns3_map_rx_interrupt(dev);
5753 goto map_rx_inter_err;
5756 * There are three register used to control the status of a TQP
5757 * (contains a pair of Tx queue and Rx queue) in the new version network
5758 * engine. One is used to control the enabling of Tx queue, the other is
5759 * used to control the enabling of Rx queue, and the last is the master
5760 * switch used to control the enabling of the tqp. The Tx register and
5761 * TQP register must be enabled at the same time to enable a Tx queue.
5762 * The same applies to the Rx queue. For the older network engine, this
5763 * function only refresh the enabled flag, and it is used to update the
5764 * status of queue in the dpdk framework.
5766 ret = hns3_start_all_txqs(dev);
5768 goto map_rx_inter_err;
5770 ret = hns3_start_all_rxqs(dev);
5772 goto start_all_rxqs_fail;
5774 hw->adapter_state = HNS3_NIC_STARTED;
5775 rte_spinlock_unlock(&hw->lock);
5777 hns3_rx_scattered_calc(dev);
5778 hns3_set_rxtx_function(dev);
5779 hns3_mp_req_start_rxtx(dev);
5781 hns3_restore_filter(dev);
5783 /* Enable interrupt of all rx queues before enabling queues */
5784 hns3_dev_all_rx_queue_intr_enable(hw, true);
5787 * After finished the initialization, enable tqps to receive/transmit
5788 * packets and refresh all queue status.
5790 hns3_start_tqps(hw);
5792 hns3_tm_dev_start_proc(hw);
5794 if (dev->data->dev_conf.intr_conf.lsc != 0)
5795 hns3_dev_link_update(dev, 0);
5796 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5798 hns3_info(hw, "hns3 dev start successful!");
5802 start_all_rxqs_fail:
5803 hns3_stop_all_txqs(dev);
5805 (void)hns3_do_stop(hns);
5806 hw->adapter_state = HNS3_NIC_CONFIGURED;
5807 rte_spinlock_unlock(&hw->lock);
5813 hns3_do_stop(struct hns3_adapter *hns)
5815 struct hns3_hw *hw = &hns->hw;
5819 * The "hns3_do_stop" function will also be called by .stop_service to
5820 * prepare reset. At the time of global or IMP reset, the command cannot
5821 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5822 * accessed during the reset process. So the mbuf can not be released
5823 * during reset and is required to be released after the reset is
5826 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)
5827 hns3_dev_release_mbufs(hns);
5829 ret = hns3_cfg_mac_mode(hw, false);
5832 hw->mac.link_status = ETH_LINK_DOWN;
5834 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5835 hns3_configure_all_mac_addr(hns, true);
5836 ret = hns3_reset_all_tqps(hns);
5838 hns3_err(hw, "failed to reset all queues ret = %d.",
5843 hw->mac.default_addr_setted = false;
5848 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5850 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5851 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5852 struct hns3_adapter *hns = dev->data->dev_private;
5853 struct hns3_hw *hw = &hns->hw;
5854 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5855 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5858 if (dev->data->dev_conf.intr_conf.rxq == 0)
5861 /* unmap the ring with vector */
5862 if (rte_intr_allow_others(intr_handle)) {
5863 vec = RTE_INTR_VEC_RXTX_OFFSET;
5864 base = RTE_INTR_VEC_RXTX_OFFSET;
5866 if (rte_intr_dp_is_en(intr_handle)) {
5867 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5868 (void)hns3_bind_ring_with_vector(hw, vec, false,
5871 if (vec < base + intr_handle->nb_efd - 1)
5875 /* Clean datapath event and queue/vec mapping */
5876 rte_intr_efd_disable(intr_handle);
5877 if (intr_handle->intr_vec) {
5878 rte_free(intr_handle->intr_vec);
5879 intr_handle->intr_vec = NULL;
5884 hns3_dev_stop(struct rte_eth_dev *dev)
5886 struct hns3_adapter *hns = dev->data->dev_private;
5887 struct hns3_hw *hw = &hns->hw;
5889 PMD_INIT_FUNC_TRACE();
5890 dev->data->dev_started = 0;
5892 hw->adapter_state = HNS3_NIC_STOPPING;
5893 hns3_set_rxtx_function(dev);
5895 /* Disable datapath on secondary process. */
5896 hns3_mp_req_stop_rxtx(dev);
5897 /* Prevent crashes when queues are still in use. */
5898 rte_delay_ms(hw->cfg_max_queues);
5900 rte_spinlock_lock(&hw->lock);
5901 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5902 hns3_tm_dev_stop_proc(hw);
5903 hns3_config_mac_tnl_int(hw, false);
5906 hns3_unmap_rx_interrupt(dev);
5907 hw->adapter_state = HNS3_NIC_CONFIGURED;
5909 hns3_rx_scattered_reset(dev);
5910 rte_eal_alarm_cancel(hns3_service_handler, dev);
5911 hns3_stop_report_lse(dev);
5912 rte_spinlock_unlock(&hw->lock);
5918 hns3_dev_close(struct rte_eth_dev *eth_dev)
5920 struct hns3_adapter *hns = eth_dev->data->dev_private;
5921 struct hns3_hw *hw = &hns->hw;
5924 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5925 rte_free(eth_dev->process_private);
5926 eth_dev->process_private = NULL;
5930 if (hw->adapter_state == HNS3_NIC_STARTED)
5931 ret = hns3_dev_stop(eth_dev);
5933 hw->adapter_state = HNS3_NIC_CLOSING;
5934 hns3_reset_abort(hns);
5935 hw->adapter_state = HNS3_NIC_CLOSED;
5937 hns3_configure_all_mc_mac_addr(hns, true);
5938 hns3_remove_all_vlan_table(hns);
5939 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5940 hns3_uninit_pf(eth_dev);
5941 hns3_free_all_queues(eth_dev);
5942 rte_free(hw->reset.wait_data);
5943 rte_free(eth_dev->process_private);
5944 eth_dev->process_private = NULL;
5945 hns3_mp_uninit_primary();
5946 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5952 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5955 struct hns3_mac *mac = &hw->mac;
5956 uint32_t advertising = mac->advertising;
5957 uint32_t lp_advertising = mac->lp_advertising;
5961 if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5964 } else if (advertising & lp_advertising &
5965 HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5966 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5968 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5973 static enum hns3_fc_mode
5974 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5976 enum hns3_fc_mode current_mode;
5977 bool rx_pause = false;
5978 bool tx_pause = false;
5980 switch (hw->mac.media_type) {
5981 case HNS3_MEDIA_TYPE_COPPER:
5982 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5986 * Flow control auto-negotiation is not supported for fiber and
5987 * backpalne media type.
5989 case HNS3_MEDIA_TYPE_FIBER:
5990 case HNS3_MEDIA_TYPE_BACKPLANE:
5991 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
5992 current_mode = hw->requested_fc_mode;
5995 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
5996 hw->mac.media_type);
5997 current_mode = HNS3_FC_NONE;
6001 if (rx_pause && tx_pause)
6002 current_mode = HNS3_FC_FULL;
6004 current_mode = HNS3_FC_RX_PAUSE;
6006 current_mode = HNS3_FC_TX_PAUSE;
6008 current_mode = HNS3_FC_NONE;
6011 return current_mode;
6014 static enum hns3_fc_mode
6015 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
6017 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6018 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6019 struct hns3_mac *mac = &hw->mac;
6022 * When the flow control mode is obtained, the device may not complete
6023 * auto-negotiation. It is necessary to wait for link establishment.
6025 (void)hns3_dev_link_update(dev, 1);
6028 * If the link auto-negotiation of the nic is disabled, or the flow
6029 * control auto-negotiation is not supported, the forced flow control
6032 if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
6033 return hw->requested_fc_mode;
6035 return hns3_get_autoneg_fc_mode(hw);
6039 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6041 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6042 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6043 enum hns3_fc_mode current_mode;
6045 current_mode = hns3_get_current_fc_mode(dev);
6046 switch (current_mode) {
6048 fc_conf->mode = RTE_FC_FULL;
6050 case HNS3_FC_TX_PAUSE:
6051 fc_conf->mode = RTE_FC_TX_PAUSE;
6053 case HNS3_FC_RX_PAUSE:
6054 fc_conf->mode = RTE_FC_RX_PAUSE;
6058 fc_conf->mode = RTE_FC_NONE;
6062 fc_conf->pause_time = pf->pause_time;
6063 fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
6069 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
6071 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
6073 if (!pf->support_fc_autoneg) {
6075 hns3_err(hw, "unsupported fc auto-negotiation setting.");
6080 * Flow control auto-negotiation of the NIC is not supported,
6081 * but other auto-negotiation features may be supported.
6083 if (autoneg != hw->mac.link_autoneg) {
6084 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
6092 * If flow control auto-negotiation of the NIC is supported, all
6093 * auto-negotiation features are supported.
6095 if (autoneg != hw->mac.link_autoneg) {
6096 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
6104 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6106 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6109 if (fc_conf->high_water || fc_conf->low_water ||
6110 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
6111 hns3_err(hw, "Unsupported flow control settings specified, "
6112 "high_water(%u), low_water(%u), send_xon(%u) and "
6113 "mac_ctrl_frame_fwd(%u) must be set to '0'",
6114 fc_conf->high_water, fc_conf->low_water,
6115 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
6119 ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
6123 if (!fc_conf->pause_time) {
6124 hns3_err(hw, "Invalid pause time %u setting.",
6125 fc_conf->pause_time);
6129 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6130 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
6131 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
6132 "current_fc_status = %d", hw->current_fc_status);
6136 if (hw->num_tc > 1) {
6137 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
6141 rte_spinlock_lock(&hw->lock);
6142 ret = hns3_fc_enable(dev, fc_conf);
6143 rte_spinlock_unlock(&hw->lock);
6149 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
6150 struct rte_eth_pfc_conf *pfc_conf)
6152 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6155 if (!hns3_dev_dcb_supported(hw)) {
6156 hns3_err(hw, "This port does not support dcb configurations.");
6160 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
6161 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
6162 hns3_err(hw, "Unsupported flow control settings specified, "
6163 "high_water(%u), low_water(%u), send_xon(%u) and "
6164 "mac_ctrl_frame_fwd(%u) must be set to '0'",
6165 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
6166 pfc_conf->fc.send_xon,
6167 pfc_conf->fc.mac_ctrl_frame_fwd);
6170 if (pfc_conf->fc.autoneg) {
6171 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
6174 if (pfc_conf->fc.pause_time == 0) {
6175 hns3_err(hw, "Invalid pause time %u setting.",
6176 pfc_conf->fc.pause_time);
6180 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6181 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
6182 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
6183 "current_fc_status = %d", hw->current_fc_status);
6187 rte_spinlock_lock(&hw->lock);
6188 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
6189 rte_spinlock_unlock(&hw->lock);
6195 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
6197 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6198 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6199 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
6202 rte_spinlock_lock(&hw->lock);
6203 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
6204 dcb_info->nb_tcs = pf->local_max_tc;
6206 dcb_info->nb_tcs = 1;
6208 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
6209 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
6210 for (i = 0; i < dcb_info->nb_tcs; i++)
6211 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
6213 for (i = 0; i < hw->num_tc; i++) {
6214 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
6215 dcb_info->tc_queue.tc_txq[0][i].base =
6216 hw->tc_queue[i].tqp_offset;
6217 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
6218 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
6219 hw->tc_queue[i].tqp_count;
6221 rte_spinlock_unlock(&hw->lock);
6227 hns3_reinit_dev(struct hns3_adapter *hns)
6229 struct hns3_hw *hw = &hns->hw;
6232 ret = hns3_cmd_init(hw);
6234 hns3_err(hw, "Failed to init cmd: %d", ret);
6238 ret = hns3_reset_all_tqps(hns);
6240 hns3_err(hw, "Failed to reset all queues: %d", ret);
6244 ret = hns3_init_hardware(hns);
6246 hns3_err(hw, "Failed to init hardware: %d", ret);
6250 ret = hns3_enable_hw_error_intr(hns, true);
6252 hns3_err(hw, "fail to enable hw error interrupts: %d",
6256 hns3_info(hw, "Reset done, driver initialization finished.");
6262 is_pf_reset_done(struct hns3_hw *hw)
6264 uint32_t val, reg, reg_bit;
6266 switch (hw->reset.level) {
6267 case HNS3_IMP_RESET:
6268 reg = HNS3_GLOBAL_RESET_REG;
6269 reg_bit = HNS3_IMP_RESET_BIT;
6271 case HNS3_GLOBAL_RESET:
6272 reg = HNS3_GLOBAL_RESET_REG;
6273 reg_bit = HNS3_GLOBAL_RESET_BIT;
6275 case HNS3_FUNC_RESET:
6276 reg = HNS3_FUN_RST_ING;
6277 reg_bit = HNS3_FUN_RST_ING_B;
6279 case HNS3_FLR_RESET:
6281 hns3_err(hw, "Wait for unsupported reset level: %d",
6285 val = hns3_read_dev(hw, reg);
6286 if (hns3_get_bit(val, reg_bit))
6293 hns3_is_reset_pending(struct hns3_adapter *hns)
6295 struct hns3_hw *hw = &hns->hw;
6296 enum hns3_reset_level reset;
6298 hns3_check_event_cause(hns, NULL);
6299 reset = hns3_get_reset_level(hns, &hw->reset.pending);
6301 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6302 hw->reset.level < reset) {
6303 hns3_warn(hw, "High level reset %d is pending", reset);
6306 reset = hns3_get_reset_level(hns, &hw->reset.request);
6307 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6308 hw->reset.level < reset) {
6309 hns3_warn(hw, "High level reset %d is request", reset);
6316 hns3_wait_hardware_ready(struct hns3_adapter *hns)
6318 struct hns3_hw *hw = &hns->hw;
6319 struct hns3_wait_data *wait_data = hw->reset.wait_data;
6322 if (wait_data->result == HNS3_WAIT_SUCCESS)
6324 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
6325 hns3_clock_gettime(&tv);
6326 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
6327 tv.tv_sec, tv.tv_usec);
6329 } else if (wait_data->result == HNS3_WAIT_REQUEST)
6332 wait_data->hns = hns;
6333 wait_data->check_completion = is_pf_reset_done;
6334 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
6335 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms();
6336 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
6337 wait_data->count = HNS3_RESET_WAIT_CNT;
6338 wait_data->result = HNS3_WAIT_REQUEST;
6339 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
6344 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
6346 struct hns3_cmd_desc desc;
6347 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6349 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6350 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6351 req->fun_reset_vfid = func_id;
6353 return hns3_cmd_send(hw, &desc, 1);
6357 hns3_imp_reset_cmd(struct hns3_hw *hw)
6359 struct hns3_cmd_desc desc;
6361 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6362 desc.data[0] = 0xeedd;
6364 return hns3_cmd_send(hw, &desc, 1);
6368 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6370 struct hns3_hw *hw = &hns->hw;
6374 hns3_clock_gettime(&tv);
6375 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6376 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6377 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6378 tv.tv_sec, tv.tv_usec);
6382 switch (reset_level) {
6383 case HNS3_IMP_RESET:
6384 hns3_imp_reset_cmd(hw);
6385 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6386 tv.tv_sec, tv.tv_usec);
6388 case HNS3_GLOBAL_RESET:
6389 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6390 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6391 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6392 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6393 tv.tv_sec, tv.tv_usec);
6395 case HNS3_FUNC_RESET:
6396 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6397 tv.tv_sec, tv.tv_usec);
6398 /* schedule again to check later */
6399 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6400 hns3_schedule_reset(hns);
6403 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6406 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6409 static enum hns3_reset_level
6410 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6412 struct hns3_hw *hw = &hns->hw;
6413 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6415 /* Return the highest priority reset level amongst all */
6416 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6417 reset_level = HNS3_IMP_RESET;
6418 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6419 reset_level = HNS3_GLOBAL_RESET;
6420 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6421 reset_level = HNS3_FUNC_RESET;
6422 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6423 reset_level = HNS3_FLR_RESET;
6425 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6426 return HNS3_NONE_RESET;
6432 hns3_record_imp_error(struct hns3_adapter *hns)
6434 struct hns3_hw *hw = &hns->hw;
6437 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6438 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6439 hns3_warn(hw, "Detected IMP RD poison!");
6440 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6441 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6444 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6445 hns3_warn(hw, "Detected IMP CMDQ error!");
6446 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6447 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6452 hns3_prepare_reset(struct hns3_adapter *hns)
6454 struct hns3_hw *hw = &hns->hw;
6458 switch (hw->reset.level) {
6459 case HNS3_FUNC_RESET:
6460 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6465 * After performaning pf reset, it is not necessary to do the
6466 * mailbox handling or send any command to firmware, because
6467 * any mailbox handling or command to firmware is only valid
6468 * after hns3_cmd_init is called.
6470 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6471 hw->reset.stats.request_cnt++;
6473 case HNS3_IMP_RESET:
6474 hns3_record_imp_error(hns);
6475 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6476 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6477 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6486 hns3_set_rst_done(struct hns3_hw *hw)
6488 struct hns3_pf_rst_done_cmd *req;
6489 struct hns3_cmd_desc desc;
6491 req = (struct hns3_pf_rst_done_cmd *)desc.data;
6492 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6493 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6494 return hns3_cmd_send(hw, &desc, 1);
6498 hns3_stop_service(struct hns3_adapter *hns)
6500 struct hns3_hw *hw = &hns->hw;
6501 struct rte_eth_dev *eth_dev;
6503 eth_dev = &rte_eth_devices[hw->data->port_id];
6504 hw->mac.link_status = ETH_LINK_DOWN;
6505 if (hw->adapter_state == HNS3_NIC_STARTED) {
6506 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6507 hns3_update_linkstatus_and_event(hw, false);
6510 hns3_set_rxtx_function(eth_dev);
6512 /* Disable datapath on secondary process. */
6513 hns3_mp_req_stop_rxtx(eth_dev);
6514 rte_delay_ms(hw->cfg_max_queues);
6516 rte_spinlock_lock(&hw->lock);
6517 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6518 hw->adapter_state == HNS3_NIC_STOPPING) {
6519 hns3_enable_all_queues(hw, false);
6521 hw->reset.mbuf_deferred_free = true;
6523 hw->reset.mbuf_deferred_free = false;
6526 * It is cumbersome for hardware to pick-and-choose entries for deletion
6527 * from table space. Hence, for function reset software intervention is
6528 * required to delete the entries
6530 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6531 hns3_configure_all_mc_mac_addr(hns, true);
6532 rte_spinlock_unlock(&hw->lock);
6538 hns3_start_service(struct hns3_adapter *hns)
6540 struct hns3_hw *hw = &hns->hw;
6541 struct rte_eth_dev *eth_dev;
6543 if (hw->reset.level == HNS3_IMP_RESET ||
6544 hw->reset.level == HNS3_GLOBAL_RESET)
6545 hns3_set_rst_done(hw);
6546 eth_dev = &rte_eth_devices[hw->data->port_id];
6547 hns3_set_rxtx_function(eth_dev);
6548 hns3_mp_req_start_rxtx(eth_dev);
6549 if (hw->adapter_state == HNS3_NIC_STARTED) {
6551 * This API parent function already hold the hns3_hw.lock, the
6552 * hns3_service_handler may report lse, in bonding application
6553 * it will call driver's ops which may acquire the hns3_hw.lock
6554 * again, thus lead to deadlock.
6555 * We defer calls hns3_service_handler to avoid the deadlock.
6557 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6558 hns3_service_handler, eth_dev);
6560 /* Enable interrupt of all rx queues before enabling queues */
6561 hns3_dev_all_rx_queue_intr_enable(hw, true);
6563 * Enable state of each rxq and txq will be recovered after
6564 * reset, so we need to restore them before enable all tqps;
6566 hns3_restore_tqp_enable_state(hw);
6568 * When finished the initialization, enable queues to receive
6569 * and transmit packets.
6571 hns3_enable_all_queues(hw, true);
6578 hns3_restore_conf(struct hns3_adapter *hns)
6580 struct hns3_hw *hw = &hns->hw;
6583 ret = hns3_configure_all_mac_addr(hns, false);
6587 ret = hns3_configure_all_mc_mac_addr(hns, false);
6591 ret = hns3_dev_promisc_restore(hns);
6595 ret = hns3_restore_vlan_table(hns);
6599 ret = hns3_restore_vlan_conf(hns);
6603 ret = hns3_restore_all_fdir_filter(hns);
6607 ret = hns3_restore_ptp(hns);
6611 ret = hns3_restore_rx_interrupt(hw);
6615 ret = hns3_restore_gro_conf(hw);
6619 ret = hns3_restore_fec(hw);
6623 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6624 ret = hns3_do_start(hns, false);
6627 hns3_info(hw, "hns3 dev restart successful!");
6628 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6629 hw->adapter_state = HNS3_NIC_CONFIGURED;
6633 hns3_configure_all_mc_mac_addr(hns, true);
6635 hns3_configure_all_mac_addr(hns, true);
6640 hns3_reset_service(void *param)
6642 struct hns3_adapter *hns = (struct hns3_adapter *)param;
6643 struct hns3_hw *hw = &hns->hw;
6644 enum hns3_reset_level reset_level;
6645 struct timeval tv_delta;
6646 struct timeval tv_start;
6652 * The interrupt is not triggered within the delay time.
6653 * The interrupt may have been lost. It is necessary to handle
6654 * the interrupt to recover from the error.
6656 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6657 SCHEDULE_DEFERRED) {
6658 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6660 hns3_err(hw, "Handling interrupts in delayed tasks");
6661 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6662 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6663 if (reset_level == HNS3_NONE_RESET) {
6664 hns3_err(hw, "No reset level is set, try IMP reset");
6665 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6668 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6671 * Check if there is any ongoing reset in the hardware. This status can
6672 * be checked from reset_pending. If there is then, we need to wait for
6673 * hardware to complete reset.
6674 * a. If we are able to figure out in reasonable time that hardware
6675 * has fully resetted then, we can proceed with driver, client
6677 * b. else, we can come back later to check this status so re-sched
6680 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6681 if (reset_level != HNS3_NONE_RESET) {
6682 hns3_clock_gettime(&tv_start);
6683 ret = hns3_reset_process(hns, reset_level);
6684 hns3_clock_gettime(&tv);
6685 timersub(&tv, &tv_start, &tv_delta);
6686 msec = hns3_clock_calctime_ms(&tv_delta);
6687 if (msec > HNS3_RESET_PROCESS_MS)
6688 hns3_err(hw, "%d handle long time delta %" PRIu64
6689 " ms time=%ld.%.6ld",
6690 hw->reset.level, msec,
6691 tv.tv_sec, tv.tv_usec);
6696 /* Check if we got any *new* reset requests to be honored */
6697 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6698 if (reset_level != HNS3_NONE_RESET)
6699 hns3_msix_process(hns, reset_level);
6703 hns3_get_speed_capa_num(uint16_t device_id)
6707 switch (device_id) {
6708 case HNS3_DEV_ID_25GE:
6709 case HNS3_DEV_ID_25GE_RDMA:
6712 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6713 case HNS3_DEV_ID_200G_RDMA:
6725 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6728 switch (device_id) {
6729 case HNS3_DEV_ID_25GE:
6731 case HNS3_DEV_ID_25GE_RDMA:
6732 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6733 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6735 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6736 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6737 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6739 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6740 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6741 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6743 case HNS3_DEV_ID_200G_RDMA:
6744 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6745 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6755 hns3_fec_get_capability(struct rte_eth_dev *dev,
6756 struct rte_eth_fec_capa *speed_fec_capa,
6759 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6760 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6761 uint16_t device_id = pci_dev->id.device_id;
6762 unsigned int capa_num;
6765 capa_num = hns3_get_speed_capa_num(device_id);
6766 if (capa_num == 0) {
6767 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6772 if (speed_fec_capa == NULL || num < capa_num)
6775 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6783 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6785 struct hns3_config_fec_cmd *req;
6786 struct hns3_cmd_desc desc;
6790 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6791 * in device of link speed
6794 if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6799 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6800 req = (struct hns3_config_fec_cmd *)desc.data;
6801 ret = hns3_cmd_send(hw, &desc, 1);
6803 hns3_err(hw, "get current fec auto state failed, ret = %d",
6808 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6813 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6815 struct hns3_sfp_info_cmd *resp;
6816 uint32_t tmp_fec_capa;
6818 struct hns3_cmd_desc desc;
6822 * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6823 * configured FEC mode is returned.
6824 * If link is up, current FEC mode is returned.
6826 if (hw->mac.link_status == ETH_LINK_DOWN) {
6827 ret = get_current_fec_auto_state(hw, &auto_state);
6831 if (auto_state == 0x1) {
6832 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6837 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6838 resp = (struct hns3_sfp_info_cmd *)desc.data;
6839 resp->query_type = HNS3_ACTIVE_QUERY;
6841 ret = hns3_cmd_send(hw, &desc, 1);
6842 if (ret == -EOPNOTSUPP) {
6843 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6846 hns3_err(hw, "get FEC failed, ret = %d", ret);
6851 * FEC mode order defined in hns3 hardware is inconsistend with
6852 * that defined in the ethdev library. So the sequence needs
6855 switch (resp->active_fec) {
6856 case HNS3_HW_FEC_MODE_NOFEC:
6857 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6859 case HNS3_HW_FEC_MODE_BASER:
6860 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6862 case HNS3_HW_FEC_MODE_RS:
6863 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6866 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6870 *fec_capa = tmp_fec_capa;
6875 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6877 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6879 return hns3_fec_get_internal(hw, fec_capa);
6883 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6885 struct hns3_config_fec_cmd *req;
6886 struct hns3_cmd_desc desc;
6889 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6891 req = (struct hns3_config_fec_cmd *)desc.data;
6893 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6894 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6895 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6897 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6898 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6899 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6901 case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6902 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6903 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6905 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6906 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6911 ret = hns3_cmd_send(hw, &desc, 1);
6913 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6919 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6921 struct hns3_mac *mac = &hw->mac;
6924 switch (mac->link_speed) {
6925 case ETH_SPEED_NUM_10G:
6926 cur_capa = fec_capa[1].capa;
6928 case ETH_SPEED_NUM_25G:
6929 case ETH_SPEED_NUM_100G:
6930 case ETH_SPEED_NUM_200G:
6931 cur_capa = fec_capa[0].capa;
6942 is_fec_mode_one_bit_set(uint32_t mode)
6947 for (i = 0; i < sizeof(mode); i++)
6948 if (mode >> i & 0x1)
6951 return cnt == 1 ? true : false;
6955 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6957 #define FEC_CAPA_NUM 2
6958 struct hns3_adapter *hns = dev->data->dev_private;
6959 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6960 struct hns3_pf *pf = &hns->pf;
6962 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6964 uint32_t num = FEC_CAPA_NUM;
6967 ret = hns3_fec_get_capability(dev, fec_capa, num);
6971 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6972 if (!is_fec_mode_one_bit_set(mode)) {
6973 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, "
6974 "FEC mode should be only one bit set", mode);
6979 * Check whether the configured mode is within the FEC capability.
6980 * If not, the configured mode will not be supported.
6982 cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6983 if (!(cur_capa & mode)) {
6984 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6988 rte_spinlock_lock(&hw->lock);
6989 ret = hns3_set_fec_hw(hw, mode);
6991 rte_spinlock_unlock(&hw->lock);
6995 pf->fec_mode = mode;
6996 rte_spinlock_unlock(&hw->lock);
7002 hns3_restore_fec(struct hns3_hw *hw)
7004 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7005 struct hns3_pf *pf = &hns->pf;
7006 uint32_t mode = pf->fec_mode;
7009 ret = hns3_set_fec_hw(hw, mode);
7011 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
7018 hns3_query_dev_fec_info(struct hns3_hw *hw)
7020 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7021 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
7024 ret = hns3_fec_get_internal(hw, &pf->fec_mode);
7026 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
7032 hns3_optical_module_existed(struct hns3_hw *hw)
7034 struct hns3_cmd_desc desc;
7038 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
7039 ret = hns3_cmd_send(hw, &desc, 1);
7042 "fail to get optical module exist state, ret = %d.\n",
7046 existed = !!desc.data[0];
7052 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
7053 uint32_t len, uint8_t *data)
7055 #define HNS3_SFP_INFO_CMD_NUM 6
7056 #define HNS3_SFP_INFO_MAX_LEN \
7057 (HNS3_SFP_INFO_BD0_LEN + \
7058 (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
7059 struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
7060 struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
7066 for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7067 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
7069 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
7070 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
7073 sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
7074 sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
7075 read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
7076 sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
7078 ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
7080 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
7085 /* The data format in BD0 is different with the others. */
7086 copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
7087 memcpy(data, sfp_info_bd0->data, copy_len);
7088 read_len = copy_len;
7090 for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7091 if (read_len >= len)
7094 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
7095 memcpy(data + read_len, desc[i].data, copy_len);
7096 read_len += copy_len;
7099 return (int)read_len;
7103 hns3_get_module_eeprom(struct rte_eth_dev *dev,
7104 struct rte_dev_eeprom_info *info)
7106 struct hns3_adapter *hns = dev->data->dev_private;
7107 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7108 uint32_t offset = info->offset;
7109 uint32_t len = info->length;
7110 uint8_t *data = info->data;
7111 uint32_t read_len = 0;
7113 if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
7116 if (!hns3_optical_module_existed(hw)) {
7117 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
7121 while (read_len < len) {
7123 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
7135 hns3_get_module_info(struct rte_eth_dev *dev,
7136 struct rte_eth_dev_module_info *modinfo)
7138 #define HNS3_SFF8024_ID_SFP 0x03
7139 #define HNS3_SFF8024_ID_QSFP_8438 0x0c
7140 #define HNS3_SFF8024_ID_QSFP_8436_8636 0x0d
7141 #define HNS3_SFF8024_ID_QSFP28_8636 0x11
7142 #define HNS3_SFF_8636_V1_3 0x03
7143 struct hns3_adapter *hns = dev->data->dev_private;
7144 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7145 struct rte_dev_eeprom_info info;
7146 struct hns3_sfp_type sfp_type;
7149 memset(&sfp_type, 0, sizeof(sfp_type));
7150 memset(&info, 0, sizeof(info));
7151 info.data = (uint8_t *)&sfp_type;
7152 info.length = sizeof(sfp_type);
7153 ret = hns3_get_module_eeprom(dev, &info);
7157 switch (sfp_type.type) {
7158 case HNS3_SFF8024_ID_SFP:
7159 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7160 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7162 case HNS3_SFF8024_ID_QSFP_8438:
7163 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7164 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7166 case HNS3_SFF8024_ID_QSFP_8436_8636:
7167 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
7168 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7169 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7171 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7172 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7175 case HNS3_SFF8024_ID_QSFP28_8636:
7176 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7177 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7180 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
7181 sfp_type.type, sfp_type.ext_type);
7189 hns3_clock_gettime(struct timeval *tv)
7191 #ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */
7192 #define CLOCK_TYPE CLOCK_MONOTONIC_RAW
7194 #define CLOCK_TYPE CLOCK_MONOTONIC
7196 #define NSEC_TO_USEC_DIV 1000
7198 struct timespec spec;
7199 (void)clock_gettime(CLOCK_TYPE, &spec);
7201 tv->tv_sec = spec.tv_sec;
7202 tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV;
7206 hns3_clock_calctime_ms(struct timeval *tv)
7208 return (uint64_t)tv->tv_sec * MSEC_PER_SEC +
7209 tv->tv_usec / USEC_PER_MSEC;
7213 hns3_clock_gettime_ms(void)
7217 hns3_clock_gettime(&tv);
7218 return hns3_clock_calctime_ms(&tv);
7222 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
7224 uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
7228 if (strcmp(value, "vec") == 0)
7229 hint = HNS3_IO_FUNC_HINT_VEC;
7230 else if (strcmp(value, "sve") == 0)
7231 hint = HNS3_IO_FUNC_HINT_SVE;
7232 else if (strcmp(value, "simple") == 0)
7233 hint = HNS3_IO_FUNC_HINT_SIMPLE;
7234 else if (strcmp(value, "common") == 0)
7235 hint = HNS3_IO_FUNC_HINT_COMMON;
7237 /* If the hint is valid then update output parameters */
7238 if (hint != HNS3_IO_FUNC_HINT_NONE)
7239 *(uint32_t *)extra_args = hint;
7245 hns3_get_io_hint_func_name(uint32_t hint)
7248 case HNS3_IO_FUNC_HINT_VEC:
7250 case HNS3_IO_FUNC_HINT_SVE:
7252 case HNS3_IO_FUNC_HINT_SIMPLE:
7254 case HNS3_IO_FUNC_HINT_COMMON:
7262 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args)
7268 val = strtoull(value, NULL, 16);
7269 *(uint64_t *)extra_args = val;
7275 hns3_parse_devargs(struct rte_eth_dev *dev)
7277 struct hns3_adapter *hns = dev->data->dev_private;
7278 uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7279 uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7280 struct hns3_hw *hw = &hns->hw;
7281 uint64_t dev_caps_mask = 0;
7282 struct rte_kvargs *kvlist;
7284 if (dev->device->devargs == NULL)
7287 kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
7291 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
7292 &hns3_parse_io_hint_func, &rx_func_hint);
7293 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
7294 &hns3_parse_io_hint_func, &tx_func_hint);
7295 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK,
7296 &hns3_parse_dev_caps_mask, &dev_caps_mask);
7297 rte_kvargs_free(kvlist);
7299 if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7300 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
7301 hns3_get_io_hint_func_name(rx_func_hint));
7302 hns->rx_func_hint = rx_func_hint;
7303 if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7304 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
7305 hns3_get_io_hint_func_name(tx_func_hint));
7306 hns->tx_func_hint = tx_func_hint;
7308 if (dev_caps_mask != 0)
7309 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".",
7310 HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask);
7311 hns->dev_caps_mask = dev_caps_mask;
7314 static const struct eth_dev_ops hns3_eth_dev_ops = {
7315 .dev_configure = hns3_dev_configure,
7316 .dev_start = hns3_dev_start,
7317 .dev_stop = hns3_dev_stop,
7318 .dev_close = hns3_dev_close,
7319 .promiscuous_enable = hns3_dev_promiscuous_enable,
7320 .promiscuous_disable = hns3_dev_promiscuous_disable,
7321 .allmulticast_enable = hns3_dev_allmulticast_enable,
7322 .allmulticast_disable = hns3_dev_allmulticast_disable,
7323 .mtu_set = hns3_dev_mtu_set,
7324 .stats_get = hns3_stats_get,
7325 .stats_reset = hns3_stats_reset,
7326 .xstats_get = hns3_dev_xstats_get,
7327 .xstats_get_names = hns3_dev_xstats_get_names,
7328 .xstats_reset = hns3_dev_xstats_reset,
7329 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
7330 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
7331 .dev_infos_get = hns3_dev_infos_get,
7332 .fw_version_get = hns3_fw_version_get,
7333 .rx_queue_setup = hns3_rx_queue_setup,
7334 .tx_queue_setup = hns3_tx_queue_setup,
7335 .rx_queue_release = hns3_dev_rx_queue_release,
7336 .tx_queue_release = hns3_dev_tx_queue_release,
7337 .rx_queue_start = hns3_dev_rx_queue_start,
7338 .rx_queue_stop = hns3_dev_rx_queue_stop,
7339 .tx_queue_start = hns3_dev_tx_queue_start,
7340 .tx_queue_stop = hns3_dev_tx_queue_stop,
7341 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
7342 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
7343 .rxq_info_get = hns3_rxq_info_get,
7344 .txq_info_get = hns3_txq_info_get,
7345 .rx_burst_mode_get = hns3_rx_burst_mode_get,
7346 .tx_burst_mode_get = hns3_tx_burst_mode_get,
7347 .flow_ctrl_get = hns3_flow_ctrl_get,
7348 .flow_ctrl_set = hns3_flow_ctrl_set,
7349 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
7350 .mac_addr_add = hns3_add_mac_addr,
7351 .mac_addr_remove = hns3_remove_mac_addr,
7352 .mac_addr_set = hns3_set_default_mac_addr,
7353 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
7354 .link_update = hns3_dev_link_update,
7355 .rss_hash_update = hns3_dev_rss_hash_update,
7356 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
7357 .reta_update = hns3_dev_rss_reta_update,
7358 .reta_query = hns3_dev_rss_reta_query,
7359 .flow_ops_get = hns3_dev_flow_ops_get,
7360 .vlan_filter_set = hns3_vlan_filter_set,
7361 .vlan_tpid_set = hns3_vlan_tpid_set,
7362 .vlan_offload_set = hns3_vlan_offload_set,
7363 .vlan_pvid_set = hns3_vlan_pvid_set,
7364 .get_reg = hns3_get_regs,
7365 .get_module_info = hns3_get_module_info,
7366 .get_module_eeprom = hns3_get_module_eeprom,
7367 .get_dcb_info = hns3_get_dcb_info,
7368 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
7369 .fec_get_capability = hns3_fec_get_capability,
7370 .fec_get = hns3_fec_get,
7371 .fec_set = hns3_fec_set,
7372 .tm_ops_get = hns3_tm_ops_get,
7373 .tx_done_cleanup = hns3_tx_done_cleanup,
7374 .timesync_enable = hns3_timesync_enable,
7375 .timesync_disable = hns3_timesync_disable,
7376 .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
7377 .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
7378 .timesync_adjust_time = hns3_timesync_adjust_time,
7379 .timesync_read_time = hns3_timesync_read_time,
7380 .timesync_write_time = hns3_timesync_write_time,
7383 static const struct hns3_reset_ops hns3_reset_ops = {
7384 .reset_service = hns3_reset_service,
7385 .stop_service = hns3_stop_service,
7386 .prepare_reset = hns3_prepare_reset,
7387 .wait_hardware_ready = hns3_wait_hardware_ready,
7388 .reinit_dev = hns3_reinit_dev,
7389 .restore_conf = hns3_restore_conf,
7390 .start_service = hns3_start_service,
7394 hns3_dev_init(struct rte_eth_dev *eth_dev)
7396 struct hns3_adapter *hns = eth_dev->data->dev_private;
7397 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
7398 struct rte_ether_addr *eth_addr;
7399 struct hns3_hw *hw = &hns->hw;
7402 PMD_INIT_FUNC_TRACE();
7404 eth_dev->process_private = (struct hns3_process_private *)
7405 rte_zmalloc_socket("hns3_filter_list",
7406 sizeof(struct hns3_process_private),
7407 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
7408 if (eth_dev->process_private == NULL) {
7409 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
7413 hns3_flow_init(eth_dev);
7415 hns3_set_rxtx_function(eth_dev);
7416 eth_dev->dev_ops = &hns3_eth_dev_ops;
7417 eth_dev->rx_queue_count = hns3_rx_queue_count;
7418 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7419 ret = hns3_mp_init_secondary();
7421 PMD_INIT_LOG(ERR, "Failed to init for secondary "
7422 "process, ret = %d", ret);
7423 goto err_mp_init_secondary;
7426 hw->secondary_cnt++;
7430 ret = hns3_mp_init_primary();
7433 "Failed to init for primary process, ret = %d",
7435 goto err_mp_init_primary;
7438 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
7440 hw->data = eth_dev->data;
7441 hns3_parse_devargs(eth_dev);
7444 * Set default max packet size according to the mtu
7445 * default vale in DPDK frame.
7447 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
7449 ret = hns3_reset_init(hw);
7451 goto err_init_reset;
7452 hw->reset.ops = &hns3_reset_ops;
7454 ret = hns3_init_pf(eth_dev);
7456 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
7460 /* Allocate memory for storing MAC addresses */
7461 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
7462 sizeof(struct rte_ether_addr) *
7463 HNS3_UC_MACADDR_NUM, 0);
7464 if (eth_dev->data->mac_addrs == NULL) {
7465 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
7466 "to store MAC addresses",
7467 sizeof(struct rte_ether_addr) *
7468 HNS3_UC_MACADDR_NUM);
7470 goto err_rte_zmalloc;
7473 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
7474 if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
7475 rte_eth_random_addr(hw->mac.mac_addr);
7476 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
7477 (struct rte_ether_addr *)hw->mac.mac_addr);
7478 hns3_warn(hw, "default mac_addr from firmware is an invalid "
7479 "unicast address, using random MAC address %s",
7482 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7483 ð_dev->data->mac_addrs[0]);
7485 hw->adapter_state = HNS3_NIC_INITIALIZED;
7487 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7489 hns3_err(hw, "Reschedule reset service after dev_init");
7490 hns3_schedule_reset(hns);
7492 /* IMP will wait ready flag before reset */
7493 hns3_notify_reset_ready(hw, false);
7496 hns3_info(hw, "hns3 dev initialization successful!");
7500 hns3_uninit_pf(eth_dev);
7503 rte_free(hw->reset.wait_data);
7506 hns3_mp_uninit_primary();
7508 err_mp_init_primary:
7509 err_mp_init_secondary:
7510 eth_dev->dev_ops = NULL;
7511 eth_dev->rx_pkt_burst = NULL;
7512 eth_dev->rx_descriptor_status = NULL;
7513 eth_dev->tx_pkt_burst = NULL;
7514 eth_dev->tx_pkt_prepare = NULL;
7515 eth_dev->tx_descriptor_status = NULL;
7516 rte_free(eth_dev->process_private);
7517 eth_dev->process_private = NULL;
7522 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7524 struct hns3_adapter *hns = eth_dev->data->dev_private;
7525 struct hns3_hw *hw = &hns->hw;
7527 PMD_INIT_FUNC_TRACE();
7529 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7530 rte_free(eth_dev->process_private);
7531 eth_dev->process_private = NULL;
7535 if (hw->adapter_state < HNS3_NIC_CLOSING)
7536 hns3_dev_close(eth_dev);
7538 hw->adapter_state = HNS3_NIC_REMOVED;
7543 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7544 struct rte_pci_device *pci_dev)
7546 return rte_eth_dev_pci_generic_probe(pci_dev,
7547 sizeof(struct hns3_adapter),
7552 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7554 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7557 static const struct rte_pci_id pci_id_hns3_map[] = {
7558 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7559 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7560 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7561 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7562 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7563 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7564 { .vendor_id = 0, }, /* sentinel */
7567 static struct rte_pci_driver rte_hns3_pmd = {
7568 .id_table = pci_id_hns3_map,
7569 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7570 .probe = eth_hns3_pci_probe,
7571 .remove = eth_hns3_pci_remove,
7574 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7575 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7576 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7577 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7578 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7579 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
7580 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");
7581 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE);
7582 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE);