1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
6 #include <rte_bus_pci.h>
7 #include <ethdev_pci.h>
10 #include "hns3_ethdev.h"
11 #include "hns3_logs.h"
12 #include "hns3_rxtx.h"
13 #include "hns3_intr.h"
14 #include "hns3_regs.h"
18 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
19 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
21 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
22 #define HNS3_INVALID_PVID 0xFFFF
24 #define HNS3_FILTER_TYPE_VF 0
25 #define HNS3_FILTER_TYPE_PORT 1
26 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
27 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
28 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
29 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
30 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
31 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
32 | HNS3_FILTER_FE_ROCE_EGRESS_B)
33 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
34 | HNS3_FILTER_FE_ROCE_INGRESS_B)
36 /* Reset related Registers */
37 #define HNS3_GLOBAL_RESET_BIT 0
38 #define HNS3_CORE_RESET_BIT 1
39 #define HNS3_IMP_RESET_BIT 2
40 #define HNS3_FUN_RST_ING_B 0
42 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
43 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
44 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U
45 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
47 #define HNS3_RESET_WAIT_MS 100
48 #define HNS3_RESET_WAIT_CNT 200
50 /* FEC mode order defined in HNS3 hardware */
51 #define HNS3_HW_FEC_MODE_NOFEC 0
52 #define HNS3_HW_FEC_MODE_BASER 1
53 #define HNS3_HW_FEC_MODE_RS 2
56 HNS3_VECTOR0_EVENT_RST,
57 HNS3_VECTOR0_EVENT_MBX,
58 HNS3_VECTOR0_EVENT_ERR,
59 HNS3_VECTOR0_EVENT_OTHER,
62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
63 { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
64 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
65 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
67 { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
68 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
69 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
70 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
72 { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
73 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
74 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
76 { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
77 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
78 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
79 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
81 { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
82 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
83 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
85 { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
86 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
87 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
95 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
97 static int hns3_add_mc_addr(struct hns3_hw *hw,
98 struct rte_ether_addr *mac_addr);
99 static int hns3_remove_mc_addr(struct hns3_hw *hw,
100 struct rte_ether_addr *mac_addr);
101 static int hns3_restore_fec(struct hns3_hw *hw);
102 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
104 void hns3_ether_format_addr(char *buf, uint16_t size,
105 const struct rte_ether_addr *ether_addr)
107 snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
108 ether_addr->addr_bytes[0],
109 ether_addr->addr_bytes[4],
110 ether_addr->addr_bytes[5]);
114 hns3_pf_disable_irq0(struct hns3_hw *hw)
116 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
120 hns3_pf_enable_irq0(struct hns3_hw *hw)
122 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
125 static enum hns3_evt_cause
126 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
129 struct hns3_hw *hw = &hns->hw;
131 rte_atomic16_set(&hw->reset.disable_cmd, 1);
132 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
133 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
135 hw->reset.stats.imp_cnt++;
136 hns3_warn(hw, "IMP reset detected, clear reset status");
138 hns3_schedule_delayed_reset(hns);
139 hns3_warn(hw, "IMP reset detected, don't clear reset status");
142 return HNS3_VECTOR0_EVENT_RST;
145 static enum hns3_evt_cause
146 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
149 struct hns3_hw *hw = &hns->hw;
151 rte_atomic16_set(&hw->reset.disable_cmd, 1);
152 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
153 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
155 hw->reset.stats.global_cnt++;
156 hns3_warn(hw, "Global reset detected, clear reset status");
158 hns3_schedule_delayed_reset(hns);
160 "Global reset detected, don't clear reset status");
163 return HNS3_VECTOR0_EVENT_RST;
166 static enum hns3_evt_cause
167 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
169 struct hns3_hw *hw = &hns->hw;
170 uint32_t vector0_int_stats;
171 uint32_t cmdq_src_val;
172 uint32_t hw_err_src_reg;
174 enum hns3_evt_cause ret;
177 /* fetch the events from their corresponding regs */
178 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
179 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
180 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
182 is_delay = clearval == NULL ? true : false;
184 * Assumption: If by any chance reset and mailbox events are reported
185 * together then we will only process reset event and defer the
186 * processing of the mailbox events. Since, we would have not cleared
187 * RX CMDQ event this time we would receive again another interrupt
188 * from H/W just for the mailbox.
190 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
191 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
196 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
197 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
201 /* check for vector0 msix event source */
202 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
203 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
204 val = vector0_int_stats | hw_err_src_reg;
205 ret = HNS3_VECTOR0_EVENT_ERR;
209 /* check for vector0 mailbox(=CMDQ RX) event source */
210 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
211 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
213 ret = HNS3_VECTOR0_EVENT_MBX;
217 if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
218 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
219 vector0_int_stats, cmdq_src_val, hw_err_src_reg);
220 val = vector0_int_stats;
221 ret = HNS3_VECTOR0_EVENT_OTHER;
230 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
232 if (event_type == HNS3_VECTOR0_EVENT_RST)
233 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
234 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
235 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
239 hns3_clear_all_event_cause(struct hns3_hw *hw)
241 uint32_t vector0_int_stats;
242 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
244 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
245 hns3_warn(hw, "Probe during IMP reset interrupt");
247 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
248 hns3_warn(hw, "Probe during Global reset interrupt");
250 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
251 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
252 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
253 BIT(HNS3_VECTOR0_CORERESET_INT_B));
254 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
258 hns3_interrupt_handler(void *param)
260 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
261 struct hns3_adapter *hns = dev->data->dev_private;
262 struct hns3_hw *hw = &hns->hw;
263 enum hns3_evt_cause event_cause;
264 uint32_t clearval = 0;
266 /* Disable interrupt */
267 hns3_pf_disable_irq0(hw);
269 event_cause = hns3_check_event_cause(hns, &clearval);
270 /* vector 0 interrupt is shared with reset and mailbox source events. */
271 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
272 hns3_warn(hw, "Received err interrupt");
273 hns3_handle_msix_error(hns, &hw->reset.request);
274 hns3_handle_ras_error(hns, &hw->reset.request);
275 hns3_schedule_reset(hns);
276 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
277 hns3_warn(hw, "Received reset interrupt");
278 hns3_schedule_reset(hns);
279 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
280 hns3_dev_handle_mbx_msg(hw);
282 hns3_err(hw, "Received unknown event");
284 hns3_clear_event_cause(hw, event_cause, clearval);
285 /* Enable interrupt if it is not cause by reset */
286 hns3_pf_enable_irq0(hw);
290 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
292 #define HNS3_VLAN_ID_OFFSET_STEP 160
293 #define HNS3_VLAN_BYTE_SIZE 8
294 struct hns3_vlan_filter_pf_cfg_cmd *req;
295 struct hns3_hw *hw = &hns->hw;
296 uint8_t vlan_offset_byte_val;
297 struct hns3_cmd_desc desc;
298 uint8_t vlan_offset_byte;
299 uint8_t vlan_offset_base;
302 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
304 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
305 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
307 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
309 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
310 req->vlan_offset = vlan_offset_base;
311 req->vlan_cfg = on ? 0 : 1;
312 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
314 ret = hns3_cmd_send(hw, &desc, 1);
316 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
323 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
325 struct hns3_user_vlan_table *vlan_entry;
326 struct hns3_pf *pf = &hns->pf;
328 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
329 if (vlan_entry->vlan_id == vlan_id) {
330 if (vlan_entry->hd_tbl_status)
331 hns3_set_port_vlan_filter(hns, vlan_id, 0);
332 LIST_REMOVE(vlan_entry, next);
333 rte_free(vlan_entry);
340 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
343 struct hns3_user_vlan_table *vlan_entry;
344 struct hns3_hw *hw = &hns->hw;
345 struct hns3_pf *pf = &hns->pf;
347 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
348 if (vlan_entry->vlan_id == vlan_id)
352 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
353 if (vlan_entry == NULL) {
354 hns3_err(hw, "Failed to malloc hns3 vlan table");
358 vlan_entry->hd_tbl_status = writen_to_tbl;
359 vlan_entry->vlan_id = vlan_id;
361 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
365 hns3_restore_vlan_table(struct hns3_adapter *hns)
367 struct hns3_user_vlan_table *vlan_entry;
368 struct hns3_hw *hw = &hns->hw;
369 struct hns3_pf *pf = &hns->pf;
373 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
374 return hns3_vlan_pvid_configure(hns,
375 hw->port_base_vlan_cfg.pvid, 1);
377 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
378 if (vlan_entry->hd_tbl_status) {
379 vlan_id = vlan_entry->vlan_id;
380 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
390 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
392 struct hns3_hw *hw = &hns->hw;
393 bool writen_to_tbl = false;
397 * When vlan filter is enabled, hardware regards packets without vlan
398 * as packets with vlan 0. So, to receive packets without vlan, vlan id
399 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
401 if (on == 0 && vlan_id == 0)
405 * When port base vlan enabled, we use port base vlan as the vlan
406 * filter condition. In this case, we don't update vlan filter table
407 * when user add new vlan or remove exist vlan, just update the
408 * vlan list. The vlan id in vlan list will be writen in vlan filter
409 * table until port base vlan disabled
411 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
412 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
413 writen_to_tbl = true;
418 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
420 hns3_rm_dev_vlan_table(hns, vlan_id);
426 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
428 struct hns3_adapter *hns = dev->data->dev_private;
429 struct hns3_hw *hw = &hns->hw;
432 rte_spinlock_lock(&hw->lock);
433 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
434 rte_spinlock_unlock(&hw->lock);
439 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
442 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
443 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
444 struct hns3_hw *hw = &hns->hw;
445 struct hns3_cmd_desc desc;
448 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
449 vlan_type != ETH_VLAN_TYPE_OUTER)) {
450 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
454 if (tpid != RTE_ETHER_TYPE_VLAN) {
455 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
459 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
460 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
462 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
463 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
464 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
465 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
466 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
467 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
468 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
469 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
472 ret = hns3_cmd_send(hw, &desc, 1);
474 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
479 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
481 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
482 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
483 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
485 ret = hns3_cmd_send(hw, &desc, 1);
487 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
493 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
496 struct hns3_adapter *hns = dev->data->dev_private;
497 struct hns3_hw *hw = &hns->hw;
500 rte_spinlock_lock(&hw->lock);
501 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
502 rte_spinlock_unlock(&hw->lock);
507 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
508 struct hns3_rx_vtag_cfg *vcfg)
510 struct hns3_vport_vtag_rx_cfg_cmd *req;
511 struct hns3_hw *hw = &hns->hw;
512 struct hns3_cmd_desc desc;
517 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
519 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
520 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
521 vcfg->strip_tag1_en ? 1 : 0);
522 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
523 vcfg->strip_tag2_en ? 1 : 0);
524 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
525 vcfg->vlan1_vlan_prionly ? 1 : 0);
526 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
527 vcfg->vlan2_vlan_prionly ? 1 : 0);
529 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
530 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
531 vcfg->strip_tag1_discard_en ? 1 : 0);
532 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
533 vcfg->strip_tag2_discard_en ? 1 : 0);
535 * In current version VF is not supported when PF is driven by DPDK
536 * driver, just need to configure parameters for PF vport.
538 vport_id = HNS3_PF_FUNC_ID;
539 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
540 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
541 req->vf_bitmap[req->vf_offset] = bitmap;
543 ret = hns3_cmd_send(hw, &desc, 1);
545 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
550 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
551 struct hns3_rx_vtag_cfg *vcfg)
553 struct hns3_pf *pf = &hns->pf;
554 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
558 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
559 struct hns3_tx_vtag_cfg *vcfg)
561 struct hns3_pf *pf = &hns->pf;
562 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
566 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
568 struct hns3_rx_vtag_cfg rxvlan_cfg;
569 struct hns3_hw *hw = &hns->hw;
572 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
573 rxvlan_cfg.strip_tag1_en = false;
574 rxvlan_cfg.strip_tag2_en = enable;
575 rxvlan_cfg.strip_tag2_discard_en = false;
577 rxvlan_cfg.strip_tag1_en = enable;
578 rxvlan_cfg.strip_tag2_en = true;
579 rxvlan_cfg.strip_tag2_discard_en = true;
582 rxvlan_cfg.strip_tag1_discard_en = false;
583 rxvlan_cfg.vlan1_vlan_prionly = false;
584 rxvlan_cfg.vlan2_vlan_prionly = false;
585 rxvlan_cfg.rx_vlan_offload_en = enable;
587 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
589 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
593 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
599 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
600 uint8_t fe_type, bool filter_en, uint8_t vf_id)
602 struct hns3_vlan_filter_ctrl_cmd *req;
603 struct hns3_cmd_desc desc;
606 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
608 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
609 req->vlan_type = vlan_type;
610 req->vlan_fe = filter_en ? fe_type : 0;
613 ret = hns3_cmd_send(hw, &desc, 1);
615 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
621 hns3_vlan_filter_init(struct hns3_adapter *hns)
623 struct hns3_hw *hw = &hns->hw;
626 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
627 HNS3_FILTER_FE_EGRESS, false,
630 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
634 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
635 HNS3_FILTER_FE_INGRESS, false,
638 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
644 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
646 struct hns3_hw *hw = &hns->hw;
649 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
650 HNS3_FILTER_FE_INGRESS, enable,
653 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
654 enable ? "enable" : "disable", ret);
660 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
662 struct hns3_adapter *hns = dev->data->dev_private;
663 struct hns3_hw *hw = &hns->hw;
664 struct rte_eth_rxmode *rxmode;
665 unsigned int tmp_mask;
669 rte_spinlock_lock(&hw->lock);
670 rxmode = &dev->data->dev_conf.rxmode;
671 tmp_mask = (unsigned int)mask;
672 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
673 /* ignore vlan filter configuration during promiscuous mode */
674 if (!dev->data->promiscuous) {
675 /* Enable or disable VLAN filter */
676 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
679 ret = hns3_enable_vlan_filter(hns, enable);
681 rte_spinlock_unlock(&hw->lock);
682 hns3_err(hw, "failed to %s rx filter, ret = %d",
683 enable ? "enable" : "disable", ret);
689 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
690 /* Enable or disable VLAN stripping */
691 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
694 ret = hns3_en_hw_strip_rxvtag(hns, enable);
696 rte_spinlock_unlock(&hw->lock);
697 hns3_err(hw, "failed to %s rx strip, ret = %d",
698 enable ? "enable" : "disable", ret);
703 rte_spinlock_unlock(&hw->lock);
709 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
710 struct hns3_tx_vtag_cfg *vcfg)
712 struct hns3_vport_vtag_tx_cfg_cmd *req;
713 struct hns3_cmd_desc desc;
714 struct hns3_hw *hw = &hns->hw;
719 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
721 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
722 req->def_vlan_tag1 = vcfg->default_tag1;
723 req->def_vlan_tag2 = vcfg->default_tag2;
724 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
725 vcfg->accept_tag1 ? 1 : 0);
726 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
727 vcfg->accept_untag1 ? 1 : 0);
728 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
729 vcfg->accept_tag2 ? 1 : 0);
730 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
731 vcfg->accept_untag2 ? 1 : 0);
732 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
733 vcfg->insert_tag1_en ? 1 : 0);
734 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
735 vcfg->insert_tag2_en ? 1 : 0);
736 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
738 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
739 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
740 vcfg->tag_shift_mode_en ? 1 : 0);
743 * In current version VF is not supported when PF is driven by DPDK
744 * driver, just need to configure parameters for PF vport.
746 vport_id = HNS3_PF_FUNC_ID;
747 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
748 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
749 req->vf_bitmap[req->vf_offset] = bitmap;
751 ret = hns3_cmd_send(hw, &desc, 1);
753 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
759 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
762 struct hns3_hw *hw = &hns->hw;
763 struct hns3_tx_vtag_cfg txvlan_cfg;
766 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
767 txvlan_cfg.accept_tag1 = true;
768 txvlan_cfg.insert_tag1_en = false;
769 txvlan_cfg.default_tag1 = 0;
771 txvlan_cfg.accept_tag1 =
772 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
773 txvlan_cfg.insert_tag1_en = true;
774 txvlan_cfg.default_tag1 = pvid;
777 txvlan_cfg.accept_untag1 = true;
778 txvlan_cfg.accept_tag2 = true;
779 txvlan_cfg.accept_untag2 = true;
780 txvlan_cfg.insert_tag2_en = false;
781 txvlan_cfg.default_tag2 = 0;
782 txvlan_cfg.tag_shift_mode_en = true;
784 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
786 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
791 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
797 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
799 struct hns3_user_vlan_table *vlan_entry;
800 struct hns3_pf *pf = &hns->pf;
802 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
803 if (vlan_entry->hd_tbl_status) {
804 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
805 vlan_entry->hd_tbl_status = false;
810 vlan_entry = LIST_FIRST(&pf->vlan_list);
812 LIST_REMOVE(vlan_entry, next);
813 rte_free(vlan_entry);
814 vlan_entry = LIST_FIRST(&pf->vlan_list);
820 hns3_add_all_vlan_table(struct hns3_adapter *hns)
822 struct hns3_user_vlan_table *vlan_entry;
823 struct hns3_pf *pf = &hns->pf;
825 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
826 if (!vlan_entry->hd_tbl_status) {
827 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
828 vlan_entry->hd_tbl_status = true;
834 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
836 struct hns3_hw *hw = &hns->hw;
839 hns3_rm_all_vlan_table(hns, true);
840 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
841 ret = hns3_set_port_vlan_filter(hns,
842 hw->port_base_vlan_cfg.pvid, 0);
844 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
852 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
853 uint16_t port_base_vlan_state, uint16_t new_pvid)
855 struct hns3_hw *hw = &hns->hw;
859 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
860 old_pvid = hw->port_base_vlan_cfg.pvid;
861 if (old_pvid != HNS3_INVALID_PVID) {
862 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
864 hns3_err(hw, "failed to remove old pvid %u, "
865 "ret = %d", old_pvid, ret);
870 hns3_rm_all_vlan_table(hns, false);
871 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
873 hns3_err(hw, "failed to add new pvid %u, ret = %d",
878 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
880 hns3_err(hw, "failed to remove pvid %u, ret = %d",
885 hns3_add_all_vlan_table(hns);
891 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
893 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
894 struct hns3_rx_vtag_cfg rx_vlan_cfg;
898 rx_strip_en = old_cfg->rx_vlan_offload_en;
900 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
901 rx_vlan_cfg.strip_tag2_en = true;
902 rx_vlan_cfg.strip_tag2_discard_en = true;
904 rx_vlan_cfg.strip_tag1_en = false;
905 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
906 rx_vlan_cfg.strip_tag2_discard_en = false;
908 rx_vlan_cfg.strip_tag1_discard_en = false;
909 rx_vlan_cfg.vlan1_vlan_prionly = false;
910 rx_vlan_cfg.vlan2_vlan_prionly = false;
911 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
913 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
917 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
922 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
924 struct hns3_hw *hw = &hns->hw;
925 uint16_t port_base_vlan_state;
928 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
929 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
930 hns3_warn(hw, "Invalid operation! As current pvid set "
931 "is %u, disable pvid %u is invalid",
932 hw->port_base_vlan_cfg.pvid, pvid);
936 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
937 HNS3_PORT_BASE_VLAN_DISABLE;
938 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
940 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
945 ret = hns3_en_pvid_strip(hns, on);
947 hns3_err(hw, "failed to config rx vlan strip for pvid, "
952 if (pvid == HNS3_INVALID_PVID)
954 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
956 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
962 hw->port_base_vlan_cfg.state = port_base_vlan_state;
963 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
968 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
970 struct hns3_adapter *hns = dev->data->dev_private;
971 struct hns3_hw *hw = &hns->hw;
972 bool pvid_en_state_change;
976 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
977 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
978 RTE_ETHER_MAX_VLAN_ID);
983 * If PVID configuration state change, should refresh the PVID
984 * configuration state in struct hns3_tx_queue/hns3_rx_queue.
986 pvid_state = hw->port_base_vlan_cfg.state;
987 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
988 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
989 pvid_en_state_change = false;
991 pvid_en_state_change = true;
993 rte_spinlock_lock(&hw->lock);
994 ret = hns3_vlan_pvid_configure(hns, pvid, on);
995 rte_spinlock_unlock(&hw->lock);
999 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1000 * need be processed by PMD driver.
1002 if (pvid_en_state_change &&
1003 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1004 hns3_update_all_queues_pvid_proc_en(hw);
1010 hns3_default_vlan_config(struct hns3_adapter *hns)
1012 struct hns3_hw *hw = &hns->hw;
1016 * When vlan filter is enabled, hardware regards packets without vlan
1017 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1018 * table, packets without vlan won't be received. So, add vlan 0 as
1021 ret = hns3_vlan_filter_configure(hns, 0, 1);
1023 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1028 hns3_init_vlan_config(struct hns3_adapter *hns)
1030 struct hns3_hw *hw = &hns->hw;
1034 * This function can be called in the initialization and reset process,
1035 * when in reset process, it means that hardware had been reseted
1036 * successfully and we need to restore the hardware configuration to
1037 * ensure that the hardware configuration remains unchanged before and
1040 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1041 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1042 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1045 ret = hns3_vlan_filter_init(hns);
1047 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1051 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1052 RTE_ETHER_TYPE_VLAN);
1054 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1059 * When in the reinit dev stage of the reset process, the following
1060 * vlan-related configurations may differ from those at initialization,
1061 * we will restore configurations to hardware in hns3_restore_vlan_table
1062 * and hns3_restore_vlan_conf later.
1064 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1065 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1067 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1071 ret = hns3_en_hw_strip_rxvtag(hns, false);
1073 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1079 return hns3_default_vlan_config(hns);
1083 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1085 struct hns3_pf *pf = &hns->pf;
1086 struct hns3_hw *hw = &hns->hw;
1091 if (!hw->data->promiscuous) {
1092 /* restore vlan filter states */
1093 offloads = hw->data->dev_conf.rxmode.offloads;
1094 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1095 ret = hns3_enable_vlan_filter(hns, enable);
1097 hns3_err(hw, "failed to restore vlan rx filter conf, "
1103 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1105 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1109 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1111 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1117 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1119 struct hns3_adapter *hns = dev->data->dev_private;
1120 struct rte_eth_dev_data *data = dev->data;
1121 struct rte_eth_txmode *txmode;
1122 struct hns3_hw *hw = &hns->hw;
1126 txmode = &data->dev_conf.txmode;
1127 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1129 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1130 "configuration is not supported! Ignore these two "
1131 "parameters: hw_vlan_reject_tagged(%u), "
1132 "hw_vlan_reject_untagged(%u)",
1133 txmode->hw_vlan_reject_tagged,
1134 txmode->hw_vlan_reject_untagged);
1136 /* Apply vlan offload setting */
1137 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1138 ret = hns3_vlan_offload_set(dev, mask);
1140 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1146 * If pvid config is not set in rte_eth_conf, driver needn't to set
1147 * VLAN pvid related configuration to hardware.
1149 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1152 /* Apply pvid setting */
1153 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1154 txmode->hw_vlan_insert_pvid);
1156 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1163 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1164 unsigned int tso_mss_max)
1166 struct hns3_cfg_tso_status_cmd *req;
1167 struct hns3_cmd_desc desc;
1170 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1172 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1175 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1177 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1180 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1182 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1184 return hns3_cmd_send(hw, &desc, 1);
1188 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1189 uint16_t *allocated_size, bool is_alloc)
1191 struct hns3_umv_spc_alc_cmd *req;
1192 struct hns3_cmd_desc desc;
1195 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1196 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1197 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1198 req->space_size = rte_cpu_to_le_32(space_size);
1200 ret = hns3_cmd_send(hw, &desc, 1);
1202 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1203 is_alloc ? "allocate" : "free", ret);
1207 if (is_alloc && allocated_size)
1208 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1214 hns3_init_umv_space(struct hns3_hw *hw)
1216 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1217 struct hns3_pf *pf = &hns->pf;
1218 uint16_t allocated_size = 0;
1221 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1226 if (allocated_size < pf->wanted_umv_size)
1227 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1228 pf->wanted_umv_size, allocated_size);
1230 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1231 pf->wanted_umv_size;
1232 pf->used_umv_size = 0;
1237 hns3_uninit_umv_space(struct hns3_hw *hw)
1239 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1240 struct hns3_pf *pf = &hns->pf;
1243 if (pf->max_umv_size == 0)
1246 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1250 pf->max_umv_size = 0;
1256 hns3_is_umv_space_full(struct hns3_hw *hw)
1258 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1259 struct hns3_pf *pf = &hns->pf;
1262 is_full = (pf->used_umv_size >= pf->max_umv_size);
1268 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1270 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1271 struct hns3_pf *pf = &hns->pf;
1274 if (pf->used_umv_size > 0)
1275 pf->used_umv_size--;
1277 pf->used_umv_size++;
1281 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1282 const uint8_t *addr, bool is_mc)
1284 const unsigned char *mac_addr = addr;
1285 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1286 ((uint32_t)mac_addr[2] << 16) |
1287 ((uint32_t)mac_addr[1] << 8) |
1288 (uint32_t)mac_addr[0];
1289 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1291 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1293 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1294 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1295 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1298 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1299 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1303 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1305 enum hns3_mac_vlan_tbl_opcode op)
1308 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1313 if (op == HNS3_MAC_VLAN_ADD) {
1314 if (resp_code == 0 || resp_code == 1) {
1316 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1317 hns3_err(hw, "add mac addr failed for uc_overflow");
1319 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1320 hns3_err(hw, "add mac addr failed for mc_overflow");
1324 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1327 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1328 if (resp_code == 0) {
1330 } else if (resp_code == 1) {
1331 hns3_dbg(hw, "remove mac addr failed for miss");
1335 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1338 } else if (op == HNS3_MAC_VLAN_LKUP) {
1339 if (resp_code == 0) {
1341 } else if (resp_code == 1) {
1342 hns3_dbg(hw, "lookup mac addr failed for miss");
1346 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1351 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1358 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1359 struct hns3_mac_vlan_tbl_entry_cmd *req,
1360 struct hns3_cmd_desc *desc, bool is_mc)
1366 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1368 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1369 memcpy(desc[0].data, req,
1370 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1371 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1373 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1374 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1376 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1378 memcpy(desc[0].data, req,
1379 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1380 ret = hns3_cmd_send(hw, desc, 1);
1383 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1387 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1388 retval = rte_le_to_cpu_16(desc[0].retval);
1390 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1391 HNS3_MAC_VLAN_LKUP);
1395 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1396 struct hns3_mac_vlan_tbl_entry_cmd *req,
1397 struct hns3_cmd_desc *mc_desc)
1404 if (mc_desc == NULL) {
1405 struct hns3_cmd_desc desc;
1407 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1408 memcpy(desc.data, req,
1409 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1410 ret = hns3_cmd_send(hw, &desc, 1);
1411 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1412 retval = rte_le_to_cpu_16(desc.retval);
1414 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1417 hns3_cmd_reuse_desc(&mc_desc[0], false);
1418 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1419 hns3_cmd_reuse_desc(&mc_desc[1], false);
1420 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1421 hns3_cmd_reuse_desc(&mc_desc[2], false);
1422 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1423 memcpy(mc_desc[0].data, req,
1424 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1425 mc_desc[0].retval = 0;
1426 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1427 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1428 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1430 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1435 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1443 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1444 struct hns3_mac_vlan_tbl_entry_cmd *req)
1446 struct hns3_cmd_desc desc;
1451 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1453 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1455 ret = hns3_cmd_send(hw, &desc, 1);
1457 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1460 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1461 retval = rte_le_to_cpu_16(desc.retval);
1463 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1464 HNS3_MAC_VLAN_REMOVE);
1468 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1470 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1471 struct hns3_mac_vlan_tbl_entry_cmd req;
1472 struct hns3_pf *pf = &hns->pf;
1473 struct hns3_cmd_desc desc[3];
1474 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1475 uint16_t egress_port = 0;
1479 /* check if mac addr is valid */
1480 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1481 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1483 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1488 memset(&req, 0, sizeof(req));
1491 * In current version VF is not supported when PF is driven by DPDK
1492 * driver, just need to configure parameters for PF vport.
1494 vf_id = HNS3_PF_FUNC_ID;
1495 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1496 HNS3_MAC_EPORT_VFID_S, vf_id);
1498 req.egress_port = rte_cpu_to_le_16(egress_port);
1500 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1503 * Lookup the mac address in the mac_vlan table, and add
1504 * it if the entry is inexistent. Repeated unicast entry
1505 * is not allowed in the mac vlan table.
1507 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1508 if (ret == -ENOENT) {
1509 if (!hns3_is_umv_space_full(hw)) {
1510 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1512 hns3_update_umv_space(hw, false);
1516 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1521 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1523 /* check if we just hit the duplicate */
1525 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1529 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1536 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1538 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1539 struct rte_ether_addr *addr;
1543 for (i = 0; i < hw->mc_addrs_num; i++) {
1544 addr = &hw->mc_addrs[i];
1545 /* Check if there are duplicate addresses */
1546 if (rte_is_same_ether_addr(addr, mac_addr)) {
1547 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1549 hns3_err(hw, "failed to add mc mac addr, same addrs"
1550 "(%s) is added by the set_mc_mac_addr_list "
1556 ret = hns3_add_mc_addr(hw, mac_addr);
1558 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1560 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1567 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1569 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1572 ret = hns3_remove_mc_addr(hw, mac_addr);
1574 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1576 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1583 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1584 uint32_t idx, __rte_unused uint32_t pool)
1586 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1587 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1590 rte_spinlock_lock(&hw->lock);
1593 * In hns3 network engine adding UC and MC mac address with different
1594 * commands with firmware. We need to determine whether the input
1595 * address is a UC or a MC address to call different commands.
1596 * By the way, it is recommended calling the API function named
1597 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1598 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1599 * may affect the specifications of UC mac addresses.
1601 if (rte_is_multicast_ether_addr(mac_addr))
1602 ret = hns3_add_mc_addr_common(hw, mac_addr);
1604 ret = hns3_add_uc_addr_common(hw, mac_addr);
1607 rte_spinlock_unlock(&hw->lock);
1608 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1610 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1616 hw->mac.default_addr_setted = true;
1617 rte_spinlock_unlock(&hw->lock);
1623 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1625 struct hns3_mac_vlan_tbl_entry_cmd req;
1626 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1629 /* check if mac addr is valid */
1630 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1631 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1633 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1638 memset(&req, 0, sizeof(req));
1639 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1640 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1641 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1642 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1645 hns3_update_umv_space(hw, true);
1651 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1653 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654 /* index will be checked by upper level rte interface */
1655 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1656 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1659 rte_spinlock_lock(&hw->lock);
1661 if (rte_is_multicast_ether_addr(mac_addr))
1662 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1664 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1665 rte_spinlock_unlock(&hw->lock);
1667 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1669 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1675 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1676 struct rte_ether_addr *mac_addr)
1678 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1679 struct rte_ether_addr *oaddr;
1680 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1681 bool default_addr_setted;
1682 bool rm_succes = false;
1686 * It has been guaranteed that input parameter named mac_addr is valid
1687 * address in the rte layer of DPDK framework.
1689 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1690 default_addr_setted = hw->mac.default_addr_setted;
1691 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1694 rte_spinlock_lock(&hw->lock);
1695 if (default_addr_setted) {
1696 ret = hns3_remove_uc_addr_common(hw, oaddr);
1698 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1700 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1707 ret = hns3_add_uc_addr_common(hw, mac_addr);
1709 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1711 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1712 goto err_add_uc_addr;
1715 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1717 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1718 goto err_pause_addr_cfg;
1721 rte_ether_addr_copy(mac_addr,
1722 (struct rte_ether_addr *)hw->mac.mac_addr);
1723 hw->mac.default_addr_setted = true;
1724 rte_spinlock_unlock(&hw->lock);
1729 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1731 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1734 "Failed to roll back to del setted mac addr(%s): %d",
1740 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1742 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1745 "Failed to restore old uc mac addr(%s): %d",
1747 hw->mac.default_addr_setted = false;
1750 rte_spinlock_unlock(&hw->lock);
1756 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1758 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1759 struct hns3_hw *hw = &hns->hw;
1760 struct rte_ether_addr *addr;
1765 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1766 addr = &hw->data->mac_addrs[i];
1767 if (rte_is_zero_ether_addr(addr))
1769 if (rte_is_multicast_ether_addr(addr))
1770 ret = del ? hns3_remove_mc_addr(hw, addr) :
1771 hns3_add_mc_addr(hw, addr);
1773 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1774 hns3_add_uc_addr_common(hw, addr);
1778 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1780 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1781 "ret = %d.", del ? "remove" : "restore",
1789 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1791 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1795 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1796 word_num = vfid / 32;
1797 bit_num = vfid % 32;
1799 desc[1].data[word_num] &=
1800 rte_cpu_to_le_32(~(1UL << bit_num));
1802 desc[1].data[word_num] |=
1803 rte_cpu_to_le_32(1UL << bit_num);
1805 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1806 bit_num = vfid % 32;
1808 desc[2].data[word_num] &=
1809 rte_cpu_to_le_32(~(1UL << bit_num));
1811 desc[2].data[word_num] |=
1812 rte_cpu_to_le_32(1UL << bit_num);
1817 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1819 struct hns3_mac_vlan_tbl_entry_cmd req;
1820 struct hns3_cmd_desc desc[3];
1821 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1825 /* Check if mac addr is valid */
1826 if (!rte_is_multicast_ether_addr(mac_addr)) {
1827 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1829 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1834 memset(&req, 0, sizeof(req));
1835 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1836 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1837 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1839 /* This mac addr do not exist, add new entry for it */
1840 memset(desc[0].data, 0, sizeof(desc[0].data));
1841 memset(desc[1].data, 0, sizeof(desc[0].data));
1842 memset(desc[2].data, 0, sizeof(desc[0].data));
1846 * In current version VF is not supported when PF is driven by DPDK
1847 * driver, just need to configure parameters for PF vport.
1849 vf_id = HNS3_PF_FUNC_ID;
1850 hns3_update_desc_vfid(desc, vf_id, false);
1851 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1854 hns3_err(hw, "mc mac vlan table is full");
1855 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1857 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1864 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1866 struct hns3_mac_vlan_tbl_entry_cmd req;
1867 struct hns3_cmd_desc desc[3];
1868 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1872 /* Check if mac addr is valid */
1873 if (!rte_is_multicast_ether_addr(mac_addr)) {
1874 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1876 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1881 memset(&req, 0, sizeof(req));
1882 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1883 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1884 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1887 * This mac addr exist, remove this handle's VFID for it.
1888 * In current version VF is not supported when PF is driven by
1889 * DPDK driver, just need to configure parameters for PF vport.
1891 vf_id = HNS3_PF_FUNC_ID;
1892 hns3_update_desc_vfid(desc, vf_id, true);
1894 /* All the vfid is zero, so need to delete this entry */
1895 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1896 } else if (ret == -ENOENT) {
1897 /* This mac addr doesn't exist. */
1902 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1904 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1911 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1912 struct rte_ether_addr *mc_addr_set,
1913 uint32_t nb_mc_addr)
1915 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1916 struct rte_ether_addr *addr;
1920 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1921 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1922 "invalid. valid range: 0~%d",
1923 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1927 /* Check if input mac addresses are valid */
1928 for (i = 0; i < nb_mc_addr; i++) {
1929 addr = &mc_addr_set[i];
1930 if (!rte_is_multicast_ether_addr(addr)) {
1931 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1934 "failed to set mc mac addr, addr(%s) invalid.",
1939 /* Check if there are duplicate addresses */
1940 for (j = i + 1; j < nb_mc_addr; j++) {
1941 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1942 hns3_ether_format_addr(mac_str,
1943 RTE_ETHER_ADDR_FMT_SIZE,
1945 hns3_err(hw, "failed to set mc mac addr, "
1946 "addrs invalid. two same addrs(%s).",
1953 * Check if there are duplicate addresses between mac_addrs
1956 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1957 if (rte_is_same_ether_addr(addr,
1958 &hw->data->mac_addrs[j])) {
1959 hns3_ether_format_addr(mac_str,
1960 RTE_ETHER_ADDR_FMT_SIZE,
1962 hns3_err(hw, "failed to set mc mac addr, "
1963 "addrs invalid. addrs(%s) has already "
1964 "configured in mac_addr add API",
1975 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1976 struct rte_ether_addr *mc_addr_set,
1978 struct rte_ether_addr *reserved_addr_list,
1979 int *reserved_addr_num,
1980 struct rte_ether_addr *add_addr_list,
1982 struct rte_ether_addr *rm_addr_list,
1985 struct rte_ether_addr *addr;
1986 int current_addr_num;
1987 int reserved_num = 0;
1995 /* Calculate the mc mac address list that should be removed */
1996 current_addr_num = hw->mc_addrs_num;
1997 for (i = 0; i < current_addr_num; i++) {
1998 addr = &hw->mc_addrs[i];
2000 for (j = 0; j < mc_addr_num; j++) {
2001 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2008 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2011 rte_ether_addr_copy(addr,
2012 &reserved_addr_list[reserved_num]);
2017 /* Calculate the mc mac address list that should be added */
2018 for (i = 0; i < mc_addr_num; i++) {
2019 addr = &mc_addr_set[i];
2021 for (j = 0; j < current_addr_num; j++) {
2022 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2029 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2034 /* Reorder the mc mac address list maintained by driver */
2035 for (i = 0; i < reserved_num; i++)
2036 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2038 for (i = 0; i < rm_num; i++) {
2039 num = reserved_num + i;
2040 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2043 *reserved_addr_num = reserved_num;
2044 *add_addr_num = add_num;
2045 *rm_addr_num = rm_num;
2049 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2050 struct rte_ether_addr *mc_addr_set,
2051 uint32_t nb_mc_addr)
2053 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2054 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2055 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2056 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2057 struct rte_ether_addr *addr;
2058 int reserved_addr_num;
2066 /* Check if input parameters are valid */
2067 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2071 rte_spinlock_lock(&hw->lock);
2074 * Calculate the mc mac address lists those should be removed and be
2075 * added, Reorder the mc mac address list maintained by driver.
2077 mc_addr_num = (int)nb_mc_addr;
2078 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2079 reserved_addr_list, &reserved_addr_num,
2080 add_addr_list, &add_addr_num,
2081 rm_addr_list, &rm_addr_num);
2083 /* Remove mc mac addresses */
2084 for (i = 0; i < rm_addr_num; i++) {
2085 num = rm_addr_num - i - 1;
2086 addr = &rm_addr_list[num];
2087 ret = hns3_remove_mc_addr(hw, addr);
2089 rte_spinlock_unlock(&hw->lock);
2095 /* Add mc mac addresses */
2096 for (i = 0; i < add_addr_num; i++) {
2097 addr = &add_addr_list[i];
2098 ret = hns3_add_mc_addr(hw, addr);
2100 rte_spinlock_unlock(&hw->lock);
2104 num = reserved_addr_num + i;
2105 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2108 rte_spinlock_unlock(&hw->lock);
2114 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2116 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2117 struct hns3_hw *hw = &hns->hw;
2118 struct rte_ether_addr *addr;
2123 for (i = 0; i < hw->mc_addrs_num; i++) {
2124 addr = &hw->mc_addrs[i];
2125 if (!rte_is_multicast_ether_addr(addr))
2128 ret = hns3_remove_mc_addr(hw, addr);
2130 ret = hns3_add_mc_addr(hw, addr);
2133 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2135 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2136 del ? "Remove" : "Restore", mac_str, ret);
2143 hns3_check_mq_mode(struct rte_eth_dev *dev)
2145 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2146 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2147 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2149 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2150 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2155 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2156 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2158 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2159 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2160 "rx_mq_mode = %d", rx_mq_mode);
2164 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2165 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2166 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2167 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2168 rx_mq_mode, tx_mq_mode);
2172 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2173 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2174 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2175 dcb_rx_conf->nb_tcs, pf->tc_max);
2179 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2180 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2181 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2182 "nb_tcs(%d) != %d or %d in rx direction.",
2183 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2187 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2188 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2189 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2193 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2194 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2195 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2196 "is not equal to one in tx direction.",
2197 i, dcb_rx_conf->dcb_tc[i]);
2200 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2201 max_tc = dcb_rx_conf->dcb_tc[i];
2204 num_tc = max_tc + 1;
2205 if (num_tc > dcb_rx_conf->nb_tcs) {
2206 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2207 num_tc, dcb_rx_conf->nb_tcs);
2216 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2218 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2220 if (!hns3_dev_dcb_supported(hw)) {
2221 hns3_err(hw, "this port does not support dcb configurations.");
2225 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2226 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2230 /* Check multiple queue mode */
2231 return hns3_check_mq_mode(dev);
2235 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2236 enum hns3_ring_type queue_type, uint16_t queue_id)
2238 struct hns3_cmd_desc desc;
2239 struct hns3_ctrl_vector_chain_cmd *req =
2240 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2241 enum hns3_cmd_status status;
2242 enum hns3_opcode_type op;
2243 uint16_t tqp_type_and_id = 0;
2247 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2248 hns3_cmd_setup_basic_desc(&desc, op, false);
2249 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2250 HNS3_TQP_INT_ID_L_S);
2251 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2252 HNS3_TQP_INT_ID_H_S);
2254 if (queue_type == HNS3_RING_TYPE_RX)
2255 gl = HNS3_RING_GL_RX;
2257 gl = HNS3_RING_GL_TX;
2261 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2263 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2264 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2266 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2267 req->int_cause_num = 1;
2268 status = hns3_cmd_send(hw, &desc, 1);
2270 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2271 en ? "Map" : "Unmap", queue_id, vector_id, status);
2279 hns3_init_ring_with_vector(struct hns3_hw *hw)
2286 * In hns3 network engine, vector 0 is always the misc interrupt of this
2287 * function, vector 1~N can be used respectively for the queues of the
2288 * function. Tx and Rx queues with the same number share the interrupt
2289 * vector. In the initialization clearing the all hardware mapping
2290 * relationship configurations between queues and interrupt vectors is
2291 * needed, so some error caused by the residual configurations, such as
2292 * the unexpected Tx interrupt, can be avoid.
2294 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2295 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2296 vec = vec - 1; /* the last interrupt is reserved */
2297 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2298 for (i = 0; i < hw->intr_tqps_num; i++) {
2300 * Set gap limiter/rate limiter/quanity limiter algorithm
2301 * configuration for interrupt coalesce of queue's interrupt.
2303 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2304 HNS3_TQP_INTR_GL_DEFAULT);
2305 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2306 HNS3_TQP_INTR_GL_DEFAULT);
2307 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2309 * QL(quantity limiter) is not used currently, just set 0 to
2312 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2314 ret = hns3_bind_ring_with_vector(hw, vec, false,
2315 HNS3_RING_TYPE_TX, i);
2317 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2318 "vector: %u, ret=%d", i, vec, ret);
2322 ret = hns3_bind_ring_with_vector(hw, vec, false,
2323 HNS3_RING_TYPE_RX, i);
2325 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2326 "vector: %u, ret=%d", i, vec, ret);
2335 hns3_dev_configure(struct rte_eth_dev *dev)
2337 struct hns3_adapter *hns = dev->data->dev_private;
2338 struct rte_eth_conf *conf = &dev->data->dev_conf;
2339 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2340 struct hns3_hw *hw = &hns->hw;
2341 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2342 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2343 struct rte_eth_rss_conf rss_conf;
2348 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2351 * Some versions of hardware network engine does not support
2352 * individually enable/disable/reset the Tx or Rx queue. These devices
2353 * must enable/disable/reset Tx and Rx queues at the same time. When the
2354 * numbers of Tx queues allocated by upper applications are not equal to
2355 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2356 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2357 * work as usual. But these fake queues are imperceptible, and can not
2358 * be used by upper applications.
2360 if (!hns3_dev_indep_txrx_supported(hw)) {
2361 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2363 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2369 hw->adapter_state = HNS3_NIC_CONFIGURING;
2370 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2371 hns3_err(hw, "setting link speed/duplex not supported");
2376 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2377 ret = hns3_check_dcb_cfg(dev);
2382 /* When RSS is not configured, redirect the packet queue 0 */
2383 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2384 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2385 rss_conf = conf->rx_adv_conf.rss_conf;
2386 hw->rss_dis_flag = false;
2387 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2393 * If jumbo frames are enabled, MTU needs to be refreshed
2394 * according to the maximum RX packet length.
2396 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2398 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2399 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2400 * can safely assign to "uint16_t" type variable.
2402 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2403 ret = hns3_dev_mtu_set(dev, mtu);
2406 dev->data->mtu = mtu;
2409 ret = hns3_dev_configure_vlan(dev);
2413 /* config hardware GRO */
2414 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2415 ret = hns3_config_gro(hw, gro_en);
2419 hns->rx_simple_allowed = true;
2420 hns->rx_vec_allowed = true;
2421 hns->tx_simple_allowed = true;
2422 hns->tx_vec_allowed = true;
2424 hns3_init_rx_ptype_tble(dev);
2425 hw->adapter_state = HNS3_NIC_CONFIGURED;
2430 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2431 hw->adapter_state = HNS3_NIC_INITIALIZED;
2437 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2439 struct hns3_config_max_frm_size_cmd *req;
2440 struct hns3_cmd_desc desc;
2442 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2444 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2445 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2446 req->min_frm_size = RTE_ETHER_MIN_LEN;
2448 return hns3_cmd_send(hw, &desc, 1);
2452 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2456 ret = hns3_set_mac_mtu(hw, mps);
2458 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2462 ret = hns3_buffer_alloc(hw);
2464 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2470 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2472 struct hns3_adapter *hns = dev->data->dev_private;
2473 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2474 struct hns3_hw *hw = &hns->hw;
2475 bool is_jumbo_frame;
2478 if (dev->data->dev_started) {
2479 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2480 "before configuration", dev->data->port_id);
2484 rte_spinlock_lock(&hw->lock);
2485 is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2486 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2489 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2490 * assign to "uint16_t" type variable.
2492 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2494 rte_spinlock_unlock(&hw->lock);
2495 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2496 dev->data->port_id, mtu, ret);
2499 hns->pf.mps = (uint16_t)frame_size;
2501 dev->data->dev_conf.rxmode.offloads |=
2502 DEV_RX_OFFLOAD_JUMBO_FRAME;
2504 dev->data->dev_conf.rxmode.offloads &=
2505 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2506 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2507 rte_spinlock_unlock(&hw->lock);
2513 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2515 struct hns3_adapter *hns = eth_dev->data->dev_private;
2516 struct hns3_hw *hw = &hns->hw;
2517 uint16_t queue_num = hw->tqps_num;
2520 * In interrupt mode, 'max_rx_queues' is set based on the number of
2521 * MSI-X interrupt resources of the hardware.
2523 if (hw->data->dev_conf.intr_conf.rxq == 1)
2524 queue_num = hw->intr_tqps_num;
2526 info->max_rx_queues = queue_num;
2527 info->max_tx_queues = hw->tqps_num;
2528 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2529 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2530 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2531 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2532 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2533 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2534 DEV_RX_OFFLOAD_TCP_CKSUM |
2535 DEV_RX_OFFLOAD_UDP_CKSUM |
2536 DEV_RX_OFFLOAD_SCTP_CKSUM |
2537 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2538 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2539 DEV_RX_OFFLOAD_KEEP_CRC |
2540 DEV_RX_OFFLOAD_SCATTER |
2541 DEV_RX_OFFLOAD_VLAN_STRIP |
2542 DEV_RX_OFFLOAD_VLAN_FILTER |
2543 DEV_RX_OFFLOAD_JUMBO_FRAME |
2544 DEV_RX_OFFLOAD_RSS_HASH |
2545 DEV_RX_OFFLOAD_TCP_LRO);
2546 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2547 DEV_TX_OFFLOAD_IPV4_CKSUM |
2548 DEV_TX_OFFLOAD_TCP_CKSUM |
2549 DEV_TX_OFFLOAD_UDP_CKSUM |
2550 DEV_TX_OFFLOAD_SCTP_CKSUM |
2551 DEV_TX_OFFLOAD_MULTI_SEGS |
2552 DEV_TX_OFFLOAD_TCP_TSO |
2553 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2554 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2555 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2556 DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2557 hns3_txvlan_cap_get(hw));
2559 if (hns3_dev_indep_txrx_supported(hw))
2560 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2561 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2563 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2564 .nb_max = HNS3_MAX_RING_DESC,
2565 .nb_min = HNS3_MIN_RING_DESC,
2566 .nb_align = HNS3_ALIGN_RING_DESC,
2569 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2570 .nb_max = HNS3_MAX_RING_DESC,
2571 .nb_min = HNS3_MIN_RING_DESC,
2572 .nb_align = HNS3_ALIGN_RING_DESC,
2573 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2574 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2577 info->default_rxconf = (struct rte_eth_rxconf) {
2578 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2580 * If there are no available Rx buffer descriptors, incoming
2581 * packets are always dropped by hardware based on hns3 network
2587 info->default_txconf = (struct rte_eth_txconf) {
2588 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2592 info->vmdq_queue_num = 0;
2594 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2595 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2596 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2598 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2599 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2600 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2601 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2602 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2603 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2609 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2612 struct hns3_adapter *hns = eth_dev->data->dev_private;
2613 struct hns3_hw *hw = &hns->hw;
2614 uint32_t version = hw->fw_version;
2617 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2618 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2619 HNS3_FW_VERSION_BYTE3_S),
2620 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2621 HNS3_FW_VERSION_BYTE2_S),
2622 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2623 HNS3_FW_VERSION_BYTE1_S),
2624 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2625 HNS3_FW_VERSION_BYTE0_S));
2626 ret += 1; /* add the size of '\0' */
2627 if (fw_size < (uint32_t)ret)
2634 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2635 __rte_unused int wait_to_complete)
2637 struct hns3_adapter *hns = eth_dev->data->dev_private;
2638 struct hns3_hw *hw = &hns->hw;
2639 struct hns3_mac *mac = &hw->mac;
2640 struct rte_eth_link new_link;
2642 if (!hns3_is_reset_pending(hns)) {
2643 hns3_update_speed_duplex(eth_dev);
2644 hns3_update_link_status(hw);
2647 memset(&new_link, 0, sizeof(new_link));
2648 switch (mac->link_speed) {
2649 case ETH_SPEED_NUM_10M:
2650 case ETH_SPEED_NUM_100M:
2651 case ETH_SPEED_NUM_1G:
2652 case ETH_SPEED_NUM_10G:
2653 case ETH_SPEED_NUM_25G:
2654 case ETH_SPEED_NUM_40G:
2655 case ETH_SPEED_NUM_50G:
2656 case ETH_SPEED_NUM_100G:
2657 case ETH_SPEED_NUM_200G:
2658 new_link.link_speed = mac->link_speed;
2661 new_link.link_speed = ETH_SPEED_NUM_100M;
2665 new_link.link_duplex = mac->link_duplex;
2666 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2667 new_link.link_autoneg =
2668 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2670 return rte_eth_linkstatus_set(eth_dev, &new_link);
2674 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2676 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2677 struct hns3_pf *pf = &hns->pf;
2679 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2682 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2688 hns3_query_function_status(struct hns3_hw *hw)
2690 #define HNS3_QUERY_MAX_CNT 10
2691 #define HNS3_QUERY_SLEEP_MSCOEND 1
2692 struct hns3_func_status_cmd *req;
2693 struct hns3_cmd_desc desc;
2697 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2698 req = (struct hns3_func_status_cmd *)desc.data;
2701 ret = hns3_cmd_send(hw, &desc, 1);
2703 PMD_INIT_LOG(ERR, "query function status failed %d",
2708 /* Check pf reset is done */
2712 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2713 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2715 return hns3_parse_func_status(hw, req);
2719 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2721 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2722 struct hns3_pf *pf = &hns->pf;
2724 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2726 * The total_tqps_num obtained from firmware is maximum tqp
2727 * numbers of this port, which should be used for PF and VFs.
2728 * There is no need for pf to have so many tqp numbers in
2729 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2730 * coming from config file, is assigned to maximum queue number
2731 * for the PF of this port by user. So users can modify the
2732 * maximum queue number of PF according to their own application
2733 * scenarios, which is more flexible to use. In addition, many
2734 * memories can be saved due to allocating queue statistics
2735 * room according to the actual number of queues required. The
2736 * maximum queue number of PF for network engine with
2737 * revision_id greater than 0x30 is assigned by config file.
2739 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2740 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2741 "must be greater than 0.",
2742 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2746 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2747 hw->total_tqps_num);
2750 * Due to the limitation on the number of PF interrupts
2751 * available, the maximum queue number assigned to PF on
2752 * the network engine with revision_id 0x21 is 64.
2754 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2755 HNS3_MAX_TQP_NUM_HIP08_PF);
2762 hns3_query_pf_resource(struct hns3_hw *hw)
2764 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2765 struct hns3_pf *pf = &hns->pf;
2766 struct hns3_pf_res_cmd *req;
2767 struct hns3_cmd_desc desc;
2770 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2771 ret = hns3_cmd_send(hw, &desc, 1);
2773 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2777 req = (struct hns3_pf_res_cmd *)desc.data;
2778 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2779 rte_le_to_cpu_16(req->ext_tqp_num);
2780 ret = hns3_get_pf_max_tqp_num(hw);
2784 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2785 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2787 if (req->tx_buf_size)
2789 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2791 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2793 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2795 if (req->dv_buf_size)
2797 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2799 pf->dv_buf_size = HNS3_DEFAULT_DV;
2801 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2804 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2805 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2811 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2813 struct hns3_cfg_param_cmd *req;
2814 uint64_t mac_addr_tmp_high;
2815 uint8_t ext_rss_size_max;
2816 uint64_t mac_addr_tmp;
2819 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2821 /* get the configuration */
2822 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2823 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2824 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2825 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2826 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2827 HNS3_CFG_TQP_DESC_N_M,
2828 HNS3_CFG_TQP_DESC_N_S);
2830 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2831 HNS3_CFG_PHY_ADDR_M,
2832 HNS3_CFG_PHY_ADDR_S);
2833 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2834 HNS3_CFG_MEDIA_TP_M,
2835 HNS3_CFG_MEDIA_TP_S);
2836 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2837 HNS3_CFG_RX_BUF_LEN_M,
2838 HNS3_CFG_RX_BUF_LEN_S);
2839 /* get mac address */
2840 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2841 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2842 HNS3_CFG_MAC_ADDR_H_M,
2843 HNS3_CFG_MAC_ADDR_H_S);
2845 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2847 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2848 HNS3_CFG_DEFAULT_SPEED_M,
2849 HNS3_CFG_DEFAULT_SPEED_S);
2850 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2851 HNS3_CFG_RSS_SIZE_M,
2852 HNS3_CFG_RSS_SIZE_S);
2854 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2855 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2857 req = (struct hns3_cfg_param_cmd *)desc[1].data;
2858 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2860 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2861 HNS3_CFG_SPEED_ABILITY_M,
2862 HNS3_CFG_SPEED_ABILITY_S);
2863 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2864 HNS3_CFG_UMV_TBL_SPACE_M,
2865 HNS3_CFG_UMV_TBL_SPACE_S);
2866 if (!cfg->umv_space)
2867 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2869 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2870 HNS3_CFG_EXT_RSS_SIZE_M,
2871 HNS3_CFG_EXT_RSS_SIZE_S);
2874 * Field ext_rss_size_max obtained from firmware will be more flexible
2875 * for future changes and expansions, which is an exponent of 2, instead
2876 * of reading out directly. If this field is not zero, hns3 PF PMD
2877 * driver uses it as rss_size_max under one TC. Device, whose revision
2878 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2879 * maximum number of queues supported under a TC through this field.
2881 if (ext_rss_size_max)
2882 cfg->rss_size_max = 1U << ext_rss_size_max;
2885 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2886 * @hw: pointer to struct hns3_hw
2887 * @hcfg: the config structure to be getted
2890 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2892 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2893 struct hns3_cfg_param_cmd *req;
2898 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2900 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2901 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2903 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2904 i * HNS3_CFG_RD_LEN_BYTES);
2905 /* Len should be divided by 4 when send to hardware */
2906 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2907 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2908 req->offset = rte_cpu_to_le_32(offset);
2911 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2913 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2917 hns3_parse_cfg(hcfg, desc);
2923 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2925 switch (speed_cmd) {
2926 case HNS3_CFG_SPEED_10M:
2927 *speed = ETH_SPEED_NUM_10M;
2929 case HNS3_CFG_SPEED_100M:
2930 *speed = ETH_SPEED_NUM_100M;
2932 case HNS3_CFG_SPEED_1G:
2933 *speed = ETH_SPEED_NUM_1G;
2935 case HNS3_CFG_SPEED_10G:
2936 *speed = ETH_SPEED_NUM_10G;
2938 case HNS3_CFG_SPEED_25G:
2939 *speed = ETH_SPEED_NUM_25G;
2941 case HNS3_CFG_SPEED_40G:
2942 *speed = ETH_SPEED_NUM_40G;
2944 case HNS3_CFG_SPEED_50G:
2945 *speed = ETH_SPEED_NUM_50G;
2947 case HNS3_CFG_SPEED_100G:
2948 *speed = ETH_SPEED_NUM_100G;
2950 case HNS3_CFG_SPEED_200G:
2951 *speed = ETH_SPEED_NUM_200G;
2961 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2963 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2964 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2965 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2966 hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2967 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2971 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2973 struct hns3_dev_specs_0_cmd *req0;
2975 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2977 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2978 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2979 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2980 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2981 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
2985 hns3_query_dev_specifications(struct hns3_hw *hw)
2987 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2991 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2992 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2994 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2996 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2998 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3002 hns3_parse_dev_specifications(hw, desc);
3008 hns3_get_capability(struct hns3_hw *hw)
3010 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3011 struct rte_pci_device *pci_dev;
3012 struct hns3_pf *pf = &hns->pf;
3013 struct rte_eth_dev *eth_dev;
3018 eth_dev = &rte_eth_devices[hw->data->port_id];
3019 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3020 device_id = pci_dev->id.device_id;
3022 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3023 device_id == HNS3_DEV_ID_50GE_RDMA ||
3024 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3025 device_id == HNS3_DEV_ID_200G_RDMA)
3026 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3028 /* Get PCI revision id */
3029 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3030 HNS3_PCI_REVISION_ID);
3031 if (ret != HNS3_PCI_REVISION_ID_LEN) {
3032 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3036 hw->revision = revision;
3038 if (revision < PCI_REVISION_ID_HIP09_A) {
3039 hns3_set_default_dev_specifications(hw);
3040 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3041 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3042 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3043 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3044 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3045 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3046 hw->rss_info.ipv6_sctp_offload_supported = false;
3050 ret = hns3_query_dev_specifications(hw);
3053 "failed to query dev specifications, ret = %d",
3058 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3059 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3060 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3061 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3062 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3063 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3064 hw->rss_info.ipv6_sctp_offload_supported = true;
3070 hns3_get_board_configuration(struct hns3_hw *hw)
3072 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3073 struct hns3_pf *pf = &hns->pf;
3074 struct hns3_cfg cfg;
3077 ret = hns3_get_board_cfg(hw, &cfg);
3079 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3083 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
3084 !hns3_dev_copper_supported(hw)) {
3085 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
3089 hw->mac.media_type = cfg.media_type;
3090 hw->rss_size_max = cfg.rss_size_max;
3091 hw->rss_dis_flag = false;
3092 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3093 hw->mac.phy_addr = cfg.phy_addr;
3094 hw->mac.default_addr_setted = false;
3095 hw->num_tx_desc = cfg.tqp_desc_num;
3096 hw->num_rx_desc = cfg.tqp_desc_num;
3097 hw->dcb_info.num_pg = 1;
3098 hw->dcb_info.hw_pfc_map = 0;
3100 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3102 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3103 cfg.default_speed, ret);
3107 pf->tc_max = cfg.tc_num;
3108 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3109 PMD_INIT_LOG(WARNING,
3110 "Get TC num(%u) from flash, set TC num to 1",
3115 /* Dev does not support DCB */
3116 if (!hns3_dev_dcb_supported(hw)) {
3120 pf->pfc_max = pf->tc_max;
3122 hw->dcb_info.num_tc = 1;
3123 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3124 hw->tqps_num / hw->dcb_info.num_tc);
3125 hns3_set_bit(hw->hw_tc_map, 0, 1);
3126 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3128 pf->wanted_umv_size = cfg.umv_space;
3134 hns3_get_configuration(struct hns3_hw *hw)
3138 ret = hns3_query_function_status(hw);
3140 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3144 /* Get device capability */
3145 ret = hns3_get_capability(hw);
3147 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3151 /* Get pf resource */
3152 ret = hns3_query_pf_resource(hw);
3154 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3158 ret = hns3_get_board_configuration(hw);
3160 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3164 ret = hns3_query_dev_fec_info(hw);
3167 "failed to query FEC information, ret = %d", ret);
3173 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3174 uint16_t tqp_vid, bool is_pf)
3176 struct hns3_tqp_map_cmd *req;
3177 struct hns3_cmd_desc desc;
3180 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3182 req = (struct hns3_tqp_map_cmd *)desc.data;
3183 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3184 req->tqp_vf = func_id;
3185 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3187 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3188 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3190 ret = hns3_cmd_send(hw, &desc, 1);
3192 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3198 hns3_map_tqp(struct hns3_hw *hw)
3204 * In current version, VF is not supported when PF is driven by DPDK
3205 * driver, so we assign total tqps_num tqps allocated to this port
3208 for (i = 0; i < hw->total_tqps_num; i++) {
3209 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3218 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3220 struct hns3_config_mac_speed_dup_cmd *req;
3221 struct hns3_cmd_desc desc;
3224 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3226 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3228 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3231 case ETH_SPEED_NUM_10M:
3232 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3233 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3235 case ETH_SPEED_NUM_100M:
3236 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3237 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3239 case ETH_SPEED_NUM_1G:
3240 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3241 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3243 case ETH_SPEED_NUM_10G:
3244 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3245 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3247 case ETH_SPEED_NUM_25G:
3248 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3249 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3251 case ETH_SPEED_NUM_40G:
3252 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3253 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3255 case ETH_SPEED_NUM_50G:
3256 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3257 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3259 case ETH_SPEED_NUM_100G:
3260 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3261 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3263 case ETH_SPEED_NUM_200G:
3264 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3265 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3268 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3272 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3274 ret = hns3_cmd_send(hw, &desc, 1);
3276 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3282 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3284 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3285 struct hns3_pf *pf = &hns->pf;
3286 struct hns3_priv_buf *priv;
3287 uint32_t i, total_size;
3289 total_size = pf->pkt_buf_size;
3291 /* alloc tx buffer for all enabled tc */
3292 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3293 priv = &buf_alloc->priv_buf[i];
3295 if (hw->hw_tc_map & BIT(i)) {
3296 if (total_size < pf->tx_buf_size)
3299 priv->tx_buf_size = pf->tx_buf_size;
3301 priv->tx_buf_size = 0;
3303 total_size -= priv->tx_buf_size;
3310 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3312 /* TX buffer size is unit by 128 byte */
3313 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3314 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3315 struct hns3_tx_buff_alloc_cmd *req;
3316 struct hns3_cmd_desc desc;
3321 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3323 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3324 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3325 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3327 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3328 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3329 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3332 ret = hns3_cmd_send(hw, &desc, 1);
3334 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3340 hns3_get_tc_num(struct hns3_hw *hw)
3345 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3346 if (hw->hw_tc_map & BIT(i))
3352 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3354 struct hns3_priv_buf *priv;
3355 uint32_t rx_priv = 0;
3358 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3359 priv = &buf_alloc->priv_buf[i];
3361 rx_priv += priv->buf_size;
3367 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3369 uint32_t total_tx_size = 0;
3372 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3373 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3375 return total_tx_size;
3378 /* Get the number of pfc enabled TCs, which have private buffer */
3380 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3382 struct hns3_priv_buf *priv;
3386 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3387 priv = &buf_alloc->priv_buf[i];
3388 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3395 /* Get the number of pfc disabled TCs, which have private buffer */
3397 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3398 struct hns3_pkt_buf_alloc *buf_alloc)
3400 struct hns3_priv_buf *priv;
3404 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3405 priv = &buf_alloc->priv_buf[i];
3406 if (hw->hw_tc_map & BIT(i) &&
3407 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3415 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3418 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3419 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3420 struct hns3_pf *pf = &hns->pf;
3421 uint32_t shared_buf, aligned_mps;
3426 tc_num = hns3_get_tc_num(hw);
3427 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3429 if (hns3_dev_dcb_supported(hw))
3430 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3433 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3436 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3437 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3438 HNS3_BUF_SIZE_UNIT);
3440 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3441 if (rx_all < rx_priv + shared_std)
3444 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3445 buf_alloc->s_buf.buf_size = shared_buf;
3446 if (hns3_dev_dcb_supported(hw)) {
3447 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3448 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3449 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3450 HNS3_BUF_SIZE_UNIT);
3452 buf_alloc->s_buf.self.high =
3453 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3454 buf_alloc->s_buf.self.low = aligned_mps;
3457 if (hns3_dev_dcb_supported(hw)) {
3458 hi_thrd = shared_buf - pf->dv_buf_size;
3460 if (tc_num <= NEED_RESERVE_TC_NUM)
3461 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3465 hi_thrd = hi_thrd / tc_num;
3467 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3468 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3469 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3471 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3472 lo_thrd = aligned_mps;
3475 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3476 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3477 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3484 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3485 struct hns3_pkt_buf_alloc *buf_alloc)
3487 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3488 struct hns3_pf *pf = &hns->pf;
3489 struct hns3_priv_buf *priv;
3490 uint32_t aligned_mps;
3494 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3495 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3497 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3498 priv = &buf_alloc->priv_buf[i];
3505 if (!(hw->hw_tc_map & BIT(i)))
3509 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3510 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3511 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3512 HNS3_BUF_SIZE_UNIT);
3515 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3519 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3522 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3526 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3527 struct hns3_pkt_buf_alloc *buf_alloc)
3529 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3530 struct hns3_pf *pf = &hns->pf;
3531 struct hns3_priv_buf *priv;
3532 int no_pfc_priv_num;
3537 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3538 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3540 /* let the last to be cleared first */
3541 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3542 priv = &buf_alloc->priv_buf[i];
3543 mask = BIT((uint8_t)i);
3545 if (hw->hw_tc_map & mask &&
3546 !(hw->dcb_info.hw_pfc_map & mask)) {
3547 /* Clear the no pfc TC private buffer */
3555 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3556 no_pfc_priv_num == 0)
3560 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3564 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3565 struct hns3_pkt_buf_alloc *buf_alloc)
3567 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3568 struct hns3_pf *pf = &hns->pf;
3569 struct hns3_priv_buf *priv;
3575 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3576 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3578 /* let the last to be cleared first */
3579 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3580 priv = &buf_alloc->priv_buf[i];
3581 mask = BIT((uint8_t)i);
3582 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3583 /* Reduce the number of pfc TC with private buffer */
3590 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3595 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3599 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3600 struct hns3_pkt_buf_alloc *buf_alloc)
3602 #define COMPENSATE_BUFFER 0x3C00
3603 #define COMPENSATE_HALF_MPS_NUM 5
3604 #define PRIV_WL_GAP 0x1800
3605 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3606 struct hns3_pf *pf = &hns->pf;
3607 uint32_t tc_num = hns3_get_tc_num(hw);
3608 uint32_t half_mps = pf->mps >> 1;
3609 struct hns3_priv_buf *priv;
3610 uint32_t min_rx_priv;
3614 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3616 rx_priv = rx_priv / tc_num;
3618 if (tc_num <= NEED_RESERVE_TC_NUM)
3619 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3622 * Minimum value of private buffer in rx direction (min_rx_priv) is
3623 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3624 * buffer if rx_priv is greater than min_rx_priv.
3626 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3627 COMPENSATE_HALF_MPS_NUM * half_mps;
3628 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3629 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3631 if (rx_priv < min_rx_priv)
3634 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3635 priv = &buf_alloc->priv_buf[i];
3641 if (!(hw->hw_tc_map & BIT(i)))
3645 priv->buf_size = rx_priv;
3646 priv->wl.high = rx_priv - pf->dv_buf_size;
3647 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3650 buf_alloc->s_buf.buf_size = 0;
3656 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3657 * @hw: pointer to struct hns3_hw
3658 * @buf_alloc: pointer to buffer calculation data
3659 * @return: 0: calculate sucessful, negative: fail
3662 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3664 /* When DCB is not supported, rx private buffer is not allocated. */
3665 if (!hns3_dev_dcb_supported(hw)) {
3666 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3667 struct hns3_pf *pf = &hns->pf;
3668 uint32_t rx_all = pf->pkt_buf_size;
3670 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3671 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3678 * Try to allocate privated packet buffer for all TCs without share
3681 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3685 * Try to allocate privated packet buffer for all TCs with share
3688 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3692 * For different application scenes, the enabled port number, TC number
3693 * and no_drop TC number are different. In order to obtain the better
3694 * performance, software could allocate the buffer size and configure
3695 * the waterline by tring to decrease the private buffer size according
3696 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3699 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3702 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3705 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3712 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3714 struct hns3_rx_priv_buff_cmd *req;
3715 struct hns3_cmd_desc desc;
3720 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3721 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3723 /* Alloc private buffer TCs */
3724 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3725 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3728 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3729 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3732 buf_size = buf_alloc->s_buf.buf_size;
3733 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3734 (1 << HNS3_TC0_PRI_BUF_EN_B));
3736 ret = hns3_cmd_send(hw, &desc, 1);
3738 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3744 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3746 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3747 struct hns3_rx_priv_wl_buf *req;
3748 struct hns3_priv_buf *priv;
3749 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3753 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3754 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3756 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3758 /* The first descriptor set the NEXT bit to 1 */
3760 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3762 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3764 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3765 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3767 priv = &buf_alloc->priv_buf[idx];
3768 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3770 req->tc_wl[j].high |=
3771 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3772 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3774 req->tc_wl[j].low |=
3775 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3779 /* Send 2 descriptor at one time */
3780 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3782 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3788 hns3_common_thrd_config(struct hns3_hw *hw,
3789 struct hns3_pkt_buf_alloc *buf_alloc)
3791 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3792 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3793 struct hns3_rx_com_thrd *req;
3794 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3795 struct hns3_tc_thrd *tc;
3800 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3801 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3803 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3805 /* The first descriptor set the NEXT bit to 1 */
3807 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3809 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3811 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3812 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3813 tc = &s_buf->tc_thrd[tc_idx];
3815 req->com_thrd[j].high =
3816 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3817 req->com_thrd[j].high |=
3818 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3819 req->com_thrd[j].low =
3820 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3821 req->com_thrd[j].low |=
3822 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3826 /* Send 2 descriptors at one time */
3827 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3829 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3835 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3837 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3838 struct hns3_rx_com_wl *req;
3839 struct hns3_cmd_desc desc;
3842 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3844 req = (struct hns3_rx_com_wl *)desc.data;
3845 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3846 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3848 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3849 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3851 ret = hns3_cmd_send(hw, &desc, 1);
3853 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3859 hns3_buffer_alloc(struct hns3_hw *hw)
3861 struct hns3_pkt_buf_alloc pkt_buf;
3864 memset(&pkt_buf, 0, sizeof(pkt_buf));
3865 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3868 "could not calc tx buffer size for all TCs %d",
3873 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3875 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3879 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3882 "could not calc rx priv buffer size for all TCs %d",
3887 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3889 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3893 if (hns3_dev_dcb_supported(hw)) {
3894 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3897 "could not configure rx private waterline %d",
3902 ret = hns3_common_thrd_config(hw, &pkt_buf);
3905 "could not configure common threshold %d",
3911 ret = hns3_common_wl_config(hw, &pkt_buf);
3913 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3920 hns3_mac_init(struct hns3_hw *hw)
3922 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3923 struct hns3_mac *mac = &hw->mac;
3924 struct hns3_pf *pf = &hns->pf;
3927 pf->support_sfp_query = true;
3928 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3929 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3931 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3935 mac->link_status = ETH_LINK_DOWN;
3937 return hns3_config_mtu(hw, pf->mps);
3941 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3943 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
3944 #define HNS3_ETHERTYPE_ALREADY_ADD 1
3945 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
3946 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
3951 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
3956 switch (resp_code) {
3957 case HNS3_ETHERTYPE_SUCCESS_ADD:
3958 case HNS3_ETHERTYPE_ALREADY_ADD:
3961 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3963 "add mac ethertype failed for manager table overflow.");
3964 return_status = -EIO;
3966 case HNS3_ETHERTYPE_KEY_CONFLICT:
3967 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3968 return_status = -EIO;
3972 "add mac ethertype failed for undefined, code=%u.",
3974 return_status = -EIO;
3978 return return_status;
3982 hns3_add_mgr_tbl(struct hns3_hw *hw,
3983 const struct hns3_mac_mgr_tbl_entry_cmd *req)
3985 struct hns3_cmd_desc desc;
3990 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3991 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3993 ret = hns3_cmd_send(hw, &desc, 1);
3996 "add mac ethertype failed for cmd_send, ret =%d.",
4001 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4002 retval = rte_le_to_cpu_16(desc.retval);
4004 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4008 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4009 int *table_item_num)
4011 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4014 * In current version, we add one item in management table as below:
4015 * 0x0180C200000E -- LLDP MC address
4018 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4019 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4020 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4021 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4022 tbl->i_port_bitmap = 0x1;
4023 *table_item_num = 1;
4027 hns3_init_mgr_tbl(struct hns3_hw *hw)
4029 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
4030 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4035 memset(mgr_table, 0, sizeof(mgr_table));
4036 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4037 for (i = 0; i < table_item_num; i++) {
4038 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4040 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4050 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4051 bool en_mc, bool en_bc, int vport_id)
4056 memset(param, 0, sizeof(struct hns3_promisc_param));
4058 param->enable = HNS3_PROMISC_EN_UC;
4060 param->enable |= HNS3_PROMISC_EN_MC;
4062 param->enable |= HNS3_PROMISC_EN_BC;
4063 param->vf_id = vport_id;
4067 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4069 struct hns3_promisc_cfg_cmd *req;
4070 struct hns3_cmd_desc desc;
4073 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4075 req = (struct hns3_promisc_cfg_cmd *)desc.data;
4076 req->vf_id = param->vf_id;
4077 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4078 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4080 ret = hns3_cmd_send(hw, &desc, 1);
4082 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4088 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4090 struct hns3_promisc_param param;
4091 bool en_bc_pmc = true;
4095 * In current version VF is not supported when PF is driven by DPDK
4096 * driver, just need to configure parameters for PF vport.
4098 vf_id = HNS3_PF_FUNC_ID;
4100 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4101 return hns3_cmd_set_promisc_mode(hw, ¶m);
4105 hns3_promisc_init(struct hns3_hw *hw)
4107 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4108 struct hns3_pf *pf = &hns->pf;
4109 struct hns3_promisc_param param;
4113 ret = hns3_set_promisc_mode(hw, false, false);
4115 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4120 * In current version VFs are not supported when PF is driven by DPDK
4121 * driver. After PF has been taken over by DPDK, the original VF will
4122 * be invalid. So, there is a possibility of entry residues. It should
4123 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4126 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4127 hns3_promisc_param_init(¶m, false, false, false, func_id);
4128 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4130 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4131 " ret = %d", func_id, ret);
4140 hns3_promisc_uninit(struct hns3_hw *hw)
4142 struct hns3_promisc_param param;
4146 func_id = HNS3_PF_FUNC_ID;
4149 * In current version VFs are not supported when PF is driven by
4150 * DPDK driver, and VFs' promisc mode status has been cleared during
4151 * init and their status will not change. So just clear PF's promisc
4152 * mode status during uninit.
4154 hns3_promisc_param_init(¶m, false, false, false, func_id);
4155 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4157 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4158 " uninit, ret = %d", ret);
4162 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4164 bool allmulti = dev->data->all_multicast ? true : false;
4165 struct hns3_adapter *hns = dev->data->dev_private;
4166 struct hns3_hw *hw = &hns->hw;
4171 rte_spinlock_lock(&hw->lock);
4172 ret = hns3_set_promisc_mode(hw, true, true);
4174 rte_spinlock_unlock(&hw->lock);
4175 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4181 * When promiscuous mode was enabled, disable the vlan filter to let
4182 * all packets coming in in the receiving direction.
4184 offloads = dev->data->dev_conf.rxmode.offloads;
4185 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4186 ret = hns3_enable_vlan_filter(hns, false);
4188 hns3_err(hw, "failed to enable promiscuous mode due to "
4189 "failure to disable vlan filter, ret = %d",
4191 err = hns3_set_promisc_mode(hw, false, allmulti);
4193 hns3_err(hw, "failed to restore promiscuous "
4194 "status after disable vlan filter "
4195 "failed during enabling promiscuous "
4196 "mode, ret = %d", ret);
4200 rte_spinlock_unlock(&hw->lock);
4206 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4208 bool allmulti = dev->data->all_multicast ? true : false;
4209 struct hns3_adapter *hns = dev->data->dev_private;
4210 struct hns3_hw *hw = &hns->hw;
4215 /* If now in all_multicast mode, must remain in all_multicast mode. */
4216 rte_spinlock_lock(&hw->lock);
4217 ret = hns3_set_promisc_mode(hw, false, allmulti);
4219 rte_spinlock_unlock(&hw->lock);
4220 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4224 /* when promiscuous mode was disabled, restore the vlan filter status */
4225 offloads = dev->data->dev_conf.rxmode.offloads;
4226 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4227 ret = hns3_enable_vlan_filter(hns, true);
4229 hns3_err(hw, "failed to disable promiscuous mode due to"
4230 " failure to restore vlan filter, ret = %d",
4232 err = hns3_set_promisc_mode(hw, true, true);
4234 hns3_err(hw, "failed to restore promiscuous "
4235 "status after enabling vlan filter "
4236 "failed during disabling promiscuous "
4237 "mode, ret = %d", ret);
4240 rte_spinlock_unlock(&hw->lock);
4246 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4248 struct hns3_adapter *hns = dev->data->dev_private;
4249 struct hns3_hw *hw = &hns->hw;
4252 if (dev->data->promiscuous)
4255 rte_spinlock_lock(&hw->lock);
4256 ret = hns3_set_promisc_mode(hw, false, true);
4257 rte_spinlock_unlock(&hw->lock);
4259 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4266 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4268 struct hns3_adapter *hns = dev->data->dev_private;
4269 struct hns3_hw *hw = &hns->hw;
4272 /* If now in promiscuous mode, must remain in all_multicast mode. */
4273 if (dev->data->promiscuous)
4276 rte_spinlock_lock(&hw->lock);
4277 ret = hns3_set_promisc_mode(hw, false, false);
4278 rte_spinlock_unlock(&hw->lock);
4280 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4287 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4289 struct hns3_hw *hw = &hns->hw;
4290 bool allmulti = hw->data->all_multicast ? true : false;
4293 if (hw->data->promiscuous) {
4294 ret = hns3_set_promisc_mode(hw, true, true);
4296 hns3_err(hw, "failed to restore promiscuous mode, "
4301 ret = hns3_set_promisc_mode(hw, false, allmulti);
4303 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4309 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4311 struct hns3_sfp_speed_cmd *resp;
4312 struct hns3_cmd_desc desc;
4315 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4316 resp = (struct hns3_sfp_speed_cmd *)desc.data;
4317 ret = hns3_cmd_send(hw, &desc, 1);
4318 if (ret == -EOPNOTSUPP) {
4319 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4322 hns3_err(hw, "get sfp speed failed %d", ret);
4326 *speed = resp->sfp_speed;
4332 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4334 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4335 duplex = ETH_LINK_FULL_DUPLEX;
4341 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4343 struct hns3_mac *mac = &hw->mac;
4344 uint32_t cur_speed = mac->link_speed;
4347 duplex = hns3_check_speed_dup(duplex, speed);
4348 if (mac->link_speed == speed && mac->link_duplex == duplex)
4351 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4355 mac->link_speed = speed;
4356 ret = hns3_dcb_port_shaper_cfg(hw);
4358 hns3_err(hw, "failed to configure port shaper, ret = %d.", ret);
4359 mac->link_speed = cur_speed;
4363 mac->link_duplex = duplex;
4369 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4371 struct hns3_adapter *hns = eth_dev->data->dev_private;
4372 struct hns3_hw *hw = &hns->hw;
4373 struct hns3_pf *pf = &hns->pf;
4377 /* If IMP do not support get SFP/qSFP speed, return directly */
4378 if (!pf->support_sfp_query)
4381 ret = hns3_get_sfp_speed(hw, &speed);
4382 if (ret == -EOPNOTSUPP) {
4383 pf->support_sfp_query = false;
4388 if (speed == ETH_SPEED_NUM_NONE)
4389 return 0; /* do nothing if no SFP */
4391 /* Config full duplex for SFP */
4392 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4396 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4398 struct hns3_config_mac_mode_cmd *req;
4399 struct hns3_cmd_desc desc;
4400 uint32_t loop_en = 0;
4404 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4406 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4409 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4410 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4411 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4412 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4413 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4414 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4415 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4416 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4417 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4418 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4421 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4422 * when receiving frames. Otherwise, CRC will be stripped.
4424 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4425 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4427 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4428 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4429 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4430 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4431 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4433 ret = hns3_cmd_send(hw, &desc, 1);
4435 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4441 hns3_get_mac_link_status(struct hns3_hw *hw)
4443 struct hns3_link_status_cmd *req;
4444 struct hns3_cmd_desc desc;
4448 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4449 ret = hns3_cmd_send(hw, &desc, 1);
4451 hns3_err(hw, "get link status cmd failed %d", ret);
4452 return ETH_LINK_DOWN;
4455 req = (struct hns3_link_status_cmd *)desc.data;
4456 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4458 return !!link_status;
4462 hns3_update_link_status(struct hns3_hw *hw)
4466 state = hns3_get_mac_link_status(hw);
4467 if (state != hw->mac.link_status) {
4468 hw->mac.link_status = state;
4469 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4474 hns3_service_handler(void *param)
4476 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4477 struct hns3_adapter *hns = eth_dev->data->dev_private;
4478 struct hns3_hw *hw = &hns->hw;
4480 if (!hns3_is_reset_pending(hns)) {
4481 hns3_update_speed_duplex(eth_dev);
4482 hns3_update_link_status(hw);
4484 hns3_warn(hw, "Cancel the query when reset is pending");
4486 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4490 hns3_init_hardware(struct hns3_adapter *hns)
4492 struct hns3_hw *hw = &hns->hw;
4495 ret = hns3_map_tqp(hw);
4497 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4501 ret = hns3_init_umv_space(hw);
4503 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4507 ret = hns3_mac_init(hw);
4509 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4513 ret = hns3_init_mgr_tbl(hw);
4515 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4519 ret = hns3_promisc_init(hw);
4521 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4526 ret = hns3_init_vlan_config(hns);
4528 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4532 ret = hns3_dcb_init(hw);
4534 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4538 ret = hns3_init_fd_config(hns);
4540 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4544 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4546 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4550 ret = hns3_config_gro(hw, false);
4552 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4557 * In the initialization clearing the all hardware mapping relationship
4558 * configurations between queues and interrupt vectors is needed, so
4559 * some error caused by the residual configurations, such as the
4560 * unexpected interrupt, can be avoid.
4562 ret = hns3_init_ring_with_vector(hw);
4564 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4571 hns3_uninit_umv_space(hw);
4576 hns3_clear_hw(struct hns3_hw *hw)
4578 struct hns3_cmd_desc desc;
4581 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4583 ret = hns3_cmd_send(hw, &desc, 1);
4584 if (ret && ret != -EOPNOTSUPP)
4591 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4596 * The new firmware support report more hardware error types by
4597 * msix mode. These errors are defined as RAS errors in hardware
4598 * and belong to a different type from the MSI-x errors processed
4599 * by the network driver.
4601 * Network driver should open the new error report on initialition
4603 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4604 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4605 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4609 hns3_init_pf(struct rte_eth_dev *eth_dev)
4611 struct rte_device *dev = eth_dev->device;
4612 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4613 struct hns3_adapter *hns = eth_dev->data->dev_private;
4614 struct hns3_hw *hw = &hns->hw;
4617 PMD_INIT_FUNC_TRACE();
4619 /* Get hardware io base address from pcie BAR2 IO space */
4620 hw->io_base = pci_dev->mem_resource[2].addr;
4622 /* Firmware command queue initialize */
4623 ret = hns3_cmd_init_queue(hw);
4625 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4626 goto err_cmd_init_queue;
4629 hns3_clear_all_event_cause(hw);
4631 /* Firmware command initialize */
4632 ret = hns3_cmd_init(hw);
4634 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4639 * To ensure that the hardware environment is clean during
4640 * initialization, the driver actively clear the hardware environment
4641 * during initialization, including PF and corresponding VFs' vlan, mac,
4642 * flow table configurations, etc.
4644 ret = hns3_clear_hw(hw);
4646 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4650 hns3_config_all_msix_error(hw, true);
4652 ret = rte_intr_callback_register(&pci_dev->intr_handle,
4653 hns3_interrupt_handler,
4656 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4657 goto err_intr_callback_register;
4660 /* Enable interrupt */
4661 rte_intr_enable(&pci_dev->intr_handle);
4662 hns3_pf_enable_irq0(hw);
4664 /* Get configuration */
4665 ret = hns3_get_configuration(hw);
4667 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4668 goto err_get_config;
4671 ret = hns3_tqp_stats_init(hw);
4673 goto err_get_config;
4675 ret = hns3_init_hardware(hns);
4677 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4681 /* Initialize flow director filter list & hash */
4682 ret = hns3_fdir_filter_init(hns);
4684 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4688 hns3_rss_set_default_args(hw);
4690 ret = hns3_enable_hw_error_intr(hns, true);
4692 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4694 goto err_enable_intr;
4697 hns3_tm_conf_init(eth_dev);
4702 hns3_fdir_filter_uninit(hns);
4704 hns3_uninit_umv_space(hw);
4706 hns3_tqp_stats_uninit(hw);
4708 hns3_pf_disable_irq0(hw);
4709 rte_intr_disable(&pci_dev->intr_handle);
4710 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4712 err_intr_callback_register:
4714 hns3_cmd_uninit(hw);
4715 hns3_cmd_destroy_queue(hw);
4723 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4725 struct hns3_adapter *hns = eth_dev->data->dev_private;
4726 struct rte_device *dev = eth_dev->device;
4727 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4728 struct hns3_hw *hw = &hns->hw;
4730 PMD_INIT_FUNC_TRACE();
4732 hns3_tm_conf_uninit(eth_dev);
4733 hns3_enable_hw_error_intr(hns, false);
4734 hns3_rss_uninit(hns);
4735 (void)hns3_config_gro(hw, false);
4736 hns3_promisc_uninit(hw);
4737 hns3_fdir_filter_uninit(hns);
4738 hns3_uninit_umv_space(hw);
4739 hns3_tqp_stats_uninit(hw);
4740 hns3_pf_disable_irq0(hw);
4741 rte_intr_disable(&pci_dev->intr_handle);
4742 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4744 hns3_config_all_msix_error(hw, false);
4745 hns3_cmd_uninit(hw);
4746 hns3_cmd_destroy_queue(hw);
4751 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4753 struct hns3_hw *hw = &hns->hw;
4756 ret = hns3_dcb_cfg_update(hns);
4761 * The hns3_dcb_cfg_update may configure TM module, so
4762 * hns3_tm_conf_update must called later.
4764 ret = hns3_tm_conf_update(hw);
4766 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
4770 ret = hns3_init_queues(hns, reset_queue);
4772 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
4776 ret = hns3_cfg_mac_mode(hw, true);
4778 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
4779 goto err_config_mac_mode;
4783 err_config_mac_mode:
4784 hns3_dev_release_mbufs(hns);
4786 * Here is exception handling, hns3_reset_all_tqps will have the
4787 * corresponding error message if it is handled incorrectly, so it is
4788 * not necessary to check hns3_reset_all_tqps return value, here keep
4789 * ret as the error code causing the exception.
4791 (void)hns3_reset_all_tqps(hns);
4796 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4798 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4799 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4800 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4801 uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
4802 uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4803 uint32_t intr_vector;
4808 * hns3 needs a separate interrupt to be used as event interrupt which
4809 * could not be shared with task queue pair, so KERNEL drivers need
4810 * support multiple interrupt vectors.
4812 if (dev->data->dev_conf.intr_conf.rxq == 0 ||
4813 !rte_intr_cap_multiple(intr_handle))
4816 rte_intr_disable(intr_handle);
4817 intr_vector = hw->used_rx_queues;
4818 /* creates event fd for each intr vector when MSIX is used */
4819 if (rte_intr_efd_enable(intr_handle, intr_vector))
4822 if (intr_handle->intr_vec == NULL) {
4823 intr_handle->intr_vec =
4824 rte_zmalloc("intr_vec",
4825 hw->used_rx_queues * sizeof(int), 0);
4826 if (intr_handle->intr_vec == NULL) {
4827 hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
4828 hw->used_rx_queues);
4830 goto alloc_intr_vec_error;
4834 if (rte_intr_allow_others(intr_handle)) {
4835 vec = RTE_INTR_VEC_RXTX_OFFSET;
4836 base = RTE_INTR_VEC_RXTX_OFFSET;
4839 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4840 ret = hns3_bind_ring_with_vector(hw, vec, true,
4841 HNS3_RING_TYPE_RX, q_id);
4843 goto bind_vector_error;
4844 intr_handle->intr_vec[q_id] = vec;
4846 * If there are not enough efds (e.g. not enough interrupt),
4847 * remaining queues will be bond to the last interrupt.
4849 if (vec < base + intr_handle->nb_efd - 1)
4852 rte_intr_enable(intr_handle);
4856 rte_free(intr_handle->intr_vec);
4857 intr_handle->intr_vec = NULL;
4858 alloc_intr_vec_error:
4859 rte_intr_efd_disable(intr_handle);
4864 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4866 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4867 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4868 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4872 if (dev->data->dev_conf.intr_conf.rxq == 0)
4875 if (rte_intr_dp_is_en(intr_handle)) {
4876 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4877 ret = hns3_bind_ring_with_vector(hw,
4878 intr_handle->intr_vec[q_id], true,
4879 HNS3_RING_TYPE_RX, q_id);
4889 hns3_restore_filter(struct rte_eth_dev *dev)
4891 hns3_restore_rss_filter(dev);
4895 hns3_dev_start(struct rte_eth_dev *dev)
4897 struct hns3_adapter *hns = dev->data->dev_private;
4898 struct hns3_hw *hw = &hns->hw;
4901 PMD_INIT_FUNC_TRACE();
4902 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
4905 rte_spinlock_lock(&hw->lock);
4906 hw->adapter_state = HNS3_NIC_STARTING;
4908 ret = hns3_do_start(hns, true);
4910 hw->adapter_state = HNS3_NIC_CONFIGURED;
4911 rte_spinlock_unlock(&hw->lock);
4914 ret = hns3_map_rx_interrupt(dev);
4916 hw->adapter_state = HNS3_NIC_CONFIGURED;
4917 rte_spinlock_unlock(&hw->lock);
4922 * There are three register used to control the status of a TQP
4923 * (contains a pair of Tx queue and Rx queue) in the new version network
4924 * engine. One is used to control the enabling of Tx queue, the other is
4925 * used to control the enabling of Rx queue, and the last is the master
4926 * switch used to control the enabling of the tqp. The Tx register and
4927 * TQP register must be enabled at the same time to enable a Tx queue.
4928 * The same applies to the Rx queue. For the older network engine, this
4929 * function only refresh the enabled flag, and it is used to update the
4930 * status of queue in the dpdk framework.
4932 ret = hns3_start_all_txqs(dev);
4934 hw->adapter_state = HNS3_NIC_CONFIGURED;
4935 rte_spinlock_unlock(&hw->lock);
4939 ret = hns3_start_all_rxqs(dev);
4941 hns3_stop_all_txqs(dev);
4942 hw->adapter_state = HNS3_NIC_CONFIGURED;
4943 rte_spinlock_unlock(&hw->lock);
4947 hw->adapter_state = HNS3_NIC_STARTED;
4948 rte_spinlock_unlock(&hw->lock);
4950 hns3_rx_scattered_calc(dev);
4951 hns3_set_rxtx_function(dev);
4952 hns3_mp_req_start_rxtx(dev);
4953 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4955 hns3_restore_filter(dev);
4957 /* Enable interrupt of all rx queues before enabling queues */
4958 hns3_dev_all_rx_queue_intr_enable(hw, true);
4961 * After finished the initialization, enable tqps to receive/transmit
4962 * packets and refresh all queue status.
4964 hns3_start_tqps(hw);
4966 hns3_tm_dev_start_proc(hw);
4968 hns3_info(hw, "hns3 dev start successful!");
4973 hns3_do_stop(struct hns3_adapter *hns)
4975 struct hns3_hw *hw = &hns->hw;
4978 ret = hns3_cfg_mac_mode(hw, false);
4981 hw->mac.link_status = ETH_LINK_DOWN;
4983 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4984 hns3_configure_all_mac_addr(hns, true);
4985 ret = hns3_reset_all_tqps(hns);
4987 hns3_err(hw, "failed to reset all queues ret = %d.",
4992 hw->mac.default_addr_setted = false;
4997 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4999 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5000 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5001 struct hns3_adapter *hns = dev->data->dev_private;
5002 struct hns3_hw *hw = &hns->hw;
5003 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5004 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5007 if (dev->data->dev_conf.intr_conf.rxq == 0)
5010 /* unmap the ring with vector */
5011 if (rte_intr_allow_others(intr_handle)) {
5012 vec = RTE_INTR_VEC_RXTX_OFFSET;
5013 base = RTE_INTR_VEC_RXTX_OFFSET;
5015 if (rte_intr_dp_is_en(intr_handle)) {
5016 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5017 (void)hns3_bind_ring_with_vector(hw, vec, false,
5020 if (vec < base + intr_handle->nb_efd - 1)
5024 /* Clean datapath event and queue/vec mapping */
5025 rte_intr_efd_disable(intr_handle);
5026 if (intr_handle->intr_vec) {
5027 rte_free(intr_handle->intr_vec);
5028 intr_handle->intr_vec = NULL;
5033 hns3_dev_stop(struct rte_eth_dev *dev)
5035 struct hns3_adapter *hns = dev->data->dev_private;
5036 struct hns3_hw *hw = &hns->hw;
5038 PMD_INIT_FUNC_TRACE();
5039 dev->data->dev_started = 0;
5041 hw->adapter_state = HNS3_NIC_STOPPING;
5042 hns3_set_rxtx_function(dev);
5044 /* Disable datapath on secondary process. */
5045 hns3_mp_req_stop_rxtx(dev);
5046 /* Prevent crashes when queues are still in use. */
5047 rte_delay_ms(hw->tqps_num);
5049 rte_spinlock_lock(&hw->lock);
5050 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5051 hns3_tm_dev_stop_proc(hw);
5054 hns3_unmap_rx_interrupt(dev);
5055 hns3_dev_release_mbufs(hns);
5056 hw->adapter_state = HNS3_NIC_CONFIGURED;
5058 hns3_rx_scattered_reset(dev);
5059 rte_eal_alarm_cancel(hns3_service_handler, dev);
5060 rte_spinlock_unlock(&hw->lock);
5066 hns3_dev_close(struct rte_eth_dev *eth_dev)
5068 struct hns3_adapter *hns = eth_dev->data->dev_private;
5069 struct hns3_hw *hw = &hns->hw;
5072 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5073 rte_free(eth_dev->process_private);
5074 eth_dev->process_private = NULL;
5078 if (hw->adapter_state == HNS3_NIC_STARTED)
5079 ret = hns3_dev_stop(eth_dev);
5081 hw->adapter_state = HNS3_NIC_CLOSING;
5082 hns3_reset_abort(hns);
5083 hw->adapter_state = HNS3_NIC_CLOSED;
5085 hns3_configure_all_mc_mac_addr(hns, true);
5086 hns3_remove_all_vlan_table(hns);
5087 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5088 hns3_uninit_pf(eth_dev);
5089 hns3_free_all_queues(eth_dev);
5090 rte_free(hw->reset.wait_data);
5091 rte_free(eth_dev->process_private);
5092 eth_dev->process_private = NULL;
5093 hns3_mp_uninit_primary();
5094 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5100 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5102 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5103 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5105 fc_conf->pause_time = pf->pause_time;
5107 /* return fc current mode */
5108 switch (hw->current_mode) {
5110 fc_conf->mode = RTE_FC_FULL;
5112 case HNS3_FC_TX_PAUSE:
5113 fc_conf->mode = RTE_FC_TX_PAUSE;
5115 case HNS3_FC_RX_PAUSE:
5116 fc_conf->mode = RTE_FC_RX_PAUSE;
5120 fc_conf->mode = RTE_FC_NONE;
5128 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5132 hw->requested_mode = HNS3_FC_NONE;
5134 case RTE_FC_RX_PAUSE:
5135 hw->requested_mode = HNS3_FC_RX_PAUSE;
5137 case RTE_FC_TX_PAUSE:
5138 hw->requested_mode = HNS3_FC_TX_PAUSE;
5141 hw->requested_mode = HNS3_FC_FULL;
5144 hw->requested_mode = HNS3_FC_NONE;
5145 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5146 "configured to RTE_FC_NONE", mode);
5152 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5154 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5155 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5158 if (fc_conf->high_water || fc_conf->low_water ||
5159 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5160 hns3_err(hw, "Unsupported flow control settings specified, "
5161 "high_water(%u), low_water(%u), send_xon(%u) and "
5162 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5163 fc_conf->high_water, fc_conf->low_water,
5164 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5167 if (fc_conf->autoneg) {
5168 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5171 if (!fc_conf->pause_time) {
5172 hns3_err(hw, "Invalid pause time %u setting.",
5173 fc_conf->pause_time);
5177 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5178 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5179 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5180 "current_fc_status = %d", hw->current_fc_status);
5184 hns3_get_fc_mode(hw, fc_conf->mode);
5185 if (hw->requested_mode == hw->current_mode &&
5186 pf->pause_time == fc_conf->pause_time)
5189 rte_spinlock_lock(&hw->lock);
5190 ret = hns3_fc_enable(dev, fc_conf);
5191 rte_spinlock_unlock(&hw->lock);
5197 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5198 struct rte_eth_pfc_conf *pfc_conf)
5200 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5201 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5205 if (!hns3_dev_dcb_supported(hw)) {
5206 hns3_err(hw, "This port does not support dcb configurations.");
5210 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5211 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5212 hns3_err(hw, "Unsupported flow control settings specified, "
5213 "high_water(%u), low_water(%u), send_xon(%u) and "
5214 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5215 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5216 pfc_conf->fc.send_xon,
5217 pfc_conf->fc.mac_ctrl_frame_fwd);
5220 if (pfc_conf->fc.autoneg) {
5221 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5224 if (pfc_conf->fc.pause_time == 0) {
5225 hns3_err(hw, "Invalid pause time %u setting.",
5226 pfc_conf->fc.pause_time);
5230 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5231 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5232 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5233 "current_fc_status = %d", hw->current_fc_status);
5237 priority = pfc_conf->priority;
5238 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5239 if (hw->dcb_info.pfc_en & BIT(priority) &&
5240 hw->requested_mode == hw->current_mode &&
5241 pfc_conf->fc.pause_time == pf->pause_time)
5244 rte_spinlock_lock(&hw->lock);
5245 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5246 rte_spinlock_unlock(&hw->lock);
5252 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5254 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5255 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5256 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5259 rte_spinlock_lock(&hw->lock);
5260 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5261 dcb_info->nb_tcs = pf->local_max_tc;
5263 dcb_info->nb_tcs = 1;
5265 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5266 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5267 for (i = 0; i < dcb_info->nb_tcs; i++)
5268 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5270 for (i = 0; i < hw->num_tc; i++) {
5271 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5272 dcb_info->tc_queue.tc_txq[0][i].base =
5273 hw->tc_queue[i].tqp_offset;
5274 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5275 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5276 hw->tc_queue[i].tqp_count;
5278 rte_spinlock_unlock(&hw->lock);
5284 hns3_reinit_dev(struct hns3_adapter *hns)
5286 struct hns3_hw *hw = &hns->hw;
5289 ret = hns3_cmd_init(hw);
5291 hns3_err(hw, "Failed to init cmd: %d", ret);
5295 ret = hns3_reset_all_tqps(hns);
5297 hns3_err(hw, "Failed to reset all queues: %d", ret);
5301 ret = hns3_init_hardware(hns);
5303 hns3_err(hw, "Failed to init hardware: %d", ret);
5307 ret = hns3_enable_hw_error_intr(hns, true);
5309 hns3_err(hw, "fail to enable hw error interrupts: %d",
5313 hns3_info(hw, "Reset done, driver initialization finished.");
5319 is_pf_reset_done(struct hns3_hw *hw)
5321 uint32_t val, reg, reg_bit;
5323 switch (hw->reset.level) {
5324 case HNS3_IMP_RESET:
5325 reg = HNS3_GLOBAL_RESET_REG;
5326 reg_bit = HNS3_IMP_RESET_BIT;
5328 case HNS3_GLOBAL_RESET:
5329 reg = HNS3_GLOBAL_RESET_REG;
5330 reg_bit = HNS3_GLOBAL_RESET_BIT;
5332 case HNS3_FUNC_RESET:
5333 reg = HNS3_FUN_RST_ING;
5334 reg_bit = HNS3_FUN_RST_ING_B;
5336 case HNS3_FLR_RESET:
5338 hns3_err(hw, "Wait for unsupported reset level: %d",
5342 val = hns3_read_dev(hw, reg);
5343 if (hns3_get_bit(val, reg_bit))
5350 hns3_is_reset_pending(struct hns3_adapter *hns)
5352 struct hns3_hw *hw = &hns->hw;
5353 enum hns3_reset_level reset;
5355 hns3_check_event_cause(hns, NULL);
5356 reset = hns3_get_reset_level(hns, &hw->reset.pending);
5357 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5358 hns3_warn(hw, "High level reset %d is pending", reset);
5361 reset = hns3_get_reset_level(hns, &hw->reset.request);
5362 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5363 hns3_warn(hw, "High level reset %d is request", reset);
5370 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5372 struct hns3_hw *hw = &hns->hw;
5373 struct hns3_wait_data *wait_data = hw->reset.wait_data;
5376 if (wait_data->result == HNS3_WAIT_SUCCESS)
5378 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5379 gettimeofday(&tv, NULL);
5380 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5381 tv.tv_sec, tv.tv_usec);
5383 } else if (wait_data->result == HNS3_WAIT_REQUEST)
5386 wait_data->hns = hns;
5387 wait_data->check_completion = is_pf_reset_done;
5388 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5389 HNS3_RESET_WAIT_MS + get_timeofday_ms();
5390 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5391 wait_data->count = HNS3_RESET_WAIT_CNT;
5392 wait_data->result = HNS3_WAIT_REQUEST;
5393 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5398 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5400 struct hns3_cmd_desc desc;
5401 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5403 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5404 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5405 req->fun_reset_vfid = func_id;
5407 return hns3_cmd_send(hw, &desc, 1);
5411 hns3_imp_reset_cmd(struct hns3_hw *hw)
5413 struct hns3_cmd_desc desc;
5415 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5416 desc.data[0] = 0xeedd;
5418 return hns3_cmd_send(hw, &desc, 1);
5422 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5424 struct hns3_hw *hw = &hns->hw;
5428 gettimeofday(&tv, NULL);
5429 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5430 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5431 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5432 tv.tv_sec, tv.tv_usec);
5436 switch (reset_level) {
5437 case HNS3_IMP_RESET:
5438 hns3_imp_reset_cmd(hw);
5439 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5440 tv.tv_sec, tv.tv_usec);
5442 case HNS3_GLOBAL_RESET:
5443 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5444 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5445 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5446 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5447 tv.tv_sec, tv.tv_usec);
5449 case HNS3_FUNC_RESET:
5450 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5451 tv.tv_sec, tv.tv_usec);
5452 /* schedule again to check later */
5453 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5454 hns3_schedule_reset(hns);
5457 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5460 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5463 static enum hns3_reset_level
5464 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5466 struct hns3_hw *hw = &hns->hw;
5467 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5469 /* Return the highest priority reset level amongst all */
5470 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5471 reset_level = HNS3_IMP_RESET;
5472 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5473 reset_level = HNS3_GLOBAL_RESET;
5474 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5475 reset_level = HNS3_FUNC_RESET;
5476 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5477 reset_level = HNS3_FLR_RESET;
5479 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5480 return HNS3_NONE_RESET;
5486 hns3_record_imp_error(struct hns3_adapter *hns)
5488 struct hns3_hw *hw = &hns->hw;
5491 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5492 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5493 hns3_warn(hw, "Detected IMP RD poison!");
5494 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5495 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5496 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5499 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5500 hns3_warn(hw, "Detected IMP CMDQ error!");
5501 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5502 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5503 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5508 hns3_prepare_reset(struct hns3_adapter *hns)
5510 struct hns3_hw *hw = &hns->hw;
5514 switch (hw->reset.level) {
5515 case HNS3_FUNC_RESET:
5516 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5521 * After performaning pf reset, it is not necessary to do the
5522 * mailbox handling or send any command to firmware, because
5523 * any mailbox handling or command to firmware is only valid
5524 * after hns3_cmd_init is called.
5526 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5527 hw->reset.stats.request_cnt++;
5529 case HNS3_IMP_RESET:
5530 hns3_record_imp_error(hns);
5531 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5532 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5533 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5542 hns3_set_rst_done(struct hns3_hw *hw)
5544 struct hns3_pf_rst_done_cmd *req;
5545 struct hns3_cmd_desc desc;
5547 req = (struct hns3_pf_rst_done_cmd *)desc.data;
5548 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5549 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5550 return hns3_cmd_send(hw, &desc, 1);
5554 hns3_stop_service(struct hns3_adapter *hns)
5556 struct hns3_hw *hw = &hns->hw;
5557 struct rte_eth_dev *eth_dev;
5559 eth_dev = &rte_eth_devices[hw->data->port_id];
5560 if (hw->adapter_state == HNS3_NIC_STARTED)
5561 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5562 hw->mac.link_status = ETH_LINK_DOWN;
5564 hns3_set_rxtx_function(eth_dev);
5566 /* Disable datapath on secondary process. */
5567 hns3_mp_req_stop_rxtx(eth_dev);
5568 rte_delay_ms(hw->tqps_num);
5570 rte_spinlock_lock(&hw->lock);
5571 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5572 hw->adapter_state == HNS3_NIC_STOPPING) {
5573 hns3_enable_all_queues(hw, false);
5575 hw->reset.mbuf_deferred_free = true;
5577 hw->reset.mbuf_deferred_free = false;
5580 * It is cumbersome for hardware to pick-and-choose entries for deletion
5581 * from table space. Hence, for function reset software intervention is
5582 * required to delete the entries
5584 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5585 hns3_configure_all_mc_mac_addr(hns, true);
5586 rte_spinlock_unlock(&hw->lock);
5592 hns3_start_service(struct hns3_adapter *hns)
5594 struct hns3_hw *hw = &hns->hw;
5595 struct rte_eth_dev *eth_dev;
5597 if (hw->reset.level == HNS3_IMP_RESET ||
5598 hw->reset.level == HNS3_GLOBAL_RESET)
5599 hns3_set_rst_done(hw);
5600 eth_dev = &rte_eth_devices[hw->data->port_id];
5601 hns3_set_rxtx_function(eth_dev);
5602 hns3_mp_req_start_rxtx(eth_dev);
5603 if (hw->adapter_state == HNS3_NIC_STARTED) {
5604 hns3_service_handler(eth_dev);
5606 /* Enable interrupt of all rx queues before enabling queues */
5607 hns3_dev_all_rx_queue_intr_enable(hw, true);
5609 * Enable state of each rxq and txq will be recovered after
5610 * reset, so we need to restore them before enable all tqps;
5612 hns3_restore_tqp_enable_state(hw);
5614 * When finished the initialization, enable queues to receive
5615 * and transmit packets.
5617 hns3_enable_all_queues(hw, true);
5624 hns3_restore_conf(struct hns3_adapter *hns)
5626 struct hns3_hw *hw = &hns->hw;
5629 ret = hns3_configure_all_mac_addr(hns, false);
5633 ret = hns3_configure_all_mc_mac_addr(hns, false);
5637 ret = hns3_dev_promisc_restore(hns);
5641 ret = hns3_restore_vlan_table(hns);
5645 ret = hns3_restore_vlan_conf(hns);
5649 ret = hns3_restore_all_fdir_filter(hns);
5653 ret = hns3_restore_rx_interrupt(hw);
5657 ret = hns3_restore_gro_conf(hw);
5661 ret = hns3_restore_fec(hw);
5665 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5666 ret = hns3_do_start(hns, false);
5669 hns3_info(hw, "hns3 dev restart successful!");
5670 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5671 hw->adapter_state = HNS3_NIC_CONFIGURED;
5675 hns3_configure_all_mc_mac_addr(hns, true);
5677 hns3_configure_all_mac_addr(hns, true);
5682 hns3_reset_service(void *param)
5684 struct hns3_adapter *hns = (struct hns3_adapter *)param;
5685 struct hns3_hw *hw = &hns->hw;
5686 enum hns3_reset_level reset_level;
5687 struct timeval tv_delta;
5688 struct timeval tv_start;
5694 * The interrupt is not triggered within the delay time.
5695 * The interrupt may have been lost. It is necessary to handle
5696 * the interrupt to recover from the error.
5698 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5699 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5700 hns3_err(hw, "Handling interrupts in delayed tasks");
5701 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5702 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5703 if (reset_level == HNS3_NONE_RESET) {
5704 hns3_err(hw, "No reset level is set, try IMP reset");
5705 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5708 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5711 * Check if there is any ongoing reset in the hardware. This status can
5712 * be checked from reset_pending. If there is then, we need to wait for
5713 * hardware to complete reset.
5714 * a. If we are able to figure out in reasonable time that hardware
5715 * has fully resetted then, we can proceed with driver, client
5717 * b. else, we can come back later to check this status so re-sched
5720 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5721 if (reset_level != HNS3_NONE_RESET) {
5722 gettimeofday(&tv_start, NULL);
5723 ret = hns3_reset_process(hns, reset_level);
5724 gettimeofday(&tv, NULL);
5725 timersub(&tv, &tv_start, &tv_delta);
5726 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5727 tv_delta.tv_usec / USEC_PER_MSEC;
5728 if (msec > HNS3_RESET_PROCESS_MS)
5729 hns3_err(hw, "%d handle long time delta %" PRIx64
5730 " ms time=%ld.%.6ld",
5731 hw->reset.level, msec,
5732 tv.tv_sec, tv.tv_usec);
5737 /* Check if we got any *new* reset requests to be honored */
5738 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5739 if (reset_level != HNS3_NONE_RESET)
5740 hns3_msix_process(hns, reset_level);
5744 hns3_get_speed_capa_num(uint16_t device_id)
5748 switch (device_id) {
5749 case HNS3_DEV_ID_25GE:
5750 case HNS3_DEV_ID_25GE_RDMA:
5753 case HNS3_DEV_ID_100G_RDMA_MACSEC:
5754 case HNS3_DEV_ID_200G_RDMA:
5766 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
5769 switch (device_id) {
5770 case HNS3_DEV_ID_25GE:
5772 case HNS3_DEV_ID_25GE_RDMA:
5773 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
5774 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
5776 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
5777 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
5778 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
5780 case HNS3_DEV_ID_100G_RDMA_MACSEC:
5781 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
5782 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
5784 case HNS3_DEV_ID_200G_RDMA:
5785 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
5786 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
5796 hns3_fec_get_capability(struct rte_eth_dev *dev,
5797 struct rte_eth_fec_capa *speed_fec_capa,
5800 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5801 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5802 uint16_t device_id = pci_dev->id.device_id;
5803 unsigned int capa_num;
5806 capa_num = hns3_get_speed_capa_num(device_id);
5807 if (capa_num == 0) {
5808 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
5813 if (speed_fec_capa == NULL || num < capa_num)
5816 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
5824 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
5826 struct hns3_config_fec_cmd *req;
5827 struct hns3_cmd_desc desc;
5831 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
5832 * in device of link speed
5835 if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
5840 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
5841 req = (struct hns3_config_fec_cmd *)desc.data;
5842 ret = hns3_cmd_send(hw, &desc, 1);
5844 hns3_err(hw, "get current fec auto state failed, ret = %d",
5849 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
5854 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
5856 #define QUERY_ACTIVE_SPEED 1
5857 struct hns3_sfp_speed_cmd *resp;
5858 uint32_t tmp_fec_capa;
5860 struct hns3_cmd_desc desc;
5864 * If link is down and AUTO is enabled, AUTO is returned, otherwise,
5865 * configured FEC mode is returned.
5866 * If link is up, current FEC mode is returned.
5868 if (hw->mac.link_status == ETH_LINK_DOWN) {
5869 ret = get_current_fec_auto_state(hw, &auto_state);
5873 if (auto_state == 0x1) {
5874 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
5879 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
5880 resp = (struct hns3_sfp_speed_cmd *)desc.data;
5881 resp->query_type = QUERY_ACTIVE_SPEED;
5883 ret = hns3_cmd_send(hw, &desc, 1);
5884 if (ret == -EOPNOTSUPP) {
5885 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
5888 hns3_err(hw, "get FEC failed, ret = %d", ret);
5893 * FEC mode order defined in hns3 hardware is inconsistend with
5894 * that defined in the ethdev library. So the sequence needs
5897 switch (resp->active_fec) {
5898 case HNS3_HW_FEC_MODE_NOFEC:
5899 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5901 case HNS3_HW_FEC_MODE_BASER:
5902 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
5904 case HNS3_HW_FEC_MODE_RS:
5905 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
5908 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5912 *fec_capa = tmp_fec_capa;
5917 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
5919 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5921 return hns3_fec_get_internal(hw, fec_capa);
5925 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
5927 struct hns3_config_fec_cmd *req;
5928 struct hns3_cmd_desc desc;
5931 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
5933 req = (struct hns3_config_fec_cmd *)desc.data;
5935 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
5936 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5937 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
5939 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
5940 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5941 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
5943 case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
5944 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5945 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
5947 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
5948 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
5953 ret = hns3_cmd_send(hw, &desc, 1);
5955 hns3_err(hw, "set fec mode failed, ret = %d", ret);
5961 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
5963 struct hns3_mac *mac = &hw->mac;
5966 switch (mac->link_speed) {
5967 case ETH_SPEED_NUM_10G:
5968 cur_capa = fec_capa[1].capa;
5970 case ETH_SPEED_NUM_25G:
5971 case ETH_SPEED_NUM_100G:
5972 case ETH_SPEED_NUM_200G:
5973 cur_capa = fec_capa[0].capa;
5984 is_fec_mode_one_bit_set(uint32_t mode)
5989 for (i = 0; i < sizeof(mode); i++)
5990 if (mode >> i & 0x1)
5993 return cnt == 1 ? true : false;
5997 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
5999 #define FEC_CAPA_NUM 2
6000 struct hns3_adapter *hns = dev->data->dev_private;
6001 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6002 struct hns3_pf *pf = &hns->pf;
6004 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6006 uint32_t num = FEC_CAPA_NUM;
6009 ret = hns3_fec_get_capability(dev, fec_capa, num);
6013 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6014 if (!is_fec_mode_one_bit_set(mode))
6015 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6016 "FEC mode should be only one bit set", mode);
6019 * Check whether the configured mode is within the FEC capability.
6020 * If not, the configured mode will not be supported.
6022 cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6023 if (!(cur_capa & mode)) {
6024 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6028 ret = hns3_set_fec_hw(hw, mode);
6032 pf->fec_mode = mode;
6037 hns3_restore_fec(struct hns3_hw *hw)
6039 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6040 struct hns3_pf *pf = &hns->pf;
6041 uint32_t mode = pf->fec_mode;
6044 ret = hns3_set_fec_hw(hw, mode);
6046 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6053 hns3_query_dev_fec_info(struct hns3_hw *hw)
6055 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6056 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6059 ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6061 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6066 static const struct eth_dev_ops hns3_eth_dev_ops = {
6067 .dev_configure = hns3_dev_configure,
6068 .dev_start = hns3_dev_start,
6069 .dev_stop = hns3_dev_stop,
6070 .dev_close = hns3_dev_close,
6071 .promiscuous_enable = hns3_dev_promiscuous_enable,
6072 .promiscuous_disable = hns3_dev_promiscuous_disable,
6073 .allmulticast_enable = hns3_dev_allmulticast_enable,
6074 .allmulticast_disable = hns3_dev_allmulticast_disable,
6075 .mtu_set = hns3_dev_mtu_set,
6076 .stats_get = hns3_stats_get,
6077 .stats_reset = hns3_stats_reset,
6078 .xstats_get = hns3_dev_xstats_get,
6079 .xstats_get_names = hns3_dev_xstats_get_names,
6080 .xstats_reset = hns3_dev_xstats_reset,
6081 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
6082 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6083 .dev_infos_get = hns3_dev_infos_get,
6084 .fw_version_get = hns3_fw_version_get,
6085 .rx_queue_setup = hns3_rx_queue_setup,
6086 .tx_queue_setup = hns3_tx_queue_setup,
6087 .rx_queue_release = hns3_dev_rx_queue_release,
6088 .tx_queue_release = hns3_dev_tx_queue_release,
6089 .rx_queue_start = hns3_dev_rx_queue_start,
6090 .rx_queue_stop = hns3_dev_rx_queue_stop,
6091 .tx_queue_start = hns3_dev_tx_queue_start,
6092 .tx_queue_stop = hns3_dev_tx_queue_stop,
6093 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
6094 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
6095 .rxq_info_get = hns3_rxq_info_get,
6096 .txq_info_get = hns3_txq_info_get,
6097 .rx_burst_mode_get = hns3_rx_burst_mode_get,
6098 .tx_burst_mode_get = hns3_tx_burst_mode_get,
6099 .flow_ctrl_get = hns3_flow_ctrl_get,
6100 .flow_ctrl_set = hns3_flow_ctrl_set,
6101 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6102 .mac_addr_add = hns3_add_mac_addr,
6103 .mac_addr_remove = hns3_remove_mac_addr,
6104 .mac_addr_set = hns3_set_default_mac_addr,
6105 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
6106 .link_update = hns3_dev_link_update,
6107 .rss_hash_update = hns3_dev_rss_hash_update,
6108 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
6109 .reta_update = hns3_dev_rss_reta_update,
6110 .reta_query = hns3_dev_rss_reta_query,
6111 .filter_ctrl = hns3_dev_filter_ctrl,
6112 .vlan_filter_set = hns3_vlan_filter_set,
6113 .vlan_tpid_set = hns3_vlan_tpid_set,
6114 .vlan_offload_set = hns3_vlan_offload_set,
6115 .vlan_pvid_set = hns3_vlan_pvid_set,
6116 .get_reg = hns3_get_regs,
6117 .get_dcb_info = hns3_get_dcb_info,
6118 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6119 .fec_get_capability = hns3_fec_get_capability,
6120 .fec_get = hns3_fec_get,
6121 .fec_set = hns3_fec_set,
6122 .tm_ops_get = hns3_tm_ops_get,
6125 static const struct hns3_reset_ops hns3_reset_ops = {
6126 .reset_service = hns3_reset_service,
6127 .stop_service = hns3_stop_service,
6128 .prepare_reset = hns3_prepare_reset,
6129 .wait_hardware_ready = hns3_wait_hardware_ready,
6130 .reinit_dev = hns3_reinit_dev,
6131 .restore_conf = hns3_restore_conf,
6132 .start_service = hns3_start_service,
6136 hns3_dev_init(struct rte_eth_dev *eth_dev)
6138 struct hns3_adapter *hns = eth_dev->data->dev_private;
6139 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6140 struct rte_ether_addr *eth_addr;
6141 struct hns3_hw *hw = &hns->hw;
6144 PMD_INIT_FUNC_TRACE();
6146 eth_dev->process_private = (struct hns3_process_private *)
6147 rte_zmalloc_socket("hns3_filter_list",
6148 sizeof(struct hns3_process_private),
6149 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6150 if (eth_dev->process_private == NULL) {
6151 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6154 /* initialize flow filter lists */
6155 hns3_filterlist_init(eth_dev);
6157 hns3_set_rxtx_function(eth_dev);
6158 eth_dev->dev_ops = &hns3_eth_dev_ops;
6159 eth_dev->rx_queue_count = hns3_rx_queue_count;
6160 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6161 ret = hns3_mp_init_secondary();
6163 PMD_INIT_LOG(ERR, "Failed to init for secondary "
6164 "process, ret = %d", ret);
6165 goto err_mp_init_secondary;
6168 hw->secondary_cnt++;
6172 ret = hns3_mp_init_primary();
6175 "Failed to init for primary process, ret = %d",
6177 goto err_mp_init_primary;
6180 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6182 hw->data = eth_dev->data;
6185 * Set default max packet size according to the mtu
6186 * default vale in DPDK frame.
6188 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6190 ret = hns3_reset_init(hw);
6192 goto err_init_reset;
6193 hw->reset.ops = &hns3_reset_ops;
6195 ret = hns3_init_pf(eth_dev);
6197 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6201 /* Allocate memory for storing MAC addresses */
6202 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6203 sizeof(struct rte_ether_addr) *
6204 HNS3_UC_MACADDR_NUM, 0);
6205 if (eth_dev->data->mac_addrs == NULL) {
6206 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6207 "to store MAC addresses",
6208 sizeof(struct rte_ether_addr) *
6209 HNS3_UC_MACADDR_NUM);
6211 goto err_rte_zmalloc;
6214 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6215 if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6216 rte_eth_random_addr(hw->mac.mac_addr);
6217 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6218 (struct rte_ether_addr *)hw->mac.mac_addr);
6219 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6220 "unicast address, using random MAC address %s",
6223 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6224 ð_dev->data->mac_addrs[0]);
6226 hw->adapter_state = HNS3_NIC_INITIALIZED;
6228 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
6229 hns3_err(hw, "Reschedule reset service after dev_init");
6230 hns3_schedule_reset(hns);
6232 /* IMP will wait ready flag before reset */
6233 hns3_notify_reset_ready(hw, false);
6236 hns3_info(hw, "hns3 dev initialization successful!");
6240 hns3_uninit_pf(eth_dev);
6243 rte_free(hw->reset.wait_data);
6246 hns3_mp_uninit_primary();
6248 err_mp_init_primary:
6249 err_mp_init_secondary:
6250 eth_dev->dev_ops = NULL;
6251 eth_dev->rx_pkt_burst = NULL;
6252 eth_dev->tx_pkt_burst = NULL;
6253 eth_dev->tx_pkt_prepare = NULL;
6254 rte_free(eth_dev->process_private);
6255 eth_dev->process_private = NULL;
6260 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6262 struct hns3_adapter *hns = eth_dev->data->dev_private;
6263 struct hns3_hw *hw = &hns->hw;
6265 PMD_INIT_FUNC_TRACE();
6267 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6268 rte_free(eth_dev->process_private);
6269 eth_dev->process_private = NULL;
6273 if (hw->adapter_state < HNS3_NIC_CLOSING)
6274 hns3_dev_close(eth_dev);
6276 hw->adapter_state = HNS3_NIC_REMOVED;
6281 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6282 struct rte_pci_device *pci_dev)
6284 return rte_eth_dev_pci_generic_probe(pci_dev,
6285 sizeof(struct hns3_adapter),
6290 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6292 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6295 static const struct rte_pci_id pci_id_hns3_map[] = {
6296 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6297 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6298 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6299 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6300 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6301 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6302 { .vendor_id = 0, }, /* sentinel */
6305 static struct rte_pci_driver rte_hns3_pmd = {
6306 .id_table = pci_id_hns3_map,
6307 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6308 .probe = eth_hns3_pci_probe,
6309 .remove = eth_hns3_pci_remove,
6312 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6313 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6314 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6315 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6316 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);