1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
6 #include <rte_bus_pci.h>
7 #include <ethdev_pci.h>
10 #include "hns3_ethdev.h"
11 #include "hns3_logs.h"
12 #include "hns3_rxtx.h"
13 #include "hns3_intr.h"
14 #include "hns3_regs.h"
18 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
19 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
21 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
22 #define HNS3_SERVICE_QUICK_INTERVAL 10
23 #define HNS3_INVALID_PVID 0xFFFF
25 #define HNS3_FILTER_TYPE_VF 0
26 #define HNS3_FILTER_TYPE_PORT 1
27 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
28 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
29 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
30 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
31 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
32 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
33 | HNS3_FILTER_FE_ROCE_EGRESS_B)
34 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
35 | HNS3_FILTER_FE_ROCE_INGRESS_B)
37 /* Reset related Registers */
38 #define HNS3_GLOBAL_RESET_BIT 0
39 #define HNS3_CORE_RESET_BIT 1
40 #define HNS3_IMP_RESET_BIT 2
41 #define HNS3_FUN_RST_ING_B 0
43 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
44 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
45 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U
46 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
48 #define HNS3_RESET_WAIT_MS 100
49 #define HNS3_RESET_WAIT_CNT 200
51 /* FEC mode order defined in HNS3 hardware */
52 #define HNS3_HW_FEC_MODE_NOFEC 0
53 #define HNS3_HW_FEC_MODE_BASER 1
54 #define HNS3_HW_FEC_MODE_RS 2
57 HNS3_VECTOR0_EVENT_RST,
58 HNS3_VECTOR0_EVENT_MBX,
59 HNS3_VECTOR0_EVENT_ERR,
60 HNS3_VECTOR0_EVENT_OTHER,
63 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
64 { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
65 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
66 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
68 { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
69 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
70 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
71 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
73 { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
74 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
75 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
77 { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
78 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
79 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
80 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
82 { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
83 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
84 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
86 { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
87 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
88 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
91 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
93 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
94 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
96 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
97 static bool hns3_update_link_status(struct hns3_hw *hw);
99 static int hns3_add_mc_addr(struct hns3_hw *hw,
100 struct rte_ether_addr *mac_addr);
101 static int hns3_remove_mc_addr(struct hns3_hw *hw,
102 struct rte_ether_addr *mac_addr);
103 static int hns3_restore_fec(struct hns3_hw *hw);
104 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
106 void hns3_ether_format_addr(char *buf, uint16_t size,
107 const struct rte_ether_addr *ether_addr)
109 snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
110 ether_addr->addr_bytes[0],
111 ether_addr->addr_bytes[4],
112 ether_addr->addr_bytes[5]);
116 hns3_pf_disable_irq0(struct hns3_hw *hw)
118 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
122 hns3_pf_enable_irq0(struct hns3_hw *hw)
124 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
127 static enum hns3_evt_cause
128 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
131 struct hns3_hw *hw = &hns->hw;
133 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
134 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
135 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
137 hw->reset.stats.imp_cnt++;
138 hns3_warn(hw, "IMP reset detected, clear reset status");
140 hns3_schedule_delayed_reset(hns);
141 hns3_warn(hw, "IMP reset detected, don't clear reset status");
144 return HNS3_VECTOR0_EVENT_RST;
147 static enum hns3_evt_cause
148 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
151 struct hns3_hw *hw = &hns->hw;
153 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
154 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
155 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
157 hw->reset.stats.global_cnt++;
158 hns3_warn(hw, "Global reset detected, clear reset status");
160 hns3_schedule_delayed_reset(hns);
162 "Global reset detected, don't clear reset status");
165 return HNS3_VECTOR0_EVENT_RST;
168 static enum hns3_evt_cause
169 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
171 struct hns3_hw *hw = &hns->hw;
172 uint32_t vector0_int_stats;
173 uint32_t cmdq_src_val;
174 uint32_t hw_err_src_reg;
176 enum hns3_evt_cause ret;
179 /* fetch the events from their corresponding regs */
180 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
181 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
182 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
184 is_delay = clearval == NULL ? true : false;
186 * Assumption: If by any chance reset and mailbox events are reported
187 * together then we will only process reset event and defer the
188 * processing of the mailbox events. Since, we would have not cleared
189 * RX CMDQ event this time we would receive again another interrupt
190 * from H/W just for the mailbox.
192 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
193 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
198 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
199 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
203 /* check for vector0 msix event source */
204 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
205 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
206 val = vector0_int_stats | hw_err_src_reg;
207 ret = HNS3_VECTOR0_EVENT_ERR;
211 /* check for vector0 mailbox(=CMDQ RX) event source */
212 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
213 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
215 ret = HNS3_VECTOR0_EVENT_MBX;
219 if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
220 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
221 vector0_int_stats, cmdq_src_val, hw_err_src_reg);
222 val = vector0_int_stats;
223 ret = HNS3_VECTOR0_EVENT_OTHER;
232 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
234 if (event_type == HNS3_VECTOR0_EVENT_RST)
235 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
236 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
237 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
241 hns3_clear_all_event_cause(struct hns3_hw *hw)
243 uint32_t vector0_int_stats;
244 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
246 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
247 hns3_warn(hw, "Probe during IMP reset interrupt");
249 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
250 hns3_warn(hw, "Probe during Global reset interrupt");
252 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
253 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
254 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
255 BIT(HNS3_VECTOR0_CORERESET_INT_B));
256 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
260 hns3_interrupt_handler(void *param)
262 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
263 struct hns3_adapter *hns = dev->data->dev_private;
264 struct hns3_hw *hw = &hns->hw;
265 enum hns3_evt_cause event_cause;
266 uint32_t clearval = 0;
268 /* Disable interrupt */
269 hns3_pf_disable_irq0(hw);
271 event_cause = hns3_check_event_cause(hns, &clearval);
272 /* vector 0 interrupt is shared with reset and mailbox source events. */
273 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
274 hns3_warn(hw, "Received err interrupt");
275 hns3_handle_msix_error(hns, &hw->reset.request);
276 hns3_handle_ras_error(hns, &hw->reset.request);
277 hns3_schedule_reset(hns);
278 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
279 hns3_warn(hw, "Received reset interrupt");
280 hns3_schedule_reset(hns);
281 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
282 hns3_dev_handle_mbx_msg(hw);
284 hns3_err(hw, "Received unknown event");
286 hns3_clear_event_cause(hw, event_cause, clearval);
287 /* Enable interrupt if it is not cause by reset */
288 hns3_pf_enable_irq0(hw);
292 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
294 #define HNS3_VLAN_ID_OFFSET_STEP 160
295 #define HNS3_VLAN_BYTE_SIZE 8
296 struct hns3_vlan_filter_pf_cfg_cmd *req;
297 struct hns3_hw *hw = &hns->hw;
298 uint8_t vlan_offset_byte_val;
299 struct hns3_cmd_desc desc;
300 uint8_t vlan_offset_byte;
301 uint8_t vlan_offset_base;
304 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
306 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
307 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
309 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
311 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
312 req->vlan_offset = vlan_offset_base;
313 req->vlan_cfg = on ? 0 : 1;
314 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
316 ret = hns3_cmd_send(hw, &desc, 1);
318 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
325 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
327 struct hns3_user_vlan_table *vlan_entry;
328 struct hns3_pf *pf = &hns->pf;
330 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
331 if (vlan_entry->vlan_id == vlan_id) {
332 if (vlan_entry->hd_tbl_status)
333 hns3_set_port_vlan_filter(hns, vlan_id, 0);
334 LIST_REMOVE(vlan_entry, next);
335 rte_free(vlan_entry);
342 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
345 struct hns3_user_vlan_table *vlan_entry;
346 struct hns3_hw *hw = &hns->hw;
347 struct hns3_pf *pf = &hns->pf;
349 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
350 if (vlan_entry->vlan_id == vlan_id)
354 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
355 if (vlan_entry == NULL) {
356 hns3_err(hw, "Failed to malloc hns3 vlan table");
360 vlan_entry->hd_tbl_status = writen_to_tbl;
361 vlan_entry->vlan_id = vlan_id;
363 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
367 hns3_restore_vlan_table(struct hns3_adapter *hns)
369 struct hns3_user_vlan_table *vlan_entry;
370 struct hns3_hw *hw = &hns->hw;
371 struct hns3_pf *pf = &hns->pf;
375 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
376 return hns3_vlan_pvid_configure(hns,
377 hw->port_base_vlan_cfg.pvid, 1);
379 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
380 if (vlan_entry->hd_tbl_status) {
381 vlan_id = vlan_entry->vlan_id;
382 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
392 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
394 struct hns3_hw *hw = &hns->hw;
395 bool writen_to_tbl = false;
399 * When vlan filter is enabled, hardware regards packets without vlan
400 * as packets with vlan 0. So, to receive packets without vlan, vlan id
401 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
403 if (on == 0 && vlan_id == 0)
407 * When port base vlan enabled, we use port base vlan as the vlan
408 * filter condition. In this case, we don't update vlan filter table
409 * when user add new vlan or remove exist vlan, just update the
410 * vlan list. The vlan id in vlan list will be writen in vlan filter
411 * table until port base vlan disabled
413 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
414 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
415 writen_to_tbl = true;
420 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
422 hns3_rm_dev_vlan_table(hns, vlan_id);
428 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
430 struct hns3_adapter *hns = dev->data->dev_private;
431 struct hns3_hw *hw = &hns->hw;
434 rte_spinlock_lock(&hw->lock);
435 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
436 rte_spinlock_unlock(&hw->lock);
441 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
444 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
445 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
446 struct hns3_hw *hw = &hns->hw;
447 struct hns3_cmd_desc desc;
450 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
451 vlan_type != ETH_VLAN_TYPE_OUTER)) {
452 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
456 if (tpid != RTE_ETHER_TYPE_VLAN) {
457 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
461 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
462 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
464 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
465 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
466 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
467 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
468 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
469 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
470 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
471 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
474 ret = hns3_cmd_send(hw, &desc, 1);
476 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
481 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
483 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
484 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
485 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
487 ret = hns3_cmd_send(hw, &desc, 1);
489 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
495 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
498 struct hns3_adapter *hns = dev->data->dev_private;
499 struct hns3_hw *hw = &hns->hw;
502 rte_spinlock_lock(&hw->lock);
503 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
504 rte_spinlock_unlock(&hw->lock);
509 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
510 struct hns3_rx_vtag_cfg *vcfg)
512 struct hns3_vport_vtag_rx_cfg_cmd *req;
513 struct hns3_hw *hw = &hns->hw;
514 struct hns3_cmd_desc desc;
519 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
521 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
522 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
523 vcfg->strip_tag1_en ? 1 : 0);
524 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
525 vcfg->strip_tag2_en ? 1 : 0);
526 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
527 vcfg->vlan1_vlan_prionly ? 1 : 0);
528 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
529 vcfg->vlan2_vlan_prionly ? 1 : 0);
531 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
532 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
533 vcfg->strip_tag1_discard_en ? 1 : 0);
534 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
535 vcfg->strip_tag2_discard_en ? 1 : 0);
537 * In current version VF is not supported when PF is driven by DPDK
538 * driver, just need to configure parameters for PF vport.
540 vport_id = HNS3_PF_FUNC_ID;
541 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
542 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
543 req->vf_bitmap[req->vf_offset] = bitmap;
545 ret = hns3_cmd_send(hw, &desc, 1);
547 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
552 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
553 struct hns3_rx_vtag_cfg *vcfg)
555 struct hns3_pf *pf = &hns->pf;
556 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
560 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
561 struct hns3_tx_vtag_cfg *vcfg)
563 struct hns3_pf *pf = &hns->pf;
564 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
568 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
570 struct hns3_rx_vtag_cfg rxvlan_cfg;
571 struct hns3_hw *hw = &hns->hw;
574 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
575 rxvlan_cfg.strip_tag1_en = false;
576 rxvlan_cfg.strip_tag2_en = enable;
577 rxvlan_cfg.strip_tag2_discard_en = false;
579 rxvlan_cfg.strip_tag1_en = enable;
580 rxvlan_cfg.strip_tag2_en = true;
581 rxvlan_cfg.strip_tag2_discard_en = true;
584 rxvlan_cfg.strip_tag1_discard_en = false;
585 rxvlan_cfg.vlan1_vlan_prionly = false;
586 rxvlan_cfg.vlan2_vlan_prionly = false;
587 rxvlan_cfg.rx_vlan_offload_en = enable;
589 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
591 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
595 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
601 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
602 uint8_t fe_type, bool filter_en, uint8_t vf_id)
604 struct hns3_vlan_filter_ctrl_cmd *req;
605 struct hns3_cmd_desc desc;
608 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
610 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
611 req->vlan_type = vlan_type;
612 req->vlan_fe = filter_en ? fe_type : 0;
615 ret = hns3_cmd_send(hw, &desc, 1);
617 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
623 hns3_vlan_filter_init(struct hns3_adapter *hns)
625 struct hns3_hw *hw = &hns->hw;
628 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
629 HNS3_FILTER_FE_EGRESS, false,
632 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
636 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
637 HNS3_FILTER_FE_INGRESS, false,
640 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
646 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
648 struct hns3_hw *hw = &hns->hw;
651 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
652 HNS3_FILTER_FE_INGRESS, enable,
655 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
656 enable ? "enable" : "disable", ret);
662 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
664 struct hns3_adapter *hns = dev->data->dev_private;
665 struct hns3_hw *hw = &hns->hw;
666 struct rte_eth_rxmode *rxmode;
667 unsigned int tmp_mask;
671 rte_spinlock_lock(&hw->lock);
672 rxmode = &dev->data->dev_conf.rxmode;
673 tmp_mask = (unsigned int)mask;
674 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
675 /* ignore vlan filter configuration during promiscuous mode */
676 if (!dev->data->promiscuous) {
677 /* Enable or disable VLAN filter */
678 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
681 ret = hns3_enable_vlan_filter(hns, enable);
683 rte_spinlock_unlock(&hw->lock);
684 hns3_err(hw, "failed to %s rx filter, ret = %d",
685 enable ? "enable" : "disable", ret);
691 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
692 /* Enable or disable VLAN stripping */
693 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
696 ret = hns3_en_hw_strip_rxvtag(hns, enable);
698 rte_spinlock_unlock(&hw->lock);
699 hns3_err(hw, "failed to %s rx strip, ret = %d",
700 enable ? "enable" : "disable", ret);
705 rte_spinlock_unlock(&hw->lock);
711 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
712 struct hns3_tx_vtag_cfg *vcfg)
714 struct hns3_vport_vtag_tx_cfg_cmd *req;
715 struct hns3_cmd_desc desc;
716 struct hns3_hw *hw = &hns->hw;
721 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
723 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
724 req->def_vlan_tag1 = vcfg->default_tag1;
725 req->def_vlan_tag2 = vcfg->default_tag2;
726 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
727 vcfg->accept_tag1 ? 1 : 0);
728 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
729 vcfg->accept_untag1 ? 1 : 0);
730 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
731 vcfg->accept_tag2 ? 1 : 0);
732 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
733 vcfg->accept_untag2 ? 1 : 0);
734 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
735 vcfg->insert_tag1_en ? 1 : 0);
736 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
737 vcfg->insert_tag2_en ? 1 : 0);
738 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
740 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
741 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
742 vcfg->tag_shift_mode_en ? 1 : 0);
745 * In current version VF is not supported when PF is driven by DPDK
746 * driver, just need to configure parameters for PF vport.
748 vport_id = HNS3_PF_FUNC_ID;
749 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
750 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
751 req->vf_bitmap[req->vf_offset] = bitmap;
753 ret = hns3_cmd_send(hw, &desc, 1);
755 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
761 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
764 struct hns3_hw *hw = &hns->hw;
765 struct hns3_tx_vtag_cfg txvlan_cfg;
768 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
769 txvlan_cfg.accept_tag1 = true;
770 txvlan_cfg.insert_tag1_en = false;
771 txvlan_cfg.default_tag1 = 0;
773 txvlan_cfg.accept_tag1 =
774 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
775 txvlan_cfg.insert_tag1_en = true;
776 txvlan_cfg.default_tag1 = pvid;
779 txvlan_cfg.accept_untag1 = true;
780 txvlan_cfg.accept_tag2 = true;
781 txvlan_cfg.accept_untag2 = true;
782 txvlan_cfg.insert_tag2_en = false;
783 txvlan_cfg.default_tag2 = 0;
784 txvlan_cfg.tag_shift_mode_en = true;
786 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
788 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
793 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
799 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
801 struct hns3_user_vlan_table *vlan_entry;
802 struct hns3_pf *pf = &hns->pf;
804 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
805 if (vlan_entry->hd_tbl_status) {
806 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
807 vlan_entry->hd_tbl_status = false;
812 vlan_entry = LIST_FIRST(&pf->vlan_list);
814 LIST_REMOVE(vlan_entry, next);
815 rte_free(vlan_entry);
816 vlan_entry = LIST_FIRST(&pf->vlan_list);
822 hns3_add_all_vlan_table(struct hns3_adapter *hns)
824 struct hns3_user_vlan_table *vlan_entry;
825 struct hns3_pf *pf = &hns->pf;
827 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
828 if (!vlan_entry->hd_tbl_status) {
829 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
830 vlan_entry->hd_tbl_status = true;
836 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
838 struct hns3_hw *hw = &hns->hw;
841 hns3_rm_all_vlan_table(hns, true);
842 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
843 ret = hns3_set_port_vlan_filter(hns,
844 hw->port_base_vlan_cfg.pvid, 0);
846 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
854 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
855 uint16_t port_base_vlan_state, uint16_t new_pvid)
857 struct hns3_hw *hw = &hns->hw;
861 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
862 old_pvid = hw->port_base_vlan_cfg.pvid;
863 if (old_pvid != HNS3_INVALID_PVID) {
864 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
866 hns3_err(hw, "failed to remove old pvid %u, "
867 "ret = %d", old_pvid, ret);
872 hns3_rm_all_vlan_table(hns, false);
873 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
875 hns3_err(hw, "failed to add new pvid %u, ret = %d",
880 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
882 hns3_err(hw, "failed to remove pvid %u, ret = %d",
887 hns3_add_all_vlan_table(hns);
893 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
895 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
896 struct hns3_rx_vtag_cfg rx_vlan_cfg;
900 rx_strip_en = old_cfg->rx_vlan_offload_en;
902 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
903 rx_vlan_cfg.strip_tag2_en = true;
904 rx_vlan_cfg.strip_tag2_discard_en = true;
906 rx_vlan_cfg.strip_tag1_en = false;
907 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
908 rx_vlan_cfg.strip_tag2_discard_en = false;
910 rx_vlan_cfg.strip_tag1_discard_en = false;
911 rx_vlan_cfg.vlan1_vlan_prionly = false;
912 rx_vlan_cfg.vlan2_vlan_prionly = false;
913 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
915 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
919 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
924 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
926 struct hns3_hw *hw = &hns->hw;
927 uint16_t port_base_vlan_state;
930 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
931 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
932 hns3_warn(hw, "Invalid operation! As current pvid set "
933 "is %u, disable pvid %u is invalid",
934 hw->port_base_vlan_cfg.pvid, pvid);
938 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
939 HNS3_PORT_BASE_VLAN_DISABLE;
940 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
942 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
947 ret = hns3_en_pvid_strip(hns, on);
949 hns3_err(hw, "failed to config rx vlan strip for pvid, "
954 if (pvid == HNS3_INVALID_PVID)
956 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
958 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
964 hw->port_base_vlan_cfg.state = port_base_vlan_state;
965 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
970 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
972 struct hns3_adapter *hns = dev->data->dev_private;
973 struct hns3_hw *hw = &hns->hw;
974 bool pvid_en_state_change;
978 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
979 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
980 RTE_ETHER_MAX_VLAN_ID);
985 * If PVID configuration state change, should refresh the PVID
986 * configuration state in struct hns3_tx_queue/hns3_rx_queue.
988 pvid_state = hw->port_base_vlan_cfg.state;
989 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
990 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
991 pvid_en_state_change = false;
993 pvid_en_state_change = true;
995 rte_spinlock_lock(&hw->lock);
996 ret = hns3_vlan_pvid_configure(hns, pvid, on);
997 rte_spinlock_unlock(&hw->lock);
1001 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1002 * need be processed by PMD driver.
1004 if (pvid_en_state_change &&
1005 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1006 hns3_update_all_queues_pvid_proc_en(hw);
1012 hns3_default_vlan_config(struct hns3_adapter *hns)
1014 struct hns3_hw *hw = &hns->hw;
1018 * When vlan filter is enabled, hardware regards packets without vlan
1019 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1020 * table, packets without vlan won't be received. So, add vlan 0 as
1023 ret = hns3_vlan_filter_configure(hns, 0, 1);
1025 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1030 hns3_init_vlan_config(struct hns3_adapter *hns)
1032 struct hns3_hw *hw = &hns->hw;
1036 * This function can be called in the initialization and reset process,
1037 * when in reset process, it means that hardware had been reseted
1038 * successfully and we need to restore the hardware configuration to
1039 * ensure that the hardware configuration remains unchanged before and
1042 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1043 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1044 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1047 ret = hns3_vlan_filter_init(hns);
1049 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1053 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1054 RTE_ETHER_TYPE_VLAN);
1056 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1061 * When in the reinit dev stage of the reset process, the following
1062 * vlan-related configurations may differ from those at initialization,
1063 * we will restore configurations to hardware in hns3_restore_vlan_table
1064 * and hns3_restore_vlan_conf later.
1066 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1067 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1069 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1073 ret = hns3_en_hw_strip_rxvtag(hns, false);
1075 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1081 return hns3_default_vlan_config(hns);
1085 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1087 struct hns3_pf *pf = &hns->pf;
1088 struct hns3_hw *hw = &hns->hw;
1093 if (!hw->data->promiscuous) {
1094 /* restore vlan filter states */
1095 offloads = hw->data->dev_conf.rxmode.offloads;
1096 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1097 ret = hns3_enable_vlan_filter(hns, enable);
1099 hns3_err(hw, "failed to restore vlan rx filter conf, "
1105 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1107 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1111 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1113 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1119 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1121 struct hns3_adapter *hns = dev->data->dev_private;
1122 struct rte_eth_dev_data *data = dev->data;
1123 struct rte_eth_txmode *txmode;
1124 struct hns3_hw *hw = &hns->hw;
1128 txmode = &data->dev_conf.txmode;
1129 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1131 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1132 "configuration is not supported! Ignore these two "
1133 "parameters: hw_vlan_reject_tagged(%u), "
1134 "hw_vlan_reject_untagged(%u)",
1135 txmode->hw_vlan_reject_tagged,
1136 txmode->hw_vlan_reject_untagged);
1138 /* Apply vlan offload setting */
1139 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1140 ret = hns3_vlan_offload_set(dev, mask);
1142 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1148 * If pvid config is not set in rte_eth_conf, driver needn't to set
1149 * VLAN pvid related configuration to hardware.
1151 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1154 /* Apply pvid setting */
1155 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1156 txmode->hw_vlan_insert_pvid);
1158 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1165 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1166 unsigned int tso_mss_max)
1168 struct hns3_cfg_tso_status_cmd *req;
1169 struct hns3_cmd_desc desc;
1172 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1174 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1177 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1179 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1182 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1184 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1186 return hns3_cmd_send(hw, &desc, 1);
1190 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1191 uint16_t *allocated_size, bool is_alloc)
1193 struct hns3_umv_spc_alc_cmd *req;
1194 struct hns3_cmd_desc desc;
1197 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1198 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1199 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1200 req->space_size = rte_cpu_to_le_32(space_size);
1202 ret = hns3_cmd_send(hw, &desc, 1);
1204 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1205 is_alloc ? "allocate" : "free", ret);
1209 if (is_alloc && allocated_size)
1210 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1216 hns3_init_umv_space(struct hns3_hw *hw)
1218 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1219 struct hns3_pf *pf = &hns->pf;
1220 uint16_t allocated_size = 0;
1223 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1228 if (allocated_size < pf->wanted_umv_size)
1229 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1230 pf->wanted_umv_size, allocated_size);
1232 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1233 pf->wanted_umv_size;
1234 pf->used_umv_size = 0;
1239 hns3_uninit_umv_space(struct hns3_hw *hw)
1241 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1242 struct hns3_pf *pf = &hns->pf;
1245 if (pf->max_umv_size == 0)
1248 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1252 pf->max_umv_size = 0;
1258 hns3_is_umv_space_full(struct hns3_hw *hw)
1260 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1261 struct hns3_pf *pf = &hns->pf;
1264 is_full = (pf->used_umv_size >= pf->max_umv_size);
1270 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1272 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1273 struct hns3_pf *pf = &hns->pf;
1276 if (pf->used_umv_size > 0)
1277 pf->used_umv_size--;
1279 pf->used_umv_size++;
1283 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1284 const uint8_t *addr, bool is_mc)
1286 const unsigned char *mac_addr = addr;
1287 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1288 ((uint32_t)mac_addr[2] << 16) |
1289 ((uint32_t)mac_addr[1] << 8) |
1290 (uint32_t)mac_addr[0];
1291 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1293 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1295 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1296 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1297 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1300 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1301 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1305 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1307 enum hns3_mac_vlan_tbl_opcode op)
1310 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1315 if (op == HNS3_MAC_VLAN_ADD) {
1316 if (resp_code == 0 || resp_code == 1) {
1318 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1319 hns3_err(hw, "add mac addr failed for uc_overflow");
1321 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1322 hns3_err(hw, "add mac addr failed for mc_overflow");
1326 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1329 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1330 if (resp_code == 0) {
1332 } else if (resp_code == 1) {
1333 hns3_dbg(hw, "remove mac addr failed for miss");
1337 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1340 } else if (op == HNS3_MAC_VLAN_LKUP) {
1341 if (resp_code == 0) {
1343 } else if (resp_code == 1) {
1344 hns3_dbg(hw, "lookup mac addr failed for miss");
1348 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1353 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1360 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1361 struct hns3_mac_vlan_tbl_entry_cmd *req,
1362 struct hns3_cmd_desc *desc, bool is_mc)
1368 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1370 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1371 memcpy(desc[0].data, req,
1372 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1373 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1375 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1376 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1378 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1380 memcpy(desc[0].data, req,
1381 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1382 ret = hns3_cmd_send(hw, desc, 1);
1385 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1389 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1390 retval = rte_le_to_cpu_16(desc[0].retval);
1392 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1393 HNS3_MAC_VLAN_LKUP);
1397 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1398 struct hns3_mac_vlan_tbl_entry_cmd *req,
1399 struct hns3_cmd_desc *mc_desc)
1406 if (mc_desc == NULL) {
1407 struct hns3_cmd_desc desc;
1409 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1410 memcpy(desc.data, req,
1411 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1412 ret = hns3_cmd_send(hw, &desc, 1);
1413 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1414 retval = rte_le_to_cpu_16(desc.retval);
1416 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1419 hns3_cmd_reuse_desc(&mc_desc[0], false);
1420 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1421 hns3_cmd_reuse_desc(&mc_desc[1], false);
1422 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1423 hns3_cmd_reuse_desc(&mc_desc[2], false);
1424 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1425 memcpy(mc_desc[0].data, req,
1426 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1427 mc_desc[0].retval = 0;
1428 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1429 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1430 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1432 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1437 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1445 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1446 struct hns3_mac_vlan_tbl_entry_cmd *req)
1448 struct hns3_cmd_desc desc;
1453 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1455 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1457 ret = hns3_cmd_send(hw, &desc, 1);
1459 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1462 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1463 retval = rte_le_to_cpu_16(desc.retval);
1465 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1466 HNS3_MAC_VLAN_REMOVE);
1470 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1472 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1473 struct hns3_mac_vlan_tbl_entry_cmd req;
1474 struct hns3_pf *pf = &hns->pf;
1475 struct hns3_cmd_desc desc[3];
1476 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1477 uint16_t egress_port = 0;
1481 /* check if mac addr is valid */
1482 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1483 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1485 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1490 memset(&req, 0, sizeof(req));
1493 * In current version VF is not supported when PF is driven by DPDK
1494 * driver, just need to configure parameters for PF vport.
1496 vf_id = HNS3_PF_FUNC_ID;
1497 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1498 HNS3_MAC_EPORT_VFID_S, vf_id);
1500 req.egress_port = rte_cpu_to_le_16(egress_port);
1502 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1505 * Lookup the mac address in the mac_vlan table, and add
1506 * it if the entry is inexistent. Repeated unicast entry
1507 * is not allowed in the mac vlan table.
1509 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1510 if (ret == -ENOENT) {
1511 if (!hns3_is_umv_space_full(hw)) {
1512 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1514 hns3_update_umv_space(hw, false);
1518 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1523 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1525 /* check if we just hit the duplicate */
1527 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1531 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1538 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1540 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1541 struct rte_ether_addr *addr;
1545 for (i = 0; i < hw->mc_addrs_num; i++) {
1546 addr = &hw->mc_addrs[i];
1547 /* Check if there are duplicate addresses */
1548 if (rte_is_same_ether_addr(addr, mac_addr)) {
1549 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1551 hns3_err(hw, "failed to add mc mac addr, same addrs"
1552 "(%s) is added by the set_mc_mac_addr_list "
1558 ret = hns3_add_mc_addr(hw, mac_addr);
1560 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1562 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1569 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1571 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1574 ret = hns3_remove_mc_addr(hw, mac_addr);
1576 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1578 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1585 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1586 uint32_t idx, __rte_unused uint32_t pool)
1588 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1589 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1592 rte_spinlock_lock(&hw->lock);
1595 * In hns3 network engine adding UC and MC mac address with different
1596 * commands with firmware. We need to determine whether the input
1597 * address is a UC or a MC address to call different commands.
1598 * By the way, it is recommended calling the API function named
1599 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1600 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1601 * may affect the specifications of UC mac addresses.
1603 if (rte_is_multicast_ether_addr(mac_addr))
1604 ret = hns3_add_mc_addr_common(hw, mac_addr);
1606 ret = hns3_add_uc_addr_common(hw, mac_addr);
1609 rte_spinlock_unlock(&hw->lock);
1610 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1612 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1618 hw->mac.default_addr_setted = true;
1619 rte_spinlock_unlock(&hw->lock);
1625 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1627 struct hns3_mac_vlan_tbl_entry_cmd req;
1628 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1631 /* check if mac addr is valid */
1632 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1633 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1635 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1640 memset(&req, 0, sizeof(req));
1641 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1642 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1643 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1644 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1647 hns3_update_umv_space(hw, true);
1653 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1655 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1656 /* index will be checked by upper level rte interface */
1657 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1658 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1661 rte_spinlock_lock(&hw->lock);
1663 if (rte_is_multicast_ether_addr(mac_addr))
1664 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1666 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1667 rte_spinlock_unlock(&hw->lock);
1669 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1671 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1677 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1678 struct rte_ether_addr *mac_addr)
1680 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1681 struct rte_ether_addr *oaddr;
1682 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1683 bool default_addr_setted;
1684 bool rm_succes = false;
1688 * It has been guaranteed that input parameter named mac_addr is valid
1689 * address in the rte layer of DPDK framework.
1691 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1692 default_addr_setted = hw->mac.default_addr_setted;
1693 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1696 rte_spinlock_lock(&hw->lock);
1697 if (default_addr_setted) {
1698 ret = hns3_remove_uc_addr_common(hw, oaddr);
1700 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1702 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1709 ret = hns3_add_uc_addr_common(hw, mac_addr);
1711 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1713 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1714 goto err_add_uc_addr;
1717 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1719 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1720 goto err_pause_addr_cfg;
1723 rte_ether_addr_copy(mac_addr,
1724 (struct rte_ether_addr *)hw->mac.mac_addr);
1725 hw->mac.default_addr_setted = true;
1726 rte_spinlock_unlock(&hw->lock);
1731 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1733 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1736 "Failed to roll back to del setted mac addr(%s): %d",
1742 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1744 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1747 "Failed to restore old uc mac addr(%s): %d",
1749 hw->mac.default_addr_setted = false;
1752 rte_spinlock_unlock(&hw->lock);
1758 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1760 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1761 struct hns3_hw *hw = &hns->hw;
1762 struct rte_ether_addr *addr;
1767 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1768 addr = &hw->data->mac_addrs[i];
1769 if (rte_is_zero_ether_addr(addr))
1771 if (rte_is_multicast_ether_addr(addr))
1772 ret = del ? hns3_remove_mc_addr(hw, addr) :
1773 hns3_add_mc_addr(hw, addr);
1775 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1776 hns3_add_uc_addr_common(hw, addr);
1780 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1782 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1783 "ret = %d.", del ? "remove" : "restore",
1791 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1793 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1797 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1798 word_num = vfid / 32;
1799 bit_num = vfid % 32;
1801 desc[1].data[word_num] &=
1802 rte_cpu_to_le_32(~(1UL << bit_num));
1804 desc[1].data[word_num] |=
1805 rte_cpu_to_le_32(1UL << bit_num);
1807 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1808 bit_num = vfid % 32;
1810 desc[2].data[word_num] &=
1811 rte_cpu_to_le_32(~(1UL << bit_num));
1813 desc[2].data[word_num] |=
1814 rte_cpu_to_le_32(1UL << bit_num);
1819 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1821 struct hns3_mac_vlan_tbl_entry_cmd req;
1822 struct hns3_cmd_desc desc[3];
1823 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1827 /* Check if mac addr is valid */
1828 if (!rte_is_multicast_ether_addr(mac_addr)) {
1829 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1831 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1836 memset(&req, 0, sizeof(req));
1837 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1838 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1839 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1841 /* This mac addr do not exist, add new entry for it */
1842 memset(desc[0].data, 0, sizeof(desc[0].data));
1843 memset(desc[1].data, 0, sizeof(desc[0].data));
1844 memset(desc[2].data, 0, sizeof(desc[0].data));
1848 * In current version VF is not supported when PF is driven by DPDK
1849 * driver, just need to configure parameters for PF vport.
1851 vf_id = HNS3_PF_FUNC_ID;
1852 hns3_update_desc_vfid(desc, vf_id, false);
1853 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1856 hns3_err(hw, "mc mac vlan table is full");
1857 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1859 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1866 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1868 struct hns3_mac_vlan_tbl_entry_cmd req;
1869 struct hns3_cmd_desc desc[3];
1870 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1874 /* Check if mac addr is valid */
1875 if (!rte_is_multicast_ether_addr(mac_addr)) {
1876 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1878 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1883 memset(&req, 0, sizeof(req));
1884 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1885 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1886 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1889 * This mac addr exist, remove this handle's VFID for it.
1890 * In current version VF is not supported when PF is driven by
1891 * DPDK driver, just need to configure parameters for PF vport.
1893 vf_id = HNS3_PF_FUNC_ID;
1894 hns3_update_desc_vfid(desc, vf_id, true);
1896 /* All the vfid is zero, so need to delete this entry */
1897 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1898 } else if (ret == -ENOENT) {
1899 /* This mac addr doesn't exist. */
1904 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1906 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1913 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1914 struct rte_ether_addr *mc_addr_set,
1915 uint32_t nb_mc_addr)
1917 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1918 struct rte_ether_addr *addr;
1922 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1923 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1924 "invalid. valid range: 0~%d",
1925 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1929 /* Check if input mac addresses are valid */
1930 for (i = 0; i < nb_mc_addr; i++) {
1931 addr = &mc_addr_set[i];
1932 if (!rte_is_multicast_ether_addr(addr)) {
1933 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1936 "failed to set mc mac addr, addr(%s) invalid.",
1941 /* Check if there are duplicate addresses */
1942 for (j = i + 1; j < nb_mc_addr; j++) {
1943 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1944 hns3_ether_format_addr(mac_str,
1945 RTE_ETHER_ADDR_FMT_SIZE,
1947 hns3_err(hw, "failed to set mc mac addr, "
1948 "addrs invalid. two same addrs(%s).",
1955 * Check if there are duplicate addresses between mac_addrs
1958 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1959 if (rte_is_same_ether_addr(addr,
1960 &hw->data->mac_addrs[j])) {
1961 hns3_ether_format_addr(mac_str,
1962 RTE_ETHER_ADDR_FMT_SIZE,
1964 hns3_err(hw, "failed to set mc mac addr, "
1965 "addrs invalid. addrs(%s) has already "
1966 "configured in mac_addr add API",
1977 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1978 struct rte_ether_addr *mc_addr_set,
1980 struct rte_ether_addr *reserved_addr_list,
1981 int *reserved_addr_num,
1982 struct rte_ether_addr *add_addr_list,
1984 struct rte_ether_addr *rm_addr_list,
1987 struct rte_ether_addr *addr;
1988 int current_addr_num;
1989 int reserved_num = 0;
1997 /* Calculate the mc mac address list that should be removed */
1998 current_addr_num = hw->mc_addrs_num;
1999 for (i = 0; i < current_addr_num; i++) {
2000 addr = &hw->mc_addrs[i];
2002 for (j = 0; j < mc_addr_num; j++) {
2003 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2010 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2013 rte_ether_addr_copy(addr,
2014 &reserved_addr_list[reserved_num]);
2019 /* Calculate the mc mac address list that should be added */
2020 for (i = 0; i < mc_addr_num; i++) {
2021 addr = &mc_addr_set[i];
2023 for (j = 0; j < current_addr_num; j++) {
2024 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2031 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2036 /* Reorder the mc mac address list maintained by driver */
2037 for (i = 0; i < reserved_num; i++)
2038 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2040 for (i = 0; i < rm_num; i++) {
2041 num = reserved_num + i;
2042 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2045 *reserved_addr_num = reserved_num;
2046 *add_addr_num = add_num;
2047 *rm_addr_num = rm_num;
2051 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2052 struct rte_ether_addr *mc_addr_set,
2053 uint32_t nb_mc_addr)
2055 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2056 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2057 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2058 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2059 struct rte_ether_addr *addr;
2060 int reserved_addr_num;
2068 /* Check if input parameters are valid */
2069 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2073 rte_spinlock_lock(&hw->lock);
2076 * Calculate the mc mac address lists those should be removed and be
2077 * added, Reorder the mc mac address list maintained by driver.
2079 mc_addr_num = (int)nb_mc_addr;
2080 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2081 reserved_addr_list, &reserved_addr_num,
2082 add_addr_list, &add_addr_num,
2083 rm_addr_list, &rm_addr_num);
2085 /* Remove mc mac addresses */
2086 for (i = 0; i < rm_addr_num; i++) {
2087 num = rm_addr_num - i - 1;
2088 addr = &rm_addr_list[num];
2089 ret = hns3_remove_mc_addr(hw, addr);
2091 rte_spinlock_unlock(&hw->lock);
2097 /* Add mc mac addresses */
2098 for (i = 0; i < add_addr_num; i++) {
2099 addr = &add_addr_list[i];
2100 ret = hns3_add_mc_addr(hw, addr);
2102 rte_spinlock_unlock(&hw->lock);
2106 num = reserved_addr_num + i;
2107 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2110 rte_spinlock_unlock(&hw->lock);
2116 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2118 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2119 struct hns3_hw *hw = &hns->hw;
2120 struct rte_ether_addr *addr;
2125 for (i = 0; i < hw->mc_addrs_num; i++) {
2126 addr = &hw->mc_addrs[i];
2127 if (!rte_is_multicast_ether_addr(addr))
2130 ret = hns3_remove_mc_addr(hw, addr);
2132 ret = hns3_add_mc_addr(hw, addr);
2135 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2137 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2138 del ? "Remove" : "Restore", mac_str, ret);
2145 hns3_check_mq_mode(struct rte_eth_dev *dev)
2147 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2148 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2149 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2151 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2152 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2157 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2158 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2160 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2161 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2162 "rx_mq_mode = %d", rx_mq_mode);
2166 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2167 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2168 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2169 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2170 rx_mq_mode, tx_mq_mode);
2174 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2175 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2176 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2177 dcb_rx_conf->nb_tcs, pf->tc_max);
2181 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2182 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2183 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2184 "nb_tcs(%d) != %d or %d in rx direction.",
2185 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2189 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2190 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2191 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2195 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2196 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2197 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2198 "is not equal to one in tx direction.",
2199 i, dcb_rx_conf->dcb_tc[i]);
2202 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2203 max_tc = dcb_rx_conf->dcb_tc[i];
2206 num_tc = max_tc + 1;
2207 if (num_tc > dcb_rx_conf->nb_tcs) {
2208 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2209 num_tc, dcb_rx_conf->nb_tcs);
2218 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2220 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2222 if (!hns3_dev_dcb_supported(hw)) {
2223 hns3_err(hw, "this port does not support dcb configurations.");
2227 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2228 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2232 /* Check multiple queue mode */
2233 return hns3_check_mq_mode(dev);
2237 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2238 enum hns3_ring_type queue_type, uint16_t queue_id)
2240 struct hns3_cmd_desc desc;
2241 struct hns3_ctrl_vector_chain_cmd *req =
2242 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2243 enum hns3_cmd_status status;
2244 enum hns3_opcode_type op;
2245 uint16_t tqp_type_and_id = 0;
2249 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2250 hns3_cmd_setup_basic_desc(&desc, op, false);
2251 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2252 HNS3_TQP_INT_ID_L_S);
2253 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2254 HNS3_TQP_INT_ID_H_S);
2256 if (queue_type == HNS3_RING_TYPE_RX)
2257 gl = HNS3_RING_GL_RX;
2259 gl = HNS3_RING_GL_TX;
2263 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2265 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2266 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2268 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2269 req->int_cause_num = 1;
2270 status = hns3_cmd_send(hw, &desc, 1);
2272 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2273 en ? "Map" : "Unmap", queue_id, vector_id, status);
2281 hns3_init_ring_with_vector(struct hns3_hw *hw)
2288 * In hns3 network engine, vector 0 is always the misc interrupt of this
2289 * function, vector 1~N can be used respectively for the queues of the
2290 * function. Tx and Rx queues with the same number share the interrupt
2291 * vector. In the initialization clearing the all hardware mapping
2292 * relationship configurations between queues and interrupt vectors is
2293 * needed, so some error caused by the residual configurations, such as
2294 * the unexpected Tx interrupt, can be avoid.
2296 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2297 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2298 vec = vec - 1; /* the last interrupt is reserved */
2299 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2300 for (i = 0; i < hw->intr_tqps_num; i++) {
2302 * Set gap limiter/rate limiter/quanity limiter algorithm
2303 * configuration for interrupt coalesce of queue's interrupt.
2305 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2306 HNS3_TQP_INTR_GL_DEFAULT);
2307 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2308 HNS3_TQP_INTR_GL_DEFAULT);
2309 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2311 * QL(quantity limiter) is not used currently, just set 0 to
2314 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2316 ret = hns3_bind_ring_with_vector(hw, vec, false,
2317 HNS3_RING_TYPE_TX, i);
2319 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2320 "vector: %u, ret=%d", i, vec, ret);
2324 ret = hns3_bind_ring_with_vector(hw, vec, false,
2325 HNS3_RING_TYPE_RX, i);
2327 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2328 "vector: %u, ret=%d", i, vec, ret);
2337 hns3_dev_configure(struct rte_eth_dev *dev)
2339 struct hns3_adapter *hns = dev->data->dev_private;
2340 struct rte_eth_conf *conf = &dev->data->dev_conf;
2341 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2342 struct hns3_hw *hw = &hns->hw;
2343 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2344 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2345 struct rte_eth_rss_conf rss_conf;
2346 uint32_t max_rx_pkt_len;
2351 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2354 * Some versions of hardware network engine does not support
2355 * individually enable/disable/reset the Tx or Rx queue. These devices
2356 * must enable/disable/reset Tx and Rx queues at the same time. When the
2357 * numbers of Tx queues allocated by upper applications are not equal to
2358 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2359 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2360 * work as usual. But these fake queues are imperceptible, and can not
2361 * be used by upper applications.
2363 if (!hns3_dev_indep_txrx_supported(hw)) {
2364 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2366 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2372 hw->adapter_state = HNS3_NIC_CONFIGURING;
2373 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2374 hns3_err(hw, "setting link speed/duplex not supported");
2379 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2380 ret = hns3_check_dcb_cfg(dev);
2385 /* When RSS is not configured, redirect the packet queue 0 */
2386 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2387 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2388 rss_conf = conf->rx_adv_conf.rss_conf;
2389 hw->rss_dis_flag = false;
2390 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2396 * If jumbo frames are enabled, MTU needs to be refreshed
2397 * according to the maximum RX packet length.
2399 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2400 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2401 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2402 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2403 hns3_err(hw, "maximum Rx packet length must be greater "
2404 "than %u and less than %u when jumbo frame enabled.",
2405 (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2406 (uint16_t)HNS3_MAX_FRAME_LEN);
2411 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2412 ret = hns3_dev_mtu_set(dev, mtu);
2415 dev->data->mtu = mtu;
2418 ret = hns3_dev_configure_vlan(dev);
2422 /* config hardware GRO */
2423 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2424 ret = hns3_config_gro(hw, gro_en);
2428 hns->rx_simple_allowed = true;
2429 hns->rx_vec_allowed = true;
2430 hns->tx_simple_allowed = true;
2431 hns->tx_vec_allowed = true;
2433 hns3_init_rx_ptype_tble(dev);
2434 hw->adapter_state = HNS3_NIC_CONFIGURED;
2439 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2440 hw->adapter_state = HNS3_NIC_INITIALIZED;
2446 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2448 struct hns3_config_max_frm_size_cmd *req;
2449 struct hns3_cmd_desc desc;
2451 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2453 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2454 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2455 req->min_frm_size = RTE_ETHER_MIN_LEN;
2457 return hns3_cmd_send(hw, &desc, 1);
2461 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2465 ret = hns3_set_mac_mtu(hw, mps);
2467 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2471 ret = hns3_buffer_alloc(hw);
2473 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2479 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2481 struct hns3_adapter *hns = dev->data->dev_private;
2482 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2483 struct hns3_hw *hw = &hns->hw;
2484 bool is_jumbo_frame;
2487 if (dev->data->dev_started) {
2488 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2489 "before configuration", dev->data->port_id);
2493 rte_spinlock_lock(&hw->lock);
2494 is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2495 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2498 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2499 * assign to "uint16_t" type variable.
2501 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2503 rte_spinlock_unlock(&hw->lock);
2504 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2505 dev->data->port_id, mtu, ret);
2508 hns->pf.mps = (uint16_t)frame_size;
2510 dev->data->dev_conf.rxmode.offloads |=
2511 DEV_RX_OFFLOAD_JUMBO_FRAME;
2513 dev->data->dev_conf.rxmode.offloads &=
2514 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2515 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2516 rte_spinlock_unlock(&hw->lock);
2522 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2524 struct hns3_adapter *hns = eth_dev->data->dev_private;
2525 struct hns3_hw *hw = &hns->hw;
2526 uint16_t queue_num = hw->tqps_num;
2529 * In interrupt mode, 'max_rx_queues' is set based on the number of
2530 * MSI-X interrupt resources of the hardware.
2532 if (hw->data->dev_conf.intr_conf.rxq == 1)
2533 queue_num = hw->intr_tqps_num;
2535 info->max_rx_queues = queue_num;
2536 info->max_tx_queues = hw->tqps_num;
2537 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2538 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2539 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2540 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2541 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2542 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2543 DEV_RX_OFFLOAD_TCP_CKSUM |
2544 DEV_RX_OFFLOAD_UDP_CKSUM |
2545 DEV_RX_OFFLOAD_SCTP_CKSUM |
2546 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2547 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2548 DEV_RX_OFFLOAD_KEEP_CRC |
2549 DEV_RX_OFFLOAD_SCATTER |
2550 DEV_RX_OFFLOAD_VLAN_STRIP |
2551 DEV_RX_OFFLOAD_VLAN_FILTER |
2552 DEV_RX_OFFLOAD_JUMBO_FRAME |
2553 DEV_RX_OFFLOAD_RSS_HASH |
2554 DEV_RX_OFFLOAD_TCP_LRO);
2555 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2556 DEV_TX_OFFLOAD_IPV4_CKSUM |
2557 DEV_TX_OFFLOAD_TCP_CKSUM |
2558 DEV_TX_OFFLOAD_UDP_CKSUM |
2559 DEV_TX_OFFLOAD_SCTP_CKSUM |
2560 DEV_TX_OFFLOAD_MULTI_SEGS |
2561 DEV_TX_OFFLOAD_TCP_TSO |
2562 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2563 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2564 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2565 DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2566 hns3_txvlan_cap_get(hw));
2568 if (hns3_dev_indep_txrx_supported(hw))
2569 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2570 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2572 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2573 .nb_max = HNS3_MAX_RING_DESC,
2574 .nb_min = HNS3_MIN_RING_DESC,
2575 .nb_align = HNS3_ALIGN_RING_DESC,
2578 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2579 .nb_max = HNS3_MAX_RING_DESC,
2580 .nb_min = HNS3_MIN_RING_DESC,
2581 .nb_align = HNS3_ALIGN_RING_DESC,
2582 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2583 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2586 info->default_rxconf = (struct rte_eth_rxconf) {
2587 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2589 * If there are no available Rx buffer descriptors, incoming
2590 * packets are always dropped by hardware based on hns3 network
2596 info->default_txconf = (struct rte_eth_txconf) {
2597 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2601 info->vmdq_queue_num = 0;
2603 info->reta_size = hw->rss_ind_tbl_size;
2604 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2605 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2607 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2608 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2609 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2610 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2611 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2612 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2618 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2621 struct hns3_adapter *hns = eth_dev->data->dev_private;
2622 struct hns3_hw *hw = &hns->hw;
2623 uint32_t version = hw->fw_version;
2626 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2627 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2628 HNS3_FW_VERSION_BYTE3_S),
2629 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2630 HNS3_FW_VERSION_BYTE2_S),
2631 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2632 HNS3_FW_VERSION_BYTE1_S),
2633 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2634 HNS3_FW_VERSION_BYTE0_S));
2635 ret += 1; /* add the size of '\0' */
2636 if (fw_size < (uint32_t)ret)
2643 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2644 __rte_unused int wait_to_complete)
2646 struct hns3_adapter *hns = eth_dev->data->dev_private;
2647 struct hns3_hw *hw = &hns->hw;
2648 struct hns3_mac *mac = &hw->mac;
2649 struct rte_eth_link new_link;
2651 if (!hns3_is_reset_pending(hns)) {
2652 hns3_update_link_status(hw);
2653 hns3_update_link_info(eth_dev);
2656 memset(&new_link, 0, sizeof(new_link));
2657 switch (mac->link_speed) {
2658 case ETH_SPEED_NUM_10M:
2659 case ETH_SPEED_NUM_100M:
2660 case ETH_SPEED_NUM_1G:
2661 case ETH_SPEED_NUM_10G:
2662 case ETH_SPEED_NUM_25G:
2663 case ETH_SPEED_NUM_40G:
2664 case ETH_SPEED_NUM_50G:
2665 case ETH_SPEED_NUM_100G:
2666 case ETH_SPEED_NUM_200G:
2667 new_link.link_speed = mac->link_speed;
2670 new_link.link_speed = ETH_SPEED_NUM_100M;
2674 new_link.link_duplex = mac->link_duplex;
2675 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2676 new_link.link_autoneg =
2677 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2679 return rte_eth_linkstatus_set(eth_dev, &new_link);
2683 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2685 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2686 struct hns3_pf *pf = &hns->pf;
2688 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2691 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2697 hns3_query_function_status(struct hns3_hw *hw)
2699 #define HNS3_QUERY_MAX_CNT 10
2700 #define HNS3_QUERY_SLEEP_MSCOEND 1
2701 struct hns3_func_status_cmd *req;
2702 struct hns3_cmd_desc desc;
2706 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2707 req = (struct hns3_func_status_cmd *)desc.data;
2710 ret = hns3_cmd_send(hw, &desc, 1);
2712 PMD_INIT_LOG(ERR, "query function status failed %d",
2717 /* Check pf reset is done */
2721 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2722 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2724 return hns3_parse_func_status(hw, req);
2728 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2730 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2731 struct hns3_pf *pf = &hns->pf;
2733 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2735 * The total_tqps_num obtained from firmware is maximum tqp
2736 * numbers of this port, which should be used for PF and VFs.
2737 * There is no need for pf to have so many tqp numbers in
2738 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2739 * coming from config file, is assigned to maximum queue number
2740 * for the PF of this port by user. So users can modify the
2741 * maximum queue number of PF according to their own application
2742 * scenarios, which is more flexible to use. In addition, many
2743 * memories can be saved due to allocating queue statistics
2744 * room according to the actual number of queues required. The
2745 * maximum queue number of PF for network engine with
2746 * revision_id greater than 0x30 is assigned by config file.
2748 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2749 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2750 "must be greater than 0.",
2751 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2755 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2756 hw->total_tqps_num);
2759 * Due to the limitation on the number of PF interrupts
2760 * available, the maximum queue number assigned to PF on
2761 * the network engine with revision_id 0x21 is 64.
2763 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2764 HNS3_MAX_TQP_NUM_HIP08_PF);
2771 hns3_query_pf_resource(struct hns3_hw *hw)
2773 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2774 struct hns3_pf *pf = &hns->pf;
2775 struct hns3_pf_res_cmd *req;
2776 struct hns3_cmd_desc desc;
2779 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2780 ret = hns3_cmd_send(hw, &desc, 1);
2782 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2786 req = (struct hns3_pf_res_cmd *)desc.data;
2787 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2788 rte_le_to_cpu_16(req->ext_tqp_num);
2789 ret = hns3_get_pf_max_tqp_num(hw);
2793 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2794 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2796 if (req->tx_buf_size)
2798 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2800 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2802 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2804 if (req->dv_buf_size)
2806 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2808 pf->dv_buf_size = HNS3_DEFAULT_DV;
2810 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2813 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2814 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2820 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2822 struct hns3_cfg_param_cmd *req;
2823 uint64_t mac_addr_tmp_high;
2824 uint8_t ext_rss_size_max;
2825 uint64_t mac_addr_tmp;
2828 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2830 /* get the configuration */
2831 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2832 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2833 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2834 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2835 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2836 HNS3_CFG_TQP_DESC_N_M,
2837 HNS3_CFG_TQP_DESC_N_S);
2839 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2840 HNS3_CFG_PHY_ADDR_M,
2841 HNS3_CFG_PHY_ADDR_S);
2842 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2843 HNS3_CFG_MEDIA_TP_M,
2844 HNS3_CFG_MEDIA_TP_S);
2845 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2846 HNS3_CFG_RX_BUF_LEN_M,
2847 HNS3_CFG_RX_BUF_LEN_S);
2848 /* get mac address */
2849 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2850 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2851 HNS3_CFG_MAC_ADDR_H_M,
2852 HNS3_CFG_MAC_ADDR_H_S);
2854 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2856 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2857 HNS3_CFG_DEFAULT_SPEED_M,
2858 HNS3_CFG_DEFAULT_SPEED_S);
2859 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2860 HNS3_CFG_RSS_SIZE_M,
2861 HNS3_CFG_RSS_SIZE_S);
2863 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2864 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2866 req = (struct hns3_cfg_param_cmd *)desc[1].data;
2867 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2869 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2870 HNS3_CFG_SPEED_ABILITY_M,
2871 HNS3_CFG_SPEED_ABILITY_S);
2872 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2873 HNS3_CFG_UMV_TBL_SPACE_M,
2874 HNS3_CFG_UMV_TBL_SPACE_S);
2875 if (!cfg->umv_space)
2876 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2878 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2879 HNS3_CFG_EXT_RSS_SIZE_M,
2880 HNS3_CFG_EXT_RSS_SIZE_S);
2883 * Field ext_rss_size_max obtained from firmware will be more flexible
2884 * for future changes and expansions, which is an exponent of 2, instead
2885 * of reading out directly. If this field is not zero, hns3 PF PMD
2886 * driver uses it as rss_size_max under one TC. Device, whose revision
2887 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2888 * maximum number of queues supported under a TC through this field.
2890 if (ext_rss_size_max)
2891 cfg->rss_size_max = 1U << ext_rss_size_max;
2894 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2895 * @hw: pointer to struct hns3_hw
2896 * @hcfg: the config structure to be getted
2899 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2901 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2902 struct hns3_cfg_param_cmd *req;
2907 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2909 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2910 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2912 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2913 i * HNS3_CFG_RD_LEN_BYTES);
2914 /* Len should be divided by 4 when send to hardware */
2915 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2916 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2917 req->offset = rte_cpu_to_le_32(offset);
2920 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2922 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2926 hns3_parse_cfg(hcfg, desc);
2932 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2934 switch (speed_cmd) {
2935 case HNS3_CFG_SPEED_10M:
2936 *speed = ETH_SPEED_NUM_10M;
2938 case HNS3_CFG_SPEED_100M:
2939 *speed = ETH_SPEED_NUM_100M;
2941 case HNS3_CFG_SPEED_1G:
2942 *speed = ETH_SPEED_NUM_1G;
2944 case HNS3_CFG_SPEED_10G:
2945 *speed = ETH_SPEED_NUM_10G;
2947 case HNS3_CFG_SPEED_25G:
2948 *speed = ETH_SPEED_NUM_25G;
2950 case HNS3_CFG_SPEED_40G:
2951 *speed = ETH_SPEED_NUM_40G;
2953 case HNS3_CFG_SPEED_50G:
2954 *speed = ETH_SPEED_NUM_50G;
2956 case HNS3_CFG_SPEED_100G:
2957 *speed = ETH_SPEED_NUM_100G;
2959 case HNS3_CFG_SPEED_200G:
2960 *speed = ETH_SPEED_NUM_200G;
2970 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2972 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2973 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2974 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2975 hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2976 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2980 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2982 struct hns3_dev_specs_0_cmd *req0;
2984 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2986 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2987 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2988 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2989 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2990 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
2994 hns3_check_dev_specifications(struct hns3_hw *hw)
2996 if (hw->rss_ind_tbl_size == 0 ||
2997 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
2998 hns3_err(hw, "the size of hash lookup table configured (%u)"
2999 " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3000 HNS3_RSS_IND_TBL_SIZE_MAX);
3008 hns3_query_dev_specifications(struct hns3_hw *hw)
3010 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3014 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3015 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3017 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3019 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3021 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3025 hns3_parse_dev_specifications(hw, desc);
3027 return hns3_check_dev_specifications(hw);
3031 hns3_get_capability(struct hns3_hw *hw)
3033 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3034 struct rte_pci_device *pci_dev;
3035 struct hns3_pf *pf = &hns->pf;
3036 struct rte_eth_dev *eth_dev;
3041 eth_dev = &rte_eth_devices[hw->data->port_id];
3042 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3043 device_id = pci_dev->id.device_id;
3045 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3046 device_id == HNS3_DEV_ID_50GE_RDMA ||
3047 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3048 device_id == HNS3_DEV_ID_200G_RDMA)
3049 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3051 /* Get PCI revision id */
3052 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3053 HNS3_PCI_REVISION_ID);
3054 if (ret != HNS3_PCI_REVISION_ID_LEN) {
3055 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3059 hw->revision = revision;
3061 if (revision < PCI_REVISION_ID_HIP09_A) {
3062 hns3_set_default_dev_specifications(hw);
3063 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3064 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3065 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3066 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3067 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3068 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3069 hw->rss_info.ipv6_sctp_offload_supported = false;
3073 ret = hns3_query_dev_specifications(hw);
3076 "failed to query dev specifications, ret = %d",
3081 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3082 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3083 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3084 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3085 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3086 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3087 hw->rss_info.ipv6_sctp_offload_supported = true;
3093 hns3_get_board_configuration(struct hns3_hw *hw)
3095 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3096 struct hns3_pf *pf = &hns->pf;
3097 struct hns3_cfg cfg;
3100 ret = hns3_get_board_cfg(hw, &cfg);
3102 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3106 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
3107 !hns3_dev_copper_supported(hw)) {
3108 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
3112 hw->mac.media_type = cfg.media_type;
3113 hw->rss_size_max = cfg.rss_size_max;
3114 hw->rss_dis_flag = false;
3115 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3116 hw->mac.phy_addr = cfg.phy_addr;
3117 hw->mac.default_addr_setted = false;
3118 hw->num_tx_desc = cfg.tqp_desc_num;
3119 hw->num_rx_desc = cfg.tqp_desc_num;
3120 hw->dcb_info.num_pg = 1;
3121 hw->dcb_info.hw_pfc_map = 0;
3123 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3125 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3126 cfg.default_speed, ret);
3130 pf->tc_max = cfg.tc_num;
3131 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3132 PMD_INIT_LOG(WARNING,
3133 "Get TC num(%u) from flash, set TC num to 1",
3138 /* Dev does not support DCB */
3139 if (!hns3_dev_dcb_supported(hw)) {
3143 pf->pfc_max = pf->tc_max;
3145 hw->dcb_info.num_tc = 1;
3146 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3147 hw->tqps_num / hw->dcb_info.num_tc);
3148 hns3_set_bit(hw->hw_tc_map, 0, 1);
3149 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3151 pf->wanted_umv_size = cfg.umv_space;
3157 hns3_get_configuration(struct hns3_hw *hw)
3161 ret = hns3_query_function_status(hw);
3163 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3167 /* Get device capability */
3168 ret = hns3_get_capability(hw);
3170 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3174 /* Get pf resource */
3175 ret = hns3_query_pf_resource(hw);
3177 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3181 ret = hns3_get_board_configuration(hw);
3183 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3187 ret = hns3_query_dev_fec_info(hw);
3190 "failed to query FEC information, ret = %d", ret);
3196 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3197 uint16_t tqp_vid, bool is_pf)
3199 struct hns3_tqp_map_cmd *req;
3200 struct hns3_cmd_desc desc;
3203 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3205 req = (struct hns3_tqp_map_cmd *)desc.data;
3206 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3207 req->tqp_vf = func_id;
3208 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3210 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3211 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3213 ret = hns3_cmd_send(hw, &desc, 1);
3215 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3221 hns3_map_tqp(struct hns3_hw *hw)
3227 * In current version, VF is not supported when PF is driven by DPDK
3228 * driver, so we assign total tqps_num tqps allocated to this port
3231 for (i = 0; i < hw->total_tqps_num; i++) {
3232 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3241 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3243 struct hns3_config_mac_speed_dup_cmd *req;
3244 struct hns3_cmd_desc desc;
3247 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3249 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3251 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3254 case ETH_SPEED_NUM_10M:
3255 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3256 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3258 case ETH_SPEED_NUM_100M:
3259 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3260 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3262 case ETH_SPEED_NUM_1G:
3263 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3264 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3266 case ETH_SPEED_NUM_10G:
3267 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3268 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3270 case ETH_SPEED_NUM_25G:
3271 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3272 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3274 case ETH_SPEED_NUM_40G:
3275 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3276 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3278 case ETH_SPEED_NUM_50G:
3279 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3280 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3282 case ETH_SPEED_NUM_100G:
3283 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3284 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3286 case ETH_SPEED_NUM_200G:
3287 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3288 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3291 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3295 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3297 ret = hns3_cmd_send(hw, &desc, 1);
3299 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3305 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3307 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3308 struct hns3_pf *pf = &hns->pf;
3309 struct hns3_priv_buf *priv;
3310 uint32_t i, total_size;
3312 total_size = pf->pkt_buf_size;
3314 /* alloc tx buffer for all enabled tc */
3315 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3316 priv = &buf_alloc->priv_buf[i];
3318 if (hw->hw_tc_map & BIT(i)) {
3319 if (total_size < pf->tx_buf_size)
3322 priv->tx_buf_size = pf->tx_buf_size;
3324 priv->tx_buf_size = 0;
3326 total_size -= priv->tx_buf_size;
3333 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3335 /* TX buffer size is unit by 128 byte */
3336 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3337 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3338 struct hns3_tx_buff_alloc_cmd *req;
3339 struct hns3_cmd_desc desc;
3344 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3346 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3347 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3348 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3350 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3351 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3352 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3355 ret = hns3_cmd_send(hw, &desc, 1);
3357 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3363 hns3_get_tc_num(struct hns3_hw *hw)
3368 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3369 if (hw->hw_tc_map & BIT(i))
3375 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3377 struct hns3_priv_buf *priv;
3378 uint32_t rx_priv = 0;
3381 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3382 priv = &buf_alloc->priv_buf[i];
3384 rx_priv += priv->buf_size;
3390 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3392 uint32_t total_tx_size = 0;
3395 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3396 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3398 return total_tx_size;
3401 /* Get the number of pfc enabled TCs, which have private buffer */
3403 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3405 struct hns3_priv_buf *priv;
3409 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3410 priv = &buf_alloc->priv_buf[i];
3411 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3418 /* Get the number of pfc disabled TCs, which have private buffer */
3420 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3421 struct hns3_pkt_buf_alloc *buf_alloc)
3423 struct hns3_priv_buf *priv;
3427 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3428 priv = &buf_alloc->priv_buf[i];
3429 if (hw->hw_tc_map & BIT(i) &&
3430 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3438 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3441 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3442 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3443 struct hns3_pf *pf = &hns->pf;
3444 uint32_t shared_buf, aligned_mps;
3449 tc_num = hns3_get_tc_num(hw);
3450 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3452 if (hns3_dev_dcb_supported(hw))
3453 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3456 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3459 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3460 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3461 HNS3_BUF_SIZE_UNIT);
3463 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3464 if (rx_all < rx_priv + shared_std)
3467 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3468 buf_alloc->s_buf.buf_size = shared_buf;
3469 if (hns3_dev_dcb_supported(hw)) {
3470 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3471 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3472 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3473 HNS3_BUF_SIZE_UNIT);
3475 buf_alloc->s_buf.self.high =
3476 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3477 buf_alloc->s_buf.self.low = aligned_mps;
3480 if (hns3_dev_dcb_supported(hw)) {
3481 hi_thrd = shared_buf - pf->dv_buf_size;
3483 if (tc_num <= NEED_RESERVE_TC_NUM)
3484 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3488 hi_thrd = hi_thrd / tc_num;
3490 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3491 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3492 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3494 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3495 lo_thrd = aligned_mps;
3498 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3499 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3500 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3507 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3508 struct hns3_pkt_buf_alloc *buf_alloc)
3510 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3511 struct hns3_pf *pf = &hns->pf;
3512 struct hns3_priv_buf *priv;
3513 uint32_t aligned_mps;
3517 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3518 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3520 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3521 priv = &buf_alloc->priv_buf[i];
3528 if (!(hw->hw_tc_map & BIT(i)))
3532 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3533 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3534 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3535 HNS3_BUF_SIZE_UNIT);
3538 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3542 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3545 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3549 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3550 struct hns3_pkt_buf_alloc *buf_alloc)
3552 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3553 struct hns3_pf *pf = &hns->pf;
3554 struct hns3_priv_buf *priv;
3555 int no_pfc_priv_num;
3560 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3561 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3563 /* let the last to be cleared first */
3564 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3565 priv = &buf_alloc->priv_buf[i];
3566 mask = BIT((uint8_t)i);
3568 if (hw->hw_tc_map & mask &&
3569 !(hw->dcb_info.hw_pfc_map & mask)) {
3570 /* Clear the no pfc TC private buffer */
3578 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3579 no_pfc_priv_num == 0)
3583 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3587 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3588 struct hns3_pkt_buf_alloc *buf_alloc)
3590 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3591 struct hns3_pf *pf = &hns->pf;
3592 struct hns3_priv_buf *priv;
3598 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3599 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3601 /* let the last to be cleared first */
3602 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3603 priv = &buf_alloc->priv_buf[i];
3604 mask = BIT((uint8_t)i);
3605 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3606 /* Reduce the number of pfc TC with private buffer */
3613 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3618 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3622 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3623 struct hns3_pkt_buf_alloc *buf_alloc)
3625 #define COMPENSATE_BUFFER 0x3C00
3626 #define COMPENSATE_HALF_MPS_NUM 5
3627 #define PRIV_WL_GAP 0x1800
3628 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3629 struct hns3_pf *pf = &hns->pf;
3630 uint32_t tc_num = hns3_get_tc_num(hw);
3631 uint32_t half_mps = pf->mps >> 1;
3632 struct hns3_priv_buf *priv;
3633 uint32_t min_rx_priv;
3637 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3639 rx_priv = rx_priv / tc_num;
3641 if (tc_num <= NEED_RESERVE_TC_NUM)
3642 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3645 * Minimum value of private buffer in rx direction (min_rx_priv) is
3646 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3647 * buffer if rx_priv is greater than min_rx_priv.
3649 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3650 COMPENSATE_HALF_MPS_NUM * half_mps;
3651 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3652 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3654 if (rx_priv < min_rx_priv)
3657 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3658 priv = &buf_alloc->priv_buf[i];
3664 if (!(hw->hw_tc_map & BIT(i)))
3668 priv->buf_size = rx_priv;
3669 priv->wl.high = rx_priv - pf->dv_buf_size;
3670 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3673 buf_alloc->s_buf.buf_size = 0;
3679 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3680 * @hw: pointer to struct hns3_hw
3681 * @buf_alloc: pointer to buffer calculation data
3682 * @return: 0: calculate sucessful, negative: fail
3685 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3687 /* When DCB is not supported, rx private buffer is not allocated. */
3688 if (!hns3_dev_dcb_supported(hw)) {
3689 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3690 struct hns3_pf *pf = &hns->pf;
3691 uint32_t rx_all = pf->pkt_buf_size;
3693 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3694 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3701 * Try to allocate privated packet buffer for all TCs without share
3704 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3708 * Try to allocate privated packet buffer for all TCs with share
3711 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3715 * For different application scenes, the enabled port number, TC number
3716 * and no_drop TC number are different. In order to obtain the better
3717 * performance, software could allocate the buffer size and configure
3718 * the waterline by tring to decrease the private buffer size according
3719 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3722 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3725 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3728 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3735 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3737 struct hns3_rx_priv_buff_cmd *req;
3738 struct hns3_cmd_desc desc;
3743 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3744 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3746 /* Alloc private buffer TCs */
3747 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3748 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3751 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3752 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3755 buf_size = buf_alloc->s_buf.buf_size;
3756 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3757 (1 << HNS3_TC0_PRI_BUF_EN_B));
3759 ret = hns3_cmd_send(hw, &desc, 1);
3761 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3767 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3769 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3770 struct hns3_rx_priv_wl_buf *req;
3771 struct hns3_priv_buf *priv;
3772 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3776 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3777 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3779 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3781 /* The first descriptor set the NEXT bit to 1 */
3783 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3785 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3787 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3788 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3790 priv = &buf_alloc->priv_buf[idx];
3791 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3793 req->tc_wl[j].high |=
3794 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3795 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3797 req->tc_wl[j].low |=
3798 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3802 /* Send 2 descriptor at one time */
3803 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3805 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3811 hns3_common_thrd_config(struct hns3_hw *hw,
3812 struct hns3_pkt_buf_alloc *buf_alloc)
3814 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3815 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3816 struct hns3_rx_com_thrd *req;
3817 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3818 struct hns3_tc_thrd *tc;
3823 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3824 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3826 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3828 /* The first descriptor set the NEXT bit to 1 */
3830 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3832 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3834 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3835 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3836 tc = &s_buf->tc_thrd[tc_idx];
3838 req->com_thrd[j].high =
3839 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3840 req->com_thrd[j].high |=
3841 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3842 req->com_thrd[j].low =
3843 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3844 req->com_thrd[j].low |=
3845 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3849 /* Send 2 descriptors at one time */
3850 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3852 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3858 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3860 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3861 struct hns3_rx_com_wl *req;
3862 struct hns3_cmd_desc desc;
3865 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3867 req = (struct hns3_rx_com_wl *)desc.data;
3868 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3869 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3871 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3872 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3874 ret = hns3_cmd_send(hw, &desc, 1);
3876 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3882 hns3_buffer_alloc(struct hns3_hw *hw)
3884 struct hns3_pkt_buf_alloc pkt_buf;
3887 memset(&pkt_buf, 0, sizeof(pkt_buf));
3888 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3891 "could not calc tx buffer size for all TCs %d",
3896 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3898 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3902 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3905 "could not calc rx priv buffer size for all TCs %d",
3910 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3912 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3916 if (hns3_dev_dcb_supported(hw)) {
3917 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3920 "could not configure rx private waterline %d",
3925 ret = hns3_common_thrd_config(hw, &pkt_buf);
3928 "could not configure common threshold %d",
3934 ret = hns3_common_wl_config(hw, &pkt_buf);
3936 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3943 hns3_firmware_compat_config(struct hns3_hw *hw, bool is_init)
3945 struct hns3_firmware_compat_cmd *req;
3946 struct hns3_cmd_desc desc;
3947 uint32_t compat = 0;
3949 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_FIRMWARE_COMPAT_CFG, false);
3950 req = (struct hns3_firmware_compat_cmd *)desc.data;
3953 hns3_set_bit(compat, HNS3_LINK_EVENT_REPORT_EN_B, 1);
3954 hns3_set_bit(compat, HNS3_NCSI_ERROR_REPORT_EN_B, 0);
3957 req->compat = rte_cpu_to_le_32(compat);
3959 return hns3_cmd_send(hw, &desc, 1);
3963 hns3_mac_init(struct hns3_hw *hw)
3965 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3966 struct hns3_mac *mac = &hw->mac;
3967 struct hns3_pf *pf = &hns->pf;
3970 pf->support_sfp_query = true;
3971 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3972 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3974 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3978 mac->link_status = ETH_LINK_DOWN;
3980 return hns3_config_mtu(hw, pf->mps);
3984 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3986 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
3987 #define HNS3_ETHERTYPE_ALREADY_ADD 1
3988 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
3989 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
3994 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
3999 switch (resp_code) {
4000 case HNS3_ETHERTYPE_SUCCESS_ADD:
4001 case HNS3_ETHERTYPE_ALREADY_ADD:
4004 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4006 "add mac ethertype failed for manager table overflow.");
4007 return_status = -EIO;
4009 case HNS3_ETHERTYPE_KEY_CONFLICT:
4010 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4011 return_status = -EIO;
4015 "add mac ethertype failed for undefined, code=%u.",
4017 return_status = -EIO;
4021 return return_status;
4025 hns3_add_mgr_tbl(struct hns3_hw *hw,
4026 const struct hns3_mac_mgr_tbl_entry_cmd *req)
4028 struct hns3_cmd_desc desc;
4033 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4034 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4036 ret = hns3_cmd_send(hw, &desc, 1);
4039 "add mac ethertype failed for cmd_send, ret =%d.",
4044 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4045 retval = rte_le_to_cpu_16(desc.retval);
4047 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4051 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4052 int *table_item_num)
4054 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4057 * In current version, we add one item in management table as below:
4058 * 0x0180C200000E -- LLDP MC address
4061 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4062 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4063 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4064 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4065 tbl->i_port_bitmap = 0x1;
4066 *table_item_num = 1;
4070 hns3_init_mgr_tbl(struct hns3_hw *hw)
4072 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
4073 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4078 memset(mgr_table, 0, sizeof(mgr_table));
4079 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4080 for (i = 0; i < table_item_num; i++) {
4081 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4083 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4093 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4094 bool en_mc, bool en_bc, int vport_id)
4099 memset(param, 0, sizeof(struct hns3_promisc_param));
4101 param->enable = HNS3_PROMISC_EN_UC;
4103 param->enable |= HNS3_PROMISC_EN_MC;
4105 param->enable |= HNS3_PROMISC_EN_BC;
4106 param->vf_id = vport_id;
4110 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4112 struct hns3_promisc_cfg_cmd *req;
4113 struct hns3_cmd_desc desc;
4116 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4118 req = (struct hns3_promisc_cfg_cmd *)desc.data;
4119 req->vf_id = param->vf_id;
4120 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4121 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4123 ret = hns3_cmd_send(hw, &desc, 1);
4125 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4131 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4133 struct hns3_promisc_param param;
4134 bool en_bc_pmc = true;
4138 * In current version VF is not supported when PF is driven by DPDK
4139 * driver, just need to configure parameters for PF vport.
4141 vf_id = HNS3_PF_FUNC_ID;
4143 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4144 return hns3_cmd_set_promisc_mode(hw, ¶m);
4148 hns3_promisc_init(struct hns3_hw *hw)
4150 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4151 struct hns3_pf *pf = &hns->pf;
4152 struct hns3_promisc_param param;
4156 ret = hns3_set_promisc_mode(hw, false, false);
4158 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4163 * In current version VFs are not supported when PF is driven by DPDK
4164 * driver. After PF has been taken over by DPDK, the original VF will
4165 * be invalid. So, there is a possibility of entry residues. It should
4166 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4169 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4170 hns3_promisc_param_init(¶m, false, false, false, func_id);
4171 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4173 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4174 " ret = %d", func_id, ret);
4183 hns3_promisc_uninit(struct hns3_hw *hw)
4185 struct hns3_promisc_param param;
4189 func_id = HNS3_PF_FUNC_ID;
4192 * In current version VFs are not supported when PF is driven by
4193 * DPDK driver, and VFs' promisc mode status has been cleared during
4194 * init and their status will not change. So just clear PF's promisc
4195 * mode status during uninit.
4197 hns3_promisc_param_init(¶m, false, false, false, func_id);
4198 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4200 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4201 " uninit, ret = %d", ret);
4205 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4207 bool allmulti = dev->data->all_multicast ? true : false;
4208 struct hns3_adapter *hns = dev->data->dev_private;
4209 struct hns3_hw *hw = &hns->hw;
4214 rte_spinlock_lock(&hw->lock);
4215 ret = hns3_set_promisc_mode(hw, true, true);
4217 rte_spinlock_unlock(&hw->lock);
4218 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4224 * When promiscuous mode was enabled, disable the vlan filter to let
4225 * all packets coming in in the receiving direction.
4227 offloads = dev->data->dev_conf.rxmode.offloads;
4228 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4229 ret = hns3_enable_vlan_filter(hns, false);
4231 hns3_err(hw, "failed to enable promiscuous mode due to "
4232 "failure to disable vlan filter, ret = %d",
4234 err = hns3_set_promisc_mode(hw, false, allmulti);
4236 hns3_err(hw, "failed to restore promiscuous "
4237 "status after disable vlan filter "
4238 "failed during enabling promiscuous "
4239 "mode, ret = %d", ret);
4243 rte_spinlock_unlock(&hw->lock);
4249 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4251 bool allmulti = dev->data->all_multicast ? true : false;
4252 struct hns3_adapter *hns = dev->data->dev_private;
4253 struct hns3_hw *hw = &hns->hw;
4258 /* If now in all_multicast mode, must remain in all_multicast mode. */
4259 rte_spinlock_lock(&hw->lock);
4260 ret = hns3_set_promisc_mode(hw, false, allmulti);
4262 rte_spinlock_unlock(&hw->lock);
4263 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4267 /* when promiscuous mode was disabled, restore the vlan filter status */
4268 offloads = dev->data->dev_conf.rxmode.offloads;
4269 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4270 ret = hns3_enable_vlan_filter(hns, true);
4272 hns3_err(hw, "failed to disable promiscuous mode due to"
4273 " failure to restore vlan filter, ret = %d",
4275 err = hns3_set_promisc_mode(hw, true, true);
4277 hns3_err(hw, "failed to restore promiscuous "
4278 "status after enabling vlan filter "
4279 "failed during disabling promiscuous "
4280 "mode, ret = %d", ret);
4283 rte_spinlock_unlock(&hw->lock);
4289 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4291 struct hns3_adapter *hns = dev->data->dev_private;
4292 struct hns3_hw *hw = &hns->hw;
4295 if (dev->data->promiscuous)
4298 rte_spinlock_lock(&hw->lock);
4299 ret = hns3_set_promisc_mode(hw, false, true);
4300 rte_spinlock_unlock(&hw->lock);
4302 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4309 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4311 struct hns3_adapter *hns = dev->data->dev_private;
4312 struct hns3_hw *hw = &hns->hw;
4315 /* If now in promiscuous mode, must remain in all_multicast mode. */
4316 if (dev->data->promiscuous)
4319 rte_spinlock_lock(&hw->lock);
4320 ret = hns3_set_promisc_mode(hw, false, false);
4321 rte_spinlock_unlock(&hw->lock);
4323 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4330 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4332 struct hns3_hw *hw = &hns->hw;
4333 bool allmulti = hw->data->all_multicast ? true : false;
4336 if (hw->data->promiscuous) {
4337 ret = hns3_set_promisc_mode(hw, true, true);
4339 hns3_err(hw, "failed to restore promiscuous mode, "
4344 ret = hns3_set_promisc_mode(hw, false, allmulti);
4346 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4352 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4354 struct hns3_sfp_speed_cmd *resp;
4355 struct hns3_cmd_desc desc;
4358 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4359 resp = (struct hns3_sfp_speed_cmd *)desc.data;
4360 ret = hns3_cmd_send(hw, &desc, 1);
4361 if (ret == -EOPNOTSUPP) {
4362 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4365 hns3_err(hw, "get sfp speed failed %d", ret);
4369 *speed = resp->sfp_speed;
4375 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4377 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4378 duplex = ETH_LINK_FULL_DUPLEX;
4384 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4386 struct hns3_mac *mac = &hw->mac;
4387 uint32_t cur_speed = mac->link_speed;
4390 duplex = hns3_check_speed_dup(duplex, speed);
4391 if (mac->link_speed == speed && mac->link_duplex == duplex)
4394 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4398 mac->link_speed = speed;
4399 ret = hns3_dcb_port_shaper_cfg(hw);
4401 hns3_err(hw, "failed to configure port shaper, ret = %d.", ret);
4402 mac->link_speed = cur_speed;
4406 mac->link_duplex = duplex;
4412 hns3_update_fiber_link_info(struct hns3_hw *hw)
4414 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4418 /* If IMP do not support get SFP/qSFP speed, return directly */
4419 if (!pf->support_sfp_query)
4422 ret = hns3_get_sfp_speed(hw, &speed);
4423 if (ret == -EOPNOTSUPP) {
4424 pf->support_sfp_query = false;
4429 if (speed == ETH_SPEED_NUM_NONE)
4430 return 0; /* do nothing if no SFP */
4432 /* Config full duplex for SFP */
4433 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4437 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4439 struct hns3_adapter *hns = eth_dev->data->dev_private;
4440 struct hns3_hw *hw = &hns->hw;
4443 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4445 else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4446 ret = hns3_update_fiber_link_info(hw);
4452 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4454 struct hns3_config_mac_mode_cmd *req;
4455 struct hns3_cmd_desc desc;
4456 uint32_t loop_en = 0;
4460 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4462 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4465 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4466 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4467 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4468 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4469 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4470 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4471 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4472 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4473 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4474 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4477 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4478 * when receiving frames. Otherwise, CRC will be stripped.
4480 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4481 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4483 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4484 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4485 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4486 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4487 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4489 ret = hns3_cmd_send(hw, &desc, 1);
4491 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4497 hns3_get_mac_link_status(struct hns3_hw *hw)
4499 struct hns3_link_status_cmd *req;
4500 struct hns3_cmd_desc desc;
4504 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4505 ret = hns3_cmd_send(hw, &desc, 1);
4507 hns3_err(hw, "get link status cmd failed %d", ret);
4508 return ETH_LINK_DOWN;
4511 req = (struct hns3_link_status_cmd *)desc.data;
4512 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4514 return !!link_status;
4518 hns3_update_link_status(struct hns3_hw *hw)
4522 state = hns3_get_mac_link_status(hw);
4523 if (state != hw->mac.link_status) {
4524 hw->mac.link_status = state;
4525 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4533 * Current, the PF driver get link status by two ways:
4534 * 1) Periodic polling in the intr thread context, driver call
4535 * hns3_update_link_status to update link status.
4536 * 2) Firmware report async interrupt, driver process the event in the intr
4537 * thread context, and call hns3_update_link_status to update link status.
4539 * If detect link status changed, driver need report LSE. One method is add the
4540 * report LSE logic in hns3_update_link_status.
4542 * But the PF driver ops(link_update) also call hns3_update_link_status to
4543 * update link status.
4544 * If we report LSE in hns3_update_link_status, it may lead to deadlock in the
4545 * bonding application.
4547 * So add the one new API which used only in intr thread context.
4550 hns3_update_link_status_and_event(struct hns3_hw *hw)
4552 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4553 bool changed = hns3_update_link_status(hw);
4555 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4559 hns3_service_handler(void *param)
4561 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4562 struct hns3_adapter *hns = eth_dev->data->dev_private;
4563 struct hns3_hw *hw = &hns->hw;
4565 if (!hns3_is_reset_pending(hns)) {
4566 hns3_update_link_status_and_event(hw);
4567 hns3_update_link_info(eth_dev);
4569 hns3_warn(hw, "Cancel the query when reset is pending");
4572 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4576 hns3_init_hardware(struct hns3_adapter *hns)
4578 struct hns3_hw *hw = &hns->hw;
4581 ret = hns3_map_tqp(hw);
4583 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4587 ret = hns3_init_umv_space(hw);
4589 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4593 ret = hns3_mac_init(hw);
4595 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4599 ret = hns3_init_mgr_tbl(hw);
4601 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4605 ret = hns3_promisc_init(hw);
4607 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4612 ret = hns3_init_vlan_config(hns);
4614 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4618 ret = hns3_dcb_init(hw);
4620 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4624 ret = hns3_init_fd_config(hns);
4626 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4630 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4632 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4636 ret = hns3_config_gro(hw, false);
4638 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4643 * In the initialization clearing the all hardware mapping relationship
4644 * configurations between queues and interrupt vectors is needed, so
4645 * some error caused by the residual configurations, such as the
4646 * unexpected interrupt, can be avoid.
4648 ret = hns3_init_ring_with_vector(hw);
4650 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4655 * Requiring firmware to enable some features, driver can
4656 * still work without it.
4658 ret = hns3_firmware_compat_config(hw, true);
4660 PMD_INIT_LOG(WARNING, "firmware compatible features not "
4661 "supported, ret = %d.", ret);
4666 hns3_uninit_umv_space(hw);
4671 hns3_clear_hw(struct hns3_hw *hw)
4673 struct hns3_cmd_desc desc;
4676 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4678 ret = hns3_cmd_send(hw, &desc, 1);
4679 if (ret && ret != -EOPNOTSUPP)
4686 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4691 * The new firmware support report more hardware error types by
4692 * msix mode. These errors are defined as RAS errors in hardware
4693 * and belong to a different type from the MSI-x errors processed
4694 * by the network driver.
4696 * Network driver should open the new error report on initialition
4698 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4699 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4700 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4704 hns3_init_pf(struct rte_eth_dev *eth_dev)
4706 struct rte_device *dev = eth_dev->device;
4707 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4708 struct hns3_adapter *hns = eth_dev->data->dev_private;
4709 struct hns3_hw *hw = &hns->hw;
4712 PMD_INIT_FUNC_TRACE();
4714 /* Get hardware io base address from pcie BAR2 IO space */
4715 hw->io_base = pci_dev->mem_resource[2].addr;
4717 /* Firmware command queue initialize */
4718 ret = hns3_cmd_init_queue(hw);
4720 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4721 goto err_cmd_init_queue;
4724 hns3_clear_all_event_cause(hw);
4726 /* Firmware command initialize */
4727 ret = hns3_cmd_init(hw);
4729 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4734 * To ensure that the hardware environment is clean during
4735 * initialization, the driver actively clear the hardware environment
4736 * during initialization, including PF and corresponding VFs' vlan, mac,
4737 * flow table configurations, etc.
4739 ret = hns3_clear_hw(hw);
4741 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4745 hns3_config_all_msix_error(hw, true);
4747 ret = rte_intr_callback_register(&pci_dev->intr_handle,
4748 hns3_interrupt_handler,
4751 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4752 goto err_intr_callback_register;
4755 /* Enable interrupt */
4756 rte_intr_enable(&pci_dev->intr_handle);
4757 hns3_pf_enable_irq0(hw);
4759 /* Get configuration */
4760 ret = hns3_get_configuration(hw);
4762 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4763 goto err_get_config;
4766 ret = hns3_tqp_stats_init(hw);
4768 goto err_get_config;
4770 ret = hns3_init_hardware(hns);
4772 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4776 /* Initialize flow director filter list & hash */
4777 ret = hns3_fdir_filter_init(hns);
4779 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4783 hns3_rss_set_default_args(hw);
4785 ret = hns3_enable_hw_error_intr(hns, true);
4787 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4789 goto err_enable_intr;
4792 hns3_tm_conf_init(eth_dev);
4797 hns3_fdir_filter_uninit(hns);
4799 (void)hns3_firmware_compat_config(hw, false);
4800 hns3_uninit_umv_space(hw);
4802 hns3_tqp_stats_uninit(hw);
4804 hns3_pf_disable_irq0(hw);
4805 rte_intr_disable(&pci_dev->intr_handle);
4806 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4808 err_intr_callback_register:
4810 hns3_cmd_uninit(hw);
4811 hns3_cmd_destroy_queue(hw);
4819 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4821 struct hns3_adapter *hns = eth_dev->data->dev_private;
4822 struct rte_device *dev = eth_dev->device;
4823 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4824 struct hns3_hw *hw = &hns->hw;
4826 PMD_INIT_FUNC_TRACE();
4828 hns3_tm_conf_uninit(eth_dev);
4829 hns3_enable_hw_error_intr(hns, false);
4830 hns3_rss_uninit(hns);
4831 (void)hns3_config_gro(hw, false);
4832 hns3_promisc_uninit(hw);
4833 hns3_fdir_filter_uninit(hns);
4834 (void)hns3_firmware_compat_config(hw, false);
4835 hns3_uninit_umv_space(hw);
4836 hns3_tqp_stats_uninit(hw);
4837 hns3_pf_disable_irq0(hw);
4838 rte_intr_disable(&pci_dev->intr_handle);
4839 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4841 hns3_config_all_msix_error(hw, false);
4842 hns3_cmd_uninit(hw);
4843 hns3_cmd_destroy_queue(hw);
4848 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4850 struct hns3_hw *hw = &hns->hw;
4853 ret = hns3_dcb_cfg_update(hns);
4858 * The hns3_dcb_cfg_update may configure TM module, so
4859 * hns3_tm_conf_update must called later.
4861 ret = hns3_tm_conf_update(hw);
4863 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
4867 ret = hns3_init_queues(hns, reset_queue);
4869 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
4873 ret = hns3_cfg_mac_mode(hw, true);
4875 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
4876 goto err_config_mac_mode;
4880 err_config_mac_mode:
4881 hns3_dev_release_mbufs(hns);
4883 * Here is exception handling, hns3_reset_all_tqps will have the
4884 * corresponding error message if it is handled incorrectly, so it is
4885 * not necessary to check hns3_reset_all_tqps return value, here keep
4886 * ret as the error code causing the exception.
4888 (void)hns3_reset_all_tqps(hns);
4893 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4895 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4896 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4897 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4898 uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
4899 uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4900 uint32_t intr_vector;
4905 * hns3 needs a separate interrupt to be used as event interrupt which
4906 * could not be shared with task queue pair, so KERNEL drivers need
4907 * support multiple interrupt vectors.
4909 if (dev->data->dev_conf.intr_conf.rxq == 0 ||
4910 !rte_intr_cap_multiple(intr_handle))
4913 rte_intr_disable(intr_handle);
4914 intr_vector = hw->used_rx_queues;
4915 /* creates event fd for each intr vector when MSIX is used */
4916 if (rte_intr_efd_enable(intr_handle, intr_vector))
4919 if (intr_handle->intr_vec == NULL) {
4920 intr_handle->intr_vec =
4921 rte_zmalloc("intr_vec",
4922 hw->used_rx_queues * sizeof(int), 0);
4923 if (intr_handle->intr_vec == NULL) {
4924 hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
4925 hw->used_rx_queues);
4927 goto alloc_intr_vec_error;
4931 if (rte_intr_allow_others(intr_handle)) {
4932 vec = RTE_INTR_VEC_RXTX_OFFSET;
4933 base = RTE_INTR_VEC_RXTX_OFFSET;
4936 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4937 ret = hns3_bind_ring_with_vector(hw, vec, true,
4938 HNS3_RING_TYPE_RX, q_id);
4940 goto bind_vector_error;
4941 intr_handle->intr_vec[q_id] = vec;
4943 * If there are not enough efds (e.g. not enough interrupt),
4944 * remaining queues will be bond to the last interrupt.
4946 if (vec < base + intr_handle->nb_efd - 1)
4949 rte_intr_enable(intr_handle);
4953 rte_free(intr_handle->intr_vec);
4954 intr_handle->intr_vec = NULL;
4955 alloc_intr_vec_error:
4956 rte_intr_efd_disable(intr_handle);
4961 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4963 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4964 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4965 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4969 if (dev->data->dev_conf.intr_conf.rxq == 0)
4972 if (rte_intr_dp_is_en(intr_handle)) {
4973 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4974 ret = hns3_bind_ring_with_vector(hw,
4975 intr_handle->intr_vec[q_id], true,
4976 HNS3_RING_TYPE_RX, q_id);
4986 hns3_restore_filter(struct rte_eth_dev *dev)
4988 hns3_restore_rss_filter(dev);
4992 hns3_dev_start(struct rte_eth_dev *dev)
4994 struct hns3_adapter *hns = dev->data->dev_private;
4995 struct hns3_hw *hw = &hns->hw;
4998 PMD_INIT_FUNC_TRACE();
4999 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5002 rte_spinlock_lock(&hw->lock);
5003 hw->adapter_state = HNS3_NIC_STARTING;
5005 ret = hns3_do_start(hns, true);
5007 hw->adapter_state = HNS3_NIC_CONFIGURED;
5008 rte_spinlock_unlock(&hw->lock);
5011 ret = hns3_map_rx_interrupt(dev);
5013 hw->adapter_state = HNS3_NIC_CONFIGURED;
5014 rte_spinlock_unlock(&hw->lock);
5019 * There are three register used to control the status of a TQP
5020 * (contains a pair of Tx queue and Rx queue) in the new version network
5021 * engine. One is used to control the enabling of Tx queue, the other is
5022 * used to control the enabling of Rx queue, and the last is the master
5023 * switch used to control the enabling of the tqp. The Tx register and
5024 * TQP register must be enabled at the same time to enable a Tx queue.
5025 * The same applies to the Rx queue. For the older network engine, this
5026 * function only refresh the enabled flag, and it is used to update the
5027 * status of queue in the dpdk framework.
5029 ret = hns3_start_all_txqs(dev);
5031 hw->adapter_state = HNS3_NIC_CONFIGURED;
5032 rte_spinlock_unlock(&hw->lock);
5036 ret = hns3_start_all_rxqs(dev);
5038 hns3_stop_all_txqs(dev);
5039 hw->adapter_state = HNS3_NIC_CONFIGURED;
5040 rte_spinlock_unlock(&hw->lock);
5044 hw->adapter_state = HNS3_NIC_STARTED;
5045 rte_spinlock_unlock(&hw->lock);
5047 hns3_rx_scattered_calc(dev);
5048 hns3_set_rxtx_function(dev);
5049 hns3_mp_req_start_rxtx(dev);
5050 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5052 hns3_restore_filter(dev);
5054 /* Enable interrupt of all rx queues before enabling queues */
5055 hns3_dev_all_rx_queue_intr_enable(hw, true);
5058 * After finished the initialization, enable tqps to receive/transmit
5059 * packets and refresh all queue status.
5061 hns3_start_tqps(hw);
5063 hns3_tm_dev_start_proc(hw);
5065 hns3_info(hw, "hns3 dev start successful!");
5070 hns3_do_stop(struct hns3_adapter *hns)
5072 struct hns3_hw *hw = &hns->hw;
5075 ret = hns3_cfg_mac_mode(hw, false);
5078 hw->mac.link_status = ETH_LINK_DOWN;
5080 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5081 hns3_configure_all_mac_addr(hns, true);
5082 ret = hns3_reset_all_tqps(hns);
5084 hns3_err(hw, "failed to reset all queues ret = %d.",
5089 hw->mac.default_addr_setted = false;
5094 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5096 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5097 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5098 struct hns3_adapter *hns = dev->data->dev_private;
5099 struct hns3_hw *hw = &hns->hw;
5100 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5101 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5104 if (dev->data->dev_conf.intr_conf.rxq == 0)
5107 /* unmap the ring with vector */
5108 if (rte_intr_allow_others(intr_handle)) {
5109 vec = RTE_INTR_VEC_RXTX_OFFSET;
5110 base = RTE_INTR_VEC_RXTX_OFFSET;
5112 if (rte_intr_dp_is_en(intr_handle)) {
5113 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5114 (void)hns3_bind_ring_with_vector(hw, vec, false,
5117 if (vec < base + intr_handle->nb_efd - 1)
5121 /* Clean datapath event and queue/vec mapping */
5122 rte_intr_efd_disable(intr_handle);
5123 if (intr_handle->intr_vec) {
5124 rte_free(intr_handle->intr_vec);
5125 intr_handle->intr_vec = NULL;
5130 hns3_dev_stop(struct rte_eth_dev *dev)
5132 struct hns3_adapter *hns = dev->data->dev_private;
5133 struct hns3_hw *hw = &hns->hw;
5135 PMD_INIT_FUNC_TRACE();
5136 dev->data->dev_started = 0;
5138 hw->adapter_state = HNS3_NIC_STOPPING;
5139 hns3_set_rxtx_function(dev);
5141 /* Disable datapath on secondary process. */
5142 hns3_mp_req_stop_rxtx(dev);
5143 /* Prevent crashes when queues are still in use. */
5144 rte_delay_ms(hw->tqps_num);
5146 rte_spinlock_lock(&hw->lock);
5147 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5148 hns3_tm_dev_stop_proc(hw);
5151 hns3_unmap_rx_interrupt(dev);
5152 hns3_dev_release_mbufs(hns);
5153 hw->adapter_state = HNS3_NIC_CONFIGURED;
5155 hns3_rx_scattered_reset(dev);
5156 rte_eal_alarm_cancel(hns3_service_handler, dev);
5157 rte_spinlock_unlock(&hw->lock);
5163 hns3_dev_close(struct rte_eth_dev *eth_dev)
5165 struct hns3_adapter *hns = eth_dev->data->dev_private;
5166 struct hns3_hw *hw = &hns->hw;
5169 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5170 rte_free(eth_dev->process_private);
5171 eth_dev->process_private = NULL;
5175 if (hw->adapter_state == HNS3_NIC_STARTED)
5176 ret = hns3_dev_stop(eth_dev);
5178 hw->adapter_state = HNS3_NIC_CLOSING;
5179 hns3_reset_abort(hns);
5180 hw->adapter_state = HNS3_NIC_CLOSED;
5182 hns3_configure_all_mc_mac_addr(hns, true);
5183 hns3_remove_all_vlan_table(hns);
5184 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5185 hns3_uninit_pf(eth_dev);
5186 hns3_free_all_queues(eth_dev);
5187 rte_free(hw->reset.wait_data);
5188 rte_free(eth_dev->process_private);
5189 eth_dev->process_private = NULL;
5190 hns3_mp_uninit_primary();
5191 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5197 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5199 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5200 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5202 fc_conf->pause_time = pf->pause_time;
5204 /* return fc current mode */
5205 switch (hw->current_mode) {
5207 fc_conf->mode = RTE_FC_FULL;
5209 case HNS3_FC_TX_PAUSE:
5210 fc_conf->mode = RTE_FC_TX_PAUSE;
5212 case HNS3_FC_RX_PAUSE:
5213 fc_conf->mode = RTE_FC_RX_PAUSE;
5217 fc_conf->mode = RTE_FC_NONE;
5225 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5229 hw->requested_mode = HNS3_FC_NONE;
5231 case RTE_FC_RX_PAUSE:
5232 hw->requested_mode = HNS3_FC_RX_PAUSE;
5234 case RTE_FC_TX_PAUSE:
5235 hw->requested_mode = HNS3_FC_TX_PAUSE;
5238 hw->requested_mode = HNS3_FC_FULL;
5241 hw->requested_mode = HNS3_FC_NONE;
5242 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5243 "configured to RTE_FC_NONE", mode);
5249 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5251 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5252 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5255 if (fc_conf->high_water || fc_conf->low_water ||
5256 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5257 hns3_err(hw, "Unsupported flow control settings specified, "
5258 "high_water(%u), low_water(%u), send_xon(%u) and "
5259 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5260 fc_conf->high_water, fc_conf->low_water,
5261 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5264 if (fc_conf->autoneg) {
5265 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5268 if (!fc_conf->pause_time) {
5269 hns3_err(hw, "Invalid pause time %u setting.",
5270 fc_conf->pause_time);
5274 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5275 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5276 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5277 "current_fc_status = %d", hw->current_fc_status);
5281 hns3_get_fc_mode(hw, fc_conf->mode);
5282 if (hw->requested_mode == hw->current_mode &&
5283 pf->pause_time == fc_conf->pause_time)
5286 rte_spinlock_lock(&hw->lock);
5287 ret = hns3_fc_enable(dev, fc_conf);
5288 rte_spinlock_unlock(&hw->lock);
5294 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5295 struct rte_eth_pfc_conf *pfc_conf)
5297 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5298 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5302 if (!hns3_dev_dcb_supported(hw)) {
5303 hns3_err(hw, "This port does not support dcb configurations.");
5307 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5308 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5309 hns3_err(hw, "Unsupported flow control settings specified, "
5310 "high_water(%u), low_water(%u), send_xon(%u) and "
5311 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5312 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5313 pfc_conf->fc.send_xon,
5314 pfc_conf->fc.mac_ctrl_frame_fwd);
5317 if (pfc_conf->fc.autoneg) {
5318 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5321 if (pfc_conf->fc.pause_time == 0) {
5322 hns3_err(hw, "Invalid pause time %u setting.",
5323 pfc_conf->fc.pause_time);
5327 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5328 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5329 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5330 "current_fc_status = %d", hw->current_fc_status);
5334 priority = pfc_conf->priority;
5335 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5336 if (hw->dcb_info.pfc_en & BIT(priority) &&
5337 hw->requested_mode == hw->current_mode &&
5338 pfc_conf->fc.pause_time == pf->pause_time)
5341 rte_spinlock_lock(&hw->lock);
5342 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5343 rte_spinlock_unlock(&hw->lock);
5349 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5351 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5352 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5353 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5356 rte_spinlock_lock(&hw->lock);
5357 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5358 dcb_info->nb_tcs = pf->local_max_tc;
5360 dcb_info->nb_tcs = 1;
5362 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5363 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5364 for (i = 0; i < dcb_info->nb_tcs; i++)
5365 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5367 for (i = 0; i < hw->num_tc; i++) {
5368 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5369 dcb_info->tc_queue.tc_txq[0][i].base =
5370 hw->tc_queue[i].tqp_offset;
5371 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5372 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5373 hw->tc_queue[i].tqp_count;
5375 rte_spinlock_unlock(&hw->lock);
5381 hns3_reinit_dev(struct hns3_adapter *hns)
5383 struct hns3_hw *hw = &hns->hw;
5386 ret = hns3_cmd_init(hw);
5388 hns3_err(hw, "Failed to init cmd: %d", ret);
5392 ret = hns3_reset_all_tqps(hns);
5394 hns3_err(hw, "Failed to reset all queues: %d", ret);
5398 ret = hns3_init_hardware(hns);
5400 hns3_err(hw, "Failed to init hardware: %d", ret);
5404 ret = hns3_enable_hw_error_intr(hns, true);
5406 hns3_err(hw, "fail to enable hw error interrupts: %d",
5410 hns3_info(hw, "Reset done, driver initialization finished.");
5416 is_pf_reset_done(struct hns3_hw *hw)
5418 uint32_t val, reg, reg_bit;
5420 switch (hw->reset.level) {
5421 case HNS3_IMP_RESET:
5422 reg = HNS3_GLOBAL_RESET_REG;
5423 reg_bit = HNS3_IMP_RESET_BIT;
5425 case HNS3_GLOBAL_RESET:
5426 reg = HNS3_GLOBAL_RESET_REG;
5427 reg_bit = HNS3_GLOBAL_RESET_BIT;
5429 case HNS3_FUNC_RESET:
5430 reg = HNS3_FUN_RST_ING;
5431 reg_bit = HNS3_FUN_RST_ING_B;
5433 case HNS3_FLR_RESET:
5435 hns3_err(hw, "Wait for unsupported reset level: %d",
5439 val = hns3_read_dev(hw, reg);
5440 if (hns3_get_bit(val, reg_bit))
5447 hns3_is_reset_pending(struct hns3_adapter *hns)
5449 struct hns3_hw *hw = &hns->hw;
5450 enum hns3_reset_level reset;
5452 hns3_check_event_cause(hns, NULL);
5453 reset = hns3_get_reset_level(hns, &hw->reset.pending);
5454 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5455 hns3_warn(hw, "High level reset %d is pending", reset);
5458 reset = hns3_get_reset_level(hns, &hw->reset.request);
5459 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5460 hns3_warn(hw, "High level reset %d is request", reset);
5467 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5469 struct hns3_hw *hw = &hns->hw;
5470 struct hns3_wait_data *wait_data = hw->reset.wait_data;
5473 if (wait_data->result == HNS3_WAIT_SUCCESS)
5475 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5476 gettimeofday(&tv, NULL);
5477 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5478 tv.tv_sec, tv.tv_usec);
5480 } else if (wait_data->result == HNS3_WAIT_REQUEST)
5483 wait_data->hns = hns;
5484 wait_data->check_completion = is_pf_reset_done;
5485 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5486 HNS3_RESET_WAIT_MS + get_timeofday_ms();
5487 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5488 wait_data->count = HNS3_RESET_WAIT_CNT;
5489 wait_data->result = HNS3_WAIT_REQUEST;
5490 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5495 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5497 struct hns3_cmd_desc desc;
5498 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5500 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5501 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5502 req->fun_reset_vfid = func_id;
5504 return hns3_cmd_send(hw, &desc, 1);
5508 hns3_imp_reset_cmd(struct hns3_hw *hw)
5510 struct hns3_cmd_desc desc;
5512 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5513 desc.data[0] = 0xeedd;
5515 return hns3_cmd_send(hw, &desc, 1);
5519 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5521 struct hns3_hw *hw = &hns->hw;
5525 gettimeofday(&tv, NULL);
5526 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5527 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5528 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5529 tv.tv_sec, tv.tv_usec);
5533 switch (reset_level) {
5534 case HNS3_IMP_RESET:
5535 hns3_imp_reset_cmd(hw);
5536 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5537 tv.tv_sec, tv.tv_usec);
5539 case HNS3_GLOBAL_RESET:
5540 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5541 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5542 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5543 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5544 tv.tv_sec, tv.tv_usec);
5546 case HNS3_FUNC_RESET:
5547 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5548 tv.tv_sec, tv.tv_usec);
5549 /* schedule again to check later */
5550 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5551 hns3_schedule_reset(hns);
5554 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5557 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5560 static enum hns3_reset_level
5561 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5563 struct hns3_hw *hw = &hns->hw;
5564 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5566 /* Return the highest priority reset level amongst all */
5567 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5568 reset_level = HNS3_IMP_RESET;
5569 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5570 reset_level = HNS3_GLOBAL_RESET;
5571 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5572 reset_level = HNS3_FUNC_RESET;
5573 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5574 reset_level = HNS3_FLR_RESET;
5576 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5577 return HNS3_NONE_RESET;
5583 hns3_record_imp_error(struct hns3_adapter *hns)
5585 struct hns3_hw *hw = &hns->hw;
5588 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5589 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5590 hns3_warn(hw, "Detected IMP RD poison!");
5591 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5592 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5593 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5596 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5597 hns3_warn(hw, "Detected IMP CMDQ error!");
5598 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5599 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5600 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5605 hns3_prepare_reset(struct hns3_adapter *hns)
5607 struct hns3_hw *hw = &hns->hw;
5611 switch (hw->reset.level) {
5612 case HNS3_FUNC_RESET:
5613 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5618 * After performaning pf reset, it is not necessary to do the
5619 * mailbox handling or send any command to firmware, because
5620 * any mailbox handling or command to firmware is only valid
5621 * after hns3_cmd_init is called.
5623 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
5624 hw->reset.stats.request_cnt++;
5626 case HNS3_IMP_RESET:
5627 hns3_record_imp_error(hns);
5628 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5629 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5630 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5639 hns3_set_rst_done(struct hns3_hw *hw)
5641 struct hns3_pf_rst_done_cmd *req;
5642 struct hns3_cmd_desc desc;
5644 req = (struct hns3_pf_rst_done_cmd *)desc.data;
5645 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5646 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5647 return hns3_cmd_send(hw, &desc, 1);
5651 hns3_stop_service(struct hns3_adapter *hns)
5653 struct hns3_hw *hw = &hns->hw;
5654 struct rte_eth_dev *eth_dev;
5656 eth_dev = &rte_eth_devices[hw->data->port_id];
5657 if (hw->adapter_state == HNS3_NIC_STARTED) {
5658 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5659 hns3_update_link_status_and_event(hw);
5661 hw->mac.link_status = ETH_LINK_DOWN;
5663 hns3_set_rxtx_function(eth_dev);
5665 /* Disable datapath on secondary process. */
5666 hns3_mp_req_stop_rxtx(eth_dev);
5667 rte_delay_ms(hw->tqps_num);
5669 rte_spinlock_lock(&hw->lock);
5670 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5671 hw->adapter_state == HNS3_NIC_STOPPING) {
5672 hns3_enable_all_queues(hw, false);
5674 hw->reset.mbuf_deferred_free = true;
5676 hw->reset.mbuf_deferred_free = false;
5679 * It is cumbersome for hardware to pick-and-choose entries for deletion
5680 * from table space. Hence, for function reset software intervention is
5681 * required to delete the entries
5683 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
5684 hns3_configure_all_mc_mac_addr(hns, true);
5685 rte_spinlock_unlock(&hw->lock);
5691 hns3_start_service(struct hns3_adapter *hns)
5693 struct hns3_hw *hw = &hns->hw;
5694 struct rte_eth_dev *eth_dev;
5696 if (hw->reset.level == HNS3_IMP_RESET ||
5697 hw->reset.level == HNS3_GLOBAL_RESET)
5698 hns3_set_rst_done(hw);
5699 eth_dev = &rte_eth_devices[hw->data->port_id];
5700 hns3_set_rxtx_function(eth_dev);
5701 hns3_mp_req_start_rxtx(eth_dev);
5702 if (hw->adapter_state == HNS3_NIC_STARTED) {
5704 * This API parent function already hold the hns3_hw.lock, the
5705 * hns3_service_handler may report lse, in bonding application
5706 * it will call driver's ops which may acquire the hns3_hw.lock
5707 * again, thus lead to deadlock.
5708 * We defer calls hns3_service_handler to avoid the deadlock.
5710 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
5711 hns3_service_handler, eth_dev);
5713 /* Enable interrupt of all rx queues before enabling queues */
5714 hns3_dev_all_rx_queue_intr_enable(hw, true);
5716 * Enable state of each rxq and txq will be recovered after
5717 * reset, so we need to restore them before enable all tqps;
5719 hns3_restore_tqp_enable_state(hw);
5721 * When finished the initialization, enable queues to receive
5722 * and transmit packets.
5724 hns3_enable_all_queues(hw, true);
5731 hns3_restore_conf(struct hns3_adapter *hns)
5733 struct hns3_hw *hw = &hns->hw;
5736 ret = hns3_configure_all_mac_addr(hns, false);
5740 ret = hns3_configure_all_mc_mac_addr(hns, false);
5744 ret = hns3_dev_promisc_restore(hns);
5748 ret = hns3_restore_vlan_table(hns);
5752 ret = hns3_restore_vlan_conf(hns);
5756 ret = hns3_restore_all_fdir_filter(hns);
5760 ret = hns3_restore_rx_interrupt(hw);
5764 ret = hns3_restore_gro_conf(hw);
5768 ret = hns3_restore_fec(hw);
5772 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5773 ret = hns3_do_start(hns, false);
5776 hns3_info(hw, "hns3 dev restart successful!");
5777 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5778 hw->adapter_state = HNS3_NIC_CONFIGURED;
5782 hns3_configure_all_mc_mac_addr(hns, true);
5784 hns3_configure_all_mac_addr(hns, true);
5789 hns3_reset_service(void *param)
5791 struct hns3_adapter *hns = (struct hns3_adapter *)param;
5792 struct hns3_hw *hw = &hns->hw;
5793 enum hns3_reset_level reset_level;
5794 struct timeval tv_delta;
5795 struct timeval tv_start;
5801 * The interrupt is not triggered within the delay time.
5802 * The interrupt may have been lost. It is necessary to handle
5803 * the interrupt to recover from the error.
5805 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
5806 SCHEDULE_DEFERRED) {
5807 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
5809 hns3_err(hw, "Handling interrupts in delayed tasks");
5810 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5811 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5812 if (reset_level == HNS3_NONE_RESET) {
5813 hns3_err(hw, "No reset level is set, try IMP reset");
5814 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5817 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
5820 * Check if there is any ongoing reset in the hardware. This status can
5821 * be checked from reset_pending. If there is then, we need to wait for
5822 * hardware to complete reset.
5823 * a. If we are able to figure out in reasonable time that hardware
5824 * has fully resetted then, we can proceed with driver, client
5826 * b. else, we can come back later to check this status so re-sched
5829 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5830 if (reset_level != HNS3_NONE_RESET) {
5831 gettimeofday(&tv_start, NULL);
5832 ret = hns3_reset_process(hns, reset_level);
5833 gettimeofday(&tv, NULL);
5834 timersub(&tv, &tv_start, &tv_delta);
5835 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5836 tv_delta.tv_usec / USEC_PER_MSEC;
5837 if (msec > HNS3_RESET_PROCESS_MS)
5838 hns3_err(hw, "%d handle long time delta %" PRIx64
5839 " ms time=%ld.%.6ld",
5840 hw->reset.level, msec,
5841 tv.tv_sec, tv.tv_usec);
5846 /* Check if we got any *new* reset requests to be honored */
5847 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5848 if (reset_level != HNS3_NONE_RESET)
5849 hns3_msix_process(hns, reset_level);
5853 hns3_get_speed_capa_num(uint16_t device_id)
5857 switch (device_id) {
5858 case HNS3_DEV_ID_25GE:
5859 case HNS3_DEV_ID_25GE_RDMA:
5862 case HNS3_DEV_ID_100G_RDMA_MACSEC:
5863 case HNS3_DEV_ID_200G_RDMA:
5875 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
5878 switch (device_id) {
5879 case HNS3_DEV_ID_25GE:
5881 case HNS3_DEV_ID_25GE_RDMA:
5882 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
5883 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
5885 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
5886 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
5887 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
5889 case HNS3_DEV_ID_100G_RDMA_MACSEC:
5890 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
5891 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
5893 case HNS3_DEV_ID_200G_RDMA:
5894 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
5895 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
5905 hns3_fec_get_capability(struct rte_eth_dev *dev,
5906 struct rte_eth_fec_capa *speed_fec_capa,
5909 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5910 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5911 uint16_t device_id = pci_dev->id.device_id;
5912 unsigned int capa_num;
5915 capa_num = hns3_get_speed_capa_num(device_id);
5916 if (capa_num == 0) {
5917 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
5922 if (speed_fec_capa == NULL || num < capa_num)
5925 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
5933 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
5935 struct hns3_config_fec_cmd *req;
5936 struct hns3_cmd_desc desc;
5940 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
5941 * in device of link speed
5944 if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
5949 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
5950 req = (struct hns3_config_fec_cmd *)desc.data;
5951 ret = hns3_cmd_send(hw, &desc, 1);
5953 hns3_err(hw, "get current fec auto state failed, ret = %d",
5958 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
5963 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
5965 #define QUERY_ACTIVE_SPEED 1
5966 struct hns3_sfp_speed_cmd *resp;
5967 uint32_t tmp_fec_capa;
5969 struct hns3_cmd_desc desc;
5973 * If link is down and AUTO is enabled, AUTO is returned, otherwise,
5974 * configured FEC mode is returned.
5975 * If link is up, current FEC mode is returned.
5977 if (hw->mac.link_status == ETH_LINK_DOWN) {
5978 ret = get_current_fec_auto_state(hw, &auto_state);
5982 if (auto_state == 0x1) {
5983 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
5988 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
5989 resp = (struct hns3_sfp_speed_cmd *)desc.data;
5990 resp->query_type = QUERY_ACTIVE_SPEED;
5992 ret = hns3_cmd_send(hw, &desc, 1);
5993 if (ret == -EOPNOTSUPP) {
5994 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
5997 hns3_err(hw, "get FEC failed, ret = %d", ret);
6002 * FEC mode order defined in hns3 hardware is inconsistend with
6003 * that defined in the ethdev library. So the sequence needs
6006 switch (resp->active_fec) {
6007 case HNS3_HW_FEC_MODE_NOFEC:
6008 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6010 case HNS3_HW_FEC_MODE_BASER:
6011 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6013 case HNS3_HW_FEC_MODE_RS:
6014 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6017 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6021 *fec_capa = tmp_fec_capa;
6026 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6028 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6030 return hns3_fec_get_internal(hw, fec_capa);
6034 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6036 struct hns3_config_fec_cmd *req;
6037 struct hns3_cmd_desc desc;
6040 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6042 req = (struct hns3_config_fec_cmd *)desc.data;
6044 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6045 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6046 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6048 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6049 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6050 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6052 case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6053 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6054 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6056 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6057 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6062 ret = hns3_cmd_send(hw, &desc, 1);
6064 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6070 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6072 struct hns3_mac *mac = &hw->mac;
6075 switch (mac->link_speed) {
6076 case ETH_SPEED_NUM_10G:
6077 cur_capa = fec_capa[1].capa;
6079 case ETH_SPEED_NUM_25G:
6080 case ETH_SPEED_NUM_100G:
6081 case ETH_SPEED_NUM_200G:
6082 cur_capa = fec_capa[0].capa;
6093 is_fec_mode_one_bit_set(uint32_t mode)
6098 for (i = 0; i < sizeof(mode); i++)
6099 if (mode >> i & 0x1)
6102 return cnt == 1 ? true : false;
6106 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6108 #define FEC_CAPA_NUM 2
6109 struct hns3_adapter *hns = dev->data->dev_private;
6110 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6111 struct hns3_pf *pf = &hns->pf;
6113 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6115 uint32_t num = FEC_CAPA_NUM;
6118 ret = hns3_fec_get_capability(dev, fec_capa, num);
6122 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6123 if (!is_fec_mode_one_bit_set(mode))
6124 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6125 "FEC mode should be only one bit set", mode);
6128 * Check whether the configured mode is within the FEC capability.
6129 * If not, the configured mode will not be supported.
6131 cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6132 if (!(cur_capa & mode)) {
6133 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6137 ret = hns3_set_fec_hw(hw, mode);
6141 pf->fec_mode = mode;
6146 hns3_restore_fec(struct hns3_hw *hw)
6148 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6149 struct hns3_pf *pf = &hns->pf;
6150 uint32_t mode = pf->fec_mode;
6153 ret = hns3_set_fec_hw(hw, mode);
6155 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6162 hns3_query_dev_fec_info(struct hns3_hw *hw)
6164 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6165 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6168 ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6170 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6175 static const struct eth_dev_ops hns3_eth_dev_ops = {
6176 .dev_configure = hns3_dev_configure,
6177 .dev_start = hns3_dev_start,
6178 .dev_stop = hns3_dev_stop,
6179 .dev_close = hns3_dev_close,
6180 .promiscuous_enable = hns3_dev_promiscuous_enable,
6181 .promiscuous_disable = hns3_dev_promiscuous_disable,
6182 .allmulticast_enable = hns3_dev_allmulticast_enable,
6183 .allmulticast_disable = hns3_dev_allmulticast_disable,
6184 .mtu_set = hns3_dev_mtu_set,
6185 .stats_get = hns3_stats_get,
6186 .stats_reset = hns3_stats_reset,
6187 .xstats_get = hns3_dev_xstats_get,
6188 .xstats_get_names = hns3_dev_xstats_get_names,
6189 .xstats_reset = hns3_dev_xstats_reset,
6190 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
6191 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6192 .dev_infos_get = hns3_dev_infos_get,
6193 .fw_version_get = hns3_fw_version_get,
6194 .rx_queue_setup = hns3_rx_queue_setup,
6195 .tx_queue_setup = hns3_tx_queue_setup,
6196 .rx_queue_release = hns3_dev_rx_queue_release,
6197 .tx_queue_release = hns3_dev_tx_queue_release,
6198 .rx_queue_start = hns3_dev_rx_queue_start,
6199 .rx_queue_stop = hns3_dev_rx_queue_stop,
6200 .tx_queue_start = hns3_dev_tx_queue_start,
6201 .tx_queue_stop = hns3_dev_tx_queue_stop,
6202 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
6203 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
6204 .rxq_info_get = hns3_rxq_info_get,
6205 .txq_info_get = hns3_txq_info_get,
6206 .rx_burst_mode_get = hns3_rx_burst_mode_get,
6207 .tx_burst_mode_get = hns3_tx_burst_mode_get,
6208 .flow_ctrl_get = hns3_flow_ctrl_get,
6209 .flow_ctrl_set = hns3_flow_ctrl_set,
6210 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6211 .mac_addr_add = hns3_add_mac_addr,
6212 .mac_addr_remove = hns3_remove_mac_addr,
6213 .mac_addr_set = hns3_set_default_mac_addr,
6214 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
6215 .link_update = hns3_dev_link_update,
6216 .rss_hash_update = hns3_dev_rss_hash_update,
6217 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
6218 .reta_update = hns3_dev_rss_reta_update,
6219 .reta_query = hns3_dev_rss_reta_query,
6220 .filter_ctrl = hns3_dev_filter_ctrl,
6221 .vlan_filter_set = hns3_vlan_filter_set,
6222 .vlan_tpid_set = hns3_vlan_tpid_set,
6223 .vlan_offload_set = hns3_vlan_offload_set,
6224 .vlan_pvid_set = hns3_vlan_pvid_set,
6225 .get_reg = hns3_get_regs,
6226 .get_dcb_info = hns3_get_dcb_info,
6227 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6228 .fec_get_capability = hns3_fec_get_capability,
6229 .fec_get = hns3_fec_get,
6230 .fec_set = hns3_fec_set,
6231 .tm_ops_get = hns3_tm_ops_get,
6234 static const struct hns3_reset_ops hns3_reset_ops = {
6235 .reset_service = hns3_reset_service,
6236 .stop_service = hns3_stop_service,
6237 .prepare_reset = hns3_prepare_reset,
6238 .wait_hardware_ready = hns3_wait_hardware_ready,
6239 .reinit_dev = hns3_reinit_dev,
6240 .restore_conf = hns3_restore_conf,
6241 .start_service = hns3_start_service,
6245 hns3_dev_init(struct rte_eth_dev *eth_dev)
6247 struct hns3_adapter *hns = eth_dev->data->dev_private;
6248 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6249 struct rte_ether_addr *eth_addr;
6250 struct hns3_hw *hw = &hns->hw;
6253 PMD_INIT_FUNC_TRACE();
6255 eth_dev->process_private = (struct hns3_process_private *)
6256 rte_zmalloc_socket("hns3_filter_list",
6257 sizeof(struct hns3_process_private),
6258 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6259 if (eth_dev->process_private == NULL) {
6260 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6263 /* initialize flow filter lists */
6264 hns3_filterlist_init(eth_dev);
6266 hns3_set_rxtx_function(eth_dev);
6267 eth_dev->dev_ops = &hns3_eth_dev_ops;
6268 eth_dev->rx_queue_count = hns3_rx_queue_count;
6269 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6270 ret = hns3_mp_init_secondary();
6272 PMD_INIT_LOG(ERR, "Failed to init for secondary "
6273 "process, ret = %d", ret);
6274 goto err_mp_init_secondary;
6277 hw->secondary_cnt++;
6281 ret = hns3_mp_init_primary();
6284 "Failed to init for primary process, ret = %d",
6286 goto err_mp_init_primary;
6289 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6291 hw->data = eth_dev->data;
6294 * Set default max packet size according to the mtu
6295 * default vale in DPDK frame.
6297 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6299 ret = hns3_reset_init(hw);
6301 goto err_init_reset;
6302 hw->reset.ops = &hns3_reset_ops;
6304 ret = hns3_init_pf(eth_dev);
6306 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6310 /* Allocate memory for storing MAC addresses */
6311 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6312 sizeof(struct rte_ether_addr) *
6313 HNS3_UC_MACADDR_NUM, 0);
6314 if (eth_dev->data->mac_addrs == NULL) {
6315 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6316 "to store MAC addresses",
6317 sizeof(struct rte_ether_addr) *
6318 HNS3_UC_MACADDR_NUM);
6320 goto err_rte_zmalloc;
6323 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6324 if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6325 rte_eth_random_addr(hw->mac.mac_addr);
6326 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6327 (struct rte_ether_addr *)hw->mac.mac_addr);
6328 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6329 "unicast address, using random MAC address %s",
6332 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6333 ð_dev->data->mac_addrs[0]);
6335 hw->adapter_state = HNS3_NIC_INITIALIZED;
6337 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6339 hns3_err(hw, "Reschedule reset service after dev_init");
6340 hns3_schedule_reset(hns);
6342 /* IMP will wait ready flag before reset */
6343 hns3_notify_reset_ready(hw, false);
6346 hns3_info(hw, "hns3 dev initialization successful!");
6350 hns3_uninit_pf(eth_dev);
6353 rte_free(hw->reset.wait_data);
6356 hns3_mp_uninit_primary();
6358 err_mp_init_primary:
6359 err_mp_init_secondary:
6360 eth_dev->dev_ops = NULL;
6361 eth_dev->rx_pkt_burst = NULL;
6362 eth_dev->tx_pkt_burst = NULL;
6363 eth_dev->tx_pkt_prepare = NULL;
6364 rte_free(eth_dev->process_private);
6365 eth_dev->process_private = NULL;
6370 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6372 struct hns3_adapter *hns = eth_dev->data->dev_private;
6373 struct hns3_hw *hw = &hns->hw;
6375 PMD_INIT_FUNC_TRACE();
6377 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6378 rte_free(eth_dev->process_private);
6379 eth_dev->process_private = NULL;
6383 if (hw->adapter_state < HNS3_NIC_CLOSING)
6384 hns3_dev_close(eth_dev);
6386 hw->adapter_state = HNS3_NIC_REMOVED;
6391 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6392 struct rte_pci_device *pci_dev)
6394 return rte_eth_dev_pci_generic_probe(pci_dev,
6395 sizeof(struct hns3_adapter),
6400 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6402 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6405 static const struct rte_pci_id pci_id_hns3_map[] = {
6406 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6407 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6408 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6409 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6410 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6411 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6412 { .vendor_id = 0, }, /* sentinel */
6415 static struct rte_pci_driver rte_hns3_pmd = {
6416 .id_table = pci_id_hns3_map,
6417 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6418 .probe = eth_hns3_pci_probe,
6419 .remove = eth_hns3_pci_remove,
6422 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6423 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6424 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6425 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6426 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);