drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9 #include <rte_kvargs.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18
  19 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  20 #define HNS3_SERVICE_QUICK_INTERVAL     10
  21 #define HNS3_INVALID_PVID               0xFFFF
  22
  23 #define HNS3_FILTER_TYPE_VF             0
  24 #define HNS3_FILTER_TYPE_PORT           1
  25 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  26 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  27 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  28 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  29 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  30 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  31                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  32 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  33                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  34
  35 /* Reset related Registers */
  36 #define HNS3_GLOBAL_RESET_BIT           0
  37 #define HNS3_CORE_RESET_BIT             1
  38 #define HNS3_IMP_RESET_BIT              2
  39 #define HNS3_FUN_RST_ING_B              0
  40
  41 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  42 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  43 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  44 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  45
  46 #define HNS3_RESET_WAIT_MS      100
  47 #define HNS3_RESET_WAIT_CNT     200
  48
  49 /* FEC mode order defined in HNS3 hardware */
  50 #define HNS3_HW_FEC_MODE_NOFEC  0
  51 #define HNS3_HW_FEC_MODE_BASER  1
  52 #define HNS3_HW_FEC_MODE_RS     2
  53
  54 enum hns3_evt_cause {
  55         HNS3_VECTOR0_EVENT_RST,
  56         HNS3_VECTOR0_EVENT_MBX,
  57         HNS3_VECTOR0_EVENT_ERR,
  58         HNS3_VECTOR0_EVENT_PTP,
  59         HNS3_VECTOR0_EVENT_OTHER,
  60 };
  61
  62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  63         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  64                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  66
  67         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  71
  72         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  75
  76         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  80
  81         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  82                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  84
  85         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  88 };
  89
  90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  91                                                  uint64_t *levels);
  92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  94                                     int on);
  95 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  96 static bool hns3_update_link_status(struct hns3_hw *hw);
  97
  98 static int hns3_add_mc_addr(struct hns3_hw *hw,
  99                             struct rte_ether_addr *mac_addr);
 100 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 101                             struct rte_ether_addr *mac_addr);
 102 static int hns3_restore_fec(struct hns3_hw *hw);
 103 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 104 static int hns3_do_stop(struct hns3_adapter *hns);
 105 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
 106
 107 void hns3_ether_format_addr(char *buf, uint16_t size,
 108                             const struct rte_ether_addr *ether_addr)
 109 {
 110         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 111                 ether_addr->addr_bytes[0],
 112                 ether_addr->addr_bytes[4],
 113                 ether_addr->addr_bytes[5]);
 114 }
 115
 116 static void
 117 hns3_pf_disable_irq0(struct hns3_hw *hw)
 118 {
 119         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 120 }
 121
 122 static void
 123 hns3_pf_enable_irq0(struct hns3_hw *hw)
 124 {
 125         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 126 }
 127
 128 static enum hns3_evt_cause
 129 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 130                           uint32_t *vec_val)
 131 {
 132         struct hns3_hw *hw = &hns->hw;
 133
 134         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 135         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 136         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 137         if (!is_delay) {
 138                 hw->reset.stats.imp_cnt++;
 139                 hns3_warn(hw, "IMP reset detected, clear reset status");
 140         } else {
 141                 hns3_schedule_delayed_reset(hns);
 142                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 143         }
 144
 145         return HNS3_VECTOR0_EVENT_RST;
 146 }
 147
 148 static enum hns3_evt_cause
 149 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 150                              uint32_t *vec_val)
 151 {
 152         struct hns3_hw *hw = &hns->hw;
 153
 154         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 155         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 156         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 157         if (!is_delay) {
 158                 hw->reset.stats.global_cnt++;
 159                 hns3_warn(hw, "Global reset detected, clear reset status");
 160         } else {
 161                 hns3_schedule_delayed_reset(hns);
 162                 hns3_warn(hw,
 163                           "Global reset detected, don't clear reset status");
 164         }
 165
 166         return HNS3_VECTOR0_EVENT_RST;
 167 }
 168
 169 static enum hns3_evt_cause
 170 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 171 {
 172         struct hns3_hw *hw = &hns->hw;
 173         uint32_t vector0_int_stats;
 174         uint32_t cmdq_src_val;
 175         uint32_t hw_err_src_reg;
 176         uint32_t val;
 177         enum hns3_evt_cause ret;
 178         bool is_delay;
 179
 180         /* fetch the events from their corresponding regs */
 181         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 182         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 183         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 184
 185         is_delay = clearval == NULL ? true : false;
 186         /*
 187          * Assumption: If by any chance reset and mailbox events are reported
 188          * together then we will only process reset event and defer the
 189          * processing of the mailbox events. Since, we would have not cleared
 190          * RX CMDQ event this time we would receive again another interrupt
 191          * from H/W just for the mailbox.
 192          */
 193         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 194                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 195                 goto out;
 196         }
 197
 198         /* Global reset */
 199         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 200                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 201                 goto out;
 202         }
 203
 204         /* Check for vector0 1588 event source */
 205         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
 206                 val = BIT(HNS3_VECTOR0_1588_INT_B);
 207                 ret = HNS3_VECTOR0_EVENT_PTP;
 208                 goto out;
 209         }
 210
 211         /* check for vector0 msix event source */
 212         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 213             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 214                 val = vector0_int_stats | hw_err_src_reg;
 215                 ret = HNS3_VECTOR0_EVENT_ERR;
 216                 goto out;
 217         }
 218
 219         /* check for vector0 mailbox(=CMDQ RX) event source */
 220         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 221                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 222                 val = cmdq_src_val;
 223                 ret = HNS3_VECTOR0_EVENT_MBX;
 224                 goto out;
 225         }
 226
 227         val = vector0_int_stats;
 228         ret = HNS3_VECTOR0_EVENT_OTHER;
 229 out:
 230
 231         if (clearval)
 232                 *clearval = val;
 233         return ret;
 234 }
 235
 236 static bool
 237 hns3_is_1588_event_type(uint32_t event_type)
 238 {
 239         return (event_type == HNS3_VECTOR0_EVENT_PTP);
 240 }
 241
 242 static void
 243 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 244 {
 245         if (event_type == HNS3_VECTOR0_EVENT_RST ||
 246             hns3_is_1588_event_type(event_type))
 247                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 248         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 249                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 250 }
 251
 252 static void
 253 hns3_clear_all_event_cause(struct hns3_hw *hw)
 254 {
 255         uint32_t vector0_int_stats;
 256
 257         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 258         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 259                 hns3_warn(hw, "Probe during IMP reset interrupt");
 260
 261         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 262                 hns3_warn(hw, "Probe during Global reset interrupt");
 263
 264         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 265                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 266                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 267                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 268         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 269         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
 270                                 BIT(HNS3_VECTOR0_1588_INT_B));
 271 }
 272
 273 static void
 274 hns3_handle_mac_tnl(struct hns3_hw *hw)
 275 {
 276         struct hns3_cmd_desc desc;
 277         uint32_t status;
 278         int ret;
 279
 280         /* query and clear mac tnl interrupt */
 281         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 282         ret = hns3_cmd_send(hw, &desc, 1);
 283         if (ret) {
 284                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 285                 return;
 286         }
 287
 288         status = rte_le_to_cpu_32(desc.data[0]);
 289         if (status) {
 290                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 291                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 292                                           false);
 293                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 294                 ret = hns3_cmd_send(hw, &desc, 1);
 295                 if (ret)
 296                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 297                                  ret);
 298         }
 299 }
 300
 301 static void
 302 hns3_interrupt_handler(void *param)
 303 {
 304         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 305         struct hns3_adapter *hns = dev->data->dev_private;
 306         struct hns3_hw *hw = &hns->hw;
 307         enum hns3_evt_cause event_cause;
 308         uint32_t clearval = 0;
 309         uint32_t vector0_int;
 310         uint32_t ras_int;
 311         uint32_t cmdq_int;
 312
 313         /* Disable interrupt */
 314         hns3_pf_disable_irq0(hw);
 315
 316         event_cause = hns3_check_event_cause(hns, &clearval);
 317         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 318         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 319         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 320         hns3_clear_event_cause(hw, event_cause, clearval);
 321         /* vector 0 interrupt is shared with reset and mailbox source events. */
 322         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 323                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 324                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 325                           vector0_int, ras_int, cmdq_int);
 326                 hns3_handle_mac_tnl(hw);
 327                 hns3_handle_error(hns);
 328         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 329                 hns3_warn(hw, "received reset interrupt");
 330                 hns3_schedule_reset(hns);
 331         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 332                 hns3_dev_handle_mbx_msg(hw);
 333         } else {
 334                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 335                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 336                           vector0_int, ras_int, cmdq_int);
 337         }
 338
 339         /* Enable interrupt if it is not cause by reset */
 340         hns3_pf_enable_irq0(hw);
 341 }
 342
 343 static int
 344 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 345 {
 346 #define HNS3_VLAN_ID_OFFSET_STEP        160
 347 #define HNS3_VLAN_BYTE_SIZE             8
 348         struct hns3_vlan_filter_pf_cfg_cmd *req;
 349         struct hns3_hw *hw = &hns->hw;
 350         uint8_t vlan_offset_byte_val;
 351         struct hns3_cmd_desc desc;
 352         uint8_t vlan_offset_byte;
 353         uint8_t vlan_offset_base;
 354         int ret;
 355
 356         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 357
 358         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 359         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 360                            HNS3_VLAN_BYTE_SIZE;
 361         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 362
 363         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 364         req->vlan_offset = vlan_offset_base;
 365         req->vlan_cfg = on ? 0 : 1;
 366         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 367
 368         ret = hns3_cmd_send(hw, &desc, 1);
 369         if (ret)
 370                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 371                          vlan_id, ret);
 372
 373         return ret;
 374 }
 375
 376 static void
 377 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 378 {
 379         struct hns3_user_vlan_table *vlan_entry;
 380         struct hns3_pf *pf = &hns->pf;
 381
 382         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 383                 if (vlan_entry->vlan_id == vlan_id) {
 384                         if (vlan_entry->hd_tbl_status)
 385                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 386                         LIST_REMOVE(vlan_entry, next);
 387                         rte_free(vlan_entry);
 388                         break;
 389                 }
 390         }
 391 }
 392
 393 static void
 394 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 395                         bool writen_to_tbl)
 396 {
 397         struct hns3_user_vlan_table *vlan_entry;
 398         struct hns3_hw *hw = &hns->hw;
 399         struct hns3_pf *pf = &hns->pf;
 400
 401         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 402                 if (vlan_entry->vlan_id == vlan_id)
 403                         return;
 404         }
 405
 406         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 407         if (vlan_entry == NULL) {
 408                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 409                 return;
 410         }
 411
 412         vlan_entry->hd_tbl_status = writen_to_tbl;
 413         vlan_entry->vlan_id = vlan_id;
 414
 415         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 416 }
 417
 418 static int
 419 hns3_restore_vlan_table(struct hns3_adapter *hns)
 420 {
 421         struct hns3_user_vlan_table *vlan_entry;
 422         struct hns3_hw *hw = &hns->hw;
 423         struct hns3_pf *pf = &hns->pf;
 424         uint16_t vlan_id;
 425         int ret = 0;
 426
 427         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 428                 return hns3_vlan_pvid_configure(hns,
 429                                                 hw->port_base_vlan_cfg.pvid, 1);
 430
 431         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 432                 if (vlan_entry->hd_tbl_status) {
 433                         vlan_id = vlan_entry->vlan_id;
 434                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 435                         if (ret)
 436                                 break;
 437                 }
 438         }
 439
 440         return ret;
 441 }
 442
 443 static int
 444 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 445 {
 446         struct hns3_hw *hw = &hns->hw;
 447         bool writen_to_tbl = false;
 448         int ret = 0;
 449
 450         /*
 451          * When vlan filter is enabled, hardware regards packets without vlan
 452          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 453          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 454          */
 455         if (on == 0 && vlan_id == 0)
 456                 return 0;
 457
 458         /*
 459          * When port base vlan enabled, we use port base vlan as the vlan
 460          * filter condition. In this case, we don't update vlan filter table
 461          * when user add new vlan or remove exist vlan, just update the
 462          * vlan list. The vlan id in vlan list will be written in vlan filter
 463          * table until port base vlan disabled
 464          */
 465         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 466                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 467                 writen_to_tbl = true;
 468         }
 469
 470         if (ret == 0) {
 471                 if (on)
 472                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 473                 else
 474                         hns3_rm_dev_vlan_table(hns, vlan_id);
 475         }
 476         return ret;
 477 }
 478
 479 static int
 480 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 481 {
 482         struct hns3_adapter *hns = dev->data->dev_private;
 483         struct hns3_hw *hw = &hns->hw;
 484         int ret;
 485
 486         rte_spinlock_lock(&hw->lock);
 487         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 488         rte_spinlock_unlock(&hw->lock);
 489         return ret;
 490 }
 491
 492 static int
 493 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 494                          uint16_t tpid)
 495 {
 496         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 497         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 498         struct hns3_hw *hw = &hns->hw;
 499         struct hns3_cmd_desc desc;
 500         int ret;
 501
 502         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 503              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 504                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 505                 return -EINVAL;
 506         }
 507
 508         if (tpid != RTE_ETHER_TYPE_VLAN) {
 509                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 510                 return -EINVAL;
 511         }
 512
 513         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 514         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 515
 516         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 517                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 518                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 519         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 520                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 521                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 522                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 523                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 524         }
 525
 526         ret = hns3_cmd_send(hw, &desc, 1);
 527         if (ret) {
 528                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 529                          ret);
 530                 return ret;
 531         }
 532
 533         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 534
 535         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 536         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 537         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 538
 539         ret = hns3_cmd_send(hw, &desc, 1);
 540         if (ret)
 541                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 542                          ret);
 543         return ret;
 544 }
 545
 546 static int
 547 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 548                    uint16_t tpid)
 549 {
 550         struct hns3_adapter *hns = dev->data->dev_private;
 551         struct hns3_hw *hw = &hns->hw;
 552         int ret;
 553
 554         rte_spinlock_lock(&hw->lock);
 555         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 556         rte_spinlock_unlock(&hw->lock);
 557         return ret;
 558 }
 559
 560 static int
 561 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 562                              struct hns3_rx_vtag_cfg *vcfg)
 563 {
 564         struct hns3_vport_vtag_rx_cfg_cmd *req;
 565         struct hns3_hw *hw = &hns->hw;
 566         struct hns3_cmd_desc desc;
 567         uint16_t vport_id;
 568         uint8_t bitmap;
 569         int ret;
 570
 571         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 572
 573         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 574         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 575                      vcfg->strip_tag1_en ? 1 : 0);
 576         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 577                      vcfg->strip_tag2_en ? 1 : 0);
 578         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 579                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 580         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 581                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 582
 583         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 584         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 585                      vcfg->strip_tag1_discard_en ? 1 : 0);
 586         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 587                      vcfg->strip_tag2_discard_en ? 1 : 0);
 588         /*
 589          * In current version VF is not supported when PF is driven by DPDK
 590          * driver, just need to configure parameters for PF vport.
 591          */
 592         vport_id = HNS3_PF_FUNC_ID;
 593         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 594         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 595         req->vf_bitmap[req->vf_offset] = bitmap;
 596
 597         ret = hns3_cmd_send(hw, &desc, 1);
 598         if (ret)
 599                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 600         return ret;
 601 }
 602
 603 static void
 604 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 605                            struct hns3_rx_vtag_cfg *vcfg)
 606 {
 607         struct hns3_pf *pf = &hns->pf;
 608         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 609 }
 610
 611 static void
 612 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 613                            struct hns3_tx_vtag_cfg *vcfg)
 614 {
 615         struct hns3_pf *pf = &hns->pf;
 616         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 617 }
 618
 619 static int
 620 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 621 {
 622         struct hns3_rx_vtag_cfg rxvlan_cfg;
 623         struct hns3_hw *hw = &hns->hw;
 624         int ret;
 625
 626         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 627                 rxvlan_cfg.strip_tag1_en = false;
 628                 rxvlan_cfg.strip_tag2_en = enable;
 629                 rxvlan_cfg.strip_tag2_discard_en = false;
 630         } else {
 631                 rxvlan_cfg.strip_tag1_en = enable;
 632                 rxvlan_cfg.strip_tag2_en = true;
 633                 rxvlan_cfg.strip_tag2_discard_en = true;
 634         }
 635
 636         rxvlan_cfg.strip_tag1_discard_en = false;
 637         rxvlan_cfg.vlan1_vlan_prionly = false;
 638         rxvlan_cfg.vlan2_vlan_prionly = false;
 639         rxvlan_cfg.rx_vlan_offload_en = enable;
 640
 641         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 642         if (ret) {
 643                 hns3_err(hw, "%s strip rx vtag failed, ret = %d.",
 644                                 enable ? "enable" : "disable", ret);
 645                 return ret;
 646         }
 647
 648         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 649
 650         return ret;
 651 }
 652
 653 static int
 654 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 655                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 656 {
 657         struct hns3_vlan_filter_ctrl_cmd *req;
 658         struct hns3_cmd_desc desc;
 659         int ret;
 660
 661         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 662
 663         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 664         req->vlan_type = vlan_type;
 665         req->vlan_fe = filter_en ? fe_type : 0;
 666         req->vf_id = vf_id;
 667
 668         ret = hns3_cmd_send(hw, &desc, 1);
 669         if (ret)
 670                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 671
 672         return ret;
 673 }
 674
 675 static int
 676 hns3_vlan_filter_init(struct hns3_adapter *hns)
 677 {
 678         struct hns3_hw *hw = &hns->hw;
 679         int ret;
 680
 681         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 682                                         HNS3_FILTER_FE_EGRESS, false,
 683                                         HNS3_PF_FUNC_ID);
 684         if (ret) {
 685                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 686                 return ret;
 687         }
 688
 689         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 690                                         HNS3_FILTER_FE_INGRESS, false,
 691                                         HNS3_PF_FUNC_ID);
 692         if (ret)
 693                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 694
 695         return ret;
 696 }
 697
 698 static int
 699 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 700 {
 701         struct hns3_hw *hw = &hns->hw;
 702         int ret;
 703
 704         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 705                                         HNS3_FILTER_FE_INGRESS, enable,
 706                                         HNS3_PF_FUNC_ID);
 707         if (ret)
 708                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 709                          enable ? "enable" : "disable", ret);
 710
 711         return ret;
 712 }
 713
 714 static int
 715 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 716 {
 717         struct hns3_adapter *hns = dev->data->dev_private;
 718         struct hns3_hw *hw = &hns->hw;
 719         struct rte_eth_rxmode *rxmode;
 720         unsigned int tmp_mask;
 721         bool enable;
 722         int ret = 0;
 723
 724         rte_spinlock_lock(&hw->lock);
 725         rxmode = &dev->data->dev_conf.rxmode;
 726         tmp_mask = (unsigned int)mask;
 727         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 728                 /* ignore vlan filter configuration during promiscuous mode */
 729                 if (!dev->data->promiscuous) {
 730                         /* Enable or disable VLAN filter */
 731                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 732                                  true : false;
 733
 734                         ret = hns3_enable_vlan_filter(hns, enable);
 735                         if (ret) {
 736                                 rte_spinlock_unlock(&hw->lock);
 737                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 738                                          enable ? "enable" : "disable", ret);
 739                                 return ret;
 740                         }
 741                 }
 742         }
 743
 744         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 745                 /* Enable or disable VLAN stripping */
 746                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 747                     true : false;
 748
 749                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 750                 if (ret) {
 751                         rte_spinlock_unlock(&hw->lock);
 752                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 753                                  enable ? "enable" : "disable", ret);
 754                         return ret;
 755                 }
 756         }
 757
 758         rte_spinlock_unlock(&hw->lock);
 759
 760         return ret;
 761 }
 762
 763 static int
 764 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 765                              struct hns3_tx_vtag_cfg *vcfg)
 766 {
 767         struct hns3_vport_vtag_tx_cfg_cmd *req;
 768         struct hns3_cmd_desc desc;
 769         struct hns3_hw *hw = &hns->hw;
 770         uint16_t vport_id;
 771         uint8_t bitmap;
 772         int ret;
 773
 774         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 775
 776         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 777         req->def_vlan_tag1 = vcfg->default_tag1;
 778         req->def_vlan_tag2 = vcfg->default_tag2;
 779         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 780                      vcfg->accept_tag1 ? 1 : 0);
 781         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 782                      vcfg->accept_untag1 ? 1 : 0);
 783         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 784                      vcfg->accept_tag2 ? 1 : 0);
 785         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 786                      vcfg->accept_untag2 ? 1 : 0);
 787         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 788                      vcfg->insert_tag1_en ? 1 : 0);
 789         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 790                      vcfg->insert_tag2_en ? 1 : 0);
 791         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 792
 793         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 794         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 795                      vcfg->tag_shift_mode_en ? 1 : 0);
 796
 797         /*
 798          * In current version VF is not supported when PF is driven by DPDK
 799          * driver, just need to configure parameters for PF vport.
 800          */
 801         vport_id = HNS3_PF_FUNC_ID;
 802         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 803         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 804         req->vf_bitmap[req->vf_offset] = bitmap;
 805
 806         ret = hns3_cmd_send(hw, &desc, 1);
 807         if (ret)
 808                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 809
 810         return ret;
 811 }
 812
 813 static int
 814 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 815                      uint16_t pvid)
 816 {
 817         struct hns3_hw *hw = &hns->hw;
 818         struct hns3_tx_vtag_cfg txvlan_cfg;
 819         int ret;
 820
 821         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 822                 txvlan_cfg.accept_tag1 = true;
 823                 txvlan_cfg.insert_tag1_en = false;
 824                 txvlan_cfg.default_tag1 = 0;
 825         } else {
 826                 txvlan_cfg.accept_tag1 =
 827                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 828                 txvlan_cfg.insert_tag1_en = true;
 829                 txvlan_cfg.default_tag1 = pvid;
 830         }
 831
 832         txvlan_cfg.accept_untag1 = true;
 833         txvlan_cfg.accept_tag2 = true;
 834         txvlan_cfg.accept_untag2 = true;
 835         txvlan_cfg.insert_tag2_en = false;
 836         txvlan_cfg.default_tag2 = 0;
 837         txvlan_cfg.tag_shift_mode_en = true;
 838
 839         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 840         if (ret) {
 841                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 842                          ret);
 843                 return ret;
 844         }
 845
 846         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 847         return ret;
 848 }
 849
 850
 851 static void
 852 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 853 {
 854         struct hns3_user_vlan_table *vlan_entry;
 855         struct hns3_pf *pf = &hns->pf;
 856
 857         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 858                 if (vlan_entry->hd_tbl_status) {
 859                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 860                         vlan_entry->hd_tbl_status = false;
 861                 }
 862         }
 863
 864         if (is_del_list) {
 865                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 866                 while (vlan_entry) {
 867                         LIST_REMOVE(vlan_entry, next);
 868                         rte_free(vlan_entry);
 869                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 870                 }
 871         }
 872 }
 873
 874 static void
 875 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 876 {
 877         struct hns3_user_vlan_table *vlan_entry;
 878         struct hns3_pf *pf = &hns->pf;
 879
 880         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 881                 if (!vlan_entry->hd_tbl_status) {
 882                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 883                         vlan_entry->hd_tbl_status = true;
 884                 }
 885         }
 886 }
 887
 888 static void
 889 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 890 {
 891         struct hns3_hw *hw = &hns->hw;
 892         int ret;
 893
 894         hns3_rm_all_vlan_table(hns, true);
 895         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 896                 ret = hns3_set_port_vlan_filter(hns,
 897                                                 hw->port_base_vlan_cfg.pvid, 0);
 898                 if (ret) {
 899                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 900                                  ret);
 901                         return;
 902                 }
 903         }
 904 }
 905
 906 static int
 907 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 908                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 909 {
 910         struct hns3_hw *hw = &hns->hw;
 911         uint16_t old_pvid;
 912         int ret;
 913
 914         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 915                 old_pvid = hw->port_base_vlan_cfg.pvid;
 916                 if (old_pvid != HNS3_INVALID_PVID) {
 917                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 918                         if (ret) {
 919                                 hns3_err(hw, "failed to remove old pvid %u, "
 920                                                 "ret = %d", old_pvid, ret);
 921                                 return ret;
 922                         }
 923                 }
 924
 925                 hns3_rm_all_vlan_table(hns, false);
 926                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 927                 if (ret) {
 928                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 929                                         new_pvid, ret);
 930                         return ret;
 931                 }
 932         } else {
 933                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 934                 if (ret) {
 935                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 936                                         new_pvid, ret);
 937                         return ret;
 938                 }
 939
 940                 hns3_add_all_vlan_table(hns);
 941         }
 942         return 0;
 943 }
 944
 945 static int
 946 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 947 {
 948         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 949         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 950         bool rx_strip_en;
 951         int ret;
 952
 953         rx_strip_en = old_cfg->rx_vlan_offload_en;
 954         if (on) {
 955                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 956                 rx_vlan_cfg.strip_tag2_en = true;
 957                 rx_vlan_cfg.strip_tag2_discard_en = true;
 958         } else {
 959                 rx_vlan_cfg.strip_tag1_en = false;
 960                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 961                 rx_vlan_cfg.strip_tag2_discard_en = false;
 962         }
 963         rx_vlan_cfg.strip_tag1_discard_en = false;
 964         rx_vlan_cfg.vlan1_vlan_prionly = false;
 965         rx_vlan_cfg.vlan2_vlan_prionly = false;
 966         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 967
 968         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 969         if (ret)
 970                 return ret;
 971
 972         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 973         return ret;
 974 }
 975
 976 static int
 977 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 978 {
 979         struct hns3_hw *hw = &hns->hw;
 980         uint16_t port_base_vlan_state;
 981         int ret, err;
 982
 983         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 984                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 985                         hns3_warn(hw, "Invalid operation! As current pvid set "
 986                                   "is %u, disable pvid %u is invalid",
 987                                   hw->port_base_vlan_cfg.pvid, pvid);
 988                 return 0;
 989         }
 990
 991         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 992                                     HNS3_PORT_BASE_VLAN_DISABLE;
 993         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 994         if (ret) {
 995                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 996                          ret);
 997                 return ret;
 998         }
 999
1000         ret = hns3_en_pvid_strip(hns, on);
1001         if (ret) {
1002                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1003                          "ret = %d", ret);
1004                 goto pvid_vlan_strip_fail;
1005         }
1006
1007         if (pvid == HNS3_INVALID_PVID)
1008                 goto out;
1009         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1010         if (ret) {
1011                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1012                          ret);
1013                 goto vlan_filter_set_fail;
1014         }
1015
1016 out:
1017         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1018         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1019         return ret;
1020
1021 vlan_filter_set_fail:
1022         err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1023                                         HNS3_PORT_BASE_VLAN_ENABLE);
1024         if (err)
1025                 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1026
1027 pvid_vlan_strip_fail:
1028         err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1029                                         hw->port_base_vlan_cfg.pvid);
1030         if (err)
1031                 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1032
1033         return ret;
1034 }
1035
1036 static int
1037 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1038 {
1039         struct hns3_adapter *hns = dev->data->dev_private;
1040         struct hns3_hw *hw = &hns->hw;
1041         bool pvid_en_state_change;
1042         uint16_t pvid_state;
1043         int ret;
1044
1045         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1046                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1047                          RTE_ETHER_MAX_VLAN_ID);
1048                 return -EINVAL;
1049         }
1050
1051         /*
1052          * If PVID configuration state change, should refresh the PVID
1053          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1054          */
1055         pvid_state = hw->port_base_vlan_cfg.state;
1056         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1057             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1058                 pvid_en_state_change = false;
1059         else
1060                 pvid_en_state_change = true;
1061
1062         rte_spinlock_lock(&hw->lock);
1063         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1064         rte_spinlock_unlock(&hw->lock);
1065         if (ret)
1066                 return ret;
1067         /*
1068          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1069          * need be processed by PMD driver.
1070          */
1071         if (pvid_en_state_change &&
1072             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1073                 hns3_update_all_queues_pvid_proc_en(hw);
1074
1075         return 0;
1076 }
1077
1078 static int
1079 hns3_default_vlan_config(struct hns3_adapter *hns)
1080 {
1081         struct hns3_hw *hw = &hns->hw;
1082         int ret;
1083
1084         /*
1085          * When vlan filter is enabled, hardware regards packets without vlan
1086          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1087          * table, packets without vlan won't be received. So, add vlan 0 as
1088          * the default vlan.
1089          */
1090         ret = hns3_vlan_filter_configure(hns, 0, 1);
1091         if (ret)
1092                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1093         return ret;
1094 }
1095
1096 static int
1097 hns3_init_vlan_config(struct hns3_adapter *hns)
1098 {
1099         struct hns3_hw *hw = &hns->hw;
1100         int ret;
1101
1102         /*
1103          * This function can be called in the initialization and reset process,
1104          * when in reset process, it means that hardware had been reseted
1105          * successfully and we need to restore the hardware configuration to
1106          * ensure that the hardware configuration remains unchanged before and
1107          * after reset.
1108          */
1109         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1110                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1111                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1112         }
1113
1114         ret = hns3_vlan_filter_init(hns);
1115         if (ret) {
1116                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1117                 return ret;
1118         }
1119
1120         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1121                                        RTE_ETHER_TYPE_VLAN);
1122         if (ret) {
1123                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1124                 return ret;
1125         }
1126
1127         /*
1128          * When in the reinit dev stage of the reset process, the following
1129          * vlan-related configurations may differ from those at initialization,
1130          * we will restore configurations to hardware in hns3_restore_vlan_table
1131          * and hns3_restore_vlan_conf later.
1132          */
1133         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1134                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1135                 if (ret) {
1136                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1137                         return ret;
1138                 }
1139
1140                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1141                 if (ret) {
1142                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1143                                  ret);
1144                         return ret;
1145                 }
1146         }
1147
1148         return hns3_default_vlan_config(hns);
1149 }
1150
1151 static int
1152 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1153 {
1154         struct hns3_pf *pf = &hns->pf;
1155         struct hns3_hw *hw = &hns->hw;
1156         uint64_t offloads;
1157         bool enable;
1158         int ret;
1159
1160         if (!hw->data->promiscuous) {
1161                 /* restore vlan filter states */
1162                 offloads = hw->data->dev_conf.rxmode.offloads;
1163                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1164                 ret = hns3_enable_vlan_filter(hns, enable);
1165                 if (ret) {
1166                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1167                                  "ret = %d", ret);
1168                         return ret;
1169                 }
1170         }
1171
1172         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1173         if (ret) {
1174                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1175                 return ret;
1176         }
1177
1178         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1179         if (ret)
1180                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1181
1182         return ret;
1183 }
1184
1185 static int
1186 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1187 {
1188         struct hns3_adapter *hns = dev->data->dev_private;
1189         struct rte_eth_dev_data *data = dev->data;
1190         struct rte_eth_txmode *txmode;
1191         struct hns3_hw *hw = &hns->hw;
1192         int mask;
1193         int ret;
1194
1195         txmode = &data->dev_conf.txmode;
1196         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1197                 hns3_warn(hw,
1198                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1199                           "configuration is not supported! Ignore these two "
1200                           "parameters: hw_vlan_reject_tagged(%u), "
1201                           "hw_vlan_reject_untagged(%u)",
1202                           txmode->hw_vlan_reject_tagged,
1203                           txmode->hw_vlan_reject_untagged);
1204
1205         /* Apply vlan offload setting */
1206         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1207         ret = hns3_vlan_offload_set(dev, mask);
1208         if (ret) {
1209                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1210                          ret);
1211                 return ret;
1212         }
1213
1214         /*
1215          * If pvid config is not set in rte_eth_conf, driver needn't to set
1216          * VLAN pvid related configuration to hardware.
1217          */
1218         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1219                 return 0;
1220
1221         /* Apply pvid setting */
1222         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1223                                  txmode->hw_vlan_insert_pvid);
1224         if (ret)
1225                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1226                          txmode->pvid, ret);
1227
1228         return ret;
1229 }
1230
1231 static int
1232 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1233                 unsigned int tso_mss_max)
1234 {
1235         struct hns3_cfg_tso_status_cmd *req;
1236         struct hns3_cmd_desc desc;
1237         uint16_t tso_mss;
1238
1239         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1240
1241         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1242
1243         tso_mss = 0;
1244         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1245                        tso_mss_min);
1246         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1247
1248         tso_mss = 0;
1249         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1250                        tso_mss_max);
1251         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1252
1253         return hns3_cmd_send(hw, &desc, 1);
1254 }
1255
1256 static int
1257 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1258                    uint16_t *allocated_size, bool is_alloc)
1259 {
1260         struct hns3_umv_spc_alc_cmd *req;
1261         struct hns3_cmd_desc desc;
1262         int ret;
1263
1264         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1265         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1266         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1267         req->space_size = rte_cpu_to_le_32(space_size);
1268
1269         ret = hns3_cmd_send(hw, &desc, 1);
1270         if (ret) {
1271                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1272                              is_alloc ? "allocate" : "free", ret);
1273                 return ret;
1274         }
1275
1276         if (is_alloc && allocated_size)
1277                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1278
1279         return 0;
1280 }
1281
1282 static int
1283 hns3_init_umv_space(struct hns3_hw *hw)
1284 {
1285         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1286         struct hns3_pf *pf = &hns->pf;
1287         uint16_t allocated_size = 0;
1288         int ret;
1289
1290         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1291                                  true);
1292         if (ret)
1293                 return ret;
1294
1295         if (allocated_size < pf->wanted_umv_size)
1296                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1297                              pf->wanted_umv_size, allocated_size);
1298
1299         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1300                                                 pf->wanted_umv_size;
1301         pf->used_umv_size = 0;
1302         return 0;
1303 }
1304
1305 static int
1306 hns3_uninit_umv_space(struct hns3_hw *hw)
1307 {
1308         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1309         struct hns3_pf *pf = &hns->pf;
1310         int ret;
1311
1312         if (pf->max_umv_size == 0)
1313                 return 0;
1314
1315         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1316         if (ret)
1317                 return ret;
1318
1319         pf->max_umv_size = 0;
1320
1321         return 0;
1322 }
1323
1324 static bool
1325 hns3_is_umv_space_full(struct hns3_hw *hw)
1326 {
1327         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1328         struct hns3_pf *pf = &hns->pf;
1329         bool is_full;
1330
1331         is_full = (pf->used_umv_size >= pf->max_umv_size);
1332
1333         return is_full;
1334 }
1335
1336 static void
1337 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1338 {
1339         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1340         struct hns3_pf *pf = &hns->pf;
1341
1342         if (is_free) {
1343                 if (pf->used_umv_size > 0)
1344                         pf->used_umv_size--;
1345         } else
1346                 pf->used_umv_size++;
1347 }
1348
1349 static void
1350 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1351                       const uint8_t *addr, bool is_mc)
1352 {
1353         const unsigned char *mac_addr = addr;
1354         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1355                             ((uint32_t)mac_addr[2] << 16) |
1356                             ((uint32_t)mac_addr[1] << 8) |
1357                             (uint32_t)mac_addr[0];
1358         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1359
1360         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1361         if (is_mc) {
1362                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1363                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1364                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1365         }
1366
1367         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1368         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1369 }
1370
1371 static int
1372 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1373                              uint8_t resp_code,
1374                              enum hns3_mac_vlan_tbl_opcode op)
1375 {
1376         if (cmdq_resp) {
1377                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1378                          cmdq_resp);
1379                 return -EIO;
1380         }
1381
1382         if (op == HNS3_MAC_VLAN_ADD) {
1383                 if (resp_code == 0 || resp_code == 1) {
1384                         return 0;
1385                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1386                         hns3_err(hw, "add mac addr failed for uc_overflow");
1387                         return -ENOSPC;
1388                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1389                         hns3_err(hw, "add mac addr failed for mc_overflow");
1390                         return -ENOSPC;
1391                 }
1392
1393                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1394                          resp_code);
1395                 return -EIO;
1396         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1397                 if (resp_code == 0) {
1398                         return 0;
1399                 } else if (resp_code == 1) {
1400                         hns3_dbg(hw, "remove mac addr failed for miss");
1401                         return -ENOENT;
1402                 }
1403
1404                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1405                          resp_code);
1406                 return -EIO;
1407         } else if (op == HNS3_MAC_VLAN_LKUP) {
1408                 if (resp_code == 0) {
1409                         return 0;
1410                 } else if (resp_code == 1) {
1411                         hns3_dbg(hw, "lookup mac addr failed for miss");
1412                         return -ENOENT;
1413                 }
1414
1415                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1416                          resp_code);
1417                 return -EIO;
1418         }
1419
1420         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1421                  op);
1422
1423         return -EINVAL;
1424 }
1425
1426 static int
1427 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1428                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1429                          struct hns3_cmd_desc *desc, bool is_mc)
1430 {
1431         uint8_t resp_code;
1432         uint16_t retval;
1433         int ret;
1434
1435         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1436         if (is_mc) {
1437                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1438                 memcpy(desc[0].data, req,
1439                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1440                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1441                                           true);
1442                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1443                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1444                                           true);
1445                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1446         } else {
1447                 memcpy(desc[0].data, req,
1448                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1449                 ret = hns3_cmd_send(hw, desc, 1);
1450         }
1451         if (ret) {
1452                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1453                          ret);
1454                 return ret;
1455         }
1456         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1457         retval = rte_le_to_cpu_16(desc[0].retval);
1458
1459         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1460                                             HNS3_MAC_VLAN_LKUP);
1461 }
1462
1463 static int
1464 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1465                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1466                       struct hns3_cmd_desc *mc_desc)
1467 {
1468         uint8_t resp_code;
1469         uint16_t retval;
1470         int cfg_status;
1471         int ret;
1472
1473         if (mc_desc == NULL) {
1474                 struct hns3_cmd_desc desc;
1475
1476                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1477                 memcpy(desc.data, req,
1478                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1479                 ret = hns3_cmd_send(hw, &desc, 1);
1480                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1481                 retval = rte_le_to_cpu_16(desc.retval);
1482
1483                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1484                                                           HNS3_MAC_VLAN_ADD);
1485         } else {
1486                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1487                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1488                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1489                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1490                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1491                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1492                 memcpy(mc_desc[0].data, req,
1493                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1494                 mc_desc[0].retval = 0;
1495                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1496                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1497                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1498
1499                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1500                                                           HNS3_MAC_VLAN_ADD);
1501         }
1502
1503         if (ret) {
1504                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1505                 return ret;
1506         }
1507
1508         return cfg_status;
1509 }
1510
1511 static int
1512 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1513                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1514 {
1515         struct hns3_cmd_desc desc;
1516         uint8_t resp_code;
1517         uint16_t retval;
1518         int ret;
1519
1520         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1521
1522         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1523
1524         ret = hns3_cmd_send(hw, &desc, 1);
1525         if (ret) {
1526                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1527                 return ret;
1528         }
1529         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1530         retval = rte_le_to_cpu_16(desc.retval);
1531
1532         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1533                                             HNS3_MAC_VLAN_REMOVE);
1534 }
1535
1536 static int
1537 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1538 {
1539         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1540         struct hns3_mac_vlan_tbl_entry_cmd req;
1541         struct hns3_pf *pf = &hns->pf;
1542         struct hns3_cmd_desc desc[3];
1543         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1544         uint16_t egress_port = 0;
1545         uint8_t vf_id;
1546         int ret;
1547
1548         /* check if mac addr is valid */
1549         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1550                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1551                                       mac_addr);
1552                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1553                          mac_str);
1554                 return -EINVAL;
1555         }
1556
1557         memset(&req, 0, sizeof(req));
1558
1559         /*
1560          * In current version VF is not supported when PF is driven by DPDK
1561          * driver, just need to configure parameters for PF vport.
1562          */
1563         vf_id = HNS3_PF_FUNC_ID;
1564         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1565                        HNS3_MAC_EPORT_VFID_S, vf_id);
1566
1567         req.egress_port = rte_cpu_to_le_16(egress_port);
1568
1569         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1570
1571         /*
1572          * Lookup the mac address in the mac_vlan table, and add
1573          * it if the entry is inexistent. Repeated unicast entry
1574          * is not allowed in the mac vlan table.
1575          */
1576         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1577         if (ret == -ENOENT) {
1578                 if (!hns3_is_umv_space_full(hw)) {
1579                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1580                         if (!ret)
1581                                 hns3_update_umv_space(hw, false);
1582                         return ret;
1583                 }
1584
1585                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1586
1587                 return -ENOSPC;
1588         }
1589
1590         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1591
1592         /* check if we just hit the duplicate */
1593         if (ret == 0) {
1594                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1595                 return 0;
1596         }
1597
1598         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1599                  mac_str);
1600
1601         return ret;
1602 }
1603
1604 static int
1605 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1606 {
1607         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1608         struct rte_ether_addr *addr;
1609         int ret;
1610         int i;
1611
1612         for (i = 0; i < hw->mc_addrs_num; i++) {
1613                 addr = &hw->mc_addrs[i];
1614                 /* Check if there are duplicate addresses */
1615                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1616                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1617                                               addr);
1618                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1619                                  "(%s) is added by the set_mc_mac_addr_list "
1620                                  "API", mac_str);
1621                         return -EINVAL;
1622                 }
1623         }
1624
1625         ret = hns3_add_mc_addr(hw, mac_addr);
1626         if (ret) {
1627                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1628                                       mac_addr);
1629                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1630                          mac_str, ret);
1631         }
1632         return ret;
1633 }
1634
1635 static int
1636 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1637 {
1638         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1639         int ret;
1640
1641         ret = hns3_remove_mc_addr(hw, mac_addr);
1642         if (ret) {
1643                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1644                                       mac_addr);
1645                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1646                          mac_str, ret);
1647         }
1648         return ret;
1649 }
1650
1651 static int
1652 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1653                   uint32_t idx, __rte_unused uint32_t pool)
1654 {
1655         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1656         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1657         int ret;
1658
1659         rte_spinlock_lock(&hw->lock);
1660
1661         /*
1662          * In hns3 network engine adding UC and MC mac address with different
1663          * commands with firmware. We need to determine whether the input
1664          * address is a UC or a MC address to call different commands.
1665          * By the way, it is recommended calling the API function named
1666          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1667          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1668          * may affect the specifications of UC mac addresses.
1669          */
1670         if (rte_is_multicast_ether_addr(mac_addr))
1671                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1672         else
1673                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1674
1675         if (ret) {
1676                 rte_spinlock_unlock(&hw->lock);
1677                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1678                                       mac_addr);
1679                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1680                          ret);
1681                 return ret;
1682         }
1683
1684         if (idx == 0)
1685                 hw->mac.default_addr_setted = true;
1686         rte_spinlock_unlock(&hw->lock);
1687
1688         return ret;
1689 }
1690
1691 static int
1692 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1693 {
1694         struct hns3_mac_vlan_tbl_entry_cmd req;
1695         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1696         int ret;
1697
1698         /* check if mac addr is valid */
1699         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1700                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1701                                       mac_addr);
1702                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1703                          mac_str);
1704                 return -EINVAL;
1705         }
1706
1707         memset(&req, 0, sizeof(req));
1708         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1709         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1710         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1711         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1712                 return 0;
1713         else if (ret == 0)
1714                 hns3_update_umv_space(hw, true);
1715
1716         return ret;
1717 }
1718
1719 static void
1720 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1721 {
1722         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1723         /* index will be checked by upper level rte interface */
1724         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1725         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1726         int ret;
1727
1728         rte_spinlock_lock(&hw->lock);
1729
1730         if (rte_is_multicast_ether_addr(mac_addr))
1731                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1732         else
1733                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1734         rte_spinlock_unlock(&hw->lock);
1735         if (ret) {
1736                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1737                                       mac_addr);
1738                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1739                          ret);
1740         }
1741 }
1742
1743 static int
1744 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1745                           struct rte_ether_addr *mac_addr)
1746 {
1747         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1748         struct rte_ether_addr *oaddr;
1749         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1750         bool default_addr_setted;
1751         int ret, ret_val;
1752
1753         /*
1754          * It has been guaranteed that input parameter named mac_addr is valid
1755          * address in the rte layer of DPDK framework.
1756          */
1757         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1758         default_addr_setted = hw->mac.default_addr_setted;
1759         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1760                 return 0;
1761
1762         rte_spinlock_lock(&hw->lock);
1763         if (default_addr_setted) {
1764                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1765                 if (ret) {
1766                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1767                                               oaddr);
1768                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1769                                   mac_str, ret);
1770
1771                         rte_spinlock_unlock(&hw->lock);
1772                         return ret;
1773                 }
1774         }
1775
1776         ret = hns3_add_uc_addr_common(hw, mac_addr);
1777         if (ret) {
1778                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1779                                       mac_addr);
1780                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1781                 goto err_add_uc_addr;
1782         }
1783
1784         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1785         if (ret) {
1786                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1787                 goto err_pause_addr_cfg;
1788         }
1789
1790         rte_ether_addr_copy(mac_addr,
1791                             (struct rte_ether_addr *)hw->mac.mac_addr);
1792         hw->mac.default_addr_setted = true;
1793         rte_spinlock_unlock(&hw->lock);
1794
1795         return 0;
1796
1797 err_pause_addr_cfg:
1798         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1799         if (ret_val) {
1800                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1801                                       mac_addr);
1802                 hns3_warn(hw,
1803                           "Failed to roll back to del setted mac addr(%s): %d",
1804                           mac_str, ret_val);
1805         }
1806
1807 err_add_uc_addr:
1808         ret_val = hns3_add_uc_addr_common(hw, oaddr);
1809         if (ret_val) {
1810                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, oaddr);
1811                 hns3_warn(hw, "Failed to restore old uc mac addr(%s): %d",
1812                                   mac_str, ret_val);
1813                 hw->mac.default_addr_setted = false;
1814         }
1815         rte_spinlock_unlock(&hw->lock);
1816
1817         return ret;
1818 }
1819
1820 static int
1821 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1822 {
1823         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1824         struct hns3_hw *hw = &hns->hw;
1825         struct rte_ether_addr *addr;
1826         int err = 0;
1827         int ret;
1828         int i;
1829
1830         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1831                 addr = &hw->data->mac_addrs[i];
1832                 if (rte_is_zero_ether_addr(addr))
1833                         continue;
1834                 if (rte_is_multicast_ether_addr(addr))
1835                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1836                               hns3_add_mc_addr(hw, addr);
1837                 else
1838                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1839                               hns3_add_uc_addr_common(hw, addr);
1840
1841                 if (ret) {
1842                         err = ret;
1843                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1844                                               addr);
1845                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1846                                  "ret = %d.", del ? "remove" : "restore",
1847                                  mac_str, i, ret);
1848                 }
1849         }
1850         return err;
1851 }
1852
1853 static void
1854 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1855 {
1856 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1857         uint8_t word_num;
1858         uint8_t bit_num;
1859
1860         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1861                 word_num = vfid / 32;
1862                 bit_num = vfid % 32;
1863                 if (clr)
1864                         desc[1].data[word_num] &=
1865                             rte_cpu_to_le_32(~(1UL << bit_num));
1866                 else
1867                         desc[1].data[word_num] |=
1868                             rte_cpu_to_le_32(1UL << bit_num);
1869         } else {
1870                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1871                 bit_num = vfid % 32;
1872                 if (clr)
1873                         desc[2].data[word_num] &=
1874                             rte_cpu_to_le_32(~(1UL << bit_num));
1875                 else
1876                         desc[2].data[word_num] |=
1877                             rte_cpu_to_le_32(1UL << bit_num);
1878         }
1879 }
1880
1881 static int
1882 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1883 {
1884         struct hns3_mac_vlan_tbl_entry_cmd req;
1885         struct hns3_cmd_desc desc[3];
1886         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1887         uint8_t vf_id;
1888         int ret;
1889
1890         /* Check if mac addr is valid */
1891         if (!rte_is_multicast_ether_addr(mac_addr)) {
1892                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1893                                       mac_addr);
1894                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1895                          mac_str);
1896                 return -EINVAL;
1897         }
1898
1899         memset(&req, 0, sizeof(req));
1900         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1901         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1902         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1903         if (ret) {
1904                 /* This mac addr do not exist, add new entry for it */
1905                 memset(desc[0].data, 0, sizeof(desc[0].data));
1906                 memset(desc[1].data, 0, sizeof(desc[0].data));
1907                 memset(desc[2].data, 0, sizeof(desc[0].data));
1908         }
1909
1910         /*
1911          * In current version VF is not supported when PF is driven by DPDK
1912          * driver, just need to configure parameters for PF vport.
1913          */
1914         vf_id = HNS3_PF_FUNC_ID;
1915         hns3_update_desc_vfid(desc, vf_id, false);
1916         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1917         if (ret) {
1918                 if (ret == -ENOSPC)
1919                         hns3_err(hw, "mc mac vlan table is full");
1920                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1921                                       mac_addr);
1922                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1923         }
1924
1925         return ret;
1926 }
1927
1928 static int
1929 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1930 {
1931         struct hns3_mac_vlan_tbl_entry_cmd req;
1932         struct hns3_cmd_desc desc[3];
1933         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1934         uint8_t vf_id;
1935         int ret;
1936
1937         /* Check if mac addr is valid */
1938         if (!rte_is_multicast_ether_addr(mac_addr)) {
1939                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1940                                       mac_addr);
1941                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1942                          mac_str);
1943                 return -EINVAL;
1944         }
1945
1946         memset(&req, 0, sizeof(req));
1947         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1948         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1949         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1950         if (ret == 0) {
1951                 /*
1952                  * This mac addr exist, remove this handle's VFID for it.
1953                  * In current version VF is not supported when PF is driven by
1954                  * DPDK driver, just need to configure parameters for PF vport.
1955                  */
1956                 vf_id = HNS3_PF_FUNC_ID;
1957                 hns3_update_desc_vfid(desc, vf_id, true);
1958
1959                 /* All the vfid is zero, so need to delete this entry */
1960                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1961         } else if (ret == -ENOENT) {
1962                 /* This mac addr doesn't exist. */
1963                 return 0;
1964         }
1965
1966         if (ret) {
1967                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1968                                       mac_addr);
1969                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1970         }
1971
1972         return ret;
1973 }
1974
1975 static int
1976 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1977                            struct rte_ether_addr *mc_addr_set,
1978                            uint32_t nb_mc_addr)
1979 {
1980         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1981         struct rte_ether_addr *addr;
1982         uint32_t i;
1983         uint32_t j;
1984
1985         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1986                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1987                          "invalid. valid range: 0~%d",
1988                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1989                 return -EINVAL;
1990         }
1991
1992         /* Check if input mac addresses are valid */
1993         for (i = 0; i < nb_mc_addr; i++) {
1994                 addr = &mc_addr_set[i];
1995                 if (!rte_is_multicast_ether_addr(addr)) {
1996                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1997                                               addr);
1998                         hns3_err(hw,
1999                                  "failed to set mc mac addr, addr(%s) invalid.",
2000                                  mac_str);
2001                         return -EINVAL;
2002                 }
2003
2004                 /* Check if there are duplicate addresses */
2005                 for (j = i + 1; j < nb_mc_addr; j++) {
2006                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2007                                 hns3_ether_format_addr(mac_str,
2008                                                       RTE_ETHER_ADDR_FMT_SIZE,
2009                                                       addr);
2010                                 hns3_err(hw, "failed to set mc mac addr, "
2011                                          "addrs invalid. two same addrs(%s).",
2012                                          mac_str);
2013                                 return -EINVAL;
2014                         }
2015                 }
2016
2017                 /*
2018                  * Check if there are duplicate addresses between mac_addrs
2019                  * and mc_addr_set
2020                  */
2021                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2022                         if (rte_is_same_ether_addr(addr,
2023                                                    &hw->data->mac_addrs[j])) {
2024                                 hns3_ether_format_addr(mac_str,
2025                                                       RTE_ETHER_ADDR_FMT_SIZE,
2026                                                       addr);
2027                                 hns3_err(hw, "failed to set mc mac addr, "
2028                                          "addrs invalid. addrs(%s) has already "
2029                                          "configured in mac_addr add API",
2030                                          mac_str);
2031                                 return -EINVAL;
2032                         }
2033                 }
2034         }
2035
2036         return 0;
2037 }
2038
2039 static void
2040 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2041                            struct rte_ether_addr *mc_addr_set,
2042                            int mc_addr_num,
2043                            struct rte_ether_addr *reserved_addr_list,
2044                            int *reserved_addr_num,
2045                            struct rte_ether_addr *add_addr_list,
2046                            int *add_addr_num,
2047                            struct rte_ether_addr *rm_addr_list,
2048                            int *rm_addr_num)
2049 {
2050         struct rte_ether_addr *addr;
2051         int current_addr_num;
2052         int reserved_num = 0;
2053         int add_num = 0;
2054         int rm_num = 0;
2055         int num;
2056         int i;
2057         int j;
2058         bool same_addr;
2059
2060         /* Calculate the mc mac address list that should be removed */
2061         current_addr_num = hw->mc_addrs_num;
2062         for (i = 0; i < current_addr_num; i++) {
2063                 addr = &hw->mc_addrs[i];
2064                 same_addr = false;
2065                 for (j = 0; j < mc_addr_num; j++) {
2066                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2067                                 same_addr = true;
2068                                 break;
2069                         }
2070                 }
2071
2072                 if (!same_addr) {
2073                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2074                         rm_num++;
2075                 } else {
2076                         rte_ether_addr_copy(addr,
2077                                             &reserved_addr_list[reserved_num]);
2078                         reserved_num++;
2079                 }
2080         }
2081
2082         /* Calculate the mc mac address list that should be added */
2083         for (i = 0; i < mc_addr_num; i++) {
2084                 addr = &mc_addr_set[i];
2085                 same_addr = false;
2086                 for (j = 0; j < current_addr_num; j++) {
2087                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2088                                 same_addr = true;
2089                                 break;
2090                         }
2091                 }
2092
2093                 if (!same_addr) {
2094                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2095                         add_num++;
2096                 }
2097         }
2098
2099         /* Reorder the mc mac address list maintained by driver */
2100         for (i = 0; i < reserved_num; i++)
2101                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2102
2103         for (i = 0; i < rm_num; i++) {
2104                 num = reserved_num + i;
2105                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2106         }
2107
2108         *reserved_addr_num = reserved_num;
2109         *add_addr_num = add_num;
2110         *rm_addr_num = rm_num;
2111 }
2112
2113 static int
2114 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2115                           struct rte_ether_addr *mc_addr_set,
2116                           uint32_t nb_mc_addr)
2117 {
2118         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2119         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2120         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2121         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2122         struct rte_ether_addr *addr;
2123         int reserved_addr_num;
2124         int add_addr_num;
2125         int rm_addr_num;
2126         int mc_addr_num;
2127         int num;
2128         int ret;
2129         int i;
2130
2131         /* Check if input parameters are valid */
2132         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2133         if (ret)
2134                 return ret;
2135
2136         rte_spinlock_lock(&hw->lock);
2137
2138         /*
2139          * Calculate the mc mac address lists those should be removed and be
2140          * added, Reorder the mc mac address list maintained by driver.
2141          */
2142         mc_addr_num = (int)nb_mc_addr;
2143         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2144                                    reserved_addr_list, &reserved_addr_num,
2145                                    add_addr_list, &add_addr_num,
2146                                    rm_addr_list, &rm_addr_num);
2147
2148         /* Remove mc mac addresses */
2149         for (i = 0; i < rm_addr_num; i++) {
2150                 num = rm_addr_num - i - 1;
2151                 addr = &rm_addr_list[num];
2152                 ret = hns3_remove_mc_addr(hw, addr);
2153                 if (ret) {
2154                         rte_spinlock_unlock(&hw->lock);
2155                         return ret;
2156                 }
2157                 hw->mc_addrs_num--;
2158         }
2159
2160         /* Add mc mac addresses */
2161         for (i = 0; i < add_addr_num; i++) {
2162                 addr = &add_addr_list[i];
2163                 ret = hns3_add_mc_addr(hw, addr);
2164                 if (ret) {
2165                         rte_spinlock_unlock(&hw->lock);
2166                         return ret;
2167                 }
2168
2169                 num = reserved_addr_num + i;
2170                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2171                 hw->mc_addrs_num++;
2172         }
2173         rte_spinlock_unlock(&hw->lock);
2174
2175         return 0;
2176 }
2177
2178 static int
2179 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2180 {
2181         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2182         struct hns3_hw *hw = &hns->hw;
2183         struct rte_ether_addr *addr;
2184         int err = 0;
2185         int ret;
2186         int i;
2187
2188         for (i = 0; i < hw->mc_addrs_num; i++) {
2189                 addr = &hw->mc_addrs[i];
2190                 if (!rte_is_multicast_ether_addr(addr))
2191                         continue;
2192                 if (del)
2193                         ret = hns3_remove_mc_addr(hw, addr);
2194                 else
2195                         ret = hns3_add_mc_addr(hw, addr);
2196                 if (ret) {
2197                         err = ret;
2198                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2199                                               addr);
2200                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2201                                  del ? "Remove" : "Restore", mac_str, ret);
2202                 }
2203         }
2204         return err;
2205 }
2206
2207 static int
2208 hns3_check_mq_mode(struct rte_eth_dev *dev)
2209 {
2210         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2211         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2212         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2213         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2214         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2215         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2216         uint8_t num_tc;
2217         int max_tc = 0;
2218         int i;
2219
2220         if ((rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG) ||
2221             (tx_mq_mode == ETH_MQ_TX_VMDQ_DCB ||
2222              tx_mq_mode == ETH_MQ_TX_VMDQ_ONLY)) {
2223                 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
2224                          rx_mq_mode, tx_mq_mode);
2225                 return -EOPNOTSUPP;
2226         }
2227
2228         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2229         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2230         if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
2231                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2232                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2233                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2234                         return -EINVAL;
2235                 }
2236
2237                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2238                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2239                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2240                                  "nb_tcs(%d) != %d or %d in rx direction.",
2241                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2242                         return -EINVAL;
2243                 }
2244
2245                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2246                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2247                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2248                         return -EINVAL;
2249                 }
2250
2251                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2252                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2253                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2254                                          "is not equal to one in tx direction.",
2255                                          i, dcb_rx_conf->dcb_tc[i]);
2256                                 return -EINVAL;
2257                         }
2258                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2259                                 max_tc = dcb_rx_conf->dcb_tc[i];
2260                 }
2261
2262                 num_tc = max_tc + 1;
2263                 if (num_tc > dcb_rx_conf->nb_tcs) {
2264                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2265                                  num_tc, dcb_rx_conf->nb_tcs);
2266                         return -EINVAL;
2267                 }
2268         }
2269
2270         return 0;
2271 }
2272
2273 static int
2274 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2275                            enum hns3_ring_type queue_type, uint16_t queue_id)
2276 {
2277         struct hns3_cmd_desc desc;
2278         struct hns3_ctrl_vector_chain_cmd *req =
2279                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2280         enum hns3_opcode_type op;
2281         uint16_t tqp_type_and_id = 0;
2282         uint16_t type;
2283         uint16_t gl;
2284         int ret;
2285
2286         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2287         hns3_cmd_setup_basic_desc(&desc, op, false);
2288         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2289                                               HNS3_TQP_INT_ID_L_S);
2290         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2291                                               HNS3_TQP_INT_ID_H_S);
2292
2293         if (queue_type == HNS3_RING_TYPE_RX)
2294                 gl = HNS3_RING_GL_RX;
2295         else
2296                 gl = HNS3_RING_GL_TX;
2297
2298         type = queue_type;
2299
2300         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2301                        type);
2302         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2303         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2304                        gl);
2305         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2306         req->int_cause_num = 1;
2307         ret = hns3_cmd_send(hw, &desc, 1);
2308         if (ret) {
2309                 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2310                          en ? "Map" : "Unmap", queue_id, vector_id, ret);
2311                 return ret;
2312         }
2313
2314         return 0;
2315 }
2316
2317 static int
2318 hns3_init_ring_with_vector(struct hns3_hw *hw)
2319 {
2320         uint16_t vec;
2321         int ret;
2322         int i;
2323
2324         /*
2325          * In hns3 network engine, vector 0 is always the misc interrupt of this
2326          * function, vector 1~N can be used respectively for the queues of the
2327          * function. Tx and Rx queues with the same number share the interrupt
2328          * vector. In the initialization clearing the all hardware mapping
2329          * relationship configurations between queues and interrupt vectors is
2330          * needed, so some error caused by the residual configurations, such as
2331          * the unexpected Tx interrupt, can be avoid.
2332          */
2333         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2334         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2335                 vec = vec - 1; /* the last interrupt is reserved */
2336         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2337         for (i = 0; i < hw->intr_tqps_num; i++) {
2338                 /*
2339                  * Set gap limiter/rate limiter/quanity limiter algorithm
2340                  * configuration for interrupt coalesce of queue's interrupt.
2341                  */
2342                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2343                                        HNS3_TQP_INTR_GL_DEFAULT);
2344                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2345                                        HNS3_TQP_INTR_GL_DEFAULT);
2346                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2347                 /*
2348                  * QL(quantity limiter) is not used currently, just set 0 to
2349                  * close it.
2350                  */
2351                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2352
2353                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2354                                                  HNS3_RING_TYPE_TX, i);
2355                 if (ret) {
2356                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2357                                           "vector: %u, ret=%d", i, vec, ret);
2358                         return ret;
2359                 }
2360
2361                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2362                                                  HNS3_RING_TYPE_RX, i);
2363                 if (ret) {
2364                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2365                                           "vector: %u, ret=%d", i, vec, ret);
2366                         return ret;
2367                 }
2368         }
2369
2370         return 0;
2371 }
2372
2373 static int
2374 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2375 {
2376         struct hns3_adapter *hns = dev->data->dev_private;
2377         struct hns3_hw *hw = &hns->hw;
2378         uint32_t max_rx_pkt_len;
2379         uint16_t mtu;
2380         int ret;
2381
2382         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2383                 return 0;
2384
2385         /*
2386          * If jumbo frames are enabled, MTU needs to be refreshed
2387          * according to the maximum RX packet length.
2388          */
2389         max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2390         if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2391             max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2392                 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2393                          "and no more than %u when jumbo frame enabled.",
2394                          (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2395                          (uint16_t)HNS3_MAX_FRAME_LEN);
2396                 return -EINVAL;
2397         }
2398
2399         mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2400         ret = hns3_dev_mtu_set(dev, mtu);
2401         if (ret)
2402                 return ret;
2403         dev->data->mtu = mtu;
2404
2405         return 0;
2406 }
2407
2408 static int
2409 hns3_setup_dcb(struct rte_eth_dev *dev)
2410 {
2411         struct hns3_adapter *hns = dev->data->dev_private;
2412         struct hns3_hw *hw = &hns->hw;
2413         int ret;
2414
2415         if (!hns3_dev_dcb_supported(hw)) {
2416                 hns3_err(hw, "this port does not support dcb configurations.");
2417                 return -EOPNOTSUPP;
2418         }
2419
2420         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2421                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2422                 return -EOPNOTSUPP;
2423         }
2424
2425         ret = hns3_dcb_configure(hns);
2426         if (ret)
2427                 hns3_err(hw, "failed to config dcb: %d", ret);
2428
2429         return ret;
2430 }
2431
2432 static int
2433 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
2434 {
2435         int ret;
2436
2437         /*
2438          * Some hardware doesn't support auto-negotiation, but users may not
2439          * configure link_speeds (default 0), which means auto-negotiation.
2440          * In this case, a warning message need to be printed, instead of
2441          * an error.
2442          */
2443         if (link_speeds == ETH_LINK_SPEED_AUTONEG &&
2444             hw->mac.support_autoneg == 0) {
2445                 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
2446                 return 0;
2447         }
2448
2449         if (link_speeds != ETH_LINK_SPEED_AUTONEG) {
2450                 ret = hns3_check_port_speed(hw, link_speeds);
2451                 if (ret)
2452                         return ret;
2453         }
2454
2455         return 0;
2456 }
2457
2458 static int
2459 hns3_check_dev_conf(struct rte_eth_dev *dev)
2460 {
2461         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2462         struct rte_eth_conf *conf = &dev->data->dev_conf;
2463         int ret;
2464
2465         ret = hns3_check_mq_mode(dev);
2466         if (ret)
2467                 return ret;
2468
2469         return hns3_check_link_speed(hw, conf->link_speeds);
2470 }
2471
2472 static int
2473 hns3_dev_configure(struct rte_eth_dev *dev)
2474 {
2475         struct hns3_adapter *hns = dev->data->dev_private;
2476         struct rte_eth_conf *conf = &dev->data->dev_conf;
2477         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2478         struct hns3_hw *hw = &hns->hw;
2479         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2480         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2481         struct rte_eth_rss_conf rss_conf;
2482         bool gro_en;
2483         int ret;
2484
2485         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2486
2487         /*
2488          * Some versions of hardware network engine does not support
2489          * individually enable/disable/reset the Tx or Rx queue. These devices
2490          * must enable/disable/reset Tx and Rx queues at the same time. When the
2491          * numbers of Tx queues allocated by upper applications are not equal to
2492          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2493          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2494          * work as usual. But these fake queues are imperceptible, and can not
2495          * be used by upper applications.
2496          */
2497         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2498         if (ret) {
2499                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
2500                 hw->cfg_max_queues = 0;
2501                 return ret;
2502         }
2503
2504         hw->adapter_state = HNS3_NIC_CONFIGURING;
2505         ret = hns3_check_dev_conf(dev);
2506         if (ret)
2507                 goto cfg_err;
2508
2509         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2510                 ret = hns3_setup_dcb(dev);
2511                 if (ret)
2512                         goto cfg_err;
2513         }
2514
2515         /* When RSS is not configured, redirect the packet queue 0 */
2516         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2517                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2518                 rss_conf = conf->rx_adv_conf.rss_conf;
2519                 hw->rss_dis_flag = false;
2520                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2521                 if (ret)
2522                         goto cfg_err;
2523         }
2524
2525         ret = hns3_refresh_mtu(dev, conf);
2526         if (ret)
2527                 goto cfg_err;
2528
2529         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2530         if (ret)
2531                 goto cfg_err;
2532
2533         ret = hns3_dev_configure_vlan(dev);
2534         if (ret)
2535                 goto cfg_err;
2536
2537         /* config hardware GRO */
2538         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2539         ret = hns3_config_gro(hw, gro_en);
2540         if (ret)
2541                 goto cfg_err;
2542
2543         hns3_init_rx_ptype_tble(dev);
2544         hw->adapter_state = HNS3_NIC_CONFIGURED;
2545
2546         return 0;
2547
2548 cfg_err:
2549         hw->cfg_max_queues = 0;
2550         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2551         hw->adapter_state = HNS3_NIC_INITIALIZED;
2552
2553         return ret;
2554 }
2555
2556 static int
2557 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2558 {
2559         struct hns3_config_max_frm_size_cmd *req;
2560         struct hns3_cmd_desc desc;
2561
2562         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2563
2564         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2565         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2566         req->min_frm_size = RTE_ETHER_MIN_LEN;
2567
2568         return hns3_cmd_send(hw, &desc, 1);
2569 }
2570
2571 static int
2572 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2573 {
2574         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2575         uint16_t original_mps = hns->pf.mps;
2576         int err;
2577         int ret;
2578
2579         ret = hns3_set_mac_mtu(hw, mps);
2580         if (ret) {
2581                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2582                 return ret;
2583         }
2584
2585         hns->pf.mps = mps;
2586         ret = hns3_buffer_alloc(hw);
2587         if (ret) {
2588                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2589                 goto rollback;
2590         }
2591
2592         return 0;
2593
2594 rollback:
2595         err = hns3_set_mac_mtu(hw, original_mps);
2596         if (err) {
2597                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2598                 return ret;
2599         }
2600         hns->pf.mps = original_mps;
2601
2602         return ret;
2603 }
2604
2605 static int
2606 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2607 {
2608         struct hns3_adapter *hns = dev->data->dev_private;
2609         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2610         struct hns3_hw *hw = &hns->hw;
2611         bool is_jumbo_frame;
2612         int ret;
2613
2614         if (dev->data->dev_started) {
2615                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2616                          "before configuration", dev->data->port_id);
2617                 return -EBUSY;
2618         }
2619
2620         rte_spinlock_lock(&hw->lock);
2621         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2622         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2623
2624         /*
2625          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2626          * assign to "uint16_t" type variable.
2627          */
2628         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2629         if (ret) {
2630                 rte_spinlock_unlock(&hw->lock);
2631                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2632                          dev->data->port_id, mtu, ret);
2633                 return ret;
2634         }
2635
2636         if (is_jumbo_frame)
2637                 dev->data->dev_conf.rxmode.offloads |=
2638                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2639         else
2640                 dev->data->dev_conf.rxmode.offloads &=
2641                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2642         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2643         rte_spinlock_unlock(&hw->lock);
2644
2645         return 0;
2646 }
2647
2648 static uint32_t
2649 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2650 {
2651         uint32_t speed_capa = 0;
2652
2653         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2654                 speed_capa |= ETH_LINK_SPEED_10M_HD;
2655         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2656                 speed_capa |= ETH_LINK_SPEED_10M;
2657         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2658                 speed_capa |= ETH_LINK_SPEED_100M_HD;
2659         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2660                 speed_capa |= ETH_LINK_SPEED_100M;
2661         if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2662                 speed_capa |= ETH_LINK_SPEED_1G;
2663
2664         return speed_capa;
2665 }
2666
2667 static uint32_t
2668 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2669 {
2670         uint32_t speed_capa = 0;
2671
2672         if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2673                 speed_capa |= ETH_LINK_SPEED_1G;
2674         if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2675                 speed_capa |= ETH_LINK_SPEED_10G;
2676         if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2677                 speed_capa |= ETH_LINK_SPEED_25G;
2678         if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2679                 speed_capa |= ETH_LINK_SPEED_40G;
2680         if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2681                 speed_capa |= ETH_LINK_SPEED_50G;
2682         if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2683                 speed_capa |= ETH_LINK_SPEED_100G;
2684         if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2685                 speed_capa |= ETH_LINK_SPEED_200G;
2686
2687         return speed_capa;
2688 }
2689
2690 static uint32_t
2691 hns3_get_speed_capa(struct hns3_hw *hw)
2692 {
2693         struct hns3_mac *mac = &hw->mac;
2694         uint32_t speed_capa;
2695
2696         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2697                 speed_capa =
2698                         hns3_get_copper_port_speed_capa(mac->supported_speed);
2699         else
2700                 speed_capa =
2701                         hns3_get_firber_port_speed_capa(mac->supported_speed);
2702
2703         if (mac->support_autoneg == 0)
2704                 speed_capa |= ETH_LINK_SPEED_FIXED;
2705
2706         return speed_capa;
2707 }
2708
2709 int
2710 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2711 {
2712         struct hns3_adapter *hns = eth_dev->data->dev_private;
2713         struct hns3_hw *hw = &hns->hw;
2714         uint16_t queue_num = hw->tqps_num;
2715
2716         /*
2717          * In interrupt mode, 'max_rx_queues' is set based on the number of
2718          * MSI-X interrupt resources of the hardware.
2719          */
2720         if (hw->data->dev_conf.intr_conf.rxq == 1)
2721                 queue_num = hw->intr_tqps_num;
2722
2723         info->max_rx_queues = queue_num;
2724         info->max_tx_queues = hw->tqps_num;
2725         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2726         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2727         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2728         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2729         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2730         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2731                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2732                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2733                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2734                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2735                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2736                                  DEV_RX_OFFLOAD_KEEP_CRC |
2737                                  DEV_RX_OFFLOAD_SCATTER |
2738                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2739                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2740                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2741                                  DEV_RX_OFFLOAD_RSS_HASH |
2742                                  DEV_RX_OFFLOAD_TCP_LRO);
2743         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2744                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2745                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2746                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2747                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2748                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2749                                  DEV_TX_OFFLOAD_TCP_TSO |
2750                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2751                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2752                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2753                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2754                                  hns3_txvlan_cap_get(hw));
2755
2756         if (hns3_dev_outer_udp_cksum_supported(hw))
2757                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2758
2759         if (hns3_dev_indep_txrx_supported(hw))
2760                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2761                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2762
2763         if (hns3_dev_ptp_supported(hw))
2764                 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2765
2766         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2767                 .nb_max = HNS3_MAX_RING_DESC,
2768                 .nb_min = HNS3_MIN_RING_DESC,
2769                 .nb_align = HNS3_ALIGN_RING_DESC,
2770         };
2771
2772         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2773                 .nb_max = HNS3_MAX_RING_DESC,
2774                 .nb_min = HNS3_MIN_RING_DESC,
2775                 .nb_align = HNS3_ALIGN_RING_DESC,
2776                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2777                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2778         };
2779
2780         info->speed_capa = hns3_get_speed_capa(hw);
2781         info->default_rxconf = (struct rte_eth_rxconf) {
2782                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2783                 /*
2784                  * If there are no available Rx buffer descriptors, incoming
2785                  * packets are always dropped by hardware based on hns3 network
2786                  * engine.
2787                  */
2788                 .rx_drop_en = 1,
2789                 .offloads = 0,
2790         };
2791         info->default_txconf = (struct rte_eth_txconf) {
2792                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2793                 .offloads = 0,
2794         };
2795
2796         info->reta_size = hw->rss_ind_tbl_size;
2797         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2798         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2799
2800         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2801         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2802         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2803         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2804         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2805         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2806
2807         return 0;
2808 }
2809
2810 static int
2811 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2812                     size_t fw_size)
2813 {
2814         struct hns3_adapter *hns = eth_dev->data->dev_private;
2815         struct hns3_hw *hw = &hns->hw;
2816         uint32_t version = hw->fw_version;
2817         int ret;
2818
2819         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2820                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2821                                       HNS3_FW_VERSION_BYTE3_S),
2822                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2823                                       HNS3_FW_VERSION_BYTE2_S),
2824                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2825                                       HNS3_FW_VERSION_BYTE1_S),
2826                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2827                                       HNS3_FW_VERSION_BYTE0_S));
2828         if (ret < 0)
2829                 return -EINVAL;
2830
2831         ret += 1; /* add the size of '\0' */
2832         if (fw_size < (size_t)ret)
2833                 return ret;
2834         else
2835                 return 0;
2836 }
2837
2838 static int
2839 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2840 {
2841         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2842         int ret;
2843
2844         (void)hns3_update_link_status(hw);
2845
2846         ret = hns3_update_link_info(eth_dev);
2847         if (ret)
2848                 hw->mac.link_status = ETH_LINK_DOWN;
2849
2850         return ret;
2851 }
2852
2853 static void
2854 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2855                       struct rte_eth_link *new_link)
2856 {
2857         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2858         struct hns3_mac *mac = &hw->mac;
2859
2860         switch (mac->link_speed) {
2861         case ETH_SPEED_NUM_10M:
2862         case ETH_SPEED_NUM_100M:
2863         case ETH_SPEED_NUM_1G:
2864         case ETH_SPEED_NUM_10G:
2865         case ETH_SPEED_NUM_25G:
2866         case ETH_SPEED_NUM_40G:
2867         case ETH_SPEED_NUM_50G:
2868         case ETH_SPEED_NUM_100G:
2869         case ETH_SPEED_NUM_200G:
2870                 if (mac->link_status)
2871                         new_link->link_speed = mac->link_speed;
2872                 break;
2873         default:
2874                 if (mac->link_status)
2875                         new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2876                 break;
2877         }
2878
2879         if (!mac->link_status)
2880                 new_link->link_speed = ETH_SPEED_NUM_NONE;
2881
2882         new_link->link_duplex = mac->link_duplex;
2883         new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2884         new_link->link_autoneg = mac->link_autoneg;
2885 }
2886
2887 static int
2888 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2889 {
2890 #define HNS3_LINK_CHECK_INTERVAL 100  /* 100ms */
2891 #define HNS3_MAX_LINK_CHECK_TIMES 20  /* 2s (100 * 20ms) in total */
2892
2893         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2894         uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2895         struct hns3_mac *mac = &hw->mac;
2896         struct rte_eth_link new_link;
2897         int ret;
2898
2899         /* When port is stopped, report link down. */
2900         if (eth_dev->data->dev_started == 0) {
2901                 new_link.link_autoneg = mac->link_autoneg;
2902                 new_link.link_duplex = mac->link_duplex;
2903                 new_link.link_speed = ETH_SPEED_NUM_NONE;
2904                 new_link.link_status = ETH_LINK_DOWN;
2905                 goto out;
2906         }
2907
2908         do {
2909                 ret = hns3_update_port_link_info(eth_dev);
2910                 if (ret) {
2911                         hns3_err(hw, "failed to get port link info, ret = %d.",
2912                                  ret);
2913                         break;
2914                 }
2915
2916                 if (!wait_to_complete || mac->link_status == ETH_LINK_UP)
2917                         break;
2918
2919                 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2920         } while (retry_cnt--);
2921
2922         memset(&new_link, 0, sizeof(new_link));
2923         hns3_setup_linkstatus(eth_dev, &new_link);
2924
2925 out:
2926         return rte_eth_linkstatus_set(eth_dev, &new_link);
2927 }
2928
2929 static int
2930 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2931 {
2932         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2933         struct hns3_pf *pf = &hns->pf;
2934
2935         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2936                 return -EINVAL;
2937
2938         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2939
2940         return 0;
2941 }
2942
2943 static int
2944 hns3_query_function_status(struct hns3_hw *hw)
2945 {
2946 #define HNS3_QUERY_MAX_CNT              10
2947 #define HNS3_QUERY_SLEEP_MSCOEND        1
2948         struct hns3_func_status_cmd *req;
2949         struct hns3_cmd_desc desc;
2950         int timeout = 0;
2951         int ret;
2952
2953         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2954         req = (struct hns3_func_status_cmd *)desc.data;
2955
2956         do {
2957                 ret = hns3_cmd_send(hw, &desc, 1);
2958                 if (ret) {
2959                         PMD_INIT_LOG(ERR, "query function status failed %d",
2960                                      ret);
2961                         return ret;
2962                 }
2963
2964                 /* Check pf reset is done */
2965                 if (req->pf_state)
2966                         break;
2967
2968                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2969         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2970
2971         return hns3_parse_func_status(hw, req);
2972 }
2973
2974 static int
2975 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2976 {
2977         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2978         struct hns3_pf *pf = &hns->pf;
2979
2980         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2981                 /*
2982                  * The total_tqps_num obtained from firmware is maximum tqp
2983                  * numbers of this port, which should be used for PF and VFs.
2984                  * There is no need for pf to have so many tqp numbers in
2985                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2986                  * coming from config file, is assigned to maximum queue number
2987                  * for the PF of this port by user. So users can modify the
2988                  * maximum queue number of PF according to their own application
2989                  * scenarios, which is more flexible to use. In addition, many
2990                  * memories can be saved due to allocating queue statistics
2991                  * room according to the actual number of queues required. The
2992                  * maximum queue number of PF for network engine with
2993                  * revision_id greater than 0x30 is assigned by config file.
2994                  */
2995                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2996                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2997                                  "must be greater than 0.",
2998                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2999                         return -EINVAL;
3000                 }
3001
3002                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
3003                                        hw->total_tqps_num);
3004         } else {
3005                 /*
3006                  * Due to the limitation on the number of PF interrupts
3007                  * available, the maximum queue number assigned to PF on
3008                  * the network engine with revision_id 0x21 is 64.
3009                  */
3010                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
3011                                        HNS3_MAX_TQP_NUM_HIP08_PF);
3012         }
3013
3014         return 0;
3015 }
3016
3017 static int
3018 hns3_query_pf_resource(struct hns3_hw *hw)
3019 {
3020         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3021         struct hns3_pf *pf = &hns->pf;
3022         struct hns3_pf_res_cmd *req;
3023         struct hns3_cmd_desc desc;
3024         int ret;
3025
3026         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
3027         ret = hns3_cmd_send(hw, &desc, 1);
3028         if (ret) {
3029                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
3030                 return ret;
3031         }
3032
3033         req = (struct hns3_pf_res_cmd *)desc.data;
3034         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
3035                              rte_le_to_cpu_16(req->ext_tqp_num);
3036         ret = hns3_get_pf_max_tqp_num(hw);
3037         if (ret)
3038                 return ret;
3039
3040         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
3041         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
3042
3043         if (req->tx_buf_size)
3044                 pf->tx_buf_size =
3045                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
3046         else
3047                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
3048
3049         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
3050
3051         if (req->dv_buf_size)
3052                 pf->dv_buf_size =
3053                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3054         else
3055                 pf->dv_buf_size = HNS3_DEFAULT_DV;
3056
3057         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3058
3059         hw->num_msi =
3060                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3061                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3062
3063         return 0;
3064 }
3065
3066 static void
3067 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3068 {
3069         struct hns3_cfg_param_cmd *req;
3070         uint64_t mac_addr_tmp_high;
3071         uint8_t ext_rss_size_max;
3072         uint64_t mac_addr_tmp;
3073         uint32_t i;
3074
3075         req = (struct hns3_cfg_param_cmd *)desc[0].data;
3076
3077         /* get the configuration */
3078         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3079                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3080         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3081                                            HNS3_CFG_TQP_DESC_N_M,
3082                                            HNS3_CFG_TQP_DESC_N_S);
3083
3084         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3085                                        HNS3_CFG_PHY_ADDR_M,
3086                                        HNS3_CFG_PHY_ADDR_S);
3087         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3088                                          HNS3_CFG_MEDIA_TP_M,
3089                                          HNS3_CFG_MEDIA_TP_S);
3090         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3091                                          HNS3_CFG_RX_BUF_LEN_M,
3092                                          HNS3_CFG_RX_BUF_LEN_S);
3093         /* get mac address */
3094         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3095         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3096                                            HNS3_CFG_MAC_ADDR_H_M,
3097                                            HNS3_CFG_MAC_ADDR_H_S);
3098
3099         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3100
3101         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3102                                             HNS3_CFG_DEFAULT_SPEED_M,
3103                                             HNS3_CFG_DEFAULT_SPEED_S);
3104         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3105                                            HNS3_CFG_RSS_SIZE_M,
3106                                            HNS3_CFG_RSS_SIZE_S);
3107
3108         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3109                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3110
3111         req = (struct hns3_cfg_param_cmd *)desc[1].data;
3112         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3113
3114         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3115                                             HNS3_CFG_SPEED_ABILITY_M,
3116                                             HNS3_CFG_SPEED_ABILITY_S);
3117         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3118                                         HNS3_CFG_UMV_TBL_SPACE_M,
3119                                         HNS3_CFG_UMV_TBL_SPACE_S);
3120         if (!cfg->umv_space)
3121                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3122
3123         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3124                                                HNS3_CFG_EXT_RSS_SIZE_M,
3125                                                HNS3_CFG_EXT_RSS_SIZE_S);
3126         /*
3127          * Field ext_rss_size_max obtained from firmware will be more flexible
3128          * for future changes and expansions, which is an exponent of 2, instead
3129          * of reading out directly. If this field is not zero, hns3 PF PMD
3130          * driver uses it as rss_size_max under one TC. Device, whose revision
3131          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3132          * maximum number of queues supported under a TC through this field.
3133          */
3134         if (ext_rss_size_max)
3135                 cfg->rss_size_max = 1U << ext_rss_size_max;
3136 }
3137
3138 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3139  * @hw: pointer to struct hns3_hw
3140  * @hcfg: the config structure to be getted
3141  */
3142 static int
3143 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3144 {
3145         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3146         struct hns3_cfg_param_cmd *req;
3147         uint32_t offset;
3148         uint32_t i;
3149         int ret;
3150
3151         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3152                 offset = 0;
3153                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3154                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3155                                           true);
3156                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3157                                i * HNS3_CFG_RD_LEN_BYTES);
3158                 /* Len should be divided by 4 when send to hardware */
3159                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3160                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3161                 req->offset = rte_cpu_to_le_32(offset);
3162         }
3163
3164         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3165         if (ret) {
3166                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3167                 return ret;
3168         }
3169
3170         hns3_parse_cfg(hcfg, desc);
3171
3172         return 0;
3173 }
3174
3175 static int
3176 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3177 {
3178         switch (speed_cmd) {
3179         case HNS3_CFG_SPEED_10M:
3180                 *speed = ETH_SPEED_NUM_10M;
3181                 break;
3182         case HNS3_CFG_SPEED_100M:
3183                 *speed = ETH_SPEED_NUM_100M;
3184                 break;
3185         case HNS3_CFG_SPEED_1G:
3186                 *speed = ETH_SPEED_NUM_1G;
3187                 break;
3188         case HNS3_CFG_SPEED_10G:
3189                 *speed = ETH_SPEED_NUM_10G;
3190                 break;
3191         case HNS3_CFG_SPEED_25G:
3192                 *speed = ETH_SPEED_NUM_25G;
3193                 break;
3194         case HNS3_CFG_SPEED_40G:
3195                 *speed = ETH_SPEED_NUM_40G;
3196                 break;
3197         case HNS3_CFG_SPEED_50G:
3198                 *speed = ETH_SPEED_NUM_50G;
3199                 break;
3200         case HNS3_CFG_SPEED_100G:
3201                 *speed = ETH_SPEED_NUM_100G;
3202                 break;
3203         case HNS3_CFG_SPEED_200G:
3204                 *speed = ETH_SPEED_NUM_200G;
3205                 break;
3206         default:
3207                 return -EINVAL;
3208         }
3209
3210         return 0;
3211 }
3212
3213 static void
3214 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3215 {
3216         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3217         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3218         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3219         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3220         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3221 }
3222
3223 static void
3224 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3225 {
3226         struct hns3_dev_specs_0_cmd *req0;
3227
3228         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3229
3230         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3231         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3232         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3233         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3234         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3235 }
3236
3237 static int
3238 hns3_check_dev_specifications(struct hns3_hw *hw)
3239 {
3240         if (hw->rss_ind_tbl_size == 0 ||
3241             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3242                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3243                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3244                               HNS3_RSS_IND_TBL_SIZE_MAX);
3245                 return -EINVAL;
3246         }
3247
3248         return 0;
3249 }
3250
3251 static int
3252 hns3_query_dev_specifications(struct hns3_hw *hw)
3253 {
3254         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3255         int ret;
3256         int i;
3257
3258         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3259                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3260                                           true);
3261                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3262         }
3263         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3264
3265         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3266         if (ret)
3267                 return ret;
3268
3269         hns3_parse_dev_specifications(hw, desc);
3270
3271         return hns3_check_dev_specifications(hw);
3272 }
3273
3274 static int
3275 hns3_get_capability(struct hns3_hw *hw)
3276 {
3277         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3278         struct rte_pci_device *pci_dev;
3279         struct hns3_pf *pf = &hns->pf;
3280         struct rte_eth_dev *eth_dev;
3281         uint16_t device_id;
3282         uint8_t revision;
3283         int ret;
3284
3285         eth_dev = &rte_eth_devices[hw->data->port_id];
3286         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3287         device_id = pci_dev->id.device_id;
3288
3289         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3290             device_id == HNS3_DEV_ID_50GE_RDMA ||
3291             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3292             device_id == HNS3_DEV_ID_200G_RDMA)
3293                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3294
3295         /* Get PCI revision id */
3296         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3297                                   HNS3_PCI_REVISION_ID);
3298         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3299                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3300                              ret);
3301                 return -EIO;
3302         }
3303         hw->revision = revision;
3304
3305         if (revision < PCI_REVISION_ID_HIP09_A) {
3306                 hns3_set_default_dev_specifications(hw);
3307                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3308                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3309                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3310                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3311                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3312                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3313                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3314                 hw->rss_info.ipv6_sctp_offload_supported = false;
3315                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3316                 pf->support_multi_tc_pause = false;
3317                 return 0;
3318         }
3319
3320         ret = hns3_query_dev_specifications(hw);
3321         if (ret) {
3322                 PMD_INIT_LOG(ERR,
3323                              "failed to query dev specifications, ret = %d",
3324                              ret);
3325                 return ret;
3326         }
3327
3328         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3329         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3330         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3331         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3332         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3333         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3334         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3335         hw->rss_info.ipv6_sctp_offload_supported = true;
3336         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3337         pf->support_multi_tc_pause = true;
3338
3339         return 0;
3340 }
3341
3342 static int
3343 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3344 {
3345         int ret;
3346
3347         switch (media_type) {
3348         case HNS3_MEDIA_TYPE_COPPER:
3349                 if (!hns3_dev_copper_supported(hw)) {
3350                         PMD_INIT_LOG(ERR,
3351                                      "Media type is copper, not supported.");
3352                         ret = -EOPNOTSUPP;
3353                 } else {
3354                         ret = 0;
3355                 }
3356                 break;
3357         case HNS3_MEDIA_TYPE_FIBER:
3358                 ret = 0;
3359                 break;
3360         case HNS3_MEDIA_TYPE_BACKPLANE:
3361                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3362                 ret = -EOPNOTSUPP;
3363                 break;
3364         default:
3365                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3366                 ret = -EINVAL;
3367                 break;
3368         }
3369
3370         return ret;
3371 }
3372
3373 static int
3374 hns3_get_board_configuration(struct hns3_hw *hw)
3375 {
3376         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3377         struct hns3_pf *pf = &hns->pf;
3378         struct hns3_cfg cfg;
3379         int ret;
3380
3381         ret = hns3_get_board_cfg(hw, &cfg);
3382         if (ret) {
3383                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3384                 return ret;
3385         }
3386
3387         ret = hns3_check_media_type(hw, cfg.media_type);
3388         if (ret)
3389                 return ret;
3390
3391         hw->mac.media_type = cfg.media_type;
3392         hw->rss_size_max = cfg.rss_size_max;
3393         hw->rss_dis_flag = false;
3394         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3395         hw->mac.phy_addr = cfg.phy_addr;
3396         hw->mac.default_addr_setted = false;
3397         hw->num_tx_desc = cfg.tqp_desc_num;
3398         hw->num_rx_desc = cfg.tqp_desc_num;
3399         hw->dcb_info.num_pg = 1;
3400         hw->dcb_info.hw_pfc_map = 0;
3401
3402         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3403         if (ret) {
3404                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3405                              cfg.default_speed, ret);
3406                 return ret;
3407         }
3408
3409         pf->tc_max = cfg.tc_num;
3410         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3411                 PMD_INIT_LOG(WARNING,
3412                              "Get TC num(%u) from flash, set TC num to 1",
3413                              pf->tc_max);
3414                 pf->tc_max = 1;
3415         }
3416
3417         /* Dev does not support DCB */
3418         if (!hns3_dev_dcb_supported(hw)) {
3419                 pf->tc_max = 1;
3420                 pf->pfc_max = 0;
3421         } else
3422                 pf->pfc_max = pf->tc_max;
3423
3424         hw->dcb_info.num_tc = 1;
3425         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3426                                      hw->tqps_num / hw->dcb_info.num_tc);
3427         hns3_set_bit(hw->hw_tc_map, 0, 1);
3428         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3429
3430         pf->wanted_umv_size = cfg.umv_space;
3431
3432         return ret;
3433 }
3434
3435 static int
3436 hns3_get_configuration(struct hns3_hw *hw)
3437 {
3438         int ret;
3439
3440         ret = hns3_query_function_status(hw);
3441         if (ret) {
3442                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3443                 return ret;
3444         }
3445
3446         /* Get device capability */
3447         ret = hns3_get_capability(hw);
3448         if (ret) {
3449                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3450                 return ret;
3451         }
3452
3453         /* Get pf resource */
3454         ret = hns3_query_pf_resource(hw);
3455         if (ret) {
3456                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3457                 return ret;
3458         }
3459
3460         ret = hns3_get_board_configuration(hw);
3461         if (ret) {
3462                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3463                 return ret;
3464         }
3465
3466         ret = hns3_query_dev_fec_info(hw);
3467         if (ret)
3468                 PMD_INIT_LOG(ERR,
3469                              "failed to query FEC information, ret = %d", ret);
3470
3471         return ret;
3472 }
3473
3474 static int
3475 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3476                       uint16_t tqp_vid, bool is_pf)
3477 {
3478         struct hns3_tqp_map_cmd *req;
3479         struct hns3_cmd_desc desc;
3480         int ret;
3481
3482         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3483
3484         req = (struct hns3_tqp_map_cmd *)desc.data;
3485         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3486         req->tqp_vf = func_id;
3487         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3488         if (!is_pf)
3489                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3490         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3491
3492         ret = hns3_cmd_send(hw, &desc, 1);
3493         if (ret)
3494                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3495
3496         return ret;
3497 }
3498
3499 static int
3500 hns3_map_tqp(struct hns3_hw *hw)
3501 {
3502         int ret;
3503         int i;
3504
3505         /*
3506          * In current version, VF is not supported when PF is driven by DPDK
3507          * driver, so we assign total tqps_num tqps allocated to this port
3508          * to PF.
3509          */
3510         for (i = 0; i < hw->total_tqps_num; i++) {
3511                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3512                 if (ret)
3513                         return ret;
3514         }
3515
3516         return 0;
3517 }
3518
3519 static int
3520 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3521 {
3522         struct hns3_config_mac_speed_dup_cmd *req;
3523         struct hns3_cmd_desc desc;
3524         int ret;
3525
3526         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3527
3528         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3529
3530         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3531
3532         switch (speed) {
3533         case ETH_SPEED_NUM_10M:
3534                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3535                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3536                 break;
3537         case ETH_SPEED_NUM_100M:
3538                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3539                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3540                 break;
3541         case ETH_SPEED_NUM_1G:
3542                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3543                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3544                 break;
3545         case ETH_SPEED_NUM_10G:
3546                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3547                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3548                 break;
3549         case ETH_SPEED_NUM_25G:
3550                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3551                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3552                 break;
3553         case ETH_SPEED_NUM_40G:
3554                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3555                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3556                 break;
3557         case ETH_SPEED_NUM_50G:
3558                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3559                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3560                 break;
3561         case ETH_SPEED_NUM_100G:
3562                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3563                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3564                 break;
3565         case ETH_SPEED_NUM_200G:
3566                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3567                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3568                 break;
3569         default:
3570                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3571                 return -EINVAL;
3572         }
3573
3574         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3575
3576         ret = hns3_cmd_send(hw, &desc, 1);
3577         if (ret)
3578                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3579
3580         return ret;
3581 }
3582
3583 static int
3584 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3585 {
3586         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3587         struct hns3_pf *pf = &hns->pf;
3588         struct hns3_priv_buf *priv;
3589         uint32_t i, total_size;
3590
3591         total_size = pf->pkt_buf_size;
3592
3593         /* alloc tx buffer for all enabled tc */
3594         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3595                 priv = &buf_alloc->priv_buf[i];
3596
3597                 if (hw->hw_tc_map & BIT(i)) {
3598                         if (total_size < pf->tx_buf_size)
3599                                 return -ENOMEM;
3600
3601                         priv->tx_buf_size = pf->tx_buf_size;
3602                 } else
3603                         priv->tx_buf_size = 0;
3604
3605                 total_size -= priv->tx_buf_size;
3606         }
3607
3608         return 0;
3609 }
3610
3611 static int
3612 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3613 {
3614 /* TX buffer size is unit by 128 byte */
3615 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3616 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3617         struct hns3_tx_buff_alloc_cmd *req;
3618         struct hns3_cmd_desc desc;
3619         uint32_t buf_size;
3620         uint32_t i;
3621         int ret;
3622
3623         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3624
3625         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3626         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3627                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3628
3629                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3630                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3631                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3632         }
3633
3634         ret = hns3_cmd_send(hw, &desc, 1);
3635         if (ret)
3636                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3637
3638         return ret;
3639 }
3640
3641 static int
3642 hns3_get_tc_num(struct hns3_hw *hw)
3643 {
3644         int cnt = 0;
3645         uint8_t i;
3646
3647         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3648                 if (hw->hw_tc_map & BIT(i))
3649                         cnt++;
3650         return cnt;
3651 }
3652
3653 static uint32_t
3654 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3655 {
3656         struct hns3_priv_buf *priv;
3657         uint32_t rx_priv = 0;
3658         int i;
3659
3660         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3661                 priv = &buf_alloc->priv_buf[i];
3662                 if (priv->enable)
3663                         rx_priv += priv->buf_size;
3664         }
3665         return rx_priv;
3666 }
3667
3668 static uint32_t
3669 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3670 {
3671         uint32_t total_tx_size = 0;
3672         uint32_t i;
3673
3674         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3675                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3676
3677         return total_tx_size;
3678 }
3679
3680 /* Get the number of pfc enabled TCs, which have private buffer */
3681 static int
3682 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3683 {
3684         struct hns3_priv_buf *priv;
3685         int cnt = 0;
3686         uint8_t i;
3687
3688         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3689                 priv = &buf_alloc->priv_buf[i];
3690                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3691                         cnt++;
3692         }
3693
3694         return cnt;
3695 }
3696
3697 /* Get the number of pfc disabled TCs, which have private buffer */
3698 static int
3699 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3700                          struct hns3_pkt_buf_alloc *buf_alloc)
3701 {
3702         struct hns3_priv_buf *priv;
3703         int cnt = 0;
3704         uint8_t i;
3705
3706         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3707                 priv = &buf_alloc->priv_buf[i];
3708                 if (hw->hw_tc_map & BIT(i) &&
3709                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3710                         cnt++;
3711         }
3712
3713         return cnt;
3714 }
3715
3716 static bool
3717 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3718                   uint32_t rx_all)
3719 {
3720         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3721         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3722         struct hns3_pf *pf = &hns->pf;
3723         uint32_t shared_buf, aligned_mps;
3724         uint32_t rx_priv;
3725         uint8_t tc_num;
3726         uint8_t i;
3727
3728         tc_num = hns3_get_tc_num(hw);
3729         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3730
3731         if (hns3_dev_dcb_supported(hw))
3732                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3733                                         pf->dv_buf_size;
3734         else
3735                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3736                                         + pf->dv_buf_size;
3737
3738         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3739         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3740                              HNS3_BUF_SIZE_UNIT);
3741
3742         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3743         if (rx_all < rx_priv + shared_std)
3744                 return false;
3745
3746         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3747         buf_alloc->s_buf.buf_size = shared_buf;
3748         if (hns3_dev_dcb_supported(hw)) {
3749                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3750                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3751                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3752                                   HNS3_BUF_SIZE_UNIT);
3753         } else {
3754                 buf_alloc->s_buf.self.high =
3755                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3756                 buf_alloc->s_buf.self.low = aligned_mps;
3757         }
3758
3759         if (hns3_dev_dcb_supported(hw)) {
3760                 hi_thrd = shared_buf - pf->dv_buf_size;
3761
3762                 if (tc_num <= NEED_RESERVE_TC_NUM)
3763                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3764                                   BUF_MAX_PERCENT;
3765
3766                 if (tc_num)
3767                         hi_thrd = hi_thrd / tc_num;
3768
3769                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3770                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3771                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3772         } else {
3773                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3774                 lo_thrd = aligned_mps;
3775         }
3776
3777         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3778                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3779                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3780         }
3781
3782         return true;
3783 }
3784
3785 static bool
3786 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3787                      struct hns3_pkt_buf_alloc *buf_alloc)
3788 {
3789         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3790         struct hns3_pf *pf = &hns->pf;
3791         struct hns3_priv_buf *priv;
3792         uint32_t aligned_mps;
3793         uint32_t rx_all;
3794         uint8_t i;
3795
3796         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3797         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3798
3799         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3800                 priv = &buf_alloc->priv_buf[i];
3801
3802                 priv->enable = 0;
3803                 priv->wl.low = 0;
3804                 priv->wl.high = 0;
3805                 priv->buf_size = 0;
3806
3807                 if (!(hw->hw_tc_map & BIT(i)))
3808                         continue;
3809
3810                 priv->enable = 1;
3811                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3812                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3813                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3814                                                 HNS3_BUF_SIZE_UNIT);
3815                 } else {
3816                         priv->wl.low = 0;
3817                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3818                                         aligned_mps;
3819                 }
3820
3821                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3822         }
3823
3824         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3825 }
3826
3827 static bool
3828 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3829                              struct hns3_pkt_buf_alloc *buf_alloc)
3830 {
3831         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3832         struct hns3_pf *pf = &hns->pf;
3833         struct hns3_priv_buf *priv;
3834         int no_pfc_priv_num;
3835         uint32_t rx_all;
3836         uint8_t mask;
3837         int i;
3838
3839         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3840         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3841
3842         /* let the last to be cleared first */
3843         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3844                 priv = &buf_alloc->priv_buf[i];
3845                 mask = BIT((uint8_t)i);
3846                 if (hw->hw_tc_map & mask &&
3847                     !(hw->dcb_info.hw_pfc_map & mask)) {
3848                         /* Clear the no pfc TC private buffer */
3849                         priv->wl.low = 0;
3850                         priv->wl.high = 0;
3851                         priv->buf_size = 0;
3852                         priv->enable = 0;
3853                         no_pfc_priv_num--;
3854                 }
3855
3856                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3857                     no_pfc_priv_num == 0)
3858                         break;
3859         }
3860
3861         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3862 }
3863
3864 static bool
3865 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3866                            struct hns3_pkt_buf_alloc *buf_alloc)
3867 {
3868         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3869         struct hns3_pf *pf = &hns->pf;
3870         struct hns3_priv_buf *priv;
3871         uint32_t rx_all;
3872         int pfc_priv_num;
3873         uint8_t mask;
3874         int i;
3875
3876         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3877         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3878
3879         /* let the last to be cleared first */
3880         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3881                 priv = &buf_alloc->priv_buf[i];
3882                 mask = BIT((uint8_t)i);
3883                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3884                         /* Reduce the number of pfc TC with private buffer */
3885                         priv->wl.low = 0;
3886                         priv->enable = 0;
3887                         priv->wl.high = 0;
3888                         priv->buf_size = 0;
3889                         pfc_priv_num--;
3890                 }
3891                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3892                     pfc_priv_num == 0)
3893                         break;
3894         }
3895
3896         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3897 }
3898
3899 static bool
3900 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3901                           struct hns3_pkt_buf_alloc *buf_alloc)
3902 {
3903 #define COMPENSATE_BUFFER       0x3C00
3904 #define COMPENSATE_HALF_MPS_NUM 5
3905 #define PRIV_WL_GAP             0x1800
3906         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3907         struct hns3_pf *pf = &hns->pf;
3908         uint32_t tc_num = hns3_get_tc_num(hw);
3909         uint32_t half_mps = pf->mps >> 1;
3910         struct hns3_priv_buf *priv;
3911         uint32_t min_rx_priv;
3912         uint32_t rx_priv;
3913         uint8_t i;
3914
3915         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3916         if (tc_num)
3917                 rx_priv = rx_priv / tc_num;
3918
3919         if (tc_num <= NEED_RESERVE_TC_NUM)
3920                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3921
3922         /*
3923          * Minimum value of private buffer in rx direction (min_rx_priv) is
3924          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3925          * buffer if rx_priv is greater than min_rx_priv.
3926          */
3927         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3928                         COMPENSATE_HALF_MPS_NUM * half_mps;
3929         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3930         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3931         if (rx_priv < min_rx_priv)
3932                 return false;
3933
3934         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3935                 priv = &buf_alloc->priv_buf[i];
3936                 priv->enable = 0;
3937                 priv->wl.low = 0;
3938                 priv->wl.high = 0;
3939                 priv->buf_size = 0;
3940
3941                 if (!(hw->hw_tc_map & BIT(i)))
3942                         continue;
3943
3944                 priv->enable = 1;
3945                 priv->buf_size = rx_priv;
3946                 priv->wl.high = rx_priv - pf->dv_buf_size;
3947                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3948         }
3949
3950         buf_alloc->s_buf.buf_size = 0;
3951
3952         return true;
3953 }
3954
3955 /*
3956  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3957  * @hw: pointer to struct hns3_hw
3958  * @buf_alloc: pointer to buffer calculation data
3959  * @return: 0: calculate sucessful, negative: fail
3960  */
3961 static int
3962 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3963 {
3964         /* When DCB is not supported, rx private buffer is not allocated. */
3965         if (!hns3_dev_dcb_supported(hw)) {
3966                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3967                 struct hns3_pf *pf = &hns->pf;
3968                 uint32_t rx_all = pf->pkt_buf_size;
3969
3970                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3971                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3972                         return -ENOMEM;
3973
3974                 return 0;
3975         }
3976
3977         /*
3978          * Try to allocate privated packet buffer for all TCs without share
3979          * buffer.
3980          */
3981         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3982                 return 0;
3983
3984         /*
3985          * Try to allocate privated packet buffer for all TCs with share
3986          * buffer.
3987          */
3988         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3989                 return 0;
3990
3991         /*
3992          * For different application scenes, the enabled port number, TC number
3993          * and no_drop TC number are different. In order to obtain the better
3994          * performance, software could allocate the buffer size and configure
3995          * the waterline by trying to decrease the private buffer size according
3996          * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
3997          * enabled tc.
3998          */
3999         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
4000                 return 0;
4001
4002         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
4003                 return 0;
4004
4005         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
4006                 return 0;
4007
4008         return -ENOMEM;
4009 }
4010
4011 static int
4012 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4013 {
4014         struct hns3_rx_priv_buff_cmd *req;
4015         struct hns3_cmd_desc desc;
4016         uint32_t buf_size;
4017         int ret;
4018         int i;
4019
4020         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
4021         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
4022
4023         /* Alloc private buffer TCs */
4024         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4025                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
4026
4027                 req->buf_num[i] =
4028                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
4029                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
4030         }
4031
4032         buf_size = buf_alloc->s_buf.buf_size;
4033         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
4034                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
4035
4036         ret = hns3_cmd_send(hw, &desc, 1);
4037         if (ret)
4038                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
4039
4040         return ret;
4041 }
4042
4043 static int
4044 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4045 {
4046 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
4047         struct hns3_rx_priv_wl_buf *req;
4048         struct hns3_priv_buf *priv;
4049         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4050         int i, j;
4051         int ret;
4052
4053         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4054                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4055                                           false);
4056                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4057
4058                 /* The first descriptor set the NEXT bit to 1 */
4059                 if (i == 0)
4060                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4061                 else
4062                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4063
4064                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4065                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4066
4067                         priv = &buf_alloc->priv_buf[idx];
4068                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4069                                                         HNS3_BUF_UNIT_S);
4070                         req->tc_wl[j].high |=
4071                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4072                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4073                                                         HNS3_BUF_UNIT_S);
4074                         req->tc_wl[j].low |=
4075                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4076                 }
4077         }
4078
4079         /* Send 2 descriptor at one time */
4080         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4081         if (ret)
4082                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4083                              ret);
4084         return ret;
4085 }
4086
4087 static int
4088 hns3_common_thrd_config(struct hns3_hw *hw,
4089                         struct hns3_pkt_buf_alloc *buf_alloc)
4090 {
4091 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4092         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4093         struct hns3_rx_com_thrd *req;
4094         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4095         struct hns3_tc_thrd *tc;
4096         int tc_idx;
4097         int i, j;
4098         int ret;
4099
4100         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4101                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4102                                           false);
4103                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4104
4105                 /* The first descriptor set the NEXT bit to 1 */
4106                 if (i == 0)
4107                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4108                 else
4109                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4110
4111                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4112                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4113                         tc = &s_buf->tc_thrd[tc_idx];
4114
4115                         req->com_thrd[j].high =
4116                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4117                         req->com_thrd[j].high |=
4118                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4119                         req->com_thrd[j].low =
4120                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4121                         req->com_thrd[j].low |=
4122                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4123                 }
4124         }
4125
4126         /* Send 2 descriptors at one time */
4127         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4128         if (ret)
4129                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4130
4131         return ret;
4132 }
4133
4134 static int
4135 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4136 {
4137         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4138         struct hns3_rx_com_wl *req;
4139         struct hns3_cmd_desc desc;
4140         int ret;
4141
4142         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4143
4144         req = (struct hns3_rx_com_wl *)desc.data;
4145         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4146         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4147
4148         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4149         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4150
4151         ret = hns3_cmd_send(hw, &desc, 1);
4152         if (ret)
4153                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4154
4155         return ret;
4156 }
4157
4158 int
4159 hns3_buffer_alloc(struct hns3_hw *hw)
4160 {
4161         struct hns3_pkt_buf_alloc pkt_buf;
4162         int ret;
4163
4164         memset(&pkt_buf, 0, sizeof(pkt_buf));
4165         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4166         if (ret) {
4167                 PMD_INIT_LOG(ERR,
4168                              "could not calc tx buffer size for all TCs %d",
4169                              ret);
4170                 return ret;
4171         }
4172
4173         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4174         if (ret) {
4175                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4176                 return ret;
4177         }
4178
4179         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4180         if (ret) {
4181                 PMD_INIT_LOG(ERR,
4182                              "could not calc rx priv buffer size for all TCs %d",
4183                              ret);
4184                 return ret;
4185         }
4186
4187         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4188         if (ret) {
4189                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4190                 return ret;
4191         }
4192
4193         if (hns3_dev_dcb_supported(hw)) {
4194                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4195                 if (ret) {
4196                         PMD_INIT_LOG(ERR,
4197                                      "could not configure rx private waterline %d",
4198                                      ret);
4199                         return ret;
4200                 }
4201
4202                 ret = hns3_common_thrd_config(hw, &pkt_buf);
4203                 if (ret) {
4204                         PMD_INIT_LOG(ERR,
4205                                      "could not configure common threshold %d",
4206                                      ret);
4207                         return ret;
4208                 }
4209         }
4210
4211         ret = hns3_common_wl_config(hw, &pkt_buf);
4212         if (ret)
4213                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4214                              ret);
4215
4216         return ret;
4217 }
4218
4219 static int
4220 hns3_mac_init(struct hns3_hw *hw)
4221 {
4222         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4223         struct hns3_mac *mac = &hw->mac;
4224         struct hns3_pf *pf = &hns->pf;
4225         int ret;
4226
4227         pf->support_sfp_query = true;
4228         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4229         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4230         if (ret) {
4231                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4232                 return ret;
4233         }
4234
4235         mac->link_status = ETH_LINK_DOWN;
4236
4237         return hns3_config_mtu(hw, pf->mps);
4238 }
4239
4240 static int
4241 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4242 {
4243 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4244 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4245 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4246 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4247         int return_status;
4248
4249         if (cmdq_resp) {
4250                 PMD_INIT_LOG(ERR,
4251                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4252                              cmdq_resp);
4253                 return -EIO;
4254         }
4255
4256         switch (resp_code) {
4257         case HNS3_ETHERTYPE_SUCCESS_ADD:
4258         case HNS3_ETHERTYPE_ALREADY_ADD:
4259                 return_status = 0;
4260                 break;
4261         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4262                 PMD_INIT_LOG(ERR,
4263                              "add mac ethertype failed for manager table overflow.");
4264                 return_status = -EIO;
4265                 break;
4266         case HNS3_ETHERTYPE_KEY_CONFLICT:
4267                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4268                 return_status = -EIO;
4269                 break;
4270         default:
4271                 PMD_INIT_LOG(ERR,
4272                              "add mac ethertype failed for undefined, code=%u.",
4273                              resp_code);
4274                 return_status = -EIO;
4275                 break;
4276         }
4277
4278         return return_status;
4279 }
4280
4281 static int
4282 hns3_add_mgr_tbl(struct hns3_hw *hw,
4283                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4284 {
4285         struct hns3_cmd_desc desc;
4286         uint8_t resp_code;
4287         uint16_t retval;
4288         int ret;
4289
4290         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4291         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4292
4293         ret = hns3_cmd_send(hw, &desc, 1);
4294         if (ret) {
4295                 PMD_INIT_LOG(ERR,
4296                              "add mac ethertype failed for cmd_send, ret =%d.",
4297                              ret);
4298                 return ret;
4299         }
4300
4301         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4302         retval = rte_le_to_cpu_16(desc.retval);
4303
4304         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4305 }
4306
4307 static void
4308 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4309                      int *table_item_num)
4310 {
4311         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4312
4313         /*
4314          * In current version, we add one item in management table as below:
4315          * 0x0180C200000E -- LLDP MC address
4316          */
4317         tbl = mgr_table;
4318         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4319         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4320         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4321         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4322         tbl->i_port_bitmap = 0x1;
4323         *table_item_num = 1;
4324 }
4325
4326 static int
4327 hns3_init_mgr_tbl(struct hns3_hw *hw)
4328 {
4329 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4330         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4331         int table_item_num;
4332         int ret;
4333         int i;
4334
4335         memset(mgr_table, 0, sizeof(mgr_table));
4336         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4337         for (i = 0; i < table_item_num; i++) {
4338                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4339                 if (ret) {
4340                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4341                                      ret);
4342                         return ret;
4343                 }
4344         }
4345
4346         return 0;
4347 }
4348
4349 static void
4350 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4351                         bool en_mc, bool en_bc, int vport_id)
4352 {
4353         if (!param)
4354                 return;
4355
4356         memset(param, 0, sizeof(struct hns3_promisc_param));
4357         if (en_uc)
4358                 param->enable = HNS3_PROMISC_EN_UC;
4359         if (en_mc)
4360                 param->enable |= HNS3_PROMISC_EN_MC;
4361         if (en_bc)
4362                 param->enable |= HNS3_PROMISC_EN_BC;
4363         param->vf_id = vport_id;
4364 }
4365
4366 static int
4367 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4368 {
4369         struct hns3_promisc_cfg_cmd *req;
4370         struct hns3_cmd_desc desc;
4371         int ret;
4372
4373         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4374
4375         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4376         req->vf_id = param->vf_id;
4377         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4378             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4379
4380         ret = hns3_cmd_send(hw, &desc, 1);
4381         if (ret)
4382                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4383
4384         return ret;
4385 }
4386
4387 static int
4388 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4389 {
4390         struct hns3_promisc_param param;
4391         bool en_bc_pmc = true;
4392         uint8_t vf_id;
4393
4394         /*
4395          * In current version VF is not supported when PF is driven by DPDK
4396          * driver, just need to configure parameters for PF vport.
4397          */
4398         vf_id = HNS3_PF_FUNC_ID;
4399
4400         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4401         return hns3_cmd_set_promisc_mode(hw, &param);
4402 }
4403
4404 static int
4405 hns3_promisc_init(struct hns3_hw *hw)
4406 {
4407         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4408         struct hns3_pf *pf = &hns->pf;
4409         struct hns3_promisc_param param;
4410         uint16_t func_id;
4411         int ret;
4412
4413         ret = hns3_set_promisc_mode(hw, false, false);
4414         if (ret) {
4415                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4416                 return ret;
4417         }
4418
4419         /*
4420          * In current version VFs are not supported when PF is driven by DPDK
4421          * driver. After PF has been taken over by DPDK, the original VF will
4422          * be invalid. So, there is a possibility of entry residues. It should
4423          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4424          * during init.
4425          */
4426         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4427                 hns3_promisc_param_init(&param, false, false, false, func_id);
4428                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4429                 if (ret) {
4430                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4431                                         " ret = %d", func_id, ret);
4432                         return ret;
4433                 }
4434         }
4435
4436         return 0;
4437 }
4438
4439 static void
4440 hns3_promisc_uninit(struct hns3_hw *hw)
4441 {
4442         struct hns3_promisc_param param;
4443         uint16_t func_id;
4444         int ret;
4445
4446         func_id = HNS3_PF_FUNC_ID;
4447
4448         /*
4449          * In current version VFs are not supported when PF is driven by
4450          * DPDK driver, and VFs' promisc mode status has been cleared during
4451          * init and their status will not change. So just clear PF's promisc
4452          * mode status during uninit.
4453          */
4454         hns3_promisc_param_init(&param, false, false, false, func_id);
4455         ret = hns3_cmd_set_promisc_mode(hw, &param);
4456         if (ret)
4457                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4458                                 " uninit, ret = %d", ret);
4459 }
4460
4461 static int
4462 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4463 {
4464         bool allmulti = dev->data->all_multicast ? true : false;
4465         struct hns3_adapter *hns = dev->data->dev_private;
4466         struct hns3_hw *hw = &hns->hw;
4467         uint64_t offloads;
4468         int err;
4469         int ret;
4470
4471         rte_spinlock_lock(&hw->lock);
4472         ret = hns3_set_promisc_mode(hw, true, true);
4473         if (ret) {
4474                 rte_spinlock_unlock(&hw->lock);
4475                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4476                          ret);
4477                 return ret;
4478         }
4479
4480         /*
4481          * When promiscuous mode was enabled, disable the vlan filter to let
4482          * all packets coming in in the receiving direction.
4483          */
4484         offloads = dev->data->dev_conf.rxmode.offloads;
4485         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4486                 ret = hns3_enable_vlan_filter(hns, false);
4487                 if (ret) {
4488                         hns3_err(hw, "failed to enable promiscuous mode due to "
4489                                      "failure to disable vlan filter, ret = %d",
4490                                  ret);
4491                         err = hns3_set_promisc_mode(hw, false, allmulti);
4492                         if (err)
4493                                 hns3_err(hw, "failed to restore promiscuous "
4494                                          "status after disable vlan filter "
4495                                          "failed during enabling promiscuous "
4496                                          "mode, ret = %d", ret);
4497                 }
4498         }
4499
4500         rte_spinlock_unlock(&hw->lock);
4501
4502         return ret;
4503 }
4504
4505 static int
4506 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4507 {
4508         bool allmulti = dev->data->all_multicast ? true : false;
4509         struct hns3_adapter *hns = dev->data->dev_private;
4510         struct hns3_hw *hw = &hns->hw;
4511         uint64_t offloads;
4512         int err;
4513         int ret;
4514
4515         /* If now in all_multicast mode, must remain in all_multicast mode. */
4516         rte_spinlock_lock(&hw->lock);
4517         ret = hns3_set_promisc_mode(hw, false, allmulti);
4518         if (ret) {
4519                 rte_spinlock_unlock(&hw->lock);
4520                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4521                          ret);
4522                 return ret;
4523         }
4524         /* when promiscuous mode was disabled, restore the vlan filter status */
4525         offloads = dev->data->dev_conf.rxmode.offloads;
4526         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4527                 ret = hns3_enable_vlan_filter(hns, true);
4528                 if (ret) {
4529                         hns3_err(hw, "failed to disable promiscuous mode due to"
4530                                  " failure to restore vlan filter, ret = %d",
4531                                  ret);
4532                         err = hns3_set_promisc_mode(hw, true, true);
4533                         if (err)
4534                                 hns3_err(hw, "failed to restore promiscuous "
4535                                          "status after enabling vlan filter "
4536                                          "failed during disabling promiscuous "
4537                                          "mode, ret = %d", ret);
4538                 }
4539         }
4540         rte_spinlock_unlock(&hw->lock);
4541
4542         return ret;
4543 }
4544
4545 static int
4546 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4547 {
4548         struct hns3_adapter *hns = dev->data->dev_private;
4549         struct hns3_hw *hw = &hns->hw;
4550         int ret;
4551
4552         if (dev->data->promiscuous)
4553                 return 0;
4554
4555         rte_spinlock_lock(&hw->lock);
4556         ret = hns3_set_promisc_mode(hw, false, true);
4557         rte_spinlock_unlock(&hw->lock);
4558         if (ret)
4559                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4560                          ret);
4561
4562         return ret;
4563 }
4564
4565 static int
4566 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4567 {
4568         struct hns3_adapter *hns = dev->data->dev_private;
4569         struct hns3_hw *hw = &hns->hw;
4570         int ret;
4571
4572         /* If now in promiscuous mode, must remain in all_multicast mode. */
4573         if (dev->data->promiscuous)
4574                 return 0;
4575
4576         rte_spinlock_lock(&hw->lock);
4577         ret = hns3_set_promisc_mode(hw, false, false);
4578         rte_spinlock_unlock(&hw->lock);
4579         if (ret)
4580                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4581                          ret);
4582
4583         return ret;
4584 }
4585
4586 static int
4587 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4588 {
4589         struct hns3_hw *hw = &hns->hw;
4590         bool allmulti = hw->data->all_multicast ? true : false;
4591         int ret;
4592
4593         if (hw->data->promiscuous) {
4594                 ret = hns3_set_promisc_mode(hw, true, true);
4595                 if (ret)
4596                         hns3_err(hw, "failed to restore promiscuous mode, "
4597                                  "ret = %d", ret);
4598                 return ret;
4599         }
4600
4601         ret = hns3_set_promisc_mode(hw, false, allmulti);
4602         if (ret)
4603                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4604                          ret);
4605         return ret;
4606 }
4607
4608 static int
4609 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4610 {
4611         struct hns3_sfp_info_cmd *resp;
4612         struct hns3_cmd_desc desc;
4613         int ret;
4614
4615         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4616         resp = (struct hns3_sfp_info_cmd *)desc.data;
4617         resp->query_type = HNS3_ACTIVE_QUERY;
4618
4619         ret = hns3_cmd_send(hw, &desc, 1);
4620         if (ret == -EOPNOTSUPP) {
4621                 hns3_warn(hw, "firmware does not support get SFP info,"
4622                           " ret = %d.", ret);
4623                 return ret;
4624         } else if (ret) {
4625                 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4626                 return ret;
4627         }
4628
4629         /*
4630          * In some case, the speed of MAC obtained from firmware may be 0, it
4631          * shouldn't be set to mac->speed.
4632          */
4633         if (!rte_le_to_cpu_32(resp->sfp_speed))
4634                 return 0;
4635
4636         mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4637         /*
4638          * if resp->supported_speed is 0, it means it's an old version
4639          * firmware, do not update these params.
4640          */
4641         if (resp->supported_speed) {
4642                 mac_info->query_type = HNS3_ACTIVE_QUERY;
4643                 mac_info->supported_speed =
4644                                         rte_le_to_cpu_32(resp->supported_speed);
4645                 mac_info->support_autoneg = resp->autoneg_ability;
4646                 mac_info->link_autoneg = (resp->autoneg == 0) ? ETH_LINK_FIXED
4647                                         : ETH_LINK_AUTONEG;
4648         } else {
4649                 mac_info->query_type = HNS3_DEFAULT_QUERY;
4650         }
4651
4652         return 0;
4653 }
4654
4655 static uint8_t
4656 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4657 {
4658         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4659                 duplex = ETH_LINK_FULL_DUPLEX;
4660
4661         return duplex;
4662 }
4663
4664 static int
4665 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4666 {
4667         struct hns3_mac *mac = &hw->mac;
4668         int ret;
4669
4670         duplex = hns3_check_speed_dup(duplex, speed);
4671         if (mac->link_speed == speed && mac->link_duplex == duplex)
4672                 return 0;
4673
4674         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4675         if (ret)
4676                 return ret;
4677
4678         ret = hns3_port_shaper_update(hw, speed);
4679         if (ret)
4680                 return ret;
4681
4682         mac->link_speed = speed;
4683         mac->link_duplex = duplex;
4684
4685         return 0;
4686 }
4687
4688 static int
4689 hns3_update_fiber_link_info(struct hns3_hw *hw)
4690 {
4691         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4692         struct hns3_mac *mac = &hw->mac;
4693         struct hns3_mac mac_info;
4694         int ret;
4695
4696         /* If firmware do not support get SFP/qSFP speed, return directly */
4697         if (!pf->support_sfp_query)
4698                 return 0;
4699
4700         memset(&mac_info, 0, sizeof(struct hns3_mac));
4701         ret = hns3_get_sfp_info(hw, &mac_info);
4702         if (ret == -EOPNOTSUPP) {
4703                 pf->support_sfp_query = false;
4704                 return ret;
4705         } else if (ret)
4706                 return ret;
4707
4708         /* Do nothing if no SFP */
4709         if (mac_info.link_speed == ETH_SPEED_NUM_NONE)
4710                 return 0;
4711
4712         /*
4713          * If query_type is HNS3_ACTIVE_QUERY, it is no need
4714          * to reconfigure the speed of MAC. Otherwise, it indicates
4715          * that the current firmware only supports to obtain the
4716          * speed of the SFP, and the speed of MAC needs to reconfigure.
4717          */
4718         mac->query_type = mac_info.query_type;
4719         if (mac->query_type == HNS3_ACTIVE_QUERY) {
4720                 if (mac_info.link_speed != mac->link_speed) {
4721                         ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4722                         if (ret)
4723                                 return ret;
4724                 }
4725
4726                 mac->link_speed = mac_info.link_speed;
4727                 mac->supported_speed = mac_info.supported_speed;
4728                 mac->support_autoneg = mac_info.support_autoneg;
4729                 mac->link_autoneg = mac_info.link_autoneg;
4730
4731                 return 0;
4732         }
4733
4734         /* Config full duplex for SFP */
4735         return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4736                                       ETH_LINK_FULL_DUPLEX);
4737 }
4738
4739 static void
4740 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4741 {
4742 #define HNS3_PHY_SUPPORTED_SPEED_MASK   0x2f
4743
4744         struct hns3_phy_params_bd0_cmd *req;
4745         uint32_t supported;
4746
4747         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4748         mac->link_speed = rte_le_to_cpu_32(req->speed);
4749         mac->link_duplex = hns3_get_bit(req->duplex,
4750                                            HNS3_PHY_DUPLEX_CFG_B);
4751         mac->link_autoneg = hns3_get_bit(req->autoneg,
4752                                            HNS3_PHY_AUTONEG_CFG_B);
4753         mac->advertising = rte_le_to_cpu_32(req->advertising);
4754         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4755         supported = rte_le_to_cpu_32(req->supported);
4756         mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4757         mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4758 }
4759
4760 static int
4761 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4762 {
4763         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4764         uint16_t i;
4765         int ret;
4766
4767         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4768                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4769                                           true);
4770                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4771         }
4772         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4773
4774         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4775         if (ret) {
4776                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4777                 return ret;
4778         }
4779
4780         hns3_parse_copper_phy_params(desc, mac);
4781
4782         return 0;
4783 }
4784
4785 static int
4786 hns3_update_copper_link_info(struct hns3_hw *hw)
4787 {
4788         struct hns3_mac *mac = &hw->mac;
4789         struct hns3_mac mac_info;
4790         int ret;
4791
4792         memset(&mac_info, 0, sizeof(struct hns3_mac));
4793         ret = hns3_get_copper_phy_params(hw, &mac_info);
4794         if (ret)
4795                 return ret;
4796
4797         if (mac_info.link_speed != mac->link_speed) {
4798                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4799                 if (ret)
4800                         return ret;
4801         }
4802
4803         mac->link_speed = mac_info.link_speed;
4804         mac->link_duplex = mac_info.link_duplex;
4805         mac->link_autoneg = mac_info.link_autoneg;
4806         mac->supported_speed = mac_info.supported_speed;
4807         mac->advertising = mac_info.advertising;
4808         mac->lp_advertising = mac_info.lp_advertising;
4809         mac->support_autoneg = mac_info.support_autoneg;
4810
4811         return 0;
4812 }
4813
4814 static int
4815 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4816 {
4817         struct hns3_adapter *hns = eth_dev->data->dev_private;
4818         struct hns3_hw *hw = &hns->hw;
4819         int ret = 0;
4820
4821         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4822                 ret = hns3_update_copper_link_info(hw);
4823         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4824                 ret = hns3_update_fiber_link_info(hw);
4825
4826         return ret;
4827 }
4828
4829 static int
4830 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4831 {
4832         struct hns3_config_mac_mode_cmd *req;
4833         struct hns3_cmd_desc desc;
4834         uint32_t loop_en = 0;
4835         uint8_t val = 0;
4836         int ret;
4837
4838         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4839
4840         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4841         if (enable)
4842                 val = 1;
4843         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4844         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4845         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4846         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4847         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4848         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4849         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4850         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4851         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4852         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4853
4854         /*
4855          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4856          * when receiving frames. Otherwise, CRC will be stripped.
4857          */
4858         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4859                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4860         else
4861                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4862         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4863         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4864         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4865         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4866
4867         ret = hns3_cmd_send(hw, &desc, 1);
4868         if (ret)
4869                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4870
4871         return ret;
4872 }
4873
4874 static int
4875 hns3_get_mac_link_status(struct hns3_hw *hw)
4876 {
4877         struct hns3_link_status_cmd *req;
4878         struct hns3_cmd_desc desc;
4879         int link_status;
4880         int ret;
4881
4882         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4883         ret = hns3_cmd_send(hw, &desc, 1);
4884         if (ret) {
4885                 hns3_err(hw, "get link status cmd failed %d", ret);
4886                 return ETH_LINK_DOWN;
4887         }
4888
4889         req = (struct hns3_link_status_cmd *)desc.data;
4890         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4891
4892         return !!link_status;
4893 }
4894
4895 static bool
4896 hns3_update_link_status(struct hns3_hw *hw)
4897 {
4898         int state;
4899
4900         state = hns3_get_mac_link_status(hw);
4901         if (state != hw->mac.link_status) {
4902                 hw->mac.link_status = state;
4903                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4904                 return true;
4905         }
4906
4907         return false;
4908 }
4909
4910 void
4911 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4912 {
4913         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4914         struct rte_eth_link new_link;
4915         int ret;
4916
4917         if (query)
4918                 hns3_update_port_link_info(dev);
4919
4920         memset(&new_link, 0, sizeof(new_link));
4921         hns3_setup_linkstatus(dev, &new_link);
4922
4923         ret = rte_eth_linkstatus_set(dev, &new_link);
4924         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4925                 hns3_start_report_lse(dev);
4926 }
4927
4928 static void
4929 hns3_service_handler(void *param)
4930 {
4931         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4932         struct hns3_adapter *hns = eth_dev->data->dev_private;
4933         struct hns3_hw *hw = &hns->hw;
4934
4935         if (!hns3_is_reset_pending(hns))
4936                 hns3_update_linkstatus_and_event(hw, true);
4937         else
4938                 hns3_warn(hw, "Cancel the query when reset is pending");
4939
4940         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4941 }
4942
4943 static int
4944 hns3_init_hardware(struct hns3_adapter *hns)
4945 {
4946         struct hns3_hw *hw = &hns->hw;
4947         int ret;
4948
4949         ret = hns3_map_tqp(hw);
4950         if (ret) {
4951                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4952                 return ret;
4953         }
4954
4955         ret = hns3_init_umv_space(hw);
4956         if (ret) {
4957                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4958                 return ret;
4959         }
4960
4961         ret = hns3_mac_init(hw);
4962         if (ret) {
4963                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4964                 goto err_mac_init;
4965         }
4966
4967         ret = hns3_init_mgr_tbl(hw);
4968         if (ret) {
4969                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4970                 goto err_mac_init;
4971         }
4972
4973         ret = hns3_promisc_init(hw);
4974         if (ret) {
4975                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4976                              ret);
4977                 goto err_mac_init;
4978         }
4979
4980         ret = hns3_init_vlan_config(hns);
4981         if (ret) {
4982                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4983                 goto err_mac_init;
4984         }
4985
4986         ret = hns3_dcb_init(hw);
4987         if (ret) {
4988                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4989                 goto err_mac_init;
4990         }
4991
4992         ret = hns3_init_fd_config(hns);
4993         if (ret) {
4994                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4995                 goto err_mac_init;
4996         }
4997
4998         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4999         if (ret) {
5000                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
5001                 goto err_mac_init;
5002         }
5003
5004         ret = hns3_config_gro(hw, false);
5005         if (ret) {
5006                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
5007                 goto err_mac_init;
5008         }
5009
5010         /*
5011          * In the initialization clearing the all hardware mapping relationship
5012          * configurations between queues and interrupt vectors is needed, so
5013          * some error caused by the residual configurations, such as the
5014          * unexpected interrupt, can be avoid.
5015          */
5016         ret = hns3_init_ring_with_vector(hw);
5017         if (ret) {
5018                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
5019                 goto err_mac_init;
5020         }
5021
5022         return 0;
5023
5024 err_mac_init:
5025         hns3_uninit_umv_space(hw);
5026         return ret;
5027 }
5028
5029 static int
5030 hns3_clear_hw(struct hns3_hw *hw)
5031 {
5032         struct hns3_cmd_desc desc;
5033         int ret;
5034
5035         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
5036
5037         ret = hns3_cmd_send(hw, &desc, 1);
5038         if (ret && ret != -EOPNOTSUPP)
5039                 return ret;
5040
5041         return 0;
5042 }
5043
5044 static void
5045 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
5046 {
5047         uint32_t val;
5048
5049         /*
5050          * The new firmware support report more hardware error types by
5051          * msix mode. These errors are defined as RAS errors in hardware
5052          * and belong to a different type from the MSI-x errors processed
5053          * by the network driver.
5054          *
5055          * Network driver should open the new error report on initialization.
5056          */
5057         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5058         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5059         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5060 }
5061
5062 static uint32_t
5063 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5064 {
5065         struct hns3_mac *mac = &hw->mac;
5066
5067         switch (mac->link_speed) {
5068         case ETH_SPEED_NUM_1G:
5069                 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5070         case ETH_SPEED_NUM_10G:
5071                 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5072         case ETH_SPEED_NUM_25G:
5073                 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5074         case ETH_SPEED_NUM_40G:
5075                 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5076         case ETH_SPEED_NUM_50G:
5077                 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5078         case ETH_SPEED_NUM_100G:
5079                 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5080         case ETH_SPEED_NUM_200G:
5081                 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5082         default:
5083                 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5084                 return 0;
5085         }
5086 }
5087
5088 /*
5089  * Validity of supported_speed for firber and copper media type can be
5090  * guaranteed by the following policy:
5091  * Copper:
5092  *       Although the initialization of the phy in the firmware may not be
5093  *       completed, the firmware can guarantees that the supported_speed is
5094  *       an valid value.
5095  * Firber:
5096  *       If the version of firmware supports the acitive query way of the
5097  *       HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5098  *       through it. If unsupported, use the SFP's speed as the value of the
5099  *       supported_speed.
5100  */
5101 static int
5102 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5103 {
5104         struct hns3_adapter *hns = eth_dev->data->dev_private;
5105         struct hns3_hw *hw = &hns->hw;
5106         struct hns3_mac *mac = &hw->mac;
5107         int ret;
5108
5109         ret = hns3_update_link_info(eth_dev);
5110         if (ret)
5111                 return ret;
5112
5113         if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5114                 /*
5115                  * Some firmware does not support the report of supported_speed,
5116                  * and only report the effective speed of SFP. In this case, it
5117                  * is necessary to use the SFP's speed as the supported_speed.
5118                  */
5119                 if (mac->supported_speed == 0)
5120                         mac->supported_speed =
5121                                 hns3_set_firber_default_support_speed(hw);
5122         }
5123
5124         return 0;
5125 }
5126
5127 static void
5128 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
5129 {
5130         struct hns3_mac *mac = &hns->hw.mac;
5131
5132         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
5133                 hns->pf.support_fc_autoneg = true;
5134                 return;
5135         }
5136
5137         /*
5138          * Flow control auto-negotiation requires the cooperation of the driver
5139          * and firmware. Currently, the optical port does not support flow
5140          * control auto-negotiation.
5141          */
5142         hns->pf.support_fc_autoneg = false;
5143 }
5144
5145 static int
5146 hns3_init_pf(struct rte_eth_dev *eth_dev)
5147 {
5148         struct rte_device *dev = eth_dev->device;
5149         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5150         struct hns3_adapter *hns = eth_dev->data->dev_private;
5151         struct hns3_hw *hw = &hns->hw;
5152         int ret;
5153
5154         PMD_INIT_FUNC_TRACE();
5155
5156         /* Get hardware io base address from pcie BAR2 IO space */
5157         hw->io_base = pci_dev->mem_resource[2].addr;
5158
5159         /* Firmware command queue initialize */
5160         ret = hns3_cmd_init_queue(hw);
5161         if (ret) {
5162                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5163                 goto err_cmd_init_queue;
5164         }
5165
5166         hns3_clear_all_event_cause(hw);
5167
5168         /* Firmware command initialize */
5169         ret = hns3_cmd_init(hw);
5170         if (ret) {
5171                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5172                 goto err_cmd_init;
5173         }
5174
5175         hns3_tx_push_init(eth_dev);
5176
5177         /*
5178          * To ensure that the hardware environment is clean during
5179          * initialization, the driver actively clear the hardware environment
5180          * during initialization, including PF and corresponding VFs' vlan, mac,
5181          * flow table configurations, etc.
5182          */
5183         ret = hns3_clear_hw(hw);
5184         if (ret) {
5185                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5186                 goto err_cmd_init;
5187         }
5188
5189         /* Hardware statistics of imissed registers cleared. */
5190         ret = hns3_update_imissed_stats(hw, true);
5191         if (ret) {
5192                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5193                 goto err_cmd_init;
5194         }
5195
5196         hns3_config_all_msix_error(hw, true);
5197
5198         ret = rte_intr_callback_register(&pci_dev->intr_handle,
5199                                          hns3_interrupt_handler,
5200                                          eth_dev);
5201         if (ret) {
5202                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5203                 goto err_intr_callback_register;
5204         }
5205
5206         ret = hns3_ptp_init(hw);
5207         if (ret)
5208                 goto err_get_config;
5209
5210         /* Enable interrupt */
5211         rte_intr_enable(&pci_dev->intr_handle);
5212         hns3_pf_enable_irq0(hw);
5213
5214         /* Get configuration */
5215         ret = hns3_get_configuration(hw);
5216         if (ret) {
5217                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5218                 goto err_get_config;
5219         }
5220
5221         ret = hns3_tqp_stats_init(hw);
5222         if (ret)
5223                 goto err_get_config;
5224
5225         ret = hns3_init_hardware(hns);
5226         if (ret) {
5227                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5228                 goto err_init_hw;
5229         }
5230
5231         /* Initialize flow director filter list & hash */
5232         ret = hns3_fdir_filter_init(hns);
5233         if (ret) {
5234                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5235                 goto err_fdir;
5236         }
5237
5238         hns3_rss_set_default_args(hw);
5239
5240         ret = hns3_enable_hw_error_intr(hns, true);
5241         if (ret) {
5242                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5243                              ret);
5244                 goto err_enable_intr;
5245         }
5246
5247         ret = hns3_get_port_supported_speed(eth_dev);
5248         if (ret) {
5249                 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5250                              "by device, ret = %d.", ret);
5251                 goto err_supported_speed;
5252         }
5253
5254         hns3_get_fc_autoneg_capability(hns);
5255
5256         hns3_tm_conf_init(eth_dev);
5257
5258         return 0;
5259
5260 err_supported_speed:
5261         (void)hns3_enable_hw_error_intr(hns, false);
5262 err_enable_intr:
5263         hns3_fdir_filter_uninit(hns);
5264 err_fdir:
5265         hns3_uninit_umv_space(hw);
5266 err_init_hw:
5267         hns3_tqp_stats_uninit(hw);
5268 err_get_config:
5269         hns3_pf_disable_irq0(hw);
5270         rte_intr_disable(&pci_dev->intr_handle);
5271         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5272                              eth_dev);
5273 err_intr_callback_register:
5274 err_cmd_init:
5275         hns3_cmd_uninit(hw);
5276         hns3_cmd_destroy_queue(hw);
5277 err_cmd_init_queue:
5278         hw->io_base = NULL;
5279
5280         return ret;
5281 }
5282
5283 static void
5284 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5285 {
5286         struct hns3_adapter *hns = eth_dev->data->dev_private;
5287         struct rte_device *dev = eth_dev->device;
5288         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5289         struct hns3_hw *hw = &hns->hw;
5290
5291         PMD_INIT_FUNC_TRACE();
5292
5293         hns3_tm_conf_uninit(eth_dev);
5294         hns3_enable_hw_error_intr(hns, false);
5295         hns3_rss_uninit(hns);
5296         (void)hns3_config_gro(hw, false);
5297         hns3_promisc_uninit(hw);
5298         hns3_fdir_filter_uninit(hns);
5299         hns3_uninit_umv_space(hw);
5300         hns3_tqp_stats_uninit(hw);
5301         hns3_config_mac_tnl_int(hw, false);
5302         hns3_pf_disable_irq0(hw);
5303         rte_intr_disable(&pci_dev->intr_handle);
5304         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5305                              eth_dev);
5306         hns3_config_all_msix_error(hw, false);
5307         hns3_cmd_uninit(hw);
5308         hns3_cmd_destroy_queue(hw);
5309         hw->io_base = NULL;
5310 }
5311
5312 static uint32_t
5313 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
5314 {
5315         uint32_t speed_bit;
5316
5317         switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5318         case ETH_LINK_SPEED_10M:
5319                 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
5320                 break;
5321         case ETH_LINK_SPEED_10M_HD:
5322                 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
5323                 break;
5324         case ETH_LINK_SPEED_100M:
5325                 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
5326                 break;
5327         case ETH_LINK_SPEED_100M_HD:
5328                 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
5329                 break;
5330         case ETH_LINK_SPEED_1G:
5331                 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
5332                 break;
5333         default:
5334                 speed_bit = 0;
5335                 break;
5336         }
5337
5338         return speed_bit;
5339 }
5340
5341 static uint32_t
5342 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
5343 {
5344         uint32_t speed_bit;
5345
5346         switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5347         case ETH_LINK_SPEED_1G:
5348                 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
5349                 break;
5350         case ETH_LINK_SPEED_10G:
5351                 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
5352                 break;
5353         case ETH_LINK_SPEED_25G:
5354                 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
5355                 break;
5356         case ETH_LINK_SPEED_40G:
5357                 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
5358                 break;
5359         case ETH_LINK_SPEED_50G:
5360                 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
5361                 break;
5362         case ETH_LINK_SPEED_100G:
5363                 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
5364                 break;
5365         case ETH_LINK_SPEED_200G:
5366                 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
5367                 break;
5368         default:
5369                 speed_bit = 0;
5370                 break;
5371         }
5372
5373         return speed_bit;
5374 }
5375
5376 static int
5377 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
5378 {
5379         struct hns3_mac *mac = &hw->mac;
5380         uint32_t supported_speed = mac->supported_speed;
5381         uint32_t speed_bit = 0;
5382
5383         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
5384                 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
5385         else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
5386                 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
5387
5388         if (!(speed_bit & supported_speed)) {
5389                 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
5390                          link_speeds);
5391                 return -EINVAL;
5392         }
5393
5394         return 0;
5395 }
5396
5397 static inline uint32_t
5398 hns3_get_link_speed(uint32_t link_speeds)
5399 {
5400         uint32_t speed = ETH_SPEED_NUM_NONE;
5401
5402         if (link_speeds & ETH_LINK_SPEED_10M ||
5403             link_speeds & ETH_LINK_SPEED_10M_HD)
5404                 speed = ETH_SPEED_NUM_10M;
5405         if (link_speeds & ETH_LINK_SPEED_100M ||
5406             link_speeds & ETH_LINK_SPEED_100M_HD)
5407                 speed = ETH_SPEED_NUM_100M;
5408         if (link_speeds & ETH_LINK_SPEED_1G)
5409                 speed = ETH_SPEED_NUM_1G;
5410         if (link_speeds & ETH_LINK_SPEED_10G)
5411                 speed = ETH_SPEED_NUM_10G;
5412         if (link_speeds & ETH_LINK_SPEED_25G)
5413                 speed = ETH_SPEED_NUM_25G;
5414         if (link_speeds & ETH_LINK_SPEED_40G)
5415                 speed = ETH_SPEED_NUM_40G;
5416         if (link_speeds & ETH_LINK_SPEED_50G)
5417                 speed = ETH_SPEED_NUM_50G;
5418         if (link_speeds & ETH_LINK_SPEED_100G)
5419                 speed = ETH_SPEED_NUM_100G;
5420         if (link_speeds & ETH_LINK_SPEED_200G)
5421                 speed = ETH_SPEED_NUM_200G;
5422
5423         return speed;
5424 }
5425
5426 static uint8_t
5427 hns3_get_link_duplex(uint32_t link_speeds)
5428 {
5429         if ((link_speeds & ETH_LINK_SPEED_10M_HD) ||
5430             (link_speeds & ETH_LINK_SPEED_100M_HD))
5431                 return ETH_LINK_HALF_DUPLEX;
5432         else
5433                 return ETH_LINK_FULL_DUPLEX;
5434 }
5435
5436 static int
5437 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5438                                 struct hns3_set_link_speed_cfg *cfg)
5439 {
5440         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5441         struct hns3_phy_params_bd0_cmd *req;
5442         uint16_t i;
5443
5444         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5445                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5446                                           false);
5447                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5448         }
5449         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5450         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5451         req->autoneg = cfg->autoneg;
5452
5453         /*
5454          * The full speed capability is used to negotiate when
5455          * auto-negotiation is enabled.
5456          */
5457         if (cfg->autoneg) {
5458                 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5459                                     HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5460                                     HNS3_PHY_LINK_SPEED_100M_BIT |
5461                                     HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5462                                     HNS3_PHY_LINK_SPEED_1000M_BIT;
5463         } else {
5464                 req->speed = cfg->speed;
5465                 req->duplex = cfg->duplex;
5466         }
5467
5468         return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5469 }
5470
5471 static int
5472 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5473 {
5474         struct hns3_config_auto_neg_cmd *req;
5475         struct hns3_cmd_desc desc;
5476         uint32_t flag = 0;
5477         int ret;
5478
5479         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5480
5481         req = (struct hns3_config_auto_neg_cmd *)desc.data;
5482         if (enable)
5483                 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5484         req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5485
5486         ret = hns3_cmd_send(hw, &desc, 1);
5487         if (ret)
5488                 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5489
5490         return ret;
5491 }
5492
5493 static int
5494 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5495                                struct hns3_set_link_speed_cfg *cfg)
5496 {
5497         int ret;
5498
5499         if (hw->mac.support_autoneg) {
5500                 ret = hns3_set_autoneg(hw, cfg->autoneg);
5501                 if (ret) {
5502                         hns3_err(hw, "failed to configure auto-negotiation.");
5503                         return ret;
5504                 }
5505
5506                 /*
5507                  * To enable auto-negotiation, we only need to open the switch
5508                  * of auto-negotiation, then firmware sets all speed
5509                  * capabilities.
5510                  */
5511                 if (cfg->autoneg)
5512                         return 0;
5513         }
5514
5515         /*
5516          * Some hardware doesn't support auto-negotiation, but users may not
5517          * configure link_speeds (default 0), which means auto-negotiation.
5518          * In this case, it should return success.
5519          */
5520         if (cfg->autoneg)
5521                 return 0;
5522
5523         return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
5524 }
5525
5526 static int
5527 hns3_set_port_link_speed(struct hns3_hw *hw,
5528                          struct hns3_set_link_speed_cfg *cfg)
5529 {
5530         int ret;
5531
5532         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5533 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5534                 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5535                 if (pf->is_tmp_phy)
5536                         return 0;
5537 #endif
5538
5539                 ret = hns3_set_copper_port_link_speed(hw, cfg);
5540                 if (ret) {
5541                         hns3_err(hw, "failed to set copper port link speed,"
5542                                  "ret = %d.", ret);
5543                         return ret;
5544                 }
5545         } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5546                 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5547                 if (ret) {
5548                         hns3_err(hw, "failed to set fiber port link speed,"
5549                                  "ret = %d.", ret);
5550                         return ret;
5551                 }
5552         }
5553
5554         return 0;
5555 }
5556
5557 static int
5558 hns3_apply_link_speed(struct hns3_hw *hw)
5559 {
5560         struct rte_eth_conf *conf = &hw->data->dev_conf;
5561         struct hns3_set_link_speed_cfg cfg;
5562
5563         memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5564         cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ?
5565                         ETH_LINK_AUTONEG : ETH_LINK_FIXED;
5566         if (cfg.autoneg != ETH_LINK_AUTONEG) {
5567                 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5568                 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5569         }
5570
5571         return hns3_set_port_link_speed(hw, &cfg);
5572 }
5573
5574 static int
5575 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5576 {
5577         struct hns3_hw *hw = &hns->hw;
5578         int ret;
5579
5580         ret = hns3_update_queue_map_configure(hns);
5581         if (ret) {
5582                 hns3_err(hw, "failed to update queue mapping configuration, ret = %d",
5583                          ret);
5584                 return ret;
5585         }
5586
5587         /* Note: hns3_tm_conf_update must be called after configuring DCB. */
5588         ret = hns3_tm_conf_update(hw);
5589         if (ret) {
5590                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5591                 return ret;
5592         }
5593
5594         hns3_enable_rxd_adv_layout(hw);
5595
5596         ret = hns3_init_queues(hns, reset_queue);
5597         if (ret) {
5598                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5599                 return ret;
5600         }
5601
5602         ret = hns3_cfg_mac_mode(hw, true);
5603         if (ret) {
5604                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5605                 goto err_config_mac_mode;
5606         }
5607
5608         ret = hns3_apply_link_speed(hw);
5609         if (ret)
5610                 goto err_set_link_speed;
5611
5612         return 0;
5613
5614 err_set_link_speed:
5615         (void)hns3_cfg_mac_mode(hw, false);
5616
5617 err_config_mac_mode:
5618         hns3_dev_release_mbufs(hns);
5619         /*
5620          * Here is exception handling, hns3_reset_all_tqps will have the
5621          * corresponding error message if it is handled incorrectly, so it is
5622          * not necessary to check hns3_reset_all_tqps return value, here keep
5623          * ret as the error code causing the exception.
5624          */
5625         (void)hns3_reset_all_tqps(hns);
5626         return ret;
5627 }
5628
5629 static int
5630 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5631 {
5632         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5633         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5634         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5635         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5636         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5637         uint32_t intr_vector;
5638         uint16_t q_id;
5639         int ret;
5640
5641         /*
5642          * hns3 needs a separate interrupt to be used as event interrupt which
5643          * could not be shared with task queue pair, so KERNEL drivers need
5644          * support multiple interrupt vectors.
5645          */
5646         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5647             !rte_intr_cap_multiple(intr_handle))
5648                 return 0;
5649
5650         rte_intr_disable(intr_handle);
5651         intr_vector = hw->used_rx_queues;
5652         /* creates event fd for each intr vector when MSIX is used */
5653         if (rte_intr_efd_enable(intr_handle, intr_vector))
5654                 return -EINVAL;
5655
5656         if (intr_handle->intr_vec == NULL) {
5657                 intr_handle->intr_vec =
5658                         rte_zmalloc("intr_vec",
5659                                     hw->used_rx_queues * sizeof(int), 0);
5660                 if (intr_handle->intr_vec == NULL) {
5661                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5662                                         hw->used_rx_queues);
5663                         ret = -ENOMEM;
5664                         goto alloc_intr_vec_error;
5665                 }
5666         }
5667
5668         if (rte_intr_allow_others(intr_handle)) {
5669                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5670                 base = RTE_INTR_VEC_RXTX_OFFSET;
5671         }
5672
5673         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5674                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5675                                                  HNS3_RING_TYPE_RX, q_id);
5676                 if (ret)
5677                         goto bind_vector_error;
5678                 intr_handle->intr_vec[q_id] = vec;
5679                 /*
5680                  * If there are not enough efds (e.g. not enough interrupt),
5681                  * remaining queues will be bond to the last interrupt.
5682                  */
5683                 if (vec < base + intr_handle->nb_efd - 1)
5684                         vec++;
5685         }
5686         rte_intr_enable(intr_handle);
5687         return 0;
5688
5689 bind_vector_error:
5690         rte_free(intr_handle->intr_vec);
5691         intr_handle->intr_vec = NULL;
5692 alloc_intr_vec_error:
5693         rte_intr_efd_disable(intr_handle);
5694         return ret;
5695 }
5696
5697 static int
5698 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5699 {
5700         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5701         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5702         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5703         uint16_t q_id;
5704         int ret;
5705
5706         if (dev->data->dev_conf.intr_conf.rxq == 0)
5707                 return 0;
5708
5709         if (rte_intr_dp_is_en(intr_handle)) {
5710                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5711                         ret = hns3_bind_ring_with_vector(hw,
5712                                         intr_handle->intr_vec[q_id], true,
5713                                         HNS3_RING_TYPE_RX, q_id);
5714                         if (ret)
5715                                 return ret;
5716                 }
5717         }
5718
5719         return 0;
5720 }
5721
5722 static void
5723 hns3_restore_filter(struct rte_eth_dev *dev)
5724 {
5725         hns3_restore_rss_filter(dev);
5726 }
5727
5728 static int
5729 hns3_dev_start(struct rte_eth_dev *dev)
5730 {
5731         struct hns3_adapter *hns = dev->data->dev_private;
5732         struct hns3_hw *hw = &hns->hw;
5733         int ret;
5734
5735         PMD_INIT_FUNC_TRACE();
5736         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5737                 return -EBUSY;
5738
5739         rte_spinlock_lock(&hw->lock);
5740         hw->adapter_state = HNS3_NIC_STARTING;
5741
5742         ret = hns3_do_start(hns, true);
5743         if (ret) {
5744                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5745                 rte_spinlock_unlock(&hw->lock);
5746                 return ret;
5747         }
5748         ret = hns3_map_rx_interrupt(dev);
5749         if (ret)
5750                 goto map_rx_inter_err;
5751
5752         /*
5753          * There are three register used to control the status of a TQP
5754          * (contains a pair of Tx queue and Rx queue) in the new version network
5755          * engine. One is used to control the enabling of Tx queue, the other is
5756          * used to control the enabling of Rx queue, and the last is the master
5757          * switch used to control the enabling of the tqp. The Tx register and
5758          * TQP register must be enabled at the same time to enable a Tx queue.
5759          * The same applies to the Rx queue. For the older network engine, this
5760          * function only refresh the enabled flag, and it is used to update the
5761          * status of queue in the dpdk framework.
5762          */
5763         ret = hns3_start_all_txqs(dev);
5764         if (ret)
5765                 goto map_rx_inter_err;
5766
5767         ret = hns3_start_all_rxqs(dev);
5768         if (ret)
5769                 goto start_all_rxqs_fail;
5770
5771         hw->adapter_state = HNS3_NIC_STARTED;
5772         rte_spinlock_unlock(&hw->lock);
5773
5774         hns3_rx_scattered_calc(dev);
5775         hns3_set_rxtx_function(dev);
5776         hns3_mp_req_start_rxtx(dev);
5777
5778         hns3_restore_filter(dev);
5779
5780         /* Enable interrupt of all rx queues before enabling queues */
5781         hns3_dev_all_rx_queue_intr_enable(hw, true);
5782
5783         /*
5784          * After finished the initialization, enable tqps to receive/transmit
5785          * packets and refresh all queue status.
5786          */
5787         hns3_start_tqps(hw);
5788
5789         hns3_tm_dev_start_proc(hw);
5790
5791         if (dev->data->dev_conf.intr_conf.lsc != 0)
5792                 hns3_dev_link_update(dev, 0);
5793         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5794
5795         hns3_info(hw, "hns3 dev start successful!");
5796
5797         return 0;
5798
5799 start_all_rxqs_fail:
5800         hns3_stop_all_txqs(dev);
5801 map_rx_inter_err:
5802         (void)hns3_do_stop(hns);
5803         hw->adapter_state = HNS3_NIC_CONFIGURED;
5804         rte_spinlock_unlock(&hw->lock);
5805
5806         return ret;
5807 }
5808
5809 static int
5810 hns3_do_stop(struct hns3_adapter *hns)
5811 {
5812         struct hns3_hw *hw = &hns->hw;
5813         int ret;
5814
5815         /*
5816          * The "hns3_do_stop" function will also be called by .stop_service to
5817          * prepare reset. At the time of global or IMP reset, the command cannot
5818          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5819          * accessed during the reset process. So the mbuf can not be released
5820          * during reset and is required to be released after the reset is
5821          * completed.
5822          */
5823         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5824                 hns3_dev_release_mbufs(hns);
5825
5826         ret = hns3_cfg_mac_mode(hw, false);
5827         if (ret)
5828                 return ret;
5829         hw->mac.link_status = ETH_LINK_DOWN;
5830
5831         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5832                 hns3_configure_all_mac_addr(hns, true);
5833                 ret = hns3_reset_all_tqps(hns);
5834                 if (ret) {
5835                         hns3_err(hw, "failed to reset all queues ret = %d.",
5836                                  ret);
5837                         return ret;
5838                 }
5839         }
5840         hw->mac.default_addr_setted = false;
5841         return 0;
5842 }
5843
5844 static void
5845 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5846 {
5847         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5848         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5849         struct hns3_adapter *hns = dev->data->dev_private;
5850         struct hns3_hw *hw = &hns->hw;
5851         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5852         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5853         uint16_t q_id;
5854
5855         if (dev->data->dev_conf.intr_conf.rxq == 0)
5856                 return;
5857
5858         /* unmap the ring with vector */
5859         if (rte_intr_allow_others(intr_handle)) {
5860                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5861                 base = RTE_INTR_VEC_RXTX_OFFSET;
5862         }
5863         if (rte_intr_dp_is_en(intr_handle)) {
5864                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5865                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5866                                                          HNS3_RING_TYPE_RX,
5867                                                          q_id);
5868                         if (vec < base + intr_handle->nb_efd - 1)
5869                                 vec++;
5870                 }
5871         }
5872         /* Clean datapath event and queue/vec mapping */
5873         rte_intr_efd_disable(intr_handle);
5874         if (intr_handle->intr_vec) {
5875                 rte_free(intr_handle->intr_vec);
5876                 intr_handle->intr_vec = NULL;
5877         }
5878 }
5879
5880 static int
5881 hns3_dev_stop(struct rte_eth_dev *dev)
5882 {
5883         struct hns3_adapter *hns = dev->data->dev_private;
5884         struct hns3_hw *hw = &hns->hw;
5885
5886         PMD_INIT_FUNC_TRACE();
5887         dev->data->dev_started = 0;
5888
5889         hw->adapter_state = HNS3_NIC_STOPPING;
5890         hns3_set_rxtx_function(dev);
5891         rte_wmb();
5892         /* Disable datapath on secondary process. */
5893         hns3_mp_req_stop_rxtx(dev);
5894         /* Prevent crashes when queues are still in use. */
5895         rte_delay_ms(hw->cfg_max_queues);
5896
5897         rte_spinlock_lock(&hw->lock);
5898         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5899                 hns3_tm_dev_stop_proc(hw);
5900                 hns3_config_mac_tnl_int(hw, false);
5901                 hns3_stop_tqps(hw);
5902                 hns3_do_stop(hns);
5903                 hns3_unmap_rx_interrupt(dev);
5904                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5905         }
5906         hns3_rx_scattered_reset(dev);
5907         rte_eal_alarm_cancel(hns3_service_handler, dev);
5908         hns3_stop_report_lse(dev);
5909         rte_spinlock_unlock(&hw->lock);
5910
5911         return 0;
5912 }
5913
5914 static int
5915 hns3_dev_close(struct rte_eth_dev *eth_dev)
5916 {
5917         struct hns3_adapter *hns = eth_dev->data->dev_private;
5918         struct hns3_hw *hw = &hns->hw;
5919         int ret = 0;
5920
5921         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5922                 rte_free(eth_dev->process_private);
5923                 eth_dev->process_private = NULL;
5924                 return 0;
5925         }
5926
5927         if (hw->adapter_state == HNS3_NIC_STARTED)
5928                 ret = hns3_dev_stop(eth_dev);
5929
5930         hw->adapter_state = HNS3_NIC_CLOSING;
5931         hns3_reset_abort(hns);
5932         hw->adapter_state = HNS3_NIC_CLOSED;
5933
5934         hns3_configure_all_mc_mac_addr(hns, true);
5935         hns3_remove_all_vlan_table(hns);
5936         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5937         hns3_uninit_pf(eth_dev);
5938         hns3_free_all_queues(eth_dev);
5939         rte_free(hw->reset.wait_data);
5940         rte_free(eth_dev->process_private);
5941         eth_dev->process_private = NULL;
5942         hns3_mp_uninit_primary();
5943         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5944
5945         return ret;
5946 }
5947
5948 static void
5949 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5950                                    bool *tx_pause)
5951 {
5952         struct hns3_mac *mac = &hw->mac;
5953         uint32_t advertising = mac->advertising;
5954         uint32_t lp_advertising = mac->lp_advertising;
5955         *rx_pause = false;
5956         *tx_pause = false;
5957
5958         if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5959                 *rx_pause = true;
5960                 *tx_pause = true;
5961         } else if (advertising & lp_advertising &
5962                    HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5963                 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5964                         *rx_pause = true;
5965                 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5966                         *tx_pause = true;
5967         }
5968 }
5969
5970 static enum hns3_fc_mode
5971 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5972 {
5973         enum hns3_fc_mode current_mode;
5974         bool rx_pause = false;
5975         bool tx_pause = false;
5976
5977         switch (hw->mac.media_type) {
5978         case HNS3_MEDIA_TYPE_COPPER:
5979                 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5980                 break;
5981
5982         /*
5983          * Flow control auto-negotiation is not supported for fiber and
5984          * backpalne media type.
5985          */
5986         case HNS3_MEDIA_TYPE_FIBER:
5987         case HNS3_MEDIA_TYPE_BACKPLANE:
5988                 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
5989                 current_mode = hw->requested_fc_mode;
5990                 goto out;
5991         default:
5992                 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
5993                          hw->mac.media_type);
5994                 current_mode = HNS3_FC_NONE;
5995                 goto out;
5996         }
5997
5998         if (rx_pause && tx_pause)
5999                 current_mode = HNS3_FC_FULL;
6000         else if (rx_pause)
6001                 current_mode = HNS3_FC_RX_PAUSE;
6002         else if (tx_pause)
6003                 current_mode = HNS3_FC_TX_PAUSE;
6004         else
6005                 current_mode = HNS3_FC_NONE;
6006
6007 out:
6008         return current_mode;
6009 }
6010
6011 static enum hns3_fc_mode
6012 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
6013 {
6014         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6015         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6016         struct hns3_mac *mac = &hw->mac;
6017
6018         /*
6019          * When the flow control mode is obtained, the device may not complete
6020          * auto-negotiation. It is necessary to wait for link establishment.
6021          */
6022         (void)hns3_dev_link_update(dev, 1);
6023
6024         /*
6025          * If the link auto-negotiation of the nic is disabled, or the flow
6026          * control auto-negotiation is not supported, the forced flow control
6027          * mode is used.
6028          */
6029         if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
6030                 return hw->requested_fc_mode;
6031
6032         return hns3_get_autoneg_fc_mode(hw);
6033 }
6034
6035 static int
6036 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6037 {
6038         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6039         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6040         enum hns3_fc_mode current_mode;
6041
6042         current_mode = hns3_get_current_fc_mode(dev);
6043         switch (current_mode) {
6044         case HNS3_FC_FULL:
6045                 fc_conf->mode = RTE_FC_FULL;
6046                 break;
6047         case HNS3_FC_TX_PAUSE:
6048                 fc_conf->mode = RTE_FC_TX_PAUSE;
6049                 break;
6050         case HNS3_FC_RX_PAUSE:
6051                 fc_conf->mode = RTE_FC_RX_PAUSE;
6052                 break;
6053         case HNS3_FC_NONE:
6054         default:
6055                 fc_conf->mode = RTE_FC_NONE;
6056                 break;
6057         }
6058
6059         fc_conf->pause_time = pf->pause_time;
6060         fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
6061
6062         return 0;
6063 }
6064
6065 static int
6066 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
6067 {
6068         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
6069
6070         if (!pf->support_fc_autoneg) {
6071                 if (autoneg != 0) {
6072                         hns3_err(hw, "unsupported fc auto-negotiation setting.");
6073                         return -EOPNOTSUPP;
6074                 }
6075
6076                 /*
6077                  * Flow control auto-negotiation of the NIC is not supported,
6078                  * but other auto-negotiation features may be supported.
6079                  */
6080                 if (autoneg != hw->mac.link_autoneg) {
6081                         hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
6082                         return -EOPNOTSUPP;
6083                 }
6084
6085                 return 0;
6086         }
6087
6088         /*
6089          * If flow control auto-negotiation of the NIC is supported, all
6090          * auto-negotiation features are supported.
6091          */
6092         if (autoneg != hw->mac.link_autoneg) {
6093                 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
6094                 return -EOPNOTSUPP;
6095         }
6096
6097         return 0;
6098 }
6099
6100 static int
6101 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6102 {
6103         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6104         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6105         int ret;
6106
6107         if (fc_conf->high_water || fc_conf->low_water ||
6108             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
6109                 hns3_err(hw, "Unsupported flow control settings specified, "
6110                          "high_water(%u), low_water(%u), send_xon(%u) and "
6111                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6112                          fc_conf->high_water, fc_conf->low_water,
6113                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
6114                 return -EINVAL;
6115         }
6116
6117         ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
6118         if (ret)
6119                 return ret;
6120
6121         if (!fc_conf->pause_time) {
6122                 hns3_err(hw, "Invalid pause time %u setting.",
6123                          fc_conf->pause_time);
6124                 return -EINVAL;
6125         }
6126
6127         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6128             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
6129                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
6130                          "current_fc_status = %d", hw->current_fc_status);
6131                 return -EOPNOTSUPP;
6132         }
6133
6134         if (hw->num_tc > 1 && !pf->support_multi_tc_pause) {
6135                 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
6136                 return -EOPNOTSUPP;
6137         }
6138
6139         rte_spinlock_lock(&hw->lock);
6140         ret = hns3_fc_enable(dev, fc_conf);
6141         rte_spinlock_unlock(&hw->lock);
6142
6143         return ret;
6144 }
6145
6146 static int
6147 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
6148                             struct rte_eth_pfc_conf *pfc_conf)
6149 {
6150         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6151         int ret;
6152
6153         if (!hns3_dev_dcb_supported(hw)) {
6154                 hns3_err(hw, "This port does not support dcb configurations.");
6155                 return -EOPNOTSUPP;
6156         }
6157
6158         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
6159             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
6160                 hns3_err(hw, "Unsupported flow control settings specified, "
6161                          "high_water(%u), low_water(%u), send_xon(%u) and "
6162                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6163                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
6164                          pfc_conf->fc.send_xon,
6165                          pfc_conf->fc.mac_ctrl_frame_fwd);
6166                 return -EINVAL;
6167         }
6168         if (pfc_conf->fc.autoneg) {
6169                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
6170                 return -EINVAL;
6171         }
6172         if (pfc_conf->fc.pause_time == 0) {
6173                 hns3_err(hw, "Invalid pause time %u setting.",
6174                          pfc_conf->fc.pause_time);
6175                 return -EINVAL;
6176         }
6177
6178         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6179             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
6180                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
6181                              "current_fc_status = %d", hw->current_fc_status);
6182                 return -EOPNOTSUPP;
6183         }
6184
6185         rte_spinlock_lock(&hw->lock);
6186         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
6187         rte_spinlock_unlock(&hw->lock);
6188
6189         return ret;
6190 }
6191
6192 static int
6193 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
6194 {
6195         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6196         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6197         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
6198         int i;
6199
6200         rte_spinlock_lock(&hw->lock);
6201         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
6202                 dcb_info->nb_tcs = pf->local_max_tc;
6203         else
6204                 dcb_info->nb_tcs = 1;
6205
6206         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
6207                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
6208         for (i = 0; i < dcb_info->nb_tcs; i++)
6209                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
6210
6211         for (i = 0; i < hw->num_tc; i++) {
6212                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
6213                 dcb_info->tc_queue.tc_txq[0][i].base =
6214                                                 hw->tc_queue[i].tqp_offset;
6215                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
6216                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
6217                                                 hw->tc_queue[i].tqp_count;
6218         }
6219         rte_spinlock_unlock(&hw->lock);
6220
6221         return 0;
6222 }
6223
6224 static int
6225 hns3_reinit_dev(struct hns3_adapter *hns)
6226 {
6227         struct hns3_hw *hw = &hns->hw;
6228         int ret;
6229
6230         ret = hns3_cmd_init(hw);
6231         if (ret) {
6232                 hns3_err(hw, "Failed to init cmd: %d", ret);
6233                 return ret;
6234         }
6235
6236         ret = hns3_reset_all_tqps(hns);
6237         if (ret) {
6238                 hns3_err(hw, "Failed to reset all queues: %d", ret);
6239                 return ret;
6240         }
6241
6242         ret = hns3_init_hardware(hns);
6243         if (ret) {
6244                 hns3_err(hw, "Failed to init hardware: %d", ret);
6245                 return ret;
6246         }
6247
6248         ret = hns3_enable_hw_error_intr(hns, true);
6249         if (ret) {
6250                 hns3_err(hw, "fail to enable hw error interrupts: %d",
6251                              ret);
6252                 return ret;
6253         }
6254         hns3_info(hw, "Reset done, driver initialization finished.");
6255
6256         return 0;
6257 }
6258
6259 static bool
6260 is_pf_reset_done(struct hns3_hw *hw)
6261 {
6262         uint32_t val, reg, reg_bit;
6263
6264         switch (hw->reset.level) {
6265         case HNS3_IMP_RESET:
6266                 reg = HNS3_GLOBAL_RESET_REG;
6267                 reg_bit = HNS3_IMP_RESET_BIT;
6268                 break;
6269         case HNS3_GLOBAL_RESET:
6270                 reg = HNS3_GLOBAL_RESET_REG;
6271                 reg_bit = HNS3_GLOBAL_RESET_BIT;
6272                 break;
6273         case HNS3_FUNC_RESET:
6274                 reg = HNS3_FUN_RST_ING;
6275                 reg_bit = HNS3_FUN_RST_ING_B;
6276                 break;
6277         case HNS3_FLR_RESET:
6278         default:
6279                 hns3_err(hw, "Wait for unsupported reset level: %d",
6280                          hw->reset.level);
6281                 return true;
6282         }
6283         val = hns3_read_dev(hw, reg);
6284         if (hns3_get_bit(val, reg_bit))
6285                 return false;
6286         else
6287                 return true;
6288 }
6289
6290 bool
6291 hns3_is_reset_pending(struct hns3_adapter *hns)
6292 {
6293         struct hns3_hw *hw = &hns->hw;
6294         enum hns3_reset_level reset;
6295
6296         hns3_check_event_cause(hns, NULL);
6297         reset = hns3_get_reset_level(hns, &hw->reset.pending);
6298         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6299             hw->reset.level < reset) {
6300                 hns3_warn(hw, "High level reset %d is pending", reset);
6301                 return true;
6302         }
6303         reset = hns3_get_reset_level(hns, &hw->reset.request);
6304         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6305             hw->reset.level < reset) {
6306                 hns3_warn(hw, "High level reset %d is request", reset);
6307                 return true;
6308         }
6309         return false;
6310 }
6311
6312 static int
6313 hns3_wait_hardware_ready(struct hns3_adapter *hns)
6314 {
6315         struct hns3_hw *hw = &hns->hw;
6316         struct hns3_wait_data *wait_data = hw->reset.wait_data;
6317         struct timeval tv;
6318
6319         if (wait_data->result == HNS3_WAIT_SUCCESS)
6320                 return 0;
6321         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
6322                 hns3_clock_gettime(&tv);
6323                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
6324                           tv.tv_sec, tv.tv_usec);
6325                 return -ETIME;
6326         } else if (wait_data->result == HNS3_WAIT_REQUEST)
6327                 return -EAGAIN;
6328
6329         wait_data->hns = hns;
6330         wait_data->check_completion = is_pf_reset_done;
6331         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
6332                                 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms();
6333         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
6334         wait_data->count = HNS3_RESET_WAIT_CNT;
6335         wait_data->result = HNS3_WAIT_REQUEST;
6336         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
6337         return -EAGAIN;
6338 }
6339
6340 static int
6341 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
6342 {
6343         struct hns3_cmd_desc desc;
6344         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6345
6346         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6347         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6348         req->fun_reset_vfid = func_id;
6349
6350         return hns3_cmd_send(hw, &desc, 1);
6351 }
6352
6353 static int
6354 hns3_imp_reset_cmd(struct hns3_hw *hw)
6355 {
6356         struct hns3_cmd_desc desc;
6357
6358         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6359         desc.data[0] = 0xeedd;
6360
6361         return hns3_cmd_send(hw, &desc, 1);
6362 }
6363
6364 static void
6365 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6366 {
6367         struct hns3_hw *hw = &hns->hw;
6368         struct timeval tv;
6369         uint32_t val;
6370
6371         hns3_clock_gettime(&tv);
6372         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6373             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6374                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6375                           tv.tv_sec, tv.tv_usec);
6376                 return;
6377         }
6378
6379         switch (reset_level) {
6380         case HNS3_IMP_RESET:
6381                 hns3_imp_reset_cmd(hw);
6382                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6383                           tv.tv_sec, tv.tv_usec);
6384                 break;
6385         case HNS3_GLOBAL_RESET:
6386                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6387                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6388                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6389                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6390                           tv.tv_sec, tv.tv_usec);
6391                 break;
6392         case HNS3_FUNC_RESET:
6393                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6394                           tv.tv_sec, tv.tv_usec);
6395                 /* schedule again to check later */
6396                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6397                 hns3_schedule_reset(hns);
6398                 break;
6399         default:
6400                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6401                 return;
6402         }
6403         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6404 }
6405
6406 static enum hns3_reset_level
6407 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6408 {
6409         struct hns3_hw *hw = &hns->hw;
6410         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6411
6412         /* Return the highest priority reset level amongst all */
6413         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6414                 reset_level = HNS3_IMP_RESET;
6415         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6416                 reset_level = HNS3_GLOBAL_RESET;
6417         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6418                 reset_level = HNS3_FUNC_RESET;
6419         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6420                 reset_level = HNS3_FLR_RESET;
6421
6422         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6423                 return HNS3_NONE_RESET;
6424
6425         return reset_level;
6426 }
6427
6428 static void
6429 hns3_record_imp_error(struct hns3_adapter *hns)
6430 {
6431         struct hns3_hw *hw = &hns->hw;
6432         uint32_t reg_val;
6433
6434         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6435         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6436                 hns3_warn(hw, "Detected IMP RD poison!");
6437                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6438                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6439         }
6440
6441         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6442                 hns3_warn(hw, "Detected IMP CMDQ error!");
6443                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6444                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6445         }
6446 }
6447
6448 static int
6449 hns3_prepare_reset(struct hns3_adapter *hns)
6450 {
6451         struct hns3_hw *hw = &hns->hw;
6452         uint32_t reg_val;
6453         int ret;
6454
6455         switch (hw->reset.level) {
6456         case HNS3_FUNC_RESET:
6457                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6458                 if (ret)
6459                         return ret;
6460
6461                 /*
6462                  * After performaning pf reset, it is not necessary to do the
6463                  * mailbox handling or send any command to firmware, because
6464                  * any mailbox handling or command to firmware is only valid
6465                  * after hns3_cmd_init is called.
6466                  */
6467                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6468                 hw->reset.stats.request_cnt++;
6469                 break;
6470         case HNS3_IMP_RESET:
6471                 hns3_record_imp_error(hns);
6472                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6473                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6474                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6475                 break;
6476         default:
6477                 break;
6478         }
6479         return 0;
6480 }
6481
6482 static int
6483 hns3_set_rst_done(struct hns3_hw *hw)
6484 {
6485         struct hns3_pf_rst_done_cmd *req;
6486         struct hns3_cmd_desc desc;
6487
6488         req = (struct hns3_pf_rst_done_cmd *)desc.data;
6489         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6490         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6491         return hns3_cmd_send(hw, &desc, 1);
6492 }
6493
6494 static int
6495 hns3_stop_service(struct hns3_adapter *hns)
6496 {
6497         struct hns3_hw *hw = &hns->hw;
6498         struct rte_eth_dev *eth_dev;
6499
6500         eth_dev = &rte_eth_devices[hw->data->port_id];
6501         hw->mac.link_status = ETH_LINK_DOWN;
6502         if (hw->adapter_state == HNS3_NIC_STARTED) {
6503                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6504                 hns3_update_linkstatus_and_event(hw, false);
6505         }
6506
6507         hns3_set_rxtx_function(eth_dev);
6508         rte_wmb();
6509         /* Disable datapath on secondary process. */
6510         hns3_mp_req_stop_rxtx(eth_dev);
6511         rte_delay_ms(hw->cfg_max_queues);
6512
6513         rte_spinlock_lock(&hw->lock);
6514         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6515             hw->adapter_state == HNS3_NIC_STOPPING) {
6516                 hns3_enable_all_queues(hw, false);
6517                 hns3_do_stop(hns);
6518                 hw->reset.mbuf_deferred_free = true;
6519         } else
6520                 hw->reset.mbuf_deferred_free = false;
6521
6522         /*
6523          * It is cumbersome for hardware to pick-and-choose entries for deletion
6524          * from table space. Hence, for function reset software intervention is
6525          * required to delete the entries
6526          */
6527         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6528                 hns3_configure_all_mc_mac_addr(hns, true);
6529         rte_spinlock_unlock(&hw->lock);
6530
6531         return 0;
6532 }
6533
6534 static int
6535 hns3_start_service(struct hns3_adapter *hns)
6536 {
6537         struct hns3_hw *hw = &hns->hw;
6538         struct rte_eth_dev *eth_dev;
6539
6540         if (hw->reset.level == HNS3_IMP_RESET ||
6541             hw->reset.level == HNS3_GLOBAL_RESET)
6542                 hns3_set_rst_done(hw);
6543         eth_dev = &rte_eth_devices[hw->data->port_id];
6544         hns3_set_rxtx_function(eth_dev);
6545         hns3_mp_req_start_rxtx(eth_dev);
6546         if (hw->adapter_state == HNS3_NIC_STARTED) {
6547                 /*
6548                  * This API parent function already hold the hns3_hw.lock, the
6549                  * hns3_service_handler may report lse, in bonding application
6550                  * it will call driver's ops which may acquire the hns3_hw.lock
6551                  * again, thus lead to deadlock.
6552                  * We defer calls hns3_service_handler to avoid the deadlock.
6553                  */
6554                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6555                                   hns3_service_handler, eth_dev);
6556
6557                 /* Enable interrupt of all rx queues before enabling queues */
6558                 hns3_dev_all_rx_queue_intr_enable(hw, true);
6559                 /*
6560                  * Enable state of each rxq and txq will be recovered after
6561                  * reset, so we need to restore them before enable all tqps;
6562                  */
6563                 hns3_restore_tqp_enable_state(hw);
6564                 /*
6565                  * When finished the initialization, enable queues to receive
6566                  * and transmit packets.
6567                  */
6568                 hns3_enable_all_queues(hw, true);
6569         }
6570
6571         return 0;
6572 }
6573
6574 static int
6575 hns3_restore_conf(struct hns3_adapter *hns)
6576 {
6577         struct hns3_hw *hw = &hns->hw;
6578         int ret;
6579
6580         ret = hns3_configure_all_mac_addr(hns, false);
6581         if (ret)
6582                 return ret;
6583
6584         ret = hns3_configure_all_mc_mac_addr(hns, false);
6585         if (ret)
6586                 goto err_mc_mac;
6587
6588         ret = hns3_dev_promisc_restore(hns);
6589         if (ret)
6590                 goto err_promisc;
6591
6592         ret = hns3_restore_vlan_table(hns);
6593         if (ret)
6594                 goto err_promisc;
6595
6596         ret = hns3_restore_vlan_conf(hns);
6597         if (ret)
6598                 goto err_promisc;
6599
6600         ret = hns3_restore_all_fdir_filter(hns);
6601         if (ret)
6602                 goto err_promisc;
6603
6604         ret = hns3_restore_ptp(hns);
6605         if (ret)
6606                 goto err_promisc;
6607
6608         ret = hns3_restore_rx_interrupt(hw);
6609         if (ret)
6610                 goto err_promisc;
6611
6612         ret = hns3_restore_gro_conf(hw);
6613         if (ret)
6614                 goto err_promisc;
6615
6616         ret = hns3_restore_fec(hw);
6617         if (ret)
6618                 goto err_promisc;
6619
6620         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6621                 ret = hns3_do_start(hns, false);
6622                 if (ret)
6623                         goto err_promisc;
6624                 hns3_info(hw, "hns3 dev restart successful!");
6625         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6626                 hw->adapter_state = HNS3_NIC_CONFIGURED;
6627         return 0;
6628
6629 err_promisc:
6630         hns3_configure_all_mc_mac_addr(hns, true);
6631 err_mc_mac:
6632         hns3_configure_all_mac_addr(hns, true);
6633         return ret;
6634 }
6635
6636 static void
6637 hns3_reset_service(void *param)
6638 {
6639         struct hns3_adapter *hns = (struct hns3_adapter *)param;
6640         struct hns3_hw *hw = &hns->hw;
6641         enum hns3_reset_level reset_level;
6642         struct timeval tv_delta;
6643         struct timeval tv_start;
6644         struct timeval tv;
6645         uint64_t msec;
6646         int ret;
6647
6648         /*
6649          * The interrupt is not triggered within the delay time.
6650          * The interrupt may have been lost. It is necessary to handle
6651          * the interrupt to recover from the error.
6652          */
6653         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6654                             SCHEDULE_DEFERRED) {
6655                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6656                                   __ATOMIC_RELAXED);
6657                 hns3_err(hw, "Handling interrupts in delayed tasks");
6658                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6659                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6660                 if (reset_level == HNS3_NONE_RESET) {
6661                         hns3_err(hw, "No reset level is set, try IMP reset");
6662                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6663                 }
6664         }
6665         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6666
6667         /*
6668          * Check if there is any ongoing reset in the hardware. This status can
6669          * be checked from reset_pending. If there is then, we need to wait for
6670          * hardware to complete reset.
6671          *    a. If we are able to figure out in reasonable time that hardware
6672          *       has fully resetted then, we can proceed with driver, client
6673          *       reset.
6674          *    b. else, we can come back later to check this status so re-sched
6675          *       now.
6676          */
6677         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6678         if (reset_level != HNS3_NONE_RESET) {
6679                 hns3_clock_gettime(&tv_start);
6680                 ret = hns3_reset_process(hns, reset_level);
6681                 hns3_clock_gettime(&tv);
6682                 timersub(&tv, &tv_start, &tv_delta);
6683                 msec = hns3_clock_calctime_ms(&tv_delta);
6684                 if (msec > HNS3_RESET_PROCESS_MS)
6685                         hns3_err(hw, "%d handle long time delta %" PRIu64
6686                                      " ms time=%ld.%.6ld",
6687                                  hw->reset.level, msec,
6688                                  tv.tv_sec, tv.tv_usec);
6689                 if (ret == -EAGAIN)
6690                         return;
6691         }
6692
6693         /* Check if we got any *new* reset requests to be honored */
6694         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6695         if (reset_level != HNS3_NONE_RESET)
6696                 hns3_msix_process(hns, reset_level);
6697 }
6698
6699 static unsigned int
6700 hns3_get_speed_capa_num(uint16_t device_id)
6701 {
6702         unsigned int num;
6703
6704         switch (device_id) {
6705         case HNS3_DEV_ID_25GE:
6706         case HNS3_DEV_ID_25GE_RDMA:
6707                 num = 2;
6708                 break;
6709         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6710         case HNS3_DEV_ID_200G_RDMA:
6711                 num = 1;
6712                 break;
6713         default:
6714                 num = 0;
6715                 break;
6716         }
6717
6718         return num;
6719 }
6720
6721 static int
6722 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6723                         uint16_t device_id)
6724 {
6725         switch (device_id) {
6726         case HNS3_DEV_ID_25GE:
6727         /* fallthrough */
6728         case HNS3_DEV_ID_25GE_RDMA:
6729                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6730                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6731
6732                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6733                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6734                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6735                 break;
6736         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6737                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6738                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6739                 break;
6740         case HNS3_DEV_ID_200G_RDMA:
6741                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6742                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6743                 break;
6744         default:
6745                 return -ENOTSUP;
6746         }
6747
6748         return 0;
6749 }
6750
6751 static int
6752 hns3_fec_get_capability(struct rte_eth_dev *dev,
6753                         struct rte_eth_fec_capa *speed_fec_capa,
6754                         unsigned int num)
6755 {
6756         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6757         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6758         uint16_t device_id = pci_dev->id.device_id;
6759         unsigned int capa_num;
6760         int ret;
6761
6762         capa_num = hns3_get_speed_capa_num(device_id);
6763         if (capa_num == 0) {
6764                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6765                          device_id);
6766                 return -ENOTSUP;
6767         }
6768
6769         if (speed_fec_capa == NULL || num < capa_num)
6770                 return capa_num;
6771
6772         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6773         if (ret)
6774                 return -ENOTSUP;
6775
6776         return capa_num;
6777 }
6778
6779 static int
6780 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6781 {
6782         struct hns3_config_fec_cmd *req;
6783         struct hns3_cmd_desc desc;
6784         int ret;
6785
6786         /*
6787          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6788          * in device of link speed
6789          * below 10 Gbps.
6790          */
6791         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6792                 *state = 0;
6793                 return 0;
6794         }
6795
6796         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6797         req = (struct hns3_config_fec_cmd *)desc.data;
6798         ret = hns3_cmd_send(hw, &desc, 1);
6799         if (ret) {
6800                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6801                          ret);
6802                 return ret;
6803         }
6804
6805         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6806         return 0;
6807 }
6808
6809 static int
6810 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6811 {
6812         struct hns3_sfp_info_cmd *resp;
6813         uint32_t tmp_fec_capa;
6814         uint8_t auto_state;
6815         struct hns3_cmd_desc desc;
6816         int ret;
6817
6818         /*
6819          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6820          * configured FEC mode is returned.
6821          * If link is up, current FEC mode is returned.
6822          */
6823         if (hw->mac.link_status == ETH_LINK_DOWN) {
6824                 ret = get_current_fec_auto_state(hw, &auto_state);
6825                 if (ret)
6826                         return ret;
6827
6828                 if (auto_state == 0x1) {
6829                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6830                         return 0;
6831                 }
6832         }
6833
6834         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6835         resp = (struct hns3_sfp_info_cmd *)desc.data;
6836         resp->query_type = HNS3_ACTIVE_QUERY;
6837
6838         ret = hns3_cmd_send(hw, &desc, 1);
6839         if (ret == -EOPNOTSUPP) {
6840                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6841                 return ret;
6842         } else if (ret) {
6843                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6844                 return ret;
6845         }
6846
6847         /*
6848          * FEC mode order defined in hns3 hardware is inconsistend with
6849          * that defined in the ethdev library. So the sequence needs
6850          * to be converted.
6851          */
6852         switch (resp->active_fec) {
6853         case HNS3_HW_FEC_MODE_NOFEC:
6854                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6855                 break;
6856         case HNS3_HW_FEC_MODE_BASER:
6857                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6858                 break;
6859         case HNS3_HW_FEC_MODE_RS:
6860                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6861                 break;
6862         default:
6863                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6864                 break;
6865         }
6866
6867         *fec_capa = tmp_fec_capa;
6868         return 0;
6869 }
6870
6871 static int
6872 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6873 {
6874         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6875
6876         return hns3_fec_get_internal(hw, fec_capa);
6877 }
6878
6879 static int
6880 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6881 {
6882         struct hns3_config_fec_cmd *req;
6883         struct hns3_cmd_desc desc;
6884         int ret;
6885
6886         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6887
6888         req = (struct hns3_config_fec_cmd *)desc.data;
6889         switch (mode) {
6890         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6891                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6892                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6893                 break;
6894         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6895                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6896                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6897                 break;
6898         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6899                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6900                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6901                 break;
6902         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6903                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6904                 break;
6905         default:
6906                 return 0;
6907         }
6908         ret = hns3_cmd_send(hw, &desc, 1);
6909         if (ret)
6910                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6911
6912         return ret;
6913 }
6914
6915 static uint32_t
6916 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6917 {
6918         struct hns3_mac *mac = &hw->mac;
6919         uint32_t cur_capa;
6920
6921         switch (mac->link_speed) {
6922         case ETH_SPEED_NUM_10G:
6923                 cur_capa = fec_capa[1].capa;
6924                 break;
6925         case ETH_SPEED_NUM_25G:
6926         case ETH_SPEED_NUM_100G:
6927         case ETH_SPEED_NUM_200G:
6928                 cur_capa = fec_capa[0].capa;
6929                 break;
6930         default:
6931                 cur_capa = 0;
6932                 break;
6933         }
6934
6935         return cur_capa;
6936 }
6937
6938 static bool
6939 is_fec_mode_one_bit_set(uint32_t mode)
6940 {
6941         int cnt = 0;
6942         uint8_t i;
6943
6944         for (i = 0; i < sizeof(mode); i++)
6945                 if (mode >> i & 0x1)
6946                         cnt++;
6947
6948         return cnt == 1 ? true : false;
6949 }
6950
6951 static int
6952 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6953 {
6954 #define FEC_CAPA_NUM 2
6955         struct hns3_adapter *hns = dev->data->dev_private;
6956         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6957         struct hns3_pf *pf = &hns->pf;
6958
6959         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6960         uint32_t cur_capa;
6961         uint32_t num = FEC_CAPA_NUM;
6962         int ret;
6963
6964         ret = hns3_fec_get_capability(dev, fec_capa, num);
6965         if (ret < 0)
6966                 return ret;
6967
6968         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6969         if (!is_fec_mode_one_bit_set(mode)) {
6970                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, "
6971                              "FEC mode should be only one bit set", mode);
6972                 return -EINVAL;
6973         }
6974
6975         /*
6976          * Check whether the configured mode is within the FEC capability.
6977          * If not, the configured mode will not be supported.
6978          */
6979         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6980         if (!(cur_capa & mode)) {
6981                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6982                 return -EINVAL;
6983         }
6984
6985         rte_spinlock_lock(&hw->lock);
6986         ret = hns3_set_fec_hw(hw, mode);
6987         if (ret) {
6988                 rte_spinlock_unlock(&hw->lock);
6989                 return ret;
6990         }
6991
6992         pf->fec_mode = mode;
6993         rte_spinlock_unlock(&hw->lock);
6994
6995         return 0;
6996 }
6997
6998 static int
6999 hns3_restore_fec(struct hns3_hw *hw)
7000 {
7001         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7002         struct hns3_pf *pf = &hns->pf;
7003         uint32_t mode = pf->fec_mode;
7004         int ret;
7005
7006         ret = hns3_set_fec_hw(hw, mode);
7007         if (ret)
7008                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
7009                          mode, ret);
7010
7011         return ret;
7012 }
7013
7014 static int
7015 hns3_query_dev_fec_info(struct hns3_hw *hw)
7016 {
7017         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7018         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
7019         int ret;
7020
7021         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
7022         if (ret)
7023                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
7024
7025         return ret;
7026 }
7027
7028 static bool
7029 hns3_optical_module_existed(struct hns3_hw *hw)
7030 {
7031         struct hns3_cmd_desc desc;
7032         bool existed;
7033         int ret;
7034
7035         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
7036         ret = hns3_cmd_send(hw, &desc, 1);
7037         if (ret) {
7038                 hns3_err(hw,
7039                          "fail to get optical module exist state, ret = %d.\n",
7040                          ret);
7041                 return false;
7042         }
7043         existed = !!desc.data[0];
7044
7045         return existed;
7046 }
7047
7048 static int
7049 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
7050                                 uint32_t len, uint8_t *data)
7051 {
7052 #define HNS3_SFP_INFO_CMD_NUM 6
7053 #define HNS3_SFP_INFO_MAX_LEN \
7054         (HNS3_SFP_INFO_BD0_LEN + \
7055         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
7056         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
7057         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
7058         uint16_t read_len;
7059         uint16_t copy_len;
7060         int ret;
7061         int i;
7062
7063         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7064                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
7065                                           true);
7066                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
7067                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
7068         }
7069
7070         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
7071         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
7072         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
7073         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
7074
7075         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
7076         if (ret) {
7077                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
7078                                 ret);
7079                 return ret;
7080         }
7081
7082         /* The data format in BD0 is different with the others. */
7083         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
7084         memcpy(data, sfp_info_bd0->data, copy_len);
7085         read_len = copy_len;
7086
7087         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7088                 if (read_len >= len)
7089                         break;
7090
7091                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
7092                 memcpy(data + read_len, desc[i].data, copy_len);
7093                 read_len += copy_len;
7094         }
7095
7096         return (int)read_len;
7097 }
7098
7099 static int
7100 hns3_get_module_eeprom(struct rte_eth_dev *dev,
7101                        struct rte_dev_eeprom_info *info)
7102 {
7103         struct hns3_adapter *hns = dev->data->dev_private;
7104         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7105         uint32_t offset = info->offset;
7106         uint32_t len = info->length;
7107         uint8_t *data = info->data;
7108         uint32_t read_len = 0;
7109
7110         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
7111                 return -ENOTSUP;
7112
7113         if (!hns3_optical_module_existed(hw)) {
7114                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
7115                 return -EIO;
7116         }
7117
7118         while (read_len < len) {
7119                 int ret;
7120                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
7121                                                   len - read_len,
7122                                                   data + read_len);
7123                 if (ret < 0)
7124                         return -EIO;
7125                 read_len += ret;
7126         }
7127
7128         return 0;
7129 }
7130
7131 static int
7132 hns3_get_module_info(struct rte_eth_dev *dev,
7133                      struct rte_eth_dev_module_info *modinfo)
7134 {
7135 #define HNS3_SFF8024_ID_SFP             0x03
7136 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
7137 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
7138 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
7139 #define HNS3_SFF_8636_V1_3              0x03
7140         struct hns3_adapter *hns = dev->data->dev_private;
7141         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7142         struct rte_dev_eeprom_info info;
7143         struct hns3_sfp_type sfp_type;
7144         int ret;
7145
7146         memset(&sfp_type, 0, sizeof(sfp_type));
7147         memset(&info, 0, sizeof(info));
7148         info.data = (uint8_t *)&sfp_type;
7149         info.length = sizeof(sfp_type);
7150         ret = hns3_get_module_eeprom(dev, &info);
7151         if (ret)
7152                 return ret;
7153
7154         switch (sfp_type.type) {
7155         case HNS3_SFF8024_ID_SFP:
7156                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7157                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7158                 break;
7159         case HNS3_SFF8024_ID_QSFP_8438:
7160                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7161                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7162                 break;
7163         case HNS3_SFF8024_ID_QSFP_8436_8636:
7164                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
7165                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
7166                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7167                 } else {
7168                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
7169                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7170                 }
7171                 break;
7172         case HNS3_SFF8024_ID_QSFP28_8636:
7173                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7174                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7175                 break;
7176         default:
7177                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
7178                          sfp_type.type, sfp_type.ext_type);
7179                 return -EINVAL;
7180         }
7181
7182         return 0;
7183 }
7184
7185 void
7186 hns3_clock_gettime(struct timeval *tv)
7187 {
7188 #ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */
7189 #define CLOCK_TYPE CLOCK_MONOTONIC_RAW
7190 #else
7191 #define CLOCK_TYPE CLOCK_MONOTONIC
7192 #endif
7193 #define NSEC_TO_USEC_DIV 1000
7194
7195         struct timespec spec;
7196         (void)clock_gettime(CLOCK_TYPE, &spec);
7197
7198         tv->tv_sec = spec.tv_sec;
7199         tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV;
7200 }
7201
7202 uint64_t
7203 hns3_clock_calctime_ms(struct timeval *tv)
7204 {
7205         return (uint64_t)tv->tv_sec * MSEC_PER_SEC +
7206                 tv->tv_usec / USEC_PER_MSEC;
7207 }
7208
7209 uint64_t
7210 hns3_clock_gettime_ms(void)
7211 {
7212         struct timeval tv;
7213
7214         hns3_clock_gettime(&tv);
7215         return hns3_clock_calctime_ms(&tv);
7216 }
7217
7218 static int
7219 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
7220 {
7221         uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
7222
7223         RTE_SET_USED(key);
7224
7225         if (strcmp(value, "vec") == 0)
7226                 hint = HNS3_IO_FUNC_HINT_VEC;
7227         else if (strcmp(value, "sve") == 0)
7228                 hint = HNS3_IO_FUNC_HINT_SVE;
7229         else if (strcmp(value, "simple") == 0)
7230                 hint = HNS3_IO_FUNC_HINT_SIMPLE;
7231         else if (strcmp(value, "common") == 0)
7232                 hint = HNS3_IO_FUNC_HINT_COMMON;
7233
7234         /* If the hint is valid then update output parameters */
7235         if (hint != HNS3_IO_FUNC_HINT_NONE)
7236                 *(uint32_t *)extra_args = hint;
7237
7238         return 0;
7239 }
7240
7241 static const char *
7242 hns3_get_io_hint_func_name(uint32_t hint)
7243 {
7244         switch (hint) {
7245         case HNS3_IO_FUNC_HINT_VEC:
7246                 return "vec";
7247         case HNS3_IO_FUNC_HINT_SVE:
7248                 return "sve";
7249         case HNS3_IO_FUNC_HINT_SIMPLE:
7250                 return "simple";
7251         case HNS3_IO_FUNC_HINT_COMMON:
7252                 return "common";
7253         default:
7254                 return "none";
7255         }
7256 }
7257
7258 static int
7259 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args)
7260 {
7261         uint64_t val;
7262
7263         RTE_SET_USED(key);
7264
7265         val = strtoull(value, NULL, 16);
7266         *(uint64_t *)extra_args = val;
7267
7268         return 0;
7269 }
7270
7271 void
7272 hns3_parse_devargs(struct rte_eth_dev *dev)
7273 {
7274         struct hns3_adapter *hns = dev->data->dev_private;
7275         uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7276         uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7277         struct hns3_hw *hw = &hns->hw;
7278         uint64_t dev_caps_mask = 0;
7279         struct rte_kvargs *kvlist;
7280
7281         if (dev->device->devargs == NULL)
7282                 return;
7283
7284         kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
7285         if (!kvlist)
7286                 return;
7287
7288         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
7289                            &hns3_parse_io_hint_func, &rx_func_hint);
7290         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
7291                            &hns3_parse_io_hint_func, &tx_func_hint);
7292         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK,
7293                            &hns3_parse_dev_caps_mask, &dev_caps_mask);
7294         rte_kvargs_free(kvlist);
7295
7296         if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7297                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
7298                           hns3_get_io_hint_func_name(rx_func_hint));
7299         hns->rx_func_hint = rx_func_hint;
7300         if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7301                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
7302                           hns3_get_io_hint_func_name(tx_func_hint));
7303         hns->tx_func_hint = tx_func_hint;
7304
7305         if (dev_caps_mask != 0)
7306                 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".",
7307                           HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask);
7308         hns->dev_caps_mask = dev_caps_mask;
7309 }
7310
7311 static const struct eth_dev_ops hns3_eth_dev_ops = {
7312         .dev_configure      = hns3_dev_configure,
7313         .dev_start          = hns3_dev_start,
7314         .dev_stop           = hns3_dev_stop,
7315         .dev_close          = hns3_dev_close,
7316         .promiscuous_enable = hns3_dev_promiscuous_enable,
7317         .promiscuous_disable = hns3_dev_promiscuous_disable,
7318         .allmulticast_enable  = hns3_dev_allmulticast_enable,
7319         .allmulticast_disable = hns3_dev_allmulticast_disable,
7320         .mtu_set            = hns3_dev_mtu_set,
7321         .stats_get          = hns3_stats_get,
7322         .stats_reset        = hns3_stats_reset,
7323         .xstats_get         = hns3_dev_xstats_get,
7324         .xstats_get_names   = hns3_dev_xstats_get_names,
7325         .xstats_reset       = hns3_dev_xstats_reset,
7326         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
7327         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
7328         .dev_infos_get          = hns3_dev_infos_get,
7329         .fw_version_get         = hns3_fw_version_get,
7330         .rx_queue_setup         = hns3_rx_queue_setup,
7331         .tx_queue_setup         = hns3_tx_queue_setup,
7332         .rx_queue_release       = hns3_dev_rx_queue_release,
7333         .tx_queue_release       = hns3_dev_tx_queue_release,
7334         .rx_queue_start         = hns3_dev_rx_queue_start,
7335         .rx_queue_stop          = hns3_dev_rx_queue_stop,
7336         .tx_queue_start         = hns3_dev_tx_queue_start,
7337         .tx_queue_stop          = hns3_dev_tx_queue_stop,
7338         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
7339         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
7340         .rxq_info_get           = hns3_rxq_info_get,
7341         .txq_info_get           = hns3_txq_info_get,
7342         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
7343         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
7344         .flow_ctrl_get          = hns3_flow_ctrl_get,
7345         .flow_ctrl_set          = hns3_flow_ctrl_set,
7346         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
7347         .mac_addr_add           = hns3_add_mac_addr,
7348         .mac_addr_remove        = hns3_remove_mac_addr,
7349         .mac_addr_set           = hns3_set_default_mac_addr,
7350         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
7351         .link_update            = hns3_dev_link_update,
7352         .rss_hash_update        = hns3_dev_rss_hash_update,
7353         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
7354         .reta_update            = hns3_dev_rss_reta_update,
7355         .reta_query             = hns3_dev_rss_reta_query,
7356         .flow_ops_get           = hns3_dev_flow_ops_get,
7357         .vlan_filter_set        = hns3_vlan_filter_set,
7358         .vlan_tpid_set          = hns3_vlan_tpid_set,
7359         .vlan_offload_set       = hns3_vlan_offload_set,
7360         .vlan_pvid_set          = hns3_vlan_pvid_set,
7361         .get_reg                = hns3_get_regs,
7362         .get_module_info        = hns3_get_module_info,
7363         .get_module_eeprom      = hns3_get_module_eeprom,
7364         .get_dcb_info           = hns3_get_dcb_info,
7365         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
7366         .fec_get_capability     = hns3_fec_get_capability,
7367         .fec_get                = hns3_fec_get,
7368         .fec_set                = hns3_fec_set,
7369         .tm_ops_get             = hns3_tm_ops_get,
7370         .tx_done_cleanup        = hns3_tx_done_cleanup,
7371         .timesync_enable            = hns3_timesync_enable,
7372         .timesync_disable           = hns3_timesync_disable,
7373         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
7374         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
7375         .timesync_adjust_time       = hns3_timesync_adjust_time,
7376         .timesync_read_time         = hns3_timesync_read_time,
7377         .timesync_write_time        = hns3_timesync_write_time,
7378 };
7379
7380 static const struct hns3_reset_ops hns3_reset_ops = {
7381         .reset_service       = hns3_reset_service,
7382         .stop_service        = hns3_stop_service,
7383         .prepare_reset       = hns3_prepare_reset,
7384         .wait_hardware_ready = hns3_wait_hardware_ready,
7385         .reinit_dev          = hns3_reinit_dev,
7386         .restore_conf        = hns3_restore_conf,
7387         .start_service       = hns3_start_service,
7388 };
7389
7390 static int
7391 hns3_dev_init(struct rte_eth_dev *eth_dev)
7392 {
7393         struct hns3_adapter *hns = eth_dev->data->dev_private;
7394         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
7395         struct rte_ether_addr *eth_addr;
7396         struct hns3_hw *hw = &hns->hw;
7397         int ret;
7398
7399         PMD_INIT_FUNC_TRACE();
7400
7401         eth_dev->process_private = (struct hns3_process_private *)
7402             rte_zmalloc_socket("hns3_filter_list",
7403                                sizeof(struct hns3_process_private),
7404                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
7405         if (eth_dev->process_private == NULL) {
7406                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
7407                 return -ENOMEM;
7408         }
7409
7410         hns3_flow_init(eth_dev);
7411
7412         hns3_set_rxtx_function(eth_dev);
7413         eth_dev->dev_ops = &hns3_eth_dev_ops;
7414         eth_dev->rx_queue_count = hns3_rx_queue_count;
7415         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7416                 ret = hns3_mp_init_secondary();
7417                 if (ret) {
7418                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
7419                                      "process, ret = %d", ret);
7420                         goto err_mp_init_secondary;
7421                 }
7422                 hw->secondary_cnt++;
7423                 hns3_tx_push_init(eth_dev);
7424                 return 0;
7425         }
7426
7427         ret = hns3_mp_init_primary();
7428         if (ret) {
7429                 PMD_INIT_LOG(ERR,
7430                              "Failed to init for primary process, ret = %d",
7431                              ret);
7432                 goto err_mp_init_primary;
7433         }
7434
7435         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
7436         hns->is_vf = false;
7437         hw->data = eth_dev->data;
7438         hns3_parse_devargs(eth_dev);
7439
7440         /*
7441          * Set default max packet size according to the mtu
7442          * default vale in DPDK frame.
7443          */
7444         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
7445
7446         ret = hns3_reset_init(hw);
7447         if (ret)
7448                 goto err_init_reset;
7449         hw->reset.ops = &hns3_reset_ops;
7450
7451         ret = hns3_init_pf(eth_dev);
7452         if (ret) {
7453                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
7454                 goto err_init_pf;
7455         }
7456
7457         /* Allocate memory for storing MAC addresses */
7458         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
7459                                                sizeof(struct rte_ether_addr) *
7460                                                HNS3_UC_MACADDR_NUM, 0);
7461         if (eth_dev->data->mac_addrs == NULL) {
7462                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
7463                              "to store MAC addresses",
7464                              sizeof(struct rte_ether_addr) *
7465                              HNS3_UC_MACADDR_NUM);
7466                 ret = -ENOMEM;
7467                 goto err_rte_zmalloc;
7468         }
7469
7470         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
7471         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
7472                 rte_eth_random_addr(hw->mac.mac_addr);
7473                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
7474                                 (struct rte_ether_addr *)hw->mac.mac_addr);
7475                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
7476                           "unicast address, using random MAC address %s",
7477                           mac_str);
7478         }
7479         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7480                             &eth_dev->data->mac_addrs[0]);
7481
7482         hw->adapter_state = HNS3_NIC_INITIALIZED;
7483
7484         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7485                             SCHEDULE_PENDING) {
7486                 hns3_err(hw, "Reschedule reset service after dev_init");
7487                 hns3_schedule_reset(hns);
7488         } else {
7489                 /* IMP will wait ready flag before reset */
7490                 hns3_notify_reset_ready(hw, false);
7491         }
7492
7493         hns3_info(hw, "hns3 dev initialization successful!");
7494         return 0;
7495
7496 err_rte_zmalloc:
7497         hns3_uninit_pf(eth_dev);
7498
7499 err_init_pf:
7500         rte_free(hw->reset.wait_data);
7501
7502 err_init_reset:
7503         hns3_mp_uninit_primary();
7504
7505 err_mp_init_primary:
7506 err_mp_init_secondary:
7507         eth_dev->dev_ops = NULL;
7508         eth_dev->rx_pkt_burst = NULL;
7509         eth_dev->rx_descriptor_status = NULL;
7510         eth_dev->tx_pkt_burst = NULL;
7511         eth_dev->tx_pkt_prepare = NULL;
7512         eth_dev->tx_descriptor_status = NULL;
7513         rte_free(eth_dev->process_private);
7514         eth_dev->process_private = NULL;
7515         return ret;
7516 }
7517
7518 static int
7519 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7520 {
7521         struct hns3_adapter *hns = eth_dev->data->dev_private;
7522         struct hns3_hw *hw = &hns->hw;
7523
7524         PMD_INIT_FUNC_TRACE();
7525
7526         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7527                 rte_free(eth_dev->process_private);
7528                 eth_dev->process_private = NULL;
7529                 return 0;
7530         }
7531
7532         if (hw->adapter_state < HNS3_NIC_CLOSING)
7533                 hns3_dev_close(eth_dev);
7534
7535         hw->adapter_state = HNS3_NIC_REMOVED;
7536         return 0;
7537 }
7538
7539 static int
7540 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7541                    struct rte_pci_device *pci_dev)
7542 {
7543         return rte_eth_dev_pci_generic_probe(pci_dev,
7544                                              sizeof(struct hns3_adapter),
7545                                              hns3_dev_init);
7546 }
7547
7548 static int
7549 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7550 {
7551         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7552 }
7553
7554 static const struct rte_pci_id pci_id_hns3_map[] = {
7555         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7556         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7557         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7558         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7559         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7560         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7561         { .vendor_id = 0, }, /* sentinel */
7562 };
7563
7564 static struct rte_pci_driver rte_hns3_pmd = {
7565         .id_table = pci_id_hns3_map,
7566         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7567         .probe = eth_hns3_pci_probe,
7568         .remove = eth_hns3_pci_remove,
7569 };
7570
7571 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7572 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7573 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7574 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7575                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7576                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
7577                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");
7578 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE);
7579 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE);