drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static int hns3_add_mc_addr(struct hns3_hw *hw,
  83                             struct rte_ether_addr *mac_addr);
  84 static int hns3_remove_mc_addr(struct hns3_hw *hw,
  85                             struct rte_ether_addr *mac_addr);
  86
  87 static void
  88 hns3_pf_disable_irq0(struct hns3_hw *hw)
  89 {
  90         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  91 }
  92
  93 static void
  94 hns3_pf_enable_irq0(struct hns3_hw *hw)
  95 {
  96         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  97 }
  98
  99 static enum hns3_evt_cause
 100 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 101 {
 102         struct hns3_hw *hw = &hns->hw;
 103         uint32_t vector0_int_stats;
 104         uint32_t cmdq_src_val;
 105         uint32_t val;
 106         enum hns3_evt_cause ret;
 107
 108         /* fetch the events from their corresponding regs */
 109         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 110         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 111
 112         /*
 113          * Assumption: If by any chance reset and mailbox events are reported
 114          * together then we will only process reset event and defer the
 115          * processing of the mailbox events. Since, we would have not cleared
 116          * RX CMDQ event this time we would receive again another interrupt
 117          * from H/W just for the mailbox.
 118          */
 119         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 120                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 121                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 122                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 123                 if (clearval) {
 124                         hw->reset.stats.imp_cnt++;
 125                         hns3_warn(hw, "IMP reset detected, clear reset status");
 126                 } else {
 127                         hns3_schedule_delayed_reset(hns);
 128                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 129                 }
 130
 131                 ret = HNS3_VECTOR0_EVENT_RST;
 132                 goto out;
 133         }
 134
 135         /* Global reset */
 136         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 137                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 138                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 139                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 140                 if (clearval) {
 141                         hw->reset.stats.global_cnt++;
 142                         hns3_warn(hw, "Global reset detected, clear reset status");
 143                 } else {
 144                         hns3_schedule_delayed_reset(hns);
 145                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 146                 }
 147
 148                 ret = HNS3_VECTOR0_EVENT_RST;
 149                 goto out;
 150         }
 151
 152         /* check for vector0 msix event source */
 153         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 154                 val = vector0_int_stats;
 155                 ret = HNS3_VECTOR0_EVENT_ERR;
 156                 goto out;
 157         }
 158
 159         /* check for vector0 mailbox(=CMDQ RX) event source */
 160         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 161                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 162                 val = cmdq_src_val;
 163                 ret = HNS3_VECTOR0_EVENT_MBX;
 164                 goto out;
 165         }
 166
 167         if (clearval && (vector0_int_stats || cmdq_src_val))
 168                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 169                           vector0_int_stats, cmdq_src_val);
 170         val = vector0_int_stats;
 171         ret = HNS3_VECTOR0_EVENT_OTHER;
 172 out:
 173
 174         if (clearval)
 175                 *clearval = val;
 176         return ret;
 177 }
 178
 179 static void
 180 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 181 {
 182         if (event_type == HNS3_VECTOR0_EVENT_RST)
 183                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 184         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 185                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 186 }
 187
 188 static void
 189 hns3_clear_all_event_cause(struct hns3_hw *hw)
 190 {
 191         uint32_t vector0_int_stats;
 192         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 193
 194         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 195                 hns3_warn(hw, "Probe during IMP reset interrupt");
 196
 197         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 198                 hns3_warn(hw, "Probe during Global reset interrupt");
 199
 200         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 201                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 202                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 203                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 204         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 205 }
 206
 207 static void
 208 hns3_interrupt_handler(void *param)
 209 {
 210         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 211         struct hns3_adapter *hns = dev->data->dev_private;
 212         struct hns3_hw *hw = &hns->hw;
 213         enum hns3_evt_cause event_cause;
 214         uint32_t clearval = 0;
 215
 216         /* Disable interrupt */
 217         hns3_pf_disable_irq0(hw);
 218
 219         event_cause = hns3_check_event_cause(hns, &clearval);
 220
 221         /* vector 0 interrupt is shared with reset and mailbox source events. */
 222         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 223                 hns3_handle_msix_error(hns, &hw->reset.request);
 224                 hns3_schedule_reset(hns);
 225         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 226                 hns3_schedule_reset(hns);
 227         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 228                 hns3_dev_handle_mbx_msg(hw);
 229         else
 230                 hns3_err(hw, "Received unknown event");
 231
 232         hns3_clear_event_cause(hw, event_cause, clearval);
 233         /* Enable interrupt if it is not cause by reset */
 234         hns3_pf_enable_irq0(hw);
 235 }
 236
 237 static int
 238 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 239 {
 240 #define HNS3_VLAN_ID_OFFSET_STEP        160
 241 #define HNS3_VLAN_BYTE_SIZE             8
 242         struct hns3_vlan_filter_pf_cfg_cmd *req;
 243         struct hns3_hw *hw = &hns->hw;
 244         uint8_t vlan_offset_byte_val;
 245         struct hns3_cmd_desc desc;
 246         uint8_t vlan_offset_byte;
 247         uint8_t vlan_offset_base;
 248         int ret;
 249
 250         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 251
 252         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 253         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 254                            HNS3_VLAN_BYTE_SIZE;
 255         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 256
 257         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 258         req->vlan_offset = vlan_offset_base;
 259         req->vlan_cfg = on ? 0 : 1;
 260         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 261
 262         ret = hns3_cmd_send(hw, &desc, 1);
 263         if (ret)
 264                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 265                          vlan_id, ret);
 266
 267         return ret;
 268 }
 269
 270 static void
 271 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 272 {
 273         struct hns3_user_vlan_table *vlan_entry;
 274         struct hns3_pf *pf = &hns->pf;
 275
 276         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 277                 if (vlan_entry->vlan_id == vlan_id) {
 278                         if (vlan_entry->hd_tbl_status)
 279                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 280                         LIST_REMOVE(vlan_entry, next);
 281                         rte_free(vlan_entry);
 282                         break;
 283                 }
 284         }
 285 }
 286
 287 static void
 288 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 289                         bool writen_to_tbl)
 290 {
 291         struct hns3_user_vlan_table *vlan_entry;
 292         struct hns3_hw *hw = &hns->hw;
 293         struct hns3_pf *pf = &hns->pf;
 294
 295         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 296                 if (vlan_entry->vlan_id == vlan_id)
 297                         return;
 298         }
 299
 300         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 301         if (vlan_entry == NULL) {
 302                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 303                 return;
 304         }
 305
 306         vlan_entry->hd_tbl_status = writen_to_tbl;
 307         vlan_entry->vlan_id = vlan_id;
 308
 309         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 310 }
 311
 312 static int
 313 hns3_restore_vlan_table(struct hns3_adapter *hns)
 314 {
 315         struct hns3_user_vlan_table *vlan_entry;
 316         struct hns3_pf *pf = &hns->pf;
 317         uint16_t vlan_id;
 318         int ret = 0;
 319
 320         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 321                 return hns3_vlan_pvid_configure(hns,
 322                                                 pf->port_base_vlan_cfg.pvid, 1);
 323
 324         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 325                 if (vlan_entry->hd_tbl_status) {
 326                         vlan_id = vlan_entry->vlan_id;
 327                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 328                         if (ret)
 329                                 break;
 330                 }
 331         }
 332
 333         return ret;
 334 }
 335
 336 static int
 337 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 338 {
 339         struct hns3_pf *pf = &hns->pf;
 340         bool writen_to_tbl = false;
 341         int ret = 0;
 342
 343         /*
 344          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 345          * for normal packet, deleting vlan id 0 is not allowed.
 346          */
 347         if (on == 0 && vlan_id == 0)
 348                 return 0;
 349
 350         /*
 351          * When port base vlan enabled, we use port base vlan as the vlan
 352          * filter condition. In this case, we don't update vlan filter table
 353          * when user add new vlan or remove exist vlan, just update the
 354          * vlan list. The vlan id in vlan list will be writen in vlan filter
 355          * table until port base vlan disabled
 356          */
 357         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 358                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 359                 writen_to_tbl = true;
 360         }
 361
 362         if (ret == 0 && vlan_id) {
 363                 if (on)
 364                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 365                 else
 366                         hns3_rm_dev_vlan_table(hns, vlan_id);
 367         }
 368         return ret;
 369 }
 370
 371 static int
 372 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 373 {
 374         struct hns3_adapter *hns = dev->data->dev_private;
 375         struct hns3_hw *hw = &hns->hw;
 376         int ret;
 377
 378         rte_spinlock_lock(&hw->lock);
 379         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 380         rte_spinlock_unlock(&hw->lock);
 381         return ret;
 382 }
 383
 384 static int
 385 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 386                          uint16_t tpid)
 387 {
 388         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 389         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 390         struct hns3_hw *hw = &hns->hw;
 391         struct hns3_cmd_desc desc;
 392         int ret;
 393
 394         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 395              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 396                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 397                 return -EINVAL;
 398         }
 399
 400         if (tpid != RTE_ETHER_TYPE_VLAN) {
 401                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 402                 return -EINVAL;
 403         }
 404
 405         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 406         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 407
 408         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 409                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 412                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 413                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 414                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 415                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 416         }
 417
 418         ret = hns3_cmd_send(hw, &desc, 1);
 419         if (ret) {
 420                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 421                          ret);
 422                 return ret;
 423         }
 424
 425         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 426
 427         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 428         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 429         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 430
 431         ret = hns3_cmd_send(hw, &desc, 1);
 432         if (ret)
 433                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 434                          ret);
 435         return ret;
 436 }
 437
 438 static int
 439 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 440                    uint16_t tpid)
 441 {
 442         struct hns3_adapter *hns = dev->data->dev_private;
 443         struct hns3_hw *hw = &hns->hw;
 444         int ret;
 445
 446         rte_spinlock_lock(&hw->lock);
 447         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 448         rte_spinlock_unlock(&hw->lock);
 449         return ret;
 450 }
 451
 452 static int
 453 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 454                              struct hns3_rx_vtag_cfg *vcfg)
 455 {
 456         struct hns3_vport_vtag_rx_cfg_cmd *req;
 457         struct hns3_hw *hw = &hns->hw;
 458         struct hns3_cmd_desc desc;
 459         uint16_t vport_id;
 460         uint8_t bitmap;
 461         int ret;
 462
 463         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 464
 465         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 466         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 467                      vcfg->strip_tag1_en ? 1 : 0);
 468         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 469                      vcfg->strip_tag2_en ? 1 : 0);
 470         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 471                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 472         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 473                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 474
 475         /*
 476          * In current version VF is not supported when PF is driven by DPDK
 477          * driver, just need to configure parameters for PF vport.
 478          */
 479         vport_id = HNS3_PF_FUNC_ID;
 480         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 481         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 482         req->vf_bitmap[req->vf_offset] = bitmap;
 483
 484         ret = hns3_cmd_send(hw, &desc, 1);
 485         if (ret)
 486                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 487         return ret;
 488 }
 489
 490 static void
 491 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 492                            struct hns3_rx_vtag_cfg *vcfg)
 493 {
 494         struct hns3_pf *pf = &hns->pf;
 495         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 496 }
 497
 498 static void
 499 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 500                            struct hns3_tx_vtag_cfg *vcfg)
 501 {
 502         struct hns3_pf *pf = &hns->pf;
 503         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 504 }
 505
 506 static int
 507 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 508 {
 509         struct hns3_rx_vtag_cfg rxvlan_cfg;
 510         struct hns3_pf *pf = &hns->pf;
 511         struct hns3_hw *hw = &hns->hw;
 512         int ret;
 513
 514         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 515                 rxvlan_cfg.strip_tag1_en = false;
 516                 rxvlan_cfg.strip_tag2_en = enable;
 517         } else {
 518                 rxvlan_cfg.strip_tag1_en = enable;
 519                 rxvlan_cfg.strip_tag2_en = true;
 520         }
 521
 522         rxvlan_cfg.vlan1_vlan_prionly = false;
 523         rxvlan_cfg.vlan2_vlan_prionly = false;
 524         rxvlan_cfg.rx_vlan_offload_en = enable;
 525
 526         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 527         if (ret) {
 528                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 529                 return ret;
 530         }
 531
 532         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 533
 534         return ret;
 535 }
 536
 537 static int
 538 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 539                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 540 {
 541         struct hns3_vlan_filter_ctrl_cmd *req;
 542         struct hns3_cmd_desc desc;
 543         int ret;
 544
 545         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 546
 547         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 548         req->vlan_type = vlan_type;
 549         req->vlan_fe = filter_en ? fe_type : 0;
 550         req->vf_id = vf_id;
 551
 552         ret = hns3_cmd_send(hw, &desc, 1);
 553         if (ret)
 554                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 555
 556         return ret;
 557 }
 558
 559 static int
 560 hns3_vlan_filter_init(struct hns3_adapter *hns)
 561 {
 562         struct hns3_hw *hw = &hns->hw;
 563         int ret;
 564
 565         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 566                                         HNS3_FILTER_FE_EGRESS, false,
 567                                         HNS3_PF_FUNC_ID);
 568         if (ret) {
 569                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 570                 return ret;
 571         }
 572
 573         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 574                                         HNS3_FILTER_FE_INGRESS, false,
 575                                         HNS3_PF_FUNC_ID);
 576         if (ret)
 577                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 578
 579         return ret;
 580 }
 581
 582 static int
 583 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 584 {
 585         struct hns3_hw *hw = &hns->hw;
 586         int ret;
 587
 588         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 589                                         HNS3_FILTER_FE_INGRESS, enable,
 590                                         HNS3_PF_FUNC_ID);
 591         if (ret)
 592                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 593                          enable ? "enable" : "disable", ret);
 594
 595         return ret;
 596 }
 597
 598 static int
 599 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 600 {
 601         struct hns3_adapter *hns = dev->data->dev_private;
 602         struct hns3_hw *hw = &hns->hw;
 603         struct rte_eth_rxmode *rxmode;
 604         unsigned int tmp_mask;
 605         bool enable;
 606         int ret = 0;
 607
 608         rte_spinlock_lock(&hw->lock);
 609         rxmode = &dev->data->dev_conf.rxmode;
 610         tmp_mask = (unsigned int)mask;
 611         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 612                 /* ignore vlan filter configuration during promiscuous mode */
 613                 if (!dev->data->promiscuous) {
 614                         /* Enable or disable VLAN filter */
 615                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 616                                  true : false;
 617
 618                         ret = hns3_enable_vlan_filter(hns, enable);
 619                         if (ret) {
 620                                 rte_spinlock_unlock(&hw->lock);
 621                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 622                                          enable ? "enable" : "disable", ret);
 623                                 return ret;
 624                         }
 625                 }
 626         }
 627
 628         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 629                 /* Enable or disable VLAN stripping */
 630                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 631                     true : false;
 632
 633                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 634                 if (ret) {
 635                         rte_spinlock_unlock(&hw->lock);
 636                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 637                                  enable ? "enable" : "disable", ret);
 638                         return ret;
 639                 }
 640         }
 641
 642         rte_spinlock_unlock(&hw->lock);
 643
 644         return ret;
 645 }
 646
 647 static int
 648 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 649                              struct hns3_tx_vtag_cfg *vcfg)
 650 {
 651         struct hns3_vport_vtag_tx_cfg_cmd *req;
 652         struct hns3_cmd_desc desc;
 653         struct hns3_hw *hw = &hns->hw;
 654         uint16_t vport_id;
 655         uint8_t bitmap;
 656         int ret;
 657
 658         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 659
 660         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 661         req->def_vlan_tag1 = vcfg->default_tag1;
 662         req->def_vlan_tag2 = vcfg->default_tag2;
 663         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 664                      vcfg->accept_tag1 ? 1 : 0);
 665         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 666                      vcfg->accept_untag1 ? 1 : 0);
 667         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 668                      vcfg->accept_tag2 ? 1 : 0);
 669         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 670                      vcfg->accept_untag2 ? 1 : 0);
 671         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 672                      vcfg->insert_tag1_en ? 1 : 0);
 673         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 674                      vcfg->insert_tag2_en ? 1 : 0);
 675         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 676
 677         /*
 678          * In current version VF is not supported when PF is driven by DPDK
 679          * driver, just need to configure parameters for PF vport.
 680          */
 681         vport_id = HNS3_PF_FUNC_ID;
 682         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 683         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 684         req->vf_bitmap[req->vf_offset] = bitmap;
 685
 686         ret = hns3_cmd_send(hw, &desc, 1);
 687         if (ret)
 688                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 695                      uint16_t pvid)
 696 {
 697         struct hns3_hw *hw = &hns->hw;
 698         struct hns3_tx_vtag_cfg txvlan_cfg;
 699         int ret;
 700
 701         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 702                 txvlan_cfg.accept_tag1 = true;
 703                 txvlan_cfg.insert_tag1_en = false;
 704                 txvlan_cfg.default_tag1 = 0;
 705         } else {
 706                 txvlan_cfg.accept_tag1 = false;
 707                 txvlan_cfg.insert_tag1_en = true;
 708                 txvlan_cfg.default_tag1 = pvid;
 709         }
 710
 711         txvlan_cfg.accept_untag1 = true;
 712         txvlan_cfg.accept_tag2 = true;
 713         txvlan_cfg.accept_untag2 = true;
 714         txvlan_cfg.insert_tag2_en = false;
 715         txvlan_cfg.default_tag2 = 0;
 716
 717         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 718         if (ret) {
 719                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 720                          ret);
 721                 return ret;
 722         }
 723
 724         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 725         return ret;
 726 }
 727
 728 static void
 729 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 730 {
 731         struct hns3_pf *pf = &hns->pf;
 732
 733         pf->port_base_vlan_cfg.state = on ?
 734             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 735
 736         pf->port_base_vlan_cfg.pvid = pvid;
 737 }
 738
 739 static void
 740 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 741 {
 742         struct hns3_user_vlan_table *vlan_entry;
 743         struct hns3_pf *pf = &hns->pf;
 744
 745         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 746                 if (vlan_entry->hd_tbl_status)
 747                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 748
 749                 vlan_entry->hd_tbl_status = false;
 750         }
 751
 752         if (is_del_list) {
 753                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 754                 while (vlan_entry) {
 755                         LIST_REMOVE(vlan_entry, next);
 756                         rte_free(vlan_entry);
 757                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 758                 }
 759         }
 760 }
 761
 762 static void
 763 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 764 {
 765         struct hns3_user_vlan_table *vlan_entry;
 766         struct hns3_pf *pf = &hns->pf;
 767
 768         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 769                 if (!vlan_entry->hd_tbl_status)
 770                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 771
 772                 vlan_entry->hd_tbl_status = true;
 773         }
 774 }
 775
 776 static void
 777 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 778 {
 779         struct hns3_hw *hw = &hns->hw;
 780         struct hns3_pf *pf = &hns->pf;
 781         int ret;
 782
 783         hns3_rm_all_vlan_table(hns, true);
 784         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 785                 ret = hns3_set_port_vlan_filter(hns,
 786                                                 pf->port_base_vlan_cfg.pvid, 0);
 787                 if (ret) {
 788                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 789                                  ret);
 790                         return;
 791                 }
 792         }
 793 }
 794
 795 static int
 796 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 797                                 uint16_t port_base_vlan_state,
 798                                 uint16_t new_pvid, uint16_t old_pvid)
 799 {
 800         struct hns3_pf *pf = &hns->pf;
 801         struct hns3_hw *hw = &hns->hw;
 802         int ret = 0;
 803
 804         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 805                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 806                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 807                         if (ret) {
 808                                 hns3_err(hw,
 809                                          "Failed to clear clear old pvid filter, ret =%d",
 810                                          ret);
 811                                 return ret;
 812                         }
 813                 }
 814
 815                 hns3_rm_all_vlan_table(hns, false);
 816                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 817         }
 818
 819         if (new_pvid != 0) {
 820                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 821                 if (ret) {
 822                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 823                                  ret);
 824                         return ret;
 825                 }
 826         }
 827
 828         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 829                 hns3_add_all_vlan_table(hns);
 830
 831         return ret;
 832 }
 833
 834 static int
 835 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 836 {
 837         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 838         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 839         bool rx_strip_en;
 840         int ret;
 841
 842         rx_strip_en = old_cfg->rx_vlan_offload_en ? true : false;
 843         if (on) {
 844                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 845                 rx_vlan_cfg.strip_tag2_en = true;
 846         } else {
 847                 rx_vlan_cfg.strip_tag1_en = false;
 848                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 849         }
 850         rx_vlan_cfg.vlan1_vlan_prionly = false;
 851         rx_vlan_cfg.vlan2_vlan_prionly = false;
 852         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 853
 854         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 855         if (ret)
 856                 return ret;
 857
 858         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 859         return ret;
 860 }
 861
 862 static int
 863 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 864 {
 865         struct hns3_pf *pf = &hns->pf;
 866         struct hns3_hw *hw = &hns->hw;
 867         uint16_t port_base_vlan_state;
 868         uint16_t old_pvid;
 869         int ret;
 870
 871         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 872                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 873                         hns3_warn(hw, "Invalid operation! As current pvid set "
 874                                   "is %u, disable pvid %u is invalid",
 875                                   pf->port_base_vlan_cfg.pvid, pvid);
 876                 return 0;
 877         }
 878
 879         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 880                                     HNS3_PORT_BASE_VLAN_DISABLE;
 881         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 882         if (ret) {
 883                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 884                          ret);
 885                 return ret;
 886         }
 887
 888         ret = hns3_en_pvid_strip(hns, on);
 889         if (ret) {
 890                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 891                          "ret = %d", ret);
 892                 return ret;
 893         }
 894
 895         if (pvid == HNS3_INVLID_PVID)
 896                 goto out;
 897         old_pvid = pf->port_base_vlan_cfg.pvid;
 898         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 899                                               old_pvid);
 900         if (ret) {
 901                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 902                          ret);
 903                 return ret;
 904         }
 905
 906 out:
 907         hns3_store_port_base_vlan_info(hns, pvid, on);
 908         return ret;
 909 }
 910
 911 static int
 912 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 913 {
 914         struct hns3_adapter *hns = dev->data->dev_private;
 915         struct hns3_hw *hw = &hns->hw;
 916         int ret;
 917
 918         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 919                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 920                          RTE_ETHER_MAX_VLAN_ID);
 921                 return -EINVAL;
 922         }
 923
 924         rte_spinlock_lock(&hw->lock);
 925         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 926         rte_spinlock_unlock(&hw->lock);
 927         return ret;
 928 }
 929
 930 static void
 931 init_port_base_vlan_info(struct hns3_hw *hw)
 932 {
 933         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 934         struct hns3_pf *pf = &hns->pf;
 935
 936         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 937         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 938 }
 939
 940 static int
 941 hns3_default_vlan_config(struct hns3_adapter *hns)
 942 {
 943         struct hns3_hw *hw = &hns->hw;
 944         int ret;
 945
 946         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 947         if (ret)
 948                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 949         return ret;
 950 }
 951
 952 static int
 953 hns3_init_vlan_config(struct hns3_adapter *hns)
 954 {
 955         struct hns3_hw *hw = &hns->hw;
 956         int ret;
 957
 958         /*
 959          * This function can be called in the initialization and reset process,
 960          * when in reset process, it means that hardware had been reseted
 961          * successfully and we need to restore the hardware configuration to
 962          * ensure that the hardware configuration remains unchanged before and
 963          * after reset.
 964          */
 965         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 966                 init_port_base_vlan_info(hw);
 967
 968         ret = hns3_vlan_filter_init(hns);
 969         if (ret) {
 970                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 971                 return ret;
 972         }
 973
 974         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 975                                        RTE_ETHER_TYPE_VLAN);
 976         if (ret) {
 977                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 978                 return ret;
 979         }
 980
 981         /*
 982          * When in the reinit dev stage of the reset process, the following
 983          * vlan-related configurations may differ from those at initialization,
 984          * we will restore configurations to hardware in hns3_restore_vlan_table
 985          * and hns3_restore_vlan_conf later.
 986          */
 987         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 988                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 989                 if (ret) {
 990                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 991                         return ret;
 992                 }
 993
 994                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 995                 if (ret) {
 996                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 997                                  ret);
 998                         return ret;
 999                 }
1000         }
1001
1002         return hns3_default_vlan_config(hns);
1003 }
1004
1005 static int
1006 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1007 {
1008         struct hns3_pf *pf = &hns->pf;
1009         struct hns3_hw *hw = &hns->hw;
1010         uint64_t offloads;
1011         bool enable;
1012         int ret;
1013
1014         if (!hw->data->promiscuous) {
1015                 /* restore vlan filter states */
1016                 offloads = hw->data->dev_conf.rxmode.offloads;
1017                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1018                 ret = hns3_enable_vlan_filter(hns, enable);
1019                 if (ret) {
1020                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1021                                  "ret = %d", ret);
1022                         return ret;
1023                 }
1024         }
1025
1026         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1027         if (ret) {
1028                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1029                 return ret;
1030         }
1031
1032         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1033         if (ret)
1034                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1035
1036         return ret;
1037 }
1038
1039 static int
1040 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1041 {
1042         struct hns3_adapter *hns = dev->data->dev_private;
1043         struct rte_eth_dev_data *data = dev->data;
1044         struct rte_eth_txmode *txmode;
1045         struct hns3_hw *hw = &hns->hw;
1046         int mask;
1047         int ret;
1048
1049         txmode = &data->dev_conf.txmode;
1050         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1051                 hns3_warn(hw,
1052                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1053                           "configuration is not supported! Ignore these two "
1054                           "parameters: hw_vlan_reject_tagged(%d), "
1055                           "hw_vlan_reject_untagged(%d)",
1056                           txmode->hw_vlan_reject_tagged,
1057                           txmode->hw_vlan_reject_untagged);
1058
1059         /* Apply vlan offload setting */
1060         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1061         ret = hns3_vlan_offload_set(dev, mask);
1062         if (ret) {
1063                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1064                          ret);
1065                 return ret;
1066         }
1067
1068         /*
1069          * If pvid config is not set in rte_eth_conf, driver needn't to set
1070          * VLAN pvid related configuration to hardware.
1071          */
1072         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1073                 return 0;
1074
1075         /* Apply pvid setting */
1076         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1077                                  txmode->hw_vlan_insert_pvid);
1078         if (ret)
1079                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1080                          txmode->pvid, ret);
1081
1082         return ret;
1083 }
1084
1085 static int
1086 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1087                 unsigned int tso_mss_max)
1088 {
1089         struct hns3_cfg_tso_status_cmd *req;
1090         struct hns3_cmd_desc desc;
1091         uint16_t tso_mss;
1092
1093         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1094
1095         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1096
1097         tso_mss = 0;
1098         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1099                        tso_mss_min);
1100         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1101
1102         tso_mss = 0;
1103         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1104                        tso_mss_max);
1105         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1106
1107         return hns3_cmd_send(hw, &desc, 1);
1108 }
1109
1110 int
1111 hns3_config_gro(struct hns3_hw *hw, bool en)
1112 {
1113         struct hns3_cfg_gro_status_cmd *req;
1114         struct hns3_cmd_desc desc;
1115         int ret;
1116
1117         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1118         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1119
1120         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1121
1122         ret = hns3_cmd_send(hw, &desc, 1);
1123         if (ret)
1124                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1125
1126         return ret;
1127 }
1128
1129 static int
1130 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1131                    uint16_t *allocated_size, bool is_alloc)
1132 {
1133         struct hns3_umv_spc_alc_cmd *req;
1134         struct hns3_cmd_desc desc;
1135         int ret;
1136
1137         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1138         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1139         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1140         req->space_size = rte_cpu_to_le_32(space_size);
1141
1142         ret = hns3_cmd_send(hw, &desc, 1);
1143         if (ret) {
1144                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1145                              is_alloc ? "allocate" : "free", ret);
1146                 return ret;
1147         }
1148
1149         if (is_alloc && allocated_size)
1150                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1151
1152         return 0;
1153 }
1154
1155 static int
1156 hns3_init_umv_space(struct hns3_hw *hw)
1157 {
1158         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1159         struct hns3_pf *pf = &hns->pf;
1160         uint16_t allocated_size = 0;
1161         int ret;
1162
1163         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1164                                  true);
1165         if (ret)
1166                 return ret;
1167
1168         if (allocated_size < pf->wanted_umv_size)
1169                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1170                              pf->wanted_umv_size, allocated_size);
1171
1172         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1173                                                 pf->wanted_umv_size;
1174         pf->used_umv_size = 0;
1175         return 0;
1176 }
1177
1178 static int
1179 hns3_uninit_umv_space(struct hns3_hw *hw)
1180 {
1181         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1182         struct hns3_pf *pf = &hns->pf;
1183         int ret;
1184
1185         if (pf->max_umv_size == 0)
1186                 return 0;
1187
1188         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1189         if (ret)
1190                 return ret;
1191
1192         pf->max_umv_size = 0;
1193
1194         return 0;
1195 }
1196
1197 static bool
1198 hns3_is_umv_space_full(struct hns3_hw *hw)
1199 {
1200         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1201         struct hns3_pf *pf = &hns->pf;
1202         bool is_full;
1203
1204         is_full = (pf->used_umv_size >= pf->max_umv_size);
1205
1206         return is_full;
1207 }
1208
1209 static void
1210 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1211 {
1212         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1213         struct hns3_pf *pf = &hns->pf;
1214
1215         if (is_free) {
1216                 if (pf->used_umv_size > 0)
1217                         pf->used_umv_size--;
1218         } else
1219                 pf->used_umv_size++;
1220 }
1221
1222 static void
1223 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1224                       const uint8_t *addr, bool is_mc)
1225 {
1226         const unsigned char *mac_addr = addr;
1227         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1228                             ((uint32_t)mac_addr[2] << 16) |
1229                             ((uint32_t)mac_addr[1] << 8) |
1230                             (uint32_t)mac_addr[0];
1231         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1232
1233         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1234         if (is_mc) {
1235                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1236                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1237                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1238         }
1239
1240         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1241         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1242 }
1243
1244 static int
1245 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1246                              uint8_t resp_code,
1247                              enum hns3_mac_vlan_tbl_opcode op)
1248 {
1249         if (cmdq_resp) {
1250                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1251                          cmdq_resp);
1252                 return -EIO;
1253         }
1254
1255         if (op == HNS3_MAC_VLAN_ADD) {
1256                 if (resp_code == 0 || resp_code == 1) {
1257                         return 0;
1258                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1259                         hns3_err(hw, "add mac addr failed for uc_overflow");
1260                         return -ENOSPC;
1261                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1262                         hns3_err(hw, "add mac addr failed for mc_overflow");
1263                         return -ENOSPC;
1264                 }
1265
1266                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1267                          resp_code);
1268                 return -EIO;
1269         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1270                 if (resp_code == 0) {
1271                         return 0;
1272                 } else if (resp_code == 1) {
1273                         hns3_dbg(hw, "remove mac addr failed for miss");
1274                         return -ENOENT;
1275                 }
1276
1277                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1278                          resp_code);
1279                 return -EIO;
1280         } else if (op == HNS3_MAC_VLAN_LKUP) {
1281                 if (resp_code == 0) {
1282                         return 0;
1283                 } else if (resp_code == 1) {
1284                         hns3_dbg(hw, "lookup mac addr failed for miss");
1285                         return -ENOENT;
1286                 }
1287
1288                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1289                          resp_code);
1290                 return -EIO;
1291         }
1292
1293         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1294                  op);
1295
1296         return -EINVAL;
1297 }
1298
1299 static int
1300 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1301                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1302                          struct hns3_cmd_desc *desc, bool is_mc)
1303 {
1304         uint8_t resp_code;
1305         uint16_t retval;
1306         int ret;
1307
1308         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1309         if (is_mc) {
1310                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1311                 memcpy(desc[0].data, req,
1312                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1313                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1314                                           true);
1315                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1316                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1317                                           true);
1318                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1319         } else {
1320                 memcpy(desc[0].data, req,
1321                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1322                 ret = hns3_cmd_send(hw, desc, 1);
1323         }
1324         if (ret) {
1325                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1326                          ret);
1327                 return ret;
1328         }
1329         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1330         retval = rte_le_to_cpu_16(desc[0].retval);
1331
1332         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1333                                             HNS3_MAC_VLAN_LKUP);
1334 }
1335
1336 static int
1337 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1338                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1339                       struct hns3_cmd_desc *mc_desc)
1340 {
1341         uint8_t resp_code;
1342         uint16_t retval;
1343         int cfg_status;
1344         int ret;
1345
1346         if (mc_desc == NULL) {
1347                 struct hns3_cmd_desc desc;
1348
1349                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1350                 memcpy(desc.data, req,
1351                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1352                 ret = hns3_cmd_send(hw, &desc, 1);
1353                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1354                 retval = rte_le_to_cpu_16(desc.retval);
1355
1356                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1357                                                           HNS3_MAC_VLAN_ADD);
1358         } else {
1359                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1360                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1361                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1362                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1363                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1364                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1365                 memcpy(mc_desc[0].data, req,
1366                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1367                 mc_desc[0].retval = 0;
1368                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1369                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1370                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1371
1372                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1373                                                           HNS3_MAC_VLAN_ADD);
1374         }
1375
1376         if (ret) {
1377                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1378                 return ret;
1379         }
1380
1381         return cfg_status;
1382 }
1383
1384 static int
1385 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1386                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1387 {
1388         struct hns3_cmd_desc desc;
1389         uint8_t resp_code;
1390         uint16_t retval;
1391         int ret;
1392
1393         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1394
1395         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1396
1397         ret = hns3_cmd_send(hw, &desc, 1);
1398         if (ret) {
1399                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1400                 return ret;
1401         }
1402         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1403         retval = rte_le_to_cpu_16(desc.retval);
1404
1405         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1406                                             HNS3_MAC_VLAN_REMOVE);
1407 }
1408
1409 static int
1410 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1411 {
1412         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1413         struct hns3_mac_vlan_tbl_entry_cmd req;
1414         struct hns3_pf *pf = &hns->pf;
1415         struct hns3_cmd_desc desc;
1416         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1417         uint16_t egress_port = 0;
1418         uint8_t vf_id;
1419         int ret;
1420
1421         /* check if mac addr is valid */
1422         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1423                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1424                                       mac_addr);
1425                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1426                          mac_str);
1427                 return -EINVAL;
1428         }
1429
1430         memset(&req, 0, sizeof(req));
1431
1432         /*
1433          * In current version VF is not supported when PF is driven by DPDK
1434          * driver, just need to configure parameters for PF vport.
1435          */
1436         vf_id = HNS3_PF_FUNC_ID;
1437         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1438                        HNS3_MAC_EPORT_VFID_S, vf_id);
1439
1440         req.egress_port = rte_cpu_to_le_16(egress_port);
1441
1442         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1443
1444         /*
1445          * Lookup the mac address in the mac_vlan table, and add
1446          * it if the entry is inexistent. Repeated unicast entry
1447          * is not allowed in the mac vlan table.
1448          */
1449         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1450         if (ret == -ENOENT) {
1451                 if (!hns3_is_umv_space_full(hw)) {
1452                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1453                         if (!ret)
1454                                 hns3_update_umv_space(hw, false);
1455                         return ret;
1456                 }
1457
1458                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1459
1460                 return -ENOSPC;
1461         }
1462
1463         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1464
1465         /* check if we just hit the duplicate */
1466         if (ret == 0) {
1467                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1468                 return 0;
1469         }
1470
1471         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1472                  mac_str);
1473
1474         return ret;
1475 }
1476
1477 static int
1478 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1479 {
1480         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1481         struct rte_ether_addr *addr;
1482         int ret;
1483         int i;
1484
1485         for (i = 0; i < hw->mc_addrs_num; i++) {
1486                 addr = &hw->mc_addrs[i];
1487                 /* Check if there are duplicate addresses */
1488                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1489                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1490                                               addr);
1491                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1492                                  "(%s) is added by the set_mc_mac_addr_list "
1493                                  "API", mac_str);
1494                         return -EINVAL;
1495                 }
1496         }
1497
1498         ret = hns3_add_mc_addr(hw, mac_addr);
1499         if (ret) {
1500                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1501                                       mac_addr);
1502                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1503                          mac_str, ret);
1504         }
1505         return ret;
1506 }
1507
1508 static int
1509 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1510 {
1511         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1512         int ret;
1513
1514         ret = hns3_remove_mc_addr(hw, mac_addr);
1515         if (ret) {
1516                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1517                                       mac_addr);
1518                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1519                          mac_str, ret);
1520         }
1521         return ret;
1522 }
1523
1524 static int
1525 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1526                   uint32_t idx, __rte_unused uint32_t pool)
1527 {
1528         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1529         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1530         int ret;
1531
1532         rte_spinlock_lock(&hw->lock);
1533
1534         /*
1535          * In hns3 network engine adding UC and MC mac address with different
1536          * commands with firmware. We need to determine whether the input
1537          * address is a UC or a MC address to call different commands.
1538          * By the way, it is recommended calling the API function named
1539          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1540          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1541          * may affect the specifications of UC mac addresses.
1542          */
1543         if (rte_is_multicast_ether_addr(mac_addr))
1544                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1545         else
1546                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1547
1548         if (ret) {
1549                 rte_spinlock_unlock(&hw->lock);
1550                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1551                                       mac_addr);
1552                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1553                          ret);
1554                 return ret;
1555         }
1556
1557         if (idx == 0)
1558                 hw->mac.default_addr_setted = true;
1559         rte_spinlock_unlock(&hw->lock);
1560
1561         return ret;
1562 }
1563
1564 static int
1565 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1566 {
1567         struct hns3_mac_vlan_tbl_entry_cmd req;
1568         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1569         int ret;
1570
1571         /* check if mac addr is valid */
1572         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1573                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1574                                       mac_addr);
1575                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1576                          mac_str);
1577                 return -EINVAL;
1578         }
1579
1580         memset(&req, 0, sizeof(req));
1581         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1582         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1583         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1584         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1585                 return 0;
1586         else if (ret == 0)
1587                 hns3_update_umv_space(hw, true);
1588
1589         return ret;
1590 }
1591
1592 static void
1593 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1594 {
1595         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596         /* index will be checked by upper level rte interface */
1597         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1598         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1599         int ret;
1600
1601         rte_spinlock_lock(&hw->lock);
1602
1603         if (rte_is_multicast_ether_addr(mac_addr))
1604                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1605         else
1606                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1607         rte_spinlock_unlock(&hw->lock);
1608         if (ret) {
1609                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1610                                       mac_addr);
1611                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1612                          ret);
1613         }
1614 }
1615
1616 static int
1617 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1618                           struct rte_ether_addr *mac_addr)
1619 {
1620         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1621         struct rte_ether_addr *oaddr;
1622         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1623         bool default_addr_setted;
1624         bool rm_succes = false;
1625         int ret, ret_val;
1626
1627         /*
1628          * It has been guaranteed that input parameter named mac_addr is valid
1629          * address in the rte layer of DPDK framework.
1630          */
1631         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1632         default_addr_setted = hw->mac.default_addr_setted;
1633         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1634                 return 0;
1635
1636         rte_spinlock_lock(&hw->lock);
1637         if (default_addr_setted) {
1638                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1639                 if (ret) {
1640                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1641                                               oaddr);
1642                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1643                                   mac_str, ret);
1644                         rm_succes = false;
1645                 } else
1646                         rm_succes = true;
1647         }
1648
1649         ret = hns3_add_uc_addr_common(hw, mac_addr);
1650         if (ret) {
1651                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1652                                       mac_addr);
1653                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1654                 goto err_add_uc_addr;
1655         }
1656
1657         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1658         if (ret) {
1659                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1660                 goto err_pause_addr_cfg;
1661         }
1662
1663         rte_ether_addr_copy(mac_addr,
1664                             (struct rte_ether_addr *)hw->mac.mac_addr);
1665         hw->mac.default_addr_setted = true;
1666         rte_spinlock_unlock(&hw->lock);
1667
1668         return 0;
1669
1670 err_pause_addr_cfg:
1671         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1672         if (ret_val) {
1673                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1674                                       mac_addr);
1675                 hns3_warn(hw,
1676                           "Failed to roll back to del setted mac addr(%s): %d",
1677                           mac_str, ret_val);
1678         }
1679
1680 err_add_uc_addr:
1681         if (rm_succes) {
1682                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1683                 if (ret_val) {
1684                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1685                                               oaddr);
1686                         hns3_warn(hw,
1687                                   "Failed to restore old uc mac addr(%s): %d",
1688                                   mac_str, ret_val);
1689                         hw->mac.default_addr_setted = false;
1690                 }
1691         }
1692         rte_spinlock_unlock(&hw->lock);
1693
1694         return ret;
1695 }
1696
1697 static int
1698 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1699 {
1700         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1701         struct hns3_hw *hw = &hns->hw;
1702         struct rte_ether_addr *addr;
1703         int err = 0;
1704         int ret;
1705         int i;
1706
1707         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1708                 addr = &hw->data->mac_addrs[i];
1709                 if (rte_is_zero_ether_addr(addr))
1710                         continue;
1711                 if (rte_is_multicast_ether_addr(addr))
1712                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1713                               hns3_add_mc_addr(hw, addr);
1714                 else
1715                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1716                               hns3_add_uc_addr_common(hw, addr);
1717
1718                 if (ret) {
1719                         err = ret;
1720                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1721                                               addr);
1722                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1723                                  "ret = %d.", del ? "remove" : "restore",
1724                                  mac_str, i, ret);
1725                 }
1726         }
1727         return err;
1728 }
1729
1730 static void
1731 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1732 {
1733 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1734         uint8_t word_num;
1735         uint8_t bit_num;
1736
1737         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1738                 word_num = vfid / 32;
1739                 bit_num = vfid % 32;
1740                 if (clr)
1741                         desc[1].data[word_num] &=
1742                             rte_cpu_to_le_32(~(1UL << bit_num));
1743                 else
1744                         desc[1].data[word_num] |=
1745                             rte_cpu_to_le_32(1UL << bit_num);
1746         } else {
1747                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1748                 bit_num = vfid % 32;
1749                 if (clr)
1750                         desc[2].data[word_num] &=
1751                             rte_cpu_to_le_32(~(1UL << bit_num));
1752                 else
1753                         desc[2].data[word_num] |=
1754                             rte_cpu_to_le_32(1UL << bit_num);
1755         }
1756 }
1757
1758 static int
1759 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1760 {
1761         struct hns3_mac_vlan_tbl_entry_cmd req;
1762         struct hns3_cmd_desc desc[3];
1763         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1764         uint8_t vf_id;
1765         int ret;
1766
1767         /* Check if mac addr is valid */
1768         if (!rte_is_multicast_ether_addr(mac_addr)) {
1769                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1770                                       mac_addr);
1771                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1772                          mac_str);
1773                 return -EINVAL;
1774         }
1775
1776         memset(&req, 0, sizeof(req));
1777         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1778         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1779         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1780         if (ret) {
1781                 /* This mac addr do not exist, add new entry for it */
1782                 memset(desc[0].data, 0, sizeof(desc[0].data));
1783                 memset(desc[1].data, 0, sizeof(desc[0].data));
1784                 memset(desc[2].data, 0, sizeof(desc[0].data));
1785         }
1786
1787         /*
1788          * In current version VF is not supported when PF is driven by DPDK
1789          * driver, just need to configure parameters for PF vport.
1790          */
1791         vf_id = HNS3_PF_FUNC_ID;
1792         hns3_update_desc_vfid(desc, vf_id, false);
1793         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1794         if (ret) {
1795                 if (ret == -ENOSPC)
1796                         hns3_err(hw, "mc mac vlan table is full");
1797                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1798                                       mac_addr);
1799                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1800         }
1801
1802         return ret;
1803 }
1804
1805 static int
1806 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1807 {
1808         struct hns3_mac_vlan_tbl_entry_cmd req;
1809         struct hns3_cmd_desc desc[3];
1810         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1811         uint8_t vf_id;
1812         int ret;
1813
1814         /* Check if mac addr is valid */
1815         if (!rte_is_multicast_ether_addr(mac_addr)) {
1816                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1817                                       mac_addr);
1818                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1819                          mac_str);
1820                 return -EINVAL;
1821         }
1822
1823         memset(&req, 0, sizeof(req));
1824         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1825         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1826         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1827         if (ret == 0) {
1828                 /*
1829                  * This mac addr exist, remove this handle's VFID for it.
1830                  * In current version VF is not supported when PF is driven by
1831                  * DPDK driver, just need to configure parameters for PF vport.
1832                  */
1833                 vf_id = HNS3_PF_FUNC_ID;
1834                 hns3_update_desc_vfid(desc, vf_id, true);
1835
1836                 /* All the vfid is zero, so need to delete this entry */
1837                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1838         } else if (ret == -ENOENT) {
1839                 /* This mac addr doesn't exist. */
1840                 return 0;
1841         }
1842
1843         if (ret) {
1844                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1845                                       mac_addr);
1846                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1847         }
1848
1849         return ret;
1850 }
1851
1852 static int
1853 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1854                            struct rte_ether_addr *mc_addr_set,
1855                            uint32_t nb_mc_addr)
1856 {
1857         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1858         struct rte_ether_addr *addr;
1859         uint32_t i;
1860         uint32_t j;
1861
1862         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1863                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1864                          "invalid. valid range: 0~%d",
1865                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1866                 return -EINVAL;
1867         }
1868
1869         /* Check if input mac addresses are valid */
1870         for (i = 0; i < nb_mc_addr; i++) {
1871                 addr = &mc_addr_set[i];
1872                 if (!rte_is_multicast_ether_addr(addr)) {
1873                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1874                                               addr);
1875                         hns3_err(hw,
1876                                  "failed to set mc mac addr, addr(%s) invalid.",
1877                                  mac_str);
1878                         return -EINVAL;
1879                 }
1880
1881                 /* Check if there are duplicate addresses */
1882                 for (j = i + 1; j < nb_mc_addr; j++) {
1883                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1884                                 rte_ether_format_addr(mac_str,
1885                                                       RTE_ETHER_ADDR_FMT_SIZE,
1886                                                       addr);
1887                                 hns3_err(hw, "failed to set mc mac addr, "
1888                                          "addrs invalid. two same addrs(%s).",
1889                                          mac_str);
1890                                 return -EINVAL;
1891                         }
1892                 }
1893
1894                 /*
1895                  * Check if there are duplicate addresses between mac_addrs
1896                  * and mc_addr_set
1897                  */
1898                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1899                         if (rte_is_same_ether_addr(addr,
1900                                                    &hw->data->mac_addrs[j])) {
1901                                 rte_ether_format_addr(mac_str,
1902                                                       RTE_ETHER_ADDR_FMT_SIZE,
1903                                                       addr);
1904                                 hns3_err(hw, "failed to set mc mac addr, "
1905                                          "addrs invalid. addrs(%s) has already "
1906                                          "configured in mac_addr add API",
1907                                          mac_str);
1908                                 return -EINVAL;
1909                         }
1910                 }
1911         }
1912
1913         return 0;
1914 }
1915
1916 static void
1917 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1918                            struct rte_ether_addr *mc_addr_set,
1919                            int mc_addr_num,
1920                            struct rte_ether_addr *reserved_addr_list,
1921                            int *reserved_addr_num,
1922                            struct rte_ether_addr *add_addr_list,
1923                            int *add_addr_num,
1924                            struct rte_ether_addr *rm_addr_list,
1925                            int *rm_addr_num)
1926 {
1927         struct rte_ether_addr *addr;
1928         int current_addr_num;
1929         int reserved_num = 0;
1930         int add_num = 0;
1931         int rm_num = 0;
1932         int num;
1933         int i;
1934         int j;
1935         bool same_addr;
1936
1937         /* Calculate the mc mac address list that should be removed */
1938         current_addr_num = hw->mc_addrs_num;
1939         for (i = 0; i < current_addr_num; i++) {
1940                 addr = &hw->mc_addrs[i];
1941                 same_addr = false;
1942                 for (j = 0; j < mc_addr_num; j++) {
1943                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1944                                 same_addr = true;
1945                                 break;
1946                         }
1947                 }
1948
1949                 if (!same_addr) {
1950                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1951                         rm_num++;
1952                 } else {
1953                         rte_ether_addr_copy(addr,
1954                                             &reserved_addr_list[reserved_num]);
1955                         reserved_num++;
1956                 }
1957         }
1958
1959         /* Calculate the mc mac address list that should be added */
1960         for (i = 0; i < mc_addr_num; i++) {
1961                 addr = &mc_addr_set[i];
1962                 same_addr = false;
1963                 for (j = 0; j < current_addr_num; j++) {
1964                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1965                                 same_addr = true;
1966                                 break;
1967                         }
1968                 }
1969
1970                 if (!same_addr) {
1971                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1972                         add_num++;
1973                 }
1974         }
1975
1976         /* Reorder the mc mac address list maintained by driver */
1977         for (i = 0; i < reserved_num; i++)
1978                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1979
1980         for (i = 0; i < rm_num; i++) {
1981                 num = reserved_num + i;
1982                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1983         }
1984
1985         *reserved_addr_num = reserved_num;
1986         *add_addr_num = add_num;
1987         *rm_addr_num = rm_num;
1988 }
1989
1990 static int
1991 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1992                           struct rte_ether_addr *mc_addr_set,
1993                           uint32_t nb_mc_addr)
1994 {
1995         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1996         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1997         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1998         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1999         struct rte_ether_addr *addr;
2000         int reserved_addr_num;
2001         int add_addr_num;
2002         int rm_addr_num;
2003         int mc_addr_num;
2004         int num;
2005         int ret;
2006         int i;
2007
2008         /* Check if input parameters are valid */
2009         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2010         if (ret)
2011                 return ret;
2012
2013         rte_spinlock_lock(&hw->lock);
2014
2015         /*
2016          * Calculate the mc mac address lists those should be removed and be
2017          * added, Reorder the mc mac address list maintained by driver.
2018          */
2019         mc_addr_num = (int)nb_mc_addr;
2020         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2021                                    reserved_addr_list, &reserved_addr_num,
2022                                    add_addr_list, &add_addr_num,
2023                                    rm_addr_list, &rm_addr_num);
2024
2025         /* Remove mc mac addresses */
2026         for (i = 0; i < rm_addr_num; i++) {
2027                 num = rm_addr_num - i - 1;
2028                 addr = &rm_addr_list[num];
2029                 ret = hns3_remove_mc_addr(hw, addr);
2030                 if (ret) {
2031                         rte_spinlock_unlock(&hw->lock);
2032                         return ret;
2033                 }
2034                 hw->mc_addrs_num--;
2035         }
2036
2037         /* Add mc mac addresses */
2038         for (i = 0; i < add_addr_num; i++) {
2039                 addr = &add_addr_list[i];
2040                 ret = hns3_add_mc_addr(hw, addr);
2041                 if (ret) {
2042                         rte_spinlock_unlock(&hw->lock);
2043                         return ret;
2044                 }
2045
2046                 num = reserved_addr_num + i;
2047                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2048                 hw->mc_addrs_num++;
2049         }
2050         rte_spinlock_unlock(&hw->lock);
2051
2052         return 0;
2053 }
2054
2055 static int
2056 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2057 {
2058         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2059         struct hns3_hw *hw = &hns->hw;
2060         struct rte_ether_addr *addr;
2061         int err = 0;
2062         int ret;
2063         int i;
2064
2065         for (i = 0; i < hw->mc_addrs_num; i++) {
2066                 addr = &hw->mc_addrs[i];
2067                 if (!rte_is_multicast_ether_addr(addr))
2068                         continue;
2069                 if (del)
2070                         ret = hns3_remove_mc_addr(hw, addr);
2071                 else
2072                         ret = hns3_add_mc_addr(hw, addr);
2073                 if (ret) {
2074                         err = ret;
2075                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2076                                               addr);
2077                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2078                                  del ? "Remove" : "Restore", mac_str, ret);
2079                 }
2080         }
2081         return err;
2082 }
2083
2084 static int
2085 hns3_check_mq_mode(struct rte_eth_dev *dev)
2086 {
2087         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2088         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2089         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2090         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2091         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2092         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2093         uint8_t num_tc;
2094         int max_tc = 0;
2095         int i;
2096
2097         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2098         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2099
2100         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2101                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2102                          "rx_mq_mode = %d", rx_mq_mode);
2103                 return -EINVAL;
2104         }
2105
2106         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2107             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2108                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2109                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2110                          rx_mq_mode, tx_mq_mode);
2111                 return -EINVAL;
2112         }
2113
2114         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2115                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2116                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2117                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2118                         return -EINVAL;
2119                 }
2120
2121                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2122                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2123                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2124                                  "nb_tcs(%d) != %d or %d in rx direction.",
2125                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2126                         return -EINVAL;
2127                 }
2128
2129                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2130                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2131                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2132                         return -EINVAL;
2133                 }
2134
2135                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2136                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2137                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2138                                          "is not equal to one in tx direction.",
2139                                          i, dcb_rx_conf->dcb_tc[i]);
2140                                 return -EINVAL;
2141                         }
2142                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2143                                 max_tc = dcb_rx_conf->dcb_tc[i];
2144                 }
2145
2146                 num_tc = max_tc + 1;
2147                 if (num_tc > dcb_rx_conf->nb_tcs) {
2148                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2149                                  num_tc, dcb_rx_conf->nb_tcs);
2150                         return -EINVAL;
2151                 }
2152         }
2153
2154         return 0;
2155 }
2156
2157 static int
2158 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2159 {
2160         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2161
2162         if (!hns3_dev_dcb_supported(hw)) {
2163                 hns3_err(hw, "this port does not support dcb configurations.");
2164                 return -EOPNOTSUPP;
2165         }
2166
2167         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2168                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2169                 return -EOPNOTSUPP;
2170         }
2171
2172         /* Check multiple queue mode */
2173         return hns3_check_mq_mode(dev);
2174 }
2175
2176 static int
2177 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2178                            enum hns3_ring_type queue_type, uint16_t queue_id)
2179 {
2180         struct hns3_cmd_desc desc;
2181         struct hns3_ctrl_vector_chain_cmd *req =
2182                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2183         enum hns3_cmd_status status;
2184         enum hns3_opcode_type op;
2185         uint16_t tqp_type_and_id = 0;
2186         const char *op_str;
2187         uint16_t type;
2188         uint16_t gl;
2189
2190         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2191         hns3_cmd_setup_basic_desc(&desc, op, false);
2192         req->int_vector_id = vector_id;
2193
2194         if (queue_type == HNS3_RING_TYPE_RX)
2195                 gl = HNS3_RING_GL_RX;
2196         else
2197                 gl = HNS3_RING_GL_TX;
2198
2199         type = queue_type;
2200
2201         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2202                        type);
2203         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2204         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2205                        gl);
2206         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2207         req->int_cause_num = 1;
2208         op_str = mmap ? "Map" : "Unmap";
2209         status = hns3_cmd_send(hw, &desc, 1);
2210         if (status) {
2211                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2212                          op_str, queue_id, req->int_vector_id, status);
2213                 return status;
2214         }
2215
2216         return 0;
2217 }
2218
2219 static int
2220 hns3_init_ring_with_vector(struct hns3_hw *hw)
2221 {
2222         uint8_t vec;
2223         int ret;
2224         int i;
2225
2226         /*
2227          * In hns3 network engine, vector 0 is always the misc interrupt of this
2228          * function, vector 1~N can be used respectively for the queues of the
2229          * function. Tx and Rx queues with the same number share the interrupt
2230          * vector. In the initialization clearing the all hardware mapping
2231          * relationship configurations between queues and interrupt vectors is
2232          * needed, so some error caused by the residual configurations, such as
2233          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2234          * constraints in hns3 hardware engine, we have to implement clearing
2235          * the mapping relationship configurations by binding all queues to the
2236          * last interrupt vector and reserving the last interrupt vector. This
2237          * method results in a decrease of the maximum queues when upper
2238          * applications call the rte_eth_dev_configure API function to enable
2239          * Rx interrupt.
2240          */
2241         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2242         /* vec - 1: the last interrupt is reserved */
2243         hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;
2244         for (i = 0; i < hw->intr_tqps_num; i++) {
2245                 /*
2246                  * Set gap limiter and rate limiter configuration of queue's
2247                  * interrupt.
2248                  */
2249                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2250                                        HNS3_TQP_INTR_GL_DEFAULT);
2251                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2252                                        HNS3_TQP_INTR_GL_DEFAULT);
2253                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2254
2255                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2256                                                  HNS3_RING_TYPE_TX, i);
2257                 if (ret) {
2258                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2259                                           "vector: %d, ret=%d", i, vec, ret);
2260                         return ret;
2261                 }
2262
2263                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2264                                                  HNS3_RING_TYPE_RX, i);
2265                 if (ret) {
2266                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2267                                           "vector: %d, ret=%d", i, vec, ret);
2268                         return ret;
2269                 }
2270         }
2271
2272         return 0;
2273 }
2274
2275 static int
2276 hns3_dev_configure(struct rte_eth_dev *dev)
2277 {
2278         struct hns3_adapter *hns = dev->data->dev_private;
2279         struct rte_eth_conf *conf = &dev->data->dev_conf;
2280         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2281         struct hns3_hw *hw = &hns->hw;
2282         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2283         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2284         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2285         struct rte_eth_rss_conf rss_conf;
2286         uint16_t mtu;
2287         int ret;
2288
2289         /*
2290          * Hardware does not support individually enable/disable/reset the Tx or
2291          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2292          * and Rx queues at the same time. When the numbers of Tx queues
2293          * allocated by upper applications are not equal to the numbers of Rx
2294          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2295          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2296          * these fake queues are imperceptible, and can not be used by upper
2297          * applications.
2298          */
2299         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2300         if (ret) {
2301                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2302                 return ret;
2303         }
2304
2305         hw->adapter_state = HNS3_NIC_CONFIGURING;
2306         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2307                 hns3_err(hw, "setting link speed/duplex not supported");
2308                 ret = -EINVAL;
2309                 goto cfg_err;
2310         }
2311
2312         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2313                 ret = hns3_check_dcb_cfg(dev);
2314                 if (ret)
2315                         goto cfg_err;
2316         }
2317
2318         /* When RSS is not configured, redirect the packet queue 0 */
2319         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2320                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2321                 rss_conf = conf->rx_adv_conf.rss_conf;
2322                 if (rss_conf.rss_key == NULL) {
2323                         rss_conf.rss_key = rss_cfg->key;
2324                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2325                 }
2326
2327                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2328                 if (ret)
2329                         goto cfg_err;
2330         }
2331
2332         /*
2333          * If jumbo frames are enabled, MTU needs to be refreshed
2334          * according to the maximum RX packet length.
2335          */
2336         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2337                 /*
2338                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2339                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2340                  * can safely assign to "uint16_t" type variable.
2341                  */
2342                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2343                 ret = hns3_dev_mtu_set(dev, mtu);
2344                 if (ret)
2345                         goto cfg_err;
2346                 dev->data->mtu = mtu;
2347         }
2348
2349         ret = hns3_dev_configure_vlan(dev);
2350         if (ret)
2351                 goto cfg_err;
2352
2353         hw->adapter_state = HNS3_NIC_CONFIGURED;
2354
2355         return 0;
2356
2357 cfg_err:
2358         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2359         hw->adapter_state = HNS3_NIC_INITIALIZED;
2360
2361         return ret;
2362 }
2363
2364 static int
2365 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2366 {
2367         struct hns3_config_max_frm_size_cmd *req;
2368         struct hns3_cmd_desc desc;
2369
2370         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2371
2372         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2373         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2374         req->min_frm_size = RTE_ETHER_MIN_LEN;
2375
2376         return hns3_cmd_send(hw, &desc, 1);
2377 }
2378
2379 static int
2380 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2381 {
2382         int ret;
2383
2384         ret = hns3_set_mac_mtu(hw, mps);
2385         if (ret) {
2386                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2387                 return ret;
2388         }
2389
2390         ret = hns3_buffer_alloc(hw);
2391         if (ret)
2392                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2393
2394         return ret;
2395 }
2396
2397 static int
2398 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2399 {
2400         struct hns3_adapter *hns = dev->data->dev_private;
2401         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2402         struct hns3_hw *hw = &hns->hw;
2403         bool is_jumbo_frame;
2404         int ret;
2405
2406         if (dev->data->dev_started) {
2407                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2408                          "before configuration", dev->data->port_id);
2409                 return -EBUSY;
2410         }
2411
2412         rte_spinlock_lock(&hw->lock);
2413         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2414         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2415
2416         /*
2417          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2418          * assign to "uint16_t" type variable.
2419          */
2420         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2421         if (ret) {
2422                 rte_spinlock_unlock(&hw->lock);
2423                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2424                          dev->data->port_id, mtu, ret);
2425                 return ret;
2426         }
2427         hns->pf.mps = (uint16_t)frame_size;
2428         if (is_jumbo_frame)
2429                 dev->data->dev_conf.rxmode.offloads |=
2430                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2431         else
2432                 dev->data->dev_conf.rxmode.offloads &=
2433                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2434         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2435         rte_spinlock_unlock(&hw->lock);
2436
2437         return 0;
2438 }
2439
2440 static int
2441 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2442 {
2443         struct hns3_adapter *hns = eth_dev->data->dev_private;
2444         struct hns3_hw *hw = &hns->hw;
2445         uint16_t queue_num = hw->tqps_num;
2446
2447         /*
2448          * In interrupt mode, 'max_rx_queues' is set based on the number of
2449          * MSI-X interrupt resources of the hardware.
2450          */
2451         if (hw->data->dev_conf.intr_conf.rxq == 1)
2452                 queue_num = hw->intr_tqps_num;
2453
2454         info->max_rx_queues = queue_num;
2455         info->max_tx_queues = hw->tqps_num;
2456         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2457         info->min_rx_bufsize = hw->rx_buf_len;
2458         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2459         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2460         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2461                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2462                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2463                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2464                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2465                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2466                                  DEV_RX_OFFLOAD_KEEP_CRC |
2467                                  DEV_RX_OFFLOAD_SCATTER |
2468                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2469                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2470                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2471                                  DEV_RX_OFFLOAD_RSS_HASH);
2472         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2473         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2474                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2475                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2476                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2477                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2478                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2479                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2480                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2481                                  DEV_TX_OFFLOAD_TCP_TSO |
2482                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2483                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2484                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2485                                  info->tx_queue_offload_capa);
2486
2487         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2488                 .nb_max = HNS3_MAX_RING_DESC,
2489                 .nb_min = HNS3_MIN_RING_DESC,
2490                 .nb_align = HNS3_ALIGN_RING_DESC,
2491         };
2492
2493         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2494                 .nb_max = HNS3_MAX_RING_DESC,
2495                 .nb_min = HNS3_MIN_RING_DESC,
2496                 .nb_align = HNS3_ALIGN_RING_DESC,
2497         };
2498
2499         info->vmdq_queue_num = 0;
2500
2501         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2502         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2503         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2504
2505         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2506         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2507         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2508         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2509         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2510         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2511
2512         return 0;
2513 }
2514
2515 static int
2516 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2517                     size_t fw_size)
2518 {
2519         struct hns3_adapter *hns = eth_dev->data->dev_private;
2520         struct hns3_hw *hw = &hns->hw;
2521         uint32_t version = hw->fw_version;
2522         int ret;
2523
2524         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2525                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2526                                       HNS3_FW_VERSION_BYTE3_S),
2527                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2528                                       HNS3_FW_VERSION_BYTE2_S),
2529                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2530                                       HNS3_FW_VERSION_BYTE1_S),
2531                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2532                                       HNS3_FW_VERSION_BYTE0_S));
2533         ret += 1; /* add the size of '\0' */
2534         if (fw_size < (uint32_t)ret)
2535                 return ret;
2536         else
2537                 return 0;
2538 }
2539
2540 static int
2541 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2542                      __rte_unused int wait_to_complete)
2543 {
2544         struct hns3_adapter *hns = eth_dev->data->dev_private;
2545         struct hns3_hw *hw = &hns->hw;
2546         struct hns3_mac *mac = &hw->mac;
2547         struct rte_eth_link new_link;
2548
2549         if (!hns3_is_reset_pending(hns)) {
2550                 hns3_update_speed_duplex(eth_dev);
2551                 hns3_update_link_status(hw);
2552         }
2553
2554         memset(&new_link, 0, sizeof(new_link));
2555         switch (mac->link_speed) {
2556         case ETH_SPEED_NUM_10M:
2557         case ETH_SPEED_NUM_100M:
2558         case ETH_SPEED_NUM_1G:
2559         case ETH_SPEED_NUM_10G:
2560         case ETH_SPEED_NUM_25G:
2561         case ETH_SPEED_NUM_40G:
2562         case ETH_SPEED_NUM_50G:
2563         case ETH_SPEED_NUM_100G:
2564                 new_link.link_speed = mac->link_speed;
2565                 break;
2566         default:
2567                 new_link.link_speed = ETH_SPEED_NUM_100M;
2568                 break;
2569         }
2570
2571         new_link.link_duplex = mac->link_duplex;
2572         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2573         new_link.link_autoneg =
2574             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2575
2576         return rte_eth_linkstatus_set(eth_dev, &new_link);
2577 }
2578
2579 static int
2580 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2581 {
2582         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2583         struct hns3_pf *pf = &hns->pf;
2584
2585         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2586                 return -EINVAL;
2587
2588         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2589
2590         return 0;
2591 }
2592
2593 static int
2594 hns3_query_function_status(struct hns3_hw *hw)
2595 {
2596 #define HNS3_QUERY_MAX_CNT              10
2597 #define HNS3_QUERY_SLEEP_MSCOEND        1
2598         struct hns3_func_status_cmd *req;
2599         struct hns3_cmd_desc desc;
2600         int timeout = 0;
2601         int ret;
2602
2603         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2604         req = (struct hns3_func_status_cmd *)desc.data;
2605
2606         do {
2607                 ret = hns3_cmd_send(hw, &desc, 1);
2608                 if (ret) {
2609                         PMD_INIT_LOG(ERR, "query function status failed %d",
2610                                      ret);
2611                         return ret;
2612                 }
2613
2614                 /* Check pf reset is done */
2615                 if (req->pf_state)
2616                         break;
2617
2618                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2619         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2620
2621         return hns3_parse_func_status(hw, req);
2622 }
2623
2624 static int
2625 hns3_query_pf_resource(struct hns3_hw *hw)
2626 {
2627         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2628         struct hns3_pf *pf = &hns->pf;
2629         struct hns3_pf_res_cmd *req;
2630         struct hns3_cmd_desc desc;
2631         int ret;
2632
2633         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2634         ret = hns3_cmd_send(hw, &desc, 1);
2635         if (ret) {
2636                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2637                 return ret;
2638         }
2639
2640         req = (struct hns3_pf_res_cmd *)desc.data;
2641         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2642         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2643         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2644         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2645
2646         if (req->tx_buf_size)
2647                 pf->tx_buf_size =
2648                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2649         else
2650                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2651
2652         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2653
2654         if (req->dv_buf_size)
2655                 pf->dv_buf_size =
2656                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2657         else
2658                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2659
2660         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2661
2662         hw->num_msi =
2663             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2664                            HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2665
2666         return 0;
2667 }
2668
2669 static void
2670 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2671 {
2672         struct hns3_cfg_param_cmd *req;
2673         uint64_t mac_addr_tmp_high;
2674         uint64_t mac_addr_tmp;
2675         uint32_t i;
2676
2677         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2678
2679         /* get the configuration */
2680         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2681                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2682         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2683                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2684         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2685                                            HNS3_CFG_TQP_DESC_N_M,
2686                                            HNS3_CFG_TQP_DESC_N_S);
2687
2688         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2689                                        HNS3_CFG_PHY_ADDR_M,
2690                                        HNS3_CFG_PHY_ADDR_S);
2691         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2692                                          HNS3_CFG_MEDIA_TP_M,
2693                                          HNS3_CFG_MEDIA_TP_S);
2694         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2695                                          HNS3_CFG_RX_BUF_LEN_M,
2696                                          HNS3_CFG_RX_BUF_LEN_S);
2697         /* get mac address */
2698         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2699         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2700                                            HNS3_CFG_MAC_ADDR_H_M,
2701                                            HNS3_CFG_MAC_ADDR_H_S);
2702
2703         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2704
2705         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2706                                             HNS3_CFG_DEFAULT_SPEED_M,
2707                                             HNS3_CFG_DEFAULT_SPEED_S);
2708         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2709                                            HNS3_CFG_RSS_SIZE_M,
2710                                            HNS3_CFG_RSS_SIZE_S);
2711
2712         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2713                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2714
2715         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2716         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2717
2718         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2719                                             HNS3_CFG_SPEED_ABILITY_M,
2720                                             HNS3_CFG_SPEED_ABILITY_S);
2721         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2722                                         HNS3_CFG_UMV_TBL_SPACE_M,
2723                                         HNS3_CFG_UMV_TBL_SPACE_S);
2724         if (!cfg->umv_space)
2725                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2726 }
2727
2728 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2729  * @hw: pointer to struct hns3_hw
2730  * @hcfg: the config structure to be getted
2731  */
2732 static int
2733 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2734 {
2735         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2736         struct hns3_cfg_param_cmd *req;
2737         uint32_t offset;
2738         uint32_t i;
2739         int ret;
2740
2741         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2742                 offset = 0;
2743                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2744                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2745                                           true);
2746                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2747                                i * HNS3_CFG_RD_LEN_BYTES);
2748                 /* Len should be divided by 4 when send to hardware */
2749                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2750                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2751                 req->offset = rte_cpu_to_le_32(offset);
2752         }
2753
2754         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2755         if (ret) {
2756                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2757                 return ret;
2758         }
2759
2760         hns3_parse_cfg(hcfg, desc);
2761
2762         return 0;
2763 }
2764
2765 static int
2766 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2767 {
2768         switch (speed_cmd) {
2769         case HNS3_CFG_SPEED_10M:
2770                 *speed = ETH_SPEED_NUM_10M;
2771                 break;
2772         case HNS3_CFG_SPEED_100M:
2773                 *speed = ETH_SPEED_NUM_100M;
2774                 break;
2775         case HNS3_CFG_SPEED_1G:
2776                 *speed = ETH_SPEED_NUM_1G;
2777                 break;
2778         case HNS3_CFG_SPEED_10G:
2779                 *speed = ETH_SPEED_NUM_10G;
2780                 break;
2781         case HNS3_CFG_SPEED_25G:
2782                 *speed = ETH_SPEED_NUM_25G;
2783                 break;
2784         case HNS3_CFG_SPEED_40G:
2785                 *speed = ETH_SPEED_NUM_40G;
2786                 break;
2787         case HNS3_CFG_SPEED_50G:
2788                 *speed = ETH_SPEED_NUM_50G;
2789                 break;
2790         case HNS3_CFG_SPEED_100G:
2791                 *speed = ETH_SPEED_NUM_100G;
2792                 break;
2793         default:
2794                 return -EINVAL;
2795         }
2796
2797         return 0;
2798 }
2799
2800 static int
2801 hns3_get_board_configuration(struct hns3_hw *hw)
2802 {
2803         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2804         struct hns3_pf *pf = &hns->pf;
2805         struct hns3_cfg cfg;
2806         int ret;
2807
2808         ret = hns3_get_board_cfg(hw, &cfg);
2809         if (ret) {
2810                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2811                 return ret;
2812         }
2813
2814         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2815                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2816                 return -EOPNOTSUPP;
2817         }
2818
2819         hw->mac.media_type = cfg.media_type;
2820         hw->rss_size_max = cfg.rss_size_max;
2821         hw->rss_dis_flag = false;
2822         hw->rx_buf_len = cfg.rx_buf_len;
2823         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2824         hw->mac.phy_addr = cfg.phy_addr;
2825         hw->mac.default_addr_setted = false;
2826         hw->num_tx_desc = cfg.tqp_desc_num;
2827         hw->num_rx_desc = cfg.tqp_desc_num;
2828         hw->dcb_info.num_pg = 1;
2829         hw->dcb_info.hw_pfc_map = 0;
2830
2831         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2832         if (ret) {
2833                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2834                              cfg.default_speed, ret);
2835                 return ret;
2836         }
2837
2838         pf->tc_max = cfg.tc_num;
2839         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2840                 PMD_INIT_LOG(WARNING,
2841                              "Get TC num(%u) from flash, set TC num to 1",
2842                              pf->tc_max);
2843                 pf->tc_max = 1;
2844         }
2845
2846         /* Dev does not support DCB */
2847         if (!hns3_dev_dcb_supported(hw)) {
2848                 pf->tc_max = 1;
2849                 pf->pfc_max = 0;
2850         } else
2851                 pf->pfc_max = pf->tc_max;
2852
2853         hw->dcb_info.num_tc = 1;
2854         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2855                                      hw->tqps_num / hw->dcb_info.num_tc);
2856         hns3_set_bit(hw->hw_tc_map, 0, 1);
2857         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2858
2859         pf->wanted_umv_size = cfg.umv_space;
2860
2861         return ret;
2862 }
2863
2864 static int
2865 hns3_get_configuration(struct hns3_hw *hw)
2866 {
2867         int ret;
2868
2869         ret = hns3_query_function_status(hw);
2870         if (ret) {
2871                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2872                 return ret;
2873         }
2874
2875         /* Get pf resource */
2876         ret = hns3_query_pf_resource(hw);
2877         if (ret) {
2878                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2879                 return ret;
2880         }
2881
2882         ret = hns3_get_board_configuration(hw);
2883         if (ret)
2884                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2885
2886         return ret;
2887 }
2888
2889 static int
2890 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2891                       uint16_t tqp_vid, bool is_pf)
2892 {
2893         struct hns3_tqp_map_cmd *req;
2894         struct hns3_cmd_desc desc;
2895         int ret;
2896
2897         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2898
2899         req = (struct hns3_tqp_map_cmd *)desc.data;
2900         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2901         req->tqp_vf = func_id;
2902         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2903         if (!is_pf)
2904                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2905         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2906
2907         ret = hns3_cmd_send(hw, &desc, 1);
2908         if (ret)
2909                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2910
2911         return ret;
2912 }
2913
2914 static int
2915 hns3_map_tqp(struct hns3_hw *hw)
2916 {
2917         uint16_t tqps_num = hw->total_tqps_num;
2918         uint16_t func_id;
2919         uint16_t tqp_id;
2920         bool is_pf;
2921         int num;
2922         int ret;
2923         int i;
2924
2925         /*
2926          * In current version VF is not supported when PF is driven by DPDK
2927          * driver, so we allocate tqps to PF as much as possible.
2928          */
2929         tqp_id = 0;
2930         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2931         for (func_id = HNS3_PF_FUNC_ID; func_id < num; func_id++) {
2932                 is_pf = func_id == HNS3_PF_FUNC_ID ? true : false;
2933                 for (i = 0;
2934                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2935                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2936                                                     is_pf);
2937                         if (ret)
2938                                 return ret;
2939                 }
2940         }
2941
2942         return 0;
2943 }
2944
2945 static int
2946 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2947 {
2948         struct hns3_config_mac_speed_dup_cmd *req;
2949         struct hns3_cmd_desc desc;
2950         int ret;
2951
2952         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2953
2954         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2955
2956         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2957
2958         switch (speed) {
2959         case ETH_SPEED_NUM_10M:
2960                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2961                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2962                 break;
2963         case ETH_SPEED_NUM_100M:
2964                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2965                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2966                 break;
2967         case ETH_SPEED_NUM_1G:
2968                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2969                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2970                 break;
2971         case ETH_SPEED_NUM_10G:
2972                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2973                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2974                 break;
2975         case ETH_SPEED_NUM_25G:
2976                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2977                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2978                 break;
2979         case ETH_SPEED_NUM_40G:
2980                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2981                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2982                 break;
2983         case ETH_SPEED_NUM_50G:
2984                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2985                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2986                 break;
2987         case ETH_SPEED_NUM_100G:
2988                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2989                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2990                 break;
2991         default:
2992                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2993                 return -EINVAL;
2994         }
2995
2996         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2997
2998         ret = hns3_cmd_send(hw, &desc, 1);
2999         if (ret)
3000                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3001
3002         return ret;
3003 }
3004
3005 static int
3006 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3007 {
3008         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3009         struct hns3_pf *pf = &hns->pf;
3010         struct hns3_priv_buf *priv;
3011         uint32_t i, total_size;
3012
3013         total_size = pf->pkt_buf_size;
3014
3015         /* alloc tx buffer for all enabled tc */
3016         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3017                 priv = &buf_alloc->priv_buf[i];
3018
3019                 if (hw->hw_tc_map & BIT(i)) {
3020                         if (total_size < pf->tx_buf_size)
3021                                 return -ENOMEM;
3022
3023                         priv->tx_buf_size = pf->tx_buf_size;
3024                 } else
3025                         priv->tx_buf_size = 0;
3026
3027                 total_size -= priv->tx_buf_size;
3028         }
3029
3030         return 0;
3031 }
3032
3033 static int
3034 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3035 {
3036 /* TX buffer size is unit by 128 byte */
3037 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3038 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3039         struct hns3_tx_buff_alloc_cmd *req;
3040         struct hns3_cmd_desc desc;
3041         uint32_t buf_size;
3042         uint32_t i;
3043         int ret;
3044
3045         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3046
3047         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3048         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3049                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3050
3051                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3052                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3053                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3054         }
3055
3056         ret = hns3_cmd_send(hw, &desc, 1);
3057         if (ret)
3058                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3059
3060         return ret;
3061 }
3062
3063 static int
3064 hns3_get_tc_num(struct hns3_hw *hw)
3065 {
3066         int cnt = 0;
3067         uint8_t i;
3068
3069         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3070                 if (hw->hw_tc_map & BIT(i))
3071                         cnt++;
3072         return cnt;
3073 }
3074
3075 static uint32_t
3076 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3077 {
3078         struct hns3_priv_buf *priv;
3079         uint32_t rx_priv = 0;
3080         int i;
3081
3082         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3083                 priv = &buf_alloc->priv_buf[i];
3084                 if (priv->enable)
3085                         rx_priv += priv->buf_size;
3086         }
3087         return rx_priv;
3088 }
3089
3090 static uint32_t
3091 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3092 {
3093         uint32_t total_tx_size = 0;
3094         uint32_t i;
3095
3096         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3097                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3098
3099         return total_tx_size;
3100 }
3101
3102 /* Get the number of pfc enabled TCs, which have private buffer */
3103 static int
3104 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3105 {
3106         struct hns3_priv_buf *priv;
3107         int cnt = 0;
3108         uint8_t i;
3109
3110         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3111                 priv = &buf_alloc->priv_buf[i];
3112                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3113                         cnt++;
3114         }
3115
3116         return cnt;
3117 }
3118
3119 /* Get the number of pfc disabled TCs, which have private buffer */
3120 static int
3121 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3122                          struct hns3_pkt_buf_alloc *buf_alloc)
3123 {
3124         struct hns3_priv_buf *priv;
3125         int cnt = 0;
3126         uint8_t i;
3127
3128         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3129                 priv = &buf_alloc->priv_buf[i];
3130                 if (hw->hw_tc_map & BIT(i) &&
3131                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3132                         cnt++;
3133         }
3134
3135         return cnt;
3136 }
3137
3138 static bool
3139 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3140                   uint32_t rx_all)
3141 {
3142         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3143         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3144         struct hns3_pf *pf = &hns->pf;
3145         uint32_t shared_buf, aligned_mps;
3146         uint32_t rx_priv;
3147         uint8_t tc_num;
3148         uint8_t i;
3149
3150         tc_num = hns3_get_tc_num(hw);
3151         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3152
3153         if (hns3_dev_dcb_supported(hw))
3154                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3155                                         pf->dv_buf_size;
3156         else
3157                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3158                                         + pf->dv_buf_size;
3159
3160         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3161         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3162                              HNS3_BUF_SIZE_UNIT);
3163
3164         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3165         if (rx_all < rx_priv + shared_std)
3166                 return false;
3167
3168         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3169         buf_alloc->s_buf.buf_size = shared_buf;
3170         if (hns3_dev_dcb_supported(hw)) {
3171                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3172                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3173                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3174                                   HNS3_BUF_SIZE_UNIT);
3175         } else {
3176                 buf_alloc->s_buf.self.high =
3177                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3178                 buf_alloc->s_buf.self.low = aligned_mps;
3179         }
3180
3181         if (hns3_dev_dcb_supported(hw)) {
3182                 hi_thrd = shared_buf - pf->dv_buf_size;
3183
3184                 if (tc_num <= NEED_RESERVE_TC_NUM)
3185                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3186                                         / BUF_MAX_PERCENT;
3187
3188                 if (tc_num)
3189                         hi_thrd = hi_thrd / tc_num;
3190
3191                 hi_thrd = max_t(uint32_t, hi_thrd,
3192                                 HNS3_BUF_MUL_BY * aligned_mps);
3193                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3194                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3195         } else {
3196                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3197                 lo_thrd = aligned_mps;
3198         }
3199
3200         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3201                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3202                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3203         }
3204
3205         return true;
3206 }
3207
3208 static bool
3209 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3210                      struct hns3_pkt_buf_alloc *buf_alloc)
3211 {
3212         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3213         struct hns3_pf *pf = &hns->pf;
3214         struct hns3_priv_buf *priv;
3215         uint32_t aligned_mps;
3216         uint32_t rx_all;
3217         uint8_t i;
3218
3219         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3220         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3221
3222         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3223                 priv = &buf_alloc->priv_buf[i];
3224
3225                 priv->enable = 0;
3226                 priv->wl.low = 0;
3227                 priv->wl.high = 0;
3228                 priv->buf_size = 0;
3229
3230                 if (!(hw->hw_tc_map & BIT(i)))
3231                         continue;
3232
3233                 priv->enable = 1;
3234                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3235                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3236                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3237                                                 HNS3_BUF_SIZE_UNIT);
3238                 } else {
3239                         priv->wl.low = 0;
3240                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3241                                         aligned_mps;
3242                 }
3243
3244                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3245         }
3246
3247         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3248 }
3249
3250 static bool
3251 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3252                              struct hns3_pkt_buf_alloc *buf_alloc)
3253 {
3254         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3255         struct hns3_pf *pf = &hns->pf;
3256         struct hns3_priv_buf *priv;
3257         int no_pfc_priv_num;
3258         uint32_t rx_all;
3259         uint8_t mask;
3260         int i;
3261
3262         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3263         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3264
3265         /* let the last to be cleared first */
3266         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3267                 priv = &buf_alloc->priv_buf[i];
3268                 mask = BIT((uint8_t)i);
3269
3270                 if (hw->hw_tc_map & mask &&
3271                     !(hw->dcb_info.hw_pfc_map & mask)) {
3272                         /* Clear the no pfc TC private buffer */
3273                         priv->wl.low = 0;
3274                         priv->wl.high = 0;
3275                         priv->buf_size = 0;
3276                         priv->enable = 0;
3277                         no_pfc_priv_num--;
3278                 }
3279
3280                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3281                     no_pfc_priv_num == 0)
3282                         break;
3283         }
3284
3285         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3286 }
3287
3288 static bool
3289 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3290                            struct hns3_pkt_buf_alloc *buf_alloc)
3291 {
3292         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3293         struct hns3_pf *pf = &hns->pf;
3294         struct hns3_priv_buf *priv;
3295         uint32_t rx_all;
3296         int pfc_priv_num;
3297         uint8_t mask;
3298         int i;
3299
3300         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3301         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3302
3303         /* let the last to be cleared first */
3304         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3305                 priv = &buf_alloc->priv_buf[i];
3306                 mask = BIT((uint8_t)i);
3307
3308                 if (hw->hw_tc_map & mask &&
3309                     hw->dcb_info.hw_pfc_map & mask) {
3310                         /* Reduce the number of pfc TC with private buffer */
3311                         priv->wl.low = 0;
3312                         priv->enable = 0;
3313                         priv->wl.high = 0;
3314                         priv->buf_size = 0;
3315                         pfc_priv_num--;
3316                 }
3317                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3318                     pfc_priv_num == 0)
3319                         break;
3320         }
3321
3322         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3323 }
3324
3325 static bool
3326 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3327                           struct hns3_pkt_buf_alloc *buf_alloc)
3328 {
3329 #define COMPENSATE_BUFFER       0x3C00
3330 #define COMPENSATE_HALF_MPS_NUM 5
3331 #define PRIV_WL_GAP             0x1800
3332         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3333         struct hns3_pf *pf = &hns->pf;
3334         uint32_t tc_num = hns3_get_tc_num(hw);
3335         uint32_t half_mps = pf->mps >> 1;
3336         struct hns3_priv_buf *priv;
3337         uint32_t min_rx_priv;
3338         uint32_t rx_priv;
3339         uint8_t i;
3340
3341         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3342         if (tc_num)
3343                 rx_priv = rx_priv / tc_num;
3344
3345         if (tc_num <= NEED_RESERVE_TC_NUM)
3346                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3347
3348         /*
3349          * Minimum value of private buffer in rx direction (min_rx_priv) is
3350          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3351          * buffer if rx_priv is greater than min_rx_priv.
3352          */
3353         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3354                         COMPENSATE_HALF_MPS_NUM * half_mps;
3355         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3356         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3357
3358         if (rx_priv < min_rx_priv)
3359                 return false;
3360
3361         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3362                 priv = &buf_alloc->priv_buf[i];
3363
3364                 priv->enable = 0;
3365                 priv->wl.low = 0;
3366                 priv->wl.high = 0;
3367                 priv->buf_size = 0;
3368
3369                 if (!(hw->hw_tc_map & BIT(i)))
3370                         continue;
3371
3372                 priv->enable = 1;
3373                 priv->buf_size = rx_priv;
3374                 priv->wl.high = rx_priv - pf->dv_buf_size;
3375                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3376         }
3377
3378         buf_alloc->s_buf.buf_size = 0;
3379
3380         return true;
3381 }
3382
3383 /*
3384  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3385  * @hw: pointer to struct hns3_hw
3386  * @buf_alloc: pointer to buffer calculation data
3387  * @return: 0: calculate sucessful, negative: fail
3388  */
3389 static int
3390 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3391 {
3392         /* When DCB is not supported, rx private buffer is not allocated. */
3393         if (!hns3_dev_dcb_supported(hw)) {
3394                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3395                 struct hns3_pf *pf = &hns->pf;
3396                 uint32_t rx_all = pf->pkt_buf_size;
3397
3398                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3399                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3400                         return -ENOMEM;
3401
3402                 return 0;
3403         }
3404
3405         /*
3406          * Try to allocate privated packet buffer for all TCs without share
3407          * buffer.
3408          */
3409         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3410                 return 0;
3411
3412         /*
3413          * Try to allocate privated packet buffer for all TCs with share
3414          * buffer.
3415          */
3416         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3417                 return 0;
3418
3419         /*
3420          * For different application scenes, the enabled port number, TC number
3421          * and no_drop TC number are different. In order to obtain the better
3422          * performance, software could allocate the buffer size and configure
3423          * the waterline by tring to decrease the private buffer size according
3424          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3425          * enabled tc.
3426          */
3427         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3428                 return 0;
3429
3430         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3431                 return 0;
3432
3433         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3434                 return 0;
3435
3436         return -ENOMEM;
3437 }
3438
3439 static int
3440 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3441 {
3442         struct hns3_rx_priv_buff_cmd *req;
3443         struct hns3_cmd_desc desc;
3444         uint32_t buf_size;
3445         int ret;
3446         int i;
3447
3448         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3449         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3450
3451         /* Alloc private buffer TCs */
3452         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3453                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3454
3455                 req->buf_num[i] =
3456                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3457                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3458         }
3459
3460         buf_size = buf_alloc->s_buf.buf_size;
3461         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3462                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3463
3464         ret = hns3_cmd_send(hw, &desc, 1);
3465         if (ret)
3466                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3467
3468         return ret;
3469 }
3470
3471 static int
3472 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3473 {
3474 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3475         struct hns3_rx_priv_wl_buf *req;
3476         struct hns3_priv_buf *priv;
3477         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3478         int i, j;
3479         int ret;
3480
3481         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3482                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3483                                           false);
3484                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3485
3486                 /* The first descriptor set the NEXT bit to 1 */
3487                 if (i == 0)
3488                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3489                 else
3490                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3491
3492                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3493                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3494
3495                         priv = &buf_alloc->priv_buf[idx];
3496                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3497                                                         HNS3_BUF_UNIT_S);
3498                         req->tc_wl[j].high |=
3499                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3500                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3501                                                         HNS3_BUF_UNIT_S);
3502                         req->tc_wl[j].low |=
3503                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3504                 }
3505         }
3506
3507         /* Send 2 descriptor at one time */
3508         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3509         if (ret)
3510                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3511                              ret);
3512         return ret;
3513 }
3514
3515 static int
3516 hns3_common_thrd_config(struct hns3_hw *hw,
3517                         struct hns3_pkt_buf_alloc *buf_alloc)
3518 {
3519 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3520         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3521         struct hns3_rx_com_thrd *req;
3522         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3523         struct hns3_tc_thrd *tc;
3524         int tc_idx;
3525         int i, j;
3526         int ret;
3527
3528         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3529                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3530                                           false);
3531                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3532
3533                 /* The first descriptor set the NEXT bit to 1 */
3534                 if (i == 0)
3535                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3536                 else
3537                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3538
3539                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3540                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3541                         tc = &s_buf->tc_thrd[tc_idx];
3542
3543                         req->com_thrd[j].high =
3544                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3545                         req->com_thrd[j].high |=
3546                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3547                         req->com_thrd[j].low =
3548                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3549                         req->com_thrd[j].low |=
3550                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3551                 }
3552         }
3553
3554         /* Send 2 descriptors at one time */
3555         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3556         if (ret)
3557                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3558
3559         return ret;
3560 }
3561
3562 static int
3563 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3564 {
3565         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3566         struct hns3_rx_com_wl *req;
3567         struct hns3_cmd_desc desc;
3568         int ret;
3569
3570         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3571
3572         req = (struct hns3_rx_com_wl *)desc.data;
3573         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3574         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3575
3576         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3577         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3578
3579         ret = hns3_cmd_send(hw, &desc, 1);
3580         if (ret)
3581                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3582
3583         return ret;
3584 }
3585
3586 int
3587 hns3_buffer_alloc(struct hns3_hw *hw)
3588 {
3589         struct hns3_pkt_buf_alloc pkt_buf;
3590         int ret;
3591
3592         memset(&pkt_buf, 0, sizeof(pkt_buf));
3593         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3594         if (ret) {
3595                 PMD_INIT_LOG(ERR,
3596                              "could not calc tx buffer size for all TCs %d",
3597                              ret);
3598                 return ret;
3599         }
3600
3601         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3602         if (ret) {
3603                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3604                 return ret;
3605         }
3606
3607         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3608         if (ret) {
3609                 PMD_INIT_LOG(ERR,
3610                              "could not calc rx priv buffer size for all TCs %d",
3611                              ret);
3612                 return ret;
3613         }
3614
3615         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3616         if (ret) {
3617                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3618                 return ret;
3619         }
3620
3621         if (hns3_dev_dcb_supported(hw)) {
3622                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3623                 if (ret) {
3624                         PMD_INIT_LOG(ERR,
3625                                      "could not configure rx private waterline %d",
3626                                      ret);
3627                         return ret;
3628                 }
3629
3630                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3631                 if (ret) {
3632                         PMD_INIT_LOG(ERR,
3633                                      "could not configure common threshold %d",
3634                                      ret);
3635                         return ret;
3636                 }
3637         }
3638
3639         ret = hns3_common_wl_config(hw, &pkt_buf);
3640         if (ret)
3641                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3642                              ret);
3643
3644         return ret;
3645 }
3646
3647 static int
3648 hns3_mac_init(struct hns3_hw *hw)
3649 {
3650         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3651         struct hns3_mac *mac = &hw->mac;
3652         struct hns3_pf *pf = &hns->pf;
3653         int ret;
3654
3655         pf->support_sfp_query = true;
3656         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3657         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3658         if (ret) {
3659                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3660                 return ret;
3661         }
3662
3663         mac->link_status = ETH_LINK_DOWN;
3664
3665         return hns3_config_mtu(hw, pf->mps);
3666 }
3667
3668 static int
3669 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3670 {
3671 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3672 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3673 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3674 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3675         int return_status;
3676
3677         if (cmdq_resp) {
3678                 PMD_INIT_LOG(ERR,
3679                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3680                              cmdq_resp);
3681                 return -EIO;
3682         }
3683
3684         switch (resp_code) {
3685         case HNS3_ETHERTYPE_SUCCESS_ADD:
3686         case HNS3_ETHERTYPE_ALREADY_ADD:
3687                 return_status = 0;
3688                 break;
3689         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3690                 PMD_INIT_LOG(ERR,
3691                              "add mac ethertype failed for manager table overflow.");
3692                 return_status = -EIO;
3693                 break;
3694         case HNS3_ETHERTYPE_KEY_CONFLICT:
3695                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3696                 return_status = -EIO;
3697                 break;
3698         default:
3699                 PMD_INIT_LOG(ERR,
3700                              "add mac ethertype failed for undefined, code=%d.",
3701                              resp_code);
3702                 return_status = -EIO;
3703                 break;
3704         }
3705
3706         return return_status;
3707 }
3708
3709 static int
3710 hns3_add_mgr_tbl(struct hns3_hw *hw,
3711                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3712 {
3713         struct hns3_cmd_desc desc;
3714         uint8_t resp_code;
3715         uint16_t retval;
3716         int ret;
3717
3718         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3719         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3720
3721         ret = hns3_cmd_send(hw, &desc, 1);
3722         if (ret) {
3723                 PMD_INIT_LOG(ERR,
3724                              "add mac ethertype failed for cmd_send, ret =%d.",
3725                              ret);
3726                 return ret;
3727         }
3728
3729         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3730         retval = rte_le_to_cpu_16(desc.retval);
3731
3732         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3733 }
3734
3735 static void
3736 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3737                      int *table_item_num)
3738 {
3739         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3740
3741         /*
3742          * In current version, we add one item in management table as below:
3743          * 0x0180C200000E -- LLDP MC address
3744          */
3745         tbl = mgr_table;
3746         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3747         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3748         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3749         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3750         tbl->i_port_bitmap = 0x1;
3751         *table_item_num = 1;
3752 }
3753
3754 static int
3755 hns3_init_mgr_tbl(struct hns3_hw *hw)
3756 {
3757 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3758         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3759         int table_item_num;
3760         int ret;
3761         int i;
3762
3763         memset(mgr_table, 0, sizeof(mgr_table));
3764         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3765         for (i = 0; i < table_item_num; i++) {
3766                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3767                 if (ret) {
3768                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3769                                      ret);
3770                         return ret;
3771                 }
3772         }
3773
3774         return 0;
3775 }
3776
3777 static void
3778 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3779                         bool en_mc, bool en_bc, int vport_id)
3780 {
3781         if (!param)
3782                 return;
3783
3784         memset(param, 0, sizeof(struct hns3_promisc_param));
3785         if (en_uc)
3786                 param->enable = HNS3_PROMISC_EN_UC;
3787         if (en_mc)
3788                 param->enable |= HNS3_PROMISC_EN_MC;
3789         if (en_bc)
3790                 param->enable |= HNS3_PROMISC_EN_BC;
3791         param->vf_id = vport_id;
3792 }
3793
3794 static int
3795 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3796 {
3797         struct hns3_promisc_cfg_cmd *req;
3798         struct hns3_cmd_desc desc;
3799         int ret;
3800
3801         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3802
3803         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3804         req->vf_id = param->vf_id;
3805         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3806             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3807
3808         ret = hns3_cmd_send(hw, &desc, 1);
3809         if (ret)
3810                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3811
3812         return ret;
3813 }
3814
3815 static int
3816 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3817 {
3818         struct hns3_promisc_param param;
3819         bool en_bc_pmc = true;
3820         uint8_t vf_id;
3821
3822         /*
3823          * In current version VF is not supported when PF is driven by DPDK
3824          * driver, just need to configure parameters for PF vport.
3825          */
3826         vf_id = HNS3_PF_FUNC_ID;
3827
3828         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3829         return hns3_cmd_set_promisc_mode(hw, &param);
3830 }
3831
3832 static int
3833 hns3_promisc_init(struct hns3_hw *hw)
3834 {
3835         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3836         struct hns3_pf *pf = &hns->pf;
3837         struct hns3_promisc_param param;
3838         uint16_t func_id;
3839         int ret;
3840
3841         ret = hns3_set_promisc_mode(hw, false, false);
3842         if (ret) {
3843                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
3844                 return ret;
3845         }
3846
3847         /*
3848          * In current version VFs are not supported when PF is driven by DPDK
3849          * driver. After PF has been taken over by DPDK, the original VF will
3850          * be invalid. So, there is a possibility of entry residues. It should
3851          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
3852          * during init.
3853          */
3854         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
3855                 hns3_promisc_param_init(&param, false, false, false, func_id);
3856                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3857                 if (ret) {
3858                         PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode,"
3859                                         " ret = %d", func_id, ret);
3860                         return ret;
3861                 }
3862         }
3863
3864         return 0;
3865 }
3866
3867 static void
3868 hns3_promisc_uninit(struct hns3_hw *hw)
3869 {
3870         struct hns3_promisc_param param;
3871         uint16_t func_id;
3872         int ret;
3873
3874         func_id = HNS3_PF_FUNC_ID;
3875
3876         /*
3877          * In current version VFs are not supported when PF is driven by
3878          * DPDK driver, and VFs' promisc mode status has been cleared during
3879          * init and their status will not change. So just clear PF's promisc
3880          * mode status during uninit.
3881          */
3882         hns3_promisc_param_init(&param, false, false, false, func_id);
3883         ret = hns3_cmd_set_promisc_mode(hw, &param);
3884         if (ret)
3885                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
3886                                 " uninit, ret = %d", ret);
3887 }
3888
3889 static int
3890 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3891 {
3892         bool allmulti = dev->data->all_multicast ? true : false;
3893         struct hns3_adapter *hns = dev->data->dev_private;
3894         struct hns3_hw *hw = &hns->hw;
3895         uint64_t offloads;
3896         int err;
3897         int ret;
3898
3899         rte_spinlock_lock(&hw->lock);
3900         ret = hns3_set_promisc_mode(hw, true, true);
3901         if (ret) {
3902                 rte_spinlock_unlock(&hw->lock);
3903                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
3904                          ret);
3905                 return ret;
3906         }
3907
3908         /*
3909          * When promiscuous mode was enabled, disable the vlan filter to let
3910          * all packets coming in in the receiving direction.
3911          */
3912         offloads = dev->data->dev_conf.rxmode.offloads;
3913         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3914                 ret = hns3_enable_vlan_filter(hns, false);
3915                 if (ret) {
3916                         hns3_err(hw, "failed to enable promiscuous mode due to "
3917                                      "failure to disable vlan filter, ret = %d",
3918                                  ret);
3919                         err = hns3_set_promisc_mode(hw, false, allmulti);
3920                         if (err)
3921                                 hns3_err(hw, "failed to restore promiscuous "
3922                                          "status after disable vlan filter "
3923                                          "failed during enabling promiscuous "
3924                                          "mode, ret = %d", ret);
3925                 }
3926         }
3927
3928         rte_spinlock_unlock(&hw->lock);
3929
3930         return ret;
3931 }
3932
3933 static int
3934 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3935 {
3936         bool allmulti = dev->data->all_multicast ? true : false;
3937         struct hns3_adapter *hns = dev->data->dev_private;
3938         struct hns3_hw *hw = &hns->hw;
3939         uint64_t offloads;
3940         int err;
3941         int ret;
3942
3943         /* If now in all_multicast mode, must remain in all_multicast mode. */
3944         rte_spinlock_lock(&hw->lock);
3945         ret = hns3_set_promisc_mode(hw, false, allmulti);
3946         if (ret) {
3947                 rte_spinlock_unlock(&hw->lock);
3948                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
3949                          ret);
3950                 return ret;
3951         }
3952         /* when promiscuous mode was disabled, restore the vlan filter status */
3953         offloads = dev->data->dev_conf.rxmode.offloads;
3954         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3955                 ret = hns3_enable_vlan_filter(hns, true);
3956                 if (ret) {
3957                         hns3_err(hw, "failed to disable promiscuous mode due to"
3958                                  " failure to restore vlan filter, ret = %d",
3959                                  ret);
3960                         err = hns3_set_promisc_mode(hw, true, true);
3961                         if (err)
3962                                 hns3_err(hw, "failed to restore promiscuous "
3963                                          "status after enabling vlan filter "
3964                                          "failed during disabling promiscuous "
3965                                          "mode, ret = %d", ret);
3966                 }
3967         }
3968         rte_spinlock_unlock(&hw->lock);
3969
3970         return ret;
3971 }
3972
3973 static int
3974 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3975 {
3976         struct hns3_adapter *hns = dev->data->dev_private;
3977         struct hns3_hw *hw = &hns->hw;
3978         int ret;
3979
3980         if (dev->data->promiscuous)
3981                 return 0;
3982
3983         rte_spinlock_lock(&hw->lock);
3984         ret = hns3_set_promisc_mode(hw, false, true);
3985         rte_spinlock_unlock(&hw->lock);
3986         if (ret)
3987                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
3988                          ret);
3989
3990         return ret;
3991 }
3992
3993 static int
3994 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3995 {
3996         struct hns3_adapter *hns = dev->data->dev_private;
3997         struct hns3_hw *hw = &hns->hw;
3998         int ret;
3999
4000         /* If now in promiscuous mode, must remain in all_multicast mode. */
4001         if (dev->data->promiscuous)
4002                 return 0;
4003
4004         rte_spinlock_lock(&hw->lock);
4005         ret = hns3_set_promisc_mode(hw, false, false);
4006         rte_spinlock_unlock(&hw->lock);
4007         if (ret)
4008                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4009                          ret);
4010
4011         return ret;
4012 }
4013
4014 static int
4015 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4016 {
4017         struct hns3_hw *hw = &hns->hw;
4018         bool allmulti = hw->data->all_multicast ? true : false;
4019         int ret;
4020
4021         if (hw->data->promiscuous) {
4022                 ret = hns3_set_promisc_mode(hw, true, true);
4023                 if (ret)
4024                         hns3_err(hw, "failed to restore promiscuous mode, "
4025                                  "ret = %d", ret);
4026                 return ret;
4027         }
4028
4029         ret = hns3_set_promisc_mode(hw, false, allmulti);
4030         if (ret)
4031                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4032                          ret);
4033         return ret;
4034 }
4035
4036 static int
4037 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4038 {
4039         struct hns3_sfp_speed_cmd *resp;
4040         struct hns3_cmd_desc desc;
4041         int ret;
4042
4043         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4044         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4045         ret = hns3_cmd_send(hw, &desc, 1);
4046         if (ret == -EOPNOTSUPP) {
4047                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4048                 return ret;
4049         } else if (ret) {
4050                 hns3_err(hw, "get sfp speed failed %d", ret);
4051                 return ret;
4052         }
4053
4054         *speed = resp->sfp_speed;
4055
4056         return 0;
4057 }
4058
4059 static uint8_t
4060 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4061 {
4062         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4063                 duplex = ETH_LINK_FULL_DUPLEX;
4064
4065         return duplex;
4066 }
4067
4068 static int
4069 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4070 {
4071         struct hns3_mac *mac = &hw->mac;
4072         int ret;
4073
4074         duplex = hns3_check_speed_dup(duplex, speed);
4075         if (mac->link_speed == speed && mac->link_duplex == duplex)
4076                 return 0;
4077
4078         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4079         if (ret)
4080                 return ret;
4081
4082         mac->link_speed = speed;
4083         mac->link_duplex = duplex;
4084
4085         return 0;
4086 }
4087
4088 static int
4089 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4090 {
4091         struct hns3_adapter *hns = eth_dev->data->dev_private;
4092         struct hns3_hw *hw = &hns->hw;
4093         struct hns3_pf *pf = &hns->pf;
4094         uint32_t speed;
4095         int ret;
4096
4097         /* If IMP do not support get SFP/qSFP speed, return directly */
4098         if (!pf->support_sfp_query)
4099                 return 0;
4100
4101         ret = hns3_get_sfp_speed(hw, &speed);
4102         if (ret == -EOPNOTSUPP) {
4103                 pf->support_sfp_query = false;
4104                 return ret;
4105         } else if (ret)
4106                 return ret;
4107
4108         if (speed == ETH_SPEED_NUM_NONE)
4109                 return 0; /* do nothing if no SFP */
4110
4111         /* Config full duplex for SFP */
4112         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4113 }
4114
4115 static int
4116 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4117 {
4118         struct hns3_config_mac_mode_cmd *req;
4119         struct hns3_cmd_desc desc;
4120         uint32_t loop_en = 0;
4121         uint8_t val = 0;
4122         int ret;
4123
4124         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4125
4126         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4127         if (enable)
4128                 val = 1;
4129         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4130         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4131         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4132         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4133         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4134         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4135         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4136         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4137         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4138         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4139         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4140         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4141         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4142         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4143         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4144
4145         ret = hns3_cmd_send(hw, &desc, 1);
4146         if (ret)
4147                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4148
4149         return ret;
4150 }
4151
4152 static int
4153 hns3_get_mac_link_status(struct hns3_hw *hw)
4154 {
4155         struct hns3_link_status_cmd *req;
4156         struct hns3_cmd_desc desc;
4157         int link_status;
4158         int ret;
4159
4160         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4161         ret = hns3_cmd_send(hw, &desc, 1);
4162         if (ret) {
4163                 hns3_err(hw, "get link status cmd failed %d", ret);
4164                 return ETH_LINK_DOWN;
4165         }
4166
4167         req = (struct hns3_link_status_cmd *)desc.data;
4168         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4169
4170         return !!link_status;
4171 }
4172
4173 void
4174 hns3_update_link_status(struct hns3_hw *hw)
4175 {
4176         int state;
4177
4178         state = hns3_get_mac_link_status(hw);
4179         if (state != hw->mac.link_status) {
4180                 hw->mac.link_status = state;
4181                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4182         }
4183 }
4184
4185 static void
4186 hns3_service_handler(void *param)
4187 {
4188         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4189         struct hns3_adapter *hns = eth_dev->data->dev_private;
4190         struct hns3_hw *hw = &hns->hw;
4191
4192         if (!hns3_is_reset_pending(hns)) {
4193                 hns3_update_speed_duplex(eth_dev);
4194                 hns3_update_link_status(hw);
4195         } else
4196                 hns3_warn(hw, "Cancel the query when reset is pending");
4197
4198         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4199 }
4200
4201 static int
4202 hns3_init_hardware(struct hns3_adapter *hns)
4203 {
4204         struct hns3_hw *hw = &hns->hw;
4205         int ret;
4206
4207         ret = hns3_map_tqp(hw);
4208         if (ret) {
4209                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4210                 return ret;
4211         }
4212
4213         ret = hns3_init_umv_space(hw);
4214         if (ret) {
4215                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4216                 return ret;
4217         }
4218
4219         ret = hns3_mac_init(hw);
4220         if (ret) {
4221                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4222                 goto err_mac_init;
4223         }
4224
4225         ret = hns3_init_mgr_tbl(hw);
4226         if (ret) {
4227                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4228                 goto err_mac_init;
4229         }
4230
4231         ret = hns3_promisc_init(hw);
4232         if (ret) {
4233                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4234                              ret);
4235                 goto err_mac_init;
4236         }
4237
4238         ret = hns3_init_vlan_config(hns);
4239         if (ret) {
4240                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4241                 goto err_mac_init;
4242         }
4243
4244         ret = hns3_dcb_init(hw);
4245         if (ret) {
4246                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4247                 goto err_mac_init;
4248         }
4249
4250         ret = hns3_init_fd_config(hns);
4251         if (ret) {
4252                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4253                 goto err_mac_init;
4254         }
4255
4256         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4257         if (ret) {
4258                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4259                 goto err_mac_init;
4260         }
4261
4262         ret = hns3_config_gro(hw, false);
4263         if (ret) {
4264                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4265                 goto err_mac_init;
4266         }
4267
4268         /*
4269          * In the initialization clearing the all hardware mapping relationship
4270          * configurations between queues and interrupt vectors is needed, so
4271          * some error caused by the residual configurations, such as the
4272          * unexpected interrupt, can be avoid.
4273          */
4274         ret = hns3_init_ring_with_vector(hw);
4275         if (ret) {
4276                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4277                 goto err_mac_init;
4278         }
4279
4280         return 0;
4281
4282 err_mac_init:
4283         hns3_uninit_umv_space(hw);
4284         return ret;
4285 }
4286
4287 static int
4288 hns3_init_pf(struct rte_eth_dev *eth_dev)
4289 {
4290         struct rte_device *dev = eth_dev->device;
4291         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4292         struct hns3_adapter *hns = eth_dev->data->dev_private;
4293         struct hns3_hw *hw = &hns->hw;
4294         int ret;
4295
4296         PMD_INIT_FUNC_TRACE();
4297
4298         /* Get hardware io base address from pcie BAR2 IO space */
4299         hw->io_base = pci_dev->mem_resource[2].addr;
4300
4301         /* Firmware command queue initialize */
4302         ret = hns3_cmd_init_queue(hw);
4303         if (ret) {
4304                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4305                 goto err_cmd_init_queue;
4306         }
4307
4308         hns3_clear_all_event_cause(hw);
4309
4310         /* Firmware command initialize */
4311         ret = hns3_cmd_init(hw);
4312         if (ret) {
4313                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4314                 goto err_cmd_init;
4315         }
4316
4317         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4318                                          hns3_interrupt_handler,
4319                                          eth_dev);
4320         if (ret) {
4321                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4322                 goto err_intr_callback_register;
4323         }
4324
4325         /* Enable interrupt */
4326         rte_intr_enable(&pci_dev->intr_handle);
4327         hns3_pf_enable_irq0(hw);
4328
4329         /* Get configuration */
4330         ret = hns3_get_configuration(hw);
4331         if (ret) {
4332                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4333                 goto err_get_config;
4334         }
4335
4336         ret = hns3_init_hardware(hns);
4337         if (ret) {
4338                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4339                 goto err_get_config;
4340         }
4341
4342         /* Initialize flow director filter list & hash */
4343         ret = hns3_fdir_filter_init(hns);
4344         if (ret) {
4345                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4346                 goto err_hw_init;
4347         }
4348
4349         hns3_set_default_rss_args(hw);
4350
4351         ret = hns3_enable_hw_error_intr(hns, true);
4352         if (ret) {
4353                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4354                              ret);
4355                 goto err_fdir;
4356         }
4357
4358         return 0;
4359
4360 err_fdir:
4361         hns3_fdir_filter_uninit(hns);
4362 err_hw_init:
4363         hns3_uninit_umv_space(hw);
4364
4365 err_get_config:
4366         hns3_pf_disable_irq0(hw);
4367         rte_intr_disable(&pci_dev->intr_handle);
4368         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4369                              eth_dev);
4370 err_intr_callback_register:
4371 err_cmd_init:
4372         hns3_cmd_uninit(hw);
4373         hns3_cmd_destroy_queue(hw);
4374 err_cmd_init_queue:
4375         hw->io_base = NULL;
4376
4377         return ret;
4378 }
4379
4380 static void
4381 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4382 {
4383         struct hns3_adapter *hns = eth_dev->data->dev_private;
4384         struct rte_device *dev = eth_dev->device;
4385         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4386         struct hns3_hw *hw = &hns->hw;
4387
4388         PMD_INIT_FUNC_TRACE();
4389
4390         hns3_enable_hw_error_intr(hns, false);
4391         hns3_rss_uninit(hns);
4392         hns3_promisc_uninit(hw);
4393         hns3_fdir_filter_uninit(hns);
4394         hns3_uninit_umv_space(hw);
4395         hns3_pf_disable_irq0(hw);
4396         rte_intr_disable(&pci_dev->intr_handle);
4397         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4398                              eth_dev);
4399         hns3_cmd_uninit(hw);
4400         hns3_cmd_destroy_queue(hw);
4401         hw->io_base = NULL;
4402 }
4403
4404 static int
4405 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4406 {
4407         struct hns3_hw *hw = &hns->hw;
4408         int ret;
4409
4410         ret = hns3_dcb_cfg_update(hns);
4411         if (ret)
4412                 return ret;
4413
4414         /* Enable queues */
4415         ret = hns3_start_queues(hns, reset_queue);
4416         if (ret) {
4417                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4418                 return ret;
4419         }
4420
4421         /* Enable MAC */
4422         ret = hns3_cfg_mac_mode(hw, true);
4423         if (ret) {
4424                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4425                 goto err_config_mac_mode;
4426         }
4427         return 0;
4428
4429 err_config_mac_mode:
4430         hns3_stop_queues(hns, true);
4431         return ret;
4432 }
4433
4434 static int
4435 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4436 {
4437         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4438         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4439         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4440         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4441         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4442         uint32_t intr_vector;
4443         uint16_t q_id;
4444         int ret;
4445
4446         if (dev->data->dev_conf.intr_conf.rxq == 0)
4447                 return 0;
4448
4449         /* disable uio/vfio intr/eventfd mapping */
4450         rte_intr_disable(intr_handle);
4451
4452         /* check and configure queue intr-vector mapping */
4453         if (rte_intr_cap_multiple(intr_handle) ||
4454             !RTE_ETH_DEV_SRIOV(dev).active) {
4455                 intr_vector = hw->used_rx_queues;
4456                 /* creates event fd for each intr vector when MSIX is used */
4457                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4458                         return -EINVAL;
4459         }
4460         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4461                 intr_handle->intr_vec =
4462                         rte_zmalloc("intr_vec",
4463                                     hw->used_rx_queues * sizeof(int), 0);
4464                 if (intr_handle->intr_vec == NULL) {
4465                         hns3_err(hw, "Failed to allocate %d rx_queues"
4466                                      " intr_vec", hw->used_rx_queues);
4467                         ret = -ENOMEM;
4468                         goto alloc_intr_vec_error;
4469                 }
4470         }
4471
4472         if (rte_intr_allow_others(intr_handle)) {
4473                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4474                 base = RTE_INTR_VEC_RXTX_OFFSET;
4475         }
4476         if (rte_intr_dp_is_en(intr_handle)) {
4477                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4478                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4479                                                          HNS3_RING_TYPE_RX,
4480                                                          q_id);
4481                         if (ret)
4482                                 goto bind_vector_error;
4483                         intr_handle->intr_vec[q_id] = vec;
4484                         if (vec < base + intr_handle->nb_efd - 1)
4485                                 vec++;
4486                 }
4487         }
4488         rte_intr_enable(intr_handle);
4489         return 0;
4490
4491 bind_vector_error:
4492         rte_intr_efd_disable(intr_handle);
4493         if (intr_handle->intr_vec) {
4494                 free(intr_handle->intr_vec);
4495                 intr_handle->intr_vec = NULL;
4496         }
4497         return ret;
4498 alloc_intr_vec_error:
4499         rte_intr_efd_disable(intr_handle);
4500         return ret;
4501 }
4502
4503 static int
4504 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4505 {
4506         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4507         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4508         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4509         uint16_t q_id;
4510         int ret;
4511
4512         if (dev->data->dev_conf.intr_conf.rxq == 0)
4513                 return 0;
4514
4515         if (rte_intr_dp_is_en(intr_handle)) {
4516                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4517                         ret = hns3_bind_ring_with_vector(hw,
4518                                         intr_handle->intr_vec[q_id], true,
4519                                         HNS3_RING_TYPE_RX, q_id);
4520                         if (ret)
4521                                 return ret;
4522                 }
4523         }
4524
4525         return 0;
4526 }
4527
4528 static void
4529 hns3_restore_filter(struct rte_eth_dev *dev)
4530 {
4531         hns3_restore_rss_filter(dev);
4532 }
4533
4534 static int
4535 hns3_dev_start(struct rte_eth_dev *dev)
4536 {
4537         struct hns3_adapter *hns = dev->data->dev_private;
4538         struct hns3_hw *hw = &hns->hw;
4539         int ret;
4540
4541         PMD_INIT_FUNC_TRACE();
4542         if (rte_atomic16_read(&hw->reset.resetting))
4543                 return -EBUSY;
4544
4545         rte_spinlock_lock(&hw->lock);
4546         hw->adapter_state = HNS3_NIC_STARTING;
4547
4548         ret = hns3_do_start(hns, true);
4549         if (ret) {
4550                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4551                 rte_spinlock_unlock(&hw->lock);
4552                 return ret;
4553         }
4554         ret = hns3_map_rx_interrupt(dev);
4555         if (ret) {
4556                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4557                 rte_spinlock_unlock(&hw->lock);
4558                 return ret;
4559         }
4560
4561         hw->adapter_state = HNS3_NIC_STARTED;
4562         rte_spinlock_unlock(&hw->lock);
4563
4564         hns3_set_rxtx_function(dev);
4565         hns3_mp_req_start_rxtx(dev);
4566         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4567
4568         hns3_restore_filter(dev);
4569
4570         /* Enable interrupt of all rx queues before enabling queues */
4571         hns3_dev_all_rx_queue_intr_enable(hw, true);
4572         /*
4573          * When finished the initialization, enable queues to receive/transmit
4574          * packets.
4575          */
4576         hns3_enable_all_queues(hw, true);
4577
4578         hns3_info(hw, "hns3 dev start successful!");
4579         return 0;
4580 }
4581
4582 static int
4583 hns3_do_stop(struct hns3_adapter *hns)
4584 {
4585         struct hns3_hw *hw = &hns->hw;
4586         bool reset_queue;
4587         int ret;
4588
4589         ret = hns3_cfg_mac_mode(hw, false);
4590         if (ret)
4591                 return ret;
4592         hw->mac.link_status = ETH_LINK_DOWN;
4593
4594         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4595                 hns3_configure_all_mac_addr(hns, true);
4596                 reset_queue = true;
4597         } else
4598                 reset_queue = false;
4599         hw->mac.default_addr_setted = false;
4600         return hns3_stop_queues(hns, reset_queue);
4601 }
4602
4603 static void
4604 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4605 {
4606         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4607         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4608         struct hns3_adapter *hns = dev->data->dev_private;
4609         struct hns3_hw *hw = &hns->hw;
4610         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4611         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4612         uint16_t q_id;
4613
4614         if (dev->data->dev_conf.intr_conf.rxq == 0)
4615                 return;
4616
4617         /* unmap the ring with vector */
4618         if (rte_intr_allow_others(intr_handle)) {
4619                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4620                 base = RTE_INTR_VEC_RXTX_OFFSET;
4621         }
4622         if (rte_intr_dp_is_en(intr_handle)) {
4623                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4624                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4625                                                          HNS3_RING_TYPE_RX,
4626                                                          q_id);
4627                         if (vec < base + intr_handle->nb_efd - 1)
4628                                 vec++;
4629                 }
4630         }
4631         /* Clean datapath event and queue/vec mapping */
4632         rte_intr_efd_disable(intr_handle);
4633         if (intr_handle->intr_vec) {
4634                 rte_free(intr_handle->intr_vec);
4635                 intr_handle->intr_vec = NULL;
4636         }
4637 }
4638
4639 static void
4640 hns3_dev_stop(struct rte_eth_dev *dev)
4641 {
4642         struct hns3_adapter *hns = dev->data->dev_private;
4643         struct hns3_hw *hw = &hns->hw;
4644
4645         PMD_INIT_FUNC_TRACE();
4646
4647         hw->adapter_state = HNS3_NIC_STOPPING;
4648         hns3_set_rxtx_function(dev);
4649         rte_wmb();
4650         /* Disable datapath on secondary process. */
4651         hns3_mp_req_stop_rxtx(dev);
4652         /* Prevent crashes when queues are still in use. */
4653         rte_delay_ms(hw->tqps_num);
4654
4655         rte_spinlock_lock(&hw->lock);
4656         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4657                 hns3_do_stop(hns);
4658                 hns3_unmap_rx_interrupt(dev);
4659                 hns3_dev_release_mbufs(hns);
4660                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4661         }
4662         rte_eal_alarm_cancel(hns3_service_handler, dev);
4663         rte_spinlock_unlock(&hw->lock);
4664 }
4665
4666 static void
4667 hns3_dev_close(struct rte_eth_dev *eth_dev)
4668 {
4669         struct hns3_adapter *hns = eth_dev->data->dev_private;
4670         struct hns3_hw *hw = &hns->hw;
4671
4672         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4673                 rte_free(eth_dev->process_private);
4674                 eth_dev->process_private = NULL;
4675                 return;
4676         }
4677
4678         if (hw->adapter_state == HNS3_NIC_STARTED)
4679                 hns3_dev_stop(eth_dev);
4680
4681         hw->adapter_state = HNS3_NIC_CLOSING;
4682         hns3_reset_abort(hns);
4683         hw->adapter_state = HNS3_NIC_CLOSED;
4684
4685         hns3_configure_all_mc_mac_addr(hns, true);
4686         hns3_remove_all_vlan_table(hns);
4687         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4688         hns3_uninit_pf(eth_dev);
4689         hns3_free_all_queues(eth_dev);
4690         rte_free(hw->reset.wait_data);
4691         rte_free(eth_dev->process_private);
4692         eth_dev->process_private = NULL;
4693         hns3_mp_uninit_primary();
4694         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4695 }
4696
4697 static int
4698 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4699 {
4700         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4701         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4702
4703         fc_conf->pause_time = pf->pause_time;
4704
4705         /* return fc current mode */
4706         switch (hw->current_mode) {
4707         case HNS3_FC_FULL:
4708                 fc_conf->mode = RTE_FC_FULL;
4709                 break;
4710         case HNS3_FC_TX_PAUSE:
4711                 fc_conf->mode = RTE_FC_TX_PAUSE;
4712                 break;
4713         case HNS3_FC_RX_PAUSE:
4714                 fc_conf->mode = RTE_FC_RX_PAUSE;
4715                 break;
4716         case HNS3_FC_NONE:
4717         default:
4718                 fc_conf->mode = RTE_FC_NONE;
4719                 break;
4720         }
4721
4722         return 0;
4723 }
4724
4725 static void
4726 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4727 {
4728         switch (mode) {
4729         case RTE_FC_NONE:
4730                 hw->requested_mode = HNS3_FC_NONE;
4731                 break;
4732         case RTE_FC_RX_PAUSE:
4733                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4734                 break;
4735         case RTE_FC_TX_PAUSE:
4736                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4737                 break;
4738         case RTE_FC_FULL:
4739                 hw->requested_mode = HNS3_FC_FULL;
4740                 break;
4741         default:
4742                 hw->requested_mode = HNS3_FC_NONE;
4743                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4744                           "configured to RTE_FC_NONE", mode);
4745                 break;
4746         }
4747 }
4748
4749 static int
4750 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4751 {
4752         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4753         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4754         int ret;
4755
4756         if (fc_conf->high_water || fc_conf->low_water ||
4757             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4758                 hns3_err(hw, "Unsupported flow control settings specified, "
4759                          "high_water(%u), low_water(%u), send_xon(%u) and "
4760                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4761                          fc_conf->high_water, fc_conf->low_water,
4762                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4763                 return -EINVAL;
4764         }
4765         if (fc_conf->autoneg) {
4766                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4767                 return -EINVAL;
4768         }
4769         if (!fc_conf->pause_time) {
4770                 hns3_err(hw, "Invalid pause time %d setting.",
4771                          fc_conf->pause_time);
4772                 return -EINVAL;
4773         }
4774
4775         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4776             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4777                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4778                          "current_fc_status = %d", hw->current_fc_status);
4779                 return -EOPNOTSUPP;
4780         }
4781
4782         hns3_get_fc_mode(hw, fc_conf->mode);
4783         if (hw->requested_mode == hw->current_mode &&
4784             pf->pause_time == fc_conf->pause_time)
4785                 return 0;
4786
4787         rte_spinlock_lock(&hw->lock);
4788         ret = hns3_fc_enable(dev, fc_conf);
4789         rte_spinlock_unlock(&hw->lock);
4790
4791         return ret;
4792 }
4793
4794 static int
4795 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4796                             struct rte_eth_pfc_conf *pfc_conf)
4797 {
4798         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4799         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4800         uint8_t priority;
4801         int ret;
4802
4803         if (!hns3_dev_dcb_supported(hw)) {
4804                 hns3_err(hw, "This port does not support dcb configurations.");
4805                 return -EOPNOTSUPP;
4806         }
4807
4808         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4809             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4810                 hns3_err(hw, "Unsupported flow control settings specified, "
4811                          "high_water(%u), low_water(%u), send_xon(%u) and "
4812                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4813                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4814                          pfc_conf->fc.send_xon,
4815                          pfc_conf->fc.mac_ctrl_frame_fwd);
4816                 return -EINVAL;
4817         }
4818         if (pfc_conf->fc.autoneg) {
4819                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4820                 return -EINVAL;
4821         }
4822         if (pfc_conf->fc.pause_time == 0) {
4823                 hns3_err(hw, "Invalid pause time %d setting.",
4824                          pfc_conf->fc.pause_time);
4825                 return -EINVAL;
4826         }
4827
4828         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4829             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4830                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4831                              "current_fc_status = %d", hw->current_fc_status);
4832                 return -EOPNOTSUPP;
4833         }
4834
4835         priority = pfc_conf->priority;
4836         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4837         if (hw->dcb_info.pfc_en & BIT(priority) &&
4838             hw->requested_mode == hw->current_mode &&
4839             pfc_conf->fc.pause_time == pf->pause_time)
4840                 return 0;
4841
4842         rte_spinlock_lock(&hw->lock);
4843         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4844         rte_spinlock_unlock(&hw->lock);
4845
4846         return ret;
4847 }
4848
4849 static int
4850 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4851 {
4852         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4853         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4854         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4855         int i;
4856
4857         rte_spinlock_lock(&hw->lock);
4858         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4859                 dcb_info->nb_tcs = pf->local_max_tc;
4860         else
4861                 dcb_info->nb_tcs = 1;
4862
4863         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4864                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4865         for (i = 0; i < dcb_info->nb_tcs; i++)
4866                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4867
4868         for (i = 0; i < hw->num_tc; i++) {
4869                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4870                 dcb_info->tc_queue.tc_txq[0][i].base =
4871                                                 hw->tc_queue[i].tqp_offset;
4872                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4873                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4874                                                 hw->tc_queue[i].tqp_count;
4875         }
4876         rte_spinlock_unlock(&hw->lock);
4877
4878         return 0;
4879 }
4880
4881 static int
4882 hns3_reinit_dev(struct hns3_adapter *hns)
4883 {
4884         struct hns3_hw *hw = &hns->hw;
4885         int ret;
4886
4887         ret = hns3_cmd_init(hw);
4888         if (ret) {
4889                 hns3_err(hw, "Failed to init cmd: %d", ret);
4890                 return ret;
4891         }
4892
4893         ret = hns3_reset_all_queues(hns);
4894         if (ret) {
4895                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4896                 return ret;
4897         }
4898
4899         ret = hns3_init_hardware(hns);
4900         if (ret) {
4901                 hns3_err(hw, "Failed to init hardware: %d", ret);
4902                 return ret;
4903         }
4904
4905         ret = hns3_enable_hw_error_intr(hns, true);
4906         if (ret) {
4907                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4908                              ret);
4909                 return ret;
4910         }
4911         hns3_info(hw, "Reset done, driver initialization finished.");
4912
4913         return 0;
4914 }
4915
4916 static bool
4917 is_pf_reset_done(struct hns3_hw *hw)
4918 {
4919         uint32_t val, reg, reg_bit;
4920
4921         switch (hw->reset.level) {
4922         case HNS3_IMP_RESET:
4923                 reg = HNS3_GLOBAL_RESET_REG;
4924                 reg_bit = HNS3_IMP_RESET_BIT;
4925                 break;
4926         case HNS3_GLOBAL_RESET:
4927                 reg = HNS3_GLOBAL_RESET_REG;
4928                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4929                 break;
4930         case HNS3_FUNC_RESET:
4931                 reg = HNS3_FUN_RST_ING;
4932                 reg_bit = HNS3_FUN_RST_ING_B;
4933                 break;
4934         case HNS3_FLR_RESET:
4935         default:
4936                 hns3_err(hw, "Wait for unsupported reset level: %d",
4937                          hw->reset.level);
4938                 return true;
4939         }
4940         val = hns3_read_dev(hw, reg);
4941         if (hns3_get_bit(val, reg_bit))
4942                 return false;
4943         else
4944                 return true;
4945 }
4946
4947 bool
4948 hns3_is_reset_pending(struct hns3_adapter *hns)
4949 {
4950         struct hns3_hw *hw = &hns->hw;
4951         enum hns3_reset_level reset;
4952
4953         hns3_check_event_cause(hns, NULL);
4954         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4955         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4956                 hns3_warn(hw, "High level reset %d is pending", reset);
4957                 return true;
4958         }
4959         reset = hns3_get_reset_level(hns, &hw->reset.request);
4960         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4961                 hns3_warn(hw, "High level reset %d is request", reset);
4962                 return true;
4963         }
4964         return false;
4965 }
4966
4967 static int
4968 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4969 {
4970         struct hns3_hw *hw = &hns->hw;
4971         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4972         struct timeval tv;
4973
4974         if (wait_data->result == HNS3_WAIT_SUCCESS)
4975                 return 0;
4976         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4977                 gettimeofday(&tv, NULL);
4978                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4979                           tv.tv_sec, tv.tv_usec);
4980                 return -ETIME;
4981         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4982                 return -EAGAIN;
4983
4984         wait_data->hns = hns;
4985         wait_data->check_completion = is_pf_reset_done;
4986         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4987                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4988         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4989         wait_data->count = HNS3_RESET_WAIT_CNT;
4990         wait_data->result = HNS3_WAIT_REQUEST;
4991         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4992         return -EAGAIN;
4993 }
4994
4995 static int
4996 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4997 {
4998         struct hns3_cmd_desc desc;
4999         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5000
5001         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5002         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5003         req->fun_reset_vfid = func_id;
5004
5005         return hns3_cmd_send(hw, &desc, 1);
5006 }
5007
5008 static int
5009 hns3_imp_reset_cmd(struct hns3_hw *hw)
5010 {
5011         struct hns3_cmd_desc desc;
5012
5013         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5014         desc.data[0] = 0xeedd;
5015
5016         return hns3_cmd_send(hw, &desc, 1);
5017 }
5018
5019 static void
5020 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5021 {
5022         struct hns3_hw *hw = &hns->hw;
5023         struct timeval tv;
5024         uint32_t val;
5025
5026         gettimeofday(&tv, NULL);
5027         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5028             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5029                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5030                           tv.tv_sec, tv.tv_usec);
5031                 return;
5032         }
5033
5034         switch (reset_level) {
5035         case HNS3_IMP_RESET:
5036                 hns3_imp_reset_cmd(hw);
5037                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5038                           tv.tv_sec, tv.tv_usec);
5039                 break;
5040         case HNS3_GLOBAL_RESET:
5041                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5042                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5043                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5044                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5045                           tv.tv_sec, tv.tv_usec);
5046                 break;
5047         case HNS3_FUNC_RESET:
5048                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5049                           tv.tv_sec, tv.tv_usec);
5050                 /* schedule again to check later */
5051                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5052                 hns3_schedule_reset(hns);
5053                 break;
5054         default:
5055                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5056                 return;
5057         }
5058         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5059 }
5060
5061 static enum hns3_reset_level
5062 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5063 {
5064         struct hns3_hw *hw = &hns->hw;
5065         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5066
5067         /* Return the highest priority reset level amongst all */
5068         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5069                 reset_level = HNS3_IMP_RESET;
5070         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5071                 reset_level = HNS3_GLOBAL_RESET;
5072         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5073                 reset_level = HNS3_FUNC_RESET;
5074         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5075                 reset_level = HNS3_FLR_RESET;
5076
5077         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5078                 return HNS3_NONE_RESET;
5079
5080         return reset_level;
5081 }
5082
5083 static int
5084 hns3_prepare_reset(struct hns3_adapter *hns)
5085 {
5086         struct hns3_hw *hw = &hns->hw;
5087         uint32_t reg_val;
5088         int ret;
5089
5090         switch (hw->reset.level) {
5091         case HNS3_FUNC_RESET:
5092                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5093                 if (ret)
5094                         return ret;
5095
5096                 /*
5097                  * After performaning pf reset, it is not necessary to do the
5098                  * mailbox handling or send any command to firmware, because
5099                  * any mailbox handling or command to firmware is only valid
5100                  * after hns3_cmd_init is called.
5101                  */
5102                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5103                 hw->reset.stats.request_cnt++;
5104                 break;
5105         case HNS3_IMP_RESET:
5106                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5107                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5108                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5109                 break;
5110         default:
5111                 break;
5112         }
5113         return 0;
5114 }
5115
5116 static int
5117 hns3_set_rst_done(struct hns3_hw *hw)
5118 {
5119         struct hns3_pf_rst_done_cmd *req;
5120         struct hns3_cmd_desc desc;
5121
5122         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5123         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5124         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5125         return hns3_cmd_send(hw, &desc, 1);
5126 }
5127
5128 static int
5129 hns3_stop_service(struct hns3_adapter *hns)
5130 {
5131         struct hns3_hw *hw = &hns->hw;
5132         struct rte_eth_dev *eth_dev;
5133
5134         eth_dev = &rte_eth_devices[hw->data->port_id];
5135         if (hw->adapter_state == HNS3_NIC_STARTED)
5136                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5137         hw->mac.link_status = ETH_LINK_DOWN;
5138
5139         hns3_set_rxtx_function(eth_dev);
5140         rte_wmb();
5141         /* Disable datapath on secondary process. */
5142         hns3_mp_req_stop_rxtx(eth_dev);
5143         rte_delay_ms(hw->tqps_num);
5144
5145         rte_spinlock_lock(&hw->lock);
5146         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5147             hw->adapter_state == HNS3_NIC_STOPPING) {
5148                 hns3_do_stop(hns);
5149                 hw->reset.mbuf_deferred_free = true;
5150         } else
5151                 hw->reset.mbuf_deferred_free = false;
5152
5153         /*
5154          * It is cumbersome for hardware to pick-and-choose entries for deletion
5155          * from table space. Hence, for function reset software intervention is
5156          * required to delete the entries
5157          */
5158         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5159                 hns3_configure_all_mc_mac_addr(hns, true);
5160         rte_spinlock_unlock(&hw->lock);
5161
5162         return 0;
5163 }
5164
5165 static int
5166 hns3_start_service(struct hns3_adapter *hns)
5167 {
5168         struct hns3_hw *hw = &hns->hw;
5169         struct rte_eth_dev *eth_dev;
5170
5171         if (hw->reset.level == HNS3_IMP_RESET ||
5172             hw->reset.level == HNS3_GLOBAL_RESET)
5173                 hns3_set_rst_done(hw);
5174         eth_dev = &rte_eth_devices[hw->data->port_id];
5175         hns3_set_rxtx_function(eth_dev);
5176         hns3_mp_req_start_rxtx(eth_dev);
5177         if (hw->adapter_state == HNS3_NIC_STARTED) {
5178                 hns3_service_handler(eth_dev);
5179
5180                 /* Enable interrupt of all rx queues before enabling queues */
5181                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5182                 /*
5183                  * When finished the initialization, enable queues to receive
5184                  * and transmit packets.
5185                  */
5186                 hns3_enable_all_queues(hw, true);
5187         }
5188
5189         return 0;
5190 }
5191
5192 static int
5193 hns3_restore_conf(struct hns3_adapter *hns)
5194 {
5195         struct hns3_hw *hw = &hns->hw;
5196         int ret;
5197
5198         ret = hns3_configure_all_mac_addr(hns, false);
5199         if (ret)
5200                 return ret;
5201
5202         ret = hns3_configure_all_mc_mac_addr(hns, false);
5203         if (ret)
5204                 goto err_mc_mac;
5205
5206         ret = hns3_dev_promisc_restore(hns);
5207         if (ret)
5208                 goto err_promisc;
5209
5210         ret = hns3_restore_vlan_table(hns);
5211         if (ret)
5212                 goto err_promisc;
5213
5214         ret = hns3_restore_vlan_conf(hns);
5215         if (ret)
5216                 goto err_promisc;
5217
5218         ret = hns3_restore_all_fdir_filter(hns);
5219         if (ret)
5220                 goto err_promisc;
5221
5222         ret = hns3_restore_rx_interrupt(hw);
5223         if (ret)
5224                 goto err_promisc;
5225
5226         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5227                 ret = hns3_do_start(hns, false);
5228                 if (ret)
5229                         goto err_promisc;
5230                 hns3_info(hw, "hns3 dev restart successful!");
5231         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5232                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5233         return 0;
5234
5235 err_promisc:
5236         hns3_configure_all_mc_mac_addr(hns, true);
5237 err_mc_mac:
5238         hns3_configure_all_mac_addr(hns, true);
5239         return ret;
5240 }
5241
5242 static void
5243 hns3_reset_service(void *param)
5244 {
5245         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5246         struct hns3_hw *hw = &hns->hw;
5247         enum hns3_reset_level reset_level;
5248         struct timeval tv_delta;
5249         struct timeval tv_start;
5250         struct timeval tv;
5251         uint64_t msec;
5252         int ret;
5253
5254         /*
5255          * The interrupt is not triggered within the delay time.
5256          * The interrupt may have been lost. It is necessary to handle
5257          * the interrupt to recover from the error.
5258          */
5259         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5260                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5261                 hns3_err(hw, "Handling interrupts in delayed tasks");
5262                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5263                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5264                 if (reset_level == HNS3_NONE_RESET) {
5265                         hns3_err(hw, "No reset level is set, try IMP reset");
5266                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5267                 }
5268         }
5269         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5270
5271         /*
5272          * Check if there is any ongoing reset in the hardware. This status can
5273          * be checked from reset_pending. If there is then, we need to wait for
5274          * hardware to complete reset.
5275          *    a. If we are able to figure out in reasonable time that hardware
5276          *       has fully resetted then, we can proceed with driver, client
5277          *       reset.
5278          *    b. else, we can come back later to check this status so re-sched
5279          *       now.
5280          */
5281         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5282         if (reset_level != HNS3_NONE_RESET) {
5283                 gettimeofday(&tv_start, NULL);
5284                 ret = hns3_reset_process(hns, reset_level);
5285                 gettimeofday(&tv, NULL);
5286                 timersub(&tv, &tv_start, &tv_delta);
5287                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5288                        tv_delta.tv_usec / USEC_PER_MSEC;
5289                 if (msec > HNS3_RESET_PROCESS_MS)
5290                         hns3_err(hw, "%d handle long time delta %" PRIx64
5291                                      " ms time=%ld.%.6ld",
5292                                  hw->reset.level, msec,
5293                                  tv.tv_sec, tv.tv_usec);
5294                 if (ret == -EAGAIN)
5295                         return;
5296         }
5297
5298         /* Check if we got any *new* reset requests to be honored */
5299         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5300         if (reset_level != HNS3_NONE_RESET)
5301                 hns3_msix_process(hns, reset_level);
5302 }
5303
5304 static const struct eth_dev_ops hns3_eth_dev_ops = {
5305         .dev_start          = hns3_dev_start,
5306         .dev_stop           = hns3_dev_stop,
5307         .dev_close          = hns3_dev_close,
5308         .promiscuous_enable = hns3_dev_promiscuous_enable,
5309         .promiscuous_disable = hns3_dev_promiscuous_disable,
5310         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5311         .allmulticast_disable = hns3_dev_allmulticast_disable,
5312         .mtu_set            = hns3_dev_mtu_set,
5313         .stats_get          = hns3_stats_get,
5314         .stats_reset        = hns3_stats_reset,
5315         .xstats_get         = hns3_dev_xstats_get,
5316         .xstats_get_names   = hns3_dev_xstats_get_names,
5317         .xstats_reset       = hns3_dev_xstats_reset,
5318         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5319         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5320         .dev_infos_get          = hns3_dev_infos_get,
5321         .fw_version_get         = hns3_fw_version_get,
5322         .rx_queue_setup         = hns3_rx_queue_setup,
5323         .tx_queue_setup         = hns3_tx_queue_setup,
5324         .rx_queue_release       = hns3_dev_rx_queue_release,
5325         .tx_queue_release       = hns3_dev_tx_queue_release,
5326         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5327         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5328         .dev_configure          = hns3_dev_configure,
5329         .flow_ctrl_get          = hns3_flow_ctrl_get,
5330         .flow_ctrl_set          = hns3_flow_ctrl_set,
5331         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5332         .mac_addr_add           = hns3_add_mac_addr,
5333         .mac_addr_remove        = hns3_remove_mac_addr,
5334         .mac_addr_set           = hns3_set_default_mac_addr,
5335         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5336         .link_update            = hns3_dev_link_update,
5337         .rss_hash_update        = hns3_dev_rss_hash_update,
5338         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5339         .reta_update            = hns3_dev_rss_reta_update,
5340         .reta_query             = hns3_dev_rss_reta_query,
5341         .filter_ctrl            = hns3_dev_filter_ctrl,
5342         .vlan_filter_set        = hns3_vlan_filter_set,
5343         .vlan_tpid_set          = hns3_vlan_tpid_set,
5344         .vlan_offload_set       = hns3_vlan_offload_set,
5345         .vlan_pvid_set          = hns3_vlan_pvid_set,
5346         .get_reg                = hns3_get_regs,
5347         .get_dcb_info           = hns3_get_dcb_info,
5348         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5349 };
5350
5351 static const struct hns3_reset_ops hns3_reset_ops = {
5352         .reset_service       = hns3_reset_service,
5353         .stop_service        = hns3_stop_service,
5354         .prepare_reset       = hns3_prepare_reset,
5355         .wait_hardware_ready = hns3_wait_hardware_ready,
5356         .reinit_dev          = hns3_reinit_dev,
5357         .restore_conf        = hns3_restore_conf,
5358         .start_service       = hns3_start_service,
5359 };
5360
5361 static int
5362 hns3_dev_init(struct rte_eth_dev *eth_dev)
5363 {
5364         struct rte_device *dev = eth_dev->device;
5365         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5366         struct hns3_adapter *hns = eth_dev->data->dev_private;
5367         struct hns3_hw *hw = &hns->hw;
5368         uint16_t device_id = pci_dev->id.device_id;
5369         uint8_t revision;
5370         int ret;
5371
5372         PMD_INIT_FUNC_TRACE();
5373
5374         /* Get PCI revision id */
5375         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
5376                                   HNS3_PCI_REVISION_ID);
5377         if (ret != HNS3_PCI_REVISION_ID_LEN) {
5378                 PMD_INIT_LOG(ERR, "Failed to read pci revision id, ret = %d",
5379                              ret);
5380                 return -EIO;
5381         }
5382         hw->revision = revision;
5383
5384         eth_dev->process_private = (struct hns3_process_private *)
5385             rte_zmalloc_socket("hns3_filter_list",
5386                                sizeof(struct hns3_process_private),
5387                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5388         if (eth_dev->process_private == NULL) {
5389                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5390                 return -ENOMEM;
5391         }
5392         /* initialize flow filter lists */
5393         hns3_filterlist_init(eth_dev);
5394
5395         hns3_set_rxtx_function(eth_dev);
5396         eth_dev->dev_ops = &hns3_eth_dev_ops;
5397         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5398                 hns3_mp_init_secondary();
5399                 hw->secondary_cnt++;
5400                 return 0;
5401         }
5402
5403         hns3_mp_init_primary();
5404         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5405
5406         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5407             device_id == HNS3_DEV_ID_50GE_RDMA ||
5408             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5409                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5410
5411         hns->is_vf = false;
5412         hw->data = eth_dev->data;
5413
5414         /*
5415          * Set default max packet size according to the mtu
5416          * default vale in DPDK frame.
5417          */
5418         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5419
5420         ret = hns3_reset_init(hw);
5421         if (ret)
5422                 goto err_init_reset;
5423         hw->reset.ops = &hns3_reset_ops;
5424
5425         ret = hns3_init_pf(eth_dev);
5426         if (ret) {
5427                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5428                 goto err_init_pf;
5429         }
5430
5431         /* Allocate memory for storing MAC addresses */
5432         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5433                                                sizeof(struct rte_ether_addr) *
5434                                                HNS3_UC_MACADDR_NUM, 0);
5435         if (eth_dev->data->mac_addrs == NULL) {
5436                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5437                              "to store MAC addresses",
5438                              sizeof(struct rte_ether_addr) *
5439                              HNS3_UC_MACADDR_NUM);
5440                 ret = -ENOMEM;
5441                 goto err_rte_zmalloc;
5442         }
5443
5444         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5445                             &eth_dev->data->mac_addrs[0]);
5446
5447         hw->adapter_state = HNS3_NIC_INITIALIZED;
5448         /*
5449          * Pass the information to the rte_eth_dev_close() that it should also
5450          * release the private port resources.
5451          */
5452         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5453
5454         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5455                 hns3_err(hw, "Reschedule reset service after dev_init");
5456                 hns3_schedule_reset(hns);
5457         } else {
5458                 /* IMP will wait ready flag before reset */
5459                 hns3_notify_reset_ready(hw, false);
5460         }
5461
5462         hns3_info(hw, "hns3 dev initialization successful!");
5463         return 0;
5464
5465 err_rte_zmalloc:
5466         hns3_uninit_pf(eth_dev);
5467
5468 err_init_pf:
5469         rte_free(hw->reset.wait_data);
5470 err_init_reset:
5471         eth_dev->dev_ops = NULL;
5472         eth_dev->rx_pkt_burst = NULL;
5473         eth_dev->tx_pkt_burst = NULL;
5474         eth_dev->tx_pkt_prepare = NULL;
5475         rte_free(eth_dev->process_private);
5476         eth_dev->process_private = NULL;
5477         return ret;
5478 }
5479
5480 static int
5481 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5482 {
5483         struct hns3_adapter *hns = eth_dev->data->dev_private;
5484         struct hns3_hw *hw = &hns->hw;
5485
5486         PMD_INIT_FUNC_TRACE();
5487
5488         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5489                 return -EPERM;
5490
5491         eth_dev->dev_ops = NULL;
5492         eth_dev->rx_pkt_burst = NULL;
5493         eth_dev->tx_pkt_burst = NULL;
5494         eth_dev->tx_pkt_prepare = NULL;
5495         if (hw->adapter_state < HNS3_NIC_CLOSING)
5496                 hns3_dev_close(eth_dev);
5497
5498         hw->adapter_state = HNS3_NIC_REMOVED;
5499         return 0;
5500 }
5501
5502 static int
5503 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5504                    struct rte_pci_device *pci_dev)
5505 {
5506         return rte_eth_dev_pci_generic_probe(pci_dev,
5507                                              sizeof(struct hns3_adapter),
5508                                              hns3_dev_init);
5509 }
5510
5511 static int
5512 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5513 {
5514         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5515 }
5516
5517 static const struct rte_pci_id pci_id_hns3_map[] = {
5518         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5519         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5520         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5521         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5522         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5523         { .vendor_id = 0, /* sentinel */ },
5524 };
5525
5526 static struct rte_pci_driver rte_hns3_pmd = {
5527         .id_table = pci_id_hns3_map,
5528         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5529         .probe = eth_hns3_pci_probe,
5530         .remove = eth_hns3_pci_remove,
5531 };
5532
5533 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5534 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5535 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5536
5537 RTE_INIT(hns3_init_log)
5538 {
5539         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5540         if (hns3_logtype_init >= 0)
5541                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5542         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5543         if (hns3_logtype_driver >= 0)
5544                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5545 }