1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
12 #include <rte_atomic.h>
13 #include <rte_bus_pci.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_interrupts.h>
26 #include "hns3_ethdev.h"
27 #include "hns3_logs.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_intr.h"
30 #include "hns3_regs.h"
34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
37 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
38 #define HNS3_INVLID_PVID 0xFFFF
40 #define HNS3_FILTER_TYPE_VF 0
41 #define HNS3_FILTER_TYPE_PORT 1
42 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
43 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
44 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
45 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
46 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
47 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
48 | HNS3_FILTER_FE_ROCE_EGRESS_B)
49 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
50 | HNS3_FILTER_FE_ROCE_INGRESS_B)
52 /* Reset related Registers */
53 #define HNS3_GLOBAL_RESET_BIT 0
54 #define HNS3_CORE_RESET_BIT 1
55 #define HNS3_IMP_RESET_BIT 2
56 #define HNS3_FUN_RST_ING_B 0
58 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
60 #define HNS3_RESET_WAIT_MS 100
61 #define HNS3_RESET_WAIT_CNT 200
64 HNS3_VECTOR0_EVENT_RST,
65 HNS3_VECTOR0_EVENT_MBX,
66 HNS3_VECTOR0_EVENT_ERR,
67 HNS3_VECTOR0_EVENT_OTHER,
70 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
72 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
73 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
75 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
77 static int hns3_add_mc_addr(struct hns3_hw *hw,
78 struct rte_ether_addr *mac_addr);
79 static int hns3_remove_mc_addr(struct hns3_hw *hw,
80 struct rte_ether_addr *mac_addr);
83 hns3_pf_disable_irq0(struct hns3_hw *hw)
85 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
89 hns3_pf_enable_irq0(struct hns3_hw *hw)
91 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
94 static enum hns3_evt_cause
95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
97 struct hns3_hw *hw = &hns->hw;
98 uint32_t vector0_int_stats;
99 uint32_t cmdq_src_val;
101 enum hns3_evt_cause ret;
103 /* fetch the events from their corresponding regs */
104 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
105 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
108 * Assumption: If by any chance reset and mailbox events are reported
109 * together then we will only process reset event and defer the
110 * processing of the mailbox events. Since, we would have not cleared
111 * RX CMDQ event this time we would receive again another interrupt
112 * from H/W just for the mailbox.
114 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
115 rte_atomic16_set(&hw->reset.disable_cmd, 1);
116 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
117 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
119 hw->reset.stats.imp_cnt++;
120 hns3_warn(hw, "IMP reset detected, clear reset status");
122 hns3_schedule_delayed_reset(hns);
123 hns3_warn(hw, "IMP reset detected, don't clear reset status");
126 ret = HNS3_VECTOR0_EVENT_RST;
131 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
132 rte_atomic16_set(&hw->reset.disable_cmd, 1);
133 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
134 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
136 hw->reset.stats.global_cnt++;
137 hns3_warn(hw, "Global reset detected, clear reset status");
139 hns3_schedule_delayed_reset(hns);
140 hns3_warn(hw, "Global reset detected, don't clear reset status");
143 ret = HNS3_VECTOR0_EVENT_RST;
147 /* check for vector0 msix event source */
148 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
149 val = vector0_int_stats;
150 ret = HNS3_VECTOR0_EVENT_ERR;
154 /* check for vector0 mailbox(=CMDQ RX) event source */
155 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
156 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
158 ret = HNS3_VECTOR0_EVENT_MBX;
162 if (clearval && (vector0_int_stats || cmdq_src_val))
163 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
164 vector0_int_stats, cmdq_src_val);
165 val = vector0_int_stats;
166 ret = HNS3_VECTOR0_EVENT_OTHER;
175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
177 if (event_type == HNS3_VECTOR0_EVENT_RST)
178 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
179 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
180 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
184 hns3_clear_all_event_cause(struct hns3_hw *hw)
186 uint32_t vector0_int_stats;
187 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
189 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
190 hns3_warn(hw, "Probe during IMP reset interrupt");
192 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
193 hns3_warn(hw, "Probe during Global reset interrupt");
195 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
196 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
197 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
198 BIT(HNS3_VECTOR0_CORERESET_INT_B));
199 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
203 hns3_interrupt_handler(void *param)
205 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
206 struct hns3_adapter *hns = dev->data->dev_private;
207 struct hns3_hw *hw = &hns->hw;
208 enum hns3_evt_cause event_cause;
209 uint32_t clearval = 0;
211 /* Disable interrupt */
212 hns3_pf_disable_irq0(hw);
214 event_cause = hns3_check_event_cause(hns, &clearval);
216 /* vector 0 interrupt is shared with reset and mailbox source events. */
217 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
218 hns3_handle_msix_error(hns, &hw->reset.request);
219 hns3_schedule_reset(hns);
220 } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
221 hns3_schedule_reset(hns);
222 else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
223 hns3_dev_handle_mbx_msg(hw);
225 hns3_err(hw, "Received unknown event");
227 hns3_clear_event_cause(hw, event_cause, clearval);
228 /* Enable interrupt if it is not cause by reset */
229 hns3_pf_enable_irq0(hw);
233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
235 #define HNS3_VLAN_ID_OFFSET_STEP 160
236 #define HNS3_VLAN_BYTE_SIZE 8
237 struct hns3_vlan_filter_pf_cfg_cmd *req;
238 struct hns3_hw *hw = &hns->hw;
239 uint8_t vlan_offset_byte_val;
240 struct hns3_cmd_desc desc;
241 uint8_t vlan_offset_byte;
242 uint8_t vlan_offset_base;
245 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
247 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
248 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
250 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
252 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
253 req->vlan_offset = vlan_offset_base;
254 req->vlan_cfg = on ? 0 : 1;
255 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
257 ret = hns3_cmd_send(hw, &desc, 1);
259 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
266 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
268 struct hns3_user_vlan_table *vlan_entry;
269 struct hns3_pf *pf = &hns->pf;
271 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
272 if (vlan_entry->vlan_id == vlan_id) {
273 if (vlan_entry->hd_tbl_status)
274 hns3_set_port_vlan_filter(hns, vlan_id, 0);
275 LIST_REMOVE(vlan_entry, next);
276 rte_free(vlan_entry);
283 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
286 struct hns3_user_vlan_table *vlan_entry;
287 struct hns3_hw *hw = &hns->hw;
288 struct hns3_pf *pf = &hns->pf;
290 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
291 if (vlan_entry->vlan_id == vlan_id)
295 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
296 if (vlan_entry == NULL) {
297 hns3_err(hw, "Failed to malloc hns3 vlan table");
301 vlan_entry->hd_tbl_status = writen_to_tbl;
302 vlan_entry->vlan_id = vlan_id;
304 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
308 hns3_restore_vlan_table(struct hns3_adapter *hns)
310 struct hns3_user_vlan_table *vlan_entry;
311 struct hns3_hw *hw = &hns->hw;
312 struct hns3_pf *pf = &hns->pf;
316 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
317 return hns3_vlan_pvid_configure(hns,
318 hw->port_base_vlan_cfg.pvid, 1);
320 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
321 if (vlan_entry->hd_tbl_status) {
322 vlan_id = vlan_entry->vlan_id;
323 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
333 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
335 struct hns3_hw *hw = &hns->hw;
336 bool writen_to_tbl = false;
340 * When vlan filter is enabled, hardware regards vlan id 0 as the entry
341 * for normal packet, deleting vlan id 0 is not allowed.
343 if (on == 0 && vlan_id == 0)
347 * When port base vlan enabled, we use port base vlan as the vlan
348 * filter condition. In this case, we don't update vlan filter table
349 * when user add new vlan or remove exist vlan, just update the
350 * vlan list. The vlan id in vlan list will be writen in vlan filter
351 * table until port base vlan disabled
353 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
354 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
355 writen_to_tbl = true;
358 if (ret == 0 && vlan_id) {
360 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
362 hns3_rm_dev_vlan_table(hns, vlan_id);
368 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
370 struct hns3_adapter *hns = dev->data->dev_private;
371 struct hns3_hw *hw = &hns->hw;
374 rte_spinlock_lock(&hw->lock);
375 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
376 rte_spinlock_unlock(&hw->lock);
381 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
384 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
385 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
386 struct hns3_hw *hw = &hns->hw;
387 struct hns3_cmd_desc desc;
390 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
391 vlan_type != ETH_VLAN_TYPE_OUTER)) {
392 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
396 if (tpid != RTE_ETHER_TYPE_VLAN) {
397 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
401 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
402 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
404 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
405 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
406 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
407 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
408 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
409 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
410 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
411 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
414 ret = hns3_cmd_send(hw, &desc, 1);
416 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
421 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
423 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
424 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
425 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
427 ret = hns3_cmd_send(hw, &desc, 1);
429 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
435 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
438 struct hns3_adapter *hns = dev->data->dev_private;
439 struct hns3_hw *hw = &hns->hw;
442 rte_spinlock_lock(&hw->lock);
443 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
444 rte_spinlock_unlock(&hw->lock);
449 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
450 struct hns3_rx_vtag_cfg *vcfg)
452 struct hns3_vport_vtag_rx_cfg_cmd *req;
453 struct hns3_hw *hw = &hns->hw;
454 struct hns3_cmd_desc desc;
459 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
461 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
462 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
463 vcfg->strip_tag1_en ? 1 : 0);
464 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
465 vcfg->strip_tag2_en ? 1 : 0);
466 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
467 vcfg->vlan1_vlan_prionly ? 1 : 0);
468 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
469 vcfg->vlan2_vlan_prionly ? 1 : 0);
472 * In current version VF is not supported when PF is driven by DPDK
473 * driver, just need to configure parameters for PF vport.
475 vport_id = HNS3_PF_FUNC_ID;
476 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
477 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
478 req->vf_bitmap[req->vf_offset] = bitmap;
480 ret = hns3_cmd_send(hw, &desc, 1);
482 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
487 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
488 struct hns3_rx_vtag_cfg *vcfg)
490 struct hns3_pf *pf = &hns->pf;
491 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
495 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
496 struct hns3_tx_vtag_cfg *vcfg)
498 struct hns3_pf *pf = &hns->pf;
499 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
503 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
505 struct hns3_rx_vtag_cfg rxvlan_cfg;
506 struct hns3_hw *hw = &hns->hw;
509 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
510 rxvlan_cfg.strip_tag1_en = false;
511 rxvlan_cfg.strip_tag2_en = enable;
513 rxvlan_cfg.strip_tag1_en = enable;
514 rxvlan_cfg.strip_tag2_en = true;
517 rxvlan_cfg.vlan1_vlan_prionly = false;
518 rxvlan_cfg.vlan2_vlan_prionly = false;
519 rxvlan_cfg.rx_vlan_offload_en = enable;
521 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
523 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
527 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
533 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
534 uint8_t fe_type, bool filter_en, uint8_t vf_id)
536 struct hns3_vlan_filter_ctrl_cmd *req;
537 struct hns3_cmd_desc desc;
540 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
542 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
543 req->vlan_type = vlan_type;
544 req->vlan_fe = filter_en ? fe_type : 0;
547 ret = hns3_cmd_send(hw, &desc, 1);
549 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
555 hns3_vlan_filter_init(struct hns3_adapter *hns)
557 struct hns3_hw *hw = &hns->hw;
560 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
561 HNS3_FILTER_FE_EGRESS, false,
564 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
568 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
569 HNS3_FILTER_FE_INGRESS, false,
572 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
578 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
580 struct hns3_hw *hw = &hns->hw;
583 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
584 HNS3_FILTER_FE_INGRESS, enable,
587 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
588 enable ? "enable" : "disable", ret);
594 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
596 struct hns3_adapter *hns = dev->data->dev_private;
597 struct hns3_hw *hw = &hns->hw;
598 struct rte_eth_rxmode *rxmode;
599 unsigned int tmp_mask;
603 rte_spinlock_lock(&hw->lock);
604 rxmode = &dev->data->dev_conf.rxmode;
605 tmp_mask = (unsigned int)mask;
606 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
607 /* ignore vlan filter configuration during promiscuous mode */
608 if (!dev->data->promiscuous) {
609 /* Enable or disable VLAN filter */
610 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
613 ret = hns3_enable_vlan_filter(hns, enable);
615 rte_spinlock_unlock(&hw->lock);
616 hns3_err(hw, "failed to %s rx filter, ret = %d",
617 enable ? "enable" : "disable", ret);
623 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
624 /* Enable or disable VLAN stripping */
625 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
628 ret = hns3_en_hw_strip_rxvtag(hns, enable);
630 rte_spinlock_unlock(&hw->lock);
631 hns3_err(hw, "failed to %s rx strip, ret = %d",
632 enable ? "enable" : "disable", ret);
637 rte_spinlock_unlock(&hw->lock);
643 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
644 struct hns3_tx_vtag_cfg *vcfg)
646 struct hns3_vport_vtag_tx_cfg_cmd *req;
647 struct hns3_cmd_desc desc;
648 struct hns3_hw *hw = &hns->hw;
653 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
655 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
656 req->def_vlan_tag1 = vcfg->default_tag1;
657 req->def_vlan_tag2 = vcfg->default_tag2;
658 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
659 vcfg->accept_tag1 ? 1 : 0);
660 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
661 vcfg->accept_untag1 ? 1 : 0);
662 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
663 vcfg->accept_tag2 ? 1 : 0);
664 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
665 vcfg->accept_untag2 ? 1 : 0);
666 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
667 vcfg->insert_tag1_en ? 1 : 0);
668 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
669 vcfg->insert_tag2_en ? 1 : 0);
670 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
673 * In current version VF is not supported when PF is driven by DPDK
674 * driver, just need to configure parameters for PF vport.
676 vport_id = HNS3_PF_FUNC_ID;
677 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
678 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
679 req->vf_bitmap[req->vf_offset] = bitmap;
681 ret = hns3_cmd_send(hw, &desc, 1);
683 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
689 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
692 struct hns3_hw *hw = &hns->hw;
693 struct hns3_tx_vtag_cfg txvlan_cfg;
696 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
697 txvlan_cfg.accept_tag1 = true;
698 txvlan_cfg.insert_tag1_en = false;
699 txvlan_cfg.default_tag1 = 0;
701 txvlan_cfg.accept_tag1 = false;
702 txvlan_cfg.insert_tag1_en = true;
703 txvlan_cfg.default_tag1 = pvid;
706 txvlan_cfg.accept_untag1 = true;
707 txvlan_cfg.accept_tag2 = true;
708 txvlan_cfg.accept_untag2 = true;
709 txvlan_cfg.insert_tag2_en = false;
710 txvlan_cfg.default_tag2 = 0;
712 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
714 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
719 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
724 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
726 struct hns3_hw *hw = &hns->hw;
728 hw->port_base_vlan_cfg.state = on ?
729 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
731 hw->port_base_vlan_cfg.pvid = pvid;
735 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
737 struct hns3_user_vlan_table *vlan_entry;
738 struct hns3_pf *pf = &hns->pf;
740 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
741 if (vlan_entry->hd_tbl_status)
742 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
744 vlan_entry->hd_tbl_status = false;
748 vlan_entry = LIST_FIRST(&pf->vlan_list);
750 LIST_REMOVE(vlan_entry, next);
751 rte_free(vlan_entry);
752 vlan_entry = LIST_FIRST(&pf->vlan_list);
758 hns3_add_all_vlan_table(struct hns3_adapter *hns)
760 struct hns3_user_vlan_table *vlan_entry;
761 struct hns3_pf *pf = &hns->pf;
763 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
764 if (!vlan_entry->hd_tbl_status)
765 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
767 vlan_entry->hd_tbl_status = true;
772 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
774 struct hns3_hw *hw = &hns->hw;
777 hns3_rm_all_vlan_table(hns, true);
778 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
779 ret = hns3_set_port_vlan_filter(hns,
780 hw->port_base_vlan_cfg.pvid, 0);
782 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
790 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
791 uint16_t port_base_vlan_state,
792 uint16_t new_pvid, uint16_t old_pvid)
794 struct hns3_hw *hw = &hns->hw;
797 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
798 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
799 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
802 "Failed to clear clear old pvid filter, ret =%d",
808 hns3_rm_all_vlan_table(hns, false);
809 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
813 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
815 hns3_err(hw, "Failed to set port vlan filter, ret =%d",
821 if (new_pvid == hw->port_base_vlan_cfg.pvid)
822 hns3_add_all_vlan_table(hns);
828 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
830 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
831 struct hns3_rx_vtag_cfg rx_vlan_cfg;
835 rx_strip_en = old_cfg->rx_vlan_offload_en ? true : false;
837 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
838 rx_vlan_cfg.strip_tag2_en = true;
840 rx_vlan_cfg.strip_tag1_en = false;
841 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
843 rx_vlan_cfg.vlan1_vlan_prionly = false;
844 rx_vlan_cfg.vlan2_vlan_prionly = false;
845 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
847 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
851 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
856 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
858 struct hns3_hw *hw = &hns->hw;
859 uint16_t port_base_vlan_state;
863 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
864 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
865 hns3_warn(hw, "Invalid operation! As current pvid set "
866 "is %u, disable pvid %u is invalid",
867 hw->port_base_vlan_cfg.pvid, pvid);
871 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
872 HNS3_PORT_BASE_VLAN_DISABLE;
873 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
875 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
880 ret = hns3_en_pvid_strip(hns, on);
882 hns3_err(hw, "failed to config rx vlan strip for pvid, "
887 if (pvid == HNS3_INVLID_PVID)
889 old_pvid = hw->port_base_vlan_cfg.pvid;
890 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
893 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
899 hns3_store_port_base_vlan_info(hns, pvid, on);
904 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
906 struct hns3_adapter *hns = dev->data->dev_private;
907 struct hns3_hw *hw = &hns->hw;
910 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
911 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
912 RTE_ETHER_MAX_VLAN_ID);
916 rte_spinlock_lock(&hw->lock);
917 ret = hns3_vlan_pvid_configure(hns, pvid, on);
918 rte_spinlock_unlock(&hw->lock);
923 init_port_base_vlan_info(struct hns3_hw *hw)
925 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
926 hw->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
930 hns3_default_vlan_config(struct hns3_adapter *hns)
932 struct hns3_hw *hw = &hns->hw;
935 ret = hns3_set_port_vlan_filter(hns, 0, 1);
937 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
942 hns3_init_vlan_config(struct hns3_adapter *hns)
944 struct hns3_hw *hw = &hns->hw;
948 * This function can be called in the initialization and reset process,
949 * when in reset process, it means that hardware had been reseted
950 * successfully and we need to restore the hardware configuration to
951 * ensure that the hardware configuration remains unchanged before and
954 if (rte_atomic16_read(&hw->reset.resetting) == 0)
955 init_port_base_vlan_info(hw);
957 ret = hns3_vlan_filter_init(hns);
959 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
963 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
964 RTE_ETHER_TYPE_VLAN);
966 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
971 * When in the reinit dev stage of the reset process, the following
972 * vlan-related configurations may differ from those at initialization,
973 * we will restore configurations to hardware in hns3_restore_vlan_table
974 * and hns3_restore_vlan_conf later.
976 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
977 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
979 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
983 ret = hns3_en_hw_strip_rxvtag(hns, false);
985 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
991 return hns3_default_vlan_config(hns);
995 hns3_restore_vlan_conf(struct hns3_adapter *hns)
997 struct hns3_pf *pf = &hns->pf;
998 struct hns3_hw *hw = &hns->hw;
1003 if (!hw->data->promiscuous) {
1004 /* restore vlan filter states */
1005 offloads = hw->data->dev_conf.rxmode.offloads;
1006 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1007 ret = hns3_enable_vlan_filter(hns, enable);
1009 hns3_err(hw, "failed to restore vlan rx filter conf, "
1015 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1017 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1021 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1023 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1029 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1031 struct hns3_adapter *hns = dev->data->dev_private;
1032 struct rte_eth_dev_data *data = dev->data;
1033 struct rte_eth_txmode *txmode;
1034 struct hns3_hw *hw = &hns->hw;
1038 txmode = &data->dev_conf.txmode;
1039 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1041 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1042 "configuration is not supported! Ignore these two "
1043 "parameters: hw_vlan_reject_tagged(%d), "
1044 "hw_vlan_reject_untagged(%d)",
1045 txmode->hw_vlan_reject_tagged,
1046 txmode->hw_vlan_reject_untagged);
1048 /* Apply vlan offload setting */
1049 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1050 ret = hns3_vlan_offload_set(dev, mask);
1052 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1058 * If pvid config is not set in rte_eth_conf, driver needn't to set
1059 * VLAN pvid related configuration to hardware.
1061 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1064 /* Apply pvid setting */
1065 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1066 txmode->hw_vlan_insert_pvid);
1068 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1075 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1076 unsigned int tso_mss_max)
1078 struct hns3_cfg_tso_status_cmd *req;
1079 struct hns3_cmd_desc desc;
1082 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1084 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1087 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1089 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1092 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1094 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1096 return hns3_cmd_send(hw, &desc, 1);
1100 hns3_config_gro(struct hns3_hw *hw, bool en)
1102 struct hns3_cfg_gro_status_cmd *req;
1103 struct hns3_cmd_desc desc;
1106 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1107 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1109 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1111 ret = hns3_cmd_send(hw, &desc, 1);
1113 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1119 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1120 uint16_t *allocated_size, bool is_alloc)
1122 struct hns3_umv_spc_alc_cmd *req;
1123 struct hns3_cmd_desc desc;
1126 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1127 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1128 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1129 req->space_size = rte_cpu_to_le_32(space_size);
1131 ret = hns3_cmd_send(hw, &desc, 1);
1133 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1134 is_alloc ? "allocate" : "free", ret);
1138 if (is_alloc && allocated_size)
1139 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1145 hns3_init_umv_space(struct hns3_hw *hw)
1147 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1148 struct hns3_pf *pf = &hns->pf;
1149 uint16_t allocated_size = 0;
1152 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1157 if (allocated_size < pf->wanted_umv_size)
1158 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1159 pf->wanted_umv_size, allocated_size);
1161 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1162 pf->wanted_umv_size;
1163 pf->used_umv_size = 0;
1168 hns3_uninit_umv_space(struct hns3_hw *hw)
1170 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1171 struct hns3_pf *pf = &hns->pf;
1174 if (pf->max_umv_size == 0)
1177 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1181 pf->max_umv_size = 0;
1187 hns3_is_umv_space_full(struct hns3_hw *hw)
1189 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1190 struct hns3_pf *pf = &hns->pf;
1193 is_full = (pf->used_umv_size >= pf->max_umv_size);
1199 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1201 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1202 struct hns3_pf *pf = &hns->pf;
1205 if (pf->used_umv_size > 0)
1206 pf->used_umv_size--;
1208 pf->used_umv_size++;
1212 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1213 const uint8_t *addr, bool is_mc)
1215 const unsigned char *mac_addr = addr;
1216 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1217 ((uint32_t)mac_addr[2] << 16) |
1218 ((uint32_t)mac_addr[1] << 8) |
1219 (uint32_t)mac_addr[0];
1220 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1222 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1224 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1225 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1226 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1229 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1230 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1234 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1236 enum hns3_mac_vlan_tbl_opcode op)
1239 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1244 if (op == HNS3_MAC_VLAN_ADD) {
1245 if (resp_code == 0 || resp_code == 1) {
1247 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1248 hns3_err(hw, "add mac addr failed for uc_overflow");
1250 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1251 hns3_err(hw, "add mac addr failed for mc_overflow");
1255 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1258 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1259 if (resp_code == 0) {
1261 } else if (resp_code == 1) {
1262 hns3_dbg(hw, "remove mac addr failed for miss");
1266 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1269 } else if (op == HNS3_MAC_VLAN_LKUP) {
1270 if (resp_code == 0) {
1272 } else if (resp_code == 1) {
1273 hns3_dbg(hw, "lookup mac addr failed for miss");
1277 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1282 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1289 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1290 struct hns3_mac_vlan_tbl_entry_cmd *req,
1291 struct hns3_cmd_desc *desc, bool is_mc)
1297 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1299 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1300 memcpy(desc[0].data, req,
1301 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1302 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1304 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1305 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1307 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1309 memcpy(desc[0].data, req,
1310 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1311 ret = hns3_cmd_send(hw, desc, 1);
1314 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1318 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1319 retval = rte_le_to_cpu_16(desc[0].retval);
1321 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1322 HNS3_MAC_VLAN_LKUP);
1326 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1327 struct hns3_mac_vlan_tbl_entry_cmd *req,
1328 struct hns3_cmd_desc *mc_desc)
1335 if (mc_desc == NULL) {
1336 struct hns3_cmd_desc desc;
1338 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1339 memcpy(desc.data, req,
1340 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1341 ret = hns3_cmd_send(hw, &desc, 1);
1342 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1343 retval = rte_le_to_cpu_16(desc.retval);
1345 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1348 hns3_cmd_reuse_desc(&mc_desc[0], false);
1349 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1350 hns3_cmd_reuse_desc(&mc_desc[1], false);
1351 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1352 hns3_cmd_reuse_desc(&mc_desc[2], false);
1353 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1354 memcpy(mc_desc[0].data, req,
1355 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1356 mc_desc[0].retval = 0;
1357 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1358 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1359 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1361 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1366 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1374 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1375 struct hns3_mac_vlan_tbl_entry_cmd *req)
1377 struct hns3_cmd_desc desc;
1382 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1384 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1386 ret = hns3_cmd_send(hw, &desc, 1);
1388 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1391 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1392 retval = rte_le_to_cpu_16(desc.retval);
1394 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1395 HNS3_MAC_VLAN_REMOVE);
1399 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1401 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1402 struct hns3_mac_vlan_tbl_entry_cmd req;
1403 struct hns3_pf *pf = &hns->pf;
1404 struct hns3_cmd_desc desc;
1405 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1406 uint16_t egress_port = 0;
1410 /* check if mac addr is valid */
1411 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1412 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1414 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1419 memset(&req, 0, sizeof(req));
1422 * In current version VF is not supported when PF is driven by DPDK
1423 * driver, just need to configure parameters for PF vport.
1425 vf_id = HNS3_PF_FUNC_ID;
1426 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1427 HNS3_MAC_EPORT_VFID_S, vf_id);
1429 req.egress_port = rte_cpu_to_le_16(egress_port);
1431 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1434 * Lookup the mac address in the mac_vlan table, and add
1435 * it if the entry is inexistent. Repeated unicast entry
1436 * is not allowed in the mac vlan table.
1438 ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1439 if (ret == -ENOENT) {
1440 if (!hns3_is_umv_space_full(hw)) {
1441 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1443 hns3_update_umv_space(hw, false);
1447 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1452 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1454 /* check if we just hit the duplicate */
1456 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1460 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1467 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1469 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1470 struct rte_ether_addr *addr;
1474 for (i = 0; i < hw->mc_addrs_num; i++) {
1475 addr = &hw->mc_addrs[i];
1476 /* Check if there are duplicate addresses */
1477 if (rte_is_same_ether_addr(addr, mac_addr)) {
1478 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1480 hns3_err(hw, "failed to add mc mac addr, same addrs"
1481 "(%s) is added by the set_mc_mac_addr_list "
1487 ret = hns3_add_mc_addr(hw, mac_addr);
1489 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1491 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1498 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1500 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1503 ret = hns3_remove_mc_addr(hw, mac_addr);
1505 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1507 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1514 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1515 uint32_t idx, __rte_unused uint32_t pool)
1517 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1521 rte_spinlock_lock(&hw->lock);
1524 * In hns3 network engine adding UC and MC mac address with different
1525 * commands with firmware. We need to determine whether the input
1526 * address is a UC or a MC address to call different commands.
1527 * By the way, it is recommended calling the API function named
1528 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1529 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1530 * may affect the specifications of UC mac addresses.
1532 if (rte_is_multicast_ether_addr(mac_addr))
1533 ret = hns3_add_mc_addr_common(hw, mac_addr);
1535 ret = hns3_add_uc_addr_common(hw, mac_addr);
1538 rte_spinlock_unlock(&hw->lock);
1539 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1541 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1547 hw->mac.default_addr_setted = true;
1548 rte_spinlock_unlock(&hw->lock);
1554 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1556 struct hns3_mac_vlan_tbl_entry_cmd req;
1557 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1560 /* check if mac addr is valid */
1561 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1562 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1564 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1569 memset(&req, 0, sizeof(req));
1570 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1571 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1572 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1573 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1576 hns3_update_umv_space(hw, true);
1582 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1584 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585 /* index will be checked by upper level rte interface */
1586 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1587 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1590 rte_spinlock_lock(&hw->lock);
1592 if (rte_is_multicast_ether_addr(mac_addr))
1593 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1595 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1596 rte_spinlock_unlock(&hw->lock);
1598 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1600 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1606 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1607 struct rte_ether_addr *mac_addr)
1609 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1610 struct rte_ether_addr *oaddr;
1611 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1612 bool default_addr_setted;
1613 bool rm_succes = false;
1617 * It has been guaranteed that input parameter named mac_addr is valid
1618 * address in the rte layer of DPDK framework.
1620 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1621 default_addr_setted = hw->mac.default_addr_setted;
1622 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1625 rte_spinlock_lock(&hw->lock);
1626 if (default_addr_setted) {
1627 ret = hns3_remove_uc_addr_common(hw, oaddr);
1629 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1631 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1638 ret = hns3_add_uc_addr_common(hw, mac_addr);
1640 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1642 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1643 goto err_add_uc_addr;
1646 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1648 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1649 goto err_pause_addr_cfg;
1652 rte_ether_addr_copy(mac_addr,
1653 (struct rte_ether_addr *)hw->mac.mac_addr);
1654 hw->mac.default_addr_setted = true;
1655 rte_spinlock_unlock(&hw->lock);
1660 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1662 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1665 "Failed to roll back to del setted mac addr(%s): %d",
1671 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1673 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1676 "Failed to restore old uc mac addr(%s): %d",
1678 hw->mac.default_addr_setted = false;
1681 rte_spinlock_unlock(&hw->lock);
1687 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1689 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1690 struct hns3_hw *hw = &hns->hw;
1691 struct rte_ether_addr *addr;
1696 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1697 addr = &hw->data->mac_addrs[i];
1698 if (rte_is_zero_ether_addr(addr))
1700 if (rte_is_multicast_ether_addr(addr))
1701 ret = del ? hns3_remove_mc_addr(hw, addr) :
1702 hns3_add_mc_addr(hw, addr);
1704 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1705 hns3_add_uc_addr_common(hw, addr);
1709 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1711 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1712 "ret = %d.", del ? "remove" : "restore",
1720 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1722 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1726 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1727 word_num = vfid / 32;
1728 bit_num = vfid % 32;
1730 desc[1].data[word_num] &=
1731 rte_cpu_to_le_32(~(1UL << bit_num));
1733 desc[1].data[word_num] |=
1734 rte_cpu_to_le_32(1UL << bit_num);
1736 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1737 bit_num = vfid % 32;
1739 desc[2].data[word_num] &=
1740 rte_cpu_to_le_32(~(1UL << bit_num));
1742 desc[2].data[word_num] |=
1743 rte_cpu_to_le_32(1UL << bit_num);
1748 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1750 struct hns3_mac_vlan_tbl_entry_cmd req;
1751 struct hns3_cmd_desc desc[3];
1752 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1756 /* Check if mac addr is valid */
1757 if (!rte_is_multicast_ether_addr(mac_addr)) {
1758 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1760 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1765 memset(&req, 0, sizeof(req));
1766 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1767 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1768 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1770 /* This mac addr do not exist, add new entry for it */
1771 memset(desc[0].data, 0, sizeof(desc[0].data));
1772 memset(desc[1].data, 0, sizeof(desc[0].data));
1773 memset(desc[2].data, 0, sizeof(desc[0].data));
1777 * In current version VF is not supported when PF is driven by DPDK
1778 * driver, just need to configure parameters for PF vport.
1780 vf_id = HNS3_PF_FUNC_ID;
1781 hns3_update_desc_vfid(desc, vf_id, false);
1782 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1785 hns3_err(hw, "mc mac vlan table is full");
1786 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1788 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1795 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1797 struct hns3_mac_vlan_tbl_entry_cmd req;
1798 struct hns3_cmd_desc desc[3];
1799 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1803 /* Check if mac addr is valid */
1804 if (!rte_is_multicast_ether_addr(mac_addr)) {
1805 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1807 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1812 memset(&req, 0, sizeof(req));
1813 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1814 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1815 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1818 * This mac addr exist, remove this handle's VFID for it.
1819 * In current version VF is not supported when PF is driven by
1820 * DPDK driver, just need to configure parameters for PF vport.
1822 vf_id = HNS3_PF_FUNC_ID;
1823 hns3_update_desc_vfid(desc, vf_id, true);
1825 /* All the vfid is zero, so need to delete this entry */
1826 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1827 } else if (ret == -ENOENT) {
1828 /* This mac addr doesn't exist. */
1833 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1835 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1842 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1843 struct rte_ether_addr *mc_addr_set,
1844 uint32_t nb_mc_addr)
1846 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1847 struct rte_ether_addr *addr;
1851 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1852 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1853 "invalid. valid range: 0~%d",
1854 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1858 /* Check if input mac addresses are valid */
1859 for (i = 0; i < nb_mc_addr; i++) {
1860 addr = &mc_addr_set[i];
1861 if (!rte_is_multicast_ether_addr(addr)) {
1862 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1865 "failed to set mc mac addr, addr(%s) invalid.",
1870 /* Check if there are duplicate addresses */
1871 for (j = i + 1; j < nb_mc_addr; j++) {
1872 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1873 rte_ether_format_addr(mac_str,
1874 RTE_ETHER_ADDR_FMT_SIZE,
1876 hns3_err(hw, "failed to set mc mac addr, "
1877 "addrs invalid. two same addrs(%s).",
1884 * Check if there are duplicate addresses between mac_addrs
1887 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1888 if (rte_is_same_ether_addr(addr,
1889 &hw->data->mac_addrs[j])) {
1890 rte_ether_format_addr(mac_str,
1891 RTE_ETHER_ADDR_FMT_SIZE,
1893 hns3_err(hw, "failed to set mc mac addr, "
1894 "addrs invalid. addrs(%s) has already "
1895 "configured in mac_addr add API",
1906 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1907 struct rte_ether_addr *mc_addr_set,
1909 struct rte_ether_addr *reserved_addr_list,
1910 int *reserved_addr_num,
1911 struct rte_ether_addr *add_addr_list,
1913 struct rte_ether_addr *rm_addr_list,
1916 struct rte_ether_addr *addr;
1917 int current_addr_num;
1918 int reserved_num = 0;
1926 /* Calculate the mc mac address list that should be removed */
1927 current_addr_num = hw->mc_addrs_num;
1928 for (i = 0; i < current_addr_num; i++) {
1929 addr = &hw->mc_addrs[i];
1931 for (j = 0; j < mc_addr_num; j++) {
1932 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1939 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1942 rte_ether_addr_copy(addr,
1943 &reserved_addr_list[reserved_num]);
1948 /* Calculate the mc mac address list that should be added */
1949 for (i = 0; i < mc_addr_num; i++) {
1950 addr = &mc_addr_set[i];
1952 for (j = 0; j < current_addr_num; j++) {
1953 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1960 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1965 /* Reorder the mc mac address list maintained by driver */
1966 for (i = 0; i < reserved_num; i++)
1967 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1969 for (i = 0; i < rm_num; i++) {
1970 num = reserved_num + i;
1971 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1974 *reserved_addr_num = reserved_num;
1975 *add_addr_num = add_num;
1976 *rm_addr_num = rm_num;
1980 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1981 struct rte_ether_addr *mc_addr_set,
1982 uint32_t nb_mc_addr)
1984 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1986 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1987 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1988 struct rte_ether_addr *addr;
1989 int reserved_addr_num;
1997 /* Check if input parameters are valid */
1998 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2002 rte_spinlock_lock(&hw->lock);
2005 * Calculate the mc mac address lists those should be removed and be
2006 * added, Reorder the mc mac address list maintained by driver.
2008 mc_addr_num = (int)nb_mc_addr;
2009 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2010 reserved_addr_list, &reserved_addr_num,
2011 add_addr_list, &add_addr_num,
2012 rm_addr_list, &rm_addr_num);
2014 /* Remove mc mac addresses */
2015 for (i = 0; i < rm_addr_num; i++) {
2016 num = rm_addr_num - i - 1;
2017 addr = &rm_addr_list[num];
2018 ret = hns3_remove_mc_addr(hw, addr);
2020 rte_spinlock_unlock(&hw->lock);
2026 /* Add mc mac addresses */
2027 for (i = 0; i < add_addr_num; i++) {
2028 addr = &add_addr_list[i];
2029 ret = hns3_add_mc_addr(hw, addr);
2031 rte_spinlock_unlock(&hw->lock);
2035 num = reserved_addr_num + i;
2036 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2039 rte_spinlock_unlock(&hw->lock);
2045 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2047 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2048 struct hns3_hw *hw = &hns->hw;
2049 struct rte_ether_addr *addr;
2054 for (i = 0; i < hw->mc_addrs_num; i++) {
2055 addr = &hw->mc_addrs[i];
2056 if (!rte_is_multicast_ether_addr(addr))
2059 ret = hns3_remove_mc_addr(hw, addr);
2061 ret = hns3_add_mc_addr(hw, addr);
2064 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2066 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2067 del ? "Remove" : "Restore", mac_str, ret);
2074 hns3_check_mq_mode(struct rte_eth_dev *dev)
2076 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2077 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2078 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2080 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2081 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2086 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2087 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2089 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2090 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2091 "rx_mq_mode = %d", rx_mq_mode);
2095 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2096 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2097 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2098 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2099 rx_mq_mode, tx_mq_mode);
2103 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2104 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2105 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2106 dcb_rx_conf->nb_tcs, pf->tc_max);
2110 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2111 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2112 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2113 "nb_tcs(%d) != %d or %d in rx direction.",
2114 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2118 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2119 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2120 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2124 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2125 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2126 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2127 "is not equal to one in tx direction.",
2128 i, dcb_rx_conf->dcb_tc[i]);
2131 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2132 max_tc = dcb_rx_conf->dcb_tc[i];
2135 num_tc = max_tc + 1;
2136 if (num_tc > dcb_rx_conf->nb_tcs) {
2137 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2138 num_tc, dcb_rx_conf->nb_tcs);
2147 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2149 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2151 if (!hns3_dev_dcb_supported(hw)) {
2152 hns3_err(hw, "this port does not support dcb configurations.");
2156 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2157 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2161 /* Check multiple queue mode */
2162 return hns3_check_mq_mode(dev);
2166 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2167 enum hns3_ring_type queue_type, uint16_t queue_id)
2169 struct hns3_cmd_desc desc;
2170 struct hns3_ctrl_vector_chain_cmd *req =
2171 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2172 enum hns3_cmd_status status;
2173 enum hns3_opcode_type op;
2174 uint16_t tqp_type_and_id = 0;
2179 op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2180 hns3_cmd_setup_basic_desc(&desc, op, false);
2181 req->int_vector_id = vector_id;
2183 if (queue_type == HNS3_RING_TYPE_RX)
2184 gl = HNS3_RING_GL_RX;
2186 gl = HNS3_RING_GL_TX;
2190 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2192 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2193 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2195 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2196 req->int_cause_num = 1;
2197 op_str = mmap ? "Map" : "Unmap";
2198 status = hns3_cmd_send(hw, &desc, 1);
2200 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2201 op_str, queue_id, req->int_vector_id, status);
2209 hns3_init_ring_with_vector(struct hns3_hw *hw)
2216 * In hns3 network engine, vector 0 is always the misc interrupt of this
2217 * function, vector 1~N can be used respectively for the queues of the
2218 * function. Tx and Rx queues with the same number share the interrupt
2219 * vector. In the initialization clearing the all hardware mapping
2220 * relationship configurations between queues and interrupt vectors is
2221 * needed, so some error caused by the residual configurations, such as
2222 * the unexpected Tx interrupt, can be avoid. Because of the hardware
2223 * constraints in hns3 hardware engine, we have to implement clearing
2224 * the mapping relationship configurations by binding all queues to the
2225 * last interrupt vector and reserving the last interrupt vector. This
2226 * method results in a decrease of the maximum queues when upper
2227 * applications call the rte_eth_dev_configure API function to enable
2230 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2231 /* vec - 1: the last interrupt is reserved */
2232 hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;
2233 for (i = 0; i < hw->intr_tqps_num; i++) {
2235 * Set gap limiter and rate limiter configuration of queue's
2238 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2239 HNS3_TQP_INTR_GL_DEFAULT);
2240 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2241 HNS3_TQP_INTR_GL_DEFAULT);
2242 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2244 ret = hns3_bind_ring_with_vector(hw, vec, false,
2245 HNS3_RING_TYPE_TX, i);
2247 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2248 "vector: %d, ret=%d", i, vec, ret);
2252 ret = hns3_bind_ring_with_vector(hw, vec, false,
2253 HNS3_RING_TYPE_RX, i);
2255 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2256 "vector: %d, ret=%d", i, vec, ret);
2265 hns3_dev_configure(struct rte_eth_dev *dev)
2267 struct hns3_adapter *hns = dev->data->dev_private;
2268 struct rte_eth_conf *conf = &dev->data->dev_conf;
2269 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2270 struct hns3_hw *hw = &hns->hw;
2271 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2272 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2273 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2274 struct rte_eth_rss_conf rss_conf;
2279 * Hardware does not support individually enable/disable/reset the Tx or
2280 * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2281 * and Rx queues at the same time. When the numbers of Tx queues
2282 * allocated by upper applications are not equal to the numbers of Rx
2283 * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2284 * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2285 * these fake queues are imperceptible, and can not be used by upper
2288 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2290 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2294 hw->adapter_state = HNS3_NIC_CONFIGURING;
2295 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2296 hns3_err(hw, "setting link speed/duplex not supported");
2301 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2302 ret = hns3_check_dcb_cfg(dev);
2307 /* When RSS is not configured, redirect the packet queue 0 */
2308 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2309 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2310 rss_conf = conf->rx_adv_conf.rss_conf;
2311 if (rss_conf.rss_key == NULL) {
2312 rss_conf.rss_key = rss_cfg->key;
2313 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2316 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2322 * If jumbo frames are enabled, MTU needs to be refreshed
2323 * according to the maximum RX packet length.
2325 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2327 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2328 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2329 * can safely assign to "uint16_t" type variable.
2331 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2332 ret = hns3_dev_mtu_set(dev, mtu);
2335 dev->data->mtu = mtu;
2338 ret = hns3_dev_configure_vlan(dev);
2342 hw->adapter_state = HNS3_NIC_CONFIGURED;
2347 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2348 hw->adapter_state = HNS3_NIC_INITIALIZED;
2354 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2356 struct hns3_config_max_frm_size_cmd *req;
2357 struct hns3_cmd_desc desc;
2359 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2361 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2362 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2363 req->min_frm_size = RTE_ETHER_MIN_LEN;
2365 return hns3_cmd_send(hw, &desc, 1);
2369 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2373 ret = hns3_set_mac_mtu(hw, mps);
2375 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2379 ret = hns3_buffer_alloc(hw);
2381 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2387 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2389 struct hns3_adapter *hns = dev->data->dev_private;
2390 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2391 struct hns3_hw *hw = &hns->hw;
2392 bool is_jumbo_frame;
2395 if (dev->data->dev_started) {
2396 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2397 "before configuration", dev->data->port_id);
2401 rte_spinlock_lock(&hw->lock);
2402 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2403 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2406 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2407 * assign to "uint16_t" type variable.
2409 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2411 rte_spinlock_unlock(&hw->lock);
2412 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2413 dev->data->port_id, mtu, ret);
2416 hns->pf.mps = (uint16_t)frame_size;
2418 dev->data->dev_conf.rxmode.offloads |=
2419 DEV_RX_OFFLOAD_JUMBO_FRAME;
2421 dev->data->dev_conf.rxmode.offloads &=
2422 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2423 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2424 rte_spinlock_unlock(&hw->lock);
2430 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2432 struct hns3_adapter *hns = eth_dev->data->dev_private;
2433 struct hns3_hw *hw = &hns->hw;
2434 uint16_t queue_num = hw->tqps_num;
2437 * In interrupt mode, 'max_rx_queues' is set based on the number of
2438 * MSI-X interrupt resources of the hardware.
2440 if (hw->data->dev_conf.intr_conf.rxq == 1)
2441 queue_num = hw->intr_tqps_num;
2443 info->max_rx_queues = queue_num;
2444 info->max_tx_queues = hw->tqps_num;
2445 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2446 info->min_rx_bufsize = hw->rx_buf_len;
2447 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2448 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2449 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2450 DEV_RX_OFFLOAD_TCP_CKSUM |
2451 DEV_RX_OFFLOAD_UDP_CKSUM |
2452 DEV_RX_OFFLOAD_SCTP_CKSUM |
2453 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2454 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2455 DEV_RX_OFFLOAD_KEEP_CRC |
2456 DEV_RX_OFFLOAD_SCATTER |
2457 DEV_RX_OFFLOAD_VLAN_STRIP |
2458 DEV_RX_OFFLOAD_VLAN_FILTER |
2459 DEV_RX_OFFLOAD_JUMBO_FRAME |
2460 DEV_RX_OFFLOAD_RSS_HASH);
2461 info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2462 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2463 DEV_TX_OFFLOAD_IPV4_CKSUM |
2464 DEV_TX_OFFLOAD_TCP_CKSUM |
2465 DEV_TX_OFFLOAD_UDP_CKSUM |
2466 DEV_TX_OFFLOAD_SCTP_CKSUM |
2467 DEV_TX_OFFLOAD_VLAN_INSERT |
2468 DEV_TX_OFFLOAD_QINQ_INSERT |
2469 DEV_TX_OFFLOAD_MULTI_SEGS |
2470 DEV_TX_OFFLOAD_TCP_TSO |
2471 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2472 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2473 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2474 info->tx_queue_offload_capa);
2476 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2477 .nb_max = HNS3_MAX_RING_DESC,
2478 .nb_min = HNS3_MIN_RING_DESC,
2479 .nb_align = HNS3_ALIGN_RING_DESC,
2482 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2483 .nb_max = HNS3_MAX_RING_DESC,
2484 .nb_min = HNS3_MIN_RING_DESC,
2485 .nb_align = HNS3_ALIGN_RING_DESC,
2488 info->vmdq_queue_num = 0;
2490 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2491 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2492 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2494 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2495 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2496 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2497 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2498 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2499 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2505 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2508 struct hns3_adapter *hns = eth_dev->data->dev_private;
2509 struct hns3_hw *hw = &hns->hw;
2510 uint32_t version = hw->fw_version;
2513 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2514 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2515 HNS3_FW_VERSION_BYTE3_S),
2516 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2517 HNS3_FW_VERSION_BYTE2_S),
2518 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2519 HNS3_FW_VERSION_BYTE1_S),
2520 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2521 HNS3_FW_VERSION_BYTE0_S));
2522 ret += 1; /* add the size of '\0' */
2523 if (fw_size < (uint32_t)ret)
2530 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2531 __rte_unused int wait_to_complete)
2533 struct hns3_adapter *hns = eth_dev->data->dev_private;
2534 struct hns3_hw *hw = &hns->hw;
2535 struct hns3_mac *mac = &hw->mac;
2536 struct rte_eth_link new_link;
2538 if (!hns3_is_reset_pending(hns)) {
2539 hns3_update_speed_duplex(eth_dev);
2540 hns3_update_link_status(hw);
2543 memset(&new_link, 0, sizeof(new_link));
2544 switch (mac->link_speed) {
2545 case ETH_SPEED_NUM_10M:
2546 case ETH_SPEED_NUM_100M:
2547 case ETH_SPEED_NUM_1G:
2548 case ETH_SPEED_NUM_10G:
2549 case ETH_SPEED_NUM_25G:
2550 case ETH_SPEED_NUM_40G:
2551 case ETH_SPEED_NUM_50G:
2552 case ETH_SPEED_NUM_100G:
2553 new_link.link_speed = mac->link_speed;
2556 new_link.link_speed = ETH_SPEED_NUM_100M;
2560 new_link.link_duplex = mac->link_duplex;
2561 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2562 new_link.link_autoneg =
2563 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2565 return rte_eth_linkstatus_set(eth_dev, &new_link);
2569 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2571 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2572 struct hns3_pf *pf = &hns->pf;
2574 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2577 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2583 hns3_query_function_status(struct hns3_hw *hw)
2585 #define HNS3_QUERY_MAX_CNT 10
2586 #define HNS3_QUERY_SLEEP_MSCOEND 1
2587 struct hns3_func_status_cmd *req;
2588 struct hns3_cmd_desc desc;
2592 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2593 req = (struct hns3_func_status_cmd *)desc.data;
2596 ret = hns3_cmd_send(hw, &desc, 1);
2598 PMD_INIT_LOG(ERR, "query function status failed %d",
2603 /* Check pf reset is done */
2607 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2608 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2610 return hns3_parse_func_status(hw, req);
2614 hns3_query_pf_resource(struct hns3_hw *hw)
2616 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2617 struct hns3_pf *pf = &hns->pf;
2618 struct hns3_pf_res_cmd *req;
2619 struct hns3_cmd_desc desc;
2622 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2623 ret = hns3_cmd_send(hw, &desc, 1);
2625 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2629 req = (struct hns3_pf_res_cmd *)desc.data;
2630 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2631 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2632 hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2633 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2635 if (req->tx_buf_size)
2637 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2639 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2641 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2643 if (req->dv_buf_size)
2645 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2647 pf->dv_buf_size = HNS3_DEFAULT_DV;
2649 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2652 hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2653 HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2659 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2661 struct hns3_cfg_param_cmd *req;
2662 uint64_t mac_addr_tmp_high;
2663 uint64_t mac_addr_tmp;
2666 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2668 /* get the configuration */
2669 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2670 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2671 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2672 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2673 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2674 HNS3_CFG_TQP_DESC_N_M,
2675 HNS3_CFG_TQP_DESC_N_S);
2677 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2678 HNS3_CFG_PHY_ADDR_M,
2679 HNS3_CFG_PHY_ADDR_S);
2680 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2681 HNS3_CFG_MEDIA_TP_M,
2682 HNS3_CFG_MEDIA_TP_S);
2683 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2684 HNS3_CFG_RX_BUF_LEN_M,
2685 HNS3_CFG_RX_BUF_LEN_S);
2686 /* get mac address */
2687 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2688 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2689 HNS3_CFG_MAC_ADDR_H_M,
2690 HNS3_CFG_MAC_ADDR_H_S);
2692 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2694 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2695 HNS3_CFG_DEFAULT_SPEED_M,
2696 HNS3_CFG_DEFAULT_SPEED_S);
2697 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2698 HNS3_CFG_RSS_SIZE_M,
2699 HNS3_CFG_RSS_SIZE_S);
2701 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2702 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2704 req = (struct hns3_cfg_param_cmd *)desc[1].data;
2705 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2707 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2708 HNS3_CFG_SPEED_ABILITY_M,
2709 HNS3_CFG_SPEED_ABILITY_S);
2710 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2711 HNS3_CFG_UMV_TBL_SPACE_M,
2712 HNS3_CFG_UMV_TBL_SPACE_S);
2713 if (!cfg->umv_space)
2714 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2717 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2718 * @hw: pointer to struct hns3_hw
2719 * @hcfg: the config structure to be getted
2722 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2724 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2725 struct hns3_cfg_param_cmd *req;
2730 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2732 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2733 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2735 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2736 i * HNS3_CFG_RD_LEN_BYTES);
2737 /* Len should be divided by 4 when send to hardware */
2738 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2739 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2740 req->offset = rte_cpu_to_le_32(offset);
2743 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2745 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2749 hns3_parse_cfg(hcfg, desc);
2755 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2757 switch (speed_cmd) {
2758 case HNS3_CFG_SPEED_10M:
2759 *speed = ETH_SPEED_NUM_10M;
2761 case HNS3_CFG_SPEED_100M:
2762 *speed = ETH_SPEED_NUM_100M;
2764 case HNS3_CFG_SPEED_1G:
2765 *speed = ETH_SPEED_NUM_1G;
2767 case HNS3_CFG_SPEED_10G:
2768 *speed = ETH_SPEED_NUM_10G;
2770 case HNS3_CFG_SPEED_25G:
2771 *speed = ETH_SPEED_NUM_25G;
2773 case HNS3_CFG_SPEED_40G:
2774 *speed = ETH_SPEED_NUM_40G;
2776 case HNS3_CFG_SPEED_50G:
2777 *speed = ETH_SPEED_NUM_50G;
2779 case HNS3_CFG_SPEED_100G:
2780 *speed = ETH_SPEED_NUM_100G;
2790 hns3_get_board_configuration(struct hns3_hw *hw)
2792 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2793 struct hns3_pf *pf = &hns->pf;
2794 struct hns3_cfg cfg;
2797 ret = hns3_get_board_cfg(hw, &cfg);
2799 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2803 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2804 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2808 hw->mac.media_type = cfg.media_type;
2809 hw->rss_size_max = cfg.rss_size_max;
2810 hw->rss_dis_flag = false;
2811 hw->rx_buf_len = cfg.rx_buf_len;
2812 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2813 hw->mac.phy_addr = cfg.phy_addr;
2814 hw->mac.default_addr_setted = false;
2815 hw->num_tx_desc = cfg.tqp_desc_num;
2816 hw->num_rx_desc = cfg.tqp_desc_num;
2817 hw->dcb_info.num_pg = 1;
2818 hw->dcb_info.hw_pfc_map = 0;
2820 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2822 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2823 cfg.default_speed, ret);
2827 pf->tc_max = cfg.tc_num;
2828 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2829 PMD_INIT_LOG(WARNING,
2830 "Get TC num(%u) from flash, set TC num to 1",
2835 /* Dev does not support DCB */
2836 if (!hns3_dev_dcb_supported(hw)) {
2840 pf->pfc_max = pf->tc_max;
2842 hw->dcb_info.num_tc = 1;
2843 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2844 hw->tqps_num / hw->dcb_info.num_tc);
2845 hns3_set_bit(hw->hw_tc_map, 0, 1);
2846 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2848 pf->wanted_umv_size = cfg.umv_space;
2854 hns3_get_configuration(struct hns3_hw *hw)
2858 ret = hns3_query_function_status(hw);
2860 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2864 /* Get pf resource */
2865 ret = hns3_query_pf_resource(hw);
2867 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2871 ret = hns3_get_board_configuration(hw);
2873 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2879 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2880 uint16_t tqp_vid, bool is_pf)
2882 struct hns3_tqp_map_cmd *req;
2883 struct hns3_cmd_desc desc;
2886 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2888 req = (struct hns3_tqp_map_cmd *)desc.data;
2889 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2890 req->tqp_vf = func_id;
2891 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2893 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2894 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2896 ret = hns3_cmd_send(hw, &desc, 1);
2898 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2904 hns3_map_tqp(struct hns3_hw *hw)
2906 uint16_t tqps_num = hw->total_tqps_num;
2915 * In current version VF is not supported when PF is driven by DPDK
2916 * driver, so we allocate tqps to PF as much as possible.
2919 num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2920 for (func_id = HNS3_PF_FUNC_ID; func_id < num; func_id++) {
2921 is_pf = func_id == HNS3_PF_FUNC_ID ? true : false;
2923 i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2924 ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2935 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2937 struct hns3_config_mac_speed_dup_cmd *req;
2938 struct hns3_cmd_desc desc;
2941 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2943 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2945 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2948 case ETH_SPEED_NUM_10M:
2949 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2950 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2952 case ETH_SPEED_NUM_100M:
2953 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2954 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2956 case ETH_SPEED_NUM_1G:
2957 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2958 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2960 case ETH_SPEED_NUM_10G:
2961 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2962 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2964 case ETH_SPEED_NUM_25G:
2965 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2966 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2968 case ETH_SPEED_NUM_40G:
2969 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2970 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2972 case ETH_SPEED_NUM_50G:
2973 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2974 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2976 case ETH_SPEED_NUM_100G:
2977 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2978 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2981 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2985 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2987 ret = hns3_cmd_send(hw, &desc, 1);
2989 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2995 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2997 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2998 struct hns3_pf *pf = &hns->pf;
2999 struct hns3_priv_buf *priv;
3000 uint32_t i, total_size;
3002 total_size = pf->pkt_buf_size;
3004 /* alloc tx buffer for all enabled tc */
3005 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3006 priv = &buf_alloc->priv_buf[i];
3008 if (hw->hw_tc_map & BIT(i)) {
3009 if (total_size < pf->tx_buf_size)
3012 priv->tx_buf_size = pf->tx_buf_size;
3014 priv->tx_buf_size = 0;
3016 total_size -= priv->tx_buf_size;
3023 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3025 /* TX buffer size is unit by 128 byte */
3026 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3027 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3028 struct hns3_tx_buff_alloc_cmd *req;
3029 struct hns3_cmd_desc desc;
3034 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3036 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3037 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3038 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3040 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3041 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3042 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3045 ret = hns3_cmd_send(hw, &desc, 1);
3047 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3053 hns3_get_tc_num(struct hns3_hw *hw)
3058 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3059 if (hw->hw_tc_map & BIT(i))
3065 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3067 struct hns3_priv_buf *priv;
3068 uint32_t rx_priv = 0;
3071 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3072 priv = &buf_alloc->priv_buf[i];
3074 rx_priv += priv->buf_size;
3080 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3082 uint32_t total_tx_size = 0;
3085 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3086 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3088 return total_tx_size;
3091 /* Get the number of pfc enabled TCs, which have private buffer */
3093 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3095 struct hns3_priv_buf *priv;
3099 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3100 priv = &buf_alloc->priv_buf[i];
3101 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3108 /* Get the number of pfc disabled TCs, which have private buffer */
3110 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3111 struct hns3_pkt_buf_alloc *buf_alloc)
3113 struct hns3_priv_buf *priv;
3117 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3118 priv = &buf_alloc->priv_buf[i];
3119 if (hw->hw_tc_map & BIT(i) &&
3120 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3128 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3131 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3132 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3133 struct hns3_pf *pf = &hns->pf;
3134 uint32_t shared_buf, aligned_mps;
3139 tc_num = hns3_get_tc_num(hw);
3140 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3142 if (hns3_dev_dcb_supported(hw))
3143 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3146 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3149 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3150 shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3151 HNS3_BUF_SIZE_UNIT);
3153 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3154 if (rx_all < rx_priv + shared_std)
3157 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3158 buf_alloc->s_buf.buf_size = shared_buf;
3159 if (hns3_dev_dcb_supported(hw)) {
3160 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3161 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3162 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3163 HNS3_BUF_SIZE_UNIT);
3165 buf_alloc->s_buf.self.high =
3166 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3167 buf_alloc->s_buf.self.low = aligned_mps;
3170 if (hns3_dev_dcb_supported(hw)) {
3171 hi_thrd = shared_buf - pf->dv_buf_size;
3173 if (tc_num <= NEED_RESERVE_TC_NUM)
3174 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3178 hi_thrd = hi_thrd / tc_num;
3180 hi_thrd = max_t(uint32_t, hi_thrd,
3181 HNS3_BUF_MUL_BY * aligned_mps);
3182 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3183 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3185 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3186 lo_thrd = aligned_mps;
3189 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3190 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3191 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3198 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3199 struct hns3_pkt_buf_alloc *buf_alloc)
3201 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3202 struct hns3_pf *pf = &hns->pf;
3203 struct hns3_priv_buf *priv;
3204 uint32_t aligned_mps;
3208 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3209 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3211 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3212 priv = &buf_alloc->priv_buf[i];
3219 if (!(hw->hw_tc_map & BIT(i)))
3223 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3224 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3225 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3226 HNS3_BUF_SIZE_UNIT);
3229 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3233 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3236 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3240 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3241 struct hns3_pkt_buf_alloc *buf_alloc)
3243 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3244 struct hns3_pf *pf = &hns->pf;
3245 struct hns3_priv_buf *priv;
3246 int no_pfc_priv_num;
3251 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3252 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3254 /* let the last to be cleared first */
3255 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3256 priv = &buf_alloc->priv_buf[i];
3257 mask = BIT((uint8_t)i);
3259 if (hw->hw_tc_map & mask &&
3260 !(hw->dcb_info.hw_pfc_map & mask)) {
3261 /* Clear the no pfc TC private buffer */
3269 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3270 no_pfc_priv_num == 0)
3274 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3278 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3279 struct hns3_pkt_buf_alloc *buf_alloc)
3281 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3282 struct hns3_pf *pf = &hns->pf;
3283 struct hns3_priv_buf *priv;
3289 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3290 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3292 /* let the last to be cleared first */
3293 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3294 priv = &buf_alloc->priv_buf[i];
3295 mask = BIT((uint8_t)i);
3297 if (hw->hw_tc_map & mask &&
3298 hw->dcb_info.hw_pfc_map & mask) {
3299 /* Reduce the number of pfc TC with private buffer */
3306 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3311 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3315 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3316 struct hns3_pkt_buf_alloc *buf_alloc)
3318 #define COMPENSATE_BUFFER 0x3C00
3319 #define COMPENSATE_HALF_MPS_NUM 5
3320 #define PRIV_WL_GAP 0x1800
3321 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3322 struct hns3_pf *pf = &hns->pf;
3323 uint32_t tc_num = hns3_get_tc_num(hw);
3324 uint32_t half_mps = pf->mps >> 1;
3325 struct hns3_priv_buf *priv;
3326 uint32_t min_rx_priv;
3330 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3332 rx_priv = rx_priv / tc_num;
3334 if (tc_num <= NEED_RESERVE_TC_NUM)
3335 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3338 * Minimum value of private buffer in rx direction (min_rx_priv) is
3339 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3340 * buffer if rx_priv is greater than min_rx_priv.
3342 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3343 COMPENSATE_HALF_MPS_NUM * half_mps;
3344 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3345 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3347 if (rx_priv < min_rx_priv)
3350 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3351 priv = &buf_alloc->priv_buf[i];
3358 if (!(hw->hw_tc_map & BIT(i)))
3362 priv->buf_size = rx_priv;
3363 priv->wl.high = rx_priv - pf->dv_buf_size;
3364 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3367 buf_alloc->s_buf.buf_size = 0;
3373 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3374 * @hw: pointer to struct hns3_hw
3375 * @buf_alloc: pointer to buffer calculation data
3376 * @return: 0: calculate sucessful, negative: fail
3379 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3381 /* When DCB is not supported, rx private buffer is not allocated. */
3382 if (!hns3_dev_dcb_supported(hw)) {
3383 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3384 struct hns3_pf *pf = &hns->pf;
3385 uint32_t rx_all = pf->pkt_buf_size;
3387 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3388 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3395 * Try to allocate privated packet buffer for all TCs without share
3398 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3402 * Try to allocate privated packet buffer for all TCs with share
3405 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3409 * For different application scenes, the enabled port number, TC number
3410 * and no_drop TC number are different. In order to obtain the better
3411 * performance, software could allocate the buffer size and configure
3412 * the waterline by tring to decrease the private buffer size according
3413 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3416 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3419 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3422 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3429 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3431 struct hns3_rx_priv_buff_cmd *req;
3432 struct hns3_cmd_desc desc;
3437 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3438 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3440 /* Alloc private buffer TCs */
3441 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3442 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3445 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3446 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3449 buf_size = buf_alloc->s_buf.buf_size;
3450 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3451 (1 << HNS3_TC0_PRI_BUF_EN_B));
3453 ret = hns3_cmd_send(hw, &desc, 1);
3455 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3461 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3463 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3464 struct hns3_rx_priv_wl_buf *req;
3465 struct hns3_priv_buf *priv;
3466 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3470 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3471 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3473 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3475 /* The first descriptor set the NEXT bit to 1 */
3477 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3479 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3481 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3482 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3484 priv = &buf_alloc->priv_buf[idx];
3485 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3487 req->tc_wl[j].high |=
3488 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3489 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3491 req->tc_wl[j].low |=
3492 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3496 /* Send 2 descriptor at one time */
3497 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3499 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3505 hns3_common_thrd_config(struct hns3_hw *hw,
3506 struct hns3_pkt_buf_alloc *buf_alloc)
3508 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3509 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3510 struct hns3_rx_com_thrd *req;
3511 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3512 struct hns3_tc_thrd *tc;
3517 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3518 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3520 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3522 /* The first descriptor set the NEXT bit to 1 */
3524 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3526 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3528 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3529 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3530 tc = &s_buf->tc_thrd[tc_idx];
3532 req->com_thrd[j].high =
3533 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3534 req->com_thrd[j].high |=
3535 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3536 req->com_thrd[j].low =
3537 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3538 req->com_thrd[j].low |=
3539 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3543 /* Send 2 descriptors at one time */
3544 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3546 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3552 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3554 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3555 struct hns3_rx_com_wl *req;
3556 struct hns3_cmd_desc desc;
3559 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3561 req = (struct hns3_rx_com_wl *)desc.data;
3562 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3563 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3565 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3566 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3568 ret = hns3_cmd_send(hw, &desc, 1);
3570 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3576 hns3_buffer_alloc(struct hns3_hw *hw)
3578 struct hns3_pkt_buf_alloc pkt_buf;
3581 memset(&pkt_buf, 0, sizeof(pkt_buf));
3582 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3585 "could not calc tx buffer size for all TCs %d",
3590 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3592 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3596 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3599 "could not calc rx priv buffer size for all TCs %d",
3604 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3606 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3610 if (hns3_dev_dcb_supported(hw)) {
3611 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3614 "could not configure rx private waterline %d",
3619 ret = hns3_common_thrd_config(hw, &pkt_buf);
3622 "could not configure common threshold %d",
3628 ret = hns3_common_wl_config(hw, &pkt_buf);
3630 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3637 hns3_mac_init(struct hns3_hw *hw)
3639 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3640 struct hns3_mac *mac = &hw->mac;
3641 struct hns3_pf *pf = &hns->pf;
3644 pf->support_sfp_query = true;
3645 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3646 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3648 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3652 mac->link_status = ETH_LINK_DOWN;
3654 return hns3_config_mtu(hw, pf->mps);
3658 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3660 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
3661 #define HNS3_ETHERTYPE_ALREADY_ADD 1
3662 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
3663 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
3668 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3673 switch (resp_code) {
3674 case HNS3_ETHERTYPE_SUCCESS_ADD:
3675 case HNS3_ETHERTYPE_ALREADY_ADD:
3678 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3680 "add mac ethertype failed for manager table overflow.");
3681 return_status = -EIO;
3683 case HNS3_ETHERTYPE_KEY_CONFLICT:
3684 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3685 return_status = -EIO;
3689 "add mac ethertype failed for undefined, code=%d.",
3691 return_status = -EIO;
3695 return return_status;
3699 hns3_add_mgr_tbl(struct hns3_hw *hw,
3700 const struct hns3_mac_mgr_tbl_entry_cmd *req)
3702 struct hns3_cmd_desc desc;
3707 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3708 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3710 ret = hns3_cmd_send(hw, &desc, 1);
3713 "add mac ethertype failed for cmd_send, ret =%d.",
3718 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3719 retval = rte_le_to_cpu_16(desc.retval);
3721 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3725 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3726 int *table_item_num)
3728 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3731 * In current version, we add one item in management table as below:
3732 * 0x0180C200000E -- LLDP MC address
3735 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3736 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3737 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3738 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3739 tbl->i_port_bitmap = 0x1;
3740 *table_item_num = 1;
3744 hns3_init_mgr_tbl(struct hns3_hw *hw)
3746 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
3747 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3752 memset(mgr_table, 0, sizeof(mgr_table));
3753 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3754 for (i = 0; i < table_item_num; i++) {
3755 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3757 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3767 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3768 bool en_mc, bool en_bc, int vport_id)
3773 memset(param, 0, sizeof(struct hns3_promisc_param));
3775 param->enable = HNS3_PROMISC_EN_UC;
3777 param->enable |= HNS3_PROMISC_EN_MC;
3779 param->enable |= HNS3_PROMISC_EN_BC;
3780 param->vf_id = vport_id;
3784 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3786 struct hns3_promisc_cfg_cmd *req;
3787 struct hns3_cmd_desc desc;
3790 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3792 req = (struct hns3_promisc_cfg_cmd *)desc.data;
3793 req->vf_id = param->vf_id;
3794 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3795 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3797 ret = hns3_cmd_send(hw, &desc, 1);
3799 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3805 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3807 struct hns3_promisc_param param;
3808 bool en_bc_pmc = true;
3812 * In current version VF is not supported when PF is driven by DPDK
3813 * driver, just need to configure parameters for PF vport.
3815 vf_id = HNS3_PF_FUNC_ID;
3817 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3818 return hns3_cmd_set_promisc_mode(hw, ¶m);
3822 hns3_promisc_init(struct hns3_hw *hw)
3824 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3825 struct hns3_pf *pf = &hns->pf;
3826 struct hns3_promisc_param param;
3830 ret = hns3_set_promisc_mode(hw, false, false);
3832 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
3837 * In current version VFs are not supported when PF is driven by DPDK
3838 * driver. After PF has been taken over by DPDK, the original VF will
3839 * be invalid. So, there is a possibility of entry residues. It should
3840 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
3843 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
3844 hns3_promisc_param_init(¶m, false, false, false, func_id);
3845 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
3847 PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode,"
3848 " ret = %d", func_id, ret);
3857 hns3_promisc_uninit(struct hns3_hw *hw)
3859 struct hns3_promisc_param param;
3863 func_id = HNS3_PF_FUNC_ID;
3866 * In current version VFs are not supported when PF is driven by
3867 * DPDK driver, and VFs' promisc mode status has been cleared during
3868 * init and their status will not change. So just clear PF's promisc
3869 * mode status during uninit.
3871 hns3_promisc_param_init(¶m, false, false, false, func_id);
3872 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
3874 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
3875 " uninit, ret = %d", ret);
3879 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3881 bool allmulti = dev->data->all_multicast ? true : false;
3882 struct hns3_adapter *hns = dev->data->dev_private;
3883 struct hns3_hw *hw = &hns->hw;
3888 rte_spinlock_lock(&hw->lock);
3889 ret = hns3_set_promisc_mode(hw, true, true);
3891 rte_spinlock_unlock(&hw->lock);
3892 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
3898 * When promiscuous mode was enabled, disable the vlan filter to let
3899 * all packets coming in in the receiving direction.
3901 offloads = dev->data->dev_conf.rxmode.offloads;
3902 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3903 ret = hns3_enable_vlan_filter(hns, false);
3905 hns3_err(hw, "failed to enable promiscuous mode due to "
3906 "failure to disable vlan filter, ret = %d",
3908 err = hns3_set_promisc_mode(hw, false, allmulti);
3910 hns3_err(hw, "failed to restore promiscuous "
3911 "status after disable vlan filter "
3912 "failed during enabling promiscuous "
3913 "mode, ret = %d", ret);
3917 rte_spinlock_unlock(&hw->lock);
3923 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3925 bool allmulti = dev->data->all_multicast ? true : false;
3926 struct hns3_adapter *hns = dev->data->dev_private;
3927 struct hns3_hw *hw = &hns->hw;
3932 /* If now in all_multicast mode, must remain in all_multicast mode. */
3933 rte_spinlock_lock(&hw->lock);
3934 ret = hns3_set_promisc_mode(hw, false, allmulti);
3936 rte_spinlock_unlock(&hw->lock);
3937 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
3941 /* when promiscuous mode was disabled, restore the vlan filter status */
3942 offloads = dev->data->dev_conf.rxmode.offloads;
3943 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3944 ret = hns3_enable_vlan_filter(hns, true);
3946 hns3_err(hw, "failed to disable promiscuous mode due to"
3947 " failure to restore vlan filter, ret = %d",
3949 err = hns3_set_promisc_mode(hw, true, true);
3951 hns3_err(hw, "failed to restore promiscuous "
3952 "status after enabling vlan filter "
3953 "failed during disabling promiscuous "
3954 "mode, ret = %d", ret);
3957 rte_spinlock_unlock(&hw->lock);
3963 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3965 struct hns3_adapter *hns = dev->data->dev_private;
3966 struct hns3_hw *hw = &hns->hw;
3969 if (dev->data->promiscuous)
3972 rte_spinlock_lock(&hw->lock);
3973 ret = hns3_set_promisc_mode(hw, false, true);
3974 rte_spinlock_unlock(&hw->lock);
3976 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
3983 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3985 struct hns3_adapter *hns = dev->data->dev_private;
3986 struct hns3_hw *hw = &hns->hw;
3989 /* If now in promiscuous mode, must remain in all_multicast mode. */
3990 if (dev->data->promiscuous)
3993 rte_spinlock_lock(&hw->lock);
3994 ret = hns3_set_promisc_mode(hw, false, false);
3995 rte_spinlock_unlock(&hw->lock);
3997 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4004 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4006 struct hns3_hw *hw = &hns->hw;
4007 bool allmulti = hw->data->all_multicast ? true : false;
4010 if (hw->data->promiscuous) {
4011 ret = hns3_set_promisc_mode(hw, true, true);
4013 hns3_err(hw, "failed to restore promiscuous mode, "
4018 ret = hns3_set_promisc_mode(hw, false, allmulti);
4020 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4026 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4028 struct hns3_sfp_speed_cmd *resp;
4029 struct hns3_cmd_desc desc;
4032 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4033 resp = (struct hns3_sfp_speed_cmd *)desc.data;
4034 ret = hns3_cmd_send(hw, &desc, 1);
4035 if (ret == -EOPNOTSUPP) {
4036 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4039 hns3_err(hw, "get sfp speed failed %d", ret);
4043 *speed = resp->sfp_speed;
4049 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4051 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4052 duplex = ETH_LINK_FULL_DUPLEX;
4058 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4060 struct hns3_mac *mac = &hw->mac;
4063 duplex = hns3_check_speed_dup(duplex, speed);
4064 if (mac->link_speed == speed && mac->link_duplex == duplex)
4067 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4071 mac->link_speed = speed;
4072 mac->link_duplex = duplex;
4078 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4080 struct hns3_adapter *hns = eth_dev->data->dev_private;
4081 struct hns3_hw *hw = &hns->hw;
4082 struct hns3_pf *pf = &hns->pf;
4086 /* If IMP do not support get SFP/qSFP speed, return directly */
4087 if (!pf->support_sfp_query)
4090 ret = hns3_get_sfp_speed(hw, &speed);
4091 if (ret == -EOPNOTSUPP) {
4092 pf->support_sfp_query = false;
4097 if (speed == ETH_SPEED_NUM_NONE)
4098 return 0; /* do nothing if no SFP */
4100 /* Config full duplex for SFP */
4101 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4105 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4107 struct hns3_config_mac_mode_cmd *req;
4108 struct hns3_cmd_desc desc;
4109 uint32_t loop_en = 0;
4113 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4115 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4118 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4119 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4120 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4121 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4122 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4123 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4124 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4125 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4126 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4127 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4128 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4129 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4130 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4131 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4132 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4134 ret = hns3_cmd_send(hw, &desc, 1);
4136 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4142 hns3_get_mac_link_status(struct hns3_hw *hw)
4144 struct hns3_link_status_cmd *req;
4145 struct hns3_cmd_desc desc;
4149 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4150 ret = hns3_cmd_send(hw, &desc, 1);
4152 hns3_err(hw, "get link status cmd failed %d", ret);
4153 return ETH_LINK_DOWN;
4156 req = (struct hns3_link_status_cmd *)desc.data;
4157 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4159 return !!link_status;
4163 hns3_update_link_status(struct hns3_hw *hw)
4167 state = hns3_get_mac_link_status(hw);
4168 if (state != hw->mac.link_status) {
4169 hw->mac.link_status = state;
4170 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4175 hns3_service_handler(void *param)
4177 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4178 struct hns3_adapter *hns = eth_dev->data->dev_private;
4179 struct hns3_hw *hw = &hns->hw;
4181 if (!hns3_is_reset_pending(hns)) {
4182 hns3_update_speed_duplex(eth_dev);
4183 hns3_update_link_status(hw);
4185 hns3_warn(hw, "Cancel the query when reset is pending");
4187 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4191 hns3_init_hardware(struct hns3_adapter *hns)
4193 struct hns3_hw *hw = &hns->hw;
4196 ret = hns3_map_tqp(hw);
4198 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4202 ret = hns3_init_umv_space(hw);
4204 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4208 ret = hns3_mac_init(hw);
4210 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4214 ret = hns3_init_mgr_tbl(hw);
4216 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4220 ret = hns3_promisc_init(hw);
4222 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4227 ret = hns3_init_vlan_config(hns);
4229 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4233 ret = hns3_dcb_init(hw);
4235 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4239 ret = hns3_init_fd_config(hns);
4241 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4245 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4247 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4251 ret = hns3_config_gro(hw, false);
4253 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4258 * In the initialization clearing the all hardware mapping relationship
4259 * configurations between queues and interrupt vectors is needed, so
4260 * some error caused by the residual configurations, such as the
4261 * unexpected interrupt, can be avoid.
4263 ret = hns3_init_ring_with_vector(hw);
4265 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4272 hns3_uninit_umv_space(hw);
4277 hns3_init_pf(struct rte_eth_dev *eth_dev)
4279 struct rte_device *dev = eth_dev->device;
4280 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4281 struct hns3_adapter *hns = eth_dev->data->dev_private;
4282 struct hns3_hw *hw = &hns->hw;
4285 PMD_INIT_FUNC_TRACE();
4287 /* Get hardware io base address from pcie BAR2 IO space */
4288 hw->io_base = pci_dev->mem_resource[2].addr;
4290 /* Firmware command queue initialize */
4291 ret = hns3_cmd_init_queue(hw);
4293 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4294 goto err_cmd_init_queue;
4297 hns3_clear_all_event_cause(hw);
4299 /* Firmware command initialize */
4300 ret = hns3_cmd_init(hw);
4302 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4306 ret = rte_intr_callback_register(&pci_dev->intr_handle,
4307 hns3_interrupt_handler,
4310 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4311 goto err_intr_callback_register;
4314 /* Enable interrupt */
4315 rte_intr_enable(&pci_dev->intr_handle);
4316 hns3_pf_enable_irq0(hw);
4318 /* Get configuration */
4319 ret = hns3_get_configuration(hw);
4321 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4322 goto err_get_config;
4325 ret = hns3_init_hardware(hns);
4327 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4328 goto err_get_config;
4331 /* Initialize flow director filter list & hash */
4332 ret = hns3_fdir_filter_init(hns);
4334 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4338 hns3_set_default_rss_args(hw);
4340 ret = hns3_enable_hw_error_intr(hns, true);
4342 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4350 hns3_fdir_filter_uninit(hns);
4352 hns3_uninit_umv_space(hw);
4355 hns3_pf_disable_irq0(hw);
4356 rte_intr_disable(&pci_dev->intr_handle);
4357 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4359 err_intr_callback_register:
4361 hns3_cmd_uninit(hw);
4362 hns3_cmd_destroy_queue(hw);
4370 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4372 struct hns3_adapter *hns = eth_dev->data->dev_private;
4373 struct rte_device *dev = eth_dev->device;
4374 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4375 struct hns3_hw *hw = &hns->hw;
4377 PMD_INIT_FUNC_TRACE();
4379 hns3_enable_hw_error_intr(hns, false);
4380 hns3_rss_uninit(hns);
4381 hns3_promisc_uninit(hw);
4382 hns3_fdir_filter_uninit(hns);
4383 hns3_uninit_umv_space(hw);
4384 hns3_pf_disable_irq0(hw);
4385 rte_intr_disable(&pci_dev->intr_handle);
4386 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4388 hns3_cmd_uninit(hw);
4389 hns3_cmd_destroy_queue(hw);
4394 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4396 struct hns3_hw *hw = &hns->hw;
4399 ret = hns3_dcb_cfg_update(hns);
4404 ret = hns3_start_queues(hns, reset_queue);
4406 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4411 ret = hns3_cfg_mac_mode(hw, true);
4413 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4414 goto err_config_mac_mode;
4418 err_config_mac_mode:
4419 hns3_stop_queues(hns, true);
4424 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4426 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4427 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4428 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4429 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4430 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4431 uint32_t intr_vector;
4435 if (dev->data->dev_conf.intr_conf.rxq == 0)
4438 /* disable uio/vfio intr/eventfd mapping */
4439 rte_intr_disable(intr_handle);
4441 /* check and configure queue intr-vector mapping */
4442 if (rte_intr_cap_multiple(intr_handle) ||
4443 !RTE_ETH_DEV_SRIOV(dev).active) {
4444 intr_vector = hw->used_rx_queues;
4445 /* creates event fd for each intr vector when MSIX is used */
4446 if (rte_intr_efd_enable(intr_handle, intr_vector))
4449 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4450 intr_handle->intr_vec =
4451 rte_zmalloc("intr_vec",
4452 hw->used_rx_queues * sizeof(int), 0);
4453 if (intr_handle->intr_vec == NULL) {
4454 hns3_err(hw, "Failed to allocate %d rx_queues"
4455 " intr_vec", hw->used_rx_queues);
4457 goto alloc_intr_vec_error;
4461 if (rte_intr_allow_others(intr_handle)) {
4462 vec = RTE_INTR_VEC_RXTX_OFFSET;
4463 base = RTE_INTR_VEC_RXTX_OFFSET;
4465 if (rte_intr_dp_is_en(intr_handle)) {
4466 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4467 ret = hns3_bind_ring_with_vector(hw, vec, true,
4471 goto bind_vector_error;
4472 intr_handle->intr_vec[q_id] = vec;
4473 if (vec < base + intr_handle->nb_efd - 1)
4477 rte_intr_enable(intr_handle);
4481 rte_intr_efd_disable(intr_handle);
4482 if (intr_handle->intr_vec) {
4483 free(intr_handle->intr_vec);
4484 intr_handle->intr_vec = NULL;
4487 alloc_intr_vec_error:
4488 rte_intr_efd_disable(intr_handle);
4493 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4495 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4496 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4497 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4501 if (dev->data->dev_conf.intr_conf.rxq == 0)
4504 if (rte_intr_dp_is_en(intr_handle)) {
4505 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4506 ret = hns3_bind_ring_with_vector(hw,
4507 intr_handle->intr_vec[q_id], true,
4508 HNS3_RING_TYPE_RX, q_id);
4518 hns3_restore_filter(struct rte_eth_dev *dev)
4520 hns3_restore_rss_filter(dev);
4524 hns3_dev_start(struct rte_eth_dev *dev)
4526 struct hns3_adapter *hns = dev->data->dev_private;
4527 struct hns3_hw *hw = &hns->hw;
4530 PMD_INIT_FUNC_TRACE();
4531 if (rte_atomic16_read(&hw->reset.resetting))
4534 rte_spinlock_lock(&hw->lock);
4535 hw->adapter_state = HNS3_NIC_STARTING;
4537 ret = hns3_do_start(hns, true);
4539 hw->adapter_state = HNS3_NIC_CONFIGURED;
4540 rte_spinlock_unlock(&hw->lock);
4543 ret = hns3_map_rx_interrupt(dev);
4545 hw->adapter_state = HNS3_NIC_CONFIGURED;
4546 rte_spinlock_unlock(&hw->lock);
4550 hw->adapter_state = HNS3_NIC_STARTED;
4551 rte_spinlock_unlock(&hw->lock);
4553 hns3_set_rxtx_function(dev);
4554 hns3_mp_req_start_rxtx(dev);
4555 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4557 hns3_restore_filter(dev);
4559 /* Enable interrupt of all rx queues before enabling queues */
4560 hns3_dev_all_rx_queue_intr_enable(hw, true);
4562 * When finished the initialization, enable queues to receive/transmit
4565 hns3_enable_all_queues(hw, true);
4567 hns3_info(hw, "hns3 dev start successful!");
4572 hns3_do_stop(struct hns3_adapter *hns)
4574 struct hns3_hw *hw = &hns->hw;
4578 ret = hns3_cfg_mac_mode(hw, false);
4581 hw->mac.link_status = ETH_LINK_DOWN;
4583 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4584 hns3_configure_all_mac_addr(hns, true);
4587 reset_queue = false;
4588 hw->mac.default_addr_setted = false;
4589 return hns3_stop_queues(hns, reset_queue);
4593 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4595 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4596 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4597 struct hns3_adapter *hns = dev->data->dev_private;
4598 struct hns3_hw *hw = &hns->hw;
4599 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4600 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4603 if (dev->data->dev_conf.intr_conf.rxq == 0)
4606 /* unmap the ring with vector */
4607 if (rte_intr_allow_others(intr_handle)) {
4608 vec = RTE_INTR_VEC_RXTX_OFFSET;
4609 base = RTE_INTR_VEC_RXTX_OFFSET;
4611 if (rte_intr_dp_is_en(intr_handle)) {
4612 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4613 (void)hns3_bind_ring_with_vector(hw, vec, false,
4616 if (vec < base + intr_handle->nb_efd - 1)
4620 /* Clean datapath event and queue/vec mapping */
4621 rte_intr_efd_disable(intr_handle);
4622 if (intr_handle->intr_vec) {
4623 rte_free(intr_handle->intr_vec);
4624 intr_handle->intr_vec = NULL;
4629 hns3_dev_stop(struct rte_eth_dev *dev)
4631 struct hns3_adapter *hns = dev->data->dev_private;
4632 struct hns3_hw *hw = &hns->hw;
4634 PMD_INIT_FUNC_TRACE();
4636 hw->adapter_state = HNS3_NIC_STOPPING;
4637 hns3_set_rxtx_function(dev);
4639 /* Disable datapath on secondary process. */
4640 hns3_mp_req_stop_rxtx(dev);
4641 /* Prevent crashes when queues are still in use. */
4642 rte_delay_ms(hw->tqps_num);
4644 rte_spinlock_lock(&hw->lock);
4645 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4647 hns3_unmap_rx_interrupt(dev);
4648 hns3_dev_release_mbufs(hns);
4649 hw->adapter_state = HNS3_NIC_CONFIGURED;
4651 rte_eal_alarm_cancel(hns3_service_handler, dev);
4652 rte_spinlock_unlock(&hw->lock);
4656 hns3_dev_close(struct rte_eth_dev *eth_dev)
4658 struct hns3_adapter *hns = eth_dev->data->dev_private;
4659 struct hns3_hw *hw = &hns->hw;
4661 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4662 rte_free(eth_dev->process_private);
4663 eth_dev->process_private = NULL;
4667 if (hw->adapter_state == HNS3_NIC_STARTED)
4668 hns3_dev_stop(eth_dev);
4670 hw->adapter_state = HNS3_NIC_CLOSING;
4671 hns3_reset_abort(hns);
4672 hw->adapter_state = HNS3_NIC_CLOSED;
4674 hns3_configure_all_mc_mac_addr(hns, true);
4675 hns3_remove_all_vlan_table(hns);
4676 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4677 hns3_uninit_pf(eth_dev);
4678 hns3_free_all_queues(eth_dev);
4679 rte_free(hw->reset.wait_data);
4680 rte_free(eth_dev->process_private);
4681 eth_dev->process_private = NULL;
4682 hns3_mp_uninit_primary();
4683 hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4687 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4689 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4690 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4692 fc_conf->pause_time = pf->pause_time;
4694 /* return fc current mode */
4695 switch (hw->current_mode) {
4697 fc_conf->mode = RTE_FC_FULL;
4699 case HNS3_FC_TX_PAUSE:
4700 fc_conf->mode = RTE_FC_TX_PAUSE;
4702 case HNS3_FC_RX_PAUSE:
4703 fc_conf->mode = RTE_FC_RX_PAUSE;
4707 fc_conf->mode = RTE_FC_NONE;
4715 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4719 hw->requested_mode = HNS3_FC_NONE;
4721 case RTE_FC_RX_PAUSE:
4722 hw->requested_mode = HNS3_FC_RX_PAUSE;
4724 case RTE_FC_TX_PAUSE:
4725 hw->requested_mode = HNS3_FC_TX_PAUSE;
4728 hw->requested_mode = HNS3_FC_FULL;
4731 hw->requested_mode = HNS3_FC_NONE;
4732 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4733 "configured to RTE_FC_NONE", mode);
4739 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4741 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4742 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4745 if (fc_conf->high_water || fc_conf->low_water ||
4746 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4747 hns3_err(hw, "Unsupported flow control settings specified, "
4748 "high_water(%u), low_water(%u), send_xon(%u) and "
4749 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4750 fc_conf->high_water, fc_conf->low_water,
4751 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4754 if (fc_conf->autoneg) {
4755 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4758 if (!fc_conf->pause_time) {
4759 hns3_err(hw, "Invalid pause time %d setting.",
4760 fc_conf->pause_time);
4764 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4765 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4766 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4767 "current_fc_status = %d", hw->current_fc_status);
4771 hns3_get_fc_mode(hw, fc_conf->mode);
4772 if (hw->requested_mode == hw->current_mode &&
4773 pf->pause_time == fc_conf->pause_time)
4776 rte_spinlock_lock(&hw->lock);
4777 ret = hns3_fc_enable(dev, fc_conf);
4778 rte_spinlock_unlock(&hw->lock);
4784 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4785 struct rte_eth_pfc_conf *pfc_conf)
4787 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4788 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4792 if (!hns3_dev_dcb_supported(hw)) {
4793 hns3_err(hw, "This port does not support dcb configurations.");
4797 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4798 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4799 hns3_err(hw, "Unsupported flow control settings specified, "
4800 "high_water(%u), low_water(%u), send_xon(%u) and "
4801 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4802 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4803 pfc_conf->fc.send_xon,
4804 pfc_conf->fc.mac_ctrl_frame_fwd);
4807 if (pfc_conf->fc.autoneg) {
4808 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4811 if (pfc_conf->fc.pause_time == 0) {
4812 hns3_err(hw, "Invalid pause time %d setting.",
4813 pfc_conf->fc.pause_time);
4817 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4818 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4819 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4820 "current_fc_status = %d", hw->current_fc_status);
4824 priority = pfc_conf->priority;
4825 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4826 if (hw->dcb_info.pfc_en & BIT(priority) &&
4827 hw->requested_mode == hw->current_mode &&
4828 pfc_conf->fc.pause_time == pf->pause_time)
4831 rte_spinlock_lock(&hw->lock);
4832 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4833 rte_spinlock_unlock(&hw->lock);
4839 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4841 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4842 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4843 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4846 rte_spinlock_lock(&hw->lock);
4847 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4848 dcb_info->nb_tcs = pf->local_max_tc;
4850 dcb_info->nb_tcs = 1;
4852 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4853 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4854 for (i = 0; i < dcb_info->nb_tcs; i++)
4855 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4857 for (i = 0; i < hw->num_tc; i++) {
4858 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4859 dcb_info->tc_queue.tc_txq[0][i].base =
4860 hw->tc_queue[i].tqp_offset;
4861 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4862 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4863 hw->tc_queue[i].tqp_count;
4865 rte_spinlock_unlock(&hw->lock);
4871 hns3_reinit_dev(struct hns3_adapter *hns)
4873 struct hns3_hw *hw = &hns->hw;
4876 ret = hns3_cmd_init(hw);
4878 hns3_err(hw, "Failed to init cmd: %d", ret);
4882 ret = hns3_reset_all_queues(hns);
4884 hns3_err(hw, "Failed to reset all queues: %d", ret);
4888 ret = hns3_init_hardware(hns);
4890 hns3_err(hw, "Failed to init hardware: %d", ret);
4894 ret = hns3_enable_hw_error_intr(hns, true);
4896 hns3_err(hw, "fail to enable hw error interrupts: %d",
4900 hns3_info(hw, "Reset done, driver initialization finished.");
4906 is_pf_reset_done(struct hns3_hw *hw)
4908 uint32_t val, reg, reg_bit;
4910 switch (hw->reset.level) {
4911 case HNS3_IMP_RESET:
4912 reg = HNS3_GLOBAL_RESET_REG;
4913 reg_bit = HNS3_IMP_RESET_BIT;
4915 case HNS3_GLOBAL_RESET:
4916 reg = HNS3_GLOBAL_RESET_REG;
4917 reg_bit = HNS3_GLOBAL_RESET_BIT;
4919 case HNS3_FUNC_RESET:
4920 reg = HNS3_FUN_RST_ING;
4921 reg_bit = HNS3_FUN_RST_ING_B;
4923 case HNS3_FLR_RESET:
4925 hns3_err(hw, "Wait for unsupported reset level: %d",
4929 val = hns3_read_dev(hw, reg);
4930 if (hns3_get_bit(val, reg_bit))
4937 hns3_is_reset_pending(struct hns3_adapter *hns)
4939 struct hns3_hw *hw = &hns->hw;
4940 enum hns3_reset_level reset;
4942 hns3_check_event_cause(hns, NULL);
4943 reset = hns3_get_reset_level(hns, &hw->reset.pending);
4944 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4945 hns3_warn(hw, "High level reset %d is pending", reset);
4948 reset = hns3_get_reset_level(hns, &hw->reset.request);
4949 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4950 hns3_warn(hw, "High level reset %d is request", reset);
4957 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4959 struct hns3_hw *hw = &hns->hw;
4960 struct hns3_wait_data *wait_data = hw->reset.wait_data;
4963 if (wait_data->result == HNS3_WAIT_SUCCESS)
4965 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4966 gettimeofday(&tv, NULL);
4967 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4968 tv.tv_sec, tv.tv_usec);
4970 } else if (wait_data->result == HNS3_WAIT_REQUEST)
4973 wait_data->hns = hns;
4974 wait_data->check_completion = is_pf_reset_done;
4975 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4976 HNS3_RESET_WAIT_MS + get_timeofday_ms();
4977 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4978 wait_data->count = HNS3_RESET_WAIT_CNT;
4979 wait_data->result = HNS3_WAIT_REQUEST;
4980 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4985 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4987 struct hns3_cmd_desc desc;
4988 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4990 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4991 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4992 req->fun_reset_vfid = func_id;
4994 return hns3_cmd_send(hw, &desc, 1);
4998 hns3_imp_reset_cmd(struct hns3_hw *hw)
5000 struct hns3_cmd_desc desc;
5002 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5003 desc.data[0] = 0xeedd;
5005 return hns3_cmd_send(hw, &desc, 1);
5009 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5011 struct hns3_hw *hw = &hns->hw;
5015 gettimeofday(&tv, NULL);
5016 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5017 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5018 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5019 tv.tv_sec, tv.tv_usec);
5023 switch (reset_level) {
5024 case HNS3_IMP_RESET:
5025 hns3_imp_reset_cmd(hw);
5026 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5027 tv.tv_sec, tv.tv_usec);
5029 case HNS3_GLOBAL_RESET:
5030 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5031 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5032 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5033 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5034 tv.tv_sec, tv.tv_usec);
5036 case HNS3_FUNC_RESET:
5037 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5038 tv.tv_sec, tv.tv_usec);
5039 /* schedule again to check later */
5040 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5041 hns3_schedule_reset(hns);
5044 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5047 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5050 static enum hns3_reset_level
5051 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5053 struct hns3_hw *hw = &hns->hw;
5054 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5056 /* Return the highest priority reset level amongst all */
5057 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5058 reset_level = HNS3_IMP_RESET;
5059 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5060 reset_level = HNS3_GLOBAL_RESET;
5061 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5062 reset_level = HNS3_FUNC_RESET;
5063 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5064 reset_level = HNS3_FLR_RESET;
5066 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5067 return HNS3_NONE_RESET;
5073 hns3_prepare_reset(struct hns3_adapter *hns)
5075 struct hns3_hw *hw = &hns->hw;
5079 switch (hw->reset.level) {
5080 case HNS3_FUNC_RESET:
5081 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5086 * After performaning pf reset, it is not necessary to do the
5087 * mailbox handling or send any command to firmware, because
5088 * any mailbox handling or command to firmware is only valid
5089 * after hns3_cmd_init is called.
5091 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5092 hw->reset.stats.request_cnt++;
5094 case HNS3_IMP_RESET:
5095 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5096 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5097 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5106 hns3_set_rst_done(struct hns3_hw *hw)
5108 struct hns3_pf_rst_done_cmd *req;
5109 struct hns3_cmd_desc desc;
5111 req = (struct hns3_pf_rst_done_cmd *)desc.data;
5112 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5113 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5114 return hns3_cmd_send(hw, &desc, 1);
5118 hns3_stop_service(struct hns3_adapter *hns)
5120 struct hns3_hw *hw = &hns->hw;
5121 struct rte_eth_dev *eth_dev;
5123 eth_dev = &rte_eth_devices[hw->data->port_id];
5124 if (hw->adapter_state == HNS3_NIC_STARTED)
5125 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5126 hw->mac.link_status = ETH_LINK_DOWN;
5128 hns3_set_rxtx_function(eth_dev);
5130 /* Disable datapath on secondary process. */
5131 hns3_mp_req_stop_rxtx(eth_dev);
5132 rte_delay_ms(hw->tqps_num);
5134 rte_spinlock_lock(&hw->lock);
5135 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5136 hw->adapter_state == HNS3_NIC_STOPPING) {
5138 hw->reset.mbuf_deferred_free = true;
5140 hw->reset.mbuf_deferred_free = false;
5143 * It is cumbersome for hardware to pick-and-choose entries for deletion
5144 * from table space. Hence, for function reset software intervention is
5145 * required to delete the entries
5147 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5148 hns3_configure_all_mc_mac_addr(hns, true);
5149 rte_spinlock_unlock(&hw->lock);
5155 hns3_start_service(struct hns3_adapter *hns)
5157 struct hns3_hw *hw = &hns->hw;
5158 struct rte_eth_dev *eth_dev;
5160 if (hw->reset.level == HNS3_IMP_RESET ||
5161 hw->reset.level == HNS3_GLOBAL_RESET)
5162 hns3_set_rst_done(hw);
5163 eth_dev = &rte_eth_devices[hw->data->port_id];
5164 hns3_set_rxtx_function(eth_dev);
5165 hns3_mp_req_start_rxtx(eth_dev);
5166 if (hw->adapter_state == HNS3_NIC_STARTED) {
5167 hns3_service_handler(eth_dev);
5169 /* Enable interrupt of all rx queues before enabling queues */
5170 hns3_dev_all_rx_queue_intr_enable(hw, true);
5172 * When finished the initialization, enable queues to receive
5173 * and transmit packets.
5175 hns3_enable_all_queues(hw, true);
5182 hns3_restore_conf(struct hns3_adapter *hns)
5184 struct hns3_hw *hw = &hns->hw;
5187 ret = hns3_configure_all_mac_addr(hns, false);
5191 ret = hns3_configure_all_mc_mac_addr(hns, false);
5195 ret = hns3_dev_promisc_restore(hns);
5199 ret = hns3_restore_vlan_table(hns);
5203 ret = hns3_restore_vlan_conf(hns);
5207 ret = hns3_restore_all_fdir_filter(hns);
5211 ret = hns3_restore_rx_interrupt(hw);
5215 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5216 ret = hns3_do_start(hns, false);
5219 hns3_info(hw, "hns3 dev restart successful!");
5220 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5221 hw->adapter_state = HNS3_NIC_CONFIGURED;
5225 hns3_configure_all_mc_mac_addr(hns, true);
5227 hns3_configure_all_mac_addr(hns, true);
5232 hns3_reset_service(void *param)
5234 struct hns3_adapter *hns = (struct hns3_adapter *)param;
5235 struct hns3_hw *hw = &hns->hw;
5236 enum hns3_reset_level reset_level;
5237 struct timeval tv_delta;
5238 struct timeval tv_start;
5244 * The interrupt is not triggered within the delay time.
5245 * The interrupt may have been lost. It is necessary to handle
5246 * the interrupt to recover from the error.
5248 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5249 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5250 hns3_err(hw, "Handling interrupts in delayed tasks");
5251 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5252 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5253 if (reset_level == HNS3_NONE_RESET) {
5254 hns3_err(hw, "No reset level is set, try IMP reset");
5255 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5258 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5261 * Check if there is any ongoing reset in the hardware. This status can
5262 * be checked from reset_pending. If there is then, we need to wait for
5263 * hardware to complete reset.
5264 * a. If we are able to figure out in reasonable time that hardware
5265 * has fully resetted then, we can proceed with driver, client
5267 * b. else, we can come back later to check this status so re-sched
5270 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5271 if (reset_level != HNS3_NONE_RESET) {
5272 gettimeofday(&tv_start, NULL);
5273 ret = hns3_reset_process(hns, reset_level);
5274 gettimeofday(&tv, NULL);
5275 timersub(&tv, &tv_start, &tv_delta);
5276 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5277 tv_delta.tv_usec / USEC_PER_MSEC;
5278 if (msec > HNS3_RESET_PROCESS_MS)
5279 hns3_err(hw, "%d handle long time delta %" PRIx64
5280 " ms time=%ld.%.6ld",
5281 hw->reset.level, msec,
5282 tv.tv_sec, tv.tv_usec);
5287 /* Check if we got any *new* reset requests to be honored */
5288 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5289 if (reset_level != HNS3_NONE_RESET)
5290 hns3_msix_process(hns, reset_level);
5293 static const struct eth_dev_ops hns3_eth_dev_ops = {
5294 .dev_start = hns3_dev_start,
5295 .dev_stop = hns3_dev_stop,
5296 .dev_close = hns3_dev_close,
5297 .promiscuous_enable = hns3_dev_promiscuous_enable,
5298 .promiscuous_disable = hns3_dev_promiscuous_disable,
5299 .allmulticast_enable = hns3_dev_allmulticast_enable,
5300 .allmulticast_disable = hns3_dev_allmulticast_disable,
5301 .mtu_set = hns3_dev_mtu_set,
5302 .stats_get = hns3_stats_get,
5303 .stats_reset = hns3_stats_reset,
5304 .xstats_get = hns3_dev_xstats_get,
5305 .xstats_get_names = hns3_dev_xstats_get_names,
5306 .xstats_reset = hns3_dev_xstats_reset,
5307 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
5308 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5309 .dev_infos_get = hns3_dev_infos_get,
5310 .fw_version_get = hns3_fw_version_get,
5311 .rx_queue_setup = hns3_rx_queue_setup,
5312 .tx_queue_setup = hns3_tx_queue_setup,
5313 .rx_queue_release = hns3_dev_rx_queue_release,
5314 .tx_queue_release = hns3_dev_tx_queue_release,
5315 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
5316 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
5317 .dev_configure = hns3_dev_configure,
5318 .flow_ctrl_get = hns3_flow_ctrl_get,
5319 .flow_ctrl_set = hns3_flow_ctrl_set,
5320 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5321 .mac_addr_add = hns3_add_mac_addr,
5322 .mac_addr_remove = hns3_remove_mac_addr,
5323 .mac_addr_set = hns3_set_default_mac_addr,
5324 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
5325 .link_update = hns3_dev_link_update,
5326 .rss_hash_update = hns3_dev_rss_hash_update,
5327 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
5328 .reta_update = hns3_dev_rss_reta_update,
5329 .reta_query = hns3_dev_rss_reta_query,
5330 .filter_ctrl = hns3_dev_filter_ctrl,
5331 .vlan_filter_set = hns3_vlan_filter_set,
5332 .vlan_tpid_set = hns3_vlan_tpid_set,
5333 .vlan_offload_set = hns3_vlan_offload_set,
5334 .vlan_pvid_set = hns3_vlan_pvid_set,
5335 .get_reg = hns3_get_regs,
5336 .get_dcb_info = hns3_get_dcb_info,
5337 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5340 static const struct hns3_reset_ops hns3_reset_ops = {
5341 .reset_service = hns3_reset_service,
5342 .stop_service = hns3_stop_service,
5343 .prepare_reset = hns3_prepare_reset,
5344 .wait_hardware_ready = hns3_wait_hardware_ready,
5345 .reinit_dev = hns3_reinit_dev,
5346 .restore_conf = hns3_restore_conf,
5347 .start_service = hns3_start_service,
5351 hns3_dev_init(struct rte_eth_dev *eth_dev)
5353 struct rte_device *dev = eth_dev->device;
5354 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5355 struct hns3_adapter *hns = eth_dev->data->dev_private;
5356 struct hns3_hw *hw = &hns->hw;
5357 uint16_t device_id = pci_dev->id.device_id;
5361 PMD_INIT_FUNC_TRACE();
5363 /* Get PCI revision id */
5364 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
5365 HNS3_PCI_REVISION_ID);
5366 if (ret != HNS3_PCI_REVISION_ID_LEN) {
5367 PMD_INIT_LOG(ERR, "Failed to read pci revision id, ret = %d",
5371 hw->revision = revision;
5373 eth_dev->process_private = (struct hns3_process_private *)
5374 rte_zmalloc_socket("hns3_filter_list",
5375 sizeof(struct hns3_process_private),
5376 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5377 if (eth_dev->process_private == NULL) {
5378 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5381 /* initialize flow filter lists */
5382 hns3_filterlist_init(eth_dev);
5384 hns3_set_rxtx_function(eth_dev);
5385 eth_dev->dev_ops = &hns3_eth_dev_ops;
5386 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5387 hns3_mp_init_secondary();
5388 hw->secondary_cnt++;
5392 hns3_mp_init_primary();
5393 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5395 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5396 device_id == HNS3_DEV_ID_50GE_RDMA ||
5397 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5398 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5401 hw->data = eth_dev->data;
5404 * Set default max packet size according to the mtu
5405 * default vale in DPDK frame.
5407 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5409 ret = hns3_reset_init(hw);
5411 goto err_init_reset;
5412 hw->reset.ops = &hns3_reset_ops;
5414 ret = hns3_init_pf(eth_dev);
5416 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5420 /* Allocate memory for storing MAC addresses */
5421 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5422 sizeof(struct rte_ether_addr) *
5423 HNS3_UC_MACADDR_NUM, 0);
5424 if (eth_dev->data->mac_addrs == NULL) {
5425 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5426 "to store MAC addresses",
5427 sizeof(struct rte_ether_addr) *
5428 HNS3_UC_MACADDR_NUM);
5430 goto err_rte_zmalloc;
5433 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5434 ð_dev->data->mac_addrs[0]);
5436 hw->adapter_state = HNS3_NIC_INITIALIZED;
5438 * Pass the information to the rte_eth_dev_close() that it should also
5439 * release the private port resources.
5441 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5443 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5444 hns3_err(hw, "Reschedule reset service after dev_init");
5445 hns3_schedule_reset(hns);
5447 /* IMP will wait ready flag before reset */
5448 hns3_notify_reset_ready(hw, false);
5451 hns3_info(hw, "hns3 dev initialization successful!");
5455 hns3_uninit_pf(eth_dev);
5458 rte_free(hw->reset.wait_data);
5460 eth_dev->dev_ops = NULL;
5461 eth_dev->rx_pkt_burst = NULL;
5462 eth_dev->tx_pkt_burst = NULL;
5463 eth_dev->tx_pkt_prepare = NULL;
5464 rte_free(eth_dev->process_private);
5465 eth_dev->process_private = NULL;
5470 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5472 struct hns3_adapter *hns = eth_dev->data->dev_private;
5473 struct hns3_hw *hw = &hns->hw;
5475 PMD_INIT_FUNC_TRACE();
5477 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5480 eth_dev->dev_ops = NULL;
5481 eth_dev->rx_pkt_burst = NULL;
5482 eth_dev->tx_pkt_burst = NULL;
5483 eth_dev->tx_pkt_prepare = NULL;
5484 if (hw->adapter_state < HNS3_NIC_CLOSING)
5485 hns3_dev_close(eth_dev);
5487 hw->adapter_state = HNS3_NIC_REMOVED;
5492 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5493 struct rte_pci_device *pci_dev)
5495 return rte_eth_dev_pci_generic_probe(pci_dev,
5496 sizeof(struct hns3_adapter),
5501 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5503 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5506 static const struct rte_pci_id pci_id_hns3_map[] = {
5507 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5508 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5509 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5510 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5511 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5512 { .vendor_id = 0, /* sentinel */ },
5515 static struct rte_pci_driver rte_hns3_pmd = {
5516 .id_table = pci_id_hns3_map,
5517 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5518 .probe = eth_hns3_pci_probe,
5519 .remove = eth_hns3_pci_remove,
5522 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5523 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5524 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5525 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
5526 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);