drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9
  10 #include "hns3_ethdev.h"
  11 #include "hns3_common.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18
  19 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  20 #define HNS3_SERVICE_QUICK_INTERVAL     10
  21 #define HNS3_INVALID_PVID               0xFFFF
  22
  23 #define HNS3_FILTER_TYPE_VF             0
  24 #define HNS3_FILTER_TYPE_PORT           1
  25 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  26 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  27 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  28 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  29 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  30 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  31                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  32 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  33                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  34
  35 /* Reset related Registers */
  36 #define HNS3_GLOBAL_RESET_BIT           0
  37 #define HNS3_CORE_RESET_BIT             1
  38 #define HNS3_IMP_RESET_BIT              2
  39 #define HNS3_FUN_RST_ING_B              0
  40
  41 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  42 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  43 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  44 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  45
  46 #define HNS3_RESET_WAIT_MS      100
  47 #define HNS3_RESET_WAIT_CNT     200
  48
  49 /* FEC mode order defined in HNS3 hardware */
  50 #define HNS3_HW_FEC_MODE_NOFEC  0
  51 #define HNS3_HW_FEC_MODE_BASER  1
  52 #define HNS3_HW_FEC_MODE_RS     2
  53
  54 enum hns3_evt_cause {
  55         HNS3_VECTOR0_EVENT_RST,
  56         HNS3_VECTOR0_EVENT_MBX,
  57         HNS3_VECTOR0_EVENT_ERR,
  58         HNS3_VECTOR0_EVENT_PTP,
  59         HNS3_VECTOR0_EVENT_OTHER,
  60 };
  61
  62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  63         { RTE_ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  64                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  66
  67         { RTE_ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  71
  72         { RTE_ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  75
  76         { RTE_ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  80
  81         { RTE_ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  82                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  84
  85         { RTE_ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  88 };
  89
  90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  91                                                  uint64_t *levels);
  92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  94                                     int on);
  95 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  96 static bool hns3_update_link_status(struct hns3_hw *hw);
  97
  98 static int hns3_add_mc_mac_addr(struct hns3_hw *hw,
  99                                 struct rte_ether_addr *mac_addr);
 100 static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 101                                    struct rte_ether_addr *mac_addr);
 102 static int hns3_restore_fec(struct hns3_hw *hw);
 103 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 104 static int hns3_do_stop(struct hns3_adapter *hns);
 105 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
 106 static int hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable);
 107
 108
 109 static void
 110 hns3_pf_disable_irq0(struct hns3_hw *hw)
 111 {
 112         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 113 }
 114
 115 static void
 116 hns3_pf_enable_irq0(struct hns3_hw *hw)
 117 {
 118         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 119 }
 120
 121 static enum hns3_evt_cause
 122 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 123                           uint32_t *vec_val)
 124 {
 125         struct hns3_hw *hw = &hns->hw;
 126
 127         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 128         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 129         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 130         if (!is_delay) {
 131                 hw->reset.stats.imp_cnt++;
 132                 hns3_warn(hw, "IMP reset detected, clear reset status");
 133         } else {
 134                 hns3_schedule_delayed_reset(hns);
 135                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 136         }
 137
 138         return HNS3_VECTOR0_EVENT_RST;
 139 }
 140
 141 static enum hns3_evt_cause
 142 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 143                              uint32_t *vec_val)
 144 {
 145         struct hns3_hw *hw = &hns->hw;
 146
 147         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 148         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 149         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 150         if (!is_delay) {
 151                 hw->reset.stats.global_cnt++;
 152                 hns3_warn(hw, "Global reset detected, clear reset status");
 153         } else {
 154                 hns3_schedule_delayed_reset(hns);
 155                 hns3_warn(hw,
 156                           "Global reset detected, don't clear reset status");
 157         }
 158
 159         return HNS3_VECTOR0_EVENT_RST;
 160 }
 161
 162 static enum hns3_evt_cause
 163 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 164 {
 165         struct hns3_hw *hw = &hns->hw;
 166         uint32_t vector0_int_stats;
 167         uint32_t cmdq_src_val;
 168         uint32_t hw_err_src_reg;
 169         uint32_t val;
 170         enum hns3_evt_cause ret;
 171         bool is_delay;
 172
 173         /* fetch the events from their corresponding regs */
 174         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 175         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 176         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 177
 178         is_delay = clearval == NULL ? true : false;
 179         /*
 180          * Assumption: If by any chance reset and mailbox events are reported
 181          * together then we will only process reset event and defer the
 182          * processing of the mailbox events. Since, we would have not cleared
 183          * RX CMDQ event this time we would receive again another interrupt
 184          * from H/W just for the mailbox.
 185          */
 186         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 187                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 188                 goto out;
 189         }
 190
 191         /* Global reset */
 192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 193                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 194                 goto out;
 195         }
 196
 197         /* Check for vector0 1588 event source */
 198         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
 199                 val = BIT(HNS3_VECTOR0_1588_INT_B);
 200                 ret = HNS3_VECTOR0_EVENT_PTP;
 201                 goto out;
 202         }
 203
 204         /* check for vector0 msix event source */
 205         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 206             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 207                 val = vector0_int_stats | hw_err_src_reg;
 208                 ret = HNS3_VECTOR0_EVENT_ERR;
 209                 goto out;
 210         }
 211
 212         /* check for vector0 mailbox(=CMDQ RX) event source */
 213         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 214                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 215                 val = cmdq_src_val;
 216                 ret = HNS3_VECTOR0_EVENT_MBX;
 217                 goto out;
 218         }
 219
 220         val = vector0_int_stats;
 221         ret = HNS3_VECTOR0_EVENT_OTHER;
 222 out:
 223
 224         if (clearval)
 225                 *clearval = val;
 226         return ret;
 227 }
 228
 229 static bool
 230 hns3_is_1588_event_type(uint32_t event_type)
 231 {
 232         return (event_type == HNS3_VECTOR0_EVENT_PTP);
 233 }
 234
 235 static void
 236 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 237 {
 238         if (event_type == HNS3_VECTOR0_EVENT_RST ||
 239             hns3_is_1588_event_type(event_type))
 240                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 241         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 242                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 243 }
 244
 245 static void
 246 hns3_clear_all_event_cause(struct hns3_hw *hw)
 247 {
 248         uint32_t vector0_int_stats;
 249
 250         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 251         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 252                 hns3_warn(hw, "Probe during IMP reset interrupt");
 253
 254         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 255                 hns3_warn(hw, "Probe during Global reset interrupt");
 256
 257         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 258                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 259                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 260                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 261         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 262         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
 263                                 BIT(HNS3_VECTOR0_1588_INT_B));
 264 }
 265
 266 static void
 267 hns3_handle_mac_tnl(struct hns3_hw *hw)
 268 {
 269         struct hns3_cmd_desc desc;
 270         uint32_t status;
 271         int ret;
 272
 273         /* query and clear mac tnl interrupt */
 274         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 275         ret = hns3_cmd_send(hw, &desc, 1);
 276         if (ret) {
 277                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 278                 return;
 279         }
 280
 281         status = rte_le_to_cpu_32(desc.data[0]);
 282         if (status) {
 283                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 284                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 285                                           false);
 286                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 287                 ret = hns3_cmd_send(hw, &desc, 1);
 288                 if (ret)
 289                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 290                                  ret);
 291         }
 292 }
 293
 294 static void
 295 hns3_interrupt_handler(void *param)
 296 {
 297         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 298         struct hns3_adapter *hns = dev->data->dev_private;
 299         struct hns3_hw *hw = &hns->hw;
 300         enum hns3_evt_cause event_cause;
 301         uint32_t clearval = 0;
 302         uint32_t vector0_int;
 303         uint32_t ras_int;
 304         uint32_t cmdq_int;
 305
 306         /* Disable interrupt */
 307         hns3_pf_disable_irq0(hw);
 308
 309         event_cause = hns3_check_event_cause(hns, &clearval);
 310         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 311         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 312         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 313         hns3_clear_event_cause(hw, event_cause, clearval);
 314         /* vector 0 interrupt is shared with reset and mailbox source events. */
 315         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 316                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 317                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 318                           vector0_int, ras_int, cmdq_int);
 319                 hns3_handle_mac_tnl(hw);
 320                 hns3_handle_error(hns);
 321         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 322                 hns3_warn(hw, "received reset interrupt");
 323                 hns3_schedule_reset(hns);
 324         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 325                 hns3_dev_handle_mbx_msg(hw);
 326         } else {
 327                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 328                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 329                           vector0_int, ras_int, cmdq_int);
 330         }
 331
 332         /* Enable interrupt if it is not cause by reset */
 333         hns3_pf_enable_irq0(hw);
 334 }
 335
 336 static int
 337 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 338 {
 339 #define HNS3_VLAN_ID_OFFSET_STEP        160
 340 #define HNS3_VLAN_BYTE_SIZE             8
 341         struct hns3_vlan_filter_pf_cfg_cmd *req;
 342         struct hns3_hw *hw = &hns->hw;
 343         uint8_t vlan_offset_byte_val;
 344         struct hns3_cmd_desc desc;
 345         uint8_t vlan_offset_byte;
 346         uint8_t vlan_offset_base;
 347         int ret;
 348
 349         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 350
 351         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 352         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 353                            HNS3_VLAN_BYTE_SIZE;
 354         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 355
 356         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 357         req->vlan_offset = vlan_offset_base;
 358         req->vlan_cfg = on ? 0 : 1;
 359         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 360
 361         ret = hns3_cmd_send(hw, &desc, 1);
 362         if (ret)
 363                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 364                          vlan_id, ret);
 365
 366         return ret;
 367 }
 368
 369 static void
 370 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 371 {
 372         struct hns3_user_vlan_table *vlan_entry;
 373         struct hns3_pf *pf = &hns->pf;
 374
 375         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 376                 if (vlan_entry->vlan_id == vlan_id) {
 377                         if (vlan_entry->hd_tbl_status)
 378                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 379                         LIST_REMOVE(vlan_entry, next);
 380                         rte_free(vlan_entry);
 381                         break;
 382                 }
 383         }
 384 }
 385
 386 static void
 387 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 388                         bool writen_to_tbl)
 389 {
 390         struct hns3_user_vlan_table *vlan_entry;
 391         struct hns3_hw *hw = &hns->hw;
 392         struct hns3_pf *pf = &hns->pf;
 393
 394         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 395                 if (vlan_entry->vlan_id == vlan_id)
 396                         return;
 397         }
 398
 399         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 400         if (vlan_entry == NULL) {
 401                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 402                 return;
 403         }
 404
 405         vlan_entry->hd_tbl_status = writen_to_tbl;
 406         vlan_entry->vlan_id = vlan_id;
 407
 408         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 409 }
 410
 411 static int
 412 hns3_restore_vlan_table(struct hns3_adapter *hns)
 413 {
 414         struct hns3_user_vlan_table *vlan_entry;
 415         struct hns3_hw *hw = &hns->hw;
 416         struct hns3_pf *pf = &hns->pf;
 417         uint16_t vlan_id;
 418         int ret = 0;
 419
 420         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 421                 return hns3_vlan_pvid_configure(hns,
 422                                                 hw->port_base_vlan_cfg.pvid, 1);
 423
 424         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 425                 if (vlan_entry->hd_tbl_status) {
 426                         vlan_id = vlan_entry->vlan_id;
 427                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 428                         if (ret)
 429                                 break;
 430                 }
 431         }
 432
 433         return ret;
 434 }
 435
 436 static int
 437 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 438 {
 439         struct hns3_hw *hw = &hns->hw;
 440         bool writen_to_tbl = false;
 441         int ret = 0;
 442
 443         /*
 444          * When vlan filter is enabled, hardware regards packets without vlan
 445          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 446          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 447          */
 448         if (on == 0 && vlan_id == 0)
 449                 return 0;
 450
 451         /*
 452          * When port base vlan enabled, we use port base vlan as the vlan
 453          * filter condition. In this case, we don't update vlan filter table
 454          * when user add new vlan or remove exist vlan, just update the
 455          * vlan list. The vlan id in vlan list will be written in vlan filter
 456          * table until port base vlan disabled
 457          */
 458         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 459                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 460                 writen_to_tbl = true;
 461         }
 462
 463         if (ret == 0) {
 464                 if (on)
 465                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 466                 else
 467                         hns3_rm_dev_vlan_table(hns, vlan_id);
 468         }
 469         return ret;
 470 }
 471
 472 static int
 473 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 474 {
 475         struct hns3_adapter *hns = dev->data->dev_private;
 476         struct hns3_hw *hw = &hns->hw;
 477         int ret;
 478
 479         rte_spinlock_lock(&hw->lock);
 480         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 481         rte_spinlock_unlock(&hw->lock);
 482         return ret;
 483 }
 484
 485 static int
 486 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 487                          uint16_t tpid)
 488 {
 489         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 490         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 491         struct hns3_hw *hw = &hns->hw;
 492         struct hns3_cmd_desc desc;
 493         int ret;
 494
 495         if ((vlan_type != RTE_ETH_VLAN_TYPE_INNER &&
 496              vlan_type != RTE_ETH_VLAN_TYPE_OUTER)) {
 497                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 498                 return -EINVAL;
 499         }
 500
 501         if (tpid != RTE_ETHER_TYPE_VLAN) {
 502                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 503                 return -EINVAL;
 504         }
 505
 506         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 507         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 508
 509         if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) {
 510                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 511                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 512         } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) {
 513                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 514                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 515                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 516                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 517         }
 518
 519         ret = hns3_cmd_send(hw, &desc, 1);
 520         if (ret) {
 521                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 522                          ret);
 523                 return ret;
 524         }
 525
 526         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 527
 528         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 529         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 530         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 531
 532         ret = hns3_cmd_send(hw, &desc, 1);
 533         if (ret)
 534                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 535                          ret);
 536         return ret;
 537 }
 538
 539 static int
 540 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 541                    uint16_t tpid)
 542 {
 543         struct hns3_adapter *hns = dev->data->dev_private;
 544         struct hns3_hw *hw = &hns->hw;
 545         int ret;
 546
 547         rte_spinlock_lock(&hw->lock);
 548         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 549         rte_spinlock_unlock(&hw->lock);
 550         return ret;
 551 }
 552
 553 static int
 554 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 555                              struct hns3_rx_vtag_cfg *vcfg)
 556 {
 557         struct hns3_vport_vtag_rx_cfg_cmd *req;
 558         struct hns3_hw *hw = &hns->hw;
 559         struct hns3_cmd_desc desc;
 560         uint16_t vport_id;
 561         uint8_t bitmap;
 562         int ret;
 563
 564         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 565
 566         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 567         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 568                      vcfg->strip_tag1_en ? 1 : 0);
 569         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 570                      vcfg->strip_tag2_en ? 1 : 0);
 571         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 572                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 573         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 574                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 575
 576         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 577         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 578                      vcfg->strip_tag1_discard_en ? 1 : 0);
 579         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 580                      vcfg->strip_tag2_discard_en ? 1 : 0);
 581         /*
 582          * In current version VF is not supported when PF is driven by DPDK
 583          * driver, just need to configure parameters for PF vport.
 584          */
 585         vport_id = HNS3_PF_FUNC_ID;
 586         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 587         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 588         req->vf_bitmap[req->vf_offset] = bitmap;
 589
 590         ret = hns3_cmd_send(hw, &desc, 1);
 591         if (ret)
 592                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 593         return ret;
 594 }
 595
 596 static void
 597 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 598                            struct hns3_rx_vtag_cfg *vcfg)
 599 {
 600         struct hns3_pf *pf = &hns->pf;
 601         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 602 }
 603
 604 static void
 605 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 606                            struct hns3_tx_vtag_cfg *vcfg)
 607 {
 608         struct hns3_pf *pf = &hns->pf;
 609         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 610 }
 611
 612 static int
 613 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 614 {
 615         struct hns3_rx_vtag_cfg rxvlan_cfg;
 616         struct hns3_hw *hw = &hns->hw;
 617         int ret;
 618
 619         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 620                 rxvlan_cfg.strip_tag1_en = false;
 621                 rxvlan_cfg.strip_tag2_en = enable;
 622                 rxvlan_cfg.strip_tag2_discard_en = false;
 623         } else {
 624                 rxvlan_cfg.strip_tag1_en = enable;
 625                 rxvlan_cfg.strip_tag2_en = true;
 626                 rxvlan_cfg.strip_tag2_discard_en = true;
 627         }
 628
 629         rxvlan_cfg.strip_tag1_discard_en = false;
 630         rxvlan_cfg.vlan1_vlan_prionly = false;
 631         rxvlan_cfg.vlan2_vlan_prionly = false;
 632         rxvlan_cfg.rx_vlan_offload_en = enable;
 633
 634         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 635         if (ret) {
 636                 hns3_err(hw, "%s strip rx vtag failed, ret = %d.",
 637                                 enable ? "enable" : "disable", ret);
 638                 return ret;
 639         }
 640
 641         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 642
 643         return ret;
 644 }
 645
 646 static int
 647 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 648                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 649 {
 650         struct hns3_vlan_filter_ctrl_cmd *req;
 651         struct hns3_cmd_desc desc;
 652         int ret;
 653
 654         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 655
 656         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 657         req->vlan_type = vlan_type;
 658         req->vlan_fe = filter_en ? fe_type : 0;
 659         req->vf_id = vf_id;
 660
 661         ret = hns3_cmd_send(hw, &desc, 1);
 662         if (ret)
 663                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 664
 665         return ret;
 666 }
 667
 668 static int
 669 hns3_vlan_filter_init(struct hns3_adapter *hns)
 670 {
 671         struct hns3_hw *hw = &hns->hw;
 672         int ret;
 673
 674         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 675                                         HNS3_FILTER_FE_EGRESS, false,
 676                                         HNS3_PF_FUNC_ID);
 677         if (ret) {
 678                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 679                 return ret;
 680         }
 681
 682         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 683                                         HNS3_FILTER_FE_INGRESS, false,
 684                                         HNS3_PF_FUNC_ID);
 685         if (ret)
 686                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 687
 688         return ret;
 689 }
 690
 691 static int
 692 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 693 {
 694         struct hns3_hw *hw = &hns->hw;
 695         int ret;
 696
 697         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 698                                         HNS3_FILTER_FE_INGRESS, enable,
 699                                         HNS3_PF_FUNC_ID);
 700         if (ret)
 701                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 702                          enable ? "enable" : "disable", ret);
 703
 704         return ret;
 705 }
 706
 707 static int
 708 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 709 {
 710         struct hns3_adapter *hns = dev->data->dev_private;
 711         struct hns3_hw *hw = &hns->hw;
 712         struct rte_eth_rxmode *rxmode;
 713         unsigned int tmp_mask;
 714         bool enable;
 715         int ret = 0;
 716
 717         rte_spinlock_lock(&hw->lock);
 718         rxmode = &dev->data->dev_conf.rxmode;
 719         tmp_mask = (unsigned int)mask;
 720         if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
 721                 /* ignore vlan filter configuration during promiscuous mode */
 722                 if (!dev->data->promiscuous) {
 723                         /* Enable or disable VLAN filter */
 724                         enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ?
 725                                  true : false;
 726
 727                         ret = hns3_enable_vlan_filter(hns, enable);
 728                         if (ret) {
 729                                 rte_spinlock_unlock(&hw->lock);
 730                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 731                                          enable ? "enable" : "disable", ret);
 732                                 return ret;
 733                         }
 734                 }
 735         }
 736
 737         if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
 738                 /* Enable or disable VLAN stripping */
 739                 enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ?
 740                     true : false;
 741
 742                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 743                 if (ret) {
 744                         rte_spinlock_unlock(&hw->lock);
 745                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 746                                  enable ? "enable" : "disable", ret);
 747                         return ret;
 748                 }
 749         }
 750
 751         rte_spinlock_unlock(&hw->lock);
 752
 753         return ret;
 754 }
 755
 756 static int
 757 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 758                              struct hns3_tx_vtag_cfg *vcfg)
 759 {
 760         struct hns3_vport_vtag_tx_cfg_cmd *req;
 761         struct hns3_cmd_desc desc;
 762         struct hns3_hw *hw = &hns->hw;
 763         uint16_t vport_id;
 764         uint8_t bitmap;
 765         int ret;
 766
 767         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 768
 769         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 770         req->def_vlan_tag1 = vcfg->default_tag1;
 771         req->def_vlan_tag2 = vcfg->default_tag2;
 772         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 773                      vcfg->accept_tag1 ? 1 : 0);
 774         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 775                      vcfg->accept_untag1 ? 1 : 0);
 776         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 777                      vcfg->accept_tag2 ? 1 : 0);
 778         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 779                      vcfg->accept_untag2 ? 1 : 0);
 780         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 781                      vcfg->insert_tag1_en ? 1 : 0);
 782         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 783                      vcfg->insert_tag2_en ? 1 : 0);
 784         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 785
 786         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 787         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 788                      vcfg->tag_shift_mode_en ? 1 : 0);
 789
 790         /*
 791          * In current version VF is not supported when PF is driven by DPDK
 792          * driver, just need to configure parameters for PF vport.
 793          */
 794         vport_id = HNS3_PF_FUNC_ID;
 795         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 796         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 797         req->vf_bitmap[req->vf_offset] = bitmap;
 798
 799         ret = hns3_cmd_send(hw, &desc, 1);
 800         if (ret)
 801                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 802
 803         return ret;
 804 }
 805
 806 static int
 807 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 808                      uint16_t pvid)
 809 {
 810         struct hns3_hw *hw = &hns->hw;
 811         struct hns3_tx_vtag_cfg txvlan_cfg;
 812         int ret;
 813
 814         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 815                 txvlan_cfg.accept_tag1 = true;
 816                 txvlan_cfg.insert_tag1_en = false;
 817                 txvlan_cfg.default_tag1 = 0;
 818         } else {
 819                 txvlan_cfg.accept_tag1 =
 820                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 821                 txvlan_cfg.insert_tag1_en = true;
 822                 txvlan_cfg.default_tag1 = pvid;
 823         }
 824
 825         txvlan_cfg.accept_untag1 = true;
 826         txvlan_cfg.accept_tag2 = true;
 827         txvlan_cfg.accept_untag2 = true;
 828         txvlan_cfg.insert_tag2_en = false;
 829         txvlan_cfg.default_tag2 = 0;
 830         txvlan_cfg.tag_shift_mode_en = true;
 831
 832         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 833         if (ret) {
 834                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 835                          ret);
 836                 return ret;
 837         }
 838
 839         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 840         return ret;
 841 }
 842
 843
 844 static void
 845 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 846 {
 847         struct hns3_user_vlan_table *vlan_entry;
 848         struct hns3_pf *pf = &hns->pf;
 849
 850         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 851                 if (vlan_entry->hd_tbl_status) {
 852                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 853                         vlan_entry->hd_tbl_status = false;
 854                 }
 855         }
 856
 857         if (is_del_list) {
 858                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 859                 while (vlan_entry) {
 860                         LIST_REMOVE(vlan_entry, next);
 861                         rte_free(vlan_entry);
 862                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 863                 }
 864         }
 865 }
 866
 867 static void
 868 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 869 {
 870         struct hns3_user_vlan_table *vlan_entry;
 871         struct hns3_pf *pf = &hns->pf;
 872
 873         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 874                 if (!vlan_entry->hd_tbl_status) {
 875                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 876                         vlan_entry->hd_tbl_status = true;
 877                 }
 878         }
 879 }
 880
 881 static void
 882 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 883 {
 884         struct hns3_hw *hw = &hns->hw;
 885         int ret;
 886
 887         hns3_rm_all_vlan_table(hns, true);
 888         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 889                 ret = hns3_set_port_vlan_filter(hns,
 890                                                 hw->port_base_vlan_cfg.pvid, 0);
 891                 if (ret) {
 892                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 893                                  ret);
 894                         return;
 895                 }
 896         }
 897 }
 898
 899 static int
 900 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 901                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 902 {
 903         struct hns3_hw *hw = &hns->hw;
 904         uint16_t old_pvid;
 905         int ret;
 906
 907         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 908                 old_pvid = hw->port_base_vlan_cfg.pvid;
 909                 if (old_pvid != HNS3_INVALID_PVID) {
 910                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 911                         if (ret) {
 912                                 hns3_err(hw, "failed to remove old pvid %u, "
 913                                                 "ret = %d", old_pvid, ret);
 914                                 return ret;
 915                         }
 916                 }
 917
 918                 hns3_rm_all_vlan_table(hns, false);
 919                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 920                 if (ret) {
 921                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 922                                         new_pvid, ret);
 923                         return ret;
 924                 }
 925         } else {
 926                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 927                 if (ret) {
 928                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 929                                         new_pvid, ret);
 930                         return ret;
 931                 }
 932
 933                 hns3_add_all_vlan_table(hns);
 934         }
 935         return 0;
 936 }
 937
 938 static int
 939 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 940 {
 941         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 942         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 943         bool rx_strip_en;
 944         int ret;
 945
 946         rx_strip_en = old_cfg->rx_vlan_offload_en;
 947         if (on) {
 948                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 949                 rx_vlan_cfg.strip_tag2_en = true;
 950                 rx_vlan_cfg.strip_tag2_discard_en = true;
 951         } else {
 952                 rx_vlan_cfg.strip_tag1_en = false;
 953                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 954                 rx_vlan_cfg.strip_tag2_discard_en = false;
 955         }
 956         rx_vlan_cfg.strip_tag1_discard_en = false;
 957         rx_vlan_cfg.vlan1_vlan_prionly = false;
 958         rx_vlan_cfg.vlan2_vlan_prionly = false;
 959         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 960
 961         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 962         if (ret)
 963                 return ret;
 964
 965         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 966         return ret;
 967 }
 968
 969 static int
 970 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 971 {
 972         struct hns3_hw *hw = &hns->hw;
 973         uint16_t port_base_vlan_state;
 974         int ret, err;
 975
 976         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 977                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 978                         hns3_warn(hw, "Invalid operation! As current pvid set "
 979                                   "is %u, disable pvid %u is invalid",
 980                                   hw->port_base_vlan_cfg.pvid, pvid);
 981                 return 0;
 982         }
 983
 984         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 985                                     HNS3_PORT_BASE_VLAN_DISABLE;
 986         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 987         if (ret) {
 988                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 989                          ret);
 990                 return ret;
 991         }
 992
 993         ret = hns3_en_pvid_strip(hns, on);
 994         if (ret) {
 995                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 996                          "ret = %d", ret);
 997                 goto pvid_vlan_strip_fail;
 998         }
 999
1000         if (pvid == HNS3_INVALID_PVID)
1001                 goto out;
1002         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1003         if (ret) {
1004                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1005                          ret);
1006                 goto vlan_filter_set_fail;
1007         }
1008
1009 out:
1010         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1011         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1012         return ret;
1013
1014 vlan_filter_set_fail:
1015         err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1016                                         HNS3_PORT_BASE_VLAN_ENABLE);
1017         if (err)
1018                 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1019
1020 pvid_vlan_strip_fail:
1021         err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1022                                         hw->port_base_vlan_cfg.pvid);
1023         if (err)
1024                 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1025
1026         return ret;
1027 }
1028
1029 static int
1030 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1031 {
1032         struct hns3_adapter *hns = dev->data->dev_private;
1033         struct hns3_hw *hw = &hns->hw;
1034         bool pvid_en_state_change;
1035         uint16_t pvid_state;
1036         int ret;
1037
1038         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1039                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1040                          RTE_ETHER_MAX_VLAN_ID);
1041                 return -EINVAL;
1042         }
1043
1044         /*
1045          * If PVID configuration state change, should refresh the PVID
1046          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1047          */
1048         pvid_state = hw->port_base_vlan_cfg.state;
1049         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1050             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1051                 pvid_en_state_change = false;
1052         else
1053                 pvid_en_state_change = true;
1054
1055         rte_spinlock_lock(&hw->lock);
1056         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1057         rte_spinlock_unlock(&hw->lock);
1058         if (ret)
1059                 return ret;
1060         /*
1061          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1062          * need be processed by PMD driver.
1063          */
1064         if (pvid_en_state_change &&
1065             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1066                 hns3_update_all_queues_pvid_proc_en(hw);
1067
1068         return 0;
1069 }
1070
1071 static int
1072 hns3_default_vlan_config(struct hns3_adapter *hns)
1073 {
1074         struct hns3_hw *hw = &hns->hw;
1075         int ret;
1076
1077         /*
1078          * When vlan filter is enabled, hardware regards packets without vlan
1079          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1080          * table, packets without vlan won't be received. So, add vlan 0 as
1081          * the default vlan.
1082          */
1083         ret = hns3_vlan_filter_configure(hns, 0, 1);
1084         if (ret)
1085                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1086         return ret;
1087 }
1088
1089 static int
1090 hns3_init_vlan_config(struct hns3_adapter *hns)
1091 {
1092         struct hns3_hw *hw = &hns->hw;
1093         int ret;
1094
1095         /*
1096          * This function can be called in the initialization and reset process,
1097          * when in reset process, it means that hardware had been reseted
1098          * successfully and we need to restore the hardware configuration to
1099          * ensure that the hardware configuration remains unchanged before and
1100          * after reset.
1101          */
1102         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1103                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1104                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1105         }
1106
1107         ret = hns3_vlan_filter_init(hns);
1108         if (ret) {
1109                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1110                 return ret;
1111         }
1112
1113         ret = hns3_vlan_tpid_configure(hns, RTE_ETH_VLAN_TYPE_INNER,
1114                                        RTE_ETHER_TYPE_VLAN);
1115         if (ret) {
1116                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1117                 return ret;
1118         }
1119
1120         /*
1121          * When in the reinit dev stage of the reset process, the following
1122          * vlan-related configurations may differ from those at initialization,
1123          * we will restore configurations to hardware in hns3_restore_vlan_table
1124          * and hns3_restore_vlan_conf later.
1125          */
1126         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1127                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1128                 if (ret) {
1129                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1130                         return ret;
1131                 }
1132
1133                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1134                 if (ret) {
1135                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1136                                  ret);
1137                         return ret;
1138                 }
1139         }
1140
1141         return hns3_default_vlan_config(hns);
1142 }
1143
1144 static int
1145 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1146 {
1147         struct hns3_pf *pf = &hns->pf;
1148         struct hns3_hw *hw = &hns->hw;
1149         uint64_t offloads;
1150         bool enable;
1151         int ret;
1152
1153         if (!hw->data->promiscuous) {
1154                 /* restore vlan filter states */
1155                 offloads = hw->data->dev_conf.rxmode.offloads;
1156                 enable = offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ? true : false;
1157                 ret = hns3_enable_vlan_filter(hns, enable);
1158                 if (ret) {
1159                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1160                                  "ret = %d", ret);
1161                         return ret;
1162                 }
1163         }
1164
1165         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1166         if (ret) {
1167                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1168                 return ret;
1169         }
1170
1171         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1172         if (ret)
1173                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1174
1175         return ret;
1176 }
1177
1178 static int
1179 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1180 {
1181         struct hns3_adapter *hns = dev->data->dev_private;
1182         struct rte_eth_dev_data *data = dev->data;
1183         struct rte_eth_txmode *txmode;
1184         struct hns3_hw *hw = &hns->hw;
1185         int mask;
1186         int ret;
1187
1188         txmode = &data->dev_conf.txmode;
1189         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1190                 hns3_warn(hw,
1191                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1192                           "configuration is not supported! Ignore these two "
1193                           "parameters: hw_vlan_reject_tagged(%u), "
1194                           "hw_vlan_reject_untagged(%u)",
1195                           txmode->hw_vlan_reject_tagged,
1196                           txmode->hw_vlan_reject_untagged);
1197
1198         /* Apply vlan offload setting */
1199         mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK;
1200         ret = hns3_vlan_offload_set(dev, mask);
1201         if (ret) {
1202                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1203                          ret);
1204                 return ret;
1205         }
1206
1207         /*
1208          * If pvid config is not set in rte_eth_conf, driver needn't to set
1209          * VLAN pvid related configuration to hardware.
1210          */
1211         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1212                 return 0;
1213
1214         /* Apply pvid setting */
1215         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1216                                  txmode->hw_vlan_insert_pvid);
1217         if (ret)
1218                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1219                          txmode->pvid, ret);
1220
1221         return ret;
1222 }
1223
1224 static int
1225 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1226                 unsigned int tso_mss_max)
1227 {
1228         struct hns3_cfg_tso_status_cmd *req;
1229         struct hns3_cmd_desc desc;
1230         uint16_t tso_mss;
1231
1232         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1233
1234         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1235
1236         tso_mss = 0;
1237         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1238                        tso_mss_min);
1239         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1240
1241         tso_mss = 0;
1242         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1243                        tso_mss_max);
1244         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1245
1246         return hns3_cmd_send(hw, &desc, 1);
1247 }
1248
1249 static int
1250 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1251                    uint16_t *allocated_size, bool is_alloc)
1252 {
1253         struct hns3_umv_spc_alc_cmd *req;
1254         struct hns3_cmd_desc desc;
1255         int ret;
1256
1257         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1258         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1259         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1260         req->space_size = rte_cpu_to_le_32(space_size);
1261
1262         ret = hns3_cmd_send(hw, &desc, 1);
1263         if (ret) {
1264                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1265                              is_alloc ? "allocate" : "free", ret);
1266                 return ret;
1267         }
1268
1269         if (is_alloc && allocated_size)
1270                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1271
1272         return 0;
1273 }
1274
1275 static int
1276 hns3_init_umv_space(struct hns3_hw *hw)
1277 {
1278         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1279         struct hns3_pf *pf = &hns->pf;
1280         uint16_t allocated_size = 0;
1281         int ret;
1282
1283         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1284                                  true);
1285         if (ret)
1286                 return ret;
1287
1288         if (allocated_size < pf->wanted_umv_size)
1289                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1290                              pf->wanted_umv_size, allocated_size);
1291
1292         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1293                                                 pf->wanted_umv_size;
1294         pf->used_umv_size = 0;
1295         return 0;
1296 }
1297
1298 static int
1299 hns3_uninit_umv_space(struct hns3_hw *hw)
1300 {
1301         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1302         struct hns3_pf *pf = &hns->pf;
1303         int ret;
1304
1305         if (pf->max_umv_size == 0)
1306                 return 0;
1307
1308         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1309         if (ret)
1310                 return ret;
1311
1312         pf->max_umv_size = 0;
1313
1314         return 0;
1315 }
1316
1317 static bool
1318 hns3_is_umv_space_full(struct hns3_hw *hw)
1319 {
1320         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1321         struct hns3_pf *pf = &hns->pf;
1322         bool is_full;
1323
1324         is_full = (pf->used_umv_size >= pf->max_umv_size);
1325
1326         return is_full;
1327 }
1328
1329 static void
1330 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1331 {
1332         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1333         struct hns3_pf *pf = &hns->pf;
1334
1335         if (is_free) {
1336                 if (pf->used_umv_size > 0)
1337                         pf->used_umv_size--;
1338         } else
1339                 pf->used_umv_size++;
1340 }
1341
1342 static void
1343 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1344                       const uint8_t *addr, bool is_mc)
1345 {
1346         const unsigned char *mac_addr = addr;
1347         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1348                             ((uint32_t)mac_addr[2] << 16) |
1349                             ((uint32_t)mac_addr[1] << 8) |
1350                             (uint32_t)mac_addr[0];
1351         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1352
1353         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1354         if (is_mc) {
1355                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1356                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1357                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1358         }
1359
1360         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1361         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1362 }
1363
1364 static int
1365 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1366                              uint8_t resp_code,
1367                              enum hns3_mac_vlan_tbl_opcode op)
1368 {
1369         if (cmdq_resp) {
1370                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1371                          cmdq_resp);
1372                 return -EIO;
1373         }
1374
1375         if (op == HNS3_MAC_VLAN_ADD) {
1376                 if (resp_code == 0 || resp_code == 1) {
1377                         return 0;
1378                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1379                         hns3_err(hw, "add mac addr failed for uc_overflow");
1380                         return -ENOSPC;
1381                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1382                         hns3_err(hw, "add mac addr failed for mc_overflow");
1383                         return -ENOSPC;
1384                 }
1385
1386                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1387                          resp_code);
1388                 return -EIO;
1389         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1390                 if (resp_code == 0) {
1391                         return 0;
1392                 } else if (resp_code == 1) {
1393                         hns3_dbg(hw, "remove mac addr failed for miss");
1394                         return -ENOENT;
1395                 }
1396
1397                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1398                          resp_code);
1399                 return -EIO;
1400         } else if (op == HNS3_MAC_VLAN_LKUP) {
1401                 if (resp_code == 0) {
1402                         return 0;
1403                 } else if (resp_code == 1) {
1404                         hns3_dbg(hw, "lookup mac addr failed for miss");
1405                         return -ENOENT;
1406                 }
1407
1408                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1409                          resp_code);
1410                 return -EIO;
1411         }
1412
1413         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1414                  op);
1415
1416         return -EINVAL;
1417 }
1418
1419 static int
1420 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1421                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1422                          struct hns3_cmd_desc *desc, uint8_t desc_num)
1423 {
1424         uint8_t resp_code;
1425         uint16_t retval;
1426         int ret;
1427         int i;
1428
1429         if (desc_num == HNS3_MC_MAC_VLAN_OPS_DESC_NUM) {
1430                 for (i = 0; i < desc_num - 1; i++) {
1431                         hns3_cmd_setup_basic_desc(&desc[i],
1432                                                   HNS3_OPC_MAC_VLAN_ADD, true);
1433                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1434                         if (i == 0)
1435                                 memcpy(desc[i].data, req,
1436                                 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1437                 }
1438                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_MAC_VLAN_ADD,
1439                                           true);
1440         } else {
1441                 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD,
1442                                           true);
1443                 memcpy(desc[0].data, req,
1444                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1445         }
1446         ret = hns3_cmd_send(hw, desc, desc_num);
1447         if (ret) {
1448                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1449                          ret);
1450                 return ret;
1451         }
1452         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1453         retval = rte_le_to_cpu_16(desc[0].retval);
1454
1455         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1456                                             HNS3_MAC_VLAN_LKUP);
1457 }
1458
1459 static int
1460 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1461                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1462                       struct hns3_cmd_desc *desc, uint8_t desc_num)
1463 {
1464         uint8_t resp_code;
1465         uint16_t retval;
1466         int cfg_status;
1467         int ret;
1468         int i;
1469
1470         if (desc_num == HNS3_UC_MAC_VLAN_OPS_DESC_NUM) {
1471                 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_MAC_VLAN_ADD, false);
1472                 memcpy(desc->data, req,
1473                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1474                 ret = hns3_cmd_send(hw, desc, desc_num);
1475                 resp_code = (rte_le_to_cpu_32(desc->data[0]) >> 8) & 0xff;
1476                 retval = rte_le_to_cpu_16(desc->retval);
1477
1478                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1479                                                           HNS3_MAC_VLAN_ADD);
1480         } else {
1481                 for (i = 0; i < desc_num; i++) {
1482                         hns3_cmd_reuse_desc(&desc[i], false);
1483                         if (i == desc_num - 1)
1484                                 desc[i].flag &=
1485                                         rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1486                         else
1487                                 desc[i].flag |=
1488                                         rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1489                 }
1490                 memcpy(desc[0].data, req,
1491                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1492                 desc[0].retval = 0;
1493                 ret = hns3_cmd_send(hw, desc, desc_num);
1494                 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1495                 retval = rte_le_to_cpu_16(desc[0].retval);
1496
1497                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1498                                                           HNS3_MAC_VLAN_ADD);
1499         }
1500
1501         if (ret) {
1502                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1503                 return ret;
1504         }
1505
1506         return cfg_status;
1507 }
1508
1509 static int
1510 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1511                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1512 {
1513         struct hns3_cmd_desc desc;
1514         uint8_t resp_code;
1515         uint16_t retval;
1516         int ret;
1517
1518         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1519
1520         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1521
1522         ret = hns3_cmd_send(hw, &desc, 1);
1523         if (ret) {
1524                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1525                 return ret;
1526         }
1527         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1528         retval = rte_le_to_cpu_16(desc.retval);
1529
1530         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1531                                             HNS3_MAC_VLAN_REMOVE);
1532 }
1533
1534 static int
1535 hns3_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1536 {
1537         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1538         struct hns3_mac_vlan_tbl_entry_cmd req;
1539         struct hns3_pf *pf = &hns->pf;
1540         struct hns3_cmd_desc desc;
1541         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1542         uint16_t egress_port = 0;
1543         uint8_t vf_id;
1544         int ret;
1545
1546         /* check if mac addr is valid */
1547         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1548                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1549                                       mac_addr);
1550                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1551                          mac_str);
1552                 return -EINVAL;
1553         }
1554
1555         memset(&req, 0, sizeof(req));
1556
1557         /*
1558          * In current version VF is not supported when PF is driven by DPDK
1559          * driver, just need to configure parameters for PF vport.
1560          */
1561         vf_id = HNS3_PF_FUNC_ID;
1562         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1563                        HNS3_MAC_EPORT_VFID_S, vf_id);
1564
1565         req.egress_port = rte_cpu_to_le_16(egress_port);
1566
1567         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1568
1569         /*
1570          * Lookup the mac address in the mac_vlan table, and add
1571          * it if the entry is inexistent. Repeated unicast entry
1572          * is not allowed in the mac vlan table.
1573          */
1574         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc,
1575                                         HNS3_UC_MAC_VLAN_OPS_DESC_NUM);
1576         if (ret == -ENOENT) {
1577                 if (!hns3_is_umv_space_full(hw)) {
1578                         ret = hns3_add_mac_vlan_tbl(hw, &req, &desc,
1579                                                 HNS3_UC_MAC_VLAN_OPS_DESC_NUM);
1580                         if (!ret)
1581                                 hns3_update_umv_space(hw, false);
1582                         return ret;
1583                 }
1584
1585                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1586
1587                 return -ENOSPC;
1588         }
1589
1590         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1591
1592         /* check if we just hit the duplicate */
1593         if (ret == 0) {
1594                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1595                 return 0;
1596         }
1597
1598         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1599                  mac_str);
1600
1601         return ret;
1602 }
1603
1604 static int
1605 hns3_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1606 {
1607         struct hns3_mac_vlan_tbl_entry_cmd req;
1608         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1609         int ret;
1610
1611         /* check if mac addr is valid */
1612         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1613                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1614                                       mac_addr);
1615                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1616                          mac_str);
1617                 return -EINVAL;
1618         }
1619
1620         memset(&req, 0, sizeof(req));
1621         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1622         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1623         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1624         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1625                 return 0;
1626         else if (ret == 0)
1627                 hns3_update_umv_space(hw, true);
1628
1629         return ret;
1630 }
1631
1632 static int
1633 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1634                           struct rte_ether_addr *mac_addr)
1635 {
1636         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1637         struct rte_ether_addr *oaddr;
1638         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1639         int ret, ret_val;
1640
1641         rte_spinlock_lock(&hw->lock);
1642         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1643         ret = hw->ops.del_uc_mac_addr(hw, oaddr);
1644         if (ret) {
1645                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1646                                       oaddr);
1647                 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1648                           mac_str, ret);
1649
1650                 rte_spinlock_unlock(&hw->lock);
1651                 return ret;
1652         }
1653
1654         ret = hw->ops.add_uc_mac_addr(hw, mac_addr);
1655         if (ret) {
1656                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1657                                       mac_addr);
1658                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1659                 goto err_add_uc_addr;
1660         }
1661
1662         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1663         if (ret) {
1664                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1665                 goto err_pause_addr_cfg;
1666         }
1667
1668         rte_ether_addr_copy(mac_addr,
1669                             (struct rte_ether_addr *)hw->mac.mac_addr);
1670         rte_spinlock_unlock(&hw->lock);
1671
1672         return 0;
1673
1674 err_pause_addr_cfg:
1675         ret_val = hw->ops.del_uc_mac_addr(hw, mac_addr);
1676         if (ret_val) {
1677                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1678                                       mac_addr);
1679                 hns3_warn(hw,
1680                           "Failed to roll back to del setted mac addr(%s): %d",
1681                           mac_str, ret_val);
1682         }
1683
1684 err_add_uc_addr:
1685         ret_val = hw->ops.add_uc_mac_addr(hw, oaddr);
1686         if (ret_val) {
1687                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, oaddr);
1688                 hns3_warn(hw, "Failed to restore old uc mac addr(%s): %d",
1689                                   mac_str, ret_val);
1690         }
1691         rte_spinlock_unlock(&hw->lock);
1692
1693         return ret;
1694 }
1695
1696 static void
1697 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1698 {
1699 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1700         uint8_t word_num;
1701         uint8_t bit_num;
1702
1703         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1704                 word_num = vfid / 32;
1705                 bit_num = vfid % 32;
1706                 if (clr)
1707                         desc[1].data[word_num] &=
1708                             rte_cpu_to_le_32(~(1UL << bit_num));
1709                 else
1710                         desc[1].data[word_num] |=
1711                             rte_cpu_to_le_32(1UL << bit_num);
1712         } else {
1713                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1714                 bit_num = vfid % 32;
1715                 if (clr)
1716                         desc[2].data[word_num] &=
1717                             rte_cpu_to_le_32(~(1UL << bit_num));
1718                 else
1719                         desc[2].data[word_num] |=
1720                             rte_cpu_to_le_32(1UL << bit_num);
1721         }
1722 }
1723
1724 static int
1725 hns3_add_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1726 {
1727         struct hns3_cmd_desc desc[HNS3_MC_MAC_VLAN_OPS_DESC_NUM];
1728         struct hns3_mac_vlan_tbl_entry_cmd req;
1729         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1730         uint8_t vf_id;
1731         int ret;
1732
1733         /* Check if mac addr is valid */
1734         if (!rte_is_multicast_ether_addr(mac_addr)) {
1735                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1736                                       mac_addr);
1737                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1738                          mac_str);
1739                 return -EINVAL;
1740         }
1741
1742         memset(&req, 0, sizeof(req));
1743         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1744         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1745         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc,
1746                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1747         if (ret) {
1748                 /* This mac addr do not exist, add new entry for it */
1749                 memset(desc[0].data, 0, sizeof(desc[0].data));
1750                 memset(desc[1].data, 0, sizeof(desc[0].data));
1751                 memset(desc[2].data, 0, sizeof(desc[0].data));
1752         }
1753
1754         /*
1755          * In current version VF is not supported when PF is driven by DPDK
1756          * driver, just need to configure parameters for PF vport.
1757          */
1758         vf_id = HNS3_PF_FUNC_ID;
1759         hns3_update_desc_vfid(desc, vf_id, false);
1760         ret = hns3_add_mac_vlan_tbl(hw, &req, desc,
1761                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1762         if (ret) {
1763                 if (ret == -ENOSPC)
1764                         hns3_err(hw, "mc mac vlan table is full");
1765                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1766                                       mac_addr);
1767                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1768         }
1769
1770         return ret;
1771 }
1772
1773 static int
1774 hns3_remove_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1775 {
1776         struct hns3_mac_vlan_tbl_entry_cmd req;
1777         struct hns3_cmd_desc desc[3];
1778         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1779         uint8_t vf_id;
1780         int ret;
1781
1782         /* Check if mac addr is valid */
1783         if (!rte_is_multicast_ether_addr(mac_addr)) {
1784                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1785                                       mac_addr);
1786                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1787                          mac_str);
1788                 return -EINVAL;
1789         }
1790
1791         memset(&req, 0, sizeof(req));
1792         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1793         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1794         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc,
1795                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1796         if (ret == 0) {
1797                 /*
1798                  * This mac addr exist, remove this handle's VFID for it.
1799                  * In current version VF is not supported when PF is driven by
1800                  * DPDK driver, just need to configure parameters for PF vport.
1801                  */
1802                 vf_id = HNS3_PF_FUNC_ID;
1803                 hns3_update_desc_vfid(desc, vf_id, true);
1804
1805                 /* All the vfid is zero, so need to delete this entry */
1806                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1807         } else if (ret == -ENOENT) {
1808                 /* This mac addr doesn't exist. */
1809                 return 0;
1810         }
1811
1812         if (ret) {
1813                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1814                                       mac_addr);
1815                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1816         }
1817
1818         return ret;
1819 }
1820
1821 static int
1822 hns3_check_mq_mode(struct rte_eth_dev *dev)
1823 {
1824         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1825         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1826         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1827         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1828         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1829         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1830         uint8_t num_tc;
1831         int max_tc = 0;
1832         int i;
1833
1834         if (((uint32_t)rx_mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) ||
1835             (tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB ||
1836              tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_ONLY)) {
1837                 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
1838                          rx_mq_mode, tx_mq_mode);
1839                 return -EOPNOTSUPP;
1840         }
1841
1842         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1843         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1844         if ((uint32_t)rx_mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
1845                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1846                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1847                                  dcb_rx_conf->nb_tcs, pf->tc_max);
1848                         return -EINVAL;
1849                 }
1850
1851                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1852                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1853                         hns3_err(hw, "on RTE_ETH_MQ_RX_DCB_RSS mode, "
1854                                  "nb_tcs(%d) != %d or %d in rx direction.",
1855                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1856                         return -EINVAL;
1857                 }
1858
1859                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1860                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1861                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1862                         return -EINVAL;
1863                 }
1864
1865                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1866                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1867                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
1868                                          "is not equal to one in tx direction.",
1869                                          i, dcb_rx_conf->dcb_tc[i]);
1870                                 return -EINVAL;
1871                         }
1872                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
1873                                 max_tc = dcb_rx_conf->dcb_tc[i];
1874                 }
1875
1876                 num_tc = max_tc + 1;
1877                 if (num_tc > dcb_rx_conf->nb_tcs) {
1878                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
1879                                  num_tc, dcb_rx_conf->nb_tcs);
1880                         return -EINVAL;
1881                 }
1882         }
1883
1884         return 0;
1885 }
1886
1887 static int
1888 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
1889                            enum hns3_ring_type queue_type, uint16_t queue_id)
1890 {
1891         struct hns3_cmd_desc desc;
1892         struct hns3_ctrl_vector_chain_cmd *req =
1893                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
1894         enum hns3_opcode_type op;
1895         uint16_t tqp_type_and_id = 0;
1896         uint16_t type;
1897         uint16_t gl;
1898         int ret;
1899
1900         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
1901         hns3_cmd_setup_basic_desc(&desc, op, false);
1902         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
1903                                               HNS3_TQP_INT_ID_L_S);
1904         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
1905                                               HNS3_TQP_INT_ID_H_S);
1906
1907         if (queue_type == HNS3_RING_TYPE_RX)
1908                 gl = HNS3_RING_GL_RX;
1909         else
1910                 gl = HNS3_RING_GL_TX;
1911
1912         type = queue_type;
1913
1914         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
1915                        type);
1916         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
1917         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
1918                        gl);
1919         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
1920         req->int_cause_num = 1;
1921         ret = hns3_cmd_send(hw, &desc, 1);
1922         if (ret) {
1923                 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
1924                          en ? "Map" : "Unmap", queue_id, vector_id, ret);
1925                 return ret;
1926         }
1927
1928         return 0;
1929 }
1930
1931 static int
1932 hns3_init_ring_with_vector(struct hns3_hw *hw)
1933 {
1934         uint16_t vec;
1935         int ret;
1936         int i;
1937
1938         /*
1939          * In hns3 network engine, vector 0 is always the misc interrupt of this
1940          * function, vector 1~N can be used respectively for the queues of the
1941          * function. Tx and Rx queues with the same number share the interrupt
1942          * vector. In the initialization clearing the all hardware mapping
1943          * relationship configurations between queues and interrupt vectors is
1944          * needed, so some error caused by the residual configurations, such as
1945          * the unexpected Tx interrupt, can be avoid.
1946          */
1947         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
1948         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
1949                 vec = vec - 1; /* the last interrupt is reserved */
1950         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
1951         for (i = 0; i < hw->intr_tqps_num; i++) {
1952                 /*
1953                  * Set gap limiter/rate limiter/quanity limiter algorithm
1954                  * configuration for interrupt coalesce of queue's interrupt.
1955                  */
1956                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
1957                                        HNS3_TQP_INTR_GL_DEFAULT);
1958                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
1959                                        HNS3_TQP_INTR_GL_DEFAULT);
1960                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
1961                 /*
1962                  * QL(quantity limiter) is not used currently, just set 0 to
1963                  * close it.
1964                  */
1965                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
1966
1967                 ret = hns3_bind_ring_with_vector(hw, vec, false,
1968                                                  HNS3_RING_TYPE_TX, i);
1969                 if (ret) {
1970                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
1971                                           "vector: %u, ret=%d", i, vec, ret);
1972                         return ret;
1973                 }
1974
1975                 ret = hns3_bind_ring_with_vector(hw, vec, false,
1976                                                  HNS3_RING_TYPE_RX, i);
1977                 if (ret) {
1978                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
1979                                           "vector: %u, ret=%d", i, vec, ret);
1980                         return ret;
1981                 }
1982         }
1983
1984         return 0;
1985 }
1986
1987 static int
1988 hns3_setup_dcb(struct rte_eth_dev *dev)
1989 {
1990         struct hns3_adapter *hns = dev->data->dev_private;
1991         struct hns3_hw *hw = &hns->hw;
1992         int ret;
1993
1994         if (!hns3_dev_get_support(hw, DCB)) {
1995                 hns3_err(hw, "this port does not support dcb configurations.");
1996                 return -EOPNOTSUPP;
1997         }
1998
1999         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2000                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2001                 return -EOPNOTSUPP;
2002         }
2003
2004         ret = hns3_dcb_configure(hns);
2005         if (ret)
2006                 hns3_err(hw, "failed to config dcb: %d", ret);
2007
2008         return ret;
2009 }
2010
2011 static int
2012 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
2013 {
2014         int ret;
2015
2016         /*
2017          * Some hardware doesn't support auto-negotiation, but users may not
2018          * configure link_speeds (default 0), which means auto-negotiation.
2019          * In this case, it should return success.
2020          */
2021         if (link_speeds == RTE_ETH_LINK_SPEED_AUTONEG &&
2022             hw->mac.support_autoneg == 0)
2023                 return 0;
2024
2025         if (link_speeds != RTE_ETH_LINK_SPEED_AUTONEG) {
2026                 ret = hns3_check_port_speed(hw, link_speeds);
2027                 if (ret)
2028                         return ret;
2029         }
2030
2031         return 0;
2032 }
2033
2034 static int
2035 hns3_check_dev_conf(struct rte_eth_dev *dev)
2036 {
2037         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2038         struct rte_eth_conf *conf = &dev->data->dev_conf;
2039         int ret;
2040
2041         ret = hns3_check_mq_mode(dev);
2042         if (ret)
2043                 return ret;
2044
2045         return hns3_check_link_speed(hw, conf->link_speeds);
2046 }
2047
2048 static int
2049 hns3_dev_configure(struct rte_eth_dev *dev)
2050 {
2051         struct hns3_adapter *hns = dev->data->dev_private;
2052         struct rte_eth_conf *conf = &dev->data->dev_conf;
2053         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2054         struct hns3_hw *hw = &hns->hw;
2055         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2056         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2057         struct rte_eth_rss_conf rss_conf;
2058         bool gro_en;
2059         int ret;
2060
2061         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2062
2063         /*
2064          * Some versions of hardware network engine does not support
2065          * individually enable/disable/reset the Tx or Rx queue. These devices
2066          * must enable/disable/reset Tx and Rx queues at the same time. When the
2067          * numbers of Tx queues allocated by upper applications are not equal to
2068          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2069          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2070          * work as usual. But these fake queues are imperceptible, and can not
2071          * be used by upper applications.
2072          */
2073         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2074         if (ret) {
2075                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
2076                 hw->cfg_max_queues = 0;
2077                 return ret;
2078         }
2079
2080         hw->adapter_state = HNS3_NIC_CONFIGURING;
2081         ret = hns3_check_dev_conf(dev);
2082         if (ret)
2083                 goto cfg_err;
2084
2085         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
2086                 ret = hns3_setup_dcb(dev);
2087                 if (ret)
2088                         goto cfg_err;
2089         }
2090
2091         /* When RSS is not configured, redirect the packet queue 0 */
2092         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
2093                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2094                 rss_conf = conf->rx_adv_conf.rss_conf;
2095                 hw->rss_dis_flag = false;
2096                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2097                 if (ret)
2098                         goto cfg_err;
2099         }
2100
2101         ret = hns3_dev_mtu_set(dev, conf->rxmode.mtu);
2102         if (ret != 0)
2103                 goto cfg_err;
2104
2105         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2106         if (ret)
2107                 goto cfg_err;
2108
2109         ret = hns3_dev_configure_vlan(dev);
2110         if (ret)
2111                 goto cfg_err;
2112
2113         /* config hardware GRO */
2114         gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
2115         ret = hns3_config_gro(hw, gro_en);
2116         if (ret)
2117                 goto cfg_err;
2118
2119         hns3_init_rx_ptype_tble(dev);
2120         hw->adapter_state = HNS3_NIC_CONFIGURED;
2121
2122         return 0;
2123
2124 cfg_err:
2125         hw->cfg_max_queues = 0;
2126         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2127         hw->adapter_state = HNS3_NIC_INITIALIZED;
2128
2129         return ret;
2130 }
2131
2132 static int
2133 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2134 {
2135         struct hns3_config_max_frm_size_cmd *req;
2136         struct hns3_cmd_desc desc;
2137
2138         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2139
2140         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2141         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2142         req->min_frm_size = RTE_ETHER_MIN_LEN;
2143
2144         return hns3_cmd_send(hw, &desc, 1);
2145 }
2146
2147 static int
2148 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2149 {
2150         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2151         uint16_t original_mps = hns->pf.mps;
2152         int err;
2153         int ret;
2154
2155         ret = hns3_set_mac_mtu(hw, mps);
2156         if (ret) {
2157                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2158                 return ret;
2159         }
2160
2161         hns->pf.mps = mps;
2162         ret = hns3_buffer_alloc(hw);
2163         if (ret) {
2164                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2165                 goto rollback;
2166         }
2167
2168         return 0;
2169
2170 rollback:
2171         err = hns3_set_mac_mtu(hw, original_mps);
2172         if (err) {
2173                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2174                 return ret;
2175         }
2176         hns->pf.mps = original_mps;
2177
2178         return ret;
2179 }
2180
2181 static int
2182 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2183 {
2184         struct hns3_adapter *hns = dev->data->dev_private;
2185         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2186         struct hns3_hw *hw = &hns->hw;
2187         int ret;
2188
2189         if (dev->data->dev_started) {
2190                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2191                          "before configuration", dev->data->port_id);
2192                 return -EBUSY;
2193         }
2194
2195         rte_spinlock_lock(&hw->lock);
2196         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2197
2198         /*
2199          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2200          * assign to "uint16_t" type variable.
2201          */
2202         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2203         if (ret) {
2204                 rte_spinlock_unlock(&hw->lock);
2205                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2206                          dev->data->port_id, mtu, ret);
2207                 return ret;
2208         }
2209
2210         rte_spinlock_unlock(&hw->lock);
2211
2212         return 0;
2213 }
2214
2215 static uint32_t
2216 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2217 {
2218         uint32_t speed_capa = 0;
2219
2220         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2221                 speed_capa |= RTE_ETH_LINK_SPEED_10M_HD;
2222         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2223                 speed_capa |= RTE_ETH_LINK_SPEED_10M;
2224         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2225                 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD;
2226         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2227                 speed_capa |= RTE_ETH_LINK_SPEED_100M;
2228         if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2229                 speed_capa |= RTE_ETH_LINK_SPEED_1G;
2230
2231         return speed_capa;
2232 }
2233
2234 static uint32_t
2235 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2236 {
2237         uint32_t speed_capa = 0;
2238
2239         if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2240                 speed_capa |= RTE_ETH_LINK_SPEED_1G;
2241         if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2242                 speed_capa |= RTE_ETH_LINK_SPEED_10G;
2243         if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2244                 speed_capa |= RTE_ETH_LINK_SPEED_25G;
2245         if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2246                 speed_capa |= RTE_ETH_LINK_SPEED_40G;
2247         if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2248                 speed_capa |= RTE_ETH_LINK_SPEED_50G;
2249         if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2250                 speed_capa |= RTE_ETH_LINK_SPEED_100G;
2251         if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2252                 speed_capa |= RTE_ETH_LINK_SPEED_200G;
2253
2254         return speed_capa;
2255 }
2256
2257 static uint32_t
2258 hns3_get_speed_capa(struct hns3_hw *hw)
2259 {
2260         struct hns3_mac *mac = &hw->mac;
2261         uint32_t speed_capa;
2262
2263         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2264                 speed_capa =
2265                         hns3_get_copper_port_speed_capa(mac->supported_speed);
2266         else
2267                 speed_capa =
2268                         hns3_get_firber_port_speed_capa(mac->supported_speed);
2269
2270         if (mac->support_autoneg == 0)
2271                 speed_capa |= RTE_ETH_LINK_SPEED_FIXED;
2272
2273         return speed_capa;
2274 }
2275
2276 int
2277 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2278 {
2279         struct hns3_adapter *hns = eth_dev->data->dev_private;
2280         struct hns3_hw *hw = &hns->hw;
2281         uint16_t queue_num = hw->tqps_num;
2282
2283         /*
2284          * In interrupt mode, 'max_rx_queues' is set based on the number of
2285          * MSI-X interrupt resources of the hardware.
2286          */
2287         if (hw->data->dev_conf.intr_conf.rxq == 1)
2288                 queue_num = hw->intr_tqps_num;
2289
2290         info->max_rx_queues = queue_num;
2291         info->max_tx_queues = hw->tqps_num;
2292         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2293         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2294         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2295         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2296         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2297         info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
2298                                  RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
2299                                  RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
2300                                  RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
2301                                  RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2302                                  RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
2303                                  RTE_ETH_RX_OFFLOAD_KEEP_CRC |
2304                                  RTE_ETH_RX_OFFLOAD_SCATTER |
2305                                  RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
2306                                  RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
2307                                  RTE_ETH_RX_OFFLOAD_RSS_HASH |
2308                                  RTE_ETH_RX_OFFLOAD_TCP_LRO);
2309         info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2310                                  RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
2311                                  RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
2312                                  RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
2313                                  RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
2314                                  RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
2315                                  RTE_ETH_TX_OFFLOAD_TCP_TSO |
2316                                  RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
2317                                  RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
2318                                  RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
2319                                  RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
2320                                  hns3_txvlan_cap_get(hw));
2321
2322         if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
2323                 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
2324
2325         if (hns3_dev_get_support(hw, INDEP_TXRX))
2326                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2327                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2328         info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
2329
2330         if (hns3_dev_get_support(hw, PTP))
2331                 info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP;
2332
2333         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2334                 .nb_max = HNS3_MAX_RING_DESC,
2335                 .nb_min = HNS3_MIN_RING_DESC,
2336                 .nb_align = HNS3_ALIGN_RING_DESC,
2337         };
2338
2339         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2340                 .nb_max = HNS3_MAX_RING_DESC,
2341                 .nb_min = HNS3_MIN_RING_DESC,
2342                 .nb_align = HNS3_ALIGN_RING_DESC,
2343                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2344                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2345         };
2346
2347         info->speed_capa = hns3_get_speed_capa(hw);
2348         info->default_rxconf = (struct rte_eth_rxconf) {
2349                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2350                 /*
2351                  * If there are no available Rx buffer descriptors, incoming
2352                  * packets are always dropped by hardware based on hns3 network
2353                  * engine.
2354                  */
2355                 .rx_drop_en = 1,
2356                 .offloads = 0,
2357         };
2358         info->default_txconf = (struct rte_eth_txconf) {
2359                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2360                 .offloads = 0,
2361         };
2362
2363         info->reta_size = hw->rss_ind_tbl_size;
2364         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2365         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2366
2367         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2368         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2369         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2370         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2371         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2372         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2373
2374         return 0;
2375 }
2376
2377 static int
2378 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2379                     size_t fw_size)
2380 {
2381         struct hns3_adapter *hns = eth_dev->data->dev_private;
2382         struct hns3_hw *hw = &hns->hw;
2383         uint32_t version = hw->fw_version;
2384         int ret;
2385
2386         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2387                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2388                                       HNS3_FW_VERSION_BYTE3_S),
2389                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2390                                       HNS3_FW_VERSION_BYTE2_S),
2391                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2392                                       HNS3_FW_VERSION_BYTE1_S),
2393                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2394                                       HNS3_FW_VERSION_BYTE0_S));
2395         if (ret < 0)
2396                 return -EINVAL;
2397
2398         ret += 1; /* add the size of '\0' */
2399         if (fw_size < (size_t)ret)
2400                 return ret;
2401         else
2402                 return 0;
2403 }
2404
2405 static int
2406 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2407 {
2408         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2409         int ret;
2410
2411         (void)hns3_update_link_status(hw);
2412
2413         ret = hns3_update_link_info(eth_dev);
2414         if (ret)
2415                 hw->mac.link_status = RTE_ETH_LINK_DOWN;
2416
2417         return ret;
2418 }
2419
2420 static void
2421 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2422                       struct rte_eth_link *new_link)
2423 {
2424         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2425         struct hns3_mac *mac = &hw->mac;
2426
2427         switch (mac->link_speed) {
2428         case RTE_ETH_SPEED_NUM_10M:
2429         case RTE_ETH_SPEED_NUM_100M:
2430         case RTE_ETH_SPEED_NUM_1G:
2431         case RTE_ETH_SPEED_NUM_10G:
2432         case RTE_ETH_SPEED_NUM_25G:
2433         case RTE_ETH_SPEED_NUM_40G:
2434         case RTE_ETH_SPEED_NUM_50G:
2435         case RTE_ETH_SPEED_NUM_100G:
2436         case RTE_ETH_SPEED_NUM_200G:
2437                 if (mac->link_status)
2438                         new_link->link_speed = mac->link_speed;
2439                 break;
2440         default:
2441                 if (mac->link_status)
2442                         new_link->link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2443                 break;
2444         }
2445
2446         if (!mac->link_status)
2447                 new_link->link_speed = RTE_ETH_SPEED_NUM_NONE;
2448
2449         new_link->link_duplex = mac->link_duplex;
2450         new_link->link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2451         new_link->link_autoneg = mac->link_autoneg;
2452 }
2453
2454 static int
2455 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2456 {
2457 #define HNS3_LINK_CHECK_INTERVAL 100  /* 100ms */
2458 #define HNS3_MAX_LINK_CHECK_TIMES 20  /* 2s (100 * 20ms) in total */
2459
2460         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2461         uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2462         struct hns3_mac *mac = &hw->mac;
2463         struct rte_eth_link new_link;
2464         int ret;
2465
2466         /* When port is stopped, report link down. */
2467         if (eth_dev->data->dev_started == 0) {
2468                 new_link.link_autoneg = mac->link_autoneg;
2469                 new_link.link_duplex = mac->link_duplex;
2470                 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2471                 new_link.link_status = RTE_ETH_LINK_DOWN;
2472                 goto out;
2473         }
2474
2475         do {
2476                 ret = hns3_update_port_link_info(eth_dev);
2477                 if (ret) {
2478                         hns3_err(hw, "failed to get port link info, ret = %d.",
2479                                  ret);
2480                         break;
2481                 }
2482
2483                 if (!wait_to_complete || mac->link_status == RTE_ETH_LINK_UP)
2484                         break;
2485
2486                 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2487         } while (retry_cnt--);
2488
2489         memset(&new_link, 0, sizeof(new_link));
2490         hns3_setup_linkstatus(eth_dev, &new_link);
2491
2492 out:
2493         return rte_eth_linkstatus_set(eth_dev, &new_link);
2494 }
2495
2496 static int
2497 hns3_dev_set_link_up(struct rte_eth_dev *dev)
2498 {
2499         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2500         int ret;
2501
2502         /*
2503          * The "tx_pkt_burst" will be restored. But the secondary process does
2504          * not support the mechanism for notifying the primary process.
2505          */
2506         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2507                 hns3_err(hw, "secondary process does not support to set link up.");
2508                 return -ENOTSUP;
2509         }
2510
2511         /*
2512          * If device isn't started Rx/Tx function is still disabled, setting
2513          * link up is not allowed. But it is probably better to return success
2514          * to reduce the impact on the upper layer.
2515          */
2516         if (hw->adapter_state != HNS3_NIC_STARTED) {
2517                 hns3_info(hw, "device isn't started, can't set link up.");
2518                 return 0;
2519         }
2520
2521         if (!hw->set_link_down)
2522                 return 0;
2523
2524         rte_spinlock_lock(&hw->lock);
2525         ret = hns3_cfg_mac_mode(hw, true);
2526         if (ret) {
2527                 rte_spinlock_unlock(&hw->lock);
2528                 hns3_err(hw, "failed to set link up, ret = %d", ret);
2529                 return ret;
2530         }
2531
2532         hw->set_link_down = false;
2533         hns3_start_tx_datapath(dev);
2534         rte_spinlock_unlock(&hw->lock);
2535
2536         return 0;
2537 }
2538
2539 static int
2540 hns3_dev_set_link_down(struct rte_eth_dev *dev)
2541 {
2542         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2543         int ret;
2544
2545         /*
2546          * The "tx_pkt_burst" will be set to dummy function. But the secondary
2547          * process does not support the mechanism for notifying the primary
2548          * process.
2549          */
2550         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2551                 hns3_err(hw, "secondary process does not support to set link down.");
2552                 return -ENOTSUP;
2553         }
2554
2555         /*
2556          * If device isn't started or the API has been called, link status is
2557          * down, return success.
2558          */
2559         if (hw->adapter_state != HNS3_NIC_STARTED || hw->set_link_down)
2560                 return 0;
2561
2562         rte_spinlock_lock(&hw->lock);
2563         hns3_stop_tx_datapath(dev);
2564         ret = hns3_cfg_mac_mode(hw, false);
2565         if (ret) {
2566                 hns3_start_tx_datapath(dev);
2567                 rte_spinlock_unlock(&hw->lock);
2568                 hns3_err(hw, "failed to set link down, ret = %d", ret);
2569                 return ret;
2570         }
2571
2572         hw->set_link_down = true;
2573         rte_spinlock_unlock(&hw->lock);
2574
2575         return 0;
2576 }
2577
2578 static int
2579 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2580 {
2581         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2582         struct hns3_pf *pf = &hns->pf;
2583
2584         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2585                 return -EINVAL;
2586
2587         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2588
2589         return 0;
2590 }
2591
2592 static int
2593 hns3_query_function_status(struct hns3_hw *hw)
2594 {
2595 #define HNS3_QUERY_MAX_CNT              10
2596 #define HNS3_QUERY_SLEEP_MSCOEND        1
2597         struct hns3_func_status_cmd *req;
2598         struct hns3_cmd_desc desc;
2599         int timeout = 0;
2600         int ret;
2601
2602         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2603         req = (struct hns3_func_status_cmd *)desc.data;
2604
2605         do {
2606                 ret = hns3_cmd_send(hw, &desc, 1);
2607                 if (ret) {
2608                         PMD_INIT_LOG(ERR, "query function status failed %d",
2609                                      ret);
2610                         return ret;
2611                 }
2612
2613                 /* Check pf reset is done */
2614                 if (req->pf_state)
2615                         break;
2616
2617                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2618         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2619
2620         return hns3_parse_func_status(hw, req);
2621 }
2622
2623 static int
2624 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2625 {
2626         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2627         struct hns3_pf *pf = &hns->pf;
2628
2629         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2630                 /*
2631                  * The total_tqps_num obtained from firmware is maximum tqp
2632                  * numbers of this port, which should be used for PF and VFs.
2633                  * There is no need for pf to have so many tqp numbers in
2634                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2635                  * coming from config file, is assigned to maximum queue number
2636                  * for the PF of this port by user. So users can modify the
2637                  * maximum queue number of PF according to their own application
2638                  * scenarios, which is more flexible to use. In addition, many
2639                  * memories can be saved due to allocating queue statistics
2640                  * room according to the actual number of queues required. The
2641                  * maximum queue number of PF for network engine with
2642                  * revision_id greater than 0x30 is assigned by config file.
2643                  */
2644                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2645                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2646                                  "must be greater than 0.",
2647                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2648                         return -EINVAL;
2649                 }
2650
2651                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2652                                        hw->total_tqps_num);
2653         } else {
2654                 /*
2655                  * Due to the limitation on the number of PF interrupts
2656                  * available, the maximum queue number assigned to PF on
2657                  * the network engine with revision_id 0x21 is 64.
2658                  */
2659                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2660                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2661         }
2662
2663         return 0;
2664 }
2665
2666 static int
2667 hns3_query_pf_resource(struct hns3_hw *hw)
2668 {
2669         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2670         struct hns3_pf *pf = &hns->pf;
2671         struct hns3_pf_res_cmd *req;
2672         struct hns3_cmd_desc desc;
2673         int ret;
2674
2675         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2676         ret = hns3_cmd_send(hw, &desc, 1);
2677         if (ret) {
2678                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2679                 return ret;
2680         }
2681
2682         req = (struct hns3_pf_res_cmd *)desc.data;
2683         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2684                              rte_le_to_cpu_16(req->ext_tqp_num);
2685         ret = hns3_get_pf_max_tqp_num(hw);
2686         if (ret)
2687                 return ret;
2688
2689         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2690         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2691
2692         if (req->tx_buf_size)
2693                 pf->tx_buf_size =
2694                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2695         else
2696                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2697
2698         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2699
2700         if (req->dv_buf_size)
2701                 pf->dv_buf_size =
2702                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2703         else
2704                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2705
2706         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2707
2708         hw->num_msi =
2709                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2710                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2711
2712         return 0;
2713 }
2714
2715 static void
2716 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2717 {
2718         struct hns3_cfg_param_cmd *req;
2719         uint64_t mac_addr_tmp_high;
2720         uint8_t ext_rss_size_max;
2721         uint64_t mac_addr_tmp;
2722         uint32_t i;
2723
2724         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2725
2726         /* get the configuration */
2727         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2728                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2729         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2730                                            HNS3_CFG_TQP_DESC_N_M,
2731                                            HNS3_CFG_TQP_DESC_N_S);
2732
2733         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2734                                        HNS3_CFG_PHY_ADDR_M,
2735                                        HNS3_CFG_PHY_ADDR_S);
2736         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2737                                          HNS3_CFG_MEDIA_TP_M,
2738                                          HNS3_CFG_MEDIA_TP_S);
2739         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2740                                          HNS3_CFG_RX_BUF_LEN_M,
2741                                          HNS3_CFG_RX_BUF_LEN_S);
2742         /* get mac address */
2743         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2744         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2745                                            HNS3_CFG_MAC_ADDR_H_M,
2746                                            HNS3_CFG_MAC_ADDR_H_S);
2747
2748         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2749
2750         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2751                                             HNS3_CFG_DEFAULT_SPEED_M,
2752                                             HNS3_CFG_DEFAULT_SPEED_S);
2753         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2754                                            HNS3_CFG_RSS_SIZE_M,
2755                                            HNS3_CFG_RSS_SIZE_S);
2756
2757         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2758                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2759
2760         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2761         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2762
2763         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2764                                             HNS3_CFG_SPEED_ABILITY_M,
2765                                             HNS3_CFG_SPEED_ABILITY_S);
2766         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2767                                         HNS3_CFG_UMV_TBL_SPACE_M,
2768                                         HNS3_CFG_UMV_TBL_SPACE_S);
2769         if (!cfg->umv_space)
2770                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2771
2772         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2773                                                HNS3_CFG_EXT_RSS_SIZE_M,
2774                                                HNS3_CFG_EXT_RSS_SIZE_S);
2775         /*
2776          * Field ext_rss_size_max obtained from firmware will be more flexible
2777          * for future changes and expansions, which is an exponent of 2, instead
2778          * of reading out directly. If this field is not zero, hns3 PF PMD
2779          * driver uses it as rss_size_max under one TC. Device, whose revision
2780          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2781          * maximum number of queues supported under a TC through this field.
2782          */
2783         if (ext_rss_size_max)
2784                 cfg->rss_size_max = 1U << ext_rss_size_max;
2785 }
2786
2787 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2788  * @hw: pointer to struct hns3_hw
2789  * @hcfg: the config structure to be getted
2790  */
2791 static int
2792 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2793 {
2794         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2795         struct hns3_cfg_param_cmd *req;
2796         uint32_t offset;
2797         uint32_t i;
2798         int ret;
2799
2800         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2801                 offset = 0;
2802                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2803                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2804                                           true);
2805                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2806                                i * HNS3_CFG_RD_LEN_BYTES);
2807                 /* Len should be divided by 4 when send to hardware */
2808                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2809                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2810                 req->offset = rte_cpu_to_le_32(offset);
2811         }
2812
2813         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2814         if (ret) {
2815                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2816                 return ret;
2817         }
2818
2819         hns3_parse_cfg(hcfg, desc);
2820
2821         return 0;
2822 }
2823
2824 static int
2825 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2826 {
2827         switch (speed_cmd) {
2828         case HNS3_CFG_SPEED_10M:
2829                 *speed = RTE_ETH_SPEED_NUM_10M;
2830                 break;
2831         case HNS3_CFG_SPEED_100M:
2832                 *speed = RTE_ETH_SPEED_NUM_100M;
2833                 break;
2834         case HNS3_CFG_SPEED_1G:
2835                 *speed = RTE_ETH_SPEED_NUM_1G;
2836                 break;
2837         case HNS3_CFG_SPEED_10G:
2838                 *speed = RTE_ETH_SPEED_NUM_10G;
2839                 break;
2840         case HNS3_CFG_SPEED_25G:
2841                 *speed = RTE_ETH_SPEED_NUM_25G;
2842                 break;
2843         case HNS3_CFG_SPEED_40G:
2844                 *speed = RTE_ETH_SPEED_NUM_40G;
2845                 break;
2846         case HNS3_CFG_SPEED_50G:
2847                 *speed = RTE_ETH_SPEED_NUM_50G;
2848                 break;
2849         case HNS3_CFG_SPEED_100G:
2850                 *speed = RTE_ETH_SPEED_NUM_100G;
2851                 break;
2852         case HNS3_CFG_SPEED_200G:
2853                 *speed = RTE_ETH_SPEED_NUM_200G;
2854                 break;
2855         default:
2856                 return -EINVAL;
2857         }
2858
2859         return 0;
2860 }
2861
2862 static void
2863 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2864 {
2865         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2866         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2867         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2868         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2869         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2870 }
2871
2872 static void
2873 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2874 {
2875         struct hns3_dev_specs_0_cmd *req0;
2876
2877         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2878
2879         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2880         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2881         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2882         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2883         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
2884 }
2885
2886 static int
2887 hns3_check_dev_specifications(struct hns3_hw *hw)
2888 {
2889         if (hw->rss_ind_tbl_size == 0 ||
2890             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
2891                 hns3_err(hw, "the size of hash lookup table configured (%u)"
2892                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
2893                               HNS3_RSS_IND_TBL_SIZE_MAX);
2894                 return -EINVAL;
2895         }
2896
2897         return 0;
2898 }
2899
2900 static int
2901 hns3_query_dev_specifications(struct hns3_hw *hw)
2902 {
2903         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2904         int ret;
2905         int i;
2906
2907         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2908                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2909                                           true);
2910                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2911         }
2912         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2913
2914         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2915         if (ret)
2916                 return ret;
2917
2918         hns3_parse_dev_specifications(hw, desc);
2919
2920         return hns3_check_dev_specifications(hw);
2921 }
2922
2923 static int
2924 hns3_get_capability(struct hns3_hw *hw)
2925 {
2926         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2927         struct rte_pci_device *pci_dev;
2928         struct hns3_pf *pf = &hns->pf;
2929         struct rte_eth_dev *eth_dev;
2930         uint16_t device_id;
2931         uint8_t revision;
2932         int ret;
2933
2934         eth_dev = &rte_eth_devices[hw->data->port_id];
2935         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2936         device_id = pci_dev->id.device_id;
2937
2938         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
2939             device_id == HNS3_DEV_ID_50GE_RDMA ||
2940             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
2941             device_id == HNS3_DEV_ID_200G_RDMA)
2942                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
2943
2944         /* Get PCI revision id */
2945         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
2946                                   HNS3_PCI_REVISION_ID);
2947         if (ret != HNS3_PCI_REVISION_ID_LEN) {
2948                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
2949                              ret);
2950                 return -EIO;
2951         }
2952         hw->revision = revision;
2953
2954         if (revision < PCI_REVISION_ID_HIP09_A) {
2955                 hns3_set_default_dev_specifications(hw);
2956                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
2957                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
2958                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
2959                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
2960                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
2961                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
2962                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
2963                 hw->rss_info.ipv6_sctp_offload_supported = false;
2964                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
2965                 pf->support_multi_tc_pause = false;
2966                 return 0;
2967         }
2968
2969         ret = hns3_query_dev_specifications(hw);
2970         if (ret) {
2971                 PMD_INIT_LOG(ERR,
2972                              "failed to query dev specifications, ret = %d",
2973                              ret);
2974                 return ret;
2975         }
2976
2977         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
2978         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
2979         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
2980         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
2981         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
2982         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
2983         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
2984         hw->rss_info.ipv6_sctp_offload_supported = true;
2985         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
2986         pf->support_multi_tc_pause = true;
2987
2988         return 0;
2989 }
2990
2991 static int
2992 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
2993 {
2994         int ret;
2995
2996         switch (media_type) {
2997         case HNS3_MEDIA_TYPE_COPPER:
2998                 if (!hns3_dev_get_support(hw, COPPER)) {
2999                         PMD_INIT_LOG(ERR,
3000                                      "Media type is copper, not supported.");
3001                         ret = -EOPNOTSUPP;
3002                 } else {
3003                         ret = 0;
3004                 }
3005                 break;
3006         case HNS3_MEDIA_TYPE_FIBER:
3007                 ret = 0;
3008                 break;
3009         case HNS3_MEDIA_TYPE_BACKPLANE:
3010                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3011                 ret = -EOPNOTSUPP;
3012                 break;
3013         default:
3014                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3015                 ret = -EINVAL;
3016                 break;
3017         }
3018
3019         return ret;
3020 }
3021
3022 static int
3023 hns3_get_board_configuration(struct hns3_hw *hw)
3024 {
3025         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3026         struct hns3_pf *pf = &hns->pf;
3027         struct hns3_cfg cfg;
3028         int ret;
3029
3030         ret = hns3_get_board_cfg(hw, &cfg);
3031         if (ret) {
3032                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3033                 return ret;
3034         }
3035
3036         ret = hns3_check_media_type(hw, cfg.media_type);
3037         if (ret)
3038                 return ret;
3039
3040         hw->mac.media_type = cfg.media_type;
3041         hw->rss_size_max = cfg.rss_size_max;
3042         hw->rss_dis_flag = false;
3043         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3044         hw->mac.phy_addr = cfg.phy_addr;
3045         hw->num_tx_desc = cfg.tqp_desc_num;
3046         hw->num_rx_desc = cfg.tqp_desc_num;
3047         hw->dcb_info.num_pg = 1;
3048         hw->dcb_info.hw_pfc_map = 0;
3049
3050         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3051         if (ret) {
3052                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3053                              cfg.default_speed, ret);
3054                 return ret;
3055         }
3056
3057         pf->tc_max = cfg.tc_num;
3058         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3059                 PMD_INIT_LOG(WARNING,
3060                              "Get TC num(%u) from flash, set TC num to 1",
3061                              pf->tc_max);
3062                 pf->tc_max = 1;
3063         }
3064
3065         /* Dev does not support DCB */
3066         if (!hns3_dev_get_support(hw, DCB)) {
3067                 pf->tc_max = 1;
3068                 pf->pfc_max = 0;
3069         } else
3070                 pf->pfc_max = pf->tc_max;
3071
3072         hw->dcb_info.num_tc = 1;
3073         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3074                                      hw->tqps_num / hw->dcb_info.num_tc);
3075         hns3_set_bit(hw->hw_tc_map, 0, 1);
3076         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3077
3078         pf->wanted_umv_size = cfg.umv_space;
3079
3080         return ret;
3081 }
3082
3083 static int
3084 hns3_get_configuration(struct hns3_hw *hw)
3085 {
3086         int ret;
3087
3088         ret = hns3_query_function_status(hw);
3089         if (ret) {
3090                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3091                 return ret;
3092         }
3093
3094         /* Get device capability */
3095         ret = hns3_get_capability(hw);
3096         if (ret) {
3097                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3098                 return ret;
3099         }
3100
3101         /* Get pf resource */
3102         ret = hns3_query_pf_resource(hw);
3103         if (ret) {
3104                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3105                 return ret;
3106         }
3107
3108         ret = hns3_get_board_configuration(hw);
3109         if (ret) {
3110                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3111                 return ret;
3112         }
3113
3114         ret = hns3_query_dev_fec_info(hw);
3115         if (ret)
3116                 PMD_INIT_LOG(ERR,
3117                              "failed to query FEC information, ret = %d", ret);
3118
3119         return ret;
3120 }
3121
3122 static int
3123 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3124                       uint16_t tqp_vid, bool is_pf)
3125 {
3126         struct hns3_tqp_map_cmd *req;
3127         struct hns3_cmd_desc desc;
3128         int ret;
3129
3130         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3131
3132         req = (struct hns3_tqp_map_cmd *)desc.data;
3133         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3134         req->tqp_vf = func_id;
3135         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3136         if (!is_pf)
3137                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3138         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3139
3140         ret = hns3_cmd_send(hw, &desc, 1);
3141         if (ret)
3142                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3143
3144         return ret;
3145 }
3146
3147 static int
3148 hns3_map_tqp(struct hns3_hw *hw)
3149 {
3150         int ret;
3151         int i;
3152
3153         /*
3154          * In current version, VF is not supported when PF is driven by DPDK
3155          * driver, so we assign total tqps_num tqps allocated to this port
3156          * to PF.
3157          */
3158         for (i = 0; i < hw->total_tqps_num; i++) {
3159                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3160                 if (ret)
3161                         return ret;
3162         }
3163
3164         return 0;
3165 }
3166
3167 static int
3168 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3169 {
3170         struct hns3_config_mac_speed_dup_cmd *req;
3171         struct hns3_cmd_desc desc;
3172         int ret;
3173
3174         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3175
3176         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3177
3178         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3179
3180         switch (speed) {
3181         case RTE_ETH_SPEED_NUM_10M:
3182                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3183                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3184                 break;
3185         case RTE_ETH_SPEED_NUM_100M:
3186                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3187                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3188                 break;
3189         case RTE_ETH_SPEED_NUM_1G:
3190                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3191                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3192                 break;
3193         case RTE_ETH_SPEED_NUM_10G:
3194                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3195                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3196                 break;
3197         case RTE_ETH_SPEED_NUM_25G:
3198                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3199                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3200                 break;
3201         case RTE_ETH_SPEED_NUM_40G:
3202                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3203                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3204                 break;
3205         case RTE_ETH_SPEED_NUM_50G:
3206                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3207                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3208                 break;
3209         case RTE_ETH_SPEED_NUM_100G:
3210                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3211                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3212                 break;
3213         case RTE_ETH_SPEED_NUM_200G:
3214                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3215                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3216                 break;
3217         default:
3218                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3219                 return -EINVAL;
3220         }
3221
3222         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3223
3224         ret = hns3_cmd_send(hw, &desc, 1);
3225         if (ret)
3226                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3227
3228         return ret;
3229 }
3230
3231 static int
3232 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3233 {
3234         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3235         struct hns3_pf *pf = &hns->pf;
3236         struct hns3_priv_buf *priv;
3237         uint32_t i, total_size;
3238
3239         total_size = pf->pkt_buf_size;
3240
3241         /* alloc tx buffer for all enabled tc */
3242         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3243                 priv = &buf_alloc->priv_buf[i];
3244
3245                 if (hw->hw_tc_map & BIT(i)) {
3246                         if (total_size < pf->tx_buf_size)
3247                                 return -ENOMEM;
3248
3249                         priv->tx_buf_size = pf->tx_buf_size;
3250                 } else
3251                         priv->tx_buf_size = 0;
3252
3253                 total_size -= priv->tx_buf_size;
3254         }
3255
3256         return 0;
3257 }
3258
3259 static int
3260 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3261 {
3262 /* TX buffer size is unit by 128 byte */
3263 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3264 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3265         struct hns3_tx_buff_alloc_cmd *req;
3266         struct hns3_cmd_desc desc;
3267         uint32_t buf_size;
3268         uint32_t i;
3269         int ret;
3270
3271         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3272
3273         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3274         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3275                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3276
3277                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3278                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3279                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3280         }
3281
3282         ret = hns3_cmd_send(hw, &desc, 1);
3283         if (ret)
3284                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3285
3286         return ret;
3287 }
3288
3289 static int
3290 hns3_get_tc_num(struct hns3_hw *hw)
3291 {
3292         int cnt = 0;
3293         uint8_t i;
3294
3295         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3296                 if (hw->hw_tc_map & BIT(i))
3297                         cnt++;
3298         return cnt;
3299 }
3300
3301 static uint32_t
3302 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3303 {
3304         struct hns3_priv_buf *priv;
3305         uint32_t rx_priv = 0;
3306         int i;
3307
3308         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3309                 priv = &buf_alloc->priv_buf[i];
3310                 if (priv->enable)
3311                         rx_priv += priv->buf_size;
3312         }
3313         return rx_priv;
3314 }
3315
3316 static uint32_t
3317 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3318 {
3319         uint32_t total_tx_size = 0;
3320         uint32_t i;
3321
3322         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3323                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3324
3325         return total_tx_size;
3326 }
3327
3328 /* Get the number of pfc enabled TCs, which have private buffer */
3329 static int
3330 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3331 {
3332         struct hns3_priv_buf *priv;
3333         int cnt = 0;
3334         uint8_t i;
3335
3336         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3337                 priv = &buf_alloc->priv_buf[i];
3338                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3339                         cnt++;
3340         }
3341
3342         return cnt;
3343 }
3344
3345 /* Get the number of pfc disabled TCs, which have private buffer */
3346 static int
3347 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3348                          struct hns3_pkt_buf_alloc *buf_alloc)
3349 {
3350         struct hns3_priv_buf *priv;
3351         int cnt = 0;
3352         uint8_t i;
3353
3354         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3355                 priv = &buf_alloc->priv_buf[i];
3356                 if (hw->hw_tc_map & BIT(i) &&
3357                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3358                         cnt++;
3359         }
3360
3361         return cnt;
3362 }
3363
3364 static bool
3365 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3366                   uint32_t rx_all)
3367 {
3368         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3369         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3370         struct hns3_pf *pf = &hns->pf;
3371         uint32_t shared_buf, aligned_mps;
3372         uint32_t rx_priv;
3373         uint8_t tc_num;
3374         uint8_t i;
3375
3376         tc_num = hns3_get_tc_num(hw);
3377         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3378
3379         if (hns3_dev_get_support(hw, DCB))
3380                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3381                                         pf->dv_buf_size;
3382         else
3383                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3384                                         + pf->dv_buf_size;
3385
3386         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3387         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3388                              HNS3_BUF_SIZE_UNIT);
3389
3390         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3391         if (rx_all < rx_priv + shared_std)
3392                 return false;
3393
3394         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3395         buf_alloc->s_buf.buf_size = shared_buf;
3396         if (hns3_dev_get_support(hw, DCB)) {
3397                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3398                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3399                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3400                                   HNS3_BUF_SIZE_UNIT);
3401         } else {
3402                 buf_alloc->s_buf.self.high =
3403                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3404                 buf_alloc->s_buf.self.low = aligned_mps;
3405         }
3406
3407         if (hns3_dev_get_support(hw, DCB)) {
3408                 hi_thrd = shared_buf - pf->dv_buf_size;
3409
3410                 if (tc_num <= NEED_RESERVE_TC_NUM)
3411                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3412                                   BUF_MAX_PERCENT;
3413
3414                 if (tc_num)
3415                         hi_thrd = hi_thrd / tc_num;
3416
3417                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3418                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3419                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3420         } else {
3421                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3422                 lo_thrd = aligned_mps;
3423         }
3424
3425         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3426                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3427                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3428         }
3429
3430         return true;
3431 }
3432
3433 static bool
3434 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3435                      struct hns3_pkt_buf_alloc *buf_alloc)
3436 {
3437         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3438         struct hns3_pf *pf = &hns->pf;
3439         struct hns3_priv_buf *priv;
3440         uint32_t aligned_mps;
3441         uint32_t rx_all;
3442         uint8_t i;
3443
3444         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3445         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3446
3447         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3448                 priv = &buf_alloc->priv_buf[i];
3449
3450                 priv->enable = 0;
3451                 priv->wl.low = 0;
3452                 priv->wl.high = 0;
3453                 priv->buf_size = 0;
3454
3455                 if (!(hw->hw_tc_map & BIT(i)))
3456                         continue;
3457
3458                 priv->enable = 1;
3459                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3460                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3461                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3462                                                 HNS3_BUF_SIZE_UNIT);
3463                 } else {
3464                         priv->wl.low = 0;
3465                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3466                                         aligned_mps;
3467                 }
3468
3469                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3470         }
3471
3472         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3473 }
3474
3475 static bool
3476 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3477                              struct hns3_pkt_buf_alloc *buf_alloc)
3478 {
3479         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3480         struct hns3_pf *pf = &hns->pf;
3481         struct hns3_priv_buf *priv;
3482         int no_pfc_priv_num;
3483         uint32_t rx_all;
3484         uint8_t mask;
3485         int i;
3486
3487         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3488         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3489
3490         /* let the last to be cleared first */
3491         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3492                 priv = &buf_alloc->priv_buf[i];
3493                 mask = BIT((uint8_t)i);
3494                 if (hw->hw_tc_map & mask &&
3495                     !(hw->dcb_info.hw_pfc_map & mask)) {
3496                         /* Clear the no pfc TC private buffer */
3497                         priv->wl.low = 0;
3498                         priv->wl.high = 0;
3499                         priv->buf_size = 0;
3500                         priv->enable = 0;
3501                         no_pfc_priv_num--;
3502                 }
3503
3504                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3505                     no_pfc_priv_num == 0)
3506                         break;
3507         }
3508
3509         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3510 }
3511
3512 static bool
3513 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3514                            struct hns3_pkt_buf_alloc *buf_alloc)
3515 {
3516         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3517         struct hns3_pf *pf = &hns->pf;
3518         struct hns3_priv_buf *priv;
3519         uint32_t rx_all;
3520         int pfc_priv_num;
3521         uint8_t mask;
3522         int i;
3523
3524         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3525         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3526
3527         /* let the last to be cleared first */
3528         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3529                 priv = &buf_alloc->priv_buf[i];
3530                 mask = BIT((uint8_t)i);
3531                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3532                         /* Reduce the number of pfc TC with private buffer */
3533                         priv->wl.low = 0;
3534                         priv->enable = 0;
3535                         priv->wl.high = 0;
3536                         priv->buf_size = 0;
3537                         pfc_priv_num--;
3538                 }
3539                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3540                     pfc_priv_num == 0)
3541                         break;
3542         }
3543
3544         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3545 }
3546
3547 static bool
3548 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3549                           struct hns3_pkt_buf_alloc *buf_alloc)
3550 {
3551 #define COMPENSATE_BUFFER       0x3C00
3552 #define COMPENSATE_HALF_MPS_NUM 5
3553 #define PRIV_WL_GAP             0x1800
3554         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3555         struct hns3_pf *pf = &hns->pf;
3556         uint32_t tc_num = hns3_get_tc_num(hw);
3557         uint32_t half_mps = pf->mps >> 1;
3558         struct hns3_priv_buf *priv;
3559         uint32_t min_rx_priv;
3560         uint32_t rx_priv;
3561         uint8_t i;
3562
3563         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3564         if (tc_num)
3565                 rx_priv = rx_priv / tc_num;
3566
3567         if (tc_num <= NEED_RESERVE_TC_NUM)
3568                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3569
3570         /*
3571          * Minimum value of private buffer in rx direction (min_rx_priv) is
3572          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3573          * buffer if rx_priv is greater than min_rx_priv.
3574          */
3575         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3576                         COMPENSATE_HALF_MPS_NUM * half_mps;
3577         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3578         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3579         if (rx_priv < min_rx_priv)
3580                 return false;
3581
3582         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3583                 priv = &buf_alloc->priv_buf[i];
3584                 priv->enable = 0;
3585                 priv->wl.low = 0;
3586                 priv->wl.high = 0;
3587                 priv->buf_size = 0;
3588
3589                 if (!(hw->hw_tc_map & BIT(i)))
3590                         continue;
3591
3592                 priv->enable = 1;
3593                 priv->buf_size = rx_priv;
3594                 priv->wl.high = rx_priv - pf->dv_buf_size;
3595                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3596         }
3597
3598         buf_alloc->s_buf.buf_size = 0;
3599
3600         return true;
3601 }
3602
3603 /*
3604  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3605  * @hw: pointer to struct hns3_hw
3606  * @buf_alloc: pointer to buffer calculation data
3607  * @return: 0: calculate sucessful, negative: fail
3608  */
3609 static int
3610 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3611 {
3612         /* When DCB is not supported, rx private buffer is not allocated. */
3613         if (!hns3_dev_get_support(hw, DCB)) {
3614                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3615                 struct hns3_pf *pf = &hns->pf;
3616                 uint32_t rx_all = pf->pkt_buf_size;
3617
3618                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3619                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3620                         return -ENOMEM;
3621
3622                 return 0;
3623         }
3624
3625         /*
3626          * Try to allocate privated packet buffer for all TCs without share
3627          * buffer.
3628          */
3629         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3630                 return 0;
3631
3632         /*
3633          * Try to allocate privated packet buffer for all TCs with share
3634          * buffer.
3635          */
3636         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3637                 return 0;
3638
3639         /*
3640          * For different application scenes, the enabled port number, TC number
3641          * and no_drop TC number are different. In order to obtain the better
3642          * performance, software could allocate the buffer size and configure
3643          * the waterline by trying to decrease the private buffer size according
3644          * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
3645          * enabled tc.
3646          */
3647         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3648                 return 0;
3649
3650         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3651                 return 0;
3652
3653         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3654                 return 0;
3655
3656         return -ENOMEM;
3657 }
3658
3659 static int
3660 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3661 {
3662         struct hns3_rx_priv_buff_cmd *req;
3663         struct hns3_cmd_desc desc;
3664         uint32_t buf_size;
3665         int ret;
3666         int i;
3667
3668         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3669         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3670
3671         /* Alloc private buffer TCs */
3672         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3673                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3674
3675                 req->buf_num[i] =
3676                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3677                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3678         }
3679
3680         buf_size = buf_alloc->s_buf.buf_size;
3681         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3682                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3683
3684         ret = hns3_cmd_send(hw, &desc, 1);
3685         if (ret)
3686                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3687
3688         return ret;
3689 }
3690
3691 static int
3692 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3693 {
3694 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3695         struct hns3_rx_priv_wl_buf *req;
3696         struct hns3_priv_buf *priv;
3697         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3698         int i, j;
3699         int ret;
3700
3701         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3702                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3703                                           false);
3704                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3705
3706                 /* The first descriptor set the NEXT bit to 1 */
3707                 if (i == 0)
3708                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3709                 else
3710                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3711
3712                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3713                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3714
3715                         priv = &buf_alloc->priv_buf[idx];
3716                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3717                                                         HNS3_BUF_UNIT_S);
3718                         req->tc_wl[j].high |=
3719                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3720                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3721                                                         HNS3_BUF_UNIT_S);
3722                         req->tc_wl[j].low |=
3723                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3724                 }
3725         }
3726
3727         /* Send 2 descriptor at one time */
3728         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3729         if (ret)
3730                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3731                              ret);
3732         return ret;
3733 }
3734
3735 static int
3736 hns3_common_thrd_config(struct hns3_hw *hw,
3737                         struct hns3_pkt_buf_alloc *buf_alloc)
3738 {
3739 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3740         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3741         struct hns3_rx_com_thrd *req;
3742         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3743         struct hns3_tc_thrd *tc;
3744         int tc_idx;
3745         int i, j;
3746         int ret;
3747
3748         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3749                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3750                                           false);
3751                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3752
3753                 /* The first descriptor set the NEXT bit to 1 */
3754                 if (i == 0)
3755                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3756                 else
3757                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3758
3759                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3760                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3761                         tc = &s_buf->tc_thrd[tc_idx];
3762
3763                         req->com_thrd[j].high =
3764                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3765                         req->com_thrd[j].high |=
3766                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3767                         req->com_thrd[j].low =
3768                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3769                         req->com_thrd[j].low |=
3770                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3771                 }
3772         }
3773
3774         /* Send 2 descriptors at one time */
3775         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3776         if (ret)
3777                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3778
3779         return ret;
3780 }
3781
3782 static int
3783 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3784 {
3785         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3786         struct hns3_rx_com_wl *req;
3787         struct hns3_cmd_desc desc;
3788         int ret;
3789
3790         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3791
3792         req = (struct hns3_rx_com_wl *)desc.data;
3793         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3794         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3795
3796         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3797         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3798
3799         ret = hns3_cmd_send(hw, &desc, 1);
3800         if (ret)
3801                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3802
3803         return ret;
3804 }
3805
3806 int
3807 hns3_buffer_alloc(struct hns3_hw *hw)
3808 {
3809         struct hns3_pkt_buf_alloc pkt_buf;
3810         int ret;
3811
3812         memset(&pkt_buf, 0, sizeof(pkt_buf));
3813         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3814         if (ret) {
3815                 PMD_INIT_LOG(ERR,
3816                              "could not calc tx buffer size for all TCs %d",
3817                              ret);
3818                 return ret;
3819         }
3820
3821         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3822         if (ret) {
3823                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3824                 return ret;
3825         }
3826
3827         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3828         if (ret) {
3829                 PMD_INIT_LOG(ERR,
3830                              "could not calc rx priv buffer size for all TCs %d",
3831                              ret);
3832                 return ret;
3833         }
3834
3835         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3836         if (ret) {
3837                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3838                 return ret;
3839         }
3840
3841         if (hns3_dev_get_support(hw, DCB)) {
3842                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3843                 if (ret) {
3844                         PMD_INIT_LOG(ERR,
3845                                      "could not configure rx private waterline %d",
3846                                      ret);
3847                         return ret;
3848                 }
3849
3850                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3851                 if (ret) {
3852                         PMD_INIT_LOG(ERR,
3853                                      "could not configure common threshold %d",
3854                                      ret);
3855                         return ret;
3856                 }
3857         }
3858
3859         ret = hns3_common_wl_config(hw, &pkt_buf);
3860         if (ret)
3861                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3862                              ret);
3863
3864         return ret;
3865 }
3866
3867 static int
3868 hns3_mac_init(struct hns3_hw *hw)
3869 {
3870         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3871         struct hns3_mac *mac = &hw->mac;
3872         struct hns3_pf *pf = &hns->pf;
3873         int ret;
3874
3875         pf->support_sfp_query = true;
3876         mac->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
3877         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3878         if (ret) {
3879                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3880                 return ret;
3881         }
3882
3883         mac->link_status = RTE_ETH_LINK_DOWN;
3884
3885         return hns3_config_mtu(hw, pf->mps);
3886 }
3887
3888 static int
3889 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3890 {
3891 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3892 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3893 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3894 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3895         int return_status;
3896
3897         if (cmdq_resp) {
3898                 PMD_INIT_LOG(ERR,
3899                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
3900                              cmdq_resp);
3901                 return -EIO;
3902         }
3903
3904         switch (resp_code) {
3905         case HNS3_ETHERTYPE_SUCCESS_ADD:
3906         case HNS3_ETHERTYPE_ALREADY_ADD:
3907                 return_status = 0;
3908                 break;
3909         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3910                 PMD_INIT_LOG(ERR,
3911                              "add mac ethertype failed for manager table overflow.");
3912                 return_status = -EIO;
3913                 break;
3914         case HNS3_ETHERTYPE_KEY_CONFLICT:
3915                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3916                 return_status = -EIO;
3917                 break;
3918         default:
3919                 PMD_INIT_LOG(ERR,
3920                              "add mac ethertype failed for undefined, code=%u.",
3921                              resp_code);
3922                 return_status = -EIO;
3923                 break;
3924         }
3925
3926         return return_status;
3927 }
3928
3929 static int
3930 hns3_add_mgr_tbl(struct hns3_hw *hw,
3931                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3932 {
3933         struct hns3_cmd_desc desc;
3934         uint8_t resp_code;
3935         uint16_t retval;
3936         int ret;
3937
3938         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3939         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3940
3941         ret = hns3_cmd_send(hw, &desc, 1);
3942         if (ret) {
3943                 PMD_INIT_LOG(ERR,
3944                              "add mac ethertype failed for cmd_send, ret =%d.",
3945                              ret);
3946                 return ret;
3947         }
3948
3949         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3950         retval = rte_le_to_cpu_16(desc.retval);
3951
3952         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3953 }
3954
3955 static void
3956 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3957                      int *table_item_num)
3958 {
3959         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3960
3961         /*
3962          * In current version, we add one item in management table as below:
3963          * 0x0180C200000E -- LLDP MC address
3964          */
3965         tbl = mgr_table;
3966         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3967         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3968         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3969         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3970         tbl->i_port_bitmap = 0x1;
3971         *table_item_num = 1;
3972 }
3973
3974 static int
3975 hns3_init_mgr_tbl(struct hns3_hw *hw)
3976 {
3977 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3978         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3979         int table_item_num;
3980         int ret;
3981         int i;
3982
3983         memset(mgr_table, 0, sizeof(mgr_table));
3984         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3985         for (i = 0; i < table_item_num; i++) {
3986                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3987                 if (ret) {
3988                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3989                                      ret);
3990                         return ret;
3991                 }
3992         }
3993
3994         return 0;
3995 }
3996
3997 static void
3998 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3999                         bool en_mc, bool en_bc, int vport_id)
4000 {
4001         if (!param)
4002                 return;
4003
4004         memset(param, 0, sizeof(struct hns3_promisc_param));
4005         if (en_uc)
4006                 param->enable = HNS3_PROMISC_EN_UC;
4007         if (en_mc)
4008                 param->enable |= HNS3_PROMISC_EN_MC;
4009         if (en_bc)
4010                 param->enable |= HNS3_PROMISC_EN_BC;
4011         param->vf_id = vport_id;
4012 }
4013
4014 static int
4015 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4016 {
4017         struct hns3_promisc_cfg_cmd *req;
4018         struct hns3_cmd_desc desc;
4019         int ret;
4020
4021         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4022
4023         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4024         req->vf_id = param->vf_id;
4025         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4026             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4027
4028         ret = hns3_cmd_send(hw, &desc, 1);
4029         if (ret)
4030                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4031
4032         return ret;
4033 }
4034
4035 static int
4036 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4037 {
4038         struct hns3_promisc_param param;
4039         bool en_bc_pmc = true;
4040         uint8_t vf_id;
4041
4042         /*
4043          * In current version VF is not supported when PF is driven by DPDK
4044          * driver, just need to configure parameters for PF vport.
4045          */
4046         vf_id = HNS3_PF_FUNC_ID;
4047
4048         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4049         return hns3_cmd_set_promisc_mode(hw, &param);
4050 }
4051
4052 static int
4053 hns3_promisc_init(struct hns3_hw *hw)
4054 {
4055         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4056         struct hns3_pf *pf = &hns->pf;
4057         struct hns3_promisc_param param;
4058         uint16_t func_id;
4059         int ret;
4060
4061         ret = hns3_set_promisc_mode(hw, false, false);
4062         if (ret) {
4063                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4064                 return ret;
4065         }
4066
4067         /*
4068          * In current version VFs are not supported when PF is driven by DPDK
4069          * driver. After PF has been taken over by DPDK, the original VF will
4070          * be invalid. So, there is a possibility of entry residues. It should
4071          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4072          * during init.
4073          */
4074         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4075                 hns3_promisc_param_init(&param, false, false, false, func_id);
4076                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4077                 if (ret) {
4078                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4079                                         " ret = %d", func_id, ret);
4080                         return ret;
4081                 }
4082         }
4083
4084         return 0;
4085 }
4086
4087 static void
4088 hns3_promisc_uninit(struct hns3_hw *hw)
4089 {
4090         struct hns3_promisc_param param;
4091         uint16_t func_id;
4092         int ret;
4093
4094         func_id = HNS3_PF_FUNC_ID;
4095
4096         /*
4097          * In current version VFs are not supported when PF is driven by
4098          * DPDK driver, and VFs' promisc mode status has been cleared during
4099          * init and their status will not change. So just clear PF's promisc
4100          * mode status during uninit.
4101          */
4102         hns3_promisc_param_init(&param, false, false, false, func_id);
4103         ret = hns3_cmd_set_promisc_mode(hw, &param);
4104         if (ret)
4105                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4106                                 " uninit, ret = %d", ret);
4107 }
4108
4109 static int
4110 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4111 {
4112         bool allmulti = dev->data->all_multicast ? true : false;
4113         struct hns3_adapter *hns = dev->data->dev_private;
4114         struct hns3_hw *hw = &hns->hw;
4115         uint64_t offloads;
4116         int err;
4117         int ret;
4118
4119         rte_spinlock_lock(&hw->lock);
4120         ret = hns3_set_promisc_mode(hw, true, true);
4121         if (ret) {
4122                 rte_spinlock_unlock(&hw->lock);
4123                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4124                          ret);
4125                 return ret;
4126         }
4127
4128         /*
4129          * When promiscuous mode was enabled, disable the vlan filter to let
4130          * all packets coming in in the receiving direction.
4131          */
4132         offloads = dev->data->dev_conf.rxmode.offloads;
4133         if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
4134                 ret = hns3_enable_vlan_filter(hns, false);
4135                 if (ret) {
4136                         hns3_err(hw, "failed to enable promiscuous mode due to "
4137                                      "failure to disable vlan filter, ret = %d",
4138                                  ret);
4139                         err = hns3_set_promisc_mode(hw, false, allmulti);
4140                         if (err)
4141                                 hns3_err(hw, "failed to restore promiscuous "
4142                                          "status after disable vlan filter "
4143                                          "failed during enabling promiscuous "
4144                                          "mode, ret = %d", ret);
4145                 }
4146         }
4147
4148         rte_spinlock_unlock(&hw->lock);
4149
4150         return ret;
4151 }
4152
4153 static int
4154 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4155 {
4156         bool allmulti = dev->data->all_multicast ? true : false;
4157         struct hns3_adapter *hns = dev->data->dev_private;
4158         struct hns3_hw *hw = &hns->hw;
4159         uint64_t offloads;
4160         int err;
4161         int ret;
4162
4163         /* If now in all_multicast mode, must remain in all_multicast mode. */
4164         rte_spinlock_lock(&hw->lock);
4165         ret = hns3_set_promisc_mode(hw, false, allmulti);
4166         if (ret) {
4167                 rte_spinlock_unlock(&hw->lock);
4168                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4169                          ret);
4170                 return ret;
4171         }
4172         /* when promiscuous mode was disabled, restore the vlan filter status */
4173         offloads = dev->data->dev_conf.rxmode.offloads;
4174         if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
4175                 ret = hns3_enable_vlan_filter(hns, true);
4176                 if (ret) {
4177                         hns3_err(hw, "failed to disable promiscuous mode due to"
4178                                  " failure to restore vlan filter, ret = %d",
4179                                  ret);
4180                         err = hns3_set_promisc_mode(hw, true, true);
4181                         if (err)
4182                                 hns3_err(hw, "failed to restore promiscuous "
4183                                          "status after enabling vlan filter "
4184                                          "failed during disabling promiscuous "
4185                                          "mode, ret = %d", ret);
4186                 }
4187         }
4188         rte_spinlock_unlock(&hw->lock);
4189
4190         return ret;
4191 }
4192
4193 static int
4194 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4195 {
4196         struct hns3_adapter *hns = dev->data->dev_private;
4197         struct hns3_hw *hw = &hns->hw;
4198         int ret;
4199
4200         if (dev->data->promiscuous)
4201                 return 0;
4202
4203         rte_spinlock_lock(&hw->lock);
4204         ret = hns3_set_promisc_mode(hw, false, true);
4205         rte_spinlock_unlock(&hw->lock);
4206         if (ret)
4207                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4208                          ret);
4209
4210         return ret;
4211 }
4212
4213 static int
4214 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4215 {
4216         struct hns3_adapter *hns = dev->data->dev_private;
4217         struct hns3_hw *hw = &hns->hw;
4218         int ret;
4219
4220         /* If now in promiscuous mode, must remain in all_multicast mode. */
4221         if (dev->data->promiscuous)
4222                 return 0;
4223
4224         rte_spinlock_lock(&hw->lock);
4225         ret = hns3_set_promisc_mode(hw, false, false);
4226         rte_spinlock_unlock(&hw->lock);
4227         if (ret)
4228                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4229                          ret);
4230
4231         return ret;
4232 }
4233
4234 static int
4235 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4236 {
4237         struct hns3_hw *hw = &hns->hw;
4238         bool allmulti = hw->data->all_multicast ? true : false;
4239         int ret;
4240
4241         if (hw->data->promiscuous) {
4242                 ret = hns3_set_promisc_mode(hw, true, true);
4243                 if (ret)
4244                         hns3_err(hw, "failed to restore promiscuous mode, "
4245                                  "ret = %d", ret);
4246                 return ret;
4247         }
4248
4249         ret = hns3_set_promisc_mode(hw, false, allmulti);
4250         if (ret)
4251                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4252                          ret);
4253         return ret;
4254 }
4255
4256 static int
4257 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4258 {
4259         struct hns3_sfp_info_cmd *resp;
4260         struct hns3_cmd_desc desc;
4261         int ret;
4262
4263         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4264         resp = (struct hns3_sfp_info_cmd *)desc.data;
4265         resp->query_type = HNS3_ACTIVE_QUERY;
4266
4267         ret = hns3_cmd_send(hw, &desc, 1);
4268         if (ret == -EOPNOTSUPP) {
4269                 hns3_warn(hw, "firmware does not support get SFP info,"
4270                           " ret = %d.", ret);
4271                 return ret;
4272         } else if (ret) {
4273                 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4274                 return ret;
4275         }
4276
4277         /*
4278          * In some case, the speed of MAC obtained from firmware may be 0, it
4279          * shouldn't be set to mac->speed.
4280          */
4281         if (!rte_le_to_cpu_32(resp->sfp_speed))
4282                 return 0;
4283
4284         mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4285         /*
4286          * if resp->supported_speed is 0, it means it's an old version
4287          * firmware, do not update these params.
4288          */
4289         if (resp->supported_speed) {
4290                 mac_info->query_type = HNS3_ACTIVE_QUERY;
4291                 mac_info->supported_speed =
4292                                         rte_le_to_cpu_32(resp->supported_speed);
4293                 mac_info->support_autoneg = resp->autoneg_ability;
4294                 mac_info->link_autoneg = (resp->autoneg == 0) ? RTE_ETH_LINK_FIXED
4295                                         : RTE_ETH_LINK_AUTONEG;
4296         } else {
4297                 mac_info->query_type = HNS3_DEFAULT_QUERY;
4298         }
4299
4300         return 0;
4301 }
4302
4303 static uint8_t
4304 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4305 {
4306         if (!(speed == RTE_ETH_SPEED_NUM_10M || speed == RTE_ETH_SPEED_NUM_100M))
4307                 duplex = RTE_ETH_LINK_FULL_DUPLEX;
4308
4309         return duplex;
4310 }
4311
4312 static int
4313 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4314 {
4315         struct hns3_mac *mac = &hw->mac;
4316         int ret;
4317
4318         duplex = hns3_check_speed_dup(duplex, speed);
4319         if (mac->link_speed == speed && mac->link_duplex == duplex)
4320                 return 0;
4321
4322         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4323         if (ret)
4324                 return ret;
4325
4326         ret = hns3_port_shaper_update(hw, speed);
4327         if (ret)
4328                 return ret;
4329
4330         mac->link_speed = speed;
4331         mac->link_duplex = duplex;
4332
4333         return 0;
4334 }
4335
4336 static int
4337 hns3_update_fiber_link_info(struct hns3_hw *hw)
4338 {
4339         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4340         struct hns3_mac *mac = &hw->mac;
4341         struct hns3_mac mac_info;
4342         int ret;
4343
4344         /* If firmware do not support get SFP/qSFP speed, return directly */
4345         if (!pf->support_sfp_query)
4346                 return 0;
4347
4348         memset(&mac_info, 0, sizeof(struct hns3_mac));
4349         ret = hns3_get_sfp_info(hw, &mac_info);
4350         if (ret == -EOPNOTSUPP) {
4351                 pf->support_sfp_query = false;
4352                 return ret;
4353         } else if (ret)
4354                 return ret;
4355
4356         /* Do nothing if no SFP */
4357         if (mac_info.link_speed == RTE_ETH_SPEED_NUM_NONE)
4358                 return 0;
4359
4360         /*
4361          * If query_type is HNS3_ACTIVE_QUERY, it is no need
4362          * to reconfigure the speed of MAC. Otherwise, it indicates
4363          * that the current firmware only supports to obtain the
4364          * speed of the SFP, and the speed of MAC needs to reconfigure.
4365          */
4366         mac->query_type = mac_info.query_type;
4367         if (mac->query_type == HNS3_ACTIVE_QUERY) {
4368                 if (mac_info.link_speed != mac->link_speed) {
4369                         ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4370                         if (ret)
4371                                 return ret;
4372                 }
4373
4374                 mac->link_speed = mac_info.link_speed;
4375                 mac->supported_speed = mac_info.supported_speed;
4376                 mac->support_autoneg = mac_info.support_autoneg;
4377                 mac->link_autoneg = mac_info.link_autoneg;
4378
4379                 return 0;
4380         }
4381
4382         /* Config full duplex for SFP */
4383         return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4384                                       RTE_ETH_LINK_FULL_DUPLEX);
4385 }
4386
4387 static void
4388 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4389 {
4390 #define HNS3_PHY_SUPPORTED_SPEED_MASK   0x2f
4391
4392         struct hns3_phy_params_bd0_cmd *req;
4393         uint32_t supported;
4394
4395         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4396         mac->link_speed = rte_le_to_cpu_32(req->speed);
4397         mac->link_duplex = hns3_get_bit(req->duplex,
4398                                            HNS3_PHY_DUPLEX_CFG_B);
4399         mac->link_autoneg = hns3_get_bit(req->autoneg,
4400                                            HNS3_PHY_AUTONEG_CFG_B);
4401         mac->advertising = rte_le_to_cpu_32(req->advertising);
4402         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4403         supported = rte_le_to_cpu_32(req->supported);
4404         mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4405         mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4406 }
4407
4408 static int
4409 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4410 {
4411         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4412         uint16_t i;
4413         int ret;
4414
4415         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4416                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4417                                           true);
4418                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4419         }
4420         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4421
4422         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4423         if (ret) {
4424                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4425                 return ret;
4426         }
4427
4428         hns3_parse_copper_phy_params(desc, mac);
4429
4430         return 0;
4431 }
4432
4433 static int
4434 hns3_update_copper_link_info(struct hns3_hw *hw)
4435 {
4436         struct hns3_mac *mac = &hw->mac;
4437         struct hns3_mac mac_info;
4438         int ret;
4439
4440         memset(&mac_info, 0, sizeof(struct hns3_mac));
4441         ret = hns3_get_copper_phy_params(hw, &mac_info);
4442         if (ret)
4443                 return ret;
4444
4445         if (mac_info.link_speed != mac->link_speed) {
4446                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4447                 if (ret)
4448                         return ret;
4449         }
4450
4451         mac->link_speed = mac_info.link_speed;
4452         mac->link_duplex = mac_info.link_duplex;
4453         mac->link_autoneg = mac_info.link_autoneg;
4454         mac->supported_speed = mac_info.supported_speed;
4455         mac->advertising = mac_info.advertising;
4456         mac->lp_advertising = mac_info.lp_advertising;
4457         mac->support_autoneg = mac_info.support_autoneg;
4458
4459         return 0;
4460 }
4461
4462 static int
4463 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4464 {
4465         struct hns3_adapter *hns = eth_dev->data->dev_private;
4466         struct hns3_hw *hw = &hns->hw;
4467         int ret = 0;
4468
4469         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4470                 ret = hns3_update_copper_link_info(hw);
4471         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4472                 ret = hns3_update_fiber_link_info(hw);
4473
4474         return ret;
4475 }
4476
4477 static int
4478 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4479 {
4480         struct hns3_config_mac_mode_cmd *req;
4481         struct hns3_cmd_desc desc;
4482         uint32_t loop_en = 0;
4483         uint8_t val = 0;
4484         int ret;
4485
4486         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4487
4488         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4489         if (enable)
4490                 val = 1;
4491         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4492         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4493         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4494         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4495         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4496         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4497         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4498         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4499         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4500         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4501
4502         /*
4503          * If RTE_ETH_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4504          * when receiving frames. Otherwise, CRC will be stripped.
4505          */
4506         if (hw->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
4507                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4508         else
4509                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4510         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4511         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4512         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4513         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4514
4515         ret = hns3_cmd_send(hw, &desc, 1);
4516         if (ret)
4517                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4518
4519         return ret;
4520 }
4521
4522 static int
4523 hns3_get_mac_link_status(struct hns3_hw *hw)
4524 {
4525         struct hns3_link_status_cmd *req;
4526         struct hns3_cmd_desc desc;
4527         int link_status;
4528         int ret;
4529
4530         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4531         ret = hns3_cmd_send(hw, &desc, 1);
4532         if (ret) {
4533                 hns3_err(hw, "get link status cmd failed %d", ret);
4534                 return RTE_ETH_LINK_DOWN;
4535         }
4536
4537         req = (struct hns3_link_status_cmd *)desc.data;
4538         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4539
4540         return !!link_status;
4541 }
4542
4543 static bool
4544 hns3_update_link_status(struct hns3_hw *hw)
4545 {
4546         int state;
4547
4548         state = hns3_get_mac_link_status(hw);
4549         if (state != hw->mac.link_status) {
4550                 hw->mac.link_status = state;
4551                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4552                 return true;
4553         }
4554
4555         return false;
4556 }
4557
4558 void
4559 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4560 {
4561         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4562         struct rte_eth_link new_link;
4563         int ret;
4564
4565         if (query)
4566                 hns3_update_port_link_info(dev);
4567
4568         memset(&new_link, 0, sizeof(new_link));
4569         hns3_setup_linkstatus(dev, &new_link);
4570
4571         ret = rte_eth_linkstatus_set(dev, &new_link);
4572         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4573                 hns3_start_report_lse(dev);
4574 }
4575
4576 static void
4577 hns3_service_handler(void *param)
4578 {
4579         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4580         struct hns3_adapter *hns = eth_dev->data->dev_private;
4581         struct hns3_hw *hw = &hns->hw;
4582
4583         if (!hns3_is_reset_pending(hns))
4584                 hns3_update_linkstatus_and_event(hw, true);
4585         else
4586                 hns3_warn(hw, "Cancel the query when reset is pending");
4587
4588         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4589 }
4590
4591 static int
4592 hns3_init_hardware(struct hns3_adapter *hns)
4593 {
4594         struct hns3_hw *hw = &hns->hw;
4595         int ret;
4596
4597         ret = hns3_map_tqp(hw);
4598         if (ret) {
4599                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4600                 return ret;
4601         }
4602
4603         ret = hns3_init_umv_space(hw);
4604         if (ret) {
4605                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4606                 return ret;
4607         }
4608
4609         ret = hns3_mac_init(hw);
4610         if (ret) {
4611                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4612                 goto err_mac_init;
4613         }
4614
4615         ret = hns3_init_mgr_tbl(hw);
4616         if (ret) {
4617                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4618                 goto err_mac_init;
4619         }
4620
4621         ret = hns3_promisc_init(hw);
4622         if (ret) {
4623                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4624                              ret);
4625                 goto err_mac_init;
4626         }
4627
4628         ret = hns3_init_vlan_config(hns);
4629         if (ret) {
4630                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4631                 goto err_mac_init;
4632         }
4633
4634         ret = hns3_dcb_init(hw);
4635         if (ret) {
4636                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4637                 goto err_mac_init;
4638         }
4639
4640         ret = hns3_init_fd_config(hns);
4641         if (ret) {
4642                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4643                 goto err_mac_init;
4644         }
4645
4646         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4647         if (ret) {
4648                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4649                 goto err_mac_init;
4650         }
4651
4652         ret = hns3_config_gro(hw, false);
4653         if (ret) {
4654                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4655                 goto err_mac_init;
4656         }
4657
4658         /*
4659          * In the initialization clearing the all hardware mapping relationship
4660          * configurations between queues and interrupt vectors is needed, so
4661          * some error caused by the residual configurations, such as the
4662          * unexpected interrupt, can be avoid.
4663          */
4664         ret = hns3_init_ring_with_vector(hw);
4665         if (ret) {
4666                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4667                 goto err_mac_init;
4668         }
4669
4670         return 0;
4671
4672 err_mac_init:
4673         hns3_uninit_umv_space(hw);
4674         return ret;
4675 }
4676
4677 static int
4678 hns3_clear_hw(struct hns3_hw *hw)
4679 {
4680         struct hns3_cmd_desc desc;
4681         int ret;
4682
4683         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4684
4685         ret = hns3_cmd_send(hw, &desc, 1);
4686         if (ret && ret != -EOPNOTSUPP)
4687                 return ret;
4688
4689         return 0;
4690 }
4691
4692 static void
4693 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4694 {
4695         uint32_t val;
4696
4697         /*
4698          * The new firmware support report more hardware error types by
4699          * msix mode. These errors are defined as RAS errors in hardware
4700          * and belong to a different type from the MSI-x errors processed
4701          * by the network driver.
4702          *
4703          * Network driver should open the new error report on initialization.
4704          */
4705         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4706         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4707         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4708 }
4709
4710 static uint32_t
4711 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
4712 {
4713         struct hns3_mac *mac = &hw->mac;
4714
4715         switch (mac->link_speed) {
4716         case RTE_ETH_SPEED_NUM_1G:
4717                 return HNS3_FIBER_LINK_SPEED_1G_BIT;
4718         case RTE_ETH_SPEED_NUM_10G:
4719                 return HNS3_FIBER_LINK_SPEED_10G_BIT;
4720         case RTE_ETH_SPEED_NUM_25G:
4721                 return HNS3_FIBER_LINK_SPEED_25G_BIT;
4722         case RTE_ETH_SPEED_NUM_40G:
4723                 return HNS3_FIBER_LINK_SPEED_40G_BIT;
4724         case RTE_ETH_SPEED_NUM_50G:
4725                 return HNS3_FIBER_LINK_SPEED_50G_BIT;
4726         case RTE_ETH_SPEED_NUM_100G:
4727                 return HNS3_FIBER_LINK_SPEED_100G_BIT;
4728         case RTE_ETH_SPEED_NUM_200G:
4729                 return HNS3_FIBER_LINK_SPEED_200G_BIT;
4730         default:
4731                 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
4732                 return 0;
4733         }
4734 }
4735
4736 /*
4737  * Validity of supported_speed for firber and copper media type can be
4738  * guaranteed by the following policy:
4739  * Copper:
4740  *       Although the initialization of the phy in the firmware may not be
4741  *       completed, the firmware can guarantees that the supported_speed is
4742  *       an valid value.
4743  * Firber:
4744  *       If the version of firmware supports the acitive query way of the
4745  *       HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
4746  *       through it. If unsupported, use the SFP's speed as the value of the
4747  *       supported_speed.
4748  */
4749 static int
4750 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
4751 {
4752         struct hns3_adapter *hns = eth_dev->data->dev_private;
4753         struct hns3_hw *hw = &hns->hw;
4754         struct hns3_mac *mac = &hw->mac;
4755         int ret;
4756
4757         ret = hns3_update_link_info(eth_dev);
4758         if (ret)
4759                 return ret;
4760
4761         if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
4762                 /*
4763                  * Some firmware does not support the report of supported_speed,
4764                  * and only report the effective speed of SFP. In this case, it
4765                  * is necessary to use the SFP's speed as the supported_speed.
4766                  */
4767                 if (mac->supported_speed == 0)
4768                         mac->supported_speed =
4769                                 hns3_set_firber_default_support_speed(hw);
4770         }
4771
4772         return 0;
4773 }
4774
4775 static void
4776 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
4777 {
4778         struct hns3_mac *mac = &hns->hw.mac;
4779
4780         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
4781                 hns->pf.support_fc_autoneg = true;
4782                 return;
4783         }
4784
4785         /*
4786          * Flow control auto-negotiation requires the cooperation of the driver
4787          * and firmware. Currently, the optical port does not support flow
4788          * control auto-negotiation.
4789          */
4790         hns->pf.support_fc_autoneg = false;
4791 }
4792
4793 static int
4794 hns3_init_pf(struct rte_eth_dev *eth_dev)
4795 {
4796         struct rte_device *dev = eth_dev->device;
4797         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4798         struct hns3_adapter *hns = eth_dev->data->dev_private;
4799         struct hns3_hw *hw = &hns->hw;
4800         int ret;
4801
4802         PMD_INIT_FUNC_TRACE();
4803
4804         /* Get hardware io base address from pcie BAR2 IO space */
4805         hw->io_base = pci_dev->mem_resource[2].addr;
4806
4807         /* Firmware command queue initialize */
4808         ret = hns3_cmd_init_queue(hw);
4809         if (ret) {
4810                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4811                 goto err_cmd_init_queue;
4812         }
4813
4814         hns3_clear_all_event_cause(hw);
4815
4816         /* Firmware command initialize */
4817         ret = hns3_cmd_init(hw);
4818         if (ret) {
4819                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4820                 goto err_cmd_init;
4821         }
4822
4823         hns3_tx_push_init(eth_dev);
4824
4825         /*
4826          * To ensure that the hardware environment is clean during
4827          * initialization, the driver actively clear the hardware environment
4828          * during initialization, including PF and corresponding VFs' vlan, mac,
4829          * flow table configurations, etc.
4830          */
4831         ret = hns3_clear_hw(hw);
4832         if (ret) {
4833                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4834                 goto err_cmd_init;
4835         }
4836
4837         /* Hardware statistics of imissed registers cleared. */
4838         ret = hns3_update_imissed_stats(hw, true);
4839         if (ret) {
4840                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
4841                 goto err_cmd_init;
4842         }
4843
4844         hns3_config_all_msix_error(hw, true);
4845
4846         ret = rte_intr_callback_register(pci_dev->intr_handle,
4847                                          hns3_interrupt_handler,
4848                                          eth_dev);
4849         if (ret) {
4850                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4851                 goto err_intr_callback_register;
4852         }
4853
4854         ret = hns3_ptp_init(hw);
4855         if (ret)
4856                 goto err_get_config;
4857
4858         /* Enable interrupt */
4859         rte_intr_enable(pci_dev->intr_handle);
4860         hns3_pf_enable_irq0(hw);
4861
4862         /* Get configuration */
4863         ret = hns3_get_configuration(hw);
4864         if (ret) {
4865                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4866                 goto err_get_config;
4867         }
4868
4869         ret = hns3_tqp_stats_init(hw);
4870         if (ret)
4871                 goto err_get_config;
4872
4873         ret = hns3_init_hardware(hns);
4874         if (ret) {
4875                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4876                 goto err_init_hw;
4877         }
4878
4879         /* Initialize flow director filter list & hash */
4880         ret = hns3_fdir_filter_init(hns);
4881         if (ret) {
4882                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4883                 goto err_fdir;
4884         }
4885
4886         hns3_rss_set_default_args(hw);
4887
4888         ret = hns3_enable_hw_error_intr(hns, true);
4889         if (ret) {
4890                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4891                              ret);
4892                 goto err_enable_intr;
4893         }
4894
4895         ret = hns3_get_port_supported_speed(eth_dev);
4896         if (ret) {
4897                 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
4898                              "by device, ret = %d.", ret);
4899                 goto err_supported_speed;
4900         }
4901
4902         hns3_get_fc_autoneg_capability(hns);
4903
4904         hns3_tm_conf_init(eth_dev);
4905
4906         return 0;
4907
4908 err_supported_speed:
4909         (void)hns3_enable_hw_error_intr(hns, false);
4910 err_enable_intr:
4911         hns3_fdir_filter_uninit(hns);
4912 err_fdir:
4913         hns3_uninit_umv_space(hw);
4914 err_init_hw:
4915         hns3_tqp_stats_uninit(hw);
4916 err_get_config:
4917         hns3_pf_disable_irq0(hw);
4918         rte_intr_disable(pci_dev->intr_handle);
4919         hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
4920                              eth_dev);
4921 err_intr_callback_register:
4922 err_cmd_init:
4923         hns3_cmd_uninit(hw);
4924         hns3_cmd_destroy_queue(hw);
4925 err_cmd_init_queue:
4926         hw->io_base = NULL;
4927
4928         return ret;
4929 }
4930
4931 static void
4932 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4933 {
4934         struct hns3_adapter *hns = eth_dev->data->dev_private;
4935         struct rte_device *dev = eth_dev->device;
4936         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4937         struct hns3_hw *hw = &hns->hw;
4938
4939         PMD_INIT_FUNC_TRACE();
4940
4941         hns3_tm_conf_uninit(eth_dev);
4942         hns3_enable_hw_error_intr(hns, false);
4943         hns3_rss_uninit(hns);
4944         (void)hns3_config_gro(hw, false);
4945         hns3_promisc_uninit(hw);
4946         hns3_flow_uninit(eth_dev);
4947         hns3_fdir_filter_uninit(hns);
4948         hns3_uninit_umv_space(hw);
4949         hns3_tqp_stats_uninit(hw);
4950         hns3_config_mac_tnl_int(hw, false);
4951         hns3_pf_disable_irq0(hw);
4952         rte_intr_disable(pci_dev->intr_handle);
4953         hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
4954                              eth_dev);
4955         hns3_config_all_msix_error(hw, false);
4956         hns3_cmd_uninit(hw);
4957         hns3_cmd_destroy_queue(hw);
4958         hw->io_base = NULL;
4959 }
4960
4961 static uint32_t
4962 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
4963 {
4964         uint32_t speed_bit;
4965
4966         switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) {
4967         case RTE_ETH_LINK_SPEED_10M:
4968                 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
4969                 break;
4970         case RTE_ETH_LINK_SPEED_10M_HD:
4971                 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
4972                 break;
4973         case RTE_ETH_LINK_SPEED_100M:
4974                 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
4975                 break;
4976         case RTE_ETH_LINK_SPEED_100M_HD:
4977                 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
4978                 break;
4979         case RTE_ETH_LINK_SPEED_1G:
4980                 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
4981                 break;
4982         default:
4983                 speed_bit = 0;
4984                 break;
4985         }
4986
4987         return speed_bit;
4988 }
4989
4990 static uint32_t
4991 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
4992 {
4993         uint32_t speed_bit;
4994
4995         switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) {
4996         case RTE_ETH_LINK_SPEED_1G:
4997                 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
4998                 break;
4999         case RTE_ETH_LINK_SPEED_10G:
5000                 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
5001                 break;
5002         case RTE_ETH_LINK_SPEED_25G:
5003                 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
5004                 break;
5005         case RTE_ETH_LINK_SPEED_40G:
5006                 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
5007                 break;
5008         case RTE_ETH_LINK_SPEED_50G:
5009                 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
5010                 break;
5011         case RTE_ETH_LINK_SPEED_100G:
5012                 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
5013                 break;
5014         case RTE_ETH_LINK_SPEED_200G:
5015                 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
5016                 break;
5017         default:
5018                 speed_bit = 0;
5019                 break;
5020         }
5021
5022         return speed_bit;
5023 }
5024
5025 static int
5026 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
5027 {
5028         struct hns3_mac *mac = &hw->mac;
5029         uint32_t supported_speed = mac->supported_speed;
5030         uint32_t speed_bit = 0;
5031
5032         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
5033                 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
5034         else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
5035                 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
5036
5037         if (!(speed_bit & supported_speed)) {
5038                 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
5039                          link_speeds);
5040                 return -EINVAL;
5041         }
5042
5043         return 0;
5044 }
5045
5046 static inline uint32_t
5047 hns3_get_link_speed(uint32_t link_speeds)
5048 {
5049         uint32_t speed = RTE_ETH_SPEED_NUM_NONE;
5050
5051         if (link_speeds & RTE_ETH_LINK_SPEED_10M ||
5052             link_speeds & RTE_ETH_LINK_SPEED_10M_HD)
5053                 speed = RTE_ETH_SPEED_NUM_10M;
5054         if (link_speeds & RTE_ETH_LINK_SPEED_100M ||
5055             link_speeds & RTE_ETH_LINK_SPEED_100M_HD)
5056                 speed = RTE_ETH_SPEED_NUM_100M;
5057         if (link_speeds & RTE_ETH_LINK_SPEED_1G)
5058                 speed = RTE_ETH_SPEED_NUM_1G;
5059         if (link_speeds & RTE_ETH_LINK_SPEED_10G)
5060                 speed = RTE_ETH_SPEED_NUM_10G;
5061         if (link_speeds & RTE_ETH_LINK_SPEED_25G)
5062                 speed = RTE_ETH_SPEED_NUM_25G;
5063         if (link_speeds & RTE_ETH_LINK_SPEED_40G)
5064                 speed = RTE_ETH_SPEED_NUM_40G;
5065         if (link_speeds & RTE_ETH_LINK_SPEED_50G)
5066                 speed = RTE_ETH_SPEED_NUM_50G;
5067         if (link_speeds & RTE_ETH_LINK_SPEED_100G)
5068                 speed = RTE_ETH_SPEED_NUM_100G;
5069         if (link_speeds & RTE_ETH_LINK_SPEED_200G)
5070                 speed = RTE_ETH_SPEED_NUM_200G;
5071
5072         return speed;
5073 }
5074
5075 static uint8_t
5076 hns3_get_link_duplex(uint32_t link_speeds)
5077 {
5078         if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) ||
5079             (link_speeds & RTE_ETH_LINK_SPEED_100M_HD))
5080                 return RTE_ETH_LINK_HALF_DUPLEX;
5081         else
5082                 return RTE_ETH_LINK_FULL_DUPLEX;
5083 }
5084
5085 static int
5086 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5087                                 struct hns3_set_link_speed_cfg *cfg)
5088 {
5089         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5090         struct hns3_phy_params_bd0_cmd *req;
5091         uint16_t i;
5092
5093         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5094                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5095                                           false);
5096                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5097         }
5098         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5099         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5100         req->autoneg = cfg->autoneg;
5101
5102         /*
5103          * The full speed capability is used to negotiate when
5104          * auto-negotiation is enabled.
5105          */
5106         if (cfg->autoneg) {
5107                 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5108                                     HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5109                                     HNS3_PHY_LINK_SPEED_100M_BIT |
5110                                     HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5111                                     HNS3_PHY_LINK_SPEED_1000M_BIT;
5112         } else {
5113                 req->speed = cfg->speed;
5114                 req->duplex = cfg->duplex;
5115         }
5116
5117         return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5118 }
5119
5120 static int
5121 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5122 {
5123         struct hns3_config_auto_neg_cmd *req;
5124         struct hns3_cmd_desc desc;
5125         uint32_t flag = 0;
5126         int ret;
5127
5128         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5129
5130         req = (struct hns3_config_auto_neg_cmd *)desc.data;
5131         if (enable)
5132                 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5133         req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5134
5135         ret = hns3_cmd_send(hw, &desc, 1);
5136         if (ret)
5137                 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5138
5139         return ret;
5140 }
5141
5142 static int
5143 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5144                                struct hns3_set_link_speed_cfg *cfg)
5145 {
5146         int ret;
5147
5148         if (hw->mac.support_autoneg) {
5149                 ret = hns3_set_autoneg(hw, cfg->autoneg);
5150                 if (ret) {
5151                         hns3_err(hw, "failed to configure auto-negotiation.");
5152                         return ret;
5153                 }
5154
5155                 /*
5156                  * To enable auto-negotiation, we only need to open the switch
5157                  * of auto-negotiation, then firmware sets all speed
5158                  * capabilities.
5159                  */
5160                 if (cfg->autoneg)
5161                         return 0;
5162         }
5163
5164         /*
5165          * Some hardware doesn't support auto-negotiation, but users may not
5166          * configure link_speeds (default 0), which means auto-negotiation.
5167          * In this case, a warning message need to be printed, instead of
5168          * an error.
5169          */
5170         if (cfg->autoneg) {
5171                 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
5172                 return 0;
5173         }
5174
5175         return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
5176 }
5177
5178 static int
5179 hns3_set_port_link_speed(struct hns3_hw *hw,
5180                          struct hns3_set_link_speed_cfg *cfg)
5181 {
5182         int ret;
5183
5184         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5185 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5186                 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5187                 if (pf->is_tmp_phy)
5188                         return 0;
5189 #endif
5190
5191                 ret = hns3_set_copper_port_link_speed(hw, cfg);
5192                 if (ret) {
5193                         hns3_err(hw, "failed to set copper port link speed,"
5194                                  "ret = %d.", ret);
5195                         return ret;
5196                 }
5197         } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5198                 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5199                 if (ret) {
5200                         hns3_err(hw, "failed to set fiber port link speed,"
5201                                  "ret = %d.", ret);
5202                         return ret;
5203                 }
5204         }
5205
5206         return 0;
5207 }
5208
5209 static int
5210 hns3_apply_link_speed(struct hns3_hw *hw)
5211 {
5212         struct rte_eth_conf *conf = &hw->data->dev_conf;
5213         struct hns3_set_link_speed_cfg cfg;
5214
5215         memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5216         cfg.autoneg = (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) ?
5217                         RTE_ETH_LINK_AUTONEG : RTE_ETH_LINK_FIXED;
5218         if (cfg.autoneg != RTE_ETH_LINK_AUTONEG) {
5219                 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5220                 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5221         }
5222
5223         return hns3_set_port_link_speed(hw, &cfg);
5224 }
5225
5226 static int
5227 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5228 {
5229         struct hns3_hw *hw = &hns->hw;
5230         bool link_en;
5231         int ret;
5232
5233         ret = hns3_update_queue_map_configure(hns);
5234         if (ret) {
5235                 hns3_err(hw, "failed to update queue mapping configuration, ret = %d",
5236                          ret);
5237                 return ret;
5238         }
5239
5240         /* Note: hns3_tm_conf_update must be called after configuring DCB. */
5241         ret = hns3_tm_conf_update(hw);
5242         if (ret) {
5243                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5244                 return ret;
5245         }
5246
5247         hns3_enable_rxd_adv_layout(hw);
5248
5249         ret = hns3_init_queues(hns, reset_queue);
5250         if (ret) {
5251                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5252                 return ret;
5253         }
5254
5255         link_en = hw->set_link_down ? false : true;
5256         ret = hns3_cfg_mac_mode(hw, link_en);
5257         if (ret) {
5258                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5259                 goto err_config_mac_mode;
5260         }
5261
5262         ret = hns3_apply_link_speed(hw);
5263         if (ret)
5264                 goto err_set_link_speed;
5265
5266         return 0;
5267
5268 err_set_link_speed:
5269         (void)hns3_cfg_mac_mode(hw, false);
5270
5271 err_config_mac_mode:
5272         hns3_dev_release_mbufs(hns);
5273         /*
5274          * Here is exception handling, hns3_reset_all_tqps will have the
5275          * corresponding error message if it is handled incorrectly, so it is
5276          * not necessary to check hns3_reset_all_tqps return value, here keep
5277          * ret as the error code causing the exception.
5278          */
5279         (void)hns3_reset_all_tqps(hns);
5280         return ret;
5281 }
5282
5283 static int
5284 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5285 {
5286         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5287         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5288         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5289         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5290         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5291         uint32_t intr_vector;
5292         uint16_t q_id;
5293         int ret;
5294
5295         /*
5296          * hns3 needs a separate interrupt to be used as event interrupt which
5297          * could not be shared with task queue pair, so KERNEL drivers need
5298          * support multiple interrupt vectors.
5299          */
5300         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5301             !rte_intr_cap_multiple(intr_handle))
5302                 return 0;
5303
5304         rte_intr_disable(intr_handle);
5305         intr_vector = hw->used_rx_queues;
5306         /* creates event fd for each intr vector when MSIX is used */
5307         if (rte_intr_efd_enable(intr_handle, intr_vector))
5308                 return -EINVAL;
5309
5310         /* Allocate vector list */
5311         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
5312                                     hw->used_rx_queues)) {
5313                 hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5314                          hw->used_rx_queues);
5315                 ret = -ENOMEM;
5316                 goto alloc_intr_vec_error;
5317         }
5318
5319         if (rte_intr_allow_others(intr_handle)) {
5320                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5321                 base = RTE_INTR_VEC_RXTX_OFFSET;
5322         }
5323
5324         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5325                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5326                                                  HNS3_RING_TYPE_RX, q_id);
5327                 if (ret)
5328                         goto bind_vector_error;
5329
5330                 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
5331                         goto bind_vector_error;
5332                 /*
5333                  * If there are not enough efds (e.g. not enough interrupt),
5334                  * remaining queues will be bond to the last interrupt.
5335                  */
5336                 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
5337                         vec++;
5338         }
5339         rte_intr_enable(intr_handle);
5340         return 0;
5341
5342 bind_vector_error:
5343         rte_intr_vec_list_free(intr_handle);
5344 alloc_intr_vec_error:
5345         rte_intr_efd_disable(intr_handle);
5346         return ret;
5347 }
5348
5349 static int
5350 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5351 {
5352         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5353         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5354         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5355         uint16_t q_id;
5356         int ret;
5357
5358         if (dev->data->dev_conf.intr_conf.rxq == 0)
5359                 return 0;
5360
5361         if (rte_intr_dp_is_en(intr_handle)) {
5362                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5363                         ret = hns3_bind_ring_with_vector(hw,
5364                                 rte_intr_vec_list_index_get(intr_handle,
5365                                                                    q_id),
5366                                 true, HNS3_RING_TYPE_RX, q_id);
5367                         if (ret)
5368                                 return ret;
5369                 }
5370         }
5371
5372         return 0;
5373 }
5374
5375 static void
5376 hns3_restore_filter(struct rte_eth_dev *dev)
5377 {
5378         hns3_restore_rss_filter(dev);
5379 }
5380
5381 static int
5382 hns3_dev_start(struct rte_eth_dev *dev)
5383 {
5384         struct hns3_adapter *hns = dev->data->dev_private;
5385         struct hns3_hw *hw = &hns->hw;
5386         bool old_state = hw->set_link_down;
5387         int ret;
5388
5389         PMD_INIT_FUNC_TRACE();
5390         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5391                 return -EBUSY;
5392
5393         rte_spinlock_lock(&hw->lock);
5394         hw->adapter_state = HNS3_NIC_STARTING;
5395
5396         /*
5397          * If the dev_set_link_down() API has been called, the "set_link_down"
5398          * flag can be cleared by dev_start() API. In addition, the flag should
5399          * also be cleared before calling hns3_do_start() so that MAC can be
5400          * enabled in dev_start stage.
5401          */
5402         hw->set_link_down = false;
5403         ret = hns3_do_start(hns, true);
5404         if (ret)
5405                 goto do_start_fail;
5406
5407         ret = hns3_map_rx_interrupt(dev);
5408         if (ret)
5409                 goto map_rx_inter_err;
5410
5411         /*
5412          * There are three register used to control the status of a TQP
5413          * (contains a pair of Tx queue and Rx queue) in the new version network
5414          * engine. One is used to control the enabling of Tx queue, the other is
5415          * used to control the enabling of Rx queue, and the last is the master
5416          * switch used to control the enabling of the tqp. The Tx register and
5417          * TQP register must be enabled at the same time to enable a Tx queue.
5418          * The same applies to the Rx queue. For the older network engine, this
5419          * function only refresh the enabled flag, and it is used to update the
5420          * status of queue in the dpdk framework.
5421          */
5422         ret = hns3_start_all_txqs(dev);
5423         if (ret)
5424                 goto map_rx_inter_err;
5425
5426         ret = hns3_start_all_rxqs(dev);
5427         if (ret)
5428                 goto start_all_rxqs_fail;
5429
5430         hw->adapter_state = HNS3_NIC_STARTED;
5431         rte_spinlock_unlock(&hw->lock);
5432
5433         hns3_rx_scattered_calc(dev);
5434         hns3_set_rxtx_function(dev);
5435         hns3_mp_req_start_rxtx(dev);
5436
5437         hns3_restore_filter(dev);
5438
5439         /* Enable interrupt of all rx queues before enabling queues */
5440         hns3_dev_all_rx_queue_intr_enable(hw, true);
5441
5442         /*
5443          * After finished the initialization, enable tqps to receive/transmit
5444          * packets and refresh all queue status.
5445          */
5446         hns3_start_tqps(hw);
5447
5448         hns3_tm_dev_start_proc(hw);
5449
5450         if (dev->data->dev_conf.intr_conf.lsc != 0)
5451                 hns3_dev_link_update(dev, 0);
5452         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5453
5454         hns3_info(hw, "hns3 dev start successful!");
5455
5456         return 0;
5457
5458 start_all_rxqs_fail:
5459         hns3_stop_all_txqs(dev);
5460 map_rx_inter_err:
5461         (void)hns3_do_stop(hns);
5462 do_start_fail:
5463         hw->set_link_down = old_state;
5464         hw->adapter_state = HNS3_NIC_CONFIGURED;
5465         rte_spinlock_unlock(&hw->lock);
5466
5467         return ret;
5468 }
5469
5470 static int
5471 hns3_do_stop(struct hns3_adapter *hns)
5472 {
5473         struct hns3_hw *hw = &hns->hw;
5474         int ret;
5475
5476         /*
5477          * The "hns3_do_stop" function will also be called by .stop_service to
5478          * prepare reset. At the time of global or IMP reset, the command cannot
5479          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5480          * accessed during the reset process. So the mbuf can not be released
5481          * during reset and is required to be released after the reset is
5482          * completed.
5483          */
5484         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5485                 hns3_dev_release_mbufs(hns);
5486
5487         ret = hns3_cfg_mac_mode(hw, false);
5488         if (ret)
5489                 return ret;
5490         hw->mac.link_status = RTE_ETH_LINK_DOWN;
5491
5492         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5493                 hns3_configure_all_mac_addr(hns, true);
5494                 ret = hns3_reset_all_tqps(hns);
5495                 if (ret) {
5496                         hns3_err(hw, "failed to reset all queues ret = %d.",
5497                                  ret);
5498                         return ret;
5499                 }
5500         }
5501
5502         return 0;
5503 }
5504
5505 static void
5506 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5507 {
5508         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5509         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5510         struct hns3_adapter *hns = dev->data->dev_private;
5511         struct hns3_hw *hw = &hns->hw;
5512         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5513         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5514         uint16_t q_id;
5515
5516         if (dev->data->dev_conf.intr_conf.rxq == 0)
5517                 return;
5518
5519         /* unmap the ring with vector */
5520         if (rte_intr_allow_others(intr_handle)) {
5521                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5522                 base = RTE_INTR_VEC_RXTX_OFFSET;
5523         }
5524         if (rte_intr_dp_is_en(intr_handle)) {
5525                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5526                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5527                                                          HNS3_RING_TYPE_RX,
5528                                                          q_id);
5529                         if (vec < base + rte_intr_nb_efd_get(intr_handle)
5530                                                                         - 1)
5531                                 vec++;
5532                 }
5533         }
5534         /* Clean datapath event and queue/vec mapping */
5535         rte_intr_efd_disable(intr_handle);
5536         rte_intr_vec_list_free(intr_handle);
5537 }
5538
5539 static int
5540 hns3_dev_stop(struct rte_eth_dev *dev)
5541 {
5542         struct hns3_adapter *hns = dev->data->dev_private;
5543         struct hns3_hw *hw = &hns->hw;
5544
5545         PMD_INIT_FUNC_TRACE();
5546         dev->data->dev_started = 0;
5547
5548         hw->adapter_state = HNS3_NIC_STOPPING;
5549         hns3_set_rxtx_function(dev);
5550         rte_wmb();
5551         /* Disable datapath on secondary process. */
5552         hns3_mp_req_stop_rxtx(dev);
5553         /* Prevent crashes when queues are still in use. */
5554         rte_delay_ms(hw->cfg_max_queues);
5555
5556         rte_spinlock_lock(&hw->lock);
5557         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5558                 hns3_tm_dev_stop_proc(hw);
5559                 hns3_config_mac_tnl_int(hw, false);
5560                 hns3_stop_tqps(hw);
5561                 hns3_do_stop(hns);
5562                 hns3_unmap_rx_interrupt(dev);
5563                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5564         }
5565         hns3_rx_scattered_reset(dev);
5566         rte_eal_alarm_cancel(hns3_service_handler, dev);
5567         hns3_stop_report_lse(dev);
5568         rte_spinlock_unlock(&hw->lock);
5569
5570         return 0;
5571 }
5572
5573 static int
5574 hns3_dev_close(struct rte_eth_dev *eth_dev)
5575 {
5576         struct hns3_adapter *hns = eth_dev->data->dev_private;
5577         struct hns3_hw *hw = &hns->hw;
5578         int ret = 0;
5579
5580         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5581                 hns3_mp_uninit(eth_dev);
5582                 return 0;
5583         }
5584
5585         if (hw->adapter_state == HNS3_NIC_STARTED)
5586                 ret = hns3_dev_stop(eth_dev);
5587
5588         hw->adapter_state = HNS3_NIC_CLOSING;
5589         hns3_reset_abort(hns);
5590         hw->adapter_state = HNS3_NIC_CLOSED;
5591
5592         hns3_configure_all_mc_mac_addr(hns, true);
5593         hns3_remove_all_vlan_table(hns);
5594         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5595         hns3_uninit_pf(eth_dev);
5596         hns3_free_all_queues(eth_dev);
5597         rte_free(hw->reset.wait_data);
5598         hns3_mp_uninit(eth_dev);
5599         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5600
5601         return ret;
5602 }
5603
5604 static void
5605 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5606                                    bool *tx_pause)
5607 {
5608         struct hns3_mac *mac = &hw->mac;
5609         uint32_t advertising = mac->advertising;
5610         uint32_t lp_advertising = mac->lp_advertising;
5611         *rx_pause = false;
5612         *tx_pause = false;
5613
5614         if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5615                 *rx_pause = true;
5616                 *tx_pause = true;
5617         } else if (advertising & lp_advertising &
5618                    HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5619                 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5620                         *rx_pause = true;
5621                 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5622                         *tx_pause = true;
5623         }
5624 }
5625
5626 static enum hns3_fc_mode
5627 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5628 {
5629         enum hns3_fc_mode current_mode;
5630         bool rx_pause = false;
5631         bool tx_pause = false;
5632
5633         switch (hw->mac.media_type) {
5634         case HNS3_MEDIA_TYPE_COPPER:
5635                 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5636                 break;
5637
5638         /*
5639          * Flow control auto-negotiation is not supported for fiber and
5640          * backpalne media type.
5641          */
5642         case HNS3_MEDIA_TYPE_FIBER:
5643         case HNS3_MEDIA_TYPE_BACKPLANE:
5644                 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
5645                 current_mode = hw->requested_fc_mode;
5646                 goto out;
5647         default:
5648                 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
5649                          hw->mac.media_type);
5650                 current_mode = HNS3_FC_NONE;
5651                 goto out;
5652         }
5653
5654         if (rx_pause && tx_pause)
5655                 current_mode = HNS3_FC_FULL;
5656         else if (rx_pause)
5657                 current_mode = HNS3_FC_RX_PAUSE;
5658         else if (tx_pause)
5659                 current_mode = HNS3_FC_TX_PAUSE;
5660         else
5661                 current_mode = HNS3_FC_NONE;
5662
5663 out:
5664         return current_mode;
5665 }
5666
5667 static enum hns3_fc_mode
5668 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
5669 {
5670         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5671         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5672         struct hns3_mac *mac = &hw->mac;
5673
5674         /*
5675          * When the flow control mode is obtained, the device may not complete
5676          * auto-negotiation. It is necessary to wait for link establishment.
5677          */
5678         (void)hns3_dev_link_update(dev, 1);
5679
5680         /*
5681          * If the link auto-negotiation of the nic is disabled, or the flow
5682          * control auto-negotiation is not supported, the forced flow control
5683          * mode is used.
5684          */
5685         if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
5686                 return hw->requested_fc_mode;
5687
5688         return hns3_get_autoneg_fc_mode(hw);
5689 }
5690
5691 static int
5692 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5693 {
5694         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5695         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5696         enum hns3_fc_mode current_mode;
5697
5698         current_mode = hns3_get_current_fc_mode(dev);
5699         switch (current_mode) {
5700         case HNS3_FC_FULL:
5701                 fc_conf->mode = RTE_ETH_FC_FULL;
5702                 break;
5703         case HNS3_FC_TX_PAUSE:
5704                 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
5705                 break;
5706         case HNS3_FC_RX_PAUSE:
5707                 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
5708                 break;
5709         case HNS3_FC_NONE:
5710         default:
5711                 fc_conf->mode = RTE_ETH_FC_NONE;
5712                 break;
5713         }
5714
5715         fc_conf->pause_time = pf->pause_time;
5716         fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
5717
5718         return 0;
5719 }
5720
5721 static int
5722 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
5723 {
5724         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5725
5726         if (!pf->support_fc_autoneg) {
5727                 if (autoneg != 0) {
5728                         hns3_err(hw, "unsupported fc auto-negotiation setting.");
5729                         return -EOPNOTSUPP;
5730                 }
5731
5732                 /*
5733                  * Flow control auto-negotiation of the NIC is not supported,
5734                  * but other auto-negotiation features may be supported.
5735                  */
5736                 if (autoneg != hw->mac.link_autoneg) {
5737                         hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
5738                         return -EOPNOTSUPP;
5739                 }
5740
5741                 return 0;
5742         }
5743
5744         /*
5745          * If flow control auto-negotiation of the NIC is supported, all
5746          * auto-negotiation features are supported.
5747          */
5748         if (autoneg != hw->mac.link_autoneg) {
5749                 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
5750                 return -EOPNOTSUPP;
5751         }
5752
5753         return 0;
5754 }
5755
5756 static int
5757 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5758 {
5759         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5760         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5761         int ret;
5762
5763         if (fc_conf->high_water || fc_conf->low_water ||
5764             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5765                 hns3_err(hw, "Unsupported flow control settings specified, "
5766                          "high_water(%u), low_water(%u), send_xon(%u) and "
5767                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5768                          fc_conf->high_water, fc_conf->low_water,
5769                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5770                 return -EINVAL;
5771         }
5772
5773         ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
5774         if (ret)
5775                 return ret;
5776
5777         if (!fc_conf->pause_time) {
5778                 hns3_err(hw, "Invalid pause time %u setting.",
5779                          fc_conf->pause_time);
5780                 return -EINVAL;
5781         }
5782
5783         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5784             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5785                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5786                          "current_fc_status = %d", hw->current_fc_status);
5787                 return -EOPNOTSUPP;
5788         }
5789
5790         if (hw->num_tc > 1 && !pf->support_multi_tc_pause) {
5791                 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
5792                 return -EOPNOTSUPP;
5793         }
5794
5795         rte_spinlock_lock(&hw->lock);
5796         ret = hns3_fc_enable(dev, fc_conf);
5797         rte_spinlock_unlock(&hw->lock);
5798
5799         return ret;
5800 }
5801
5802 static int
5803 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5804                             struct rte_eth_pfc_conf *pfc_conf)
5805 {
5806         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5807         int ret;
5808
5809         if (!hns3_dev_get_support(hw, DCB)) {
5810                 hns3_err(hw, "This port does not support dcb configurations.");
5811                 return -EOPNOTSUPP;
5812         }
5813
5814         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5815             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5816                 hns3_err(hw, "Unsupported flow control settings specified, "
5817                          "high_water(%u), low_water(%u), send_xon(%u) and "
5818                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5819                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5820                          pfc_conf->fc.send_xon,
5821                          pfc_conf->fc.mac_ctrl_frame_fwd);
5822                 return -EINVAL;
5823         }
5824         if (pfc_conf->fc.autoneg) {
5825                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5826                 return -EINVAL;
5827         }
5828         if (pfc_conf->fc.pause_time == 0) {
5829                 hns3_err(hw, "Invalid pause time %u setting.",
5830                          pfc_conf->fc.pause_time);
5831                 return -EINVAL;
5832         }
5833
5834         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5835             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5836                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5837                              "current_fc_status = %d", hw->current_fc_status);
5838                 return -EOPNOTSUPP;
5839         }
5840
5841         rte_spinlock_lock(&hw->lock);
5842         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5843         rte_spinlock_unlock(&hw->lock);
5844
5845         return ret;
5846 }
5847
5848 static int
5849 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5850 {
5851         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5852         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5853         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5854         int i;
5855
5856         rte_spinlock_lock(&hw->lock);
5857         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG)
5858                 dcb_info->nb_tcs = pf->local_max_tc;
5859         else
5860                 dcb_info->nb_tcs = 1;
5861
5862         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5863                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5864         for (i = 0; i < dcb_info->nb_tcs; i++)
5865                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5866
5867         for (i = 0; i < hw->num_tc; i++) {
5868                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5869                 dcb_info->tc_queue.tc_txq[0][i].base =
5870                                                 hw->tc_queue[i].tqp_offset;
5871                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5872                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5873                                                 hw->tc_queue[i].tqp_count;
5874         }
5875         rte_spinlock_unlock(&hw->lock);
5876
5877         return 0;
5878 }
5879
5880 static int
5881 hns3_reinit_dev(struct hns3_adapter *hns)
5882 {
5883         struct hns3_hw *hw = &hns->hw;
5884         int ret;
5885
5886         ret = hns3_cmd_init(hw);
5887         if (ret) {
5888                 hns3_err(hw, "Failed to init cmd: %d", ret);
5889                 return ret;
5890         }
5891
5892         ret = hns3_reset_all_tqps(hns);
5893         if (ret) {
5894                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5895                 return ret;
5896         }
5897
5898         ret = hns3_init_hardware(hns);
5899         if (ret) {
5900                 hns3_err(hw, "Failed to init hardware: %d", ret);
5901                 return ret;
5902         }
5903
5904         ret = hns3_enable_hw_error_intr(hns, true);
5905         if (ret) {
5906                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5907                              ret);
5908                 return ret;
5909         }
5910         hns3_info(hw, "Reset done, driver initialization finished.");
5911
5912         return 0;
5913 }
5914
5915 static bool
5916 is_pf_reset_done(struct hns3_hw *hw)
5917 {
5918         uint32_t val, reg, reg_bit;
5919
5920         switch (hw->reset.level) {
5921         case HNS3_IMP_RESET:
5922                 reg = HNS3_GLOBAL_RESET_REG;
5923                 reg_bit = HNS3_IMP_RESET_BIT;
5924                 break;
5925         case HNS3_GLOBAL_RESET:
5926                 reg = HNS3_GLOBAL_RESET_REG;
5927                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5928                 break;
5929         case HNS3_FUNC_RESET:
5930                 reg = HNS3_FUN_RST_ING;
5931                 reg_bit = HNS3_FUN_RST_ING_B;
5932                 break;
5933         case HNS3_FLR_RESET:
5934         default:
5935                 hns3_err(hw, "Wait for unsupported reset level: %d",
5936                          hw->reset.level);
5937                 return true;
5938         }
5939         val = hns3_read_dev(hw, reg);
5940         if (hns3_get_bit(val, reg_bit))
5941                 return false;
5942         else
5943                 return true;
5944 }
5945
5946 bool
5947 hns3_is_reset_pending(struct hns3_adapter *hns)
5948 {
5949         struct hns3_hw *hw = &hns->hw;
5950         enum hns3_reset_level reset;
5951
5952         hns3_check_event_cause(hns, NULL);
5953         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5954         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
5955             hw->reset.level < reset) {
5956                 hns3_warn(hw, "High level reset %d is pending", reset);
5957                 return true;
5958         }
5959         reset = hns3_get_reset_level(hns, &hw->reset.request);
5960         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
5961             hw->reset.level < reset) {
5962                 hns3_warn(hw, "High level reset %d is request", reset);
5963                 return true;
5964         }
5965         return false;
5966 }
5967
5968 static int
5969 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5970 {
5971         struct hns3_hw *hw = &hns->hw;
5972         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5973         struct timeval tv;
5974
5975         if (wait_data->result == HNS3_WAIT_SUCCESS)
5976                 return 0;
5977         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5978                 hns3_clock_gettime(&tv);
5979                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5980                           tv.tv_sec, tv.tv_usec);
5981                 return -ETIME;
5982         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5983                 return -EAGAIN;
5984
5985         wait_data->hns = hns;
5986         wait_data->check_completion = is_pf_reset_done;
5987         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5988                                 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms();
5989         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5990         wait_data->count = HNS3_RESET_WAIT_CNT;
5991         wait_data->result = HNS3_WAIT_REQUEST;
5992         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5993         return -EAGAIN;
5994 }
5995
5996 static int
5997 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5998 {
5999         struct hns3_cmd_desc desc;
6000         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6001
6002         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6003         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6004         req->fun_reset_vfid = func_id;
6005
6006         return hns3_cmd_send(hw, &desc, 1);
6007 }
6008
6009 static int
6010 hns3_imp_reset_cmd(struct hns3_hw *hw)
6011 {
6012         struct hns3_cmd_desc desc;
6013
6014         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6015         desc.data[0] = 0xeedd;
6016
6017         return hns3_cmd_send(hw, &desc, 1);
6018 }
6019
6020 static void
6021 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6022 {
6023         struct hns3_hw *hw = &hns->hw;
6024         struct timeval tv;
6025         uint32_t val;
6026
6027         hns3_clock_gettime(&tv);
6028         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6029             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6030                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6031                           tv.tv_sec, tv.tv_usec);
6032                 return;
6033         }
6034
6035         switch (reset_level) {
6036         case HNS3_IMP_RESET:
6037                 hns3_imp_reset_cmd(hw);
6038                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6039                           tv.tv_sec, tv.tv_usec);
6040                 break;
6041         case HNS3_GLOBAL_RESET:
6042                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6043                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6044                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6045                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6046                           tv.tv_sec, tv.tv_usec);
6047                 break;
6048         case HNS3_FUNC_RESET:
6049                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6050                           tv.tv_sec, tv.tv_usec);
6051                 /* schedule again to check later */
6052                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6053                 hns3_schedule_reset(hns);
6054                 break;
6055         default:
6056                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6057                 return;
6058         }
6059         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6060 }
6061
6062 static enum hns3_reset_level
6063 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6064 {
6065         struct hns3_hw *hw = &hns->hw;
6066         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6067
6068         /* Return the highest priority reset level amongst all */
6069         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6070                 reset_level = HNS3_IMP_RESET;
6071         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6072                 reset_level = HNS3_GLOBAL_RESET;
6073         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6074                 reset_level = HNS3_FUNC_RESET;
6075         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6076                 reset_level = HNS3_FLR_RESET;
6077
6078         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6079                 return HNS3_NONE_RESET;
6080
6081         return reset_level;
6082 }
6083
6084 static void
6085 hns3_record_imp_error(struct hns3_adapter *hns)
6086 {
6087         struct hns3_hw *hw = &hns->hw;
6088         uint32_t reg_val;
6089
6090         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6091         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6092                 hns3_warn(hw, "Detected IMP RD poison!");
6093                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6094                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6095         }
6096
6097         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6098                 hns3_warn(hw, "Detected IMP CMDQ error!");
6099                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6100                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6101         }
6102 }
6103
6104 static int
6105 hns3_prepare_reset(struct hns3_adapter *hns)
6106 {
6107         struct hns3_hw *hw = &hns->hw;
6108         uint32_t reg_val;
6109         int ret;
6110
6111         switch (hw->reset.level) {
6112         case HNS3_FUNC_RESET:
6113                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6114                 if (ret)
6115                         return ret;
6116
6117                 /*
6118                  * After performaning pf reset, it is not necessary to do the
6119                  * mailbox handling or send any command to firmware, because
6120                  * any mailbox handling or command to firmware is only valid
6121                  * after hns3_cmd_init is called.
6122                  */
6123                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6124                 hw->reset.stats.request_cnt++;
6125                 break;
6126         case HNS3_IMP_RESET:
6127                 hns3_record_imp_error(hns);
6128                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6129                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6130                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6131                 break;
6132         default:
6133                 break;
6134         }
6135         return 0;
6136 }
6137
6138 static int
6139 hns3_set_rst_done(struct hns3_hw *hw)
6140 {
6141         struct hns3_pf_rst_done_cmd *req;
6142         struct hns3_cmd_desc desc;
6143
6144         req = (struct hns3_pf_rst_done_cmd *)desc.data;
6145         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6146         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6147         return hns3_cmd_send(hw, &desc, 1);
6148 }
6149
6150 static int
6151 hns3_stop_service(struct hns3_adapter *hns)
6152 {
6153         struct hns3_hw *hw = &hns->hw;
6154         struct rte_eth_dev *eth_dev;
6155
6156         eth_dev = &rte_eth_devices[hw->data->port_id];
6157         hw->mac.link_status = RTE_ETH_LINK_DOWN;
6158         if (hw->adapter_state == HNS3_NIC_STARTED) {
6159                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6160                 hns3_update_linkstatus_and_event(hw, false);
6161         }
6162
6163         hns3_set_rxtx_function(eth_dev);
6164         rte_wmb();
6165         /* Disable datapath on secondary process. */
6166         hns3_mp_req_stop_rxtx(eth_dev);
6167         rte_delay_ms(hw->cfg_max_queues);
6168
6169         rte_spinlock_lock(&hw->lock);
6170         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6171             hw->adapter_state == HNS3_NIC_STOPPING) {
6172                 hns3_enable_all_queues(hw, false);
6173                 hns3_do_stop(hns);
6174                 hw->reset.mbuf_deferred_free = true;
6175         } else
6176                 hw->reset.mbuf_deferred_free = false;
6177
6178         /*
6179          * It is cumbersome for hardware to pick-and-choose entries for deletion
6180          * from table space. Hence, for function reset software intervention is
6181          * required to delete the entries
6182          */
6183         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6184                 hns3_configure_all_mc_mac_addr(hns, true);
6185         rte_spinlock_unlock(&hw->lock);
6186
6187         return 0;
6188 }
6189
6190 static int
6191 hns3_start_service(struct hns3_adapter *hns)
6192 {
6193         struct hns3_hw *hw = &hns->hw;
6194         struct rte_eth_dev *eth_dev;
6195
6196         if (hw->reset.level == HNS3_IMP_RESET ||
6197             hw->reset.level == HNS3_GLOBAL_RESET)
6198                 hns3_set_rst_done(hw);
6199         eth_dev = &rte_eth_devices[hw->data->port_id];
6200         hns3_set_rxtx_function(eth_dev);
6201         hns3_mp_req_start_rxtx(eth_dev);
6202         if (hw->adapter_state == HNS3_NIC_STARTED) {
6203                 /*
6204                  * This API parent function already hold the hns3_hw.lock, the
6205                  * hns3_service_handler may report lse, in bonding application
6206                  * it will call driver's ops which may acquire the hns3_hw.lock
6207                  * again, thus lead to deadlock.
6208                  * We defer calls hns3_service_handler to avoid the deadlock.
6209                  */
6210                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6211                                   hns3_service_handler, eth_dev);
6212
6213                 /* Enable interrupt of all rx queues before enabling queues */
6214                 hns3_dev_all_rx_queue_intr_enable(hw, true);
6215                 /*
6216                  * Enable state of each rxq and txq will be recovered after
6217                  * reset, so we need to restore them before enable all tqps;
6218                  */
6219                 hns3_restore_tqp_enable_state(hw);
6220                 /*
6221                  * When finished the initialization, enable queues to receive
6222                  * and transmit packets.
6223                  */
6224                 hns3_enable_all_queues(hw, true);
6225         }
6226
6227         return 0;
6228 }
6229
6230 static int
6231 hns3_restore_conf(struct hns3_adapter *hns)
6232 {
6233         struct hns3_hw *hw = &hns->hw;
6234         int ret;
6235
6236         ret = hns3_configure_all_mac_addr(hns, false);
6237         if (ret)
6238                 return ret;
6239
6240         ret = hns3_configure_all_mc_mac_addr(hns, false);
6241         if (ret)
6242                 goto err_mc_mac;
6243
6244         ret = hns3_dev_promisc_restore(hns);
6245         if (ret)
6246                 goto err_promisc;
6247
6248         ret = hns3_restore_vlan_table(hns);
6249         if (ret)
6250                 goto err_promisc;
6251
6252         ret = hns3_restore_vlan_conf(hns);
6253         if (ret)
6254                 goto err_promisc;
6255
6256         ret = hns3_restore_all_fdir_filter(hns);
6257         if (ret)
6258                 goto err_promisc;
6259
6260         ret = hns3_restore_ptp(hns);
6261         if (ret)
6262                 goto err_promisc;
6263
6264         ret = hns3_restore_rx_interrupt(hw);
6265         if (ret)
6266                 goto err_promisc;
6267
6268         ret = hns3_restore_gro_conf(hw);
6269         if (ret)
6270                 goto err_promisc;
6271
6272         ret = hns3_restore_fec(hw);
6273         if (ret)
6274                 goto err_promisc;
6275
6276         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6277                 ret = hns3_do_start(hns, false);
6278                 if (ret)
6279                         goto err_promisc;
6280                 hns3_info(hw, "hns3 dev restart successful!");
6281         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6282                 hw->adapter_state = HNS3_NIC_CONFIGURED;
6283         return 0;
6284
6285 err_promisc:
6286         hns3_configure_all_mc_mac_addr(hns, true);
6287 err_mc_mac:
6288         hns3_configure_all_mac_addr(hns, true);
6289         return ret;
6290 }
6291
6292 static void
6293 hns3_reset_service(void *param)
6294 {
6295         struct hns3_adapter *hns = (struct hns3_adapter *)param;
6296         struct hns3_hw *hw = &hns->hw;
6297         enum hns3_reset_level reset_level;
6298         struct timeval tv_delta;
6299         struct timeval tv_start;
6300         struct timeval tv;
6301         uint64_t msec;
6302         int ret;
6303
6304         /*
6305          * The interrupt is not triggered within the delay time.
6306          * The interrupt may have been lost. It is necessary to handle
6307          * the interrupt to recover from the error.
6308          */
6309         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6310                             SCHEDULE_DEFERRED) {
6311                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6312                                   __ATOMIC_RELAXED);
6313                 hns3_err(hw, "Handling interrupts in delayed tasks");
6314                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6315                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6316                 if (reset_level == HNS3_NONE_RESET) {
6317                         hns3_err(hw, "No reset level is set, try IMP reset");
6318                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6319                 }
6320         }
6321         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6322
6323         /*
6324          * Check if there is any ongoing reset in the hardware. This status can
6325          * be checked from reset_pending. If there is then, we need to wait for
6326          * hardware to complete reset.
6327          *    a. If we are able to figure out in reasonable time that hardware
6328          *       has fully resetted then, we can proceed with driver, client
6329          *       reset.
6330          *    b. else, we can come back later to check this status so re-sched
6331          *       now.
6332          */
6333         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6334         if (reset_level != HNS3_NONE_RESET) {
6335                 hns3_clock_gettime(&tv_start);
6336                 ret = hns3_reset_process(hns, reset_level);
6337                 hns3_clock_gettime(&tv);
6338                 timersub(&tv, &tv_start, &tv_delta);
6339                 msec = hns3_clock_calctime_ms(&tv_delta);
6340                 if (msec > HNS3_RESET_PROCESS_MS)
6341                         hns3_err(hw, "%d handle long time delta %" PRIu64
6342                                      " ms time=%ld.%.6ld",
6343                                  hw->reset.level, msec,
6344                                  tv.tv_sec, tv.tv_usec);
6345                 if (ret == -EAGAIN)
6346                         return;
6347         }
6348
6349         /* Check if we got any *new* reset requests to be honored */
6350         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6351         if (reset_level != HNS3_NONE_RESET)
6352                 hns3_msix_process(hns, reset_level);
6353 }
6354
6355 static unsigned int
6356 hns3_get_speed_capa_num(uint16_t device_id)
6357 {
6358         unsigned int num;
6359
6360         switch (device_id) {
6361         case HNS3_DEV_ID_25GE:
6362         case HNS3_DEV_ID_25GE_RDMA:
6363                 num = 2;
6364                 break;
6365         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6366         case HNS3_DEV_ID_200G_RDMA:
6367                 num = 1;
6368                 break;
6369         default:
6370                 num = 0;
6371                 break;
6372         }
6373
6374         return num;
6375 }
6376
6377 static int
6378 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6379                         uint16_t device_id)
6380 {
6381         switch (device_id) {
6382         case HNS3_DEV_ID_25GE:
6383         /* fallthrough */
6384         case HNS3_DEV_ID_25GE_RDMA:
6385                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6386                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6387
6388                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6389                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6390                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6391                 break;
6392         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6393                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6394                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6395                 break;
6396         case HNS3_DEV_ID_200G_RDMA:
6397                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6398                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6399                 break;
6400         default:
6401                 return -ENOTSUP;
6402         }
6403
6404         return 0;
6405 }
6406
6407 static int
6408 hns3_fec_get_capability(struct rte_eth_dev *dev,
6409                         struct rte_eth_fec_capa *speed_fec_capa,
6410                         unsigned int num)
6411 {
6412         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6413         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6414         uint16_t device_id = pci_dev->id.device_id;
6415         unsigned int capa_num;
6416         int ret;
6417
6418         capa_num = hns3_get_speed_capa_num(device_id);
6419         if (capa_num == 0) {
6420                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6421                          device_id);
6422                 return -ENOTSUP;
6423         }
6424
6425         if (speed_fec_capa == NULL || num < capa_num)
6426                 return capa_num;
6427
6428         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6429         if (ret)
6430                 return -ENOTSUP;
6431
6432         return capa_num;
6433 }
6434
6435 static int
6436 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6437 {
6438         struct hns3_config_fec_cmd *req;
6439         struct hns3_cmd_desc desc;
6440         int ret;
6441
6442         /*
6443          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6444          * in device of link speed
6445          * below 10 Gbps.
6446          */
6447         if (hw->mac.link_speed < RTE_ETH_SPEED_NUM_10G) {
6448                 *state = 0;
6449                 return 0;
6450         }
6451
6452         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6453         req = (struct hns3_config_fec_cmd *)desc.data;
6454         ret = hns3_cmd_send(hw, &desc, 1);
6455         if (ret) {
6456                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6457                          ret);
6458                 return ret;
6459         }
6460
6461         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6462         return 0;
6463 }
6464
6465 static int
6466 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6467 {
6468         struct hns3_sfp_info_cmd *resp;
6469         uint32_t tmp_fec_capa;
6470         uint8_t auto_state;
6471         struct hns3_cmd_desc desc;
6472         int ret;
6473
6474         /*
6475          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6476          * configured FEC mode is returned.
6477          * If link is up, current FEC mode is returned.
6478          */
6479         if (hw->mac.link_status == RTE_ETH_LINK_DOWN) {
6480                 ret = get_current_fec_auto_state(hw, &auto_state);
6481                 if (ret)
6482                         return ret;
6483
6484                 if (auto_state == 0x1) {
6485                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6486                         return 0;
6487                 }
6488         }
6489
6490         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6491         resp = (struct hns3_sfp_info_cmd *)desc.data;
6492         resp->query_type = HNS3_ACTIVE_QUERY;
6493
6494         ret = hns3_cmd_send(hw, &desc, 1);
6495         if (ret == -EOPNOTSUPP) {
6496                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6497                 return ret;
6498         } else if (ret) {
6499                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6500                 return ret;
6501         }
6502
6503         /*
6504          * FEC mode order defined in hns3 hardware is inconsistend with
6505          * that defined in the ethdev library. So the sequence needs
6506          * to be converted.
6507          */
6508         switch (resp->active_fec) {
6509         case HNS3_HW_FEC_MODE_NOFEC:
6510                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6511                 break;
6512         case HNS3_HW_FEC_MODE_BASER:
6513                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6514                 break;
6515         case HNS3_HW_FEC_MODE_RS:
6516                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6517                 break;
6518         default:
6519                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6520                 break;
6521         }
6522
6523         *fec_capa = tmp_fec_capa;
6524         return 0;
6525 }
6526
6527 static int
6528 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6529 {
6530         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6531
6532         return hns3_fec_get_internal(hw, fec_capa);
6533 }
6534
6535 static int
6536 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6537 {
6538         struct hns3_config_fec_cmd *req;
6539         struct hns3_cmd_desc desc;
6540         int ret;
6541
6542         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6543
6544         req = (struct hns3_config_fec_cmd *)desc.data;
6545         switch (mode) {
6546         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6547                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6548                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6549                 break;
6550         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6551                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6552                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6553                 break;
6554         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6555                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6556                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6557                 break;
6558         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6559                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6560                 break;
6561         default:
6562                 return 0;
6563         }
6564         ret = hns3_cmd_send(hw, &desc, 1);
6565         if (ret)
6566                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6567
6568         return ret;
6569 }
6570
6571 static uint32_t
6572 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6573 {
6574         struct hns3_mac *mac = &hw->mac;
6575         uint32_t cur_capa;
6576
6577         switch (mac->link_speed) {
6578         case RTE_ETH_SPEED_NUM_10G:
6579                 cur_capa = fec_capa[1].capa;
6580                 break;
6581         case RTE_ETH_SPEED_NUM_25G:
6582         case RTE_ETH_SPEED_NUM_100G:
6583         case RTE_ETH_SPEED_NUM_200G:
6584                 cur_capa = fec_capa[0].capa;
6585                 break;
6586         default:
6587                 cur_capa = 0;
6588                 break;
6589         }
6590
6591         return cur_capa;
6592 }
6593
6594 static bool
6595 is_fec_mode_one_bit_set(uint32_t mode)
6596 {
6597         int cnt = 0;
6598         uint8_t i;
6599
6600         for (i = 0; i < sizeof(mode); i++)
6601                 if (mode >> i & 0x1)
6602                         cnt++;
6603
6604         return cnt == 1 ? true : false;
6605 }
6606
6607 static int
6608 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6609 {
6610 #define FEC_CAPA_NUM 2
6611         struct hns3_adapter *hns = dev->data->dev_private;
6612         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6613         struct hns3_pf *pf = &hns->pf;
6614
6615         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6616         uint32_t cur_capa;
6617         uint32_t num = FEC_CAPA_NUM;
6618         int ret;
6619
6620         ret = hns3_fec_get_capability(dev, fec_capa, num);
6621         if (ret < 0)
6622                 return ret;
6623
6624         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6625         if (!is_fec_mode_one_bit_set(mode)) {
6626                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, "
6627                              "FEC mode should be only one bit set", mode);
6628                 return -EINVAL;
6629         }
6630
6631         /*
6632          * Check whether the configured mode is within the FEC capability.
6633          * If not, the configured mode will not be supported.
6634          */
6635         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6636         if (!(cur_capa & mode)) {
6637                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6638                 return -EINVAL;
6639         }
6640
6641         rte_spinlock_lock(&hw->lock);
6642         ret = hns3_set_fec_hw(hw, mode);
6643         if (ret) {
6644                 rte_spinlock_unlock(&hw->lock);
6645                 return ret;
6646         }
6647
6648         pf->fec_mode = mode;
6649         rte_spinlock_unlock(&hw->lock);
6650
6651         return 0;
6652 }
6653
6654 static int
6655 hns3_restore_fec(struct hns3_hw *hw)
6656 {
6657         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6658         struct hns3_pf *pf = &hns->pf;
6659         uint32_t mode = pf->fec_mode;
6660         int ret;
6661
6662         ret = hns3_set_fec_hw(hw, mode);
6663         if (ret)
6664                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6665                          mode, ret);
6666
6667         return ret;
6668 }
6669
6670 static int
6671 hns3_query_dev_fec_info(struct hns3_hw *hw)
6672 {
6673         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6674         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6675         int ret;
6676
6677         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6678         if (ret)
6679                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6680
6681         return ret;
6682 }
6683
6684 static bool
6685 hns3_optical_module_existed(struct hns3_hw *hw)
6686 {
6687         struct hns3_cmd_desc desc;
6688         bool existed;
6689         int ret;
6690
6691         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
6692         ret = hns3_cmd_send(hw, &desc, 1);
6693         if (ret) {
6694                 hns3_err(hw,
6695                          "fail to get optical module exist state, ret = %d.\n",
6696                          ret);
6697                 return false;
6698         }
6699         existed = !!desc.data[0];
6700
6701         return existed;
6702 }
6703
6704 static int
6705 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
6706                                 uint32_t len, uint8_t *data)
6707 {
6708 #define HNS3_SFP_INFO_CMD_NUM 6
6709 #define HNS3_SFP_INFO_MAX_LEN \
6710         (HNS3_SFP_INFO_BD0_LEN + \
6711         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
6712         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
6713         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
6714         uint16_t read_len;
6715         uint16_t copy_len;
6716         int ret;
6717         int i;
6718
6719         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6720                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
6721                                           true);
6722                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
6723                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
6724         }
6725
6726         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
6727         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
6728         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
6729         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
6730
6731         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
6732         if (ret) {
6733                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
6734                                 ret);
6735                 return ret;
6736         }
6737
6738         /* The data format in BD0 is different with the others. */
6739         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
6740         memcpy(data, sfp_info_bd0->data, copy_len);
6741         read_len = copy_len;
6742
6743         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6744                 if (read_len >= len)
6745                         break;
6746
6747                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
6748                 memcpy(data + read_len, desc[i].data, copy_len);
6749                 read_len += copy_len;
6750         }
6751
6752         return (int)read_len;
6753 }
6754
6755 static int
6756 hns3_get_module_eeprom(struct rte_eth_dev *dev,
6757                        struct rte_dev_eeprom_info *info)
6758 {
6759         struct hns3_adapter *hns = dev->data->dev_private;
6760         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6761         uint32_t offset = info->offset;
6762         uint32_t len = info->length;
6763         uint8_t *data = info->data;
6764         uint32_t read_len = 0;
6765
6766         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
6767                 return -ENOTSUP;
6768
6769         if (!hns3_optical_module_existed(hw)) {
6770                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
6771                 return -EIO;
6772         }
6773
6774         while (read_len < len) {
6775                 int ret;
6776                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
6777                                                   len - read_len,
6778                                                   data + read_len);
6779                 if (ret < 0)
6780                         return -EIO;
6781                 read_len += ret;
6782         }
6783
6784         return 0;
6785 }
6786
6787 static int
6788 hns3_get_module_info(struct rte_eth_dev *dev,
6789                      struct rte_eth_dev_module_info *modinfo)
6790 {
6791 #define HNS3_SFF8024_ID_SFP             0x03
6792 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
6793 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
6794 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
6795 #define HNS3_SFF_8636_V1_3              0x03
6796         struct hns3_adapter *hns = dev->data->dev_private;
6797         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6798         struct rte_dev_eeprom_info info;
6799         struct hns3_sfp_type sfp_type;
6800         int ret;
6801
6802         memset(&sfp_type, 0, sizeof(sfp_type));
6803         memset(&info, 0, sizeof(info));
6804         info.data = (uint8_t *)&sfp_type;
6805         info.length = sizeof(sfp_type);
6806         ret = hns3_get_module_eeprom(dev, &info);
6807         if (ret)
6808                 return ret;
6809
6810         switch (sfp_type.type) {
6811         case HNS3_SFF8024_ID_SFP:
6812                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
6813                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
6814                 break;
6815         case HNS3_SFF8024_ID_QSFP_8438:
6816                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6817                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6818                 break;
6819         case HNS3_SFF8024_ID_QSFP_8436_8636:
6820                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
6821                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
6822                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6823                 } else {
6824                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
6825                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6826                 }
6827                 break;
6828         case HNS3_SFF8024_ID_QSFP28_8636:
6829                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6830                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6831                 break;
6832         default:
6833                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
6834                          sfp_type.type, sfp_type.ext_type);
6835                 return -EINVAL;
6836         }
6837
6838         return 0;
6839 }
6840
6841 static const struct eth_dev_ops hns3_eth_dev_ops = {
6842         .dev_configure      = hns3_dev_configure,
6843         .dev_start          = hns3_dev_start,
6844         .dev_stop           = hns3_dev_stop,
6845         .dev_close          = hns3_dev_close,
6846         .promiscuous_enable = hns3_dev_promiscuous_enable,
6847         .promiscuous_disable = hns3_dev_promiscuous_disable,
6848         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6849         .allmulticast_disable = hns3_dev_allmulticast_disable,
6850         .mtu_set            = hns3_dev_mtu_set,
6851         .stats_get          = hns3_stats_get,
6852         .stats_reset        = hns3_stats_reset,
6853         .xstats_get         = hns3_dev_xstats_get,
6854         .xstats_get_names   = hns3_dev_xstats_get_names,
6855         .xstats_reset       = hns3_dev_xstats_reset,
6856         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6857         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6858         .dev_infos_get          = hns3_dev_infos_get,
6859         .fw_version_get         = hns3_fw_version_get,
6860         .rx_queue_setup         = hns3_rx_queue_setup,
6861         .tx_queue_setup         = hns3_tx_queue_setup,
6862         .rx_queue_release       = hns3_dev_rx_queue_release,
6863         .tx_queue_release       = hns3_dev_tx_queue_release,
6864         .rx_queue_start         = hns3_dev_rx_queue_start,
6865         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6866         .tx_queue_start         = hns3_dev_tx_queue_start,
6867         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6868         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6869         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6870         .rxq_info_get           = hns3_rxq_info_get,
6871         .txq_info_get           = hns3_txq_info_get,
6872         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6873         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6874         .flow_ctrl_get          = hns3_flow_ctrl_get,
6875         .flow_ctrl_set          = hns3_flow_ctrl_set,
6876         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6877         .mac_addr_add           = hns3_add_mac_addr,
6878         .mac_addr_remove        = hns3_remove_mac_addr,
6879         .mac_addr_set           = hns3_set_default_mac_addr,
6880         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6881         .link_update            = hns3_dev_link_update,
6882         .dev_set_link_up        = hns3_dev_set_link_up,
6883         .dev_set_link_down      = hns3_dev_set_link_down,
6884         .rss_hash_update        = hns3_dev_rss_hash_update,
6885         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6886         .reta_update            = hns3_dev_rss_reta_update,
6887         .reta_query             = hns3_dev_rss_reta_query,
6888         .flow_ops_get           = hns3_dev_flow_ops_get,
6889         .vlan_filter_set        = hns3_vlan_filter_set,
6890         .vlan_tpid_set          = hns3_vlan_tpid_set,
6891         .vlan_offload_set       = hns3_vlan_offload_set,
6892         .vlan_pvid_set          = hns3_vlan_pvid_set,
6893         .get_reg                = hns3_get_regs,
6894         .get_module_info        = hns3_get_module_info,
6895         .get_module_eeprom      = hns3_get_module_eeprom,
6896         .get_dcb_info           = hns3_get_dcb_info,
6897         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6898         .fec_get_capability     = hns3_fec_get_capability,
6899         .fec_get                = hns3_fec_get,
6900         .fec_set                = hns3_fec_set,
6901         .tm_ops_get             = hns3_tm_ops_get,
6902         .tx_done_cleanup        = hns3_tx_done_cleanup,
6903         .timesync_enable            = hns3_timesync_enable,
6904         .timesync_disable           = hns3_timesync_disable,
6905         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
6906         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
6907         .timesync_adjust_time       = hns3_timesync_adjust_time,
6908         .timesync_read_time         = hns3_timesync_read_time,
6909         .timesync_write_time        = hns3_timesync_write_time,
6910 };
6911
6912 static const struct hns3_reset_ops hns3_reset_ops = {
6913         .reset_service       = hns3_reset_service,
6914         .stop_service        = hns3_stop_service,
6915         .prepare_reset       = hns3_prepare_reset,
6916         .wait_hardware_ready = hns3_wait_hardware_ready,
6917         .reinit_dev          = hns3_reinit_dev,
6918         .restore_conf        = hns3_restore_conf,
6919         .start_service       = hns3_start_service,
6920 };
6921
6922 static void
6923 hns3_init_hw_ops(struct hns3_hw *hw)
6924 {
6925         hw->ops.add_mc_mac_addr = hns3_add_mc_mac_addr;
6926         hw->ops.del_mc_mac_addr = hns3_remove_mc_mac_addr;
6927         hw->ops.add_uc_mac_addr = hns3_add_uc_mac_addr;
6928         hw->ops.del_uc_mac_addr = hns3_remove_uc_mac_addr;
6929 }
6930
6931 static int
6932 hns3_dev_init(struct rte_eth_dev *eth_dev)
6933 {
6934         struct hns3_adapter *hns = eth_dev->data->dev_private;
6935         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6936         struct rte_ether_addr *eth_addr;
6937         struct hns3_hw *hw = &hns->hw;
6938         int ret;
6939
6940         PMD_INIT_FUNC_TRACE();
6941
6942         hns3_flow_init(eth_dev);
6943
6944         hns3_set_rxtx_function(eth_dev);
6945         eth_dev->dev_ops = &hns3_eth_dev_ops;
6946         eth_dev->rx_queue_count = hns3_rx_queue_count;
6947         ret = hns3_mp_init(eth_dev);
6948         if (ret)
6949                 goto err_mp_init;
6950
6951         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6952                 hns3_tx_push_init(eth_dev);
6953                 return 0;
6954         }
6955
6956         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6957         hns->is_vf = false;
6958         hw->data = eth_dev->data;
6959         hns3_parse_devargs(eth_dev);
6960
6961         /*
6962          * Set default max packet size according to the mtu
6963          * default vale in DPDK frame.
6964          */
6965         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6966
6967         ret = hns3_reset_init(hw);
6968         if (ret)
6969                 goto err_init_reset;
6970         hw->reset.ops = &hns3_reset_ops;
6971
6972         hns3_init_hw_ops(hw);
6973         ret = hns3_init_pf(eth_dev);
6974         if (ret) {
6975                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6976                 goto err_init_pf;
6977         }
6978
6979         /* Allocate memory for storing MAC addresses */
6980         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6981                                                sizeof(struct rte_ether_addr) *
6982                                                HNS3_UC_MACADDR_NUM, 0);
6983         if (eth_dev->data->mac_addrs == NULL) {
6984                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6985                              "to store MAC addresses",
6986                              sizeof(struct rte_ether_addr) *
6987                              HNS3_UC_MACADDR_NUM);
6988                 ret = -ENOMEM;
6989                 goto err_rte_zmalloc;
6990         }
6991
6992         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6993         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6994                 rte_eth_random_addr(hw->mac.mac_addr);
6995                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6996                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6997                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6998                           "unicast address, using random MAC address %s",
6999                           mac_str);
7000         }
7001         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7002                             &eth_dev->data->mac_addrs[0]);
7003
7004         hw->adapter_state = HNS3_NIC_INITIALIZED;
7005
7006         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7007                             SCHEDULE_PENDING) {
7008                 hns3_err(hw, "Reschedule reset service after dev_init");
7009                 hns3_schedule_reset(hns);
7010         } else {
7011                 /* IMP will wait ready flag before reset */
7012                 hns3_notify_reset_ready(hw, false);
7013         }
7014
7015         hns3_info(hw, "hns3 dev initialization successful!");
7016         return 0;
7017
7018 err_rte_zmalloc:
7019         hns3_uninit_pf(eth_dev);
7020
7021 err_init_pf:
7022         rte_free(hw->reset.wait_data);
7023
7024 err_init_reset:
7025         hns3_mp_uninit(eth_dev);
7026
7027 err_mp_init:
7028         eth_dev->dev_ops = NULL;
7029         eth_dev->rx_pkt_burst = NULL;
7030         eth_dev->rx_descriptor_status = NULL;
7031         eth_dev->tx_pkt_burst = NULL;
7032         eth_dev->tx_pkt_prepare = NULL;
7033         eth_dev->tx_descriptor_status = NULL;
7034         return ret;
7035 }
7036
7037 static int
7038 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7039 {
7040         struct hns3_adapter *hns = eth_dev->data->dev_private;
7041         struct hns3_hw *hw = &hns->hw;
7042
7043         PMD_INIT_FUNC_TRACE();
7044
7045         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7046                 hns3_mp_uninit(eth_dev);
7047                 return 0;
7048         }
7049
7050         if (hw->adapter_state < HNS3_NIC_CLOSING)
7051                 hns3_dev_close(eth_dev);
7052
7053         hw->adapter_state = HNS3_NIC_REMOVED;
7054         return 0;
7055 }
7056
7057 static int
7058 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7059                    struct rte_pci_device *pci_dev)
7060 {
7061         return rte_eth_dev_pci_generic_probe(pci_dev,
7062                                              sizeof(struct hns3_adapter),
7063                                              hns3_dev_init);
7064 }
7065
7066 static int
7067 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7068 {
7069         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7070 }
7071
7072 static const struct rte_pci_id pci_id_hns3_map[] = {
7073         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7074         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7075         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7076         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7077         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7078         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7079         { .vendor_id = 0, }, /* sentinel */
7080 };
7081
7082 static struct rte_pci_driver rte_hns3_pmd = {
7083         .id_table = pci_id_hns3_map,
7084         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7085         .probe = eth_hns3_pci_probe,
7086         .remove = eth_hns3_pci_remove,
7087 };
7088
7089 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7090 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7091 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7092 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7093                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7094                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
7095                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
7096                 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16> ");
7097 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE);
7098 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE);