1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
12 #include <rte_atomic.h>
13 #include <rte_bus_pci.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_interrupts.h>
26 #include "hns3_ethdev.h"
27 #include "hns3_logs.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_intr.h"
30 #include "hns3_regs.h"
34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
37 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
38 #define HNS3_PORT_BASE_VLAN_DISABLE 0
39 #define HNS3_PORT_BASE_VLAN_ENABLE 1
40 #define HNS3_INVLID_PVID 0xFFFF
42 #define HNS3_FILTER_TYPE_VF 0
43 #define HNS3_FILTER_TYPE_PORT 1
44 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
45 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
46 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
47 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
48 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
49 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
50 | HNS3_FILTER_FE_ROCE_EGRESS_B)
51 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
52 | HNS3_FILTER_FE_ROCE_INGRESS_B)
54 /* Reset related Registers */
55 #define HNS3_GLOBAL_RESET_BIT 0
56 #define HNS3_CORE_RESET_BIT 1
57 #define HNS3_IMP_RESET_BIT 2
58 #define HNS3_FUN_RST_ING_B 0
60 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
62 #define HNS3_RESET_WAIT_MS 100
63 #define HNS3_RESET_WAIT_CNT 200
65 int hns3_logtype_init;
66 int hns3_logtype_driver;
69 HNS3_VECTOR0_EVENT_RST,
70 HNS3_VECTOR0_EVENT_MBX,
71 HNS3_VECTOR0_EVENT_ERR,
72 HNS3_VECTOR0_EVENT_OTHER,
75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
82 static int hns3_add_mc_addr(struct hns3_hw *hw,
83 struct rte_ether_addr *mac_addr);
84 static int hns3_remove_mc_addr(struct hns3_hw *hw,
85 struct rte_ether_addr *mac_addr);
88 hns3_pf_disable_irq0(struct hns3_hw *hw)
90 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
94 hns3_pf_enable_irq0(struct hns3_hw *hw)
96 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
99 static enum hns3_evt_cause
100 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
102 struct hns3_hw *hw = &hns->hw;
103 uint32_t vector0_int_stats;
104 uint32_t cmdq_src_val;
106 enum hns3_evt_cause ret;
108 /* fetch the events from their corresponding regs */
109 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
110 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
113 * Assumption: If by any chance reset and mailbox events are reported
114 * together then we will only process reset event and defer the
115 * processing of the mailbox events. Since, we would have not cleared
116 * RX CMDQ event this time we would receive again another interrupt
117 * from H/W just for the mailbox.
119 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
120 rte_atomic16_set(&hw->reset.disable_cmd, 1);
121 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
122 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
124 hw->reset.stats.imp_cnt++;
125 hns3_warn(hw, "IMP reset detected, clear reset status");
127 hns3_schedule_delayed_reset(hns);
128 hns3_warn(hw, "IMP reset detected, don't clear reset status");
131 ret = HNS3_VECTOR0_EVENT_RST;
136 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
137 rte_atomic16_set(&hw->reset.disable_cmd, 1);
138 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
139 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
141 hw->reset.stats.global_cnt++;
142 hns3_warn(hw, "Global reset detected, clear reset status");
144 hns3_schedule_delayed_reset(hns);
145 hns3_warn(hw, "Global reset detected, don't clear reset status");
148 ret = HNS3_VECTOR0_EVENT_RST;
152 /* check for vector0 msix event source */
153 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
154 val = vector0_int_stats;
155 ret = HNS3_VECTOR0_EVENT_ERR;
159 /* check for vector0 mailbox(=CMDQ RX) event source */
160 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
161 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
163 ret = HNS3_VECTOR0_EVENT_MBX;
167 if (clearval && (vector0_int_stats || cmdq_src_val))
168 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
169 vector0_int_stats, cmdq_src_val);
170 val = vector0_int_stats;
171 ret = HNS3_VECTOR0_EVENT_OTHER;
180 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
182 if (event_type == HNS3_VECTOR0_EVENT_RST)
183 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
184 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
185 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
189 hns3_clear_all_event_cause(struct hns3_hw *hw)
191 uint32_t vector0_int_stats;
192 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
194 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
195 hns3_warn(hw, "Probe during IMP reset interrupt");
197 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
198 hns3_warn(hw, "Probe during Global reset interrupt");
200 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
201 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
202 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
203 BIT(HNS3_VECTOR0_CORERESET_INT_B));
204 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
208 hns3_interrupt_handler(void *param)
210 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
211 struct hns3_adapter *hns = dev->data->dev_private;
212 struct hns3_hw *hw = &hns->hw;
213 enum hns3_evt_cause event_cause;
214 uint32_t clearval = 0;
216 /* Disable interrupt */
217 hns3_pf_disable_irq0(hw);
219 event_cause = hns3_check_event_cause(hns, &clearval);
221 /* vector 0 interrupt is shared with reset and mailbox source events. */
222 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
223 hns3_handle_msix_error(hns, &hw->reset.request);
224 hns3_schedule_reset(hns);
225 } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
226 hns3_schedule_reset(hns);
227 else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
228 hns3_dev_handle_mbx_msg(hw);
230 hns3_err(hw, "Received unknown event");
232 hns3_clear_event_cause(hw, event_cause, clearval);
233 /* Enable interrupt if it is not cause by reset */
234 hns3_pf_enable_irq0(hw);
238 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
240 #define HNS3_VLAN_ID_OFFSET_STEP 160
241 #define HNS3_VLAN_BYTE_SIZE 8
242 struct hns3_vlan_filter_pf_cfg_cmd *req;
243 struct hns3_hw *hw = &hns->hw;
244 uint8_t vlan_offset_byte_val;
245 struct hns3_cmd_desc desc;
246 uint8_t vlan_offset_byte;
247 uint8_t vlan_offset_base;
250 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
252 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
253 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
255 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
257 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
258 req->vlan_offset = vlan_offset_base;
259 req->vlan_cfg = on ? 0 : 1;
260 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
262 ret = hns3_cmd_send(hw, &desc, 1);
264 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
271 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
273 struct hns3_user_vlan_table *vlan_entry;
274 struct hns3_pf *pf = &hns->pf;
276 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
277 if (vlan_entry->vlan_id == vlan_id) {
278 if (vlan_entry->hd_tbl_status)
279 hns3_set_port_vlan_filter(hns, vlan_id, 0);
280 LIST_REMOVE(vlan_entry, next);
281 rte_free(vlan_entry);
288 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
291 struct hns3_user_vlan_table *vlan_entry;
292 struct hns3_hw *hw = &hns->hw;
293 struct hns3_pf *pf = &hns->pf;
295 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
296 if (vlan_entry->vlan_id == vlan_id)
300 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
301 if (vlan_entry == NULL) {
302 hns3_err(hw, "Failed to malloc hns3 vlan table");
306 vlan_entry->hd_tbl_status = writen_to_tbl;
307 vlan_entry->vlan_id = vlan_id;
309 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
313 hns3_restore_vlan_table(struct hns3_adapter *hns)
315 struct hns3_user_vlan_table *vlan_entry;
316 struct hns3_pf *pf = &hns->pf;
320 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
321 return hns3_vlan_pvid_configure(hns,
322 pf->port_base_vlan_cfg.pvid, 1);
324 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
325 if (vlan_entry->hd_tbl_status) {
326 vlan_id = vlan_entry->vlan_id;
327 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
337 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
339 struct hns3_pf *pf = &hns->pf;
340 bool writen_to_tbl = false;
344 * When vlan filter is enabled, hardware regards vlan id 0 as the entry
345 * for normal packet, deleting vlan id 0 is not allowed.
347 if (on == 0 && vlan_id == 0)
351 * When port base vlan enabled, we use port base vlan as the vlan
352 * filter condition. In this case, we don't update vlan filter table
353 * when user add new vlan or remove exist vlan, just update the
354 * vlan list. The vlan id in vlan list will be writen in vlan filter
355 * table until port base vlan disabled
357 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
358 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
359 writen_to_tbl = true;
362 if (ret == 0 && vlan_id) {
364 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
366 hns3_rm_dev_vlan_table(hns, vlan_id);
372 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
374 struct hns3_adapter *hns = dev->data->dev_private;
375 struct hns3_hw *hw = &hns->hw;
378 rte_spinlock_lock(&hw->lock);
379 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
380 rte_spinlock_unlock(&hw->lock);
385 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
388 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
389 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
390 struct hns3_hw *hw = &hns->hw;
391 struct hns3_cmd_desc desc;
394 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
395 vlan_type != ETH_VLAN_TYPE_OUTER)) {
396 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
400 if (tpid != RTE_ETHER_TYPE_VLAN) {
401 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
405 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
406 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
408 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
409 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
410 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
411 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
412 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
413 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
414 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
415 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
418 ret = hns3_cmd_send(hw, &desc, 1);
420 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
425 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
427 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
428 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
429 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
431 ret = hns3_cmd_send(hw, &desc, 1);
433 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
439 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
442 struct hns3_adapter *hns = dev->data->dev_private;
443 struct hns3_hw *hw = &hns->hw;
446 rte_spinlock_lock(&hw->lock);
447 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
448 rte_spinlock_unlock(&hw->lock);
453 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
454 struct hns3_rx_vtag_cfg *vcfg)
456 struct hns3_vport_vtag_rx_cfg_cmd *req;
457 struct hns3_hw *hw = &hns->hw;
458 struct hns3_cmd_desc desc;
463 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
465 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
466 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
467 vcfg->strip_tag1_en ? 1 : 0);
468 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
469 vcfg->strip_tag2_en ? 1 : 0);
470 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
471 vcfg->vlan1_vlan_prionly ? 1 : 0);
472 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
473 vcfg->vlan2_vlan_prionly ? 1 : 0);
476 * In current version VF is not supported when PF is driven by DPDK
477 * driver, the PF-related vf_id is 0, just need to configure parameters
481 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
482 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
483 req->vf_bitmap[req->vf_offset] = bitmap;
485 ret = hns3_cmd_send(hw, &desc, 1);
487 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
492 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
493 struct hns3_rx_vtag_cfg *vcfg)
495 struct hns3_pf *pf = &hns->pf;
496 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
500 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
501 struct hns3_tx_vtag_cfg *vcfg)
503 struct hns3_pf *pf = &hns->pf;
504 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
508 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
510 struct hns3_rx_vtag_cfg rxvlan_cfg;
511 struct hns3_pf *pf = &hns->pf;
512 struct hns3_hw *hw = &hns->hw;
515 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
516 rxvlan_cfg.strip_tag1_en = false;
517 rxvlan_cfg.strip_tag2_en = enable;
519 rxvlan_cfg.strip_tag1_en = enable;
520 rxvlan_cfg.strip_tag2_en = true;
523 rxvlan_cfg.vlan1_vlan_prionly = false;
524 rxvlan_cfg.vlan2_vlan_prionly = false;
525 rxvlan_cfg.rx_vlan_offload_en = enable;
527 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
529 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
533 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
539 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
540 uint8_t fe_type, bool filter_en, uint8_t vf_id)
542 struct hns3_vlan_filter_ctrl_cmd *req;
543 struct hns3_cmd_desc desc;
546 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
548 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
549 req->vlan_type = vlan_type;
550 req->vlan_fe = filter_en ? fe_type : 0;
553 ret = hns3_cmd_send(hw, &desc, 1);
555 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
561 hns3_vlan_filter_init(struct hns3_adapter *hns)
563 struct hns3_hw *hw = &hns->hw;
566 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
567 HNS3_FILTER_FE_EGRESS, false, 0);
569 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
573 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
574 HNS3_FILTER_FE_INGRESS, false, 0);
576 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
582 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
584 struct hns3_hw *hw = &hns->hw;
587 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
588 HNS3_FILTER_FE_INGRESS, enable, 0);
590 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
591 enable ? "enable" : "disable", ret);
597 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
599 struct hns3_adapter *hns = dev->data->dev_private;
600 struct hns3_hw *hw = &hns->hw;
601 struct rte_eth_rxmode *rxmode;
602 unsigned int tmp_mask;
606 rte_spinlock_lock(&hw->lock);
607 rxmode = &dev->data->dev_conf.rxmode;
608 tmp_mask = (unsigned int)mask;
609 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
610 /* Enable or disable VLAN filter */
611 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
614 ret = hns3_enable_vlan_filter(hns, enable);
616 rte_spinlock_unlock(&hw->lock);
617 hns3_err(hw, "failed to %s rx filter, ret = %d",
618 enable ? "enable" : "disable", ret);
623 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
624 /* Enable or disable VLAN stripping */
625 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
628 ret = hns3_en_hw_strip_rxvtag(hns, enable);
630 rte_spinlock_unlock(&hw->lock);
631 hns3_err(hw, "failed to %s rx strip, ret = %d",
632 enable ? "enable" : "disable", ret);
637 rte_spinlock_unlock(&hw->lock);
643 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
644 struct hns3_tx_vtag_cfg *vcfg)
646 struct hns3_vport_vtag_tx_cfg_cmd *req;
647 struct hns3_cmd_desc desc;
648 struct hns3_hw *hw = &hns->hw;
653 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
655 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
656 req->def_vlan_tag1 = vcfg->default_tag1;
657 req->def_vlan_tag2 = vcfg->default_tag2;
658 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
659 vcfg->accept_tag1 ? 1 : 0);
660 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
661 vcfg->accept_untag1 ? 1 : 0);
662 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
663 vcfg->accept_tag2 ? 1 : 0);
664 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
665 vcfg->accept_untag2 ? 1 : 0);
666 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
667 vcfg->insert_tag1_en ? 1 : 0);
668 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
669 vcfg->insert_tag2_en ? 1 : 0);
670 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
673 * In current version VF is not supported when PF is driven by DPDK
674 * driver, the PF-related vf_id is 0, just need to configure parameters
678 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
679 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
680 req->vf_bitmap[req->vf_offset] = bitmap;
682 ret = hns3_cmd_send(hw, &desc, 1);
684 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
690 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
693 struct hns3_hw *hw = &hns->hw;
694 struct hns3_tx_vtag_cfg txvlan_cfg;
697 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
698 txvlan_cfg.accept_tag1 = true;
699 txvlan_cfg.insert_tag1_en = false;
700 txvlan_cfg.default_tag1 = 0;
702 txvlan_cfg.accept_tag1 = false;
703 txvlan_cfg.insert_tag1_en = true;
704 txvlan_cfg.default_tag1 = pvid;
707 txvlan_cfg.accept_untag1 = true;
708 txvlan_cfg.accept_tag2 = true;
709 txvlan_cfg.accept_untag2 = true;
710 txvlan_cfg.insert_tag2_en = false;
711 txvlan_cfg.default_tag2 = 0;
713 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
715 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
720 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
725 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
727 struct hns3_pf *pf = &hns->pf;
729 pf->port_base_vlan_cfg.state = on ?
730 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
732 pf->port_base_vlan_cfg.pvid = pvid;
736 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
738 struct hns3_user_vlan_table *vlan_entry;
739 struct hns3_pf *pf = &hns->pf;
741 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
742 if (vlan_entry->hd_tbl_status)
743 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
745 vlan_entry->hd_tbl_status = false;
749 vlan_entry = LIST_FIRST(&pf->vlan_list);
751 LIST_REMOVE(vlan_entry, next);
752 rte_free(vlan_entry);
753 vlan_entry = LIST_FIRST(&pf->vlan_list);
759 hns3_add_all_vlan_table(struct hns3_adapter *hns)
761 struct hns3_user_vlan_table *vlan_entry;
762 struct hns3_pf *pf = &hns->pf;
764 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
765 if (!vlan_entry->hd_tbl_status)
766 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
768 vlan_entry->hd_tbl_status = true;
773 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
775 struct hns3_hw *hw = &hns->hw;
776 struct hns3_pf *pf = &hns->pf;
779 hns3_rm_all_vlan_table(hns, true);
780 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
781 ret = hns3_set_port_vlan_filter(hns,
782 pf->port_base_vlan_cfg.pvid, 0);
784 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
792 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
793 uint16_t port_base_vlan_state,
794 uint16_t new_pvid, uint16_t old_pvid)
796 struct hns3_pf *pf = &hns->pf;
797 struct hns3_hw *hw = &hns->hw;
800 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
801 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
802 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
805 "Failed to clear clear old pvid filter, ret =%d",
811 hns3_rm_all_vlan_table(hns, false);
812 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
816 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
818 hns3_err(hw, "Failed to set port vlan filter, ret =%d",
824 if (new_pvid == pf->port_base_vlan_cfg.pvid)
825 hns3_add_all_vlan_table(hns);
831 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
833 struct hns3_rx_vtag_cfg rx_vlan_cfg;
834 struct hns3_hw *hw = &hns->hw;
838 rx_strip_en = on ? true : false;
839 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
840 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
841 rx_vlan_cfg.vlan1_vlan_prionly = false;
842 rx_vlan_cfg.vlan2_vlan_prionly = false;
843 rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
845 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
847 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
851 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
856 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
858 struct hns3_pf *pf = &hns->pf;
859 struct hns3_hw *hw = &hns->hw;
860 uint16_t port_base_vlan_state;
864 if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
865 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
866 hns3_warn(hw, "Invalid operation! As current pvid set "
867 "is %u, disable pvid %u is invalid",
868 pf->port_base_vlan_cfg.pvid, pvid);
872 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
873 HNS3_PORT_BASE_VLAN_DISABLE;
874 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
876 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
880 ret = hns3_en_rx_strip_all(hns, on);
882 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
886 if (pvid == HNS3_INVLID_PVID)
888 old_pvid = pf->port_base_vlan_cfg.pvid;
889 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
892 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
898 hns3_store_port_base_vlan_info(hns, pvid, on);
903 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
905 struct hns3_adapter *hns = dev->data->dev_private;
906 struct hns3_hw *hw = &hns->hw;
909 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
910 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
911 RTE_ETHER_MAX_VLAN_ID);
915 rte_spinlock_lock(&hw->lock);
916 ret = hns3_vlan_pvid_configure(hns, pvid, on);
917 rte_spinlock_unlock(&hw->lock);
922 init_port_base_vlan_info(struct hns3_hw *hw)
924 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
925 struct hns3_pf *pf = &hns->pf;
927 pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
928 pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
932 hns3_default_vlan_config(struct hns3_adapter *hns)
934 struct hns3_hw *hw = &hns->hw;
937 ret = hns3_set_port_vlan_filter(hns, 0, 1);
939 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
944 hns3_init_vlan_config(struct hns3_adapter *hns)
946 struct hns3_hw *hw = &hns->hw;
950 * This function can be called in the initialization and reset process,
951 * when in reset process, it means that hardware had been reseted
952 * successfully and we need to restore the hardware configuration to
953 * ensure that the hardware configuration remains unchanged before and
956 if (rte_atomic16_read(&hw->reset.resetting) == 0)
957 init_port_base_vlan_info(hw);
959 ret = hns3_vlan_filter_init(hns);
961 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
965 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
966 RTE_ETHER_TYPE_VLAN);
968 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
973 * When in the reinit dev stage of the reset process, the following
974 * vlan-related configurations may differ from those at initialization,
975 * we will restore configurations to hardware in hns3_restore_vlan_table
976 * and hns3_restore_vlan_conf later.
978 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
979 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
981 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
985 ret = hns3_en_hw_strip_rxvtag(hns, false);
987 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
993 return hns3_default_vlan_config(hns);
997 hns3_restore_vlan_conf(struct hns3_adapter *hns)
999 struct hns3_pf *pf = &hns->pf;
1000 struct hns3_hw *hw = &hns->hw;
1005 /* restore vlan filter states */
1006 offloads = hw->data->dev_conf.rxmode.offloads;
1007 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1008 ret = hns3_enable_vlan_filter(hns, enable);
1010 hns3_err(hw, "failed to restore vlan rx filter conf, ret = %d",
1015 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1017 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1021 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1023 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1029 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1031 struct hns3_adapter *hns = dev->data->dev_private;
1032 struct rte_eth_dev_data *data = dev->data;
1033 struct rte_eth_txmode *txmode;
1034 struct hns3_hw *hw = &hns->hw;
1038 txmode = &data->dev_conf.txmode;
1039 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1041 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1042 "configuration is not supported! Ignore these two "
1043 "parameters: hw_vlan_reject_tagged(%d), "
1044 "hw_vlan_reject_untagged(%d)",
1045 txmode->hw_vlan_reject_tagged,
1046 txmode->hw_vlan_reject_untagged);
1048 /* Apply vlan offload setting */
1049 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1050 ret = hns3_vlan_offload_set(dev, mask);
1052 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1057 /* Apply pvid setting */
1058 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1059 txmode->hw_vlan_insert_pvid);
1061 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1068 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1069 unsigned int tso_mss_max)
1071 struct hns3_cfg_tso_status_cmd *req;
1072 struct hns3_cmd_desc desc;
1075 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1077 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1080 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1082 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1085 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1087 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1089 return hns3_cmd_send(hw, &desc, 1);
1093 hns3_config_gro(struct hns3_hw *hw, bool en)
1095 struct hns3_cfg_gro_status_cmd *req;
1096 struct hns3_cmd_desc desc;
1099 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1100 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1102 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1104 ret = hns3_cmd_send(hw, &desc, 1);
1106 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1112 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1113 uint16_t *allocated_size, bool is_alloc)
1115 struct hns3_umv_spc_alc_cmd *req;
1116 struct hns3_cmd_desc desc;
1119 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1120 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1121 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1122 req->space_size = rte_cpu_to_le_32(space_size);
1124 ret = hns3_cmd_send(hw, &desc, 1);
1126 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1127 is_alloc ? "allocate" : "free", ret);
1131 if (is_alloc && allocated_size)
1132 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1138 hns3_init_umv_space(struct hns3_hw *hw)
1140 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1141 struct hns3_pf *pf = &hns->pf;
1142 uint16_t allocated_size = 0;
1145 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1150 if (allocated_size < pf->wanted_umv_size)
1151 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1152 pf->wanted_umv_size, allocated_size);
1154 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1155 pf->wanted_umv_size;
1156 pf->used_umv_size = 0;
1161 hns3_uninit_umv_space(struct hns3_hw *hw)
1163 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1164 struct hns3_pf *pf = &hns->pf;
1167 if (pf->max_umv_size == 0)
1170 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1174 pf->max_umv_size = 0;
1180 hns3_is_umv_space_full(struct hns3_hw *hw)
1182 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1183 struct hns3_pf *pf = &hns->pf;
1186 is_full = (pf->used_umv_size >= pf->max_umv_size);
1192 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1194 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1195 struct hns3_pf *pf = &hns->pf;
1198 if (pf->used_umv_size > 0)
1199 pf->used_umv_size--;
1201 pf->used_umv_size++;
1205 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1206 const uint8_t *addr, bool is_mc)
1208 const unsigned char *mac_addr = addr;
1209 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1210 ((uint32_t)mac_addr[2] << 16) |
1211 ((uint32_t)mac_addr[1] << 8) |
1212 (uint32_t)mac_addr[0];
1213 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1215 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1217 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1218 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1219 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1222 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1223 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1227 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1229 enum hns3_mac_vlan_tbl_opcode op)
1232 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1237 if (op == HNS3_MAC_VLAN_ADD) {
1238 if (resp_code == 0 || resp_code == 1) {
1240 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1241 hns3_err(hw, "add mac addr failed for uc_overflow");
1243 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1244 hns3_err(hw, "add mac addr failed for mc_overflow");
1248 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1251 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1252 if (resp_code == 0) {
1254 } else if (resp_code == 1) {
1255 hns3_dbg(hw, "remove mac addr failed for miss");
1259 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1262 } else if (op == HNS3_MAC_VLAN_LKUP) {
1263 if (resp_code == 0) {
1265 } else if (resp_code == 1) {
1266 hns3_dbg(hw, "lookup mac addr failed for miss");
1270 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1275 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1282 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1283 struct hns3_mac_vlan_tbl_entry_cmd *req,
1284 struct hns3_cmd_desc *desc, bool is_mc)
1290 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1292 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1293 memcpy(desc[0].data, req,
1294 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1295 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1297 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1298 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1300 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1302 memcpy(desc[0].data, req,
1303 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1304 ret = hns3_cmd_send(hw, desc, 1);
1307 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1311 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1312 retval = rte_le_to_cpu_16(desc[0].retval);
1314 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1315 HNS3_MAC_VLAN_LKUP);
1319 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1320 struct hns3_mac_vlan_tbl_entry_cmd *req,
1321 struct hns3_cmd_desc *mc_desc)
1328 if (mc_desc == NULL) {
1329 struct hns3_cmd_desc desc;
1331 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1332 memcpy(desc.data, req,
1333 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1334 ret = hns3_cmd_send(hw, &desc, 1);
1335 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1336 retval = rte_le_to_cpu_16(desc.retval);
1338 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1341 hns3_cmd_reuse_desc(&mc_desc[0], false);
1342 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1343 hns3_cmd_reuse_desc(&mc_desc[1], false);
1344 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1345 hns3_cmd_reuse_desc(&mc_desc[2], false);
1346 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1347 memcpy(mc_desc[0].data, req,
1348 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1349 mc_desc[0].retval = 0;
1350 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1351 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1352 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1354 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1359 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1367 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1368 struct hns3_mac_vlan_tbl_entry_cmd *req)
1370 struct hns3_cmd_desc desc;
1375 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1377 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1379 ret = hns3_cmd_send(hw, &desc, 1);
1381 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1384 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1385 retval = rte_le_to_cpu_16(desc.retval);
1387 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1388 HNS3_MAC_VLAN_REMOVE);
1392 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1394 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1395 struct hns3_mac_vlan_tbl_entry_cmd req;
1396 struct hns3_pf *pf = &hns->pf;
1397 struct hns3_cmd_desc desc;
1398 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1399 uint16_t egress_port = 0;
1403 /* check if mac addr is valid */
1404 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1405 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1407 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1412 memset(&req, 0, sizeof(req));
1415 * In current version VF is not supported when PF is driven by DPDK
1416 * driver, the PF-related vf_id is 0, just need to configure parameters
1420 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1421 HNS3_MAC_EPORT_VFID_S, vf_id);
1423 req.egress_port = rte_cpu_to_le_16(egress_port);
1425 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1428 * Lookup the mac address in the mac_vlan table, and add
1429 * it if the entry is inexistent. Repeated unicast entry
1430 * is not allowed in the mac vlan table.
1432 ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1433 if (ret == -ENOENT) {
1434 if (!hns3_is_umv_space_full(hw)) {
1435 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1437 hns3_update_umv_space(hw, false);
1441 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1446 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1448 /* check if we just hit the duplicate */
1450 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1454 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1461 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1463 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1464 struct rte_ether_addr *addr;
1468 for (i = 0; i < hw->mc_addrs_num; i++) {
1469 addr = &hw->mc_addrs[i];
1470 /* Check if there are duplicate addresses */
1471 if (rte_is_same_ether_addr(addr, mac_addr)) {
1472 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1474 hns3_err(hw, "failed to add mc mac addr, same addrs"
1475 "(%s) is added by the set_mc_mac_addr_list "
1481 ret = hns3_add_mc_addr(hw, mac_addr);
1483 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1485 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1492 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1494 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1497 ret = hns3_remove_mc_addr(hw, mac_addr);
1499 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1501 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1508 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1509 uint32_t idx, __rte_unused uint32_t pool)
1511 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1512 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1515 rte_spinlock_lock(&hw->lock);
1518 * In hns3 network engine adding UC and MC mac address with different
1519 * commands with firmware. We need to determine whether the input
1520 * address is a UC or a MC address to call different commands.
1521 * By the way, it is recommended calling the API function named
1522 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1523 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1524 * may affect the specifications of UC mac addresses.
1526 if (rte_is_multicast_ether_addr(mac_addr))
1527 ret = hns3_add_mc_addr_common(hw, mac_addr);
1529 ret = hns3_add_uc_addr_common(hw, mac_addr);
1532 rte_spinlock_unlock(&hw->lock);
1533 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1535 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1541 hw->mac.default_addr_setted = true;
1542 rte_spinlock_unlock(&hw->lock);
1548 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1550 struct hns3_mac_vlan_tbl_entry_cmd req;
1551 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1554 /* check if mac addr is valid */
1555 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1556 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1558 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1563 memset(&req, 0, sizeof(req));
1564 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1565 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1566 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1567 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1570 hns3_update_umv_space(hw, true);
1576 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1578 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1579 /* index will be checked by upper level rte interface */
1580 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1581 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1584 rte_spinlock_lock(&hw->lock);
1586 if (rte_is_multicast_ether_addr(mac_addr))
1587 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1589 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1590 rte_spinlock_unlock(&hw->lock);
1592 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1594 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1600 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1601 struct rte_ether_addr *mac_addr)
1603 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1604 struct rte_ether_addr *oaddr;
1605 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1606 bool default_addr_setted;
1607 bool rm_succes = false;
1611 * It has been guaranteed that input parameter named mac_addr is valid
1612 * address in the rte layer of DPDK framework.
1614 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1615 default_addr_setted = hw->mac.default_addr_setted;
1616 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1619 rte_spinlock_lock(&hw->lock);
1620 if (default_addr_setted) {
1621 ret = hns3_remove_uc_addr_common(hw, oaddr);
1623 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1625 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1632 ret = hns3_add_uc_addr_common(hw, mac_addr);
1634 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1636 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1637 goto err_add_uc_addr;
1640 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1642 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1643 goto err_pause_addr_cfg;
1646 rte_ether_addr_copy(mac_addr,
1647 (struct rte_ether_addr *)hw->mac.mac_addr);
1648 hw->mac.default_addr_setted = true;
1649 rte_spinlock_unlock(&hw->lock);
1654 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1656 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1659 "Failed to roll back to del setted mac addr(%s): %d",
1665 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1667 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1670 "Failed to restore old uc mac addr(%s): %d",
1672 hw->mac.default_addr_setted = false;
1675 rte_spinlock_unlock(&hw->lock);
1681 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1683 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1684 struct hns3_hw *hw = &hns->hw;
1685 struct rte_ether_addr *addr;
1690 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1691 addr = &hw->data->mac_addrs[i];
1692 if (rte_is_zero_ether_addr(addr))
1694 if (rte_is_multicast_ether_addr(addr))
1695 ret = del ? hns3_remove_mc_addr(hw, addr) :
1696 hns3_add_mc_addr(hw, addr);
1698 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1699 hns3_add_uc_addr_common(hw, addr);
1703 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1705 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1706 "ret = %d.", del ? "remove" : "restore",
1714 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1716 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1720 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1721 word_num = vfid / 32;
1722 bit_num = vfid % 32;
1724 desc[1].data[word_num] &=
1725 rte_cpu_to_le_32(~(1UL << bit_num));
1727 desc[1].data[word_num] |=
1728 rte_cpu_to_le_32(1UL << bit_num);
1730 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1731 bit_num = vfid % 32;
1733 desc[2].data[word_num] &=
1734 rte_cpu_to_le_32(~(1UL << bit_num));
1736 desc[2].data[word_num] |=
1737 rte_cpu_to_le_32(1UL << bit_num);
1742 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1744 struct hns3_mac_vlan_tbl_entry_cmd req;
1745 struct hns3_cmd_desc desc[3];
1746 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1750 /* Check if mac addr is valid */
1751 if (!rte_is_multicast_ether_addr(mac_addr)) {
1752 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1754 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1759 memset(&req, 0, sizeof(req));
1760 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1761 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1762 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1764 /* This mac addr do not exist, add new entry for it */
1765 memset(desc[0].data, 0, sizeof(desc[0].data));
1766 memset(desc[1].data, 0, sizeof(desc[0].data));
1767 memset(desc[2].data, 0, sizeof(desc[0].data));
1771 * In current version VF is not supported when PF is driven by DPDK
1772 * driver, the PF-related vf_id is 0, just need to configure parameters
1776 hns3_update_desc_vfid(desc, vf_id, false);
1777 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1780 hns3_err(hw, "mc mac vlan table is full");
1781 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1783 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1790 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1792 struct hns3_mac_vlan_tbl_entry_cmd req;
1793 struct hns3_cmd_desc desc[3];
1794 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1798 /* Check if mac addr is valid */
1799 if (!rte_is_multicast_ether_addr(mac_addr)) {
1800 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1802 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1807 memset(&req, 0, sizeof(req));
1808 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1809 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1810 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1813 * This mac addr exist, remove this handle's VFID for it.
1814 * In current version VF is not supported when PF is driven by
1815 * DPDK driver, the PF-related vf_id is 0, just need to
1816 * configure parameters for vf_id 0.
1819 hns3_update_desc_vfid(desc, vf_id, true);
1821 /* All the vfid is zero, so need to delete this entry */
1822 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1823 } else if (ret == -ENOENT) {
1824 /* This mac addr doesn't exist. */
1829 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1831 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1838 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1839 struct rte_ether_addr *mc_addr_set,
1840 uint32_t nb_mc_addr)
1842 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1843 struct rte_ether_addr *addr;
1847 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1848 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1849 "invalid. valid range: 0~%d",
1850 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1854 /* Check if input mac addresses are valid */
1855 for (i = 0; i < nb_mc_addr; i++) {
1856 addr = &mc_addr_set[i];
1857 if (!rte_is_multicast_ether_addr(addr)) {
1858 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1861 "failed to set mc mac addr, addr(%s) invalid.",
1866 /* Check if there are duplicate addresses */
1867 for (j = i + 1; j < nb_mc_addr; j++) {
1868 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1869 rte_ether_format_addr(mac_str,
1870 RTE_ETHER_ADDR_FMT_SIZE,
1872 hns3_err(hw, "failed to set mc mac addr, "
1873 "addrs invalid. two same addrs(%s).",
1880 * Check if there are duplicate addresses between mac_addrs
1883 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1884 if (rte_is_same_ether_addr(addr,
1885 &hw->data->mac_addrs[j])) {
1886 rte_ether_format_addr(mac_str,
1887 RTE_ETHER_ADDR_FMT_SIZE,
1889 hns3_err(hw, "failed to set mc mac addr, "
1890 "addrs invalid. addrs(%s) has already "
1891 "configured in mac_addr add API",
1902 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1903 struct rte_ether_addr *mc_addr_set,
1905 struct rte_ether_addr *reserved_addr_list,
1906 int *reserved_addr_num,
1907 struct rte_ether_addr *add_addr_list,
1909 struct rte_ether_addr *rm_addr_list,
1912 struct rte_ether_addr *addr;
1913 int current_addr_num;
1914 int reserved_num = 0;
1922 /* Calculate the mc mac address list that should be removed */
1923 current_addr_num = hw->mc_addrs_num;
1924 for (i = 0; i < current_addr_num; i++) {
1925 addr = &hw->mc_addrs[i];
1927 for (j = 0; j < mc_addr_num; j++) {
1928 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1935 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1938 rte_ether_addr_copy(addr,
1939 &reserved_addr_list[reserved_num]);
1944 /* Calculate the mc mac address list that should be added */
1945 for (i = 0; i < mc_addr_num; i++) {
1946 addr = &mc_addr_set[i];
1948 for (j = 0; j < current_addr_num; j++) {
1949 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1956 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1961 /* Reorder the mc mac address list maintained by driver */
1962 for (i = 0; i < reserved_num; i++)
1963 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1965 for (i = 0; i < rm_num; i++) {
1966 num = reserved_num + i;
1967 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1970 *reserved_addr_num = reserved_num;
1971 *add_addr_num = add_num;
1972 *rm_addr_num = rm_num;
1976 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1977 struct rte_ether_addr *mc_addr_set,
1978 uint32_t nb_mc_addr)
1980 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1981 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1982 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1983 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1984 struct rte_ether_addr *addr;
1985 int reserved_addr_num;
1993 /* Check if input parameters are valid */
1994 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1998 rte_spinlock_lock(&hw->lock);
2001 * Calculate the mc mac address lists those should be removed and be
2002 * added, Reorder the mc mac address list maintained by driver.
2004 mc_addr_num = (int)nb_mc_addr;
2005 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2006 reserved_addr_list, &reserved_addr_num,
2007 add_addr_list, &add_addr_num,
2008 rm_addr_list, &rm_addr_num);
2010 /* Remove mc mac addresses */
2011 for (i = 0; i < rm_addr_num; i++) {
2012 num = rm_addr_num - i - 1;
2013 addr = &rm_addr_list[num];
2014 ret = hns3_remove_mc_addr(hw, addr);
2016 rte_spinlock_unlock(&hw->lock);
2022 /* Add mc mac addresses */
2023 for (i = 0; i < add_addr_num; i++) {
2024 addr = &add_addr_list[i];
2025 ret = hns3_add_mc_addr(hw, addr);
2027 rte_spinlock_unlock(&hw->lock);
2031 num = reserved_addr_num + i;
2032 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2035 rte_spinlock_unlock(&hw->lock);
2041 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2043 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2044 struct hns3_hw *hw = &hns->hw;
2045 struct rte_ether_addr *addr;
2050 for (i = 0; i < hw->mc_addrs_num; i++) {
2051 addr = &hw->mc_addrs[i];
2052 if (!rte_is_multicast_ether_addr(addr))
2055 ret = hns3_remove_mc_addr(hw, addr);
2057 ret = hns3_add_mc_addr(hw, addr);
2060 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2062 hns3_dbg(hw, "%s mc mac addr: %s failed",
2063 del ? "Remove" : "Restore", mac_str);
2070 hns3_check_mq_mode(struct rte_eth_dev *dev)
2072 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2073 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2074 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2075 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2076 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2077 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2082 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2083 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2085 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2086 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2087 "rx_mq_mode = %d", rx_mq_mode);
2091 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2092 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2093 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2094 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2095 rx_mq_mode, tx_mq_mode);
2099 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2100 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2101 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2102 dcb_rx_conf->nb_tcs, pf->tc_max);
2106 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2107 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2108 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2109 "nb_tcs(%d) != %d or %d in rx direction.",
2110 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2114 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2115 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2116 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2120 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2121 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2122 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2123 "is not equal to one in tx direction.",
2124 i, dcb_rx_conf->dcb_tc[i]);
2127 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2128 max_tc = dcb_rx_conf->dcb_tc[i];
2131 num_tc = max_tc + 1;
2132 if (num_tc > dcb_rx_conf->nb_tcs) {
2133 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2134 num_tc, dcb_rx_conf->nb_tcs);
2143 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2145 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2147 if (!hns3_dev_dcb_supported(hw)) {
2148 hns3_err(hw, "this port does not support dcb configurations.");
2152 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2153 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2157 /* Check multiple queue mode */
2158 return hns3_check_mq_mode(dev);
2162 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2163 enum hns3_ring_type queue_type, uint16_t queue_id)
2165 struct hns3_cmd_desc desc;
2166 struct hns3_ctrl_vector_chain_cmd *req =
2167 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2168 enum hns3_cmd_status status;
2169 enum hns3_opcode_type op;
2170 uint16_t tqp_type_and_id = 0;
2175 op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2176 hns3_cmd_setup_basic_desc(&desc, op, false);
2177 req->int_vector_id = vector_id;
2179 if (queue_type == HNS3_RING_TYPE_RX)
2180 gl = HNS3_RING_GL_RX;
2182 gl = HNS3_RING_GL_TX;
2186 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2188 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2189 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2191 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2192 req->int_cause_num = 1;
2193 op_str = mmap ? "Map" : "Unmap";
2194 status = hns3_cmd_send(hw, &desc, 1);
2196 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2197 op_str, queue_id, req->int_vector_id, status);
2205 hns3_init_ring_with_vector(struct hns3_hw *hw)
2212 * In hns3 network engine, vector 0 is always the misc interrupt of this
2213 * function, vector 1~N can be used respectively for the queues of the
2214 * function. Tx and Rx queues with the same number share the interrupt
2215 * vector. In the initialization clearing the all hardware mapping
2216 * relationship configurations between queues and interrupt vectors is
2217 * needed, so some error caused by the residual configurations, such as
2218 * the unexpected Tx interrupt, can be avoid. Because of the hardware
2219 * constraints in hns3 hardware engine, we have to implement clearing
2220 * the mapping relationship configurations by binding all queues to the
2221 * last interrupt vector and reserving the last interrupt vector. This
2222 * method results in a decrease of the maximum queues when upper
2223 * applications call the rte_eth_dev_configure API function to enable
2226 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2227 hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
2228 for (i = 0; i < hw->intr_tqps_num; i++) {
2230 * Set gap limiter and rate limiter configuration of queue's
2233 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2234 HNS3_TQP_INTR_GL_DEFAULT);
2235 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2236 HNS3_TQP_INTR_GL_DEFAULT);
2237 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2239 ret = hns3_bind_ring_with_vector(hw, vec, false,
2240 HNS3_RING_TYPE_TX, i);
2242 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2243 "vector: %d, ret=%d", i, vec, ret);
2247 ret = hns3_bind_ring_with_vector(hw, vec, false,
2248 HNS3_RING_TYPE_RX, i);
2250 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2251 "vector: %d, ret=%d", i, vec, ret);
2260 hns3_dev_configure(struct rte_eth_dev *dev)
2262 struct hns3_adapter *hns = dev->data->dev_private;
2263 struct rte_eth_conf *conf = &dev->data->dev_conf;
2264 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2265 struct hns3_hw *hw = &hns->hw;
2266 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2267 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2268 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2269 struct rte_eth_rss_conf rss_conf;
2274 * Hardware does not support individually enable/disable/reset the Tx or
2275 * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2276 * and Rx queues at the same time. When the numbers of Tx queues
2277 * allocated by upper applications are not equal to the numbers of Rx
2278 * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2279 * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2280 * these fake queues are imperceptible, and can not be used by upper
2283 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2285 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2289 hw->adapter_state = HNS3_NIC_CONFIGURING;
2290 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2291 hns3_err(hw, "setting link speed/duplex not supported");
2296 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2297 ret = hns3_check_dcb_cfg(dev);
2302 /* When RSS is not configured, redirect the packet queue 0 */
2303 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2304 rss_conf = conf->rx_adv_conf.rss_conf;
2305 if (rss_conf.rss_key == NULL) {
2306 rss_conf.rss_key = rss_cfg->key;
2307 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2310 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2316 * If jumbo frames are enabled, MTU needs to be refreshed
2317 * according to the maximum RX packet length.
2319 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2321 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2322 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2323 * can safely assign to "uint16_t" type variable.
2325 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2326 ret = hns3_dev_mtu_set(dev, mtu);
2329 dev->data->mtu = mtu;
2332 ret = hns3_dev_configure_vlan(dev);
2336 hw->adapter_state = HNS3_NIC_CONFIGURED;
2341 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2342 hw->adapter_state = HNS3_NIC_INITIALIZED;
2348 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2350 struct hns3_config_max_frm_size_cmd *req;
2351 struct hns3_cmd_desc desc;
2353 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2355 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2356 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2357 req->min_frm_size = RTE_ETHER_MIN_LEN;
2359 return hns3_cmd_send(hw, &desc, 1);
2363 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2367 ret = hns3_set_mac_mtu(hw, mps);
2369 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2373 ret = hns3_buffer_alloc(hw);
2375 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2381 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2383 struct hns3_adapter *hns = dev->data->dev_private;
2384 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2385 struct hns3_hw *hw = &hns->hw;
2386 bool is_jumbo_frame;
2389 if (dev->data->dev_started) {
2390 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2391 "before configuration", dev->data->port_id);
2395 rte_spinlock_lock(&hw->lock);
2396 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2397 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2400 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2401 * assign to "uint16_t" type variable.
2403 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2405 rte_spinlock_unlock(&hw->lock);
2406 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2407 dev->data->port_id, mtu, ret);
2410 hns->pf.mps = (uint16_t)frame_size;
2412 dev->data->dev_conf.rxmode.offloads |=
2413 DEV_RX_OFFLOAD_JUMBO_FRAME;
2415 dev->data->dev_conf.rxmode.offloads &=
2416 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2417 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2418 rte_spinlock_unlock(&hw->lock);
2424 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2426 struct hns3_adapter *hns = eth_dev->data->dev_private;
2427 struct hns3_hw *hw = &hns->hw;
2428 uint16_t queue_num = hw->tqps_num;
2431 * In interrupt mode, 'max_rx_queues' is set based on the number of
2432 * MSI-X interrupt resources of the hardware.
2434 if (hw->data->dev_conf.intr_conf.rxq == 1)
2435 queue_num = hw->intr_tqps_num;
2437 info->max_rx_queues = queue_num;
2438 info->max_tx_queues = hw->tqps_num;
2439 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2440 info->min_rx_bufsize = hw->rx_buf_len;
2441 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2442 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2443 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2444 DEV_RX_OFFLOAD_TCP_CKSUM |
2445 DEV_RX_OFFLOAD_UDP_CKSUM |
2446 DEV_RX_OFFLOAD_SCTP_CKSUM |
2447 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2448 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2449 DEV_RX_OFFLOAD_KEEP_CRC |
2450 DEV_RX_OFFLOAD_SCATTER |
2451 DEV_RX_OFFLOAD_VLAN_STRIP |
2452 DEV_RX_OFFLOAD_QINQ_STRIP |
2453 DEV_RX_OFFLOAD_VLAN_FILTER |
2454 DEV_RX_OFFLOAD_VLAN_EXTEND |
2455 DEV_RX_OFFLOAD_JUMBO_FRAME |
2456 DEV_RX_OFFLOAD_RSS_HASH);
2457 info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2458 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2459 DEV_TX_OFFLOAD_IPV4_CKSUM |
2460 DEV_TX_OFFLOAD_TCP_CKSUM |
2461 DEV_TX_OFFLOAD_UDP_CKSUM |
2462 DEV_TX_OFFLOAD_SCTP_CKSUM |
2463 DEV_TX_OFFLOAD_VLAN_INSERT |
2464 DEV_TX_OFFLOAD_QINQ_INSERT |
2465 DEV_TX_OFFLOAD_MULTI_SEGS |
2466 DEV_TX_OFFLOAD_TCP_TSO |
2467 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2468 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2469 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2470 info->tx_queue_offload_capa);
2472 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2473 .nb_max = HNS3_MAX_RING_DESC,
2474 .nb_min = HNS3_MIN_RING_DESC,
2475 .nb_align = HNS3_ALIGN_RING_DESC,
2478 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2479 .nb_max = HNS3_MAX_RING_DESC,
2480 .nb_min = HNS3_MIN_RING_DESC,
2481 .nb_align = HNS3_ALIGN_RING_DESC,
2484 info->vmdq_queue_num = 0;
2486 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2487 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2488 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2490 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2491 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2492 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2493 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2494 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2495 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2501 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2504 struct hns3_adapter *hns = eth_dev->data->dev_private;
2505 struct hns3_hw *hw = &hns->hw;
2508 ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2509 ret += 1; /* add the size of '\0' */
2510 if (fw_size < (uint32_t)ret)
2517 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2518 __rte_unused int wait_to_complete)
2520 struct hns3_adapter *hns = eth_dev->data->dev_private;
2521 struct hns3_hw *hw = &hns->hw;
2522 struct hns3_mac *mac = &hw->mac;
2523 struct rte_eth_link new_link;
2525 if (!hns3_is_reset_pending(hns)) {
2526 hns3_update_speed_duplex(eth_dev);
2527 hns3_update_link_status(hw);
2530 memset(&new_link, 0, sizeof(new_link));
2531 switch (mac->link_speed) {
2532 case ETH_SPEED_NUM_10M:
2533 case ETH_SPEED_NUM_100M:
2534 case ETH_SPEED_NUM_1G:
2535 case ETH_SPEED_NUM_10G:
2536 case ETH_SPEED_NUM_25G:
2537 case ETH_SPEED_NUM_40G:
2538 case ETH_SPEED_NUM_50G:
2539 case ETH_SPEED_NUM_100G:
2540 new_link.link_speed = mac->link_speed;
2543 new_link.link_speed = ETH_SPEED_NUM_100M;
2547 new_link.link_duplex = mac->link_duplex;
2548 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2549 new_link.link_autoneg =
2550 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2552 return rte_eth_linkstatus_set(eth_dev, &new_link);
2556 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2558 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2559 struct hns3_pf *pf = &hns->pf;
2561 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2564 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2570 hns3_query_function_status(struct hns3_hw *hw)
2572 #define HNS3_QUERY_MAX_CNT 10
2573 #define HNS3_QUERY_SLEEP_MSCOEND 1
2574 struct hns3_func_status_cmd *req;
2575 struct hns3_cmd_desc desc;
2579 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2580 req = (struct hns3_func_status_cmd *)desc.data;
2583 ret = hns3_cmd_send(hw, &desc, 1);
2585 PMD_INIT_LOG(ERR, "query function status failed %d",
2590 /* Check pf reset is done */
2594 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2595 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2597 return hns3_parse_func_status(hw, req);
2601 hns3_query_pf_resource(struct hns3_hw *hw)
2603 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2604 struct hns3_pf *pf = &hns->pf;
2605 struct hns3_pf_res_cmd *req;
2606 struct hns3_cmd_desc desc;
2610 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2611 ret = hns3_cmd_send(hw, &desc, 1);
2613 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2617 req = (struct hns3_pf_res_cmd *)desc.data;
2618 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2619 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2620 hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2621 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2623 if (req->tx_buf_size)
2625 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2627 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2629 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2631 if (req->dv_buf_size)
2633 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2635 pf->dv_buf_size = HNS3_DEFAULT_DV;
2637 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2639 num_msi = hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2640 HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2641 hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
2647 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2649 struct hns3_cfg_param_cmd *req;
2650 uint64_t mac_addr_tmp_high;
2651 uint64_t mac_addr_tmp;
2654 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2656 /* get the configuration */
2657 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2658 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2659 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2660 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2661 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2662 HNS3_CFG_TQP_DESC_N_M,
2663 HNS3_CFG_TQP_DESC_N_S);
2665 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2666 HNS3_CFG_PHY_ADDR_M,
2667 HNS3_CFG_PHY_ADDR_S);
2668 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2669 HNS3_CFG_MEDIA_TP_M,
2670 HNS3_CFG_MEDIA_TP_S);
2671 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2672 HNS3_CFG_RX_BUF_LEN_M,
2673 HNS3_CFG_RX_BUF_LEN_S);
2674 /* get mac address */
2675 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2676 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2677 HNS3_CFG_MAC_ADDR_H_M,
2678 HNS3_CFG_MAC_ADDR_H_S);
2680 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2682 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2683 HNS3_CFG_DEFAULT_SPEED_M,
2684 HNS3_CFG_DEFAULT_SPEED_S);
2685 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2686 HNS3_CFG_RSS_SIZE_M,
2687 HNS3_CFG_RSS_SIZE_S);
2689 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2690 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2692 req = (struct hns3_cfg_param_cmd *)desc[1].data;
2693 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2695 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2696 HNS3_CFG_SPEED_ABILITY_M,
2697 HNS3_CFG_SPEED_ABILITY_S);
2698 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2699 HNS3_CFG_UMV_TBL_SPACE_M,
2700 HNS3_CFG_UMV_TBL_SPACE_S);
2701 if (!cfg->umv_space)
2702 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2705 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2706 * @hw: pointer to struct hns3_hw
2707 * @hcfg: the config structure to be getted
2710 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2712 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2713 struct hns3_cfg_param_cmd *req;
2718 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2720 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2721 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2723 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2724 i * HNS3_CFG_RD_LEN_BYTES);
2725 /* Len should be divided by 4 when send to hardware */
2726 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2727 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2728 req->offset = rte_cpu_to_le_32(offset);
2731 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2733 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2737 hns3_parse_cfg(hcfg, desc);
2743 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2745 switch (speed_cmd) {
2746 case HNS3_CFG_SPEED_10M:
2747 *speed = ETH_SPEED_NUM_10M;
2749 case HNS3_CFG_SPEED_100M:
2750 *speed = ETH_SPEED_NUM_100M;
2752 case HNS3_CFG_SPEED_1G:
2753 *speed = ETH_SPEED_NUM_1G;
2755 case HNS3_CFG_SPEED_10G:
2756 *speed = ETH_SPEED_NUM_10G;
2758 case HNS3_CFG_SPEED_25G:
2759 *speed = ETH_SPEED_NUM_25G;
2761 case HNS3_CFG_SPEED_40G:
2762 *speed = ETH_SPEED_NUM_40G;
2764 case HNS3_CFG_SPEED_50G:
2765 *speed = ETH_SPEED_NUM_50G;
2767 case HNS3_CFG_SPEED_100G:
2768 *speed = ETH_SPEED_NUM_100G;
2778 hns3_get_board_configuration(struct hns3_hw *hw)
2780 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2781 struct hns3_pf *pf = &hns->pf;
2782 struct hns3_cfg cfg;
2785 ret = hns3_get_board_cfg(hw, &cfg);
2787 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2791 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2792 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2796 hw->mac.media_type = cfg.media_type;
2797 hw->rss_size_max = cfg.rss_size_max;
2798 hw->rss_dis_flag = false;
2799 hw->rx_buf_len = cfg.rx_buf_len;
2800 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2801 hw->mac.phy_addr = cfg.phy_addr;
2802 hw->mac.default_addr_setted = false;
2803 hw->num_tx_desc = cfg.tqp_desc_num;
2804 hw->num_rx_desc = cfg.tqp_desc_num;
2805 hw->dcb_info.num_pg = 1;
2806 hw->dcb_info.hw_pfc_map = 0;
2808 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2810 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2811 cfg.default_speed, ret);
2815 pf->tc_max = cfg.tc_num;
2816 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2817 PMD_INIT_LOG(WARNING,
2818 "Get TC num(%u) from flash, set TC num to 1",
2823 /* Dev does not support DCB */
2824 if (!hns3_dev_dcb_supported(hw)) {
2828 pf->pfc_max = pf->tc_max;
2830 hw->dcb_info.num_tc = 1;
2831 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2832 hw->tqps_num / hw->dcb_info.num_tc);
2833 hns3_set_bit(hw->hw_tc_map, 0, 1);
2834 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2836 pf->wanted_umv_size = cfg.umv_space;
2842 hns3_get_configuration(struct hns3_hw *hw)
2846 ret = hns3_query_function_status(hw);
2848 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2852 /* Get pf resource */
2853 ret = hns3_query_pf_resource(hw);
2855 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2859 ret = hns3_get_board_configuration(hw);
2861 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2867 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2868 uint16_t tqp_vid, bool is_pf)
2870 struct hns3_tqp_map_cmd *req;
2871 struct hns3_cmd_desc desc;
2874 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2876 req = (struct hns3_tqp_map_cmd *)desc.data;
2877 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2878 req->tqp_vf = func_id;
2879 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2881 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2882 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2884 ret = hns3_cmd_send(hw, &desc, 1);
2886 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2892 hns3_map_tqp(struct hns3_hw *hw)
2894 uint16_t tqps_num = hw->total_tqps_num;
2903 * In current version VF is not supported when PF is driven by DPDK
2904 * driver, so we allocate tqps to PF as much as possible.
2907 num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2908 for (func_id = 0; func_id < num; func_id++) {
2909 is_pf = func_id == 0 ? true : false;
2911 i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2912 ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2923 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2925 struct hns3_config_mac_speed_dup_cmd *req;
2926 struct hns3_cmd_desc desc;
2929 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2931 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2933 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2936 case ETH_SPEED_NUM_10M:
2937 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2938 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2940 case ETH_SPEED_NUM_100M:
2941 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2942 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2944 case ETH_SPEED_NUM_1G:
2945 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2946 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2948 case ETH_SPEED_NUM_10G:
2949 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2950 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2952 case ETH_SPEED_NUM_25G:
2953 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2954 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2956 case ETH_SPEED_NUM_40G:
2957 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2958 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2960 case ETH_SPEED_NUM_50G:
2961 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2962 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2964 case ETH_SPEED_NUM_100G:
2965 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2966 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2969 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2973 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2975 ret = hns3_cmd_send(hw, &desc, 1);
2977 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2983 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2985 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2986 struct hns3_pf *pf = &hns->pf;
2987 struct hns3_priv_buf *priv;
2988 uint32_t i, total_size;
2990 total_size = pf->pkt_buf_size;
2992 /* alloc tx buffer for all enabled tc */
2993 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2994 priv = &buf_alloc->priv_buf[i];
2996 if (hw->hw_tc_map & BIT(i)) {
2997 if (total_size < pf->tx_buf_size)
3000 priv->tx_buf_size = pf->tx_buf_size;
3002 priv->tx_buf_size = 0;
3004 total_size -= priv->tx_buf_size;
3011 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3013 /* TX buffer size is unit by 128 byte */
3014 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3015 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3016 struct hns3_tx_buff_alloc_cmd *req;
3017 struct hns3_cmd_desc desc;
3022 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3024 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3025 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3026 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3028 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3029 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3030 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3033 ret = hns3_cmd_send(hw, &desc, 1);
3035 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3041 hns3_get_tc_num(struct hns3_hw *hw)
3046 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3047 if (hw->hw_tc_map & BIT(i))
3053 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3055 struct hns3_priv_buf *priv;
3056 uint32_t rx_priv = 0;
3059 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3060 priv = &buf_alloc->priv_buf[i];
3062 rx_priv += priv->buf_size;
3068 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3070 uint32_t total_tx_size = 0;
3073 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3074 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3076 return total_tx_size;
3079 /* Get the number of pfc enabled TCs, which have private buffer */
3081 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3083 struct hns3_priv_buf *priv;
3087 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3088 priv = &buf_alloc->priv_buf[i];
3089 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3096 /* Get the number of pfc disabled TCs, which have private buffer */
3098 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3099 struct hns3_pkt_buf_alloc *buf_alloc)
3101 struct hns3_priv_buf *priv;
3105 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3106 priv = &buf_alloc->priv_buf[i];
3107 if (hw->hw_tc_map & BIT(i) &&
3108 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3116 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3119 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3120 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3121 struct hns3_pf *pf = &hns->pf;
3122 uint32_t shared_buf, aligned_mps;
3127 tc_num = hns3_get_tc_num(hw);
3128 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3130 if (hns3_dev_dcb_supported(hw))
3131 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3134 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3137 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3138 shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3139 HNS3_BUF_SIZE_UNIT);
3141 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3142 if (rx_all < rx_priv + shared_std)
3145 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3146 buf_alloc->s_buf.buf_size = shared_buf;
3147 if (hns3_dev_dcb_supported(hw)) {
3148 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3149 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3150 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3151 HNS3_BUF_SIZE_UNIT);
3153 buf_alloc->s_buf.self.high =
3154 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3155 buf_alloc->s_buf.self.low = aligned_mps;
3158 if (hns3_dev_dcb_supported(hw)) {
3159 hi_thrd = shared_buf - pf->dv_buf_size;
3161 if (tc_num <= NEED_RESERVE_TC_NUM)
3162 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3166 hi_thrd = hi_thrd / tc_num;
3168 hi_thrd = max_t(uint32_t, hi_thrd,
3169 HNS3_BUF_MUL_BY * aligned_mps);
3170 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3171 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3173 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3174 lo_thrd = aligned_mps;
3177 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3178 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3179 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3186 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3187 struct hns3_pkt_buf_alloc *buf_alloc)
3189 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3190 struct hns3_pf *pf = &hns->pf;
3191 struct hns3_priv_buf *priv;
3192 uint32_t aligned_mps;
3196 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3197 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3199 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3200 priv = &buf_alloc->priv_buf[i];
3207 if (!(hw->hw_tc_map & BIT(i)))
3211 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3212 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3213 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3214 HNS3_BUF_SIZE_UNIT);
3217 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3221 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3224 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3228 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3229 struct hns3_pkt_buf_alloc *buf_alloc)
3231 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3232 struct hns3_pf *pf = &hns->pf;
3233 struct hns3_priv_buf *priv;
3234 int no_pfc_priv_num;
3239 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3240 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3242 /* let the last to be cleared first */
3243 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3244 priv = &buf_alloc->priv_buf[i];
3245 mask = BIT((uint8_t)i);
3247 if (hw->hw_tc_map & mask &&
3248 !(hw->dcb_info.hw_pfc_map & mask)) {
3249 /* Clear the no pfc TC private buffer */
3257 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3258 no_pfc_priv_num == 0)
3262 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3266 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3267 struct hns3_pkt_buf_alloc *buf_alloc)
3269 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3270 struct hns3_pf *pf = &hns->pf;
3271 struct hns3_priv_buf *priv;
3277 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3278 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3280 /* let the last to be cleared first */
3281 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3282 priv = &buf_alloc->priv_buf[i];
3283 mask = BIT((uint8_t)i);
3285 if (hw->hw_tc_map & mask &&
3286 hw->dcb_info.hw_pfc_map & mask) {
3287 /* Reduce the number of pfc TC with private buffer */
3294 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3299 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3303 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3304 struct hns3_pkt_buf_alloc *buf_alloc)
3306 #define COMPENSATE_BUFFER 0x3C00
3307 #define COMPENSATE_HALF_MPS_NUM 5
3308 #define PRIV_WL_GAP 0x1800
3309 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3310 struct hns3_pf *pf = &hns->pf;
3311 uint32_t tc_num = hns3_get_tc_num(hw);
3312 uint32_t half_mps = pf->mps >> 1;
3313 struct hns3_priv_buf *priv;
3314 uint32_t min_rx_priv;
3318 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3320 rx_priv = rx_priv / tc_num;
3322 if (tc_num <= NEED_RESERVE_TC_NUM)
3323 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3326 * Minimum value of private buffer in rx direction (min_rx_priv) is
3327 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3328 * buffer if rx_priv is greater than min_rx_priv.
3330 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3331 COMPENSATE_HALF_MPS_NUM * half_mps;
3332 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3333 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3335 if (rx_priv < min_rx_priv)
3338 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3339 priv = &buf_alloc->priv_buf[i];
3346 if (!(hw->hw_tc_map & BIT(i)))
3350 priv->buf_size = rx_priv;
3351 priv->wl.high = rx_priv - pf->dv_buf_size;
3352 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3355 buf_alloc->s_buf.buf_size = 0;
3361 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3362 * @hw: pointer to struct hns3_hw
3363 * @buf_alloc: pointer to buffer calculation data
3364 * @return: 0: calculate sucessful, negative: fail
3367 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3369 /* When DCB is not supported, rx private buffer is not allocated. */
3370 if (!hns3_dev_dcb_supported(hw)) {
3371 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3372 struct hns3_pf *pf = &hns->pf;
3373 uint32_t rx_all = pf->pkt_buf_size;
3375 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3376 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3383 * Try to allocate privated packet buffer for all TCs without share
3386 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3390 * Try to allocate privated packet buffer for all TCs with share
3393 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3397 * For different application scenes, the enabled port number, TC number
3398 * and no_drop TC number are different. In order to obtain the better
3399 * performance, software could allocate the buffer size and configure
3400 * the waterline by tring to decrease the private buffer size according
3401 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3404 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3407 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3410 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3417 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3419 struct hns3_rx_priv_buff_cmd *req;
3420 struct hns3_cmd_desc desc;
3425 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3426 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3428 /* Alloc private buffer TCs */
3429 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3430 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3433 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3434 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3437 buf_size = buf_alloc->s_buf.buf_size;
3438 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3439 (1 << HNS3_TC0_PRI_BUF_EN_B));
3441 ret = hns3_cmd_send(hw, &desc, 1);
3443 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3449 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3451 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3452 struct hns3_rx_priv_wl_buf *req;
3453 struct hns3_priv_buf *priv;
3454 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3458 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3459 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3461 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3463 /* The first descriptor set the NEXT bit to 1 */
3465 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3467 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3469 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3470 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3472 priv = &buf_alloc->priv_buf[idx];
3473 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3475 req->tc_wl[j].high |=
3476 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3477 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3479 req->tc_wl[j].low |=
3480 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3484 /* Send 2 descriptor at one time */
3485 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3487 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3493 hns3_common_thrd_config(struct hns3_hw *hw,
3494 struct hns3_pkt_buf_alloc *buf_alloc)
3496 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3497 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3498 struct hns3_rx_com_thrd *req;
3499 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3500 struct hns3_tc_thrd *tc;
3505 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3506 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3508 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3510 /* The first descriptor set the NEXT bit to 1 */
3512 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3514 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3516 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3517 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3518 tc = &s_buf->tc_thrd[tc_idx];
3520 req->com_thrd[j].high =
3521 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3522 req->com_thrd[j].high |=
3523 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3524 req->com_thrd[j].low =
3525 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3526 req->com_thrd[j].low |=
3527 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3531 /* Send 2 descriptors at one time */
3532 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3534 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3540 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3542 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3543 struct hns3_rx_com_wl *req;
3544 struct hns3_cmd_desc desc;
3547 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3549 req = (struct hns3_rx_com_wl *)desc.data;
3550 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3551 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3553 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3554 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3556 ret = hns3_cmd_send(hw, &desc, 1);
3558 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3564 hns3_buffer_alloc(struct hns3_hw *hw)
3566 struct hns3_pkt_buf_alloc pkt_buf;
3569 memset(&pkt_buf, 0, sizeof(pkt_buf));
3570 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3573 "could not calc tx buffer size for all TCs %d",
3578 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3580 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3584 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3587 "could not calc rx priv buffer size for all TCs %d",
3592 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3594 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3598 if (hns3_dev_dcb_supported(hw)) {
3599 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3602 "could not configure rx private waterline %d",
3607 ret = hns3_common_thrd_config(hw, &pkt_buf);
3610 "could not configure common threshold %d",
3616 ret = hns3_common_wl_config(hw, &pkt_buf);
3618 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3625 hns3_mac_init(struct hns3_hw *hw)
3627 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3628 struct hns3_mac *mac = &hw->mac;
3629 struct hns3_pf *pf = &hns->pf;
3632 pf->support_sfp_query = true;
3633 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3634 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3636 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3640 mac->link_status = ETH_LINK_DOWN;
3642 return hns3_config_mtu(hw, pf->mps);
3646 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3648 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
3649 #define HNS3_ETHERTYPE_ALREADY_ADD 1
3650 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
3651 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
3656 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3661 switch (resp_code) {
3662 case HNS3_ETHERTYPE_SUCCESS_ADD:
3663 case HNS3_ETHERTYPE_ALREADY_ADD:
3666 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3668 "add mac ethertype failed for manager table overflow.");
3669 return_status = -EIO;
3671 case HNS3_ETHERTYPE_KEY_CONFLICT:
3672 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3673 return_status = -EIO;
3677 "add mac ethertype failed for undefined, code=%d.",
3679 return_status = -EIO;
3683 return return_status;
3687 hns3_add_mgr_tbl(struct hns3_hw *hw,
3688 const struct hns3_mac_mgr_tbl_entry_cmd *req)
3690 struct hns3_cmd_desc desc;
3695 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3696 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3698 ret = hns3_cmd_send(hw, &desc, 1);
3701 "add mac ethertype failed for cmd_send, ret =%d.",
3706 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3707 retval = rte_le_to_cpu_16(desc.retval);
3709 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3713 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3714 int *table_item_num)
3716 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3719 * In current version, we add one item in management table as below:
3720 * 0x0180C200000E -- LLDP MC address
3723 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3724 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3725 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3726 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3727 tbl->i_port_bitmap = 0x1;
3728 *table_item_num = 1;
3732 hns3_init_mgr_tbl(struct hns3_hw *hw)
3734 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
3735 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3740 memset(mgr_table, 0, sizeof(mgr_table));
3741 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3742 for (i = 0; i < table_item_num; i++) {
3743 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3745 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3755 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3756 bool en_mc, bool en_bc, int vport_id)
3761 memset(param, 0, sizeof(struct hns3_promisc_param));
3763 param->enable = HNS3_PROMISC_EN_UC;
3765 param->enable |= HNS3_PROMISC_EN_MC;
3767 param->enable |= HNS3_PROMISC_EN_BC;
3768 param->vf_id = vport_id;
3772 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3774 struct hns3_promisc_cfg_cmd *req;
3775 struct hns3_cmd_desc desc;
3778 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3780 req = (struct hns3_promisc_cfg_cmd *)desc.data;
3781 req->vf_id = param->vf_id;
3782 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3783 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3785 ret = hns3_cmd_send(hw, &desc, 1);
3787 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3793 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3795 struct hns3_promisc_param param;
3796 bool en_bc_pmc = true;
3800 * In current version VF is not supported when PF is driven by DPDK
3801 * driver, the PF-related vf_id is 0, just need to configure parameters
3806 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3807 return hns3_cmd_set_promisc_mode(hw, ¶m);
3811 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3813 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3814 struct hns3_pf *pf = &hns->pf;
3815 struct hns3_promisc_param param;
3819 /* func_id 0 is denoted PF, the VFs start from 1 */
3820 for (func_id = 1; func_id < pf->func_num; func_id++) {
3821 hns3_promisc_param_init(¶m, false, false, false, func_id);
3822 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
3831 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3833 struct hns3_adapter *hns = dev->data->dev_private;
3834 struct hns3_hw *hw = &hns->hw;
3837 rte_spinlock_lock(&hw->lock);
3838 ret = hns3_set_promisc_mode(hw, true, true);
3839 rte_spinlock_unlock(&hw->lock);
3841 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
3848 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3850 bool allmulti = dev->data->all_multicast ? true : false;
3851 struct hns3_adapter *hns = dev->data->dev_private;
3852 struct hns3_hw *hw = &hns->hw;
3855 /* If now in all_multicast mode, must remain in all_multicast mode. */
3856 rte_spinlock_lock(&hw->lock);
3857 ret = hns3_set_promisc_mode(hw, false, allmulti);
3858 rte_spinlock_unlock(&hw->lock);
3860 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
3867 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3869 struct hns3_adapter *hns = dev->data->dev_private;
3870 struct hns3_hw *hw = &hns->hw;
3873 if (dev->data->promiscuous)
3876 rte_spinlock_lock(&hw->lock);
3877 ret = hns3_set_promisc_mode(hw, false, true);
3878 rte_spinlock_unlock(&hw->lock);
3880 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
3887 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3889 struct hns3_adapter *hns = dev->data->dev_private;
3890 struct hns3_hw *hw = &hns->hw;
3893 /* If now in promiscuous mode, must remain in all_multicast mode. */
3894 if (dev->data->promiscuous)
3897 rte_spinlock_lock(&hw->lock);
3898 ret = hns3_set_promisc_mode(hw, false, false);
3899 rte_spinlock_unlock(&hw->lock);
3901 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
3908 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3910 struct hns3_hw *hw = &hns->hw;
3911 bool allmulti = hw->data->all_multicast ? true : false;
3913 if (hw->data->promiscuous)
3914 return hns3_set_promisc_mode(hw, true, true);
3916 return hns3_set_promisc_mode(hw, false, allmulti);
3920 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3922 struct hns3_sfp_speed_cmd *resp;
3923 struct hns3_cmd_desc desc;
3926 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3927 resp = (struct hns3_sfp_speed_cmd *)desc.data;
3928 ret = hns3_cmd_send(hw, &desc, 1);
3929 if (ret == -EOPNOTSUPP) {
3930 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3933 hns3_err(hw, "get sfp speed failed %d", ret);
3937 *speed = resp->sfp_speed;
3943 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3945 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3946 duplex = ETH_LINK_FULL_DUPLEX;
3952 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3954 struct hns3_mac *mac = &hw->mac;
3957 duplex = hns3_check_speed_dup(duplex, speed);
3958 if (mac->link_speed == speed && mac->link_duplex == duplex)
3961 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3965 mac->link_speed = speed;
3966 mac->link_duplex = duplex;
3972 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3974 struct hns3_adapter *hns = eth_dev->data->dev_private;
3975 struct hns3_hw *hw = &hns->hw;
3976 struct hns3_pf *pf = &hns->pf;
3980 /* If IMP do not support get SFP/qSFP speed, return directly */
3981 if (!pf->support_sfp_query)
3984 ret = hns3_get_sfp_speed(hw, &speed);
3985 if (ret == -EOPNOTSUPP) {
3986 pf->support_sfp_query = false;
3991 if (speed == ETH_SPEED_NUM_NONE)
3992 return 0; /* do nothing if no SFP */
3994 /* Config full duplex for SFP */
3995 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3999 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4001 struct hns3_config_mac_mode_cmd *req;
4002 struct hns3_cmd_desc desc;
4003 uint32_t loop_en = 0;
4007 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4009 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4012 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4013 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4014 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4015 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4016 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4017 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4018 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4019 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4020 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4021 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4022 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4023 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4024 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4025 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4026 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4028 ret = hns3_cmd_send(hw, &desc, 1);
4030 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4036 hns3_get_mac_link_status(struct hns3_hw *hw)
4038 struct hns3_link_status_cmd *req;
4039 struct hns3_cmd_desc desc;
4043 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4044 ret = hns3_cmd_send(hw, &desc, 1);
4046 hns3_err(hw, "get link status cmd failed %d", ret);
4047 return ETH_LINK_DOWN;
4050 req = (struct hns3_link_status_cmd *)desc.data;
4051 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4053 return !!link_status;
4057 hns3_update_link_status(struct hns3_hw *hw)
4061 state = hns3_get_mac_link_status(hw);
4062 if (state != hw->mac.link_status) {
4063 hw->mac.link_status = state;
4064 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4069 hns3_service_handler(void *param)
4071 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4072 struct hns3_adapter *hns = eth_dev->data->dev_private;
4073 struct hns3_hw *hw = &hns->hw;
4075 if (!hns3_is_reset_pending(hns)) {
4076 hns3_update_speed_duplex(eth_dev);
4077 hns3_update_link_status(hw);
4079 hns3_warn(hw, "Cancel the query when reset is pending");
4081 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4085 hns3_init_hardware(struct hns3_adapter *hns)
4087 struct hns3_hw *hw = &hns->hw;
4090 ret = hns3_map_tqp(hw);
4092 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4096 ret = hns3_init_umv_space(hw);
4098 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4102 ret = hns3_mac_init(hw);
4104 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4108 ret = hns3_init_mgr_tbl(hw);
4110 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4114 ret = hns3_set_promisc_mode(hw, false, false);
4116 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
4120 ret = hns3_clear_all_vfs_promisc_mode(hw);
4122 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
4127 ret = hns3_init_vlan_config(hns);
4129 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4133 ret = hns3_dcb_init(hw);
4135 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4139 ret = hns3_init_fd_config(hns);
4141 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4145 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4147 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4151 ret = hns3_config_gro(hw, false);
4153 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4158 * In the initialization clearing the all hardware mapping relationship
4159 * configurations between queues and interrupt vectors is needed, so
4160 * some error caused by the residual configurations, such as the
4161 * unexpected interrupt, can be avoid.
4163 ret = hns3_init_ring_with_vector(hw);
4165 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4172 hns3_uninit_umv_space(hw);
4177 hns3_init_pf(struct rte_eth_dev *eth_dev)
4179 struct rte_device *dev = eth_dev->device;
4180 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4181 struct hns3_adapter *hns = eth_dev->data->dev_private;
4182 struct hns3_hw *hw = &hns->hw;
4185 PMD_INIT_FUNC_TRACE();
4187 /* Get hardware io base address from pcie BAR2 IO space */
4188 hw->io_base = pci_dev->mem_resource[2].addr;
4190 /* Firmware command queue initialize */
4191 ret = hns3_cmd_init_queue(hw);
4193 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4194 goto err_cmd_init_queue;
4197 hns3_clear_all_event_cause(hw);
4199 /* Firmware command initialize */
4200 ret = hns3_cmd_init(hw);
4202 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4206 ret = rte_intr_callback_register(&pci_dev->intr_handle,
4207 hns3_interrupt_handler,
4210 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4211 goto err_intr_callback_register;
4214 /* Enable interrupt */
4215 rte_intr_enable(&pci_dev->intr_handle);
4216 hns3_pf_enable_irq0(hw);
4218 /* Get configuration */
4219 ret = hns3_get_configuration(hw);
4221 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4222 goto err_get_config;
4225 ret = hns3_init_hardware(hns);
4227 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4228 goto err_get_config;
4231 /* Initialize flow director filter list & hash */
4232 ret = hns3_fdir_filter_init(hns);
4234 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4238 hns3_set_default_rss_args(hw);
4240 ret = hns3_enable_hw_error_intr(hns, true);
4242 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4250 hns3_fdir_filter_uninit(hns);
4252 hns3_uninit_umv_space(hw);
4255 hns3_pf_disable_irq0(hw);
4256 rte_intr_disable(&pci_dev->intr_handle);
4257 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4259 err_intr_callback_register:
4261 hns3_cmd_uninit(hw);
4262 hns3_cmd_destroy_queue(hw);
4270 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4272 struct hns3_adapter *hns = eth_dev->data->dev_private;
4273 struct rte_device *dev = eth_dev->device;
4274 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4275 struct hns3_hw *hw = &hns->hw;
4277 PMD_INIT_FUNC_TRACE();
4279 hns3_enable_hw_error_intr(hns, false);
4280 hns3_rss_uninit(hns);
4281 hns3_fdir_filter_uninit(hns);
4282 hns3_uninit_umv_space(hw);
4283 hns3_pf_disable_irq0(hw);
4284 rte_intr_disable(&pci_dev->intr_handle);
4285 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4287 hns3_cmd_uninit(hw);
4288 hns3_cmd_destroy_queue(hw);
4293 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4295 struct hns3_hw *hw = &hns->hw;
4298 ret = hns3_dcb_cfg_update(hns);
4303 ret = hns3_start_queues(hns, reset_queue);
4305 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4310 ret = hns3_cfg_mac_mode(hw, true);
4312 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4313 goto err_config_mac_mode;
4317 err_config_mac_mode:
4318 hns3_stop_queues(hns, true);
4323 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4325 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4326 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4327 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4328 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4329 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4330 uint32_t intr_vector;
4334 if (dev->data->dev_conf.intr_conf.rxq == 0)
4337 /* disable uio/vfio intr/eventfd mapping */
4338 rte_intr_disable(intr_handle);
4340 /* check and configure queue intr-vector mapping */
4341 if (rte_intr_cap_multiple(intr_handle) ||
4342 !RTE_ETH_DEV_SRIOV(dev).active) {
4343 intr_vector = hw->used_rx_queues;
4344 /* creates event fd for each intr vector when MSIX is used */
4345 if (rte_intr_efd_enable(intr_handle, intr_vector))
4348 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4349 intr_handle->intr_vec =
4350 rte_zmalloc("intr_vec",
4351 hw->used_rx_queues * sizeof(int), 0);
4352 if (intr_handle->intr_vec == NULL) {
4353 hns3_err(hw, "Failed to allocate %d rx_queues"
4354 " intr_vec", hw->used_rx_queues);
4356 goto alloc_intr_vec_error;
4360 if (rte_intr_allow_others(intr_handle)) {
4361 vec = RTE_INTR_VEC_RXTX_OFFSET;
4362 base = RTE_INTR_VEC_RXTX_OFFSET;
4364 if (rte_intr_dp_is_en(intr_handle)) {
4365 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4366 ret = hns3_bind_ring_with_vector(hw, vec, true,
4370 goto bind_vector_error;
4371 intr_handle->intr_vec[q_id] = vec;
4372 if (vec < base + intr_handle->nb_efd - 1)
4376 rte_intr_enable(intr_handle);
4380 rte_intr_efd_disable(intr_handle);
4381 if (intr_handle->intr_vec) {
4382 free(intr_handle->intr_vec);
4383 intr_handle->intr_vec = NULL;
4386 alloc_intr_vec_error:
4387 rte_intr_efd_disable(intr_handle);
4392 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4394 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4395 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4396 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4400 if (dev->data->dev_conf.intr_conf.rxq == 0)
4403 if (rte_intr_dp_is_en(intr_handle)) {
4404 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4405 ret = hns3_bind_ring_with_vector(hw,
4406 intr_handle->intr_vec[q_id], true,
4407 HNS3_RING_TYPE_RX, q_id);
4417 hns3_restore_filter(struct rte_eth_dev *dev)
4419 hns3_restore_rss_filter(dev);
4423 hns3_dev_start(struct rte_eth_dev *dev)
4425 struct hns3_adapter *hns = dev->data->dev_private;
4426 struct hns3_hw *hw = &hns->hw;
4429 PMD_INIT_FUNC_TRACE();
4430 if (rte_atomic16_read(&hw->reset.resetting))
4433 rte_spinlock_lock(&hw->lock);
4434 hw->adapter_state = HNS3_NIC_STARTING;
4436 ret = hns3_do_start(hns, true);
4438 hw->adapter_state = HNS3_NIC_CONFIGURED;
4439 rte_spinlock_unlock(&hw->lock);
4442 ret = hns3_map_rx_interrupt(dev);
4444 hw->adapter_state = HNS3_NIC_CONFIGURED;
4445 rte_spinlock_unlock(&hw->lock);
4449 hw->adapter_state = HNS3_NIC_STARTED;
4450 rte_spinlock_unlock(&hw->lock);
4452 hns3_set_rxtx_function(dev);
4453 hns3_mp_req_start_rxtx(dev);
4454 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4456 hns3_restore_filter(dev);
4458 /* Enable interrupt of all rx queues before enabling queues */
4459 hns3_dev_all_rx_queue_intr_enable(hw, true);
4461 * When finished the initialization, enable queues to receive/transmit
4464 hns3_enable_all_queues(hw, true);
4466 hns3_info(hw, "hns3 dev start successful!");
4471 hns3_do_stop(struct hns3_adapter *hns)
4473 struct hns3_hw *hw = &hns->hw;
4477 ret = hns3_cfg_mac_mode(hw, false);
4480 hw->mac.link_status = ETH_LINK_DOWN;
4482 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4483 hns3_configure_all_mac_addr(hns, true);
4486 reset_queue = false;
4487 hw->mac.default_addr_setted = false;
4488 return hns3_stop_queues(hns, reset_queue);
4492 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4494 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4495 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4496 struct hns3_adapter *hns = dev->data->dev_private;
4497 struct hns3_hw *hw = &hns->hw;
4498 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4499 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4502 if (dev->data->dev_conf.intr_conf.rxq == 0)
4505 /* unmap the ring with vector */
4506 if (rte_intr_allow_others(intr_handle)) {
4507 vec = RTE_INTR_VEC_RXTX_OFFSET;
4508 base = RTE_INTR_VEC_RXTX_OFFSET;
4510 if (rte_intr_dp_is_en(intr_handle)) {
4511 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4512 (void)hns3_bind_ring_with_vector(hw, vec, false,
4515 if (vec < base + intr_handle->nb_efd - 1)
4519 /* Clean datapath event and queue/vec mapping */
4520 rte_intr_efd_disable(intr_handle);
4521 if (intr_handle->intr_vec) {
4522 rte_free(intr_handle->intr_vec);
4523 intr_handle->intr_vec = NULL;
4528 hns3_dev_stop(struct rte_eth_dev *dev)
4530 struct hns3_adapter *hns = dev->data->dev_private;
4531 struct hns3_hw *hw = &hns->hw;
4533 PMD_INIT_FUNC_TRACE();
4535 hw->adapter_state = HNS3_NIC_STOPPING;
4536 hns3_set_rxtx_function(dev);
4538 /* Disable datapath on secondary process. */
4539 hns3_mp_req_stop_rxtx(dev);
4540 /* Prevent crashes when queues are still in use. */
4541 rte_delay_ms(hw->tqps_num);
4543 rte_spinlock_lock(&hw->lock);
4544 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4546 hns3_unmap_rx_interrupt(dev);
4547 hns3_dev_release_mbufs(hns);
4548 hw->adapter_state = HNS3_NIC_CONFIGURED;
4550 rte_eal_alarm_cancel(hns3_service_handler, dev);
4551 rte_spinlock_unlock(&hw->lock);
4555 hns3_dev_close(struct rte_eth_dev *eth_dev)
4557 struct hns3_adapter *hns = eth_dev->data->dev_private;
4558 struct hns3_hw *hw = &hns->hw;
4560 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4561 rte_free(eth_dev->process_private);
4562 eth_dev->process_private = NULL;
4566 if (hw->adapter_state == HNS3_NIC_STARTED)
4567 hns3_dev_stop(eth_dev);
4569 hw->adapter_state = HNS3_NIC_CLOSING;
4570 hns3_reset_abort(hns);
4571 hw->adapter_state = HNS3_NIC_CLOSED;
4573 hns3_configure_all_mc_mac_addr(hns, true);
4574 hns3_remove_all_vlan_table(hns);
4575 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4576 hns3_uninit_pf(eth_dev);
4577 hns3_free_all_queues(eth_dev);
4578 rte_free(hw->reset.wait_data);
4579 rte_free(eth_dev->process_private);
4580 eth_dev->process_private = NULL;
4581 hns3_mp_uninit_primary();
4582 hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4586 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4588 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4589 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4591 fc_conf->pause_time = pf->pause_time;
4593 /* return fc current mode */
4594 switch (hw->current_mode) {
4596 fc_conf->mode = RTE_FC_FULL;
4598 case HNS3_FC_TX_PAUSE:
4599 fc_conf->mode = RTE_FC_TX_PAUSE;
4601 case HNS3_FC_RX_PAUSE:
4602 fc_conf->mode = RTE_FC_RX_PAUSE;
4606 fc_conf->mode = RTE_FC_NONE;
4614 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4618 hw->requested_mode = HNS3_FC_NONE;
4620 case RTE_FC_RX_PAUSE:
4621 hw->requested_mode = HNS3_FC_RX_PAUSE;
4623 case RTE_FC_TX_PAUSE:
4624 hw->requested_mode = HNS3_FC_TX_PAUSE;
4627 hw->requested_mode = HNS3_FC_FULL;
4630 hw->requested_mode = HNS3_FC_NONE;
4631 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4632 "configured to RTE_FC_NONE", mode);
4638 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4640 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4641 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4644 if (fc_conf->high_water || fc_conf->low_water ||
4645 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4646 hns3_err(hw, "Unsupported flow control settings specified, "
4647 "high_water(%u), low_water(%u), send_xon(%u) and "
4648 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4649 fc_conf->high_water, fc_conf->low_water,
4650 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4653 if (fc_conf->autoneg) {
4654 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4657 if (!fc_conf->pause_time) {
4658 hns3_err(hw, "Invalid pause time %d setting.",
4659 fc_conf->pause_time);
4663 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4664 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4665 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4666 "current_fc_status = %d", hw->current_fc_status);
4670 hns3_get_fc_mode(hw, fc_conf->mode);
4671 if (hw->requested_mode == hw->current_mode &&
4672 pf->pause_time == fc_conf->pause_time)
4675 rte_spinlock_lock(&hw->lock);
4676 ret = hns3_fc_enable(dev, fc_conf);
4677 rte_spinlock_unlock(&hw->lock);
4683 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4684 struct rte_eth_pfc_conf *pfc_conf)
4686 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4687 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4691 if (!hns3_dev_dcb_supported(hw)) {
4692 hns3_err(hw, "This port does not support dcb configurations.");
4696 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4697 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4698 hns3_err(hw, "Unsupported flow control settings specified, "
4699 "high_water(%u), low_water(%u), send_xon(%u) and "
4700 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4701 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4702 pfc_conf->fc.send_xon,
4703 pfc_conf->fc.mac_ctrl_frame_fwd);
4706 if (pfc_conf->fc.autoneg) {
4707 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4710 if (pfc_conf->fc.pause_time == 0) {
4711 hns3_err(hw, "Invalid pause time %d setting.",
4712 pfc_conf->fc.pause_time);
4716 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4717 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4718 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4719 "current_fc_status = %d", hw->current_fc_status);
4723 priority = pfc_conf->priority;
4724 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4725 if (hw->dcb_info.pfc_en & BIT(priority) &&
4726 hw->requested_mode == hw->current_mode &&
4727 pfc_conf->fc.pause_time == pf->pause_time)
4730 rte_spinlock_lock(&hw->lock);
4731 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4732 rte_spinlock_unlock(&hw->lock);
4738 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4740 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4741 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4742 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4745 rte_spinlock_lock(&hw->lock);
4746 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4747 dcb_info->nb_tcs = pf->local_max_tc;
4749 dcb_info->nb_tcs = 1;
4751 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4752 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4753 for (i = 0; i < dcb_info->nb_tcs; i++)
4754 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4756 for (i = 0; i < hw->num_tc; i++) {
4757 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4758 dcb_info->tc_queue.tc_txq[0][i].base =
4759 hw->tc_queue[i].tqp_offset;
4760 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4761 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4762 hw->tc_queue[i].tqp_count;
4764 rte_spinlock_unlock(&hw->lock);
4770 hns3_reinit_dev(struct hns3_adapter *hns)
4772 struct hns3_hw *hw = &hns->hw;
4775 ret = hns3_cmd_init(hw);
4777 hns3_err(hw, "Failed to init cmd: %d", ret);
4781 ret = hns3_reset_all_queues(hns);
4783 hns3_err(hw, "Failed to reset all queues: %d", ret);
4787 ret = hns3_init_hardware(hns);
4789 hns3_err(hw, "Failed to init hardware: %d", ret);
4793 ret = hns3_enable_hw_error_intr(hns, true);
4795 hns3_err(hw, "fail to enable hw error interrupts: %d",
4799 hns3_info(hw, "Reset done, driver initialization finished.");
4805 is_pf_reset_done(struct hns3_hw *hw)
4807 uint32_t val, reg, reg_bit;
4809 switch (hw->reset.level) {
4810 case HNS3_IMP_RESET:
4811 reg = HNS3_GLOBAL_RESET_REG;
4812 reg_bit = HNS3_IMP_RESET_BIT;
4814 case HNS3_GLOBAL_RESET:
4815 reg = HNS3_GLOBAL_RESET_REG;
4816 reg_bit = HNS3_GLOBAL_RESET_BIT;
4818 case HNS3_FUNC_RESET:
4819 reg = HNS3_FUN_RST_ING;
4820 reg_bit = HNS3_FUN_RST_ING_B;
4822 case HNS3_FLR_RESET:
4824 hns3_err(hw, "Wait for unsupported reset level: %d",
4828 val = hns3_read_dev(hw, reg);
4829 if (hns3_get_bit(val, reg_bit))
4836 hns3_is_reset_pending(struct hns3_adapter *hns)
4838 struct hns3_hw *hw = &hns->hw;
4839 enum hns3_reset_level reset;
4841 hns3_check_event_cause(hns, NULL);
4842 reset = hns3_get_reset_level(hns, &hw->reset.pending);
4843 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4844 hns3_warn(hw, "High level reset %d is pending", reset);
4847 reset = hns3_get_reset_level(hns, &hw->reset.request);
4848 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4849 hns3_warn(hw, "High level reset %d is request", reset);
4856 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4858 struct hns3_hw *hw = &hns->hw;
4859 struct hns3_wait_data *wait_data = hw->reset.wait_data;
4862 if (wait_data->result == HNS3_WAIT_SUCCESS)
4864 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4865 gettimeofday(&tv, NULL);
4866 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4867 tv.tv_sec, tv.tv_usec);
4869 } else if (wait_data->result == HNS3_WAIT_REQUEST)
4872 wait_data->hns = hns;
4873 wait_data->check_completion = is_pf_reset_done;
4874 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4875 HNS3_RESET_WAIT_MS + get_timeofday_ms();
4876 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4877 wait_data->count = HNS3_RESET_WAIT_CNT;
4878 wait_data->result = HNS3_WAIT_REQUEST;
4879 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4884 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4886 struct hns3_cmd_desc desc;
4887 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4889 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4890 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4891 req->fun_reset_vfid = func_id;
4893 return hns3_cmd_send(hw, &desc, 1);
4897 hns3_imp_reset_cmd(struct hns3_hw *hw)
4899 struct hns3_cmd_desc desc;
4901 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4902 desc.data[0] = 0xeedd;
4904 return hns3_cmd_send(hw, &desc, 1);
4908 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4910 struct hns3_hw *hw = &hns->hw;
4914 gettimeofday(&tv, NULL);
4915 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4916 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4917 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4918 tv.tv_sec, tv.tv_usec);
4922 switch (reset_level) {
4923 case HNS3_IMP_RESET:
4924 hns3_imp_reset_cmd(hw);
4925 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4926 tv.tv_sec, tv.tv_usec);
4928 case HNS3_GLOBAL_RESET:
4929 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4930 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4931 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4932 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4933 tv.tv_sec, tv.tv_usec);
4935 case HNS3_FUNC_RESET:
4936 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4937 tv.tv_sec, tv.tv_usec);
4938 /* schedule again to check later */
4939 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4940 hns3_schedule_reset(hns);
4943 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4946 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4949 static enum hns3_reset_level
4950 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4952 struct hns3_hw *hw = &hns->hw;
4953 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4955 /* Return the highest priority reset level amongst all */
4956 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4957 reset_level = HNS3_IMP_RESET;
4958 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4959 reset_level = HNS3_GLOBAL_RESET;
4960 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4961 reset_level = HNS3_FUNC_RESET;
4962 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4963 reset_level = HNS3_FLR_RESET;
4965 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4966 return HNS3_NONE_RESET;
4972 hns3_prepare_reset(struct hns3_adapter *hns)
4974 struct hns3_hw *hw = &hns->hw;
4978 switch (hw->reset.level) {
4979 case HNS3_FUNC_RESET:
4980 ret = hns3_func_reset_cmd(hw, 0);
4985 * After performaning pf reset, it is not necessary to do the
4986 * mailbox handling or send any command to firmware, because
4987 * any mailbox handling or command to firmware is only valid
4988 * after hns3_cmd_init is called.
4990 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4991 hw->reset.stats.request_cnt++;
4993 case HNS3_IMP_RESET:
4994 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4995 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4996 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5005 hns3_set_rst_done(struct hns3_hw *hw)
5007 struct hns3_pf_rst_done_cmd *req;
5008 struct hns3_cmd_desc desc;
5010 req = (struct hns3_pf_rst_done_cmd *)desc.data;
5011 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5012 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5013 return hns3_cmd_send(hw, &desc, 1);
5017 hns3_stop_service(struct hns3_adapter *hns)
5019 struct hns3_hw *hw = &hns->hw;
5020 struct rte_eth_dev *eth_dev;
5022 eth_dev = &rte_eth_devices[hw->data->port_id];
5023 if (hw->adapter_state == HNS3_NIC_STARTED)
5024 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5025 hw->mac.link_status = ETH_LINK_DOWN;
5027 hns3_set_rxtx_function(eth_dev);
5029 /* Disable datapath on secondary process. */
5030 hns3_mp_req_stop_rxtx(eth_dev);
5031 rte_delay_ms(hw->tqps_num);
5033 rte_spinlock_lock(&hw->lock);
5034 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5035 hw->adapter_state == HNS3_NIC_STOPPING) {
5037 hw->reset.mbuf_deferred_free = true;
5039 hw->reset.mbuf_deferred_free = false;
5042 * It is cumbersome for hardware to pick-and-choose entries for deletion
5043 * from table space. Hence, for function reset software intervention is
5044 * required to delete the entries
5046 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5047 hns3_configure_all_mc_mac_addr(hns, true);
5048 rte_spinlock_unlock(&hw->lock);
5054 hns3_start_service(struct hns3_adapter *hns)
5056 struct hns3_hw *hw = &hns->hw;
5057 struct rte_eth_dev *eth_dev;
5059 if (hw->reset.level == HNS3_IMP_RESET ||
5060 hw->reset.level == HNS3_GLOBAL_RESET)
5061 hns3_set_rst_done(hw);
5062 eth_dev = &rte_eth_devices[hw->data->port_id];
5063 hns3_set_rxtx_function(eth_dev);
5064 hns3_mp_req_start_rxtx(eth_dev);
5065 if (hw->adapter_state == HNS3_NIC_STARTED) {
5066 hns3_service_handler(eth_dev);
5068 /* Enable interrupt of all rx queues before enabling queues */
5069 hns3_dev_all_rx_queue_intr_enable(hw, true);
5071 * When finished the initialization, enable queues to receive
5072 * and transmit packets.
5074 hns3_enable_all_queues(hw, true);
5081 hns3_restore_conf(struct hns3_adapter *hns)
5083 struct hns3_hw *hw = &hns->hw;
5086 ret = hns3_configure_all_mac_addr(hns, false);
5090 ret = hns3_configure_all_mc_mac_addr(hns, false);
5094 ret = hns3_dev_promisc_restore(hns);
5098 ret = hns3_restore_vlan_table(hns);
5102 ret = hns3_restore_vlan_conf(hns);
5106 ret = hns3_restore_all_fdir_filter(hns);
5110 ret = hns3_restore_rx_interrupt(hw);
5114 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5115 ret = hns3_do_start(hns, false);
5118 hns3_info(hw, "hns3 dev restart successful!");
5119 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5120 hw->adapter_state = HNS3_NIC_CONFIGURED;
5124 hns3_configure_all_mc_mac_addr(hns, true);
5126 hns3_configure_all_mac_addr(hns, true);
5131 hns3_reset_service(void *param)
5133 struct hns3_adapter *hns = (struct hns3_adapter *)param;
5134 struct hns3_hw *hw = &hns->hw;
5135 enum hns3_reset_level reset_level;
5136 struct timeval tv_delta;
5137 struct timeval tv_start;
5143 * The interrupt is not triggered within the delay time.
5144 * The interrupt may have been lost. It is necessary to handle
5145 * the interrupt to recover from the error.
5147 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5148 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5149 hns3_err(hw, "Handling interrupts in delayed tasks");
5150 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5151 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5152 if (reset_level == HNS3_NONE_RESET) {
5153 hns3_err(hw, "No reset level is set, try IMP reset");
5154 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5157 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5160 * Check if there is any ongoing reset in the hardware. This status can
5161 * be checked from reset_pending. If there is then, we need to wait for
5162 * hardware to complete reset.
5163 * a. If we are able to figure out in reasonable time that hardware
5164 * has fully resetted then, we can proceed with driver, client
5166 * b. else, we can come back later to check this status so re-sched
5169 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5170 if (reset_level != HNS3_NONE_RESET) {
5171 gettimeofday(&tv_start, NULL);
5172 ret = hns3_reset_process(hns, reset_level);
5173 gettimeofday(&tv, NULL);
5174 timersub(&tv, &tv_start, &tv_delta);
5175 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5176 tv_delta.tv_usec / USEC_PER_MSEC;
5177 if (msec > HNS3_RESET_PROCESS_MS)
5178 hns3_err(hw, "%d handle long time delta %" PRIx64
5179 " ms time=%ld.%.6ld",
5180 hw->reset.level, msec,
5181 tv.tv_sec, tv.tv_usec);
5186 /* Check if we got any *new* reset requests to be honored */
5187 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5188 if (reset_level != HNS3_NONE_RESET)
5189 hns3_msix_process(hns, reset_level);
5192 static const struct eth_dev_ops hns3_eth_dev_ops = {
5193 .dev_start = hns3_dev_start,
5194 .dev_stop = hns3_dev_stop,
5195 .dev_close = hns3_dev_close,
5196 .promiscuous_enable = hns3_dev_promiscuous_enable,
5197 .promiscuous_disable = hns3_dev_promiscuous_disable,
5198 .allmulticast_enable = hns3_dev_allmulticast_enable,
5199 .allmulticast_disable = hns3_dev_allmulticast_disable,
5200 .mtu_set = hns3_dev_mtu_set,
5201 .stats_get = hns3_stats_get,
5202 .stats_reset = hns3_stats_reset,
5203 .xstats_get = hns3_dev_xstats_get,
5204 .xstats_get_names = hns3_dev_xstats_get_names,
5205 .xstats_reset = hns3_dev_xstats_reset,
5206 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
5207 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5208 .dev_infos_get = hns3_dev_infos_get,
5209 .fw_version_get = hns3_fw_version_get,
5210 .rx_queue_setup = hns3_rx_queue_setup,
5211 .tx_queue_setup = hns3_tx_queue_setup,
5212 .rx_queue_release = hns3_dev_rx_queue_release,
5213 .tx_queue_release = hns3_dev_tx_queue_release,
5214 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
5215 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
5216 .dev_configure = hns3_dev_configure,
5217 .flow_ctrl_get = hns3_flow_ctrl_get,
5218 .flow_ctrl_set = hns3_flow_ctrl_set,
5219 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5220 .mac_addr_add = hns3_add_mac_addr,
5221 .mac_addr_remove = hns3_remove_mac_addr,
5222 .mac_addr_set = hns3_set_default_mac_addr,
5223 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
5224 .link_update = hns3_dev_link_update,
5225 .rss_hash_update = hns3_dev_rss_hash_update,
5226 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
5227 .reta_update = hns3_dev_rss_reta_update,
5228 .reta_query = hns3_dev_rss_reta_query,
5229 .filter_ctrl = hns3_dev_filter_ctrl,
5230 .vlan_filter_set = hns3_vlan_filter_set,
5231 .vlan_tpid_set = hns3_vlan_tpid_set,
5232 .vlan_offload_set = hns3_vlan_offload_set,
5233 .vlan_pvid_set = hns3_vlan_pvid_set,
5234 .get_reg = hns3_get_regs,
5235 .get_dcb_info = hns3_get_dcb_info,
5236 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5239 static const struct hns3_reset_ops hns3_reset_ops = {
5240 .reset_service = hns3_reset_service,
5241 .stop_service = hns3_stop_service,
5242 .prepare_reset = hns3_prepare_reset,
5243 .wait_hardware_ready = hns3_wait_hardware_ready,
5244 .reinit_dev = hns3_reinit_dev,
5245 .restore_conf = hns3_restore_conf,
5246 .start_service = hns3_start_service,
5250 hns3_dev_init(struct rte_eth_dev *eth_dev)
5252 struct rte_device *dev = eth_dev->device;
5253 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5254 struct hns3_adapter *hns = eth_dev->data->dev_private;
5255 struct hns3_hw *hw = &hns->hw;
5256 uint16_t device_id = pci_dev->id.device_id;
5259 PMD_INIT_FUNC_TRACE();
5260 eth_dev->process_private = (struct hns3_process_private *)
5261 rte_zmalloc_socket("hns3_filter_list",
5262 sizeof(struct hns3_process_private),
5263 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5264 if (eth_dev->process_private == NULL) {
5265 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5268 /* initialize flow filter lists */
5269 hns3_filterlist_init(eth_dev);
5271 hns3_set_rxtx_function(eth_dev);
5272 eth_dev->dev_ops = &hns3_eth_dev_ops;
5273 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5274 hns3_mp_init_secondary();
5275 hw->secondary_cnt++;
5279 hns3_mp_init_primary();
5280 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5282 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5283 device_id == HNS3_DEV_ID_50GE_RDMA ||
5284 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5285 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5288 hw->data = eth_dev->data;
5291 * Set default max packet size according to the mtu
5292 * default vale in DPDK frame.
5294 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5296 ret = hns3_reset_init(hw);
5298 goto err_init_reset;
5299 hw->reset.ops = &hns3_reset_ops;
5301 ret = hns3_init_pf(eth_dev);
5303 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5307 /* Allocate memory for storing MAC addresses */
5308 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5309 sizeof(struct rte_ether_addr) *
5310 HNS3_UC_MACADDR_NUM, 0);
5311 if (eth_dev->data->mac_addrs == NULL) {
5312 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5313 "to store MAC addresses",
5314 sizeof(struct rte_ether_addr) *
5315 HNS3_UC_MACADDR_NUM);
5317 goto err_rte_zmalloc;
5320 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5321 ð_dev->data->mac_addrs[0]);
5323 hw->adapter_state = HNS3_NIC_INITIALIZED;
5325 * Pass the information to the rte_eth_dev_close() that it should also
5326 * release the private port resources.
5328 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5330 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5331 hns3_err(hw, "Reschedule reset service after dev_init");
5332 hns3_schedule_reset(hns);
5334 /* IMP will wait ready flag before reset */
5335 hns3_notify_reset_ready(hw, false);
5338 hns3_info(hw, "hns3 dev initialization successful!");
5342 hns3_uninit_pf(eth_dev);
5345 rte_free(hw->reset.wait_data);
5347 eth_dev->dev_ops = NULL;
5348 eth_dev->rx_pkt_burst = NULL;
5349 eth_dev->tx_pkt_burst = NULL;
5350 eth_dev->tx_pkt_prepare = NULL;
5351 rte_free(eth_dev->process_private);
5352 eth_dev->process_private = NULL;
5357 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5359 struct hns3_adapter *hns = eth_dev->data->dev_private;
5360 struct hns3_hw *hw = &hns->hw;
5362 PMD_INIT_FUNC_TRACE();
5364 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5367 eth_dev->dev_ops = NULL;
5368 eth_dev->rx_pkt_burst = NULL;
5369 eth_dev->tx_pkt_burst = NULL;
5370 eth_dev->tx_pkt_prepare = NULL;
5371 if (hw->adapter_state < HNS3_NIC_CLOSING)
5372 hns3_dev_close(eth_dev);
5374 hw->adapter_state = HNS3_NIC_REMOVED;
5379 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5380 struct rte_pci_device *pci_dev)
5382 return rte_eth_dev_pci_generic_probe(pci_dev,
5383 sizeof(struct hns3_adapter),
5388 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5390 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5393 static const struct rte_pci_id pci_id_hns3_map[] = {
5394 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5395 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5396 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5397 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5398 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5399 { .vendor_id = 0, /* sentinel */ },
5402 static struct rte_pci_driver rte_hns3_pmd = {
5403 .id_table = pci_id_hns3_map,
5404 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5405 .probe = eth_hns3_pci_probe,
5406 .remove = eth_hns3_pci_remove,
5409 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5410 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5411 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5413 RTE_INIT(hns3_init_log)
5415 hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5416 if (hns3_logtype_init >= 0)
5417 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5418 hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5419 if (hns3_logtype_driver >= 0)
5420 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);