drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static int hns3_add_mc_addr(struct hns3_hw *hw,
  83                             struct rte_ether_addr *mac_addr);
  84 static int hns3_remove_mc_addr(struct hns3_hw *hw,
  85                             struct rte_ether_addr *mac_addr);
  86
  87 static void
  88 hns3_pf_disable_irq0(struct hns3_hw *hw)
  89 {
  90         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  91 }
  92
  93 static void
  94 hns3_pf_enable_irq0(struct hns3_hw *hw)
  95 {
  96         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  97 }
  98
  99 static enum hns3_evt_cause
 100 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 101 {
 102         struct hns3_hw *hw = &hns->hw;
 103         uint32_t vector0_int_stats;
 104         uint32_t cmdq_src_val;
 105         uint32_t val;
 106         enum hns3_evt_cause ret;
 107
 108         /* fetch the events from their corresponding regs */
 109         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 110         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 111
 112         /*
 113          * Assumption: If by any chance reset and mailbox events are reported
 114          * together then we will only process reset event and defer the
 115          * processing of the mailbox events. Since, we would have not cleared
 116          * RX CMDQ event this time we would receive again another interrupt
 117          * from H/W just for the mailbox.
 118          */
 119         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 120                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 121                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 122                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 123                 if (clearval) {
 124                         hw->reset.stats.imp_cnt++;
 125                         hns3_warn(hw, "IMP reset detected, clear reset status");
 126                 } else {
 127                         hns3_schedule_delayed_reset(hns);
 128                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 129                 }
 130
 131                 ret = HNS3_VECTOR0_EVENT_RST;
 132                 goto out;
 133         }
 134
 135         /* Global reset */
 136         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 137                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 138                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 139                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 140                 if (clearval) {
 141                         hw->reset.stats.global_cnt++;
 142                         hns3_warn(hw, "Global reset detected, clear reset status");
 143                 } else {
 144                         hns3_schedule_delayed_reset(hns);
 145                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 146                 }
 147
 148                 ret = HNS3_VECTOR0_EVENT_RST;
 149                 goto out;
 150         }
 151
 152         /* check for vector0 msix event source */
 153         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 154                 val = vector0_int_stats;
 155                 ret = HNS3_VECTOR0_EVENT_ERR;
 156                 goto out;
 157         }
 158
 159         /* check for vector0 mailbox(=CMDQ RX) event source */
 160         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 161                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 162                 val = cmdq_src_val;
 163                 ret = HNS3_VECTOR0_EVENT_MBX;
 164                 goto out;
 165         }
 166
 167         if (clearval && (vector0_int_stats || cmdq_src_val))
 168                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 169                           vector0_int_stats, cmdq_src_val);
 170         val = vector0_int_stats;
 171         ret = HNS3_VECTOR0_EVENT_OTHER;
 172 out:
 173
 174         if (clearval)
 175                 *clearval = val;
 176         return ret;
 177 }
 178
 179 static void
 180 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 181 {
 182         if (event_type == HNS3_VECTOR0_EVENT_RST)
 183                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 184         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 185                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 186 }
 187
 188 static void
 189 hns3_clear_all_event_cause(struct hns3_hw *hw)
 190 {
 191         uint32_t vector0_int_stats;
 192         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 193
 194         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 195                 hns3_warn(hw, "Probe during IMP reset interrupt");
 196
 197         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 198                 hns3_warn(hw, "Probe during Global reset interrupt");
 199
 200         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 201                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 202                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 203                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 204         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 205 }
 206
 207 static void
 208 hns3_interrupt_handler(void *param)
 209 {
 210         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 211         struct hns3_adapter *hns = dev->data->dev_private;
 212         struct hns3_hw *hw = &hns->hw;
 213         enum hns3_evt_cause event_cause;
 214         uint32_t clearval = 0;
 215
 216         /* Disable interrupt */
 217         hns3_pf_disable_irq0(hw);
 218
 219         event_cause = hns3_check_event_cause(hns, &clearval);
 220
 221         /* vector 0 interrupt is shared with reset and mailbox source events. */
 222         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 223                 hns3_handle_msix_error(hns, &hw->reset.request);
 224                 hns3_schedule_reset(hns);
 225         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 226                 hns3_schedule_reset(hns);
 227         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 228                 hns3_dev_handle_mbx_msg(hw);
 229         else
 230                 hns3_err(hw, "Received unknown event");
 231
 232         hns3_clear_event_cause(hw, event_cause, clearval);
 233         /* Enable interrupt if it is not cause by reset */
 234         hns3_pf_enable_irq0(hw);
 235 }
 236
 237 static int
 238 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 239 {
 240 #define HNS3_VLAN_ID_OFFSET_STEP        160
 241 #define HNS3_VLAN_BYTE_SIZE             8
 242         struct hns3_vlan_filter_pf_cfg_cmd *req;
 243         struct hns3_hw *hw = &hns->hw;
 244         uint8_t vlan_offset_byte_val;
 245         struct hns3_cmd_desc desc;
 246         uint8_t vlan_offset_byte;
 247         uint8_t vlan_offset_base;
 248         int ret;
 249
 250         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 251
 252         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 253         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 254                            HNS3_VLAN_BYTE_SIZE;
 255         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 256
 257         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 258         req->vlan_offset = vlan_offset_base;
 259         req->vlan_cfg = on ? 0 : 1;
 260         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 261
 262         ret = hns3_cmd_send(hw, &desc, 1);
 263         if (ret)
 264                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 265                          vlan_id, ret);
 266
 267         return ret;
 268 }
 269
 270 static void
 271 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 272 {
 273         struct hns3_user_vlan_table *vlan_entry;
 274         struct hns3_pf *pf = &hns->pf;
 275
 276         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 277                 if (vlan_entry->vlan_id == vlan_id) {
 278                         if (vlan_entry->hd_tbl_status)
 279                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 280                         LIST_REMOVE(vlan_entry, next);
 281                         rte_free(vlan_entry);
 282                         break;
 283                 }
 284         }
 285 }
 286
 287 static void
 288 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 289                         bool writen_to_tbl)
 290 {
 291         struct hns3_user_vlan_table *vlan_entry;
 292         struct hns3_hw *hw = &hns->hw;
 293         struct hns3_pf *pf = &hns->pf;
 294
 295         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 296                 if (vlan_entry->vlan_id == vlan_id)
 297                         return;
 298         }
 299
 300         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 301         if (vlan_entry == NULL) {
 302                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 303                 return;
 304         }
 305
 306         vlan_entry->hd_tbl_status = writen_to_tbl;
 307         vlan_entry->vlan_id = vlan_id;
 308
 309         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 310 }
 311
 312 static int
 313 hns3_restore_vlan_table(struct hns3_adapter *hns)
 314 {
 315         struct hns3_user_vlan_table *vlan_entry;
 316         struct hns3_pf *pf = &hns->pf;
 317         uint16_t vlan_id;
 318         int ret = 0;
 319
 320         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 321                 return hns3_vlan_pvid_configure(hns,
 322                                                 pf->port_base_vlan_cfg.pvid, 1);
 323
 324         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 325                 if (vlan_entry->hd_tbl_status) {
 326                         vlan_id = vlan_entry->vlan_id;
 327                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 328                         if (ret)
 329                                 break;
 330                 }
 331         }
 332
 333         return ret;
 334 }
 335
 336 static int
 337 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 338 {
 339         struct hns3_pf *pf = &hns->pf;
 340         bool writen_to_tbl = false;
 341         int ret = 0;
 342
 343         /*
 344          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 345          * for normal packet, deleting vlan id 0 is not allowed.
 346          */
 347         if (on == 0 && vlan_id == 0)
 348                 return 0;
 349
 350         /*
 351          * When port base vlan enabled, we use port base vlan as the vlan
 352          * filter condition. In this case, we don't update vlan filter table
 353          * when user add new vlan or remove exist vlan, just update the
 354          * vlan list. The vlan id in vlan list will be writen in vlan filter
 355          * table until port base vlan disabled
 356          */
 357         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 358                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 359                 writen_to_tbl = true;
 360         }
 361
 362         if (ret == 0 && vlan_id) {
 363                 if (on)
 364                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 365                 else
 366                         hns3_rm_dev_vlan_table(hns, vlan_id);
 367         }
 368         return ret;
 369 }
 370
 371 static int
 372 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 373 {
 374         struct hns3_adapter *hns = dev->data->dev_private;
 375         struct hns3_hw *hw = &hns->hw;
 376         int ret;
 377
 378         rte_spinlock_lock(&hw->lock);
 379         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 380         rte_spinlock_unlock(&hw->lock);
 381         return ret;
 382 }
 383
 384 static int
 385 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 386                          uint16_t tpid)
 387 {
 388         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 389         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 390         struct hns3_hw *hw = &hns->hw;
 391         struct hns3_cmd_desc desc;
 392         int ret;
 393
 394         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 395              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 396                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 397                 return -EINVAL;
 398         }
 399
 400         if (tpid != RTE_ETHER_TYPE_VLAN) {
 401                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 402                 return -EINVAL;
 403         }
 404
 405         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 406         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 407
 408         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 409                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 412                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 413                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 414                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 415                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 416         }
 417
 418         ret = hns3_cmd_send(hw, &desc, 1);
 419         if (ret) {
 420                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 421                          ret);
 422                 return ret;
 423         }
 424
 425         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 426
 427         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 428         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 429         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 430
 431         ret = hns3_cmd_send(hw, &desc, 1);
 432         if (ret)
 433                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 434                          ret);
 435         return ret;
 436 }
 437
 438 static int
 439 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 440                    uint16_t tpid)
 441 {
 442         struct hns3_adapter *hns = dev->data->dev_private;
 443         struct hns3_hw *hw = &hns->hw;
 444         int ret;
 445
 446         rte_spinlock_lock(&hw->lock);
 447         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 448         rte_spinlock_unlock(&hw->lock);
 449         return ret;
 450 }
 451
 452 static int
 453 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 454                              struct hns3_rx_vtag_cfg *vcfg)
 455 {
 456         struct hns3_vport_vtag_rx_cfg_cmd *req;
 457         struct hns3_hw *hw = &hns->hw;
 458         struct hns3_cmd_desc desc;
 459         uint16_t vport_id;
 460         uint8_t bitmap;
 461         int ret;
 462
 463         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 464
 465         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 466         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 467                      vcfg->strip_tag1_en ? 1 : 0);
 468         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 469                      vcfg->strip_tag2_en ? 1 : 0);
 470         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 471                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 472         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 473                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 474
 475         /*
 476          * In current version VF is not supported when PF is driven by DPDK
 477          * driver, the PF-related vf_id is 0, just need to configure parameters
 478          * for vport_id 0.
 479          */
 480         vport_id = 0;
 481         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 482         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 483         req->vf_bitmap[req->vf_offset] = bitmap;
 484
 485         ret = hns3_cmd_send(hw, &desc, 1);
 486         if (ret)
 487                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 488         return ret;
 489 }
 490
 491 static void
 492 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 493                            struct hns3_rx_vtag_cfg *vcfg)
 494 {
 495         struct hns3_pf *pf = &hns->pf;
 496         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 497 }
 498
 499 static void
 500 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 501                            struct hns3_tx_vtag_cfg *vcfg)
 502 {
 503         struct hns3_pf *pf = &hns->pf;
 504         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 505 }
 506
 507 static int
 508 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 509 {
 510         struct hns3_rx_vtag_cfg rxvlan_cfg;
 511         struct hns3_pf *pf = &hns->pf;
 512         struct hns3_hw *hw = &hns->hw;
 513         int ret;
 514
 515         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 516                 rxvlan_cfg.strip_tag1_en = false;
 517                 rxvlan_cfg.strip_tag2_en = enable;
 518         } else {
 519                 rxvlan_cfg.strip_tag1_en = enable;
 520                 rxvlan_cfg.strip_tag2_en = true;
 521         }
 522
 523         rxvlan_cfg.vlan1_vlan_prionly = false;
 524         rxvlan_cfg.vlan2_vlan_prionly = false;
 525         rxvlan_cfg.rx_vlan_offload_en = enable;
 526
 527         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 528         if (ret) {
 529                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 530                 return ret;
 531         }
 532
 533         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 534
 535         return ret;
 536 }
 537
 538 static int
 539 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 540                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 541 {
 542         struct hns3_vlan_filter_ctrl_cmd *req;
 543         struct hns3_cmd_desc desc;
 544         int ret;
 545
 546         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 547
 548         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 549         req->vlan_type = vlan_type;
 550         req->vlan_fe = filter_en ? fe_type : 0;
 551         req->vf_id = vf_id;
 552
 553         ret = hns3_cmd_send(hw, &desc, 1);
 554         if (ret)
 555                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 556
 557         return ret;
 558 }
 559
 560 static int
 561 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 562 {
 563         struct hns3_hw *hw = &hns->hw;
 564         int ret;
 565
 566         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 567                                         HNS3_FILTER_FE_EGRESS, false, 0);
 568         if (ret) {
 569                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 570                 return ret;
 571         }
 572
 573         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 574                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 575         if (ret)
 576                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 577
 578         return ret;
 579 }
 580
 581 static int
 582 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 583 {
 584         struct hns3_adapter *hns = dev->data->dev_private;
 585         struct hns3_hw *hw = &hns->hw;
 586         struct rte_eth_rxmode *rxmode;
 587         unsigned int tmp_mask;
 588         bool enable;
 589         int ret = 0;
 590
 591         rte_spinlock_lock(&hw->lock);
 592         rxmode = &dev->data->dev_conf.rxmode;
 593         tmp_mask = (unsigned int)mask;
 594         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 595                 /* Enable or disable VLAN stripping */
 596                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 597                     true : false;
 598
 599                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 600                 if (ret) {
 601                         rte_spinlock_unlock(&hw->lock);
 602                         hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
 603                         return ret;
 604                 }
 605         }
 606
 607         rte_spinlock_unlock(&hw->lock);
 608
 609         return ret;
 610 }
 611
 612 static int
 613 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 614                              struct hns3_tx_vtag_cfg *vcfg)
 615 {
 616         struct hns3_vport_vtag_tx_cfg_cmd *req;
 617         struct hns3_cmd_desc desc;
 618         struct hns3_hw *hw = &hns->hw;
 619         uint16_t vport_id;
 620         uint8_t bitmap;
 621         int ret;
 622
 623         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 624
 625         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 626         req->def_vlan_tag1 = vcfg->default_tag1;
 627         req->def_vlan_tag2 = vcfg->default_tag2;
 628         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 629                      vcfg->accept_tag1 ? 1 : 0);
 630         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 631                      vcfg->accept_untag1 ? 1 : 0);
 632         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 633                      vcfg->accept_tag2 ? 1 : 0);
 634         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 635                      vcfg->accept_untag2 ? 1 : 0);
 636         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 637                      vcfg->insert_tag1_en ? 1 : 0);
 638         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 639                      vcfg->insert_tag2_en ? 1 : 0);
 640         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 641
 642         /*
 643          * In current version VF is not supported when PF is driven by DPDK
 644          * driver, the PF-related vf_id is 0, just need to configure parameters
 645          * for vport_id 0.
 646          */
 647         vport_id = 0;
 648         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 649         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 650         req->vf_bitmap[req->vf_offset] = bitmap;
 651
 652         ret = hns3_cmd_send(hw, &desc, 1);
 653         if (ret)
 654                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 655
 656         return ret;
 657 }
 658
 659 static int
 660 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 661                      uint16_t pvid)
 662 {
 663         struct hns3_hw *hw = &hns->hw;
 664         struct hns3_tx_vtag_cfg txvlan_cfg;
 665         int ret;
 666
 667         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 668                 txvlan_cfg.accept_tag1 = true;
 669                 txvlan_cfg.insert_tag1_en = false;
 670                 txvlan_cfg.default_tag1 = 0;
 671         } else {
 672                 txvlan_cfg.accept_tag1 = false;
 673                 txvlan_cfg.insert_tag1_en = true;
 674                 txvlan_cfg.default_tag1 = pvid;
 675         }
 676
 677         txvlan_cfg.accept_untag1 = true;
 678         txvlan_cfg.accept_tag2 = true;
 679         txvlan_cfg.accept_untag2 = true;
 680         txvlan_cfg.insert_tag2_en = false;
 681         txvlan_cfg.default_tag2 = 0;
 682
 683         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 684         if (ret) {
 685                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 686                          ret);
 687                 return ret;
 688         }
 689
 690         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 691         return ret;
 692 }
 693
 694 static void
 695 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 696 {
 697         struct hns3_pf *pf = &hns->pf;
 698
 699         pf->port_base_vlan_cfg.state = on ?
 700             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 701
 702         pf->port_base_vlan_cfg.pvid = pvid;
 703 }
 704
 705 static void
 706 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 707 {
 708         struct hns3_user_vlan_table *vlan_entry;
 709         struct hns3_pf *pf = &hns->pf;
 710
 711         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 712                 if (vlan_entry->hd_tbl_status)
 713                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 714
 715                 vlan_entry->hd_tbl_status = false;
 716         }
 717
 718         if (is_del_list) {
 719                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 720                 while (vlan_entry) {
 721                         LIST_REMOVE(vlan_entry, next);
 722                         rte_free(vlan_entry);
 723                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 724                 }
 725         }
 726 }
 727
 728 static void
 729 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 730 {
 731         struct hns3_user_vlan_table *vlan_entry;
 732         struct hns3_pf *pf = &hns->pf;
 733
 734         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 735                 if (!vlan_entry->hd_tbl_status)
 736                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 737
 738                 vlan_entry->hd_tbl_status = true;
 739         }
 740 }
 741
 742 static void
 743 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 744 {
 745         struct hns3_hw *hw = &hns->hw;
 746         struct hns3_pf *pf = &hns->pf;
 747         int ret;
 748
 749         hns3_rm_all_vlan_table(hns, true);
 750         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 751                 ret = hns3_set_port_vlan_filter(hns,
 752                                                 pf->port_base_vlan_cfg.pvid, 0);
 753                 if (ret) {
 754                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 755                                  ret);
 756                         return;
 757                 }
 758         }
 759 }
 760
 761 static int
 762 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 763                                 uint16_t port_base_vlan_state,
 764                                 uint16_t new_pvid, uint16_t old_pvid)
 765 {
 766         struct hns3_pf *pf = &hns->pf;
 767         struct hns3_hw *hw = &hns->hw;
 768         int ret = 0;
 769
 770         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 771                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 772                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 773                         if (ret) {
 774                                 hns3_err(hw,
 775                                          "Failed to clear clear old pvid filter, ret =%d",
 776                                          ret);
 777                                 return ret;
 778                         }
 779                 }
 780
 781                 hns3_rm_all_vlan_table(hns, false);
 782                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 783         }
 784
 785         if (new_pvid != 0) {
 786                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 787                 if (ret) {
 788                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 789                                  ret);
 790                         return ret;
 791                 }
 792         }
 793
 794         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 795                 hns3_add_all_vlan_table(hns);
 796
 797         return ret;
 798 }
 799
 800 static int
 801 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 802 {
 803         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 804         struct hns3_hw *hw = &hns->hw;
 805         bool rx_strip_en;
 806         int ret;
 807
 808         rx_strip_en = on ? true : false;
 809         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 810         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 811         rx_vlan_cfg.vlan1_vlan_prionly = false;
 812         rx_vlan_cfg.vlan2_vlan_prionly = false;
 813         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 814
 815         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 816         if (ret) {
 817                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 818                 return ret;
 819         }
 820
 821         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 822         return ret;
 823 }
 824
 825 static int
 826 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 827 {
 828         struct hns3_pf *pf = &hns->pf;
 829         struct hns3_hw *hw = &hns->hw;
 830         uint16_t port_base_vlan_state;
 831         uint16_t old_pvid;
 832         int ret;
 833
 834         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 835                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 836                         hns3_warn(hw, "Invalid operation! As current pvid set "
 837                                   "is %u, disable pvid %u is invalid",
 838                                   pf->port_base_vlan_cfg.pvid, pvid);
 839                 return 0;
 840         }
 841
 842         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 843                                     HNS3_PORT_BASE_VLAN_DISABLE;
 844         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 845         if (ret) {
 846                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 847                 return ret;
 848         }
 849
 850         ret = hns3_en_rx_strip_all(hns, on);
 851         if (ret) {
 852                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 853                 return ret;
 854         }
 855
 856         if (pvid == HNS3_INVLID_PVID)
 857                 goto out;
 858         old_pvid = pf->port_base_vlan_cfg.pvid;
 859         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 860                                               old_pvid);
 861         if (ret) {
 862                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 863                          ret);
 864                 return ret;
 865         }
 866
 867 out:
 868         hns3_store_port_base_vlan_info(hns, pvid, on);
 869         return ret;
 870 }
 871
 872 static int
 873 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 874 {
 875         struct hns3_adapter *hns = dev->data->dev_private;
 876         struct hns3_hw *hw = &hns->hw;
 877         int ret;
 878
 879         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 880                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 881                          RTE_ETHER_MAX_VLAN_ID);
 882                 return -EINVAL;
 883         }
 884
 885         rte_spinlock_lock(&hw->lock);
 886         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 887         rte_spinlock_unlock(&hw->lock);
 888         return ret;
 889 }
 890
 891 static void
 892 init_port_base_vlan_info(struct hns3_hw *hw)
 893 {
 894         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 895         struct hns3_pf *pf = &hns->pf;
 896
 897         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 898         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 899 }
 900
 901 static int
 902 hns3_default_vlan_config(struct hns3_adapter *hns)
 903 {
 904         struct hns3_hw *hw = &hns->hw;
 905         int ret;
 906
 907         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 908         if (ret)
 909                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 910         return ret;
 911 }
 912
 913 static int
 914 hns3_init_vlan_config(struct hns3_adapter *hns)
 915 {
 916         struct hns3_hw *hw = &hns->hw;
 917         int ret;
 918
 919         /*
 920          * This function can be called in the initialization and reset process,
 921          * when in reset process, it means that hardware had been reseted
 922          * successfully and we need to restore the hardware configuration to
 923          * ensure that the hardware configuration remains unchanged before and
 924          * after reset.
 925          */
 926         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 927                 init_port_base_vlan_info(hw);
 928
 929         ret = hns3_enable_vlan_filter(hns, true);
 930         if (ret) {
 931                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 932                 return ret;
 933         }
 934
 935         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 936                                        RTE_ETHER_TYPE_VLAN);
 937         if (ret) {
 938                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 939                 return ret;
 940         }
 941
 942         /*
 943          * When in the reinit dev stage of the reset process, the following
 944          * vlan-related configurations may differ from those at initialization,
 945          * we will restore configurations to hardware in hns3_restore_vlan_table
 946          * and hns3_restore_vlan_conf later.
 947          */
 948         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 949                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 950                 if (ret) {
 951                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 952                         return ret;
 953                 }
 954
 955                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 956                 if (ret) {
 957                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 958                                  ret);
 959                         return ret;
 960                 }
 961         }
 962
 963         return hns3_default_vlan_config(hns);
 964 }
 965
 966 static int
 967 hns3_restore_vlan_conf(struct hns3_adapter *hns)
 968 {
 969         struct hns3_pf *pf = &hns->pf;
 970         struct hns3_hw *hw = &hns->hw;
 971         int ret;
 972
 973         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
 974         if (ret) {
 975                 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
 976                 return ret;
 977         }
 978
 979         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
 980         if (ret)
 981                 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
 982
 983         return ret;
 984 }
 985
 986 static int
 987 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
 988 {
 989         struct hns3_adapter *hns = dev->data->dev_private;
 990         struct rte_eth_dev_data *data = dev->data;
 991         struct rte_eth_txmode *txmode;
 992         struct hns3_hw *hw = &hns->hw;
 993         int ret;
 994
 995         txmode = &data->dev_conf.txmode;
 996         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
 997                 hns3_warn(hw,
 998                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
 999                           "configuration is not supported! Ignore these two "
1000                           "parameters: hw_vlan_reject_tagged(%d), "
1001                           "hw_vlan_reject_untagged(%d)",
1002                           txmode->hw_vlan_reject_tagged,
1003                           txmode->hw_vlan_reject_untagged);
1004
1005         /* Apply vlan offload setting */
1006         ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1007         if (ret) {
1008                 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
1009                 return ret;
1010         }
1011
1012         /* Apply pvid setting */
1013         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1014                                  txmode->hw_vlan_insert_pvid);
1015         if (ret)
1016                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
1017                          txmode->pvid, ret);
1018
1019         return ret;
1020 }
1021
1022 static int
1023 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1024                 unsigned int tso_mss_max)
1025 {
1026         struct hns3_cfg_tso_status_cmd *req;
1027         struct hns3_cmd_desc desc;
1028         uint16_t tso_mss;
1029
1030         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1031
1032         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1033
1034         tso_mss = 0;
1035         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1036                        tso_mss_min);
1037         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1038
1039         tso_mss = 0;
1040         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1041                        tso_mss_max);
1042         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1043
1044         return hns3_cmd_send(hw, &desc, 1);
1045 }
1046
1047 int
1048 hns3_config_gro(struct hns3_hw *hw, bool en)
1049 {
1050         struct hns3_cfg_gro_status_cmd *req;
1051         struct hns3_cmd_desc desc;
1052         int ret;
1053
1054         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1055         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1056
1057         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1058
1059         ret = hns3_cmd_send(hw, &desc, 1);
1060         if (ret)
1061                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1062
1063         return ret;
1064 }
1065
1066 static int
1067 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1068                    uint16_t *allocated_size, bool is_alloc)
1069 {
1070         struct hns3_umv_spc_alc_cmd *req;
1071         struct hns3_cmd_desc desc;
1072         int ret;
1073
1074         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1075         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1076         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1077         req->space_size = rte_cpu_to_le_32(space_size);
1078
1079         ret = hns3_cmd_send(hw, &desc, 1);
1080         if (ret) {
1081                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1082                              is_alloc ? "allocate" : "free", ret);
1083                 return ret;
1084         }
1085
1086         if (is_alloc && allocated_size)
1087                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1088
1089         return 0;
1090 }
1091
1092 static int
1093 hns3_init_umv_space(struct hns3_hw *hw)
1094 {
1095         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1096         struct hns3_pf *pf = &hns->pf;
1097         uint16_t allocated_size = 0;
1098         int ret;
1099
1100         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1101                                  true);
1102         if (ret)
1103                 return ret;
1104
1105         if (allocated_size < pf->wanted_umv_size)
1106                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1107                              pf->wanted_umv_size, allocated_size);
1108
1109         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1110                                                 pf->wanted_umv_size;
1111         pf->used_umv_size = 0;
1112         return 0;
1113 }
1114
1115 static int
1116 hns3_uninit_umv_space(struct hns3_hw *hw)
1117 {
1118         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1119         struct hns3_pf *pf = &hns->pf;
1120         int ret;
1121
1122         if (pf->max_umv_size == 0)
1123                 return 0;
1124
1125         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1126         if (ret)
1127                 return ret;
1128
1129         pf->max_umv_size = 0;
1130
1131         return 0;
1132 }
1133
1134 static bool
1135 hns3_is_umv_space_full(struct hns3_hw *hw)
1136 {
1137         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1138         struct hns3_pf *pf = &hns->pf;
1139         bool is_full;
1140
1141         is_full = (pf->used_umv_size >= pf->max_umv_size);
1142
1143         return is_full;
1144 }
1145
1146 static void
1147 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1148 {
1149         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1150         struct hns3_pf *pf = &hns->pf;
1151
1152         if (is_free) {
1153                 if (pf->used_umv_size > 0)
1154                         pf->used_umv_size--;
1155         } else
1156                 pf->used_umv_size++;
1157 }
1158
1159 static void
1160 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1161                       const uint8_t *addr, bool is_mc)
1162 {
1163         const unsigned char *mac_addr = addr;
1164         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1165                             ((uint32_t)mac_addr[2] << 16) |
1166                             ((uint32_t)mac_addr[1] << 8) |
1167                             (uint32_t)mac_addr[0];
1168         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1169
1170         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1171         if (is_mc) {
1172                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1173                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1174                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1175         }
1176
1177         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1178         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1179 }
1180
1181 static int
1182 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1183                              uint8_t resp_code,
1184                              enum hns3_mac_vlan_tbl_opcode op)
1185 {
1186         if (cmdq_resp) {
1187                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1188                          cmdq_resp);
1189                 return -EIO;
1190         }
1191
1192         if (op == HNS3_MAC_VLAN_ADD) {
1193                 if (resp_code == 0 || resp_code == 1) {
1194                         return 0;
1195                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1196                         hns3_err(hw, "add mac addr failed for uc_overflow");
1197                         return -ENOSPC;
1198                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1199                         hns3_err(hw, "add mac addr failed for mc_overflow");
1200                         return -ENOSPC;
1201                 }
1202
1203                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1204                          resp_code);
1205                 return -EIO;
1206         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1207                 if (resp_code == 0) {
1208                         return 0;
1209                 } else if (resp_code == 1) {
1210                         hns3_dbg(hw, "remove mac addr failed for miss");
1211                         return -ENOENT;
1212                 }
1213
1214                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1215                          resp_code);
1216                 return -EIO;
1217         } else if (op == HNS3_MAC_VLAN_LKUP) {
1218                 if (resp_code == 0) {
1219                         return 0;
1220                 } else if (resp_code == 1) {
1221                         hns3_dbg(hw, "lookup mac addr failed for miss");
1222                         return -ENOENT;
1223                 }
1224
1225                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1226                          resp_code);
1227                 return -EIO;
1228         }
1229
1230         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1231                  op);
1232
1233         return -EINVAL;
1234 }
1235
1236 static int
1237 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1238                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1239                          struct hns3_cmd_desc *desc, bool is_mc)
1240 {
1241         uint8_t resp_code;
1242         uint16_t retval;
1243         int ret;
1244
1245         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1246         if (is_mc) {
1247                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1248                 memcpy(desc[0].data, req,
1249                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1250                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1251                                           true);
1252                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1253                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1254                                           true);
1255                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1256         } else {
1257                 memcpy(desc[0].data, req,
1258                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1259                 ret = hns3_cmd_send(hw, desc, 1);
1260         }
1261         if (ret) {
1262                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1263                          ret);
1264                 return ret;
1265         }
1266         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1267         retval = rte_le_to_cpu_16(desc[0].retval);
1268
1269         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1270                                             HNS3_MAC_VLAN_LKUP);
1271 }
1272
1273 static int
1274 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1275                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1276                       struct hns3_cmd_desc *mc_desc)
1277 {
1278         uint8_t resp_code;
1279         uint16_t retval;
1280         int cfg_status;
1281         int ret;
1282
1283         if (mc_desc == NULL) {
1284                 struct hns3_cmd_desc desc;
1285
1286                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1287                 memcpy(desc.data, req,
1288                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1289                 ret = hns3_cmd_send(hw, &desc, 1);
1290                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1291                 retval = rte_le_to_cpu_16(desc.retval);
1292
1293                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1294                                                           HNS3_MAC_VLAN_ADD);
1295         } else {
1296                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1297                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1298                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1299                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1300                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1301                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1302                 memcpy(mc_desc[0].data, req,
1303                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1304                 mc_desc[0].retval = 0;
1305                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1306                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1307                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1308
1309                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1310                                                           HNS3_MAC_VLAN_ADD);
1311         }
1312
1313         if (ret) {
1314                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1315                 return ret;
1316         }
1317
1318         return cfg_status;
1319 }
1320
1321 static int
1322 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1323                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1324 {
1325         struct hns3_cmd_desc desc;
1326         uint8_t resp_code;
1327         uint16_t retval;
1328         int ret;
1329
1330         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1331
1332         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1333
1334         ret = hns3_cmd_send(hw, &desc, 1);
1335         if (ret) {
1336                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1337                 return ret;
1338         }
1339         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1340         retval = rte_le_to_cpu_16(desc.retval);
1341
1342         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1343                                             HNS3_MAC_VLAN_REMOVE);
1344 }
1345
1346 static int
1347 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1348 {
1349         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1350         struct hns3_mac_vlan_tbl_entry_cmd req;
1351         struct hns3_pf *pf = &hns->pf;
1352         struct hns3_cmd_desc desc;
1353         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1354         uint16_t egress_port = 0;
1355         uint8_t vf_id;
1356         int ret;
1357
1358         /* check if mac addr is valid */
1359         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1360                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1361                                       mac_addr);
1362                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1363                          mac_str);
1364                 return -EINVAL;
1365         }
1366
1367         memset(&req, 0, sizeof(req));
1368
1369         /*
1370          * In current version VF is not supported when PF is driven by DPDK
1371          * driver, the PF-related vf_id is 0, just need to configure parameters
1372          * for vf_id 0.
1373          */
1374         vf_id = 0;
1375         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1376                        HNS3_MAC_EPORT_VFID_S, vf_id);
1377
1378         req.egress_port = rte_cpu_to_le_16(egress_port);
1379
1380         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1381
1382         /*
1383          * Lookup the mac address in the mac_vlan table, and add
1384          * it if the entry is inexistent. Repeated unicast entry
1385          * is not allowed in the mac vlan table.
1386          */
1387         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1388         if (ret == -ENOENT) {
1389                 if (!hns3_is_umv_space_full(hw)) {
1390                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1391                         if (!ret)
1392                                 hns3_update_umv_space(hw, false);
1393                         return ret;
1394                 }
1395
1396                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1397
1398                 return -ENOSPC;
1399         }
1400
1401         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1402
1403         /* check if we just hit the duplicate */
1404         if (ret == 0) {
1405                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1406                 return 0;
1407         }
1408
1409         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1410                  mac_str);
1411
1412         return ret;
1413 }
1414
1415 static int
1416 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1417 {
1418         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1419         struct rte_ether_addr *addr;
1420         int ret;
1421         int i;
1422
1423         for (i = 0; i < hw->mc_addrs_num; i++) {
1424                 addr = &hw->mc_addrs[i];
1425                 /* Check if there are duplicate addresses */
1426                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1427                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1428                                               addr);
1429                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1430                                  "(%s) is added by the set_mc_mac_addr_list "
1431                                  "API", mac_str);
1432                         return -EINVAL;
1433                 }
1434         }
1435
1436         ret = hns3_add_mc_addr(hw, mac_addr);
1437         if (ret) {
1438                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1439                                       mac_addr);
1440                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1441                          mac_str, ret);
1442         }
1443         return ret;
1444 }
1445
1446 static int
1447 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1448 {
1449         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1450         int ret;
1451
1452         ret = hns3_remove_mc_addr(hw, mac_addr);
1453         if (ret) {
1454                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1455                                       mac_addr);
1456                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1457                          mac_str, ret);
1458         }
1459         return ret;
1460 }
1461
1462 static int
1463 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1464                   uint32_t idx, __rte_unused uint32_t pool)
1465 {
1466         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1467         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1468         int ret;
1469
1470         rte_spinlock_lock(&hw->lock);
1471
1472         /*
1473          * In hns3 network engine adding UC and MC mac address with different
1474          * commands with firmware. We need to determine whether the input
1475          * address is a UC or a MC address to call different commands.
1476          * By the way, it is recommended calling the API function named
1477          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1478          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1479          * may affect the specifications of UC mac addresses.
1480          */
1481         if (rte_is_multicast_ether_addr(mac_addr))
1482                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1483         else
1484                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1485
1486         if (ret) {
1487                 rte_spinlock_unlock(&hw->lock);
1488                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1489                                       mac_addr);
1490                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1491                          ret);
1492                 return ret;
1493         }
1494
1495         if (idx == 0)
1496                 hw->mac.default_addr_setted = true;
1497         rte_spinlock_unlock(&hw->lock);
1498
1499         return ret;
1500 }
1501
1502 static int
1503 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1504 {
1505         struct hns3_mac_vlan_tbl_entry_cmd req;
1506         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1507         int ret;
1508
1509         /* check if mac addr is valid */
1510         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1511                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1512                                       mac_addr);
1513                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1514                          mac_str);
1515                 return -EINVAL;
1516         }
1517
1518         memset(&req, 0, sizeof(req));
1519         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1520         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1521         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1522         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1523                 return 0;
1524         else if (ret == 0)
1525                 hns3_update_umv_space(hw, true);
1526
1527         return ret;
1528 }
1529
1530 static void
1531 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1532 {
1533         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1534         /* index will be checked by upper level rte interface */
1535         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1536         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1537         int ret;
1538
1539         rte_spinlock_lock(&hw->lock);
1540
1541         if (rte_is_multicast_ether_addr(mac_addr))
1542                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1543         else
1544                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1545         rte_spinlock_unlock(&hw->lock);
1546         if (ret) {
1547                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1548                                       mac_addr);
1549                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1550                          ret);
1551         }
1552 }
1553
1554 static int
1555 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1556                           struct rte_ether_addr *mac_addr)
1557 {
1558         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1559         struct rte_ether_addr *oaddr;
1560         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1561         bool default_addr_setted;
1562         bool rm_succes = false;
1563         int ret, ret_val;
1564
1565         /*
1566          * It has been guaranteed that input parameter named mac_addr is valid
1567          * address in the rte layer of DPDK framework.
1568          */
1569         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1570         default_addr_setted = hw->mac.default_addr_setted;
1571         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1572                 return 0;
1573
1574         rte_spinlock_lock(&hw->lock);
1575         if (default_addr_setted) {
1576                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1577                 if (ret) {
1578                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1579                                               oaddr);
1580                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1581                                   mac_str, ret);
1582                         rm_succes = false;
1583                 } else
1584                         rm_succes = true;
1585         }
1586
1587         ret = hns3_add_uc_addr_common(hw, mac_addr);
1588         if (ret) {
1589                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1590                                       mac_addr);
1591                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1592                 goto err_add_uc_addr;
1593         }
1594
1595         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1596         if (ret) {
1597                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1598                 goto err_pause_addr_cfg;
1599         }
1600
1601         rte_ether_addr_copy(mac_addr,
1602                             (struct rte_ether_addr *)hw->mac.mac_addr);
1603         hw->mac.default_addr_setted = true;
1604         rte_spinlock_unlock(&hw->lock);
1605
1606         return 0;
1607
1608 err_pause_addr_cfg:
1609         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1610         if (ret_val) {
1611                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1612                                       mac_addr);
1613                 hns3_warn(hw,
1614                           "Failed to roll back to del setted mac addr(%s): %d",
1615                           mac_str, ret_val);
1616         }
1617
1618 err_add_uc_addr:
1619         if (rm_succes) {
1620                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1621                 if (ret_val) {
1622                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1623                                               oaddr);
1624                         hns3_warn(hw,
1625                                   "Failed to restore old uc mac addr(%s): %d",
1626                                   mac_str, ret_val);
1627                         hw->mac.default_addr_setted = false;
1628                 }
1629         }
1630         rte_spinlock_unlock(&hw->lock);
1631
1632         return ret;
1633 }
1634
1635 static int
1636 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1637 {
1638         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1639         struct hns3_hw *hw = &hns->hw;
1640         struct rte_ether_addr *addr;
1641         int err = 0;
1642         int ret;
1643         int i;
1644
1645         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1646                 addr = &hw->data->mac_addrs[i];
1647                 if (rte_is_zero_ether_addr(addr))
1648                         continue;
1649                 if (rte_is_multicast_ether_addr(addr))
1650                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1651                               hns3_add_mc_addr(hw, addr);
1652                 else
1653                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1654                               hns3_add_uc_addr_common(hw, addr);
1655
1656                 if (ret) {
1657                         err = ret;
1658                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1659                                               addr);
1660                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1661                                  "ret = %d.", del ? "remove" : "restore",
1662                                  mac_str, i, ret);
1663                 }
1664         }
1665         return err;
1666 }
1667
1668 static void
1669 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1670 {
1671 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1672         uint8_t word_num;
1673         uint8_t bit_num;
1674
1675         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1676                 word_num = vfid / 32;
1677                 bit_num = vfid % 32;
1678                 if (clr)
1679                         desc[1].data[word_num] &=
1680                             rte_cpu_to_le_32(~(1UL << bit_num));
1681                 else
1682                         desc[1].data[word_num] |=
1683                             rte_cpu_to_le_32(1UL << bit_num);
1684         } else {
1685                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1686                 bit_num = vfid % 32;
1687                 if (clr)
1688                         desc[2].data[word_num] &=
1689                             rte_cpu_to_le_32(~(1UL << bit_num));
1690                 else
1691                         desc[2].data[word_num] |=
1692                             rte_cpu_to_le_32(1UL << bit_num);
1693         }
1694 }
1695
1696 static int
1697 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1698 {
1699         struct hns3_mac_vlan_tbl_entry_cmd req;
1700         struct hns3_cmd_desc desc[3];
1701         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1702         uint8_t vf_id;
1703         int ret;
1704
1705         /* Check if mac addr is valid */
1706         if (!rte_is_multicast_ether_addr(mac_addr)) {
1707                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1708                                       mac_addr);
1709                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1710                          mac_str);
1711                 return -EINVAL;
1712         }
1713
1714         memset(&req, 0, sizeof(req));
1715         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1716         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1717         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1718         if (ret) {
1719                 /* This mac addr do not exist, add new entry for it */
1720                 memset(desc[0].data, 0, sizeof(desc[0].data));
1721                 memset(desc[1].data, 0, sizeof(desc[0].data));
1722                 memset(desc[2].data, 0, sizeof(desc[0].data));
1723         }
1724
1725         /*
1726          * In current version VF is not supported when PF is driven by DPDK
1727          * driver, the PF-related vf_id is 0, just need to configure parameters
1728          * for vf_id 0.
1729          */
1730         vf_id = 0;
1731         hns3_update_desc_vfid(desc, vf_id, false);
1732         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1733         if (ret) {
1734                 if (ret == -ENOSPC)
1735                         hns3_err(hw, "mc mac vlan table is full");
1736                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1737                                       mac_addr);
1738                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1739         }
1740
1741         return ret;
1742 }
1743
1744 static int
1745 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1746 {
1747         struct hns3_mac_vlan_tbl_entry_cmd req;
1748         struct hns3_cmd_desc desc[3];
1749         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1750         uint8_t vf_id;
1751         int ret;
1752
1753         /* Check if mac addr is valid */
1754         if (!rte_is_multicast_ether_addr(mac_addr)) {
1755                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1756                                       mac_addr);
1757                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1758                          mac_str);
1759                 return -EINVAL;
1760         }
1761
1762         memset(&req, 0, sizeof(req));
1763         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1764         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1765         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1766         if (ret == 0) {
1767                 /*
1768                  * This mac addr exist, remove this handle's VFID for it.
1769                  * In current version VF is not supported when PF is driven by
1770                  * DPDK driver, the PF-related vf_id is 0, just need to
1771                  * configure parameters for vf_id 0.
1772                  */
1773                 vf_id = 0;
1774                 hns3_update_desc_vfid(desc, vf_id, true);
1775
1776                 /* All the vfid is zero, so need to delete this entry */
1777                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1778         } else if (ret == -ENOENT) {
1779                 /* This mac addr doesn't exist. */
1780                 return 0;
1781         }
1782
1783         if (ret) {
1784                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1785                                       mac_addr);
1786                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1787         }
1788
1789         return ret;
1790 }
1791
1792 static int
1793 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1794                            struct rte_ether_addr *mc_addr_set,
1795                            uint32_t nb_mc_addr)
1796 {
1797         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1798         struct rte_ether_addr *addr;
1799         uint32_t i;
1800         uint32_t j;
1801
1802         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1803                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1804                          "invalid. valid range: 0~%d",
1805                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1806                 return -EINVAL;
1807         }
1808
1809         /* Check if input mac addresses are valid */
1810         for (i = 0; i < nb_mc_addr; i++) {
1811                 addr = &mc_addr_set[i];
1812                 if (!rte_is_multicast_ether_addr(addr)) {
1813                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1814                                               addr);
1815                         hns3_err(hw,
1816                                  "failed to set mc mac addr, addr(%s) invalid.",
1817                                  mac_str);
1818                         return -EINVAL;
1819                 }
1820
1821                 /* Check if there are duplicate addresses */
1822                 for (j = i + 1; j < nb_mc_addr; j++) {
1823                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1824                                 rte_ether_format_addr(mac_str,
1825                                                       RTE_ETHER_ADDR_FMT_SIZE,
1826                                                       addr);
1827                                 hns3_err(hw, "failed to set mc mac addr, "
1828                                          "addrs invalid. two same addrs(%s).",
1829                                          mac_str);
1830                                 return -EINVAL;
1831                         }
1832                 }
1833
1834                 /*
1835                  * Check if there are duplicate addresses between mac_addrs
1836                  * and mc_addr_set
1837                  */
1838                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1839                         if (rte_is_same_ether_addr(addr,
1840                                                    &hw->data->mac_addrs[j])) {
1841                                 rte_ether_format_addr(mac_str,
1842                                                       RTE_ETHER_ADDR_FMT_SIZE,
1843                                                       addr);
1844                                 hns3_err(hw, "failed to set mc mac addr, "
1845                                          "addrs invalid. addrs(%s) has already "
1846                                          "configured in mac_addr add API",
1847                                          mac_str);
1848                                 return -EINVAL;
1849                         }
1850                 }
1851         }
1852
1853         return 0;
1854 }
1855
1856 static void
1857 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1858                            struct rte_ether_addr *mc_addr_set,
1859                            int mc_addr_num,
1860                            struct rte_ether_addr *reserved_addr_list,
1861                            int *reserved_addr_num,
1862                            struct rte_ether_addr *add_addr_list,
1863                            int *add_addr_num,
1864                            struct rte_ether_addr *rm_addr_list,
1865                            int *rm_addr_num)
1866 {
1867         struct rte_ether_addr *addr;
1868         int current_addr_num;
1869         int reserved_num = 0;
1870         int add_num = 0;
1871         int rm_num = 0;
1872         int num;
1873         int i;
1874         int j;
1875         bool same_addr;
1876
1877         /* Calculate the mc mac address list that should be removed */
1878         current_addr_num = hw->mc_addrs_num;
1879         for (i = 0; i < current_addr_num; i++) {
1880                 addr = &hw->mc_addrs[i];
1881                 same_addr = false;
1882                 for (j = 0; j < mc_addr_num; j++) {
1883                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1884                                 same_addr = true;
1885                                 break;
1886                         }
1887                 }
1888
1889                 if (!same_addr) {
1890                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1891                         rm_num++;
1892                 } else {
1893                         rte_ether_addr_copy(addr,
1894                                             &reserved_addr_list[reserved_num]);
1895                         reserved_num++;
1896                 }
1897         }
1898
1899         /* Calculate the mc mac address list that should be added */
1900         for (i = 0; i < mc_addr_num; i++) {
1901                 addr = &mc_addr_set[i];
1902                 same_addr = false;
1903                 for (j = 0; j < current_addr_num; j++) {
1904                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1905                                 same_addr = true;
1906                                 break;
1907                         }
1908                 }
1909
1910                 if (!same_addr) {
1911                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1912                         add_num++;
1913                 }
1914         }
1915
1916         /* Reorder the mc mac address list maintained by driver */
1917         for (i = 0; i < reserved_num; i++)
1918                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1919
1920         for (i = 0; i < rm_num; i++) {
1921                 num = reserved_num + i;
1922                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1923         }
1924
1925         *reserved_addr_num = reserved_num;
1926         *add_addr_num = add_num;
1927         *rm_addr_num = rm_num;
1928 }
1929
1930 static int
1931 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1932                           struct rte_ether_addr *mc_addr_set,
1933                           uint32_t nb_mc_addr)
1934 {
1935         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1936         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1937         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1938         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1939         struct rte_ether_addr *addr;
1940         int reserved_addr_num;
1941         int add_addr_num;
1942         int rm_addr_num;
1943         int mc_addr_num;
1944         int num;
1945         int ret;
1946         int i;
1947
1948         /* Check if input parameters are valid */
1949         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1950         if (ret)
1951                 return ret;
1952
1953         rte_spinlock_lock(&hw->lock);
1954
1955         /*
1956          * Calculate the mc mac address lists those should be removed and be
1957          * added, Reorder the mc mac address list maintained by driver.
1958          */
1959         mc_addr_num = (int)nb_mc_addr;
1960         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1961                                    reserved_addr_list, &reserved_addr_num,
1962                                    add_addr_list, &add_addr_num,
1963                                    rm_addr_list, &rm_addr_num);
1964
1965         /* Remove mc mac addresses */
1966         for (i = 0; i < rm_addr_num; i++) {
1967                 num = rm_addr_num - i - 1;
1968                 addr = &rm_addr_list[num];
1969                 ret = hns3_remove_mc_addr(hw, addr);
1970                 if (ret) {
1971                         rte_spinlock_unlock(&hw->lock);
1972                         return ret;
1973                 }
1974                 hw->mc_addrs_num--;
1975         }
1976
1977         /* Add mc mac addresses */
1978         for (i = 0; i < add_addr_num; i++) {
1979                 addr = &add_addr_list[i];
1980                 ret = hns3_add_mc_addr(hw, addr);
1981                 if (ret) {
1982                         rte_spinlock_unlock(&hw->lock);
1983                         return ret;
1984                 }
1985
1986                 num = reserved_addr_num + i;
1987                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1988                 hw->mc_addrs_num++;
1989         }
1990         rte_spinlock_unlock(&hw->lock);
1991
1992         return 0;
1993 }
1994
1995 static int
1996 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1997 {
1998         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1999         struct hns3_hw *hw = &hns->hw;
2000         struct rte_ether_addr *addr;
2001         int err = 0;
2002         int ret;
2003         int i;
2004
2005         for (i = 0; i < hw->mc_addrs_num; i++) {
2006                 addr = &hw->mc_addrs[i];
2007                 if (!rte_is_multicast_ether_addr(addr))
2008                         continue;
2009                 if (del)
2010                         ret = hns3_remove_mc_addr(hw, addr);
2011                 else
2012                         ret = hns3_add_mc_addr(hw, addr);
2013                 if (ret) {
2014                         err = ret;
2015                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2016                                               addr);
2017                         hns3_dbg(hw, "%s mc mac addr: %s failed",
2018                                  del ? "Remove" : "Restore", mac_str);
2019                 }
2020         }
2021         return err;
2022 }
2023
2024 static int
2025 hns3_check_mq_mode(struct rte_eth_dev *dev)
2026 {
2027         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2028         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2029         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2030         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2031         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2032         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2033         uint8_t num_tc;
2034         int max_tc = 0;
2035         int i;
2036
2037         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2038         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2039
2040         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2041                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2042                          "rx_mq_mode = %d", rx_mq_mode);
2043                 return -EINVAL;
2044         }
2045
2046         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2047             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2048                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2049                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2050                          rx_mq_mode, tx_mq_mode);
2051                 return -EINVAL;
2052         }
2053
2054         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2055                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2056                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2057                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2058                         return -EINVAL;
2059                 }
2060
2061                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2062                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2063                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2064                                  "nb_tcs(%d) != %d or %d in rx direction.",
2065                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2066                         return -EINVAL;
2067                 }
2068
2069                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2070                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2071                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2072                         return -EINVAL;
2073                 }
2074
2075                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2076                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2077                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2078                                          "is not equal to one in tx direction.",
2079                                          i, dcb_rx_conf->dcb_tc[i]);
2080                                 return -EINVAL;
2081                         }
2082                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2083                                 max_tc = dcb_rx_conf->dcb_tc[i];
2084                 }
2085
2086                 num_tc = max_tc + 1;
2087                 if (num_tc > dcb_rx_conf->nb_tcs) {
2088                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2089                                  num_tc, dcb_rx_conf->nb_tcs);
2090                         return -EINVAL;
2091                 }
2092         }
2093
2094         return 0;
2095 }
2096
2097 static int
2098 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2099 {
2100         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2101
2102         if (!hns3_dev_dcb_supported(hw)) {
2103                 hns3_err(hw, "this port does not support dcb configurations.");
2104                 return -EOPNOTSUPP;
2105         }
2106
2107         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2108                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2109                 return -EOPNOTSUPP;
2110         }
2111
2112         /* Check multiple queue mode */
2113         return hns3_check_mq_mode(dev);
2114 }
2115
2116 static int
2117 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2118                            enum hns3_ring_type queue_type, uint16_t queue_id)
2119 {
2120         struct hns3_cmd_desc desc;
2121         struct hns3_ctrl_vector_chain_cmd *req =
2122                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2123         enum hns3_cmd_status status;
2124         enum hns3_opcode_type op;
2125         uint16_t tqp_type_and_id = 0;
2126         const char *op_str;
2127         uint16_t type;
2128         uint16_t gl;
2129
2130         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2131         hns3_cmd_setup_basic_desc(&desc, op, false);
2132         req->int_vector_id = vector_id;
2133
2134         if (queue_type == HNS3_RING_TYPE_RX)
2135                 gl = HNS3_RING_GL_RX;
2136         else
2137                 gl = HNS3_RING_GL_TX;
2138
2139         type = queue_type;
2140
2141         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2142                        type);
2143         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2144         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2145                        gl);
2146         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2147         req->int_cause_num = 1;
2148         op_str = mmap ? "Map" : "Unmap";
2149         status = hns3_cmd_send(hw, &desc, 1);
2150         if (status) {
2151                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2152                          op_str, queue_id, req->int_vector_id, status);
2153                 return status;
2154         }
2155
2156         return 0;
2157 }
2158
2159 static int
2160 hns3_init_ring_with_vector(struct hns3_hw *hw)
2161 {
2162         uint8_t vec;
2163         int ret;
2164         int i;
2165
2166         /*
2167          * In hns3 network engine, vector 0 is always the misc interrupt of this
2168          * function, vector 1~N can be used respectively for the queues of the
2169          * function. Tx and Rx queues with the same number share the interrupt
2170          * vector. In the initialization clearing the all hardware mapping
2171          * relationship configurations between queues and interrupt vectors is
2172          * needed, so some error caused by the residual configurations, such as
2173          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2174          * constraints in hns3 hardware engine, we have to implement clearing
2175          * the mapping relationship configurations by binding all queues to the
2176          * last interrupt vector and reserving the last interrupt vector. This
2177          * method results in a decrease of the maximum queues when upper
2178          * applications call the rte_eth_dev_configure API function to enable
2179          * Rx interrupt.
2180          */
2181         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2182         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
2183         for (i = 0; i < hw->intr_tqps_num; i++) {
2184                 /*
2185                  * Set gap limiter and rate limiter configuration of queue's
2186                  * interrupt.
2187                  */
2188                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2189                                        HNS3_TQP_INTR_GL_DEFAULT);
2190                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2191                                        HNS3_TQP_INTR_GL_DEFAULT);
2192                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2193
2194                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2195                                                  HNS3_RING_TYPE_TX, i);
2196                 if (ret) {
2197                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2198                                           "vector: %d, ret=%d", i, vec, ret);
2199                         return ret;
2200                 }
2201
2202                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2203                                                  HNS3_RING_TYPE_RX, i);
2204                 if (ret) {
2205                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2206                                           "vector: %d, ret=%d", i, vec, ret);
2207                         return ret;
2208                 }
2209         }
2210
2211         return 0;
2212 }
2213
2214 static int
2215 hns3_dev_configure(struct rte_eth_dev *dev)
2216 {
2217         struct hns3_adapter *hns = dev->data->dev_private;
2218         struct rte_eth_conf *conf = &dev->data->dev_conf;
2219         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2220         struct hns3_hw *hw = &hns->hw;
2221         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2222         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2223         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2224         struct rte_eth_rss_conf rss_conf;
2225         uint16_t mtu;
2226         int ret;
2227
2228         /*
2229          * Hardware does not support individually enable/disable/reset the Tx or
2230          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2231          * and Rx queues at the same time. When the numbers of Tx queues
2232          * allocated by upper applications are not equal to the numbers of Rx
2233          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2234          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2235          * these fake queues are imperceptible, and can not be used by upper
2236          * applications.
2237          */
2238         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2239         if (ret) {
2240                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2241                 return ret;
2242         }
2243
2244         hw->adapter_state = HNS3_NIC_CONFIGURING;
2245         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2246                 hns3_err(hw, "setting link speed/duplex not supported");
2247                 ret = -EINVAL;
2248                 goto cfg_err;
2249         }
2250
2251         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2252                 ret = hns3_check_dcb_cfg(dev);
2253                 if (ret)
2254                         goto cfg_err;
2255         }
2256
2257         /* When RSS is not configured, redirect the packet queue 0 */
2258         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2259                 rss_conf = conf->rx_adv_conf.rss_conf;
2260                 if (rss_conf.rss_key == NULL) {
2261                         rss_conf.rss_key = rss_cfg->key;
2262                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2263                 }
2264
2265                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2266                 if (ret)
2267                         goto cfg_err;
2268         }
2269
2270         /*
2271          * If jumbo frames are enabled, MTU needs to be refreshed
2272          * according to the maximum RX packet length.
2273          */
2274         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2275                 /*
2276                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2277                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2278                  * can safely assign to "uint16_t" type variable.
2279                  */
2280                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2281                 ret = hns3_dev_mtu_set(dev, mtu);
2282                 if (ret)
2283                         goto cfg_err;
2284                 dev->data->mtu = mtu;
2285         }
2286
2287         ret = hns3_dev_configure_vlan(dev);
2288         if (ret)
2289                 goto cfg_err;
2290
2291         hw->adapter_state = HNS3_NIC_CONFIGURED;
2292
2293         return 0;
2294
2295 cfg_err:
2296         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2297         hw->adapter_state = HNS3_NIC_INITIALIZED;
2298
2299         return ret;
2300 }
2301
2302 static int
2303 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2304 {
2305         struct hns3_config_max_frm_size_cmd *req;
2306         struct hns3_cmd_desc desc;
2307
2308         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2309
2310         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2311         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2312         req->min_frm_size = RTE_ETHER_MIN_LEN;
2313
2314         return hns3_cmd_send(hw, &desc, 1);
2315 }
2316
2317 static int
2318 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2319 {
2320         int ret;
2321
2322         ret = hns3_set_mac_mtu(hw, mps);
2323         if (ret) {
2324                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2325                 return ret;
2326         }
2327
2328         ret = hns3_buffer_alloc(hw);
2329         if (ret)
2330                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2331
2332         return ret;
2333 }
2334
2335 static int
2336 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2337 {
2338         struct hns3_adapter *hns = dev->data->dev_private;
2339         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2340         struct hns3_hw *hw = &hns->hw;
2341         bool is_jumbo_frame;
2342         int ret;
2343
2344         if (dev->data->dev_started) {
2345                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2346                          "before configuration", dev->data->port_id);
2347                 return -EBUSY;
2348         }
2349
2350         rte_spinlock_lock(&hw->lock);
2351         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2352         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2353
2354         /*
2355          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2356          * assign to "uint16_t" type variable.
2357          */
2358         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2359         if (ret) {
2360                 rte_spinlock_unlock(&hw->lock);
2361                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2362                          dev->data->port_id, mtu, ret);
2363                 return ret;
2364         }
2365         hns->pf.mps = (uint16_t)frame_size;
2366         if (is_jumbo_frame)
2367                 dev->data->dev_conf.rxmode.offloads |=
2368                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2369         else
2370                 dev->data->dev_conf.rxmode.offloads &=
2371                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2372         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2373         rte_spinlock_unlock(&hw->lock);
2374
2375         return 0;
2376 }
2377
2378 static int
2379 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2380 {
2381         struct hns3_adapter *hns = eth_dev->data->dev_private;
2382         struct hns3_hw *hw = &hns->hw;
2383         uint16_t queue_num = hw->tqps_num;
2384
2385         /*
2386          * In interrupt mode, 'max_rx_queues' is set based on the number of
2387          * MSI-X interrupt resources of the hardware.
2388          */
2389         if (hw->data->dev_conf.intr_conf.rxq == 1)
2390                 queue_num = hw->intr_tqps_num;
2391
2392         info->max_rx_queues = queue_num;
2393         info->max_tx_queues = hw->tqps_num;
2394         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2395         info->min_rx_bufsize = hw->rx_buf_len;
2396         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2397         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2398         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2399                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2400                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2401                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2402                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2403                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2404                                  DEV_RX_OFFLOAD_KEEP_CRC |
2405                                  DEV_RX_OFFLOAD_SCATTER |
2406                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2407                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2408                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2409                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2410                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
2411         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2412         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2413                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2414                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2415                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2416                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2417                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2418                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2419                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2420                                  DEV_TX_OFFLOAD_TCP_TSO |
2421                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2422                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2423                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2424                                  info->tx_queue_offload_capa);
2425
2426         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2427                 .nb_max = HNS3_MAX_RING_DESC,
2428                 .nb_min = HNS3_MIN_RING_DESC,
2429                 .nb_align = HNS3_ALIGN_RING_DESC,
2430         };
2431
2432         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2433                 .nb_max = HNS3_MAX_RING_DESC,
2434                 .nb_min = HNS3_MIN_RING_DESC,
2435                 .nb_align = HNS3_ALIGN_RING_DESC,
2436         };
2437
2438         info->vmdq_queue_num = 0;
2439
2440         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2441         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2442         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2443
2444         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2445         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2446         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2447         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2448         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2449         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2450
2451         return 0;
2452 }
2453
2454 static int
2455 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2456                     size_t fw_size)
2457 {
2458         struct hns3_adapter *hns = eth_dev->data->dev_private;
2459         struct hns3_hw *hw = &hns->hw;
2460         int ret;
2461
2462         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2463         ret += 1; /* add the size of '\0' */
2464         if (fw_size < (uint32_t)ret)
2465                 return ret;
2466         else
2467                 return 0;
2468 }
2469
2470 static int
2471 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2472                      __rte_unused int wait_to_complete)
2473 {
2474         struct hns3_adapter *hns = eth_dev->data->dev_private;
2475         struct hns3_hw *hw = &hns->hw;
2476         struct hns3_mac *mac = &hw->mac;
2477         struct rte_eth_link new_link;
2478
2479         if (!hns3_is_reset_pending(hns)) {
2480                 hns3_update_speed_duplex(eth_dev);
2481                 hns3_update_link_status(hw);
2482         }
2483
2484         memset(&new_link, 0, sizeof(new_link));
2485         switch (mac->link_speed) {
2486         case ETH_SPEED_NUM_10M:
2487         case ETH_SPEED_NUM_100M:
2488         case ETH_SPEED_NUM_1G:
2489         case ETH_SPEED_NUM_10G:
2490         case ETH_SPEED_NUM_25G:
2491         case ETH_SPEED_NUM_40G:
2492         case ETH_SPEED_NUM_50G:
2493         case ETH_SPEED_NUM_100G:
2494                 new_link.link_speed = mac->link_speed;
2495                 break;
2496         default:
2497                 new_link.link_speed = ETH_SPEED_NUM_100M;
2498                 break;
2499         }
2500
2501         new_link.link_duplex = mac->link_duplex;
2502         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2503         new_link.link_autoneg =
2504             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2505
2506         return rte_eth_linkstatus_set(eth_dev, &new_link);
2507 }
2508
2509 static int
2510 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2511 {
2512         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2513         struct hns3_pf *pf = &hns->pf;
2514
2515         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2516                 return -EINVAL;
2517
2518         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2519
2520         return 0;
2521 }
2522
2523 static int
2524 hns3_query_function_status(struct hns3_hw *hw)
2525 {
2526 #define HNS3_QUERY_MAX_CNT              10
2527 #define HNS3_QUERY_SLEEP_MSCOEND        1
2528         struct hns3_func_status_cmd *req;
2529         struct hns3_cmd_desc desc;
2530         int timeout = 0;
2531         int ret;
2532
2533         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2534         req = (struct hns3_func_status_cmd *)desc.data;
2535
2536         do {
2537                 ret = hns3_cmd_send(hw, &desc, 1);
2538                 if (ret) {
2539                         PMD_INIT_LOG(ERR, "query function status failed %d",
2540                                      ret);
2541                         return ret;
2542                 }
2543
2544                 /* Check pf reset is done */
2545                 if (req->pf_state)
2546                         break;
2547
2548                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2549         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2550
2551         return hns3_parse_func_status(hw, req);
2552 }
2553
2554 static int
2555 hns3_query_pf_resource(struct hns3_hw *hw)
2556 {
2557         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2558         struct hns3_pf *pf = &hns->pf;
2559         struct hns3_pf_res_cmd *req;
2560         struct hns3_cmd_desc desc;
2561         uint16_t num_msi;
2562         int ret;
2563
2564         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2565         ret = hns3_cmd_send(hw, &desc, 1);
2566         if (ret) {
2567                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2568                 return ret;
2569         }
2570
2571         req = (struct hns3_pf_res_cmd *)desc.data;
2572         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2573         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2574         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2575         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2576
2577         if (req->tx_buf_size)
2578                 pf->tx_buf_size =
2579                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2580         else
2581                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2582
2583         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2584
2585         if (req->dv_buf_size)
2586                 pf->dv_buf_size =
2587                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2588         else
2589                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2590
2591         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2592
2593         num_msi = hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2594                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2595         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
2596
2597         return 0;
2598 }
2599
2600 static void
2601 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2602 {
2603         struct hns3_cfg_param_cmd *req;
2604         uint64_t mac_addr_tmp_high;
2605         uint64_t mac_addr_tmp;
2606         uint32_t i;
2607
2608         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2609
2610         /* get the configuration */
2611         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2612                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2613         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2614                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2615         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2616                                            HNS3_CFG_TQP_DESC_N_M,
2617                                            HNS3_CFG_TQP_DESC_N_S);
2618
2619         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2620                                        HNS3_CFG_PHY_ADDR_M,
2621                                        HNS3_CFG_PHY_ADDR_S);
2622         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2623                                          HNS3_CFG_MEDIA_TP_M,
2624                                          HNS3_CFG_MEDIA_TP_S);
2625         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2626                                          HNS3_CFG_RX_BUF_LEN_M,
2627                                          HNS3_CFG_RX_BUF_LEN_S);
2628         /* get mac address */
2629         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2630         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2631                                            HNS3_CFG_MAC_ADDR_H_M,
2632                                            HNS3_CFG_MAC_ADDR_H_S);
2633
2634         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2635
2636         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2637                                             HNS3_CFG_DEFAULT_SPEED_M,
2638                                             HNS3_CFG_DEFAULT_SPEED_S);
2639         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2640                                            HNS3_CFG_RSS_SIZE_M,
2641                                            HNS3_CFG_RSS_SIZE_S);
2642
2643         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2644                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2645
2646         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2647         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2648
2649         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2650                                             HNS3_CFG_SPEED_ABILITY_M,
2651                                             HNS3_CFG_SPEED_ABILITY_S);
2652         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2653                                         HNS3_CFG_UMV_TBL_SPACE_M,
2654                                         HNS3_CFG_UMV_TBL_SPACE_S);
2655         if (!cfg->umv_space)
2656                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2657 }
2658
2659 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2660  * @hw: pointer to struct hns3_hw
2661  * @hcfg: the config structure to be getted
2662  */
2663 static int
2664 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2665 {
2666         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2667         struct hns3_cfg_param_cmd *req;
2668         uint32_t offset;
2669         uint32_t i;
2670         int ret;
2671
2672         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2673                 offset = 0;
2674                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2675                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2676                                           true);
2677                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2678                                i * HNS3_CFG_RD_LEN_BYTES);
2679                 /* Len should be divided by 4 when send to hardware */
2680                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2681                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2682                 req->offset = rte_cpu_to_le_32(offset);
2683         }
2684
2685         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2686         if (ret) {
2687                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2688                 return ret;
2689         }
2690
2691         hns3_parse_cfg(hcfg, desc);
2692
2693         return 0;
2694 }
2695
2696 static int
2697 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2698 {
2699         switch (speed_cmd) {
2700         case HNS3_CFG_SPEED_10M:
2701                 *speed = ETH_SPEED_NUM_10M;
2702                 break;
2703         case HNS3_CFG_SPEED_100M:
2704                 *speed = ETH_SPEED_NUM_100M;
2705                 break;
2706         case HNS3_CFG_SPEED_1G:
2707                 *speed = ETH_SPEED_NUM_1G;
2708                 break;
2709         case HNS3_CFG_SPEED_10G:
2710                 *speed = ETH_SPEED_NUM_10G;
2711                 break;
2712         case HNS3_CFG_SPEED_25G:
2713                 *speed = ETH_SPEED_NUM_25G;
2714                 break;
2715         case HNS3_CFG_SPEED_40G:
2716                 *speed = ETH_SPEED_NUM_40G;
2717                 break;
2718         case HNS3_CFG_SPEED_50G:
2719                 *speed = ETH_SPEED_NUM_50G;
2720                 break;
2721         case HNS3_CFG_SPEED_100G:
2722                 *speed = ETH_SPEED_NUM_100G;
2723                 break;
2724         default:
2725                 return -EINVAL;
2726         }
2727
2728         return 0;
2729 }
2730
2731 static int
2732 hns3_get_board_configuration(struct hns3_hw *hw)
2733 {
2734         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2735         struct hns3_pf *pf = &hns->pf;
2736         struct hns3_cfg cfg;
2737         int ret;
2738
2739         ret = hns3_get_board_cfg(hw, &cfg);
2740         if (ret) {
2741                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2742                 return ret;
2743         }
2744
2745         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2746                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2747                 return -EOPNOTSUPP;
2748         }
2749
2750         hw->mac.media_type = cfg.media_type;
2751         hw->rss_size_max = cfg.rss_size_max;
2752         hw->rss_dis_flag = false;
2753         hw->rx_buf_len = cfg.rx_buf_len;
2754         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2755         hw->mac.phy_addr = cfg.phy_addr;
2756         hw->mac.default_addr_setted = false;
2757         hw->num_tx_desc = cfg.tqp_desc_num;
2758         hw->num_rx_desc = cfg.tqp_desc_num;
2759         hw->dcb_info.num_pg = 1;
2760         hw->dcb_info.hw_pfc_map = 0;
2761
2762         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2763         if (ret) {
2764                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2765                              cfg.default_speed, ret);
2766                 return ret;
2767         }
2768
2769         pf->tc_max = cfg.tc_num;
2770         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2771                 PMD_INIT_LOG(WARNING,
2772                              "Get TC num(%u) from flash, set TC num to 1",
2773                              pf->tc_max);
2774                 pf->tc_max = 1;
2775         }
2776
2777         /* Dev does not support DCB */
2778         if (!hns3_dev_dcb_supported(hw)) {
2779                 pf->tc_max = 1;
2780                 pf->pfc_max = 0;
2781         } else
2782                 pf->pfc_max = pf->tc_max;
2783
2784         hw->dcb_info.num_tc = 1;
2785         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2786                                      hw->tqps_num / hw->dcb_info.num_tc);
2787         hns3_set_bit(hw->hw_tc_map, 0, 1);
2788         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2789
2790         pf->wanted_umv_size = cfg.umv_space;
2791
2792         return ret;
2793 }
2794
2795 static int
2796 hns3_get_configuration(struct hns3_hw *hw)
2797 {
2798         int ret;
2799
2800         ret = hns3_query_function_status(hw);
2801         if (ret) {
2802                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2803                 return ret;
2804         }
2805
2806         /* Get pf resource */
2807         ret = hns3_query_pf_resource(hw);
2808         if (ret) {
2809                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2810                 return ret;
2811         }
2812
2813         ret = hns3_get_board_configuration(hw);
2814         if (ret)
2815                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2816
2817         return ret;
2818 }
2819
2820 static int
2821 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2822                       uint16_t tqp_vid, bool is_pf)
2823 {
2824         struct hns3_tqp_map_cmd *req;
2825         struct hns3_cmd_desc desc;
2826         int ret;
2827
2828         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2829
2830         req = (struct hns3_tqp_map_cmd *)desc.data;
2831         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2832         req->tqp_vf = func_id;
2833         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2834         if (!is_pf)
2835                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2836         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2837
2838         ret = hns3_cmd_send(hw, &desc, 1);
2839         if (ret)
2840                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2841
2842         return ret;
2843 }
2844
2845 static int
2846 hns3_map_tqp(struct hns3_hw *hw)
2847 {
2848         uint16_t tqps_num = hw->total_tqps_num;
2849         uint16_t func_id;
2850         uint16_t tqp_id;
2851         bool is_pf;
2852         int num;
2853         int ret;
2854         int i;
2855
2856         /*
2857          * In current version VF is not supported when PF is driven by DPDK
2858          * driver, so we allocate tqps to PF as much as possible.
2859          */
2860         tqp_id = 0;
2861         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2862         for (func_id = 0; func_id < num; func_id++) {
2863                 is_pf = func_id == 0 ? true : false;
2864                 for (i = 0;
2865                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2866                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2867                                                     is_pf);
2868                         if (ret)
2869                                 return ret;
2870                 }
2871         }
2872
2873         return 0;
2874 }
2875
2876 static int
2877 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2878 {
2879         struct hns3_config_mac_speed_dup_cmd *req;
2880         struct hns3_cmd_desc desc;
2881         int ret;
2882
2883         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2884
2885         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2886
2887         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2888
2889         switch (speed) {
2890         case ETH_SPEED_NUM_10M:
2891                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2892                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2893                 break;
2894         case ETH_SPEED_NUM_100M:
2895                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2896                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2897                 break;
2898         case ETH_SPEED_NUM_1G:
2899                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2900                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2901                 break;
2902         case ETH_SPEED_NUM_10G:
2903                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2904                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2905                 break;
2906         case ETH_SPEED_NUM_25G:
2907                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2908                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2909                 break;
2910         case ETH_SPEED_NUM_40G:
2911                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2912                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2913                 break;
2914         case ETH_SPEED_NUM_50G:
2915                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2916                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2917                 break;
2918         case ETH_SPEED_NUM_100G:
2919                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2920                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2921                 break;
2922         default:
2923                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2924                 return -EINVAL;
2925         }
2926
2927         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2928
2929         ret = hns3_cmd_send(hw, &desc, 1);
2930         if (ret)
2931                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2932
2933         return ret;
2934 }
2935
2936 static int
2937 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2938 {
2939         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2940         struct hns3_pf *pf = &hns->pf;
2941         struct hns3_priv_buf *priv;
2942         uint32_t i, total_size;
2943
2944         total_size = pf->pkt_buf_size;
2945
2946         /* alloc tx buffer for all enabled tc */
2947         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2948                 priv = &buf_alloc->priv_buf[i];
2949
2950                 if (hw->hw_tc_map & BIT(i)) {
2951                         if (total_size < pf->tx_buf_size)
2952                                 return -ENOMEM;
2953
2954                         priv->tx_buf_size = pf->tx_buf_size;
2955                 } else
2956                         priv->tx_buf_size = 0;
2957
2958                 total_size -= priv->tx_buf_size;
2959         }
2960
2961         return 0;
2962 }
2963
2964 static int
2965 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2966 {
2967 /* TX buffer size is unit by 128 byte */
2968 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
2969 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
2970         struct hns3_tx_buff_alloc_cmd *req;
2971         struct hns3_cmd_desc desc;
2972         uint32_t buf_size;
2973         uint32_t i;
2974         int ret;
2975
2976         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2977
2978         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2979         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2980                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2981
2982                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2983                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2984                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2985         }
2986
2987         ret = hns3_cmd_send(hw, &desc, 1);
2988         if (ret)
2989                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2990
2991         return ret;
2992 }
2993
2994 static int
2995 hns3_get_tc_num(struct hns3_hw *hw)
2996 {
2997         int cnt = 0;
2998         uint8_t i;
2999
3000         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3001                 if (hw->hw_tc_map & BIT(i))
3002                         cnt++;
3003         return cnt;
3004 }
3005
3006 static uint32_t
3007 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3008 {
3009         struct hns3_priv_buf *priv;
3010         uint32_t rx_priv = 0;
3011         int i;
3012
3013         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3014                 priv = &buf_alloc->priv_buf[i];
3015                 if (priv->enable)
3016                         rx_priv += priv->buf_size;
3017         }
3018         return rx_priv;
3019 }
3020
3021 static uint32_t
3022 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3023 {
3024         uint32_t total_tx_size = 0;
3025         uint32_t i;
3026
3027         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3028                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3029
3030         return total_tx_size;
3031 }
3032
3033 /* Get the number of pfc enabled TCs, which have private buffer */
3034 static int
3035 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3036 {
3037         struct hns3_priv_buf *priv;
3038         int cnt = 0;
3039         uint8_t i;
3040
3041         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3042                 priv = &buf_alloc->priv_buf[i];
3043                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3044                         cnt++;
3045         }
3046
3047         return cnt;
3048 }
3049
3050 /* Get the number of pfc disabled TCs, which have private buffer */
3051 static int
3052 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3053                          struct hns3_pkt_buf_alloc *buf_alloc)
3054 {
3055         struct hns3_priv_buf *priv;
3056         int cnt = 0;
3057         uint8_t i;
3058
3059         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3060                 priv = &buf_alloc->priv_buf[i];
3061                 if (hw->hw_tc_map & BIT(i) &&
3062                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3063                         cnt++;
3064         }
3065
3066         return cnt;
3067 }
3068
3069 static bool
3070 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3071                   uint32_t rx_all)
3072 {
3073         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3074         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3075         struct hns3_pf *pf = &hns->pf;
3076         uint32_t shared_buf, aligned_mps;
3077         uint32_t rx_priv;
3078         uint8_t tc_num;
3079         uint8_t i;
3080
3081         tc_num = hns3_get_tc_num(hw);
3082         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3083
3084         if (hns3_dev_dcb_supported(hw))
3085                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3086                                         pf->dv_buf_size;
3087         else
3088                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3089                                         + pf->dv_buf_size;
3090
3091         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3092         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3093                              HNS3_BUF_SIZE_UNIT);
3094
3095         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3096         if (rx_all < rx_priv + shared_std)
3097                 return false;
3098
3099         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3100         buf_alloc->s_buf.buf_size = shared_buf;
3101         if (hns3_dev_dcb_supported(hw)) {
3102                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3103                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3104                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3105                                   HNS3_BUF_SIZE_UNIT);
3106         } else {
3107                 buf_alloc->s_buf.self.high =
3108                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3109                 buf_alloc->s_buf.self.low = aligned_mps;
3110         }
3111
3112         if (hns3_dev_dcb_supported(hw)) {
3113                 hi_thrd = shared_buf - pf->dv_buf_size;
3114
3115                 if (tc_num <= NEED_RESERVE_TC_NUM)
3116                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3117                                         / BUF_MAX_PERCENT;
3118
3119                 if (tc_num)
3120                         hi_thrd = hi_thrd / tc_num;
3121
3122                 hi_thrd = max_t(uint32_t, hi_thrd,
3123                                 HNS3_BUF_MUL_BY * aligned_mps);
3124                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3125                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3126         } else {
3127                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3128                 lo_thrd = aligned_mps;
3129         }
3130
3131         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3132                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3133                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3134         }
3135
3136         return true;
3137 }
3138
3139 static bool
3140 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3141                      struct hns3_pkt_buf_alloc *buf_alloc)
3142 {
3143         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3144         struct hns3_pf *pf = &hns->pf;
3145         struct hns3_priv_buf *priv;
3146         uint32_t aligned_mps;
3147         uint32_t rx_all;
3148         uint8_t i;
3149
3150         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3151         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3152
3153         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3154                 priv = &buf_alloc->priv_buf[i];
3155
3156                 priv->enable = 0;
3157                 priv->wl.low = 0;
3158                 priv->wl.high = 0;
3159                 priv->buf_size = 0;
3160
3161                 if (!(hw->hw_tc_map & BIT(i)))
3162                         continue;
3163
3164                 priv->enable = 1;
3165                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3166                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3167                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3168                                                 HNS3_BUF_SIZE_UNIT);
3169                 } else {
3170                         priv->wl.low = 0;
3171                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3172                                         aligned_mps;
3173                 }
3174
3175                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3176         }
3177
3178         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3179 }
3180
3181 static bool
3182 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3183                              struct hns3_pkt_buf_alloc *buf_alloc)
3184 {
3185         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3186         struct hns3_pf *pf = &hns->pf;
3187         struct hns3_priv_buf *priv;
3188         int no_pfc_priv_num;
3189         uint32_t rx_all;
3190         uint8_t mask;
3191         int i;
3192
3193         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3194         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3195
3196         /* let the last to be cleared first */
3197         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3198                 priv = &buf_alloc->priv_buf[i];
3199                 mask = BIT((uint8_t)i);
3200
3201                 if (hw->hw_tc_map & mask &&
3202                     !(hw->dcb_info.hw_pfc_map & mask)) {
3203                         /* Clear the no pfc TC private buffer */
3204                         priv->wl.low = 0;
3205                         priv->wl.high = 0;
3206                         priv->buf_size = 0;
3207                         priv->enable = 0;
3208                         no_pfc_priv_num--;
3209                 }
3210
3211                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3212                     no_pfc_priv_num == 0)
3213                         break;
3214         }
3215
3216         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3217 }
3218
3219 static bool
3220 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3221                            struct hns3_pkt_buf_alloc *buf_alloc)
3222 {
3223         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3224         struct hns3_pf *pf = &hns->pf;
3225         struct hns3_priv_buf *priv;
3226         uint32_t rx_all;
3227         int pfc_priv_num;
3228         uint8_t mask;
3229         int i;
3230
3231         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3232         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3233
3234         /* let the last to be cleared first */
3235         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3236                 priv = &buf_alloc->priv_buf[i];
3237                 mask = BIT((uint8_t)i);
3238
3239                 if (hw->hw_tc_map & mask &&
3240                     hw->dcb_info.hw_pfc_map & mask) {
3241                         /* Reduce the number of pfc TC with private buffer */
3242                         priv->wl.low = 0;
3243                         priv->enable = 0;
3244                         priv->wl.high = 0;
3245                         priv->buf_size = 0;
3246                         pfc_priv_num--;
3247                 }
3248                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3249                     pfc_priv_num == 0)
3250                         break;
3251         }
3252
3253         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3254 }
3255
3256 static bool
3257 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3258                           struct hns3_pkt_buf_alloc *buf_alloc)
3259 {
3260 #define COMPENSATE_BUFFER       0x3C00
3261 #define COMPENSATE_HALF_MPS_NUM 5
3262 #define PRIV_WL_GAP             0x1800
3263         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3264         struct hns3_pf *pf = &hns->pf;
3265         uint32_t tc_num = hns3_get_tc_num(hw);
3266         uint32_t half_mps = pf->mps >> 1;
3267         struct hns3_priv_buf *priv;
3268         uint32_t min_rx_priv;
3269         uint32_t rx_priv;
3270         uint8_t i;
3271
3272         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3273         if (tc_num)
3274                 rx_priv = rx_priv / tc_num;
3275
3276         if (tc_num <= NEED_RESERVE_TC_NUM)
3277                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3278
3279         /*
3280          * Minimum value of private buffer in rx direction (min_rx_priv) is
3281          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3282          * buffer if rx_priv is greater than min_rx_priv.
3283          */
3284         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3285                         COMPENSATE_HALF_MPS_NUM * half_mps;
3286         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3287         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3288
3289         if (rx_priv < min_rx_priv)
3290                 return false;
3291
3292         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3293                 priv = &buf_alloc->priv_buf[i];
3294
3295                 priv->enable = 0;
3296                 priv->wl.low = 0;
3297                 priv->wl.high = 0;
3298                 priv->buf_size = 0;
3299
3300                 if (!(hw->hw_tc_map & BIT(i)))
3301                         continue;
3302
3303                 priv->enable = 1;
3304                 priv->buf_size = rx_priv;
3305                 priv->wl.high = rx_priv - pf->dv_buf_size;
3306                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3307         }
3308
3309         buf_alloc->s_buf.buf_size = 0;
3310
3311         return true;
3312 }
3313
3314 /*
3315  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3316  * @hw: pointer to struct hns3_hw
3317  * @buf_alloc: pointer to buffer calculation data
3318  * @return: 0: calculate sucessful, negative: fail
3319  */
3320 static int
3321 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3322 {
3323         /* When DCB is not supported, rx private buffer is not allocated. */
3324         if (!hns3_dev_dcb_supported(hw)) {
3325                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3326                 struct hns3_pf *pf = &hns->pf;
3327                 uint32_t rx_all = pf->pkt_buf_size;
3328
3329                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3330                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3331                         return -ENOMEM;
3332
3333                 return 0;
3334         }
3335
3336         /*
3337          * Try to allocate privated packet buffer for all TCs without share
3338          * buffer.
3339          */
3340         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3341                 return 0;
3342
3343         /*
3344          * Try to allocate privated packet buffer for all TCs with share
3345          * buffer.
3346          */
3347         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3348                 return 0;
3349
3350         /*
3351          * For different application scenes, the enabled port number, TC number
3352          * and no_drop TC number are different. In order to obtain the better
3353          * performance, software could allocate the buffer size and configure
3354          * the waterline by tring to decrease the private buffer size according
3355          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3356          * enabled tc.
3357          */
3358         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3359                 return 0;
3360
3361         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3362                 return 0;
3363
3364         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3365                 return 0;
3366
3367         return -ENOMEM;
3368 }
3369
3370 static int
3371 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3372 {
3373         struct hns3_rx_priv_buff_cmd *req;
3374         struct hns3_cmd_desc desc;
3375         uint32_t buf_size;
3376         int ret;
3377         int i;
3378
3379         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3380         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3381
3382         /* Alloc private buffer TCs */
3383         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3384                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3385
3386                 req->buf_num[i] =
3387                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3388                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3389         }
3390
3391         buf_size = buf_alloc->s_buf.buf_size;
3392         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3393                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3394
3395         ret = hns3_cmd_send(hw, &desc, 1);
3396         if (ret)
3397                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3398
3399         return ret;
3400 }
3401
3402 static int
3403 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3404 {
3405 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3406         struct hns3_rx_priv_wl_buf *req;
3407         struct hns3_priv_buf *priv;
3408         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3409         int i, j;
3410         int ret;
3411
3412         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3413                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3414                                           false);
3415                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3416
3417                 /* The first descriptor set the NEXT bit to 1 */
3418                 if (i == 0)
3419                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3420                 else
3421                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3422
3423                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3424                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3425
3426                         priv = &buf_alloc->priv_buf[idx];
3427                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3428                                                         HNS3_BUF_UNIT_S);
3429                         req->tc_wl[j].high |=
3430                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3431                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3432                                                         HNS3_BUF_UNIT_S);
3433                         req->tc_wl[j].low |=
3434                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3435                 }
3436         }
3437
3438         /* Send 2 descriptor at one time */
3439         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3440         if (ret)
3441                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3442                              ret);
3443         return ret;
3444 }
3445
3446 static int
3447 hns3_common_thrd_config(struct hns3_hw *hw,
3448                         struct hns3_pkt_buf_alloc *buf_alloc)
3449 {
3450 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3451         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3452         struct hns3_rx_com_thrd *req;
3453         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3454         struct hns3_tc_thrd *tc;
3455         int tc_idx;
3456         int i, j;
3457         int ret;
3458
3459         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3460                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3461                                           false);
3462                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3463
3464                 /* The first descriptor set the NEXT bit to 1 */
3465                 if (i == 0)
3466                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3467                 else
3468                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3469
3470                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3471                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3472                         tc = &s_buf->tc_thrd[tc_idx];
3473
3474                         req->com_thrd[j].high =
3475                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3476                         req->com_thrd[j].high |=
3477                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3478                         req->com_thrd[j].low =
3479                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3480                         req->com_thrd[j].low |=
3481                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3482                 }
3483         }
3484
3485         /* Send 2 descriptors at one time */
3486         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3487         if (ret)
3488                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3489
3490         return ret;
3491 }
3492
3493 static int
3494 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3495 {
3496         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3497         struct hns3_rx_com_wl *req;
3498         struct hns3_cmd_desc desc;
3499         int ret;
3500
3501         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3502
3503         req = (struct hns3_rx_com_wl *)desc.data;
3504         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3505         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3506
3507         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3508         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3509
3510         ret = hns3_cmd_send(hw, &desc, 1);
3511         if (ret)
3512                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3513
3514         return ret;
3515 }
3516
3517 int
3518 hns3_buffer_alloc(struct hns3_hw *hw)
3519 {
3520         struct hns3_pkt_buf_alloc pkt_buf;
3521         int ret;
3522
3523         memset(&pkt_buf, 0, sizeof(pkt_buf));
3524         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3525         if (ret) {
3526                 PMD_INIT_LOG(ERR,
3527                              "could not calc tx buffer size for all TCs %d",
3528                              ret);
3529                 return ret;
3530         }
3531
3532         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3533         if (ret) {
3534                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3535                 return ret;
3536         }
3537
3538         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3539         if (ret) {
3540                 PMD_INIT_LOG(ERR,
3541                              "could not calc rx priv buffer size for all TCs %d",
3542                              ret);
3543                 return ret;
3544         }
3545
3546         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3547         if (ret) {
3548                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3549                 return ret;
3550         }
3551
3552         if (hns3_dev_dcb_supported(hw)) {
3553                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3554                 if (ret) {
3555                         PMD_INIT_LOG(ERR,
3556                                      "could not configure rx private waterline %d",
3557                                      ret);
3558                         return ret;
3559                 }
3560
3561                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3562                 if (ret) {
3563                         PMD_INIT_LOG(ERR,
3564                                      "could not configure common threshold %d",
3565                                      ret);
3566                         return ret;
3567                 }
3568         }
3569
3570         ret = hns3_common_wl_config(hw, &pkt_buf);
3571         if (ret)
3572                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3573                              ret);
3574
3575         return ret;
3576 }
3577
3578 static int
3579 hns3_mac_init(struct hns3_hw *hw)
3580 {
3581         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3582         struct hns3_mac *mac = &hw->mac;
3583         struct hns3_pf *pf = &hns->pf;
3584         int ret;
3585
3586         pf->support_sfp_query = true;
3587         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3588         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3589         if (ret) {
3590                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3591                 return ret;
3592         }
3593
3594         mac->link_status = ETH_LINK_DOWN;
3595
3596         return hns3_config_mtu(hw, pf->mps);
3597 }
3598
3599 static int
3600 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3601 {
3602 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3603 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3604 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3605 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3606         int return_status;
3607
3608         if (cmdq_resp) {
3609                 PMD_INIT_LOG(ERR,
3610                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3611                              cmdq_resp);
3612                 return -EIO;
3613         }
3614
3615         switch (resp_code) {
3616         case HNS3_ETHERTYPE_SUCCESS_ADD:
3617         case HNS3_ETHERTYPE_ALREADY_ADD:
3618                 return_status = 0;
3619                 break;
3620         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3621                 PMD_INIT_LOG(ERR,
3622                              "add mac ethertype failed for manager table overflow.");
3623                 return_status = -EIO;
3624                 break;
3625         case HNS3_ETHERTYPE_KEY_CONFLICT:
3626                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3627                 return_status = -EIO;
3628                 break;
3629         default:
3630                 PMD_INIT_LOG(ERR,
3631                              "add mac ethertype failed for undefined, code=%d.",
3632                              resp_code);
3633                 return_status = -EIO;
3634                 break;
3635         }
3636
3637         return return_status;
3638 }
3639
3640 static int
3641 hns3_add_mgr_tbl(struct hns3_hw *hw,
3642                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3643 {
3644         struct hns3_cmd_desc desc;
3645         uint8_t resp_code;
3646         uint16_t retval;
3647         int ret;
3648
3649         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3650         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3651
3652         ret = hns3_cmd_send(hw, &desc, 1);
3653         if (ret) {
3654                 PMD_INIT_LOG(ERR,
3655                              "add mac ethertype failed for cmd_send, ret =%d.",
3656                              ret);
3657                 return ret;
3658         }
3659
3660         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3661         retval = rte_le_to_cpu_16(desc.retval);
3662
3663         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3664 }
3665
3666 static void
3667 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3668                      int *table_item_num)
3669 {
3670         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3671
3672         /*
3673          * In current version, we add one item in management table as below:
3674          * 0x0180C200000E -- LLDP MC address
3675          */
3676         tbl = mgr_table;
3677         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3678         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3679         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3680         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3681         tbl->i_port_bitmap = 0x1;
3682         *table_item_num = 1;
3683 }
3684
3685 static int
3686 hns3_init_mgr_tbl(struct hns3_hw *hw)
3687 {
3688 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3689         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3690         int table_item_num;
3691         int ret;
3692         int i;
3693
3694         memset(mgr_table, 0, sizeof(mgr_table));
3695         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3696         for (i = 0; i < table_item_num; i++) {
3697                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3698                 if (ret) {
3699                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3700                                      ret);
3701                         return ret;
3702                 }
3703         }
3704
3705         return 0;
3706 }
3707
3708 static void
3709 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3710                         bool en_mc, bool en_bc, int vport_id)
3711 {
3712         if (!param)
3713                 return;
3714
3715         memset(param, 0, sizeof(struct hns3_promisc_param));
3716         if (en_uc)
3717                 param->enable = HNS3_PROMISC_EN_UC;
3718         if (en_mc)
3719                 param->enable |= HNS3_PROMISC_EN_MC;
3720         if (en_bc)
3721                 param->enable |= HNS3_PROMISC_EN_BC;
3722         param->vf_id = vport_id;
3723 }
3724
3725 static int
3726 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3727 {
3728         struct hns3_promisc_cfg_cmd *req;
3729         struct hns3_cmd_desc desc;
3730         int ret;
3731
3732         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3733
3734         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3735         req->vf_id = param->vf_id;
3736         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3737             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3738
3739         ret = hns3_cmd_send(hw, &desc, 1);
3740         if (ret)
3741                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3742
3743         return ret;
3744 }
3745
3746 static int
3747 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3748 {
3749         struct hns3_promisc_param param;
3750         bool en_bc_pmc = true;
3751         uint8_t vf_id;
3752
3753         /*
3754          * In current version VF is not supported when PF is driven by DPDK
3755          * driver, the PF-related vf_id is 0, just need to configure parameters
3756          * for vf_id 0.
3757          */
3758         vf_id = 0;
3759
3760         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3761         return hns3_cmd_set_promisc_mode(hw, &param);
3762 }
3763
3764 static int
3765 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3766 {
3767         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3768         struct hns3_pf *pf = &hns->pf;
3769         struct hns3_promisc_param param;
3770         uint16_t func_id;
3771         int ret;
3772
3773         /* func_id 0 is denoted PF, the VFs start from 1 */
3774         for (func_id = 1; func_id < pf->func_num; func_id++) {
3775                 hns3_promisc_param_init(&param, false, false, false, func_id);
3776                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3777                 if (ret)
3778                         return ret;
3779         }
3780
3781         return 0;
3782 }
3783
3784 static int
3785 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3786 {
3787         struct hns3_adapter *hns = dev->data->dev_private;
3788         struct hns3_hw *hw = &hns->hw;
3789         int ret;
3790
3791         rte_spinlock_lock(&hw->lock);
3792         ret = hns3_set_promisc_mode(hw, true, true);
3793         rte_spinlock_unlock(&hw->lock);
3794         if (ret)
3795                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
3796                          ret);
3797
3798         return ret;
3799 }
3800
3801 static int
3802 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3803 {
3804         bool allmulti = dev->data->all_multicast ? true : false;
3805         struct hns3_adapter *hns = dev->data->dev_private;
3806         struct hns3_hw *hw = &hns->hw;
3807         int ret;
3808
3809         /* If now in all_multicast mode, must remain in all_multicast mode. */
3810         rte_spinlock_lock(&hw->lock);
3811         ret = hns3_set_promisc_mode(hw, false, allmulti);
3812         rte_spinlock_unlock(&hw->lock);
3813         if (ret)
3814                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
3815                          ret);
3816
3817         return ret;
3818 }
3819
3820 static int
3821 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3822 {
3823         struct hns3_adapter *hns = dev->data->dev_private;
3824         struct hns3_hw *hw = &hns->hw;
3825         int ret;
3826
3827         if (dev->data->promiscuous)
3828                 return 0;
3829
3830         rte_spinlock_lock(&hw->lock);
3831         ret = hns3_set_promisc_mode(hw, false, true);
3832         rte_spinlock_unlock(&hw->lock);
3833         if (ret)
3834                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
3835                          ret);
3836
3837         return ret;
3838 }
3839
3840 static int
3841 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3842 {
3843         struct hns3_adapter *hns = dev->data->dev_private;
3844         struct hns3_hw *hw = &hns->hw;
3845         int ret;
3846
3847         /* If now in promiscuous mode, must remain in all_multicast mode. */
3848         if (dev->data->promiscuous)
3849                 return 0;
3850
3851         rte_spinlock_lock(&hw->lock);
3852         ret = hns3_set_promisc_mode(hw, false, false);
3853         rte_spinlock_unlock(&hw->lock);
3854         if (ret)
3855                 hns3_err(hw, "Failed to disable allmulticast mode, ret =  %d",
3856                          ret);
3857
3858         return ret;
3859 }
3860
3861 static int
3862 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3863 {
3864         struct hns3_hw *hw = &hns->hw;
3865         bool allmulti = hw->data->all_multicast ? true : false;
3866
3867         if (hw->data->promiscuous)
3868                 return hns3_set_promisc_mode(hw, true, true);
3869
3870         return hns3_set_promisc_mode(hw, false, allmulti);
3871 }
3872
3873 static int
3874 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3875 {
3876         struct hns3_sfp_speed_cmd *resp;
3877         struct hns3_cmd_desc desc;
3878         int ret;
3879
3880         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3881         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3882         ret = hns3_cmd_send(hw, &desc, 1);
3883         if (ret == -EOPNOTSUPP) {
3884                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3885                 return ret;
3886         } else if (ret) {
3887                 hns3_err(hw, "get sfp speed failed %d", ret);
3888                 return ret;
3889         }
3890
3891         *speed = resp->sfp_speed;
3892
3893         return 0;
3894 }
3895
3896 static uint8_t
3897 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3898 {
3899         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3900                 duplex = ETH_LINK_FULL_DUPLEX;
3901
3902         return duplex;
3903 }
3904
3905 static int
3906 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3907 {
3908         struct hns3_mac *mac = &hw->mac;
3909         int ret;
3910
3911         duplex = hns3_check_speed_dup(duplex, speed);
3912         if (mac->link_speed == speed && mac->link_duplex == duplex)
3913                 return 0;
3914
3915         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3916         if (ret)
3917                 return ret;
3918
3919         mac->link_speed = speed;
3920         mac->link_duplex = duplex;
3921
3922         return 0;
3923 }
3924
3925 static int
3926 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3927 {
3928         struct hns3_adapter *hns = eth_dev->data->dev_private;
3929         struct hns3_hw *hw = &hns->hw;
3930         struct hns3_pf *pf = &hns->pf;
3931         uint32_t speed;
3932         int ret;
3933
3934         /* If IMP do not support get SFP/qSFP speed, return directly */
3935         if (!pf->support_sfp_query)
3936                 return 0;
3937
3938         ret = hns3_get_sfp_speed(hw, &speed);
3939         if (ret == -EOPNOTSUPP) {
3940                 pf->support_sfp_query = false;
3941                 return ret;
3942         } else if (ret)
3943                 return ret;
3944
3945         if (speed == ETH_SPEED_NUM_NONE)
3946                 return 0; /* do nothing if no SFP */
3947
3948         /* Config full duplex for SFP */
3949         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3950 }
3951
3952 static int
3953 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3954 {
3955         struct hns3_config_mac_mode_cmd *req;
3956         struct hns3_cmd_desc desc;
3957         uint32_t loop_en = 0;
3958         uint8_t val = 0;
3959         int ret;
3960
3961         req = (struct hns3_config_mac_mode_cmd *)desc.data;
3962
3963         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3964         if (enable)
3965                 val = 1;
3966         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3967         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3968         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3969         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3970         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3971         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3972         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3973         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3974         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3975         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3976         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3977         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3978         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3979         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3980         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3981
3982         ret = hns3_cmd_send(hw, &desc, 1);
3983         if (ret)
3984                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3985
3986         return ret;
3987 }
3988
3989 static int
3990 hns3_get_mac_link_status(struct hns3_hw *hw)
3991 {
3992         struct hns3_link_status_cmd *req;
3993         struct hns3_cmd_desc desc;
3994         int link_status;
3995         int ret;
3996
3997         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3998         ret = hns3_cmd_send(hw, &desc, 1);
3999         if (ret) {
4000                 hns3_err(hw, "get link status cmd failed %d", ret);
4001                 return ETH_LINK_DOWN;
4002         }
4003
4004         req = (struct hns3_link_status_cmd *)desc.data;
4005         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4006
4007         return !!link_status;
4008 }
4009
4010 void
4011 hns3_update_link_status(struct hns3_hw *hw)
4012 {
4013         int state;
4014
4015         state = hns3_get_mac_link_status(hw);
4016         if (state != hw->mac.link_status) {
4017                 hw->mac.link_status = state;
4018                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4019         }
4020 }
4021
4022 static void
4023 hns3_service_handler(void *param)
4024 {
4025         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4026         struct hns3_adapter *hns = eth_dev->data->dev_private;
4027         struct hns3_hw *hw = &hns->hw;
4028
4029         if (!hns3_is_reset_pending(hns)) {
4030                 hns3_update_speed_duplex(eth_dev);
4031                 hns3_update_link_status(hw);
4032         } else
4033                 hns3_warn(hw, "Cancel the query when reset is pending");
4034
4035         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4036 }
4037
4038 static int
4039 hns3_init_hardware(struct hns3_adapter *hns)
4040 {
4041         struct hns3_hw *hw = &hns->hw;
4042         int ret;
4043
4044         ret = hns3_map_tqp(hw);
4045         if (ret) {
4046                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4047                 return ret;
4048         }
4049
4050         ret = hns3_init_umv_space(hw);
4051         if (ret) {
4052                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4053                 return ret;
4054         }
4055
4056         ret = hns3_mac_init(hw);
4057         if (ret) {
4058                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4059                 goto err_mac_init;
4060         }
4061
4062         ret = hns3_init_mgr_tbl(hw);
4063         if (ret) {
4064                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4065                 goto err_mac_init;
4066         }
4067
4068         ret = hns3_set_promisc_mode(hw, false, false);
4069         if (ret) {
4070                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
4071                 goto err_mac_init;
4072         }
4073
4074         ret = hns3_clear_all_vfs_promisc_mode(hw);
4075         if (ret) {
4076                 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
4077                              ret);
4078                 goto err_mac_init;
4079         }
4080
4081         ret = hns3_init_vlan_config(hns);
4082         if (ret) {
4083                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4084                 goto err_mac_init;
4085         }
4086
4087         ret = hns3_dcb_init(hw);
4088         if (ret) {
4089                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4090                 goto err_mac_init;
4091         }
4092
4093         ret = hns3_init_fd_config(hns);
4094         if (ret) {
4095                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4096                 goto err_mac_init;
4097         }
4098
4099         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4100         if (ret) {
4101                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4102                 goto err_mac_init;
4103         }
4104
4105         ret = hns3_config_gro(hw, false);
4106         if (ret) {
4107                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4108                 goto err_mac_init;
4109         }
4110
4111         /*
4112          * In the initialization clearing the all hardware mapping relationship
4113          * configurations between queues and interrupt vectors is needed, so
4114          * some error caused by the residual configurations, such as the
4115          * unexpected interrupt, can be avoid.
4116          */
4117         ret = hns3_init_ring_with_vector(hw);
4118         if (ret) {
4119                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4120                 goto err_mac_init;
4121         }
4122
4123         return 0;
4124
4125 err_mac_init:
4126         hns3_uninit_umv_space(hw);
4127         return ret;
4128 }
4129
4130 static int
4131 hns3_init_pf(struct rte_eth_dev *eth_dev)
4132 {
4133         struct rte_device *dev = eth_dev->device;
4134         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4135         struct hns3_adapter *hns = eth_dev->data->dev_private;
4136         struct hns3_hw *hw = &hns->hw;
4137         int ret;
4138
4139         PMD_INIT_FUNC_TRACE();
4140
4141         /* Get hardware io base address from pcie BAR2 IO space */
4142         hw->io_base = pci_dev->mem_resource[2].addr;
4143
4144         /* Firmware command queue initialize */
4145         ret = hns3_cmd_init_queue(hw);
4146         if (ret) {
4147                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4148                 goto err_cmd_init_queue;
4149         }
4150
4151         hns3_clear_all_event_cause(hw);
4152
4153         /* Firmware command initialize */
4154         ret = hns3_cmd_init(hw);
4155         if (ret) {
4156                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4157                 goto err_cmd_init;
4158         }
4159
4160         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4161                                          hns3_interrupt_handler,
4162                                          eth_dev);
4163         if (ret) {
4164                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4165                 goto err_intr_callback_register;
4166         }
4167
4168         /* Enable interrupt */
4169         rte_intr_enable(&pci_dev->intr_handle);
4170         hns3_pf_enable_irq0(hw);
4171
4172         /* Get configuration */
4173         ret = hns3_get_configuration(hw);
4174         if (ret) {
4175                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4176                 goto err_get_config;
4177         }
4178
4179         ret = hns3_init_hardware(hns);
4180         if (ret) {
4181                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4182                 goto err_get_config;
4183         }
4184
4185         /* Initialize flow director filter list & hash */
4186         ret = hns3_fdir_filter_init(hns);
4187         if (ret) {
4188                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4189                 goto err_hw_init;
4190         }
4191
4192         hns3_set_default_rss_args(hw);
4193
4194         ret = hns3_enable_hw_error_intr(hns, true);
4195         if (ret) {
4196                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4197                              ret);
4198                 goto err_fdir;
4199         }
4200
4201         return 0;
4202
4203 err_fdir:
4204         hns3_fdir_filter_uninit(hns);
4205 err_hw_init:
4206         hns3_uninit_umv_space(hw);
4207
4208 err_get_config:
4209         hns3_pf_disable_irq0(hw);
4210         rte_intr_disable(&pci_dev->intr_handle);
4211         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4212                              eth_dev);
4213 err_intr_callback_register:
4214 err_cmd_init:
4215         hns3_cmd_uninit(hw);
4216         hns3_cmd_destroy_queue(hw);
4217 err_cmd_init_queue:
4218         hw->io_base = NULL;
4219
4220         return ret;
4221 }
4222
4223 static void
4224 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4225 {
4226         struct hns3_adapter *hns = eth_dev->data->dev_private;
4227         struct rte_device *dev = eth_dev->device;
4228         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4229         struct hns3_hw *hw = &hns->hw;
4230
4231         PMD_INIT_FUNC_TRACE();
4232
4233         hns3_enable_hw_error_intr(hns, false);
4234         hns3_rss_uninit(hns);
4235         hns3_fdir_filter_uninit(hns);
4236         hns3_uninit_umv_space(hw);
4237         hns3_pf_disable_irq0(hw);
4238         rte_intr_disable(&pci_dev->intr_handle);
4239         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4240                              eth_dev);
4241         hns3_cmd_uninit(hw);
4242         hns3_cmd_destroy_queue(hw);
4243         hw->io_base = NULL;
4244 }
4245
4246 static int
4247 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4248 {
4249         struct hns3_hw *hw = &hns->hw;
4250         int ret;
4251
4252         ret = hns3_dcb_cfg_update(hns);
4253         if (ret)
4254                 return ret;
4255
4256         /* Enable queues */
4257         ret = hns3_start_queues(hns, reset_queue);
4258         if (ret) {
4259                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4260                 return ret;
4261         }
4262
4263         /* Enable MAC */
4264         ret = hns3_cfg_mac_mode(hw, true);
4265         if (ret) {
4266                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4267                 goto err_config_mac_mode;
4268         }
4269         return 0;
4270
4271 err_config_mac_mode:
4272         hns3_stop_queues(hns, true);
4273         return ret;
4274 }
4275
4276 static int
4277 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4278 {
4279         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4280         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4281         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4282         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4283         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4284         uint32_t intr_vector;
4285         uint16_t q_id;
4286         int ret;
4287
4288         if (dev->data->dev_conf.intr_conf.rxq == 0)
4289                 return 0;
4290
4291         /* disable uio/vfio intr/eventfd mapping */
4292         rte_intr_disable(intr_handle);
4293
4294         /* check and configure queue intr-vector mapping */
4295         if (rte_intr_cap_multiple(intr_handle) ||
4296             !RTE_ETH_DEV_SRIOV(dev).active) {
4297                 intr_vector = hw->used_rx_queues;
4298                 /* creates event fd for each intr vector when MSIX is used */
4299                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4300                         return -EINVAL;
4301         }
4302         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4303                 intr_handle->intr_vec =
4304                         rte_zmalloc("intr_vec",
4305                                     hw->used_rx_queues * sizeof(int), 0);
4306                 if (intr_handle->intr_vec == NULL) {
4307                         hns3_err(hw, "Failed to allocate %d rx_queues"
4308                                      " intr_vec", hw->used_rx_queues);
4309                         ret = -ENOMEM;
4310                         goto alloc_intr_vec_error;
4311                 }
4312         }
4313
4314         if (rte_intr_allow_others(intr_handle)) {
4315                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4316                 base = RTE_INTR_VEC_RXTX_OFFSET;
4317         }
4318         if (rte_intr_dp_is_en(intr_handle)) {
4319                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4320                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4321                                                          HNS3_RING_TYPE_RX,
4322                                                          q_id);
4323                         if (ret)
4324                                 goto bind_vector_error;
4325                         intr_handle->intr_vec[q_id] = vec;
4326                         if (vec < base + intr_handle->nb_efd - 1)
4327                                 vec++;
4328                 }
4329         }
4330         rte_intr_enable(intr_handle);
4331         return 0;
4332
4333 bind_vector_error:
4334         rte_intr_efd_disable(intr_handle);
4335         if (intr_handle->intr_vec) {
4336                 free(intr_handle->intr_vec);
4337                 intr_handle->intr_vec = NULL;
4338         }
4339         return ret;
4340 alloc_intr_vec_error:
4341         rte_intr_efd_disable(intr_handle);
4342         return ret;
4343 }
4344
4345 static int
4346 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4347 {
4348         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4349         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4350         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4351         uint16_t q_id;
4352         int ret;
4353
4354         if (dev->data->dev_conf.intr_conf.rxq == 0)
4355                 return 0;
4356
4357         if (rte_intr_dp_is_en(intr_handle)) {
4358                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4359                         ret = hns3_bind_ring_with_vector(hw,
4360                                         intr_handle->intr_vec[q_id], true,
4361                                         HNS3_RING_TYPE_RX, q_id);
4362                         if (ret)
4363                                 return ret;
4364                 }
4365         }
4366
4367         return 0;
4368 }
4369
4370 static void
4371 hns3_restore_filter(struct rte_eth_dev *dev)
4372 {
4373         hns3_restore_rss_filter(dev);
4374 }
4375
4376 static int
4377 hns3_dev_start(struct rte_eth_dev *dev)
4378 {
4379         struct hns3_adapter *hns = dev->data->dev_private;
4380         struct hns3_hw *hw = &hns->hw;
4381         int ret;
4382
4383         PMD_INIT_FUNC_TRACE();
4384         if (rte_atomic16_read(&hw->reset.resetting))
4385                 return -EBUSY;
4386
4387         rte_spinlock_lock(&hw->lock);
4388         hw->adapter_state = HNS3_NIC_STARTING;
4389
4390         ret = hns3_do_start(hns, true);
4391         if (ret) {
4392                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4393                 rte_spinlock_unlock(&hw->lock);
4394                 return ret;
4395         }
4396         ret = hns3_map_rx_interrupt(dev);
4397         if (ret) {
4398                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4399                 rte_spinlock_unlock(&hw->lock);
4400                 return ret;
4401         }
4402
4403         hw->adapter_state = HNS3_NIC_STARTED;
4404         rte_spinlock_unlock(&hw->lock);
4405
4406         hns3_set_rxtx_function(dev);
4407         hns3_mp_req_start_rxtx(dev);
4408         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4409
4410         hns3_restore_filter(dev);
4411
4412         /* Enable interrupt of all rx queues before enabling queues */
4413         hns3_dev_all_rx_queue_intr_enable(hw, true);
4414         /*
4415          * When finished the initialization, enable queues to receive/transmit
4416          * packets.
4417          */
4418         hns3_enable_all_queues(hw, true);
4419
4420         hns3_info(hw, "hns3 dev start successful!");
4421         return 0;
4422 }
4423
4424 static int
4425 hns3_do_stop(struct hns3_adapter *hns)
4426 {
4427         struct hns3_hw *hw = &hns->hw;
4428         bool reset_queue;
4429         int ret;
4430
4431         ret = hns3_cfg_mac_mode(hw, false);
4432         if (ret)
4433                 return ret;
4434         hw->mac.link_status = ETH_LINK_DOWN;
4435
4436         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4437                 hns3_configure_all_mac_addr(hns, true);
4438                 reset_queue = true;
4439         } else
4440                 reset_queue = false;
4441         hw->mac.default_addr_setted = false;
4442         return hns3_stop_queues(hns, reset_queue);
4443 }
4444
4445 static void
4446 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4447 {
4448         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4449         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4450         struct hns3_adapter *hns = dev->data->dev_private;
4451         struct hns3_hw *hw = &hns->hw;
4452         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4453         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4454         uint16_t q_id;
4455
4456         if (dev->data->dev_conf.intr_conf.rxq == 0)
4457                 return;
4458
4459         /* unmap the ring with vector */
4460         if (rte_intr_allow_others(intr_handle)) {
4461                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4462                 base = RTE_INTR_VEC_RXTX_OFFSET;
4463         }
4464         if (rte_intr_dp_is_en(intr_handle)) {
4465                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4466                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4467                                                          HNS3_RING_TYPE_RX,
4468                                                          q_id);
4469                         if (vec < base + intr_handle->nb_efd - 1)
4470                                 vec++;
4471                 }
4472         }
4473         /* Clean datapath event and queue/vec mapping */
4474         rte_intr_efd_disable(intr_handle);
4475         if (intr_handle->intr_vec) {
4476                 rte_free(intr_handle->intr_vec);
4477                 intr_handle->intr_vec = NULL;
4478         }
4479 }
4480
4481 static void
4482 hns3_dev_stop(struct rte_eth_dev *dev)
4483 {
4484         struct hns3_adapter *hns = dev->data->dev_private;
4485         struct hns3_hw *hw = &hns->hw;
4486
4487         PMD_INIT_FUNC_TRACE();
4488
4489         hw->adapter_state = HNS3_NIC_STOPPING;
4490         hns3_set_rxtx_function(dev);
4491         rte_wmb();
4492         /* Disable datapath on secondary process. */
4493         hns3_mp_req_stop_rxtx(dev);
4494         /* Prevent crashes when queues are still in use. */
4495         rte_delay_ms(hw->tqps_num);
4496
4497         rte_spinlock_lock(&hw->lock);
4498         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4499                 hns3_do_stop(hns);
4500                 hns3_unmap_rx_interrupt(dev);
4501                 hns3_dev_release_mbufs(hns);
4502                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4503         }
4504         rte_eal_alarm_cancel(hns3_service_handler, dev);
4505         rte_spinlock_unlock(&hw->lock);
4506 }
4507
4508 static void
4509 hns3_dev_close(struct rte_eth_dev *eth_dev)
4510 {
4511         struct hns3_adapter *hns = eth_dev->data->dev_private;
4512         struct hns3_hw *hw = &hns->hw;
4513
4514         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4515                 rte_free(eth_dev->process_private);
4516                 eth_dev->process_private = NULL;
4517                 return;
4518         }
4519
4520         if (hw->adapter_state == HNS3_NIC_STARTED)
4521                 hns3_dev_stop(eth_dev);
4522
4523         hw->adapter_state = HNS3_NIC_CLOSING;
4524         hns3_reset_abort(hns);
4525         hw->adapter_state = HNS3_NIC_CLOSED;
4526
4527         hns3_configure_all_mc_mac_addr(hns, true);
4528         hns3_remove_all_vlan_table(hns);
4529         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4530         hns3_uninit_pf(eth_dev);
4531         hns3_free_all_queues(eth_dev);
4532         rte_free(hw->reset.wait_data);
4533         rte_free(eth_dev->process_private);
4534         eth_dev->process_private = NULL;
4535         hns3_mp_uninit_primary();
4536         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4537 }
4538
4539 static int
4540 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4541 {
4542         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4543         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4544
4545         fc_conf->pause_time = pf->pause_time;
4546
4547         /* return fc current mode */
4548         switch (hw->current_mode) {
4549         case HNS3_FC_FULL:
4550                 fc_conf->mode = RTE_FC_FULL;
4551                 break;
4552         case HNS3_FC_TX_PAUSE:
4553                 fc_conf->mode = RTE_FC_TX_PAUSE;
4554                 break;
4555         case HNS3_FC_RX_PAUSE:
4556                 fc_conf->mode = RTE_FC_RX_PAUSE;
4557                 break;
4558         case HNS3_FC_NONE:
4559         default:
4560                 fc_conf->mode = RTE_FC_NONE;
4561                 break;
4562         }
4563
4564         return 0;
4565 }
4566
4567 static void
4568 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4569 {
4570         switch (mode) {
4571         case RTE_FC_NONE:
4572                 hw->requested_mode = HNS3_FC_NONE;
4573                 break;
4574         case RTE_FC_RX_PAUSE:
4575                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4576                 break;
4577         case RTE_FC_TX_PAUSE:
4578                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4579                 break;
4580         case RTE_FC_FULL:
4581                 hw->requested_mode = HNS3_FC_FULL;
4582                 break;
4583         default:
4584                 hw->requested_mode = HNS3_FC_NONE;
4585                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4586                           "configured to RTE_FC_NONE", mode);
4587                 break;
4588         }
4589 }
4590
4591 static int
4592 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4593 {
4594         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4595         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4596         int ret;
4597
4598         if (fc_conf->high_water || fc_conf->low_water ||
4599             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4600                 hns3_err(hw, "Unsupported flow control settings specified, "
4601                          "high_water(%u), low_water(%u), send_xon(%u) and "
4602                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4603                          fc_conf->high_water, fc_conf->low_water,
4604                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4605                 return -EINVAL;
4606         }
4607         if (fc_conf->autoneg) {
4608                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4609                 return -EINVAL;
4610         }
4611         if (!fc_conf->pause_time) {
4612                 hns3_err(hw, "Invalid pause time %d setting.",
4613                          fc_conf->pause_time);
4614                 return -EINVAL;
4615         }
4616
4617         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4618             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4619                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4620                          "current_fc_status = %d", hw->current_fc_status);
4621                 return -EOPNOTSUPP;
4622         }
4623
4624         hns3_get_fc_mode(hw, fc_conf->mode);
4625         if (hw->requested_mode == hw->current_mode &&
4626             pf->pause_time == fc_conf->pause_time)
4627                 return 0;
4628
4629         rte_spinlock_lock(&hw->lock);
4630         ret = hns3_fc_enable(dev, fc_conf);
4631         rte_spinlock_unlock(&hw->lock);
4632
4633         return ret;
4634 }
4635
4636 static int
4637 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4638                             struct rte_eth_pfc_conf *pfc_conf)
4639 {
4640         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4641         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4642         uint8_t priority;
4643         int ret;
4644
4645         if (!hns3_dev_dcb_supported(hw)) {
4646                 hns3_err(hw, "This port does not support dcb configurations.");
4647                 return -EOPNOTSUPP;
4648         }
4649
4650         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4651             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4652                 hns3_err(hw, "Unsupported flow control settings specified, "
4653                          "high_water(%u), low_water(%u), send_xon(%u) and "
4654                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4655                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4656                          pfc_conf->fc.send_xon,
4657                          pfc_conf->fc.mac_ctrl_frame_fwd);
4658                 return -EINVAL;
4659         }
4660         if (pfc_conf->fc.autoneg) {
4661                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4662                 return -EINVAL;
4663         }
4664         if (pfc_conf->fc.pause_time == 0) {
4665                 hns3_err(hw, "Invalid pause time %d setting.",
4666                          pfc_conf->fc.pause_time);
4667                 return -EINVAL;
4668         }
4669
4670         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4671             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4672                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4673                              "current_fc_status = %d", hw->current_fc_status);
4674                 return -EOPNOTSUPP;
4675         }
4676
4677         priority = pfc_conf->priority;
4678         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4679         if (hw->dcb_info.pfc_en & BIT(priority) &&
4680             hw->requested_mode == hw->current_mode &&
4681             pfc_conf->fc.pause_time == pf->pause_time)
4682                 return 0;
4683
4684         rte_spinlock_lock(&hw->lock);
4685         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4686         rte_spinlock_unlock(&hw->lock);
4687
4688         return ret;
4689 }
4690
4691 static int
4692 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4693 {
4694         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4695         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4696         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4697         int i;
4698
4699         rte_spinlock_lock(&hw->lock);
4700         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4701                 dcb_info->nb_tcs = pf->local_max_tc;
4702         else
4703                 dcb_info->nb_tcs = 1;
4704
4705         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4706                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4707         for (i = 0; i < dcb_info->nb_tcs; i++)
4708                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4709
4710         for (i = 0; i < hw->num_tc; i++) {
4711                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4712                 dcb_info->tc_queue.tc_txq[0][i].base =
4713                                                 hw->tc_queue[i].tqp_offset;
4714                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4715                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4716                                                 hw->tc_queue[i].tqp_count;
4717         }
4718         rte_spinlock_unlock(&hw->lock);
4719
4720         return 0;
4721 }
4722
4723 static int
4724 hns3_reinit_dev(struct hns3_adapter *hns)
4725 {
4726         struct hns3_hw *hw = &hns->hw;
4727         int ret;
4728
4729         ret = hns3_cmd_init(hw);
4730         if (ret) {
4731                 hns3_err(hw, "Failed to init cmd: %d", ret);
4732                 return ret;
4733         }
4734
4735         ret = hns3_reset_all_queues(hns);
4736         if (ret) {
4737                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4738                 return ret;
4739         }
4740
4741         ret = hns3_init_hardware(hns);
4742         if (ret) {
4743                 hns3_err(hw, "Failed to init hardware: %d", ret);
4744                 return ret;
4745         }
4746
4747         ret = hns3_enable_hw_error_intr(hns, true);
4748         if (ret) {
4749                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4750                              ret);
4751                 return ret;
4752         }
4753         hns3_info(hw, "Reset done, driver initialization finished.");
4754
4755         return 0;
4756 }
4757
4758 static bool
4759 is_pf_reset_done(struct hns3_hw *hw)
4760 {
4761         uint32_t val, reg, reg_bit;
4762
4763         switch (hw->reset.level) {
4764         case HNS3_IMP_RESET:
4765                 reg = HNS3_GLOBAL_RESET_REG;
4766                 reg_bit = HNS3_IMP_RESET_BIT;
4767                 break;
4768         case HNS3_GLOBAL_RESET:
4769                 reg = HNS3_GLOBAL_RESET_REG;
4770                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4771                 break;
4772         case HNS3_FUNC_RESET:
4773                 reg = HNS3_FUN_RST_ING;
4774                 reg_bit = HNS3_FUN_RST_ING_B;
4775                 break;
4776         case HNS3_FLR_RESET:
4777         default:
4778                 hns3_err(hw, "Wait for unsupported reset level: %d",
4779                          hw->reset.level);
4780                 return true;
4781         }
4782         val = hns3_read_dev(hw, reg);
4783         if (hns3_get_bit(val, reg_bit))
4784                 return false;
4785         else
4786                 return true;
4787 }
4788
4789 bool
4790 hns3_is_reset_pending(struct hns3_adapter *hns)
4791 {
4792         struct hns3_hw *hw = &hns->hw;
4793         enum hns3_reset_level reset;
4794
4795         hns3_check_event_cause(hns, NULL);
4796         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4797         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4798                 hns3_warn(hw, "High level reset %d is pending", reset);
4799                 return true;
4800         }
4801         reset = hns3_get_reset_level(hns, &hw->reset.request);
4802         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4803                 hns3_warn(hw, "High level reset %d is request", reset);
4804                 return true;
4805         }
4806         return false;
4807 }
4808
4809 static int
4810 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4811 {
4812         struct hns3_hw *hw = &hns->hw;
4813         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4814         struct timeval tv;
4815
4816         if (wait_data->result == HNS3_WAIT_SUCCESS)
4817                 return 0;
4818         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4819                 gettimeofday(&tv, NULL);
4820                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4821                           tv.tv_sec, tv.tv_usec);
4822                 return -ETIME;
4823         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4824                 return -EAGAIN;
4825
4826         wait_data->hns = hns;
4827         wait_data->check_completion = is_pf_reset_done;
4828         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4829                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4830         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4831         wait_data->count = HNS3_RESET_WAIT_CNT;
4832         wait_data->result = HNS3_WAIT_REQUEST;
4833         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4834         return -EAGAIN;
4835 }
4836
4837 static int
4838 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4839 {
4840         struct hns3_cmd_desc desc;
4841         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4842
4843         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4844         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4845         req->fun_reset_vfid = func_id;
4846
4847         return hns3_cmd_send(hw, &desc, 1);
4848 }
4849
4850 static int
4851 hns3_imp_reset_cmd(struct hns3_hw *hw)
4852 {
4853         struct hns3_cmd_desc desc;
4854
4855         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4856         desc.data[0] = 0xeedd;
4857
4858         return hns3_cmd_send(hw, &desc, 1);
4859 }
4860
4861 static void
4862 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4863 {
4864         struct hns3_hw *hw = &hns->hw;
4865         struct timeval tv;
4866         uint32_t val;
4867
4868         gettimeofday(&tv, NULL);
4869         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4870             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4871                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4872                           tv.tv_sec, tv.tv_usec);
4873                 return;
4874         }
4875
4876         switch (reset_level) {
4877         case HNS3_IMP_RESET:
4878                 hns3_imp_reset_cmd(hw);
4879                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4880                           tv.tv_sec, tv.tv_usec);
4881                 break;
4882         case HNS3_GLOBAL_RESET:
4883                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4884                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4885                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4886                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4887                           tv.tv_sec, tv.tv_usec);
4888                 break;
4889         case HNS3_FUNC_RESET:
4890                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4891                           tv.tv_sec, tv.tv_usec);
4892                 /* schedule again to check later */
4893                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4894                 hns3_schedule_reset(hns);
4895                 break;
4896         default:
4897                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4898                 return;
4899         }
4900         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4901 }
4902
4903 static enum hns3_reset_level
4904 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4905 {
4906         struct hns3_hw *hw = &hns->hw;
4907         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4908
4909         /* Return the highest priority reset level amongst all */
4910         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4911                 reset_level = HNS3_IMP_RESET;
4912         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4913                 reset_level = HNS3_GLOBAL_RESET;
4914         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4915                 reset_level = HNS3_FUNC_RESET;
4916         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4917                 reset_level = HNS3_FLR_RESET;
4918
4919         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4920                 return HNS3_NONE_RESET;
4921
4922         return reset_level;
4923 }
4924
4925 static int
4926 hns3_prepare_reset(struct hns3_adapter *hns)
4927 {
4928         struct hns3_hw *hw = &hns->hw;
4929         uint32_t reg_val;
4930         int ret;
4931
4932         switch (hw->reset.level) {
4933         case HNS3_FUNC_RESET:
4934                 ret = hns3_func_reset_cmd(hw, 0);
4935                 if (ret)
4936                         return ret;
4937
4938                 /*
4939                  * After performaning pf reset, it is not necessary to do the
4940                  * mailbox handling or send any command to firmware, because
4941                  * any mailbox handling or command to firmware is only valid
4942                  * after hns3_cmd_init is called.
4943                  */
4944                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4945                 hw->reset.stats.request_cnt++;
4946                 break;
4947         case HNS3_IMP_RESET:
4948                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4949                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4950                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4951                 break;
4952         default:
4953                 break;
4954         }
4955         return 0;
4956 }
4957
4958 static int
4959 hns3_set_rst_done(struct hns3_hw *hw)
4960 {
4961         struct hns3_pf_rst_done_cmd *req;
4962         struct hns3_cmd_desc desc;
4963
4964         req = (struct hns3_pf_rst_done_cmd *)desc.data;
4965         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4966         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4967         return hns3_cmd_send(hw, &desc, 1);
4968 }
4969
4970 static int
4971 hns3_stop_service(struct hns3_adapter *hns)
4972 {
4973         struct hns3_hw *hw = &hns->hw;
4974         struct rte_eth_dev *eth_dev;
4975
4976         eth_dev = &rte_eth_devices[hw->data->port_id];
4977         if (hw->adapter_state == HNS3_NIC_STARTED)
4978                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4979         hw->mac.link_status = ETH_LINK_DOWN;
4980
4981         hns3_set_rxtx_function(eth_dev);
4982         rte_wmb();
4983         /* Disable datapath on secondary process. */
4984         hns3_mp_req_stop_rxtx(eth_dev);
4985         rte_delay_ms(hw->tqps_num);
4986
4987         rte_spinlock_lock(&hw->lock);
4988         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4989             hw->adapter_state == HNS3_NIC_STOPPING) {
4990                 hns3_do_stop(hns);
4991                 hw->reset.mbuf_deferred_free = true;
4992         } else
4993                 hw->reset.mbuf_deferred_free = false;
4994
4995         /*
4996          * It is cumbersome for hardware to pick-and-choose entries for deletion
4997          * from table space. Hence, for function reset software intervention is
4998          * required to delete the entries
4999          */
5000         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5001                 hns3_configure_all_mc_mac_addr(hns, true);
5002         rte_spinlock_unlock(&hw->lock);
5003
5004         return 0;
5005 }
5006
5007 static int
5008 hns3_start_service(struct hns3_adapter *hns)
5009 {
5010         struct hns3_hw *hw = &hns->hw;
5011         struct rte_eth_dev *eth_dev;
5012
5013         if (hw->reset.level == HNS3_IMP_RESET ||
5014             hw->reset.level == HNS3_GLOBAL_RESET)
5015                 hns3_set_rst_done(hw);
5016         eth_dev = &rte_eth_devices[hw->data->port_id];
5017         hns3_set_rxtx_function(eth_dev);
5018         hns3_mp_req_start_rxtx(eth_dev);
5019         if (hw->adapter_state == HNS3_NIC_STARTED) {
5020                 hns3_service_handler(eth_dev);
5021
5022                 /* Enable interrupt of all rx queues before enabling queues */
5023                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5024                 /*
5025                  * When finished the initialization, enable queues to receive
5026                  * and transmit packets.
5027                  */
5028                 hns3_enable_all_queues(hw, true);
5029         }
5030
5031         return 0;
5032 }
5033
5034 static int
5035 hns3_restore_conf(struct hns3_adapter *hns)
5036 {
5037         struct hns3_hw *hw = &hns->hw;
5038         int ret;
5039
5040         ret = hns3_configure_all_mac_addr(hns, false);
5041         if (ret)
5042                 return ret;
5043
5044         ret = hns3_configure_all_mc_mac_addr(hns, false);
5045         if (ret)
5046                 goto err_mc_mac;
5047
5048         ret = hns3_dev_promisc_restore(hns);
5049         if (ret)
5050                 goto err_promisc;
5051
5052         ret = hns3_restore_vlan_table(hns);
5053         if (ret)
5054                 goto err_promisc;
5055
5056         ret = hns3_restore_vlan_conf(hns);
5057         if (ret)
5058                 goto err_promisc;
5059
5060         ret = hns3_restore_all_fdir_filter(hns);
5061         if (ret)
5062                 goto err_promisc;
5063
5064         ret = hns3_restore_rx_interrupt(hw);
5065         if (ret)
5066                 goto err_promisc;
5067
5068         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5069                 ret = hns3_do_start(hns, false);
5070                 if (ret)
5071                         goto err_promisc;
5072                 hns3_info(hw, "hns3 dev restart successful!");
5073         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5074                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5075         return 0;
5076
5077 err_promisc:
5078         hns3_configure_all_mc_mac_addr(hns, true);
5079 err_mc_mac:
5080         hns3_configure_all_mac_addr(hns, true);
5081         return ret;
5082 }
5083
5084 static void
5085 hns3_reset_service(void *param)
5086 {
5087         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5088         struct hns3_hw *hw = &hns->hw;
5089         enum hns3_reset_level reset_level;
5090         struct timeval tv_delta;
5091         struct timeval tv_start;
5092         struct timeval tv;
5093         uint64_t msec;
5094         int ret;
5095
5096         /*
5097          * The interrupt is not triggered within the delay time.
5098          * The interrupt may have been lost. It is necessary to handle
5099          * the interrupt to recover from the error.
5100          */
5101         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5102                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5103                 hns3_err(hw, "Handling interrupts in delayed tasks");
5104                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5105                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5106                 if (reset_level == HNS3_NONE_RESET) {
5107                         hns3_err(hw, "No reset level is set, try IMP reset");
5108                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5109                 }
5110         }
5111         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5112
5113         /*
5114          * Check if there is any ongoing reset in the hardware. This status can
5115          * be checked from reset_pending. If there is then, we need to wait for
5116          * hardware to complete reset.
5117          *    a. If we are able to figure out in reasonable time that hardware
5118          *       has fully resetted then, we can proceed with driver, client
5119          *       reset.
5120          *    b. else, we can come back later to check this status so re-sched
5121          *       now.
5122          */
5123         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5124         if (reset_level != HNS3_NONE_RESET) {
5125                 gettimeofday(&tv_start, NULL);
5126                 ret = hns3_reset_process(hns, reset_level);
5127                 gettimeofday(&tv, NULL);
5128                 timersub(&tv, &tv_start, &tv_delta);
5129                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5130                        tv_delta.tv_usec / USEC_PER_MSEC;
5131                 if (msec > HNS3_RESET_PROCESS_MS)
5132                         hns3_err(hw, "%d handle long time delta %" PRIx64
5133                                      " ms time=%ld.%.6ld",
5134                                  hw->reset.level, msec,
5135                                  tv.tv_sec, tv.tv_usec);
5136                 if (ret == -EAGAIN)
5137                         return;
5138         }
5139
5140         /* Check if we got any *new* reset requests to be honored */
5141         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5142         if (reset_level != HNS3_NONE_RESET)
5143                 hns3_msix_process(hns, reset_level);
5144 }
5145
5146 static const struct eth_dev_ops hns3_eth_dev_ops = {
5147         .dev_start          = hns3_dev_start,
5148         .dev_stop           = hns3_dev_stop,
5149         .dev_close          = hns3_dev_close,
5150         .promiscuous_enable = hns3_dev_promiscuous_enable,
5151         .promiscuous_disable = hns3_dev_promiscuous_disable,
5152         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5153         .allmulticast_disable = hns3_dev_allmulticast_disable,
5154         .mtu_set            = hns3_dev_mtu_set,
5155         .stats_get          = hns3_stats_get,
5156         .stats_reset        = hns3_stats_reset,
5157         .xstats_get         = hns3_dev_xstats_get,
5158         .xstats_get_names   = hns3_dev_xstats_get_names,
5159         .xstats_reset       = hns3_dev_xstats_reset,
5160         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5161         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5162         .dev_infos_get          = hns3_dev_infos_get,
5163         .fw_version_get         = hns3_fw_version_get,
5164         .rx_queue_setup         = hns3_rx_queue_setup,
5165         .tx_queue_setup         = hns3_tx_queue_setup,
5166         .rx_queue_release       = hns3_dev_rx_queue_release,
5167         .tx_queue_release       = hns3_dev_tx_queue_release,
5168         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5169         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5170         .dev_configure          = hns3_dev_configure,
5171         .flow_ctrl_get          = hns3_flow_ctrl_get,
5172         .flow_ctrl_set          = hns3_flow_ctrl_set,
5173         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5174         .mac_addr_add           = hns3_add_mac_addr,
5175         .mac_addr_remove        = hns3_remove_mac_addr,
5176         .mac_addr_set           = hns3_set_default_mac_addr,
5177         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5178         .link_update            = hns3_dev_link_update,
5179         .rss_hash_update        = hns3_dev_rss_hash_update,
5180         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5181         .reta_update            = hns3_dev_rss_reta_update,
5182         .reta_query             = hns3_dev_rss_reta_query,
5183         .filter_ctrl            = hns3_dev_filter_ctrl,
5184         .vlan_filter_set        = hns3_vlan_filter_set,
5185         .vlan_tpid_set          = hns3_vlan_tpid_set,
5186         .vlan_offload_set       = hns3_vlan_offload_set,
5187         .vlan_pvid_set          = hns3_vlan_pvid_set,
5188         .get_reg                = hns3_get_regs,
5189         .get_dcb_info           = hns3_get_dcb_info,
5190         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5191 };
5192
5193 static const struct hns3_reset_ops hns3_reset_ops = {
5194         .reset_service       = hns3_reset_service,
5195         .stop_service        = hns3_stop_service,
5196         .prepare_reset       = hns3_prepare_reset,
5197         .wait_hardware_ready = hns3_wait_hardware_ready,
5198         .reinit_dev          = hns3_reinit_dev,
5199         .restore_conf        = hns3_restore_conf,
5200         .start_service       = hns3_start_service,
5201 };
5202
5203 static int
5204 hns3_dev_init(struct rte_eth_dev *eth_dev)
5205 {
5206         struct rte_device *dev = eth_dev->device;
5207         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5208         struct hns3_adapter *hns = eth_dev->data->dev_private;
5209         struct hns3_hw *hw = &hns->hw;
5210         uint16_t device_id = pci_dev->id.device_id;
5211         int ret;
5212
5213         PMD_INIT_FUNC_TRACE();
5214         eth_dev->process_private = (struct hns3_process_private *)
5215             rte_zmalloc_socket("hns3_filter_list",
5216                                sizeof(struct hns3_process_private),
5217                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5218         if (eth_dev->process_private == NULL) {
5219                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5220                 return -ENOMEM;
5221         }
5222         /* initialize flow filter lists */
5223         hns3_filterlist_init(eth_dev);
5224
5225         hns3_set_rxtx_function(eth_dev);
5226         eth_dev->dev_ops = &hns3_eth_dev_ops;
5227         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5228                 hns3_mp_init_secondary();
5229                 hw->secondary_cnt++;
5230                 return 0;
5231         }
5232
5233         hns3_mp_init_primary();
5234         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5235
5236         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5237             device_id == HNS3_DEV_ID_50GE_RDMA ||
5238             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5239                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5240
5241         hns->is_vf = false;
5242         hw->data = eth_dev->data;
5243
5244         /*
5245          * Set default max packet size according to the mtu
5246          * default vale in DPDK frame.
5247          */
5248         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5249
5250         ret = hns3_reset_init(hw);
5251         if (ret)
5252                 goto err_init_reset;
5253         hw->reset.ops = &hns3_reset_ops;
5254
5255         ret = hns3_init_pf(eth_dev);
5256         if (ret) {
5257                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5258                 goto err_init_pf;
5259         }
5260
5261         /* Allocate memory for storing MAC addresses */
5262         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5263                                                sizeof(struct rte_ether_addr) *
5264                                                HNS3_UC_MACADDR_NUM, 0);
5265         if (eth_dev->data->mac_addrs == NULL) {
5266                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5267                              "to store MAC addresses",
5268                              sizeof(struct rte_ether_addr) *
5269                              HNS3_UC_MACADDR_NUM);
5270                 ret = -ENOMEM;
5271                 goto err_rte_zmalloc;
5272         }
5273
5274         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5275                             &eth_dev->data->mac_addrs[0]);
5276
5277         hw->adapter_state = HNS3_NIC_INITIALIZED;
5278         /*
5279          * Pass the information to the rte_eth_dev_close() that it should also
5280          * release the private port resources.
5281          */
5282         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5283
5284         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5285                 hns3_err(hw, "Reschedule reset service after dev_init");
5286                 hns3_schedule_reset(hns);
5287         } else {
5288                 /* IMP will wait ready flag before reset */
5289                 hns3_notify_reset_ready(hw, false);
5290         }
5291
5292         hns3_info(hw, "hns3 dev initialization successful!");
5293         return 0;
5294
5295 err_rte_zmalloc:
5296         hns3_uninit_pf(eth_dev);
5297
5298 err_init_pf:
5299         rte_free(hw->reset.wait_data);
5300 err_init_reset:
5301         eth_dev->dev_ops = NULL;
5302         eth_dev->rx_pkt_burst = NULL;
5303         eth_dev->tx_pkt_burst = NULL;
5304         eth_dev->tx_pkt_prepare = NULL;
5305         rte_free(eth_dev->process_private);
5306         eth_dev->process_private = NULL;
5307         return ret;
5308 }
5309
5310 static int
5311 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5312 {
5313         struct hns3_adapter *hns = eth_dev->data->dev_private;
5314         struct hns3_hw *hw = &hns->hw;
5315
5316         PMD_INIT_FUNC_TRACE();
5317
5318         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5319                 return -EPERM;
5320
5321         eth_dev->dev_ops = NULL;
5322         eth_dev->rx_pkt_burst = NULL;
5323         eth_dev->tx_pkt_burst = NULL;
5324         eth_dev->tx_pkt_prepare = NULL;
5325         if (hw->adapter_state < HNS3_NIC_CLOSING)
5326                 hns3_dev_close(eth_dev);
5327
5328         hw->adapter_state = HNS3_NIC_REMOVED;
5329         return 0;
5330 }
5331
5332 static int
5333 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5334                    struct rte_pci_device *pci_dev)
5335 {
5336         return rte_eth_dev_pci_generic_probe(pci_dev,
5337                                              sizeof(struct hns3_adapter),
5338                                              hns3_dev_init);
5339 }
5340
5341 static int
5342 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5343 {
5344         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5345 }
5346
5347 static const struct rte_pci_id pci_id_hns3_map[] = {
5348         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5349         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5350         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5351         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5352         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5353         { .vendor_id = 0, /* sentinel */ },
5354 };
5355
5356 static struct rte_pci_driver rte_hns3_pmd = {
5357         .id_table = pci_id_hns3_map,
5358         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5359         .probe = eth_hns3_pci_probe,
5360         .remove = eth_hns3_pci_remove,
5361 };
5362
5363 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5364 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5365 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5366
5367 RTE_INIT(hns3_init_log)
5368 {
5369         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5370         if (hns3_logtype_init >= 0)
5371                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5372         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5373         if (hns3_logtype_driver >= 0)
5374                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5375 }