1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
12 #include <rte_atomic.h>
13 #include <rte_bus_pci.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_interrupts.h>
26 #include "hns3_ethdev.h"
27 #include "hns3_logs.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_intr.h"
30 #include "hns3_regs.h"
34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
37 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
38 #define HNS3_INVLID_PVID 0xFFFF
40 #define HNS3_FILTER_TYPE_VF 0
41 #define HNS3_FILTER_TYPE_PORT 1
42 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
43 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
44 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
45 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
46 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
47 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
48 | HNS3_FILTER_FE_ROCE_EGRESS_B)
49 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
50 | HNS3_FILTER_FE_ROCE_INGRESS_B)
52 /* Reset related Registers */
53 #define HNS3_GLOBAL_RESET_BIT 0
54 #define HNS3_CORE_RESET_BIT 1
55 #define HNS3_IMP_RESET_BIT 2
56 #define HNS3_FUN_RST_ING_B 0
58 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
60 #define HNS3_RESET_WAIT_MS 100
61 #define HNS3_RESET_WAIT_CNT 200
63 int hns3_logtype_init;
64 int hns3_logtype_driver;
67 HNS3_VECTOR0_EVENT_RST,
68 HNS3_VECTOR0_EVENT_MBX,
69 HNS3_VECTOR0_EVENT_ERR,
70 HNS3_VECTOR0_EVENT_OTHER,
73 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
75 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
76 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
78 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
80 static int hns3_add_mc_addr(struct hns3_hw *hw,
81 struct rte_ether_addr *mac_addr);
82 static int hns3_remove_mc_addr(struct hns3_hw *hw,
83 struct rte_ether_addr *mac_addr);
86 hns3_pf_disable_irq0(struct hns3_hw *hw)
88 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
92 hns3_pf_enable_irq0(struct hns3_hw *hw)
94 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
97 static enum hns3_evt_cause
98 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
100 struct hns3_hw *hw = &hns->hw;
101 uint32_t vector0_int_stats;
102 uint32_t cmdq_src_val;
104 enum hns3_evt_cause ret;
106 /* fetch the events from their corresponding regs */
107 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
108 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
111 * Assumption: If by any chance reset and mailbox events are reported
112 * together then we will only process reset event and defer the
113 * processing of the mailbox events. Since, we would have not cleared
114 * RX CMDQ event this time we would receive again another interrupt
115 * from H/W just for the mailbox.
117 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
118 rte_atomic16_set(&hw->reset.disable_cmd, 1);
119 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
120 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
122 hw->reset.stats.imp_cnt++;
123 hns3_warn(hw, "IMP reset detected, clear reset status");
125 hns3_schedule_delayed_reset(hns);
126 hns3_warn(hw, "IMP reset detected, don't clear reset status");
129 ret = HNS3_VECTOR0_EVENT_RST;
134 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
135 rte_atomic16_set(&hw->reset.disable_cmd, 1);
136 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
137 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
139 hw->reset.stats.global_cnt++;
140 hns3_warn(hw, "Global reset detected, clear reset status");
142 hns3_schedule_delayed_reset(hns);
143 hns3_warn(hw, "Global reset detected, don't clear reset status");
146 ret = HNS3_VECTOR0_EVENT_RST;
150 /* check for vector0 msix event source */
151 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
152 val = vector0_int_stats;
153 ret = HNS3_VECTOR0_EVENT_ERR;
157 /* check for vector0 mailbox(=CMDQ RX) event source */
158 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
159 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
161 ret = HNS3_VECTOR0_EVENT_MBX;
165 if (clearval && (vector0_int_stats || cmdq_src_val))
166 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
167 vector0_int_stats, cmdq_src_val);
168 val = vector0_int_stats;
169 ret = HNS3_VECTOR0_EVENT_OTHER;
178 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
180 if (event_type == HNS3_VECTOR0_EVENT_RST)
181 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
182 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
183 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
187 hns3_clear_all_event_cause(struct hns3_hw *hw)
189 uint32_t vector0_int_stats;
190 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
192 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
193 hns3_warn(hw, "Probe during IMP reset interrupt");
195 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
196 hns3_warn(hw, "Probe during Global reset interrupt");
198 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
199 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
200 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
201 BIT(HNS3_VECTOR0_CORERESET_INT_B));
202 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
206 hns3_interrupt_handler(void *param)
208 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
209 struct hns3_adapter *hns = dev->data->dev_private;
210 struct hns3_hw *hw = &hns->hw;
211 enum hns3_evt_cause event_cause;
212 uint32_t clearval = 0;
214 /* Disable interrupt */
215 hns3_pf_disable_irq0(hw);
217 event_cause = hns3_check_event_cause(hns, &clearval);
219 /* vector 0 interrupt is shared with reset and mailbox source events. */
220 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
221 hns3_handle_msix_error(hns, &hw->reset.request);
222 hns3_schedule_reset(hns);
223 } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
224 hns3_schedule_reset(hns);
225 else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
226 hns3_dev_handle_mbx_msg(hw);
228 hns3_err(hw, "Received unknown event");
230 hns3_clear_event_cause(hw, event_cause, clearval);
231 /* Enable interrupt if it is not cause by reset */
232 hns3_pf_enable_irq0(hw);
236 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
238 #define HNS3_VLAN_ID_OFFSET_STEP 160
239 #define HNS3_VLAN_BYTE_SIZE 8
240 struct hns3_vlan_filter_pf_cfg_cmd *req;
241 struct hns3_hw *hw = &hns->hw;
242 uint8_t vlan_offset_byte_val;
243 struct hns3_cmd_desc desc;
244 uint8_t vlan_offset_byte;
245 uint8_t vlan_offset_base;
248 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
250 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
251 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
253 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
255 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
256 req->vlan_offset = vlan_offset_base;
257 req->vlan_cfg = on ? 0 : 1;
258 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
260 ret = hns3_cmd_send(hw, &desc, 1);
262 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
269 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
271 struct hns3_user_vlan_table *vlan_entry;
272 struct hns3_pf *pf = &hns->pf;
274 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
275 if (vlan_entry->vlan_id == vlan_id) {
276 if (vlan_entry->hd_tbl_status)
277 hns3_set_port_vlan_filter(hns, vlan_id, 0);
278 LIST_REMOVE(vlan_entry, next);
279 rte_free(vlan_entry);
286 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
289 struct hns3_user_vlan_table *vlan_entry;
290 struct hns3_hw *hw = &hns->hw;
291 struct hns3_pf *pf = &hns->pf;
293 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
294 if (vlan_entry->vlan_id == vlan_id)
298 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
299 if (vlan_entry == NULL) {
300 hns3_err(hw, "Failed to malloc hns3 vlan table");
304 vlan_entry->hd_tbl_status = writen_to_tbl;
305 vlan_entry->vlan_id = vlan_id;
307 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
311 hns3_restore_vlan_table(struct hns3_adapter *hns)
313 struct hns3_user_vlan_table *vlan_entry;
314 struct hns3_hw *hw = &hns->hw;
315 struct hns3_pf *pf = &hns->pf;
319 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
320 return hns3_vlan_pvid_configure(hns,
321 hw->port_base_vlan_cfg.pvid, 1);
323 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
324 if (vlan_entry->hd_tbl_status) {
325 vlan_id = vlan_entry->vlan_id;
326 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
336 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
338 struct hns3_hw *hw = &hns->hw;
339 bool writen_to_tbl = false;
343 * When vlan filter is enabled, hardware regards vlan id 0 as the entry
344 * for normal packet, deleting vlan id 0 is not allowed.
346 if (on == 0 && vlan_id == 0)
350 * When port base vlan enabled, we use port base vlan as the vlan
351 * filter condition. In this case, we don't update vlan filter table
352 * when user add new vlan or remove exist vlan, just update the
353 * vlan list. The vlan id in vlan list will be writen in vlan filter
354 * table until port base vlan disabled
356 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
357 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
358 writen_to_tbl = true;
361 if (ret == 0 && vlan_id) {
363 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
365 hns3_rm_dev_vlan_table(hns, vlan_id);
371 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
373 struct hns3_adapter *hns = dev->data->dev_private;
374 struct hns3_hw *hw = &hns->hw;
377 rte_spinlock_lock(&hw->lock);
378 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
379 rte_spinlock_unlock(&hw->lock);
384 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
387 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
388 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
389 struct hns3_hw *hw = &hns->hw;
390 struct hns3_cmd_desc desc;
393 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
394 vlan_type != ETH_VLAN_TYPE_OUTER)) {
395 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
399 if (tpid != RTE_ETHER_TYPE_VLAN) {
400 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
404 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
405 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
407 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
408 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
409 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
410 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
411 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
412 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
413 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
414 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
417 ret = hns3_cmd_send(hw, &desc, 1);
419 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
424 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
426 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
427 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
428 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
430 ret = hns3_cmd_send(hw, &desc, 1);
432 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
438 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
441 struct hns3_adapter *hns = dev->data->dev_private;
442 struct hns3_hw *hw = &hns->hw;
445 rte_spinlock_lock(&hw->lock);
446 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
447 rte_spinlock_unlock(&hw->lock);
452 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
453 struct hns3_rx_vtag_cfg *vcfg)
455 struct hns3_vport_vtag_rx_cfg_cmd *req;
456 struct hns3_hw *hw = &hns->hw;
457 struct hns3_cmd_desc desc;
462 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
464 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
465 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
466 vcfg->strip_tag1_en ? 1 : 0);
467 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
468 vcfg->strip_tag2_en ? 1 : 0);
469 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
470 vcfg->vlan1_vlan_prionly ? 1 : 0);
471 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
472 vcfg->vlan2_vlan_prionly ? 1 : 0);
475 * In current version VF is not supported when PF is driven by DPDK
476 * driver, just need to configure parameters for PF vport.
478 vport_id = HNS3_PF_FUNC_ID;
479 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
480 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
481 req->vf_bitmap[req->vf_offset] = bitmap;
483 ret = hns3_cmd_send(hw, &desc, 1);
485 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
490 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
491 struct hns3_rx_vtag_cfg *vcfg)
493 struct hns3_pf *pf = &hns->pf;
494 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
498 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
499 struct hns3_tx_vtag_cfg *vcfg)
501 struct hns3_pf *pf = &hns->pf;
502 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
506 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
508 struct hns3_rx_vtag_cfg rxvlan_cfg;
509 struct hns3_hw *hw = &hns->hw;
512 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
513 rxvlan_cfg.strip_tag1_en = false;
514 rxvlan_cfg.strip_tag2_en = enable;
516 rxvlan_cfg.strip_tag1_en = enable;
517 rxvlan_cfg.strip_tag2_en = true;
520 rxvlan_cfg.vlan1_vlan_prionly = false;
521 rxvlan_cfg.vlan2_vlan_prionly = false;
522 rxvlan_cfg.rx_vlan_offload_en = enable;
524 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
526 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
530 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
536 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
537 uint8_t fe_type, bool filter_en, uint8_t vf_id)
539 struct hns3_vlan_filter_ctrl_cmd *req;
540 struct hns3_cmd_desc desc;
543 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
545 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
546 req->vlan_type = vlan_type;
547 req->vlan_fe = filter_en ? fe_type : 0;
550 ret = hns3_cmd_send(hw, &desc, 1);
552 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
558 hns3_vlan_filter_init(struct hns3_adapter *hns)
560 struct hns3_hw *hw = &hns->hw;
563 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
564 HNS3_FILTER_FE_EGRESS, false,
567 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
571 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
572 HNS3_FILTER_FE_INGRESS, false,
575 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
581 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
583 struct hns3_hw *hw = &hns->hw;
586 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
587 HNS3_FILTER_FE_INGRESS, enable,
590 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
591 enable ? "enable" : "disable", ret);
597 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
599 struct hns3_adapter *hns = dev->data->dev_private;
600 struct hns3_hw *hw = &hns->hw;
601 struct rte_eth_rxmode *rxmode;
602 unsigned int tmp_mask;
606 rte_spinlock_lock(&hw->lock);
607 rxmode = &dev->data->dev_conf.rxmode;
608 tmp_mask = (unsigned int)mask;
609 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
610 /* ignore vlan filter configuration during promiscuous mode */
611 if (!dev->data->promiscuous) {
612 /* Enable or disable VLAN filter */
613 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
616 ret = hns3_enable_vlan_filter(hns, enable);
618 rte_spinlock_unlock(&hw->lock);
619 hns3_err(hw, "failed to %s rx filter, ret = %d",
620 enable ? "enable" : "disable", ret);
626 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
627 /* Enable or disable VLAN stripping */
628 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
631 ret = hns3_en_hw_strip_rxvtag(hns, enable);
633 rte_spinlock_unlock(&hw->lock);
634 hns3_err(hw, "failed to %s rx strip, ret = %d",
635 enable ? "enable" : "disable", ret);
640 rte_spinlock_unlock(&hw->lock);
646 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
647 struct hns3_tx_vtag_cfg *vcfg)
649 struct hns3_vport_vtag_tx_cfg_cmd *req;
650 struct hns3_cmd_desc desc;
651 struct hns3_hw *hw = &hns->hw;
656 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
658 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
659 req->def_vlan_tag1 = vcfg->default_tag1;
660 req->def_vlan_tag2 = vcfg->default_tag2;
661 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
662 vcfg->accept_tag1 ? 1 : 0);
663 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
664 vcfg->accept_untag1 ? 1 : 0);
665 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
666 vcfg->accept_tag2 ? 1 : 0);
667 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
668 vcfg->accept_untag2 ? 1 : 0);
669 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
670 vcfg->insert_tag1_en ? 1 : 0);
671 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
672 vcfg->insert_tag2_en ? 1 : 0);
673 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
676 * In current version VF is not supported when PF is driven by DPDK
677 * driver, just need to configure parameters for PF vport.
679 vport_id = HNS3_PF_FUNC_ID;
680 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
681 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
682 req->vf_bitmap[req->vf_offset] = bitmap;
684 ret = hns3_cmd_send(hw, &desc, 1);
686 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
692 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
695 struct hns3_hw *hw = &hns->hw;
696 struct hns3_tx_vtag_cfg txvlan_cfg;
699 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
700 txvlan_cfg.accept_tag1 = true;
701 txvlan_cfg.insert_tag1_en = false;
702 txvlan_cfg.default_tag1 = 0;
704 txvlan_cfg.accept_tag1 = false;
705 txvlan_cfg.insert_tag1_en = true;
706 txvlan_cfg.default_tag1 = pvid;
709 txvlan_cfg.accept_untag1 = true;
710 txvlan_cfg.accept_tag2 = true;
711 txvlan_cfg.accept_untag2 = true;
712 txvlan_cfg.insert_tag2_en = false;
713 txvlan_cfg.default_tag2 = 0;
715 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
717 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
722 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
727 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
729 struct hns3_hw *hw = &hns->hw;
731 hw->port_base_vlan_cfg.state = on ?
732 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
734 hw->port_base_vlan_cfg.pvid = pvid;
738 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
740 struct hns3_user_vlan_table *vlan_entry;
741 struct hns3_pf *pf = &hns->pf;
743 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
744 if (vlan_entry->hd_tbl_status)
745 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
747 vlan_entry->hd_tbl_status = false;
751 vlan_entry = LIST_FIRST(&pf->vlan_list);
753 LIST_REMOVE(vlan_entry, next);
754 rte_free(vlan_entry);
755 vlan_entry = LIST_FIRST(&pf->vlan_list);
761 hns3_add_all_vlan_table(struct hns3_adapter *hns)
763 struct hns3_user_vlan_table *vlan_entry;
764 struct hns3_pf *pf = &hns->pf;
766 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
767 if (!vlan_entry->hd_tbl_status)
768 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
770 vlan_entry->hd_tbl_status = true;
775 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
777 struct hns3_hw *hw = &hns->hw;
780 hns3_rm_all_vlan_table(hns, true);
781 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
782 ret = hns3_set_port_vlan_filter(hns,
783 hw->port_base_vlan_cfg.pvid, 0);
785 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
793 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
794 uint16_t port_base_vlan_state,
795 uint16_t new_pvid, uint16_t old_pvid)
797 struct hns3_hw *hw = &hns->hw;
800 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
801 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
802 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
805 "Failed to clear clear old pvid filter, ret =%d",
811 hns3_rm_all_vlan_table(hns, false);
812 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
816 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
818 hns3_err(hw, "Failed to set port vlan filter, ret =%d",
824 if (new_pvid == hw->port_base_vlan_cfg.pvid)
825 hns3_add_all_vlan_table(hns);
831 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
833 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
834 struct hns3_rx_vtag_cfg rx_vlan_cfg;
838 rx_strip_en = old_cfg->rx_vlan_offload_en ? true : false;
840 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
841 rx_vlan_cfg.strip_tag2_en = true;
843 rx_vlan_cfg.strip_tag1_en = false;
844 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
846 rx_vlan_cfg.vlan1_vlan_prionly = false;
847 rx_vlan_cfg.vlan2_vlan_prionly = false;
848 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
850 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
854 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
859 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
861 struct hns3_hw *hw = &hns->hw;
862 uint16_t port_base_vlan_state;
866 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
867 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
868 hns3_warn(hw, "Invalid operation! As current pvid set "
869 "is %u, disable pvid %u is invalid",
870 hw->port_base_vlan_cfg.pvid, pvid);
874 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
875 HNS3_PORT_BASE_VLAN_DISABLE;
876 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
878 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
883 ret = hns3_en_pvid_strip(hns, on);
885 hns3_err(hw, "failed to config rx vlan strip for pvid, "
890 if (pvid == HNS3_INVLID_PVID)
892 old_pvid = hw->port_base_vlan_cfg.pvid;
893 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
896 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
902 hns3_store_port_base_vlan_info(hns, pvid, on);
907 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
909 struct hns3_adapter *hns = dev->data->dev_private;
910 struct hns3_hw *hw = &hns->hw;
913 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
914 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
915 RTE_ETHER_MAX_VLAN_ID);
919 rte_spinlock_lock(&hw->lock);
920 ret = hns3_vlan_pvid_configure(hns, pvid, on);
921 rte_spinlock_unlock(&hw->lock);
926 init_port_base_vlan_info(struct hns3_hw *hw)
928 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
929 hw->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
933 hns3_default_vlan_config(struct hns3_adapter *hns)
935 struct hns3_hw *hw = &hns->hw;
938 ret = hns3_set_port_vlan_filter(hns, 0, 1);
940 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
945 hns3_init_vlan_config(struct hns3_adapter *hns)
947 struct hns3_hw *hw = &hns->hw;
951 * This function can be called in the initialization and reset process,
952 * when in reset process, it means that hardware had been reseted
953 * successfully and we need to restore the hardware configuration to
954 * ensure that the hardware configuration remains unchanged before and
957 if (rte_atomic16_read(&hw->reset.resetting) == 0)
958 init_port_base_vlan_info(hw);
960 ret = hns3_vlan_filter_init(hns);
962 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
966 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
967 RTE_ETHER_TYPE_VLAN);
969 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
974 * When in the reinit dev stage of the reset process, the following
975 * vlan-related configurations may differ from those at initialization,
976 * we will restore configurations to hardware in hns3_restore_vlan_table
977 * and hns3_restore_vlan_conf later.
979 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
980 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
982 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
986 ret = hns3_en_hw_strip_rxvtag(hns, false);
988 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
994 return hns3_default_vlan_config(hns);
998 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1000 struct hns3_pf *pf = &hns->pf;
1001 struct hns3_hw *hw = &hns->hw;
1006 if (!hw->data->promiscuous) {
1007 /* restore vlan filter states */
1008 offloads = hw->data->dev_conf.rxmode.offloads;
1009 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1010 ret = hns3_enable_vlan_filter(hns, enable);
1012 hns3_err(hw, "failed to restore vlan rx filter conf, "
1018 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1020 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1024 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1026 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1032 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1034 struct hns3_adapter *hns = dev->data->dev_private;
1035 struct rte_eth_dev_data *data = dev->data;
1036 struct rte_eth_txmode *txmode;
1037 struct hns3_hw *hw = &hns->hw;
1041 txmode = &data->dev_conf.txmode;
1042 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1044 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1045 "configuration is not supported! Ignore these two "
1046 "parameters: hw_vlan_reject_tagged(%d), "
1047 "hw_vlan_reject_untagged(%d)",
1048 txmode->hw_vlan_reject_tagged,
1049 txmode->hw_vlan_reject_untagged);
1051 /* Apply vlan offload setting */
1052 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1053 ret = hns3_vlan_offload_set(dev, mask);
1055 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1061 * If pvid config is not set in rte_eth_conf, driver needn't to set
1062 * VLAN pvid related configuration to hardware.
1064 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1067 /* Apply pvid setting */
1068 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1069 txmode->hw_vlan_insert_pvid);
1071 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1078 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1079 unsigned int tso_mss_max)
1081 struct hns3_cfg_tso_status_cmd *req;
1082 struct hns3_cmd_desc desc;
1085 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1087 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1090 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1092 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1095 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1097 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1099 return hns3_cmd_send(hw, &desc, 1);
1103 hns3_config_gro(struct hns3_hw *hw, bool en)
1105 struct hns3_cfg_gro_status_cmd *req;
1106 struct hns3_cmd_desc desc;
1109 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1110 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1112 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1114 ret = hns3_cmd_send(hw, &desc, 1);
1116 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1122 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1123 uint16_t *allocated_size, bool is_alloc)
1125 struct hns3_umv_spc_alc_cmd *req;
1126 struct hns3_cmd_desc desc;
1129 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1130 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1131 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1132 req->space_size = rte_cpu_to_le_32(space_size);
1134 ret = hns3_cmd_send(hw, &desc, 1);
1136 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1137 is_alloc ? "allocate" : "free", ret);
1141 if (is_alloc && allocated_size)
1142 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1148 hns3_init_umv_space(struct hns3_hw *hw)
1150 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1151 struct hns3_pf *pf = &hns->pf;
1152 uint16_t allocated_size = 0;
1155 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1160 if (allocated_size < pf->wanted_umv_size)
1161 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1162 pf->wanted_umv_size, allocated_size);
1164 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1165 pf->wanted_umv_size;
1166 pf->used_umv_size = 0;
1171 hns3_uninit_umv_space(struct hns3_hw *hw)
1173 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1174 struct hns3_pf *pf = &hns->pf;
1177 if (pf->max_umv_size == 0)
1180 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1184 pf->max_umv_size = 0;
1190 hns3_is_umv_space_full(struct hns3_hw *hw)
1192 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1193 struct hns3_pf *pf = &hns->pf;
1196 is_full = (pf->used_umv_size >= pf->max_umv_size);
1202 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1204 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1205 struct hns3_pf *pf = &hns->pf;
1208 if (pf->used_umv_size > 0)
1209 pf->used_umv_size--;
1211 pf->used_umv_size++;
1215 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1216 const uint8_t *addr, bool is_mc)
1218 const unsigned char *mac_addr = addr;
1219 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1220 ((uint32_t)mac_addr[2] << 16) |
1221 ((uint32_t)mac_addr[1] << 8) |
1222 (uint32_t)mac_addr[0];
1223 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1225 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1227 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1228 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1229 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1232 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1233 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1237 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1239 enum hns3_mac_vlan_tbl_opcode op)
1242 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1247 if (op == HNS3_MAC_VLAN_ADD) {
1248 if (resp_code == 0 || resp_code == 1) {
1250 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1251 hns3_err(hw, "add mac addr failed for uc_overflow");
1253 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1254 hns3_err(hw, "add mac addr failed for mc_overflow");
1258 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1261 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1262 if (resp_code == 0) {
1264 } else if (resp_code == 1) {
1265 hns3_dbg(hw, "remove mac addr failed for miss");
1269 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1272 } else if (op == HNS3_MAC_VLAN_LKUP) {
1273 if (resp_code == 0) {
1275 } else if (resp_code == 1) {
1276 hns3_dbg(hw, "lookup mac addr failed for miss");
1280 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1285 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1292 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1293 struct hns3_mac_vlan_tbl_entry_cmd *req,
1294 struct hns3_cmd_desc *desc, bool is_mc)
1300 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1302 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1303 memcpy(desc[0].data, req,
1304 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1305 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1307 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1308 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1310 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1312 memcpy(desc[0].data, req,
1313 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1314 ret = hns3_cmd_send(hw, desc, 1);
1317 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1321 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1322 retval = rte_le_to_cpu_16(desc[0].retval);
1324 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1325 HNS3_MAC_VLAN_LKUP);
1329 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1330 struct hns3_mac_vlan_tbl_entry_cmd *req,
1331 struct hns3_cmd_desc *mc_desc)
1338 if (mc_desc == NULL) {
1339 struct hns3_cmd_desc desc;
1341 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1342 memcpy(desc.data, req,
1343 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1344 ret = hns3_cmd_send(hw, &desc, 1);
1345 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1346 retval = rte_le_to_cpu_16(desc.retval);
1348 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1351 hns3_cmd_reuse_desc(&mc_desc[0], false);
1352 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1353 hns3_cmd_reuse_desc(&mc_desc[1], false);
1354 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1355 hns3_cmd_reuse_desc(&mc_desc[2], false);
1356 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1357 memcpy(mc_desc[0].data, req,
1358 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1359 mc_desc[0].retval = 0;
1360 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1361 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1362 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1364 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1369 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1377 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1378 struct hns3_mac_vlan_tbl_entry_cmd *req)
1380 struct hns3_cmd_desc desc;
1385 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1387 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1389 ret = hns3_cmd_send(hw, &desc, 1);
1391 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1394 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1395 retval = rte_le_to_cpu_16(desc.retval);
1397 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1398 HNS3_MAC_VLAN_REMOVE);
1402 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1404 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1405 struct hns3_mac_vlan_tbl_entry_cmd req;
1406 struct hns3_pf *pf = &hns->pf;
1407 struct hns3_cmd_desc desc;
1408 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1409 uint16_t egress_port = 0;
1413 /* check if mac addr is valid */
1414 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1415 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1417 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1422 memset(&req, 0, sizeof(req));
1425 * In current version VF is not supported when PF is driven by DPDK
1426 * driver, just need to configure parameters for PF vport.
1428 vf_id = HNS3_PF_FUNC_ID;
1429 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1430 HNS3_MAC_EPORT_VFID_S, vf_id);
1432 req.egress_port = rte_cpu_to_le_16(egress_port);
1434 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1437 * Lookup the mac address in the mac_vlan table, and add
1438 * it if the entry is inexistent. Repeated unicast entry
1439 * is not allowed in the mac vlan table.
1441 ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1442 if (ret == -ENOENT) {
1443 if (!hns3_is_umv_space_full(hw)) {
1444 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1446 hns3_update_umv_space(hw, false);
1450 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1455 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1457 /* check if we just hit the duplicate */
1459 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1463 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1470 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1472 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1473 struct rte_ether_addr *addr;
1477 for (i = 0; i < hw->mc_addrs_num; i++) {
1478 addr = &hw->mc_addrs[i];
1479 /* Check if there are duplicate addresses */
1480 if (rte_is_same_ether_addr(addr, mac_addr)) {
1481 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1483 hns3_err(hw, "failed to add mc mac addr, same addrs"
1484 "(%s) is added by the set_mc_mac_addr_list "
1490 ret = hns3_add_mc_addr(hw, mac_addr);
1492 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1494 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1501 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1503 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1506 ret = hns3_remove_mc_addr(hw, mac_addr);
1508 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1510 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1517 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1518 uint32_t idx, __rte_unused uint32_t pool)
1520 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1521 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1524 rte_spinlock_lock(&hw->lock);
1527 * In hns3 network engine adding UC and MC mac address with different
1528 * commands with firmware. We need to determine whether the input
1529 * address is a UC or a MC address to call different commands.
1530 * By the way, it is recommended calling the API function named
1531 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1532 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1533 * may affect the specifications of UC mac addresses.
1535 if (rte_is_multicast_ether_addr(mac_addr))
1536 ret = hns3_add_mc_addr_common(hw, mac_addr);
1538 ret = hns3_add_uc_addr_common(hw, mac_addr);
1541 rte_spinlock_unlock(&hw->lock);
1542 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1544 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1550 hw->mac.default_addr_setted = true;
1551 rte_spinlock_unlock(&hw->lock);
1557 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1559 struct hns3_mac_vlan_tbl_entry_cmd req;
1560 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1563 /* check if mac addr is valid */
1564 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1565 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1567 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1572 memset(&req, 0, sizeof(req));
1573 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1574 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1575 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1576 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1579 hns3_update_umv_space(hw, true);
1585 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1587 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1588 /* index will be checked by upper level rte interface */
1589 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1590 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1593 rte_spinlock_lock(&hw->lock);
1595 if (rte_is_multicast_ether_addr(mac_addr))
1596 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1598 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1599 rte_spinlock_unlock(&hw->lock);
1601 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1603 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1609 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1610 struct rte_ether_addr *mac_addr)
1612 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613 struct rte_ether_addr *oaddr;
1614 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1615 bool default_addr_setted;
1616 bool rm_succes = false;
1620 * It has been guaranteed that input parameter named mac_addr is valid
1621 * address in the rte layer of DPDK framework.
1623 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1624 default_addr_setted = hw->mac.default_addr_setted;
1625 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1628 rte_spinlock_lock(&hw->lock);
1629 if (default_addr_setted) {
1630 ret = hns3_remove_uc_addr_common(hw, oaddr);
1632 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1634 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1641 ret = hns3_add_uc_addr_common(hw, mac_addr);
1643 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1645 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1646 goto err_add_uc_addr;
1649 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1651 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1652 goto err_pause_addr_cfg;
1655 rte_ether_addr_copy(mac_addr,
1656 (struct rte_ether_addr *)hw->mac.mac_addr);
1657 hw->mac.default_addr_setted = true;
1658 rte_spinlock_unlock(&hw->lock);
1663 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1665 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1668 "Failed to roll back to del setted mac addr(%s): %d",
1674 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1676 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1679 "Failed to restore old uc mac addr(%s): %d",
1681 hw->mac.default_addr_setted = false;
1684 rte_spinlock_unlock(&hw->lock);
1690 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1692 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1693 struct hns3_hw *hw = &hns->hw;
1694 struct rte_ether_addr *addr;
1699 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1700 addr = &hw->data->mac_addrs[i];
1701 if (rte_is_zero_ether_addr(addr))
1703 if (rte_is_multicast_ether_addr(addr))
1704 ret = del ? hns3_remove_mc_addr(hw, addr) :
1705 hns3_add_mc_addr(hw, addr);
1707 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1708 hns3_add_uc_addr_common(hw, addr);
1712 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1714 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1715 "ret = %d.", del ? "remove" : "restore",
1723 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1725 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1729 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1730 word_num = vfid / 32;
1731 bit_num = vfid % 32;
1733 desc[1].data[word_num] &=
1734 rte_cpu_to_le_32(~(1UL << bit_num));
1736 desc[1].data[word_num] |=
1737 rte_cpu_to_le_32(1UL << bit_num);
1739 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1740 bit_num = vfid % 32;
1742 desc[2].data[word_num] &=
1743 rte_cpu_to_le_32(~(1UL << bit_num));
1745 desc[2].data[word_num] |=
1746 rte_cpu_to_le_32(1UL << bit_num);
1751 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1753 struct hns3_mac_vlan_tbl_entry_cmd req;
1754 struct hns3_cmd_desc desc[3];
1755 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1759 /* Check if mac addr is valid */
1760 if (!rte_is_multicast_ether_addr(mac_addr)) {
1761 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1763 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1768 memset(&req, 0, sizeof(req));
1769 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1770 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1771 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1773 /* This mac addr do not exist, add new entry for it */
1774 memset(desc[0].data, 0, sizeof(desc[0].data));
1775 memset(desc[1].data, 0, sizeof(desc[0].data));
1776 memset(desc[2].data, 0, sizeof(desc[0].data));
1780 * In current version VF is not supported when PF is driven by DPDK
1781 * driver, just need to configure parameters for PF vport.
1783 vf_id = HNS3_PF_FUNC_ID;
1784 hns3_update_desc_vfid(desc, vf_id, false);
1785 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1788 hns3_err(hw, "mc mac vlan table is full");
1789 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1791 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1798 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1800 struct hns3_mac_vlan_tbl_entry_cmd req;
1801 struct hns3_cmd_desc desc[3];
1802 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1806 /* Check if mac addr is valid */
1807 if (!rte_is_multicast_ether_addr(mac_addr)) {
1808 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1810 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1815 memset(&req, 0, sizeof(req));
1816 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1817 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1818 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1821 * This mac addr exist, remove this handle's VFID for it.
1822 * In current version VF is not supported when PF is driven by
1823 * DPDK driver, just need to configure parameters for PF vport.
1825 vf_id = HNS3_PF_FUNC_ID;
1826 hns3_update_desc_vfid(desc, vf_id, true);
1828 /* All the vfid is zero, so need to delete this entry */
1829 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1830 } else if (ret == -ENOENT) {
1831 /* This mac addr doesn't exist. */
1836 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1838 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1845 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1846 struct rte_ether_addr *mc_addr_set,
1847 uint32_t nb_mc_addr)
1849 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1850 struct rte_ether_addr *addr;
1854 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1855 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1856 "invalid. valid range: 0~%d",
1857 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1861 /* Check if input mac addresses are valid */
1862 for (i = 0; i < nb_mc_addr; i++) {
1863 addr = &mc_addr_set[i];
1864 if (!rte_is_multicast_ether_addr(addr)) {
1865 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1868 "failed to set mc mac addr, addr(%s) invalid.",
1873 /* Check if there are duplicate addresses */
1874 for (j = i + 1; j < nb_mc_addr; j++) {
1875 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1876 rte_ether_format_addr(mac_str,
1877 RTE_ETHER_ADDR_FMT_SIZE,
1879 hns3_err(hw, "failed to set mc mac addr, "
1880 "addrs invalid. two same addrs(%s).",
1887 * Check if there are duplicate addresses between mac_addrs
1890 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1891 if (rte_is_same_ether_addr(addr,
1892 &hw->data->mac_addrs[j])) {
1893 rte_ether_format_addr(mac_str,
1894 RTE_ETHER_ADDR_FMT_SIZE,
1896 hns3_err(hw, "failed to set mc mac addr, "
1897 "addrs invalid. addrs(%s) has already "
1898 "configured in mac_addr add API",
1909 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1910 struct rte_ether_addr *mc_addr_set,
1912 struct rte_ether_addr *reserved_addr_list,
1913 int *reserved_addr_num,
1914 struct rte_ether_addr *add_addr_list,
1916 struct rte_ether_addr *rm_addr_list,
1919 struct rte_ether_addr *addr;
1920 int current_addr_num;
1921 int reserved_num = 0;
1929 /* Calculate the mc mac address list that should be removed */
1930 current_addr_num = hw->mc_addrs_num;
1931 for (i = 0; i < current_addr_num; i++) {
1932 addr = &hw->mc_addrs[i];
1934 for (j = 0; j < mc_addr_num; j++) {
1935 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1942 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1945 rte_ether_addr_copy(addr,
1946 &reserved_addr_list[reserved_num]);
1951 /* Calculate the mc mac address list that should be added */
1952 for (i = 0; i < mc_addr_num; i++) {
1953 addr = &mc_addr_set[i];
1955 for (j = 0; j < current_addr_num; j++) {
1956 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1963 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1968 /* Reorder the mc mac address list maintained by driver */
1969 for (i = 0; i < reserved_num; i++)
1970 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1972 for (i = 0; i < rm_num; i++) {
1973 num = reserved_num + i;
1974 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1977 *reserved_addr_num = reserved_num;
1978 *add_addr_num = add_num;
1979 *rm_addr_num = rm_num;
1983 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1984 struct rte_ether_addr *mc_addr_set,
1985 uint32_t nb_mc_addr)
1987 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1988 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1989 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1990 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1991 struct rte_ether_addr *addr;
1992 int reserved_addr_num;
2000 /* Check if input parameters are valid */
2001 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2005 rte_spinlock_lock(&hw->lock);
2008 * Calculate the mc mac address lists those should be removed and be
2009 * added, Reorder the mc mac address list maintained by driver.
2011 mc_addr_num = (int)nb_mc_addr;
2012 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2013 reserved_addr_list, &reserved_addr_num,
2014 add_addr_list, &add_addr_num,
2015 rm_addr_list, &rm_addr_num);
2017 /* Remove mc mac addresses */
2018 for (i = 0; i < rm_addr_num; i++) {
2019 num = rm_addr_num - i - 1;
2020 addr = &rm_addr_list[num];
2021 ret = hns3_remove_mc_addr(hw, addr);
2023 rte_spinlock_unlock(&hw->lock);
2029 /* Add mc mac addresses */
2030 for (i = 0; i < add_addr_num; i++) {
2031 addr = &add_addr_list[i];
2032 ret = hns3_add_mc_addr(hw, addr);
2034 rte_spinlock_unlock(&hw->lock);
2038 num = reserved_addr_num + i;
2039 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2042 rte_spinlock_unlock(&hw->lock);
2048 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2050 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2051 struct hns3_hw *hw = &hns->hw;
2052 struct rte_ether_addr *addr;
2057 for (i = 0; i < hw->mc_addrs_num; i++) {
2058 addr = &hw->mc_addrs[i];
2059 if (!rte_is_multicast_ether_addr(addr))
2062 ret = hns3_remove_mc_addr(hw, addr);
2064 ret = hns3_add_mc_addr(hw, addr);
2067 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2069 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2070 del ? "Remove" : "Restore", mac_str, ret);
2077 hns3_check_mq_mode(struct rte_eth_dev *dev)
2079 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2080 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2081 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2083 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2084 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2089 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2090 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2092 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2093 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2094 "rx_mq_mode = %d", rx_mq_mode);
2098 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2099 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2100 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2101 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2102 rx_mq_mode, tx_mq_mode);
2106 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2107 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2108 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2109 dcb_rx_conf->nb_tcs, pf->tc_max);
2113 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2114 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2115 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2116 "nb_tcs(%d) != %d or %d in rx direction.",
2117 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2121 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2122 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2123 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2127 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2128 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2129 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2130 "is not equal to one in tx direction.",
2131 i, dcb_rx_conf->dcb_tc[i]);
2134 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2135 max_tc = dcb_rx_conf->dcb_tc[i];
2138 num_tc = max_tc + 1;
2139 if (num_tc > dcb_rx_conf->nb_tcs) {
2140 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2141 num_tc, dcb_rx_conf->nb_tcs);
2150 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2152 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2154 if (!hns3_dev_dcb_supported(hw)) {
2155 hns3_err(hw, "this port does not support dcb configurations.");
2159 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2160 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2164 /* Check multiple queue mode */
2165 return hns3_check_mq_mode(dev);
2169 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2170 enum hns3_ring_type queue_type, uint16_t queue_id)
2172 struct hns3_cmd_desc desc;
2173 struct hns3_ctrl_vector_chain_cmd *req =
2174 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2175 enum hns3_cmd_status status;
2176 enum hns3_opcode_type op;
2177 uint16_t tqp_type_and_id = 0;
2182 op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2183 hns3_cmd_setup_basic_desc(&desc, op, false);
2184 req->int_vector_id = vector_id;
2186 if (queue_type == HNS3_RING_TYPE_RX)
2187 gl = HNS3_RING_GL_RX;
2189 gl = HNS3_RING_GL_TX;
2193 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2195 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2196 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2198 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2199 req->int_cause_num = 1;
2200 op_str = mmap ? "Map" : "Unmap";
2201 status = hns3_cmd_send(hw, &desc, 1);
2203 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2204 op_str, queue_id, req->int_vector_id, status);
2212 hns3_init_ring_with_vector(struct hns3_hw *hw)
2219 * In hns3 network engine, vector 0 is always the misc interrupt of this
2220 * function, vector 1~N can be used respectively for the queues of the
2221 * function. Tx and Rx queues with the same number share the interrupt
2222 * vector. In the initialization clearing the all hardware mapping
2223 * relationship configurations between queues and interrupt vectors is
2224 * needed, so some error caused by the residual configurations, such as
2225 * the unexpected Tx interrupt, can be avoid. Because of the hardware
2226 * constraints in hns3 hardware engine, we have to implement clearing
2227 * the mapping relationship configurations by binding all queues to the
2228 * last interrupt vector and reserving the last interrupt vector. This
2229 * method results in a decrease of the maximum queues when upper
2230 * applications call the rte_eth_dev_configure API function to enable
2233 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2234 /* vec - 1: the last interrupt is reserved */
2235 hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;
2236 for (i = 0; i < hw->intr_tqps_num; i++) {
2238 * Set gap limiter and rate limiter configuration of queue's
2241 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2242 HNS3_TQP_INTR_GL_DEFAULT);
2243 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2244 HNS3_TQP_INTR_GL_DEFAULT);
2245 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2247 ret = hns3_bind_ring_with_vector(hw, vec, false,
2248 HNS3_RING_TYPE_TX, i);
2250 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2251 "vector: %d, ret=%d", i, vec, ret);
2255 ret = hns3_bind_ring_with_vector(hw, vec, false,
2256 HNS3_RING_TYPE_RX, i);
2258 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2259 "vector: %d, ret=%d", i, vec, ret);
2268 hns3_dev_configure(struct rte_eth_dev *dev)
2270 struct hns3_adapter *hns = dev->data->dev_private;
2271 struct rte_eth_conf *conf = &dev->data->dev_conf;
2272 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2273 struct hns3_hw *hw = &hns->hw;
2274 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2275 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2276 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2277 struct rte_eth_rss_conf rss_conf;
2282 * Hardware does not support individually enable/disable/reset the Tx or
2283 * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2284 * and Rx queues at the same time. When the numbers of Tx queues
2285 * allocated by upper applications are not equal to the numbers of Rx
2286 * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2287 * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2288 * these fake queues are imperceptible, and can not be used by upper
2291 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2293 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2297 hw->adapter_state = HNS3_NIC_CONFIGURING;
2298 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2299 hns3_err(hw, "setting link speed/duplex not supported");
2304 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2305 ret = hns3_check_dcb_cfg(dev);
2310 /* When RSS is not configured, redirect the packet queue 0 */
2311 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2312 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2313 rss_conf = conf->rx_adv_conf.rss_conf;
2314 if (rss_conf.rss_key == NULL) {
2315 rss_conf.rss_key = rss_cfg->key;
2316 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2319 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2325 * If jumbo frames are enabled, MTU needs to be refreshed
2326 * according to the maximum RX packet length.
2328 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2330 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2331 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2332 * can safely assign to "uint16_t" type variable.
2334 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2335 ret = hns3_dev_mtu_set(dev, mtu);
2338 dev->data->mtu = mtu;
2341 ret = hns3_dev_configure_vlan(dev);
2345 hw->adapter_state = HNS3_NIC_CONFIGURED;
2350 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2351 hw->adapter_state = HNS3_NIC_INITIALIZED;
2357 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2359 struct hns3_config_max_frm_size_cmd *req;
2360 struct hns3_cmd_desc desc;
2362 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2364 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2365 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2366 req->min_frm_size = RTE_ETHER_MIN_LEN;
2368 return hns3_cmd_send(hw, &desc, 1);
2372 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2376 ret = hns3_set_mac_mtu(hw, mps);
2378 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2382 ret = hns3_buffer_alloc(hw);
2384 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2390 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2392 struct hns3_adapter *hns = dev->data->dev_private;
2393 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2394 struct hns3_hw *hw = &hns->hw;
2395 bool is_jumbo_frame;
2398 if (dev->data->dev_started) {
2399 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2400 "before configuration", dev->data->port_id);
2404 rte_spinlock_lock(&hw->lock);
2405 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2406 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2409 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2410 * assign to "uint16_t" type variable.
2412 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2414 rte_spinlock_unlock(&hw->lock);
2415 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2416 dev->data->port_id, mtu, ret);
2419 hns->pf.mps = (uint16_t)frame_size;
2421 dev->data->dev_conf.rxmode.offloads |=
2422 DEV_RX_OFFLOAD_JUMBO_FRAME;
2424 dev->data->dev_conf.rxmode.offloads &=
2425 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2426 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2427 rte_spinlock_unlock(&hw->lock);
2433 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2435 struct hns3_adapter *hns = eth_dev->data->dev_private;
2436 struct hns3_hw *hw = &hns->hw;
2437 uint16_t queue_num = hw->tqps_num;
2440 * In interrupt mode, 'max_rx_queues' is set based on the number of
2441 * MSI-X interrupt resources of the hardware.
2443 if (hw->data->dev_conf.intr_conf.rxq == 1)
2444 queue_num = hw->intr_tqps_num;
2446 info->max_rx_queues = queue_num;
2447 info->max_tx_queues = hw->tqps_num;
2448 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2449 info->min_rx_bufsize = hw->rx_buf_len;
2450 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2451 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2452 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2453 DEV_RX_OFFLOAD_TCP_CKSUM |
2454 DEV_RX_OFFLOAD_UDP_CKSUM |
2455 DEV_RX_OFFLOAD_SCTP_CKSUM |
2456 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2457 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2458 DEV_RX_OFFLOAD_KEEP_CRC |
2459 DEV_RX_OFFLOAD_SCATTER |
2460 DEV_RX_OFFLOAD_VLAN_STRIP |
2461 DEV_RX_OFFLOAD_VLAN_FILTER |
2462 DEV_RX_OFFLOAD_JUMBO_FRAME |
2463 DEV_RX_OFFLOAD_RSS_HASH);
2464 info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2465 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2466 DEV_TX_OFFLOAD_IPV4_CKSUM |
2467 DEV_TX_OFFLOAD_TCP_CKSUM |
2468 DEV_TX_OFFLOAD_UDP_CKSUM |
2469 DEV_TX_OFFLOAD_SCTP_CKSUM |
2470 DEV_TX_OFFLOAD_VLAN_INSERT |
2471 DEV_TX_OFFLOAD_QINQ_INSERT |
2472 DEV_TX_OFFLOAD_MULTI_SEGS |
2473 DEV_TX_OFFLOAD_TCP_TSO |
2474 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2475 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2476 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2477 info->tx_queue_offload_capa);
2479 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2480 .nb_max = HNS3_MAX_RING_DESC,
2481 .nb_min = HNS3_MIN_RING_DESC,
2482 .nb_align = HNS3_ALIGN_RING_DESC,
2485 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2486 .nb_max = HNS3_MAX_RING_DESC,
2487 .nb_min = HNS3_MIN_RING_DESC,
2488 .nb_align = HNS3_ALIGN_RING_DESC,
2491 info->vmdq_queue_num = 0;
2493 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2494 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2495 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2497 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2498 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2499 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2500 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2501 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2502 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2508 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2511 struct hns3_adapter *hns = eth_dev->data->dev_private;
2512 struct hns3_hw *hw = &hns->hw;
2513 uint32_t version = hw->fw_version;
2516 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2517 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2518 HNS3_FW_VERSION_BYTE3_S),
2519 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2520 HNS3_FW_VERSION_BYTE2_S),
2521 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2522 HNS3_FW_VERSION_BYTE1_S),
2523 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2524 HNS3_FW_VERSION_BYTE0_S));
2525 ret += 1; /* add the size of '\0' */
2526 if (fw_size < (uint32_t)ret)
2533 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2534 __rte_unused int wait_to_complete)
2536 struct hns3_adapter *hns = eth_dev->data->dev_private;
2537 struct hns3_hw *hw = &hns->hw;
2538 struct hns3_mac *mac = &hw->mac;
2539 struct rte_eth_link new_link;
2541 if (!hns3_is_reset_pending(hns)) {
2542 hns3_update_speed_duplex(eth_dev);
2543 hns3_update_link_status(hw);
2546 memset(&new_link, 0, sizeof(new_link));
2547 switch (mac->link_speed) {
2548 case ETH_SPEED_NUM_10M:
2549 case ETH_SPEED_NUM_100M:
2550 case ETH_SPEED_NUM_1G:
2551 case ETH_SPEED_NUM_10G:
2552 case ETH_SPEED_NUM_25G:
2553 case ETH_SPEED_NUM_40G:
2554 case ETH_SPEED_NUM_50G:
2555 case ETH_SPEED_NUM_100G:
2556 new_link.link_speed = mac->link_speed;
2559 new_link.link_speed = ETH_SPEED_NUM_100M;
2563 new_link.link_duplex = mac->link_duplex;
2564 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2565 new_link.link_autoneg =
2566 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2568 return rte_eth_linkstatus_set(eth_dev, &new_link);
2572 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2574 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2575 struct hns3_pf *pf = &hns->pf;
2577 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2580 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2586 hns3_query_function_status(struct hns3_hw *hw)
2588 #define HNS3_QUERY_MAX_CNT 10
2589 #define HNS3_QUERY_SLEEP_MSCOEND 1
2590 struct hns3_func_status_cmd *req;
2591 struct hns3_cmd_desc desc;
2595 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2596 req = (struct hns3_func_status_cmd *)desc.data;
2599 ret = hns3_cmd_send(hw, &desc, 1);
2601 PMD_INIT_LOG(ERR, "query function status failed %d",
2606 /* Check pf reset is done */
2610 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2611 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2613 return hns3_parse_func_status(hw, req);
2617 hns3_query_pf_resource(struct hns3_hw *hw)
2619 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2620 struct hns3_pf *pf = &hns->pf;
2621 struct hns3_pf_res_cmd *req;
2622 struct hns3_cmd_desc desc;
2625 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2626 ret = hns3_cmd_send(hw, &desc, 1);
2628 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2632 req = (struct hns3_pf_res_cmd *)desc.data;
2633 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2634 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2635 hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2636 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2638 if (req->tx_buf_size)
2640 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2642 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2644 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2646 if (req->dv_buf_size)
2648 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2650 pf->dv_buf_size = HNS3_DEFAULT_DV;
2652 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2655 hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2656 HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2662 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2664 struct hns3_cfg_param_cmd *req;
2665 uint64_t mac_addr_tmp_high;
2666 uint64_t mac_addr_tmp;
2669 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2671 /* get the configuration */
2672 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2673 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2674 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2675 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2676 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2677 HNS3_CFG_TQP_DESC_N_M,
2678 HNS3_CFG_TQP_DESC_N_S);
2680 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2681 HNS3_CFG_PHY_ADDR_M,
2682 HNS3_CFG_PHY_ADDR_S);
2683 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2684 HNS3_CFG_MEDIA_TP_M,
2685 HNS3_CFG_MEDIA_TP_S);
2686 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2687 HNS3_CFG_RX_BUF_LEN_M,
2688 HNS3_CFG_RX_BUF_LEN_S);
2689 /* get mac address */
2690 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2691 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2692 HNS3_CFG_MAC_ADDR_H_M,
2693 HNS3_CFG_MAC_ADDR_H_S);
2695 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2697 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2698 HNS3_CFG_DEFAULT_SPEED_M,
2699 HNS3_CFG_DEFAULT_SPEED_S);
2700 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2701 HNS3_CFG_RSS_SIZE_M,
2702 HNS3_CFG_RSS_SIZE_S);
2704 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2705 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2707 req = (struct hns3_cfg_param_cmd *)desc[1].data;
2708 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2710 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2711 HNS3_CFG_SPEED_ABILITY_M,
2712 HNS3_CFG_SPEED_ABILITY_S);
2713 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2714 HNS3_CFG_UMV_TBL_SPACE_M,
2715 HNS3_CFG_UMV_TBL_SPACE_S);
2716 if (!cfg->umv_space)
2717 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2720 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2721 * @hw: pointer to struct hns3_hw
2722 * @hcfg: the config structure to be getted
2725 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2727 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2728 struct hns3_cfg_param_cmd *req;
2733 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2735 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2736 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2738 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2739 i * HNS3_CFG_RD_LEN_BYTES);
2740 /* Len should be divided by 4 when send to hardware */
2741 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2742 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2743 req->offset = rte_cpu_to_le_32(offset);
2746 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2748 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2752 hns3_parse_cfg(hcfg, desc);
2758 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2760 switch (speed_cmd) {
2761 case HNS3_CFG_SPEED_10M:
2762 *speed = ETH_SPEED_NUM_10M;
2764 case HNS3_CFG_SPEED_100M:
2765 *speed = ETH_SPEED_NUM_100M;
2767 case HNS3_CFG_SPEED_1G:
2768 *speed = ETH_SPEED_NUM_1G;
2770 case HNS3_CFG_SPEED_10G:
2771 *speed = ETH_SPEED_NUM_10G;
2773 case HNS3_CFG_SPEED_25G:
2774 *speed = ETH_SPEED_NUM_25G;
2776 case HNS3_CFG_SPEED_40G:
2777 *speed = ETH_SPEED_NUM_40G;
2779 case HNS3_CFG_SPEED_50G:
2780 *speed = ETH_SPEED_NUM_50G;
2782 case HNS3_CFG_SPEED_100G:
2783 *speed = ETH_SPEED_NUM_100G;
2793 hns3_get_board_configuration(struct hns3_hw *hw)
2795 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2796 struct hns3_pf *pf = &hns->pf;
2797 struct hns3_cfg cfg;
2800 ret = hns3_get_board_cfg(hw, &cfg);
2802 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2806 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2807 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2811 hw->mac.media_type = cfg.media_type;
2812 hw->rss_size_max = cfg.rss_size_max;
2813 hw->rss_dis_flag = false;
2814 hw->rx_buf_len = cfg.rx_buf_len;
2815 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2816 hw->mac.phy_addr = cfg.phy_addr;
2817 hw->mac.default_addr_setted = false;
2818 hw->num_tx_desc = cfg.tqp_desc_num;
2819 hw->num_rx_desc = cfg.tqp_desc_num;
2820 hw->dcb_info.num_pg = 1;
2821 hw->dcb_info.hw_pfc_map = 0;
2823 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2825 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2826 cfg.default_speed, ret);
2830 pf->tc_max = cfg.tc_num;
2831 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2832 PMD_INIT_LOG(WARNING,
2833 "Get TC num(%u) from flash, set TC num to 1",
2838 /* Dev does not support DCB */
2839 if (!hns3_dev_dcb_supported(hw)) {
2843 pf->pfc_max = pf->tc_max;
2845 hw->dcb_info.num_tc = 1;
2846 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2847 hw->tqps_num / hw->dcb_info.num_tc);
2848 hns3_set_bit(hw->hw_tc_map, 0, 1);
2849 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2851 pf->wanted_umv_size = cfg.umv_space;
2857 hns3_get_configuration(struct hns3_hw *hw)
2861 ret = hns3_query_function_status(hw);
2863 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2867 /* Get pf resource */
2868 ret = hns3_query_pf_resource(hw);
2870 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2874 ret = hns3_get_board_configuration(hw);
2876 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2882 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2883 uint16_t tqp_vid, bool is_pf)
2885 struct hns3_tqp_map_cmd *req;
2886 struct hns3_cmd_desc desc;
2889 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2891 req = (struct hns3_tqp_map_cmd *)desc.data;
2892 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2893 req->tqp_vf = func_id;
2894 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2896 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2897 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2899 ret = hns3_cmd_send(hw, &desc, 1);
2901 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2907 hns3_map_tqp(struct hns3_hw *hw)
2909 uint16_t tqps_num = hw->total_tqps_num;
2918 * In current version VF is not supported when PF is driven by DPDK
2919 * driver, so we allocate tqps to PF as much as possible.
2922 num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2923 for (func_id = HNS3_PF_FUNC_ID; func_id < num; func_id++) {
2924 is_pf = func_id == HNS3_PF_FUNC_ID ? true : false;
2926 i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2927 ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2938 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2940 struct hns3_config_mac_speed_dup_cmd *req;
2941 struct hns3_cmd_desc desc;
2944 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2946 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2948 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2951 case ETH_SPEED_NUM_10M:
2952 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2953 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2955 case ETH_SPEED_NUM_100M:
2956 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2957 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2959 case ETH_SPEED_NUM_1G:
2960 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2961 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2963 case ETH_SPEED_NUM_10G:
2964 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2965 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2967 case ETH_SPEED_NUM_25G:
2968 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2969 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2971 case ETH_SPEED_NUM_40G:
2972 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2973 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2975 case ETH_SPEED_NUM_50G:
2976 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2977 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2979 case ETH_SPEED_NUM_100G:
2980 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2981 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2984 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2988 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2990 ret = hns3_cmd_send(hw, &desc, 1);
2992 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2998 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3000 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3001 struct hns3_pf *pf = &hns->pf;
3002 struct hns3_priv_buf *priv;
3003 uint32_t i, total_size;
3005 total_size = pf->pkt_buf_size;
3007 /* alloc tx buffer for all enabled tc */
3008 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3009 priv = &buf_alloc->priv_buf[i];
3011 if (hw->hw_tc_map & BIT(i)) {
3012 if (total_size < pf->tx_buf_size)
3015 priv->tx_buf_size = pf->tx_buf_size;
3017 priv->tx_buf_size = 0;
3019 total_size -= priv->tx_buf_size;
3026 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3028 /* TX buffer size is unit by 128 byte */
3029 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3030 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3031 struct hns3_tx_buff_alloc_cmd *req;
3032 struct hns3_cmd_desc desc;
3037 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3039 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3040 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3041 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3043 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3044 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3045 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3048 ret = hns3_cmd_send(hw, &desc, 1);
3050 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3056 hns3_get_tc_num(struct hns3_hw *hw)
3061 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3062 if (hw->hw_tc_map & BIT(i))
3068 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3070 struct hns3_priv_buf *priv;
3071 uint32_t rx_priv = 0;
3074 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3075 priv = &buf_alloc->priv_buf[i];
3077 rx_priv += priv->buf_size;
3083 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3085 uint32_t total_tx_size = 0;
3088 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3089 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3091 return total_tx_size;
3094 /* Get the number of pfc enabled TCs, which have private buffer */
3096 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3098 struct hns3_priv_buf *priv;
3102 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3103 priv = &buf_alloc->priv_buf[i];
3104 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3111 /* Get the number of pfc disabled TCs, which have private buffer */
3113 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3114 struct hns3_pkt_buf_alloc *buf_alloc)
3116 struct hns3_priv_buf *priv;
3120 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3121 priv = &buf_alloc->priv_buf[i];
3122 if (hw->hw_tc_map & BIT(i) &&
3123 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3131 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3134 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3135 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3136 struct hns3_pf *pf = &hns->pf;
3137 uint32_t shared_buf, aligned_mps;
3142 tc_num = hns3_get_tc_num(hw);
3143 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3145 if (hns3_dev_dcb_supported(hw))
3146 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3149 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3152 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3153 shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3154 HNS3_BUF_SIZE_UNIT);
3156 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3157 if (rx_all < rx_priv + shared_std)
3160 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3161 buf_alloc->s_buf.buf_size = shared_buf;
3162 if (hns3_dev_dcb_supported(hw)) {
3163 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3164 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3165 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3166 HNS3_BUF_SIZE_UNIT);
3168 buf_alloc->s_buf.self.high =
3169 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3170 buf_alloc->s_buf.self.low = aligned_mps;
3173 if (hns3_dev_dcb_supported(hw)) {
3174 hi_thrd = shared_buf - pf->dv_buf_size;
3176 if (tc_num <= NEED_RESERVE_TC_NUM)
3177 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3181 hi_thrd = hi_thrd / tc_num;
3183 hi_thrd = max_t(uint32_t, hi_thrd,
3184 HNS3_BUF_MUL_BY * aligned_mps);
3185 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3186 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3188 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3189 lo_thrd = aligned_mps;
3192 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3193 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3194 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3201 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3202 struct hns3_pkt_buf_alloc *buf_alloc)
3204 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3205 struct hns3_pf *pf = &hns->pf;
3206 struct hns3_priv_buf *priv;
3207 uint32_t aligned_mps;
3211 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3212 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3214 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3215 priv = &buf_alloc->priv_buf[i];
3222 if (!(hw->hw_tc_map & BIT(i)))
3226 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3227 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3228 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3229 HNS3_BUF_SIZE_UNIT);
3232 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3236 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3239 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3243 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3244 struct hns3_pkt_buf_alloc *buf_alloc)
3246 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3247 struct hns3_pf *pf = &hns->pf;
3248 struct hns3_priv_buf *priv;
3249 int no_pfc_priv_num;
3254 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3255 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3257 /* let the last to be cleared first */
3258 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3259 priv = &buf_alloc->priv_buf[i];
3260 mask = BIT((uint8_t)i);
3262 if (hw->hw_tc_map & mask &&
3263 !(hw->dcb_info.hw_pfc_map & mask)) {
3264 /* Clear the no pfc TC private buffer */
3272 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3273 no_pfc_priv_num == 0)
3277 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3281 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3282 struct hns3_pkt_buf_alloc *buf_alloc)
3284 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3285 struct hns3_pf *pf = &hns->pf;
3286 struct hns3_priv_buf *priv;
3292 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3293 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3295 /* let the last to be cleared first */
3296 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3297 priv = &buf_alloc->priv_buf[i];
3298 mask = BIT((uint8_t)i);
3300 if (hw->hw_tc_map & mask &&
3301 hw->dcb_info.hw_pfc_map & mask) {
3302 /* Reduce the number of pfc TC with private buffer */
3309 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3314 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3318 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3319 struct hns3_pkt_buf_alloc *buf_alloc)
3321 #define COMPENSATE_BUFFER 0x3C00
3322 #define COMPENSATE_HALF_MPS_NUM 5
3323 #define PRIV_WL_GAP 0x1800
3324 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3325 struct hns3_pf *pf = &hns->pf;
3326 uint32_t tc_num = hns3_get_tc_num(hw);
3327 uint32_t half_mps = pf->mps >> 1;
3328 struct hns3_priv_buf *priv;
3329 uint32_t min_rx_priv;
3333 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3335 rx_priv = rx_priv / tc_num;
3337 if (tc_num <= NEED_RESERVE_TC_NUM)
3338 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3341 * Minimum value of private buffer in rx direction (min_rx_priv) is
3342 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3343 * buffer if rx_priv is greater than min_rx_priv.
3345 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3346 COMPENSATE_HALF_MPS_NUM * half_mps;
3347 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3348 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3350 if (rx_priv < min_rx_priv)
3353 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3354 priv = &buf_alloc->priv_buf[i];
3361 if (!(hw->hw_tc_map & BIT(i)))
3365 priv->buf_size = rx_priv;
3366 priv->wl.high = rx_priv - pf->dv_buf_size;
3367 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3370 buf_alloc->s_buf.buf_size = 0;
3376 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3377 * @hw: pointer to struct hns3_hw
3378 * @buf_alloc: pointer to buffer calculation data
3379 * @return: 0: calculate sucessful, negative: fail
3382 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3384 /* When DCB is not supported, rx private buffer is not allocated. */
3385 if (!hns3_dev_dcb_supported(hw)) {
3386 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3387 struct hns3_pf *pf = &hns->pf;
3388 uint32_t rx_all = pf->pkt_buf_size;
3390 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3391 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3398 * Try to allocate privated packet buffer for all TCs without share
3401 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3405 * Try to allocate privated packet buffer for all TCs with share
3408 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3412 * For different application scenes, the enabled port number, TC number
3413 * and no_drop TC number are different. In order to obtain the better
3414 * performance, software could allocate the buffer size and configure
3415 * the waterline by tring to decrease the private buffer size according
3416 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3419 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3422 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3425 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3432 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3434 struct hns3_rx_priv_buff_cmd *req;
3435 struct hns3_cmd_desc desc;
3440 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3441 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3443 /* Alloc private buffer TCs */
3444 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3445 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3448 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3449 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3452 buf_size = buf_alloc->s_buf.buf_size;
3453 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3454 (1 << HNS3_TC0_PRI_BUF_EN_B));
3456 ret = hns3_cmd_send(hw, &desc, 1);
3458 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3464 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3466 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3467 struct hns3_rx_priv_wl_buf *req;
3468 struct hns3_priv_buf *priv;
3469 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3473 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3474 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3476 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3478 /* The first descriptor set the NEXT bit to 1 */
3480 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3482 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3484 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3485 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3487 priv = &buf_alloc->priv_buf[idx];
3488 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3490 req->tc_wl[j].high |=
3491 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3492 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3494 req->tc_wl[j].low |=
3495 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3499 /* Send 2 descriptor at one time */
3500 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3502 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3508 hns3_common_thrd_config(struct hns3_hw *hw,
3509 struct hns3_pkt_buf_alloc *buf_alloc)
3511 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3512 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3513 struct hns3_rx_com_thrd *req;
3514 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3515 struct hns3_tc_thrd *tc;
3520 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3521 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3523 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3525 /* The first descriptor set the NEXT bit to 1 */
3527 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3529 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3531 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3532 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3533 tc = &s_buf->tc_thrd[tc_idx];
3535 req->com_thrd[j].high =
3536 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3537 req->com_thrd[j].high |=
3538 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3539 req->com_thrd[j].low =
3540 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3541 req->com_thrd[j].low |=
3542 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3546 /* Send 2 descriptors at one time */
3547 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3549 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3555 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3557 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3558 struct hns3_rx_com_wl *req;
3559 struct hns3_cmd_desc desc;
3562 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3564 req = (struct hns3_rx_com_wl *)desc.data;
3565 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3566 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3568 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3569 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3571 ret = hns3_cmd_send(hw, &desc, 1);
3573 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3579 hns3_buffer_alloc(struct hns3_hw *hw)
3581 struct hns3_pkt_buf_alloc pkt_buf;
3584 memset(&pkt_buf, 0, sizeof(pkt_buf));
3585 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3588 "could not calc tx buffer size for all TCs %d",
3593 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3595 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3599 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3602 "could not calc rx priv buffer size for all TCs %d",
3607 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3609 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3613 if (hns3_dev_dcb_supported(hw)) {
3614 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3617 "could not configure rx private waterline %d",
3622 ret = hns3_common_thrd_config(hw, &pkt_buf);
3625 "could not configure common threshold %d",
3631 ret = hns3_common_wl_config(hw, &pkt_buf);
3633 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3640 hns3_mac_init(struct hns3_hw *hw)
3642 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3643 struct hns3_mac *mac = &hw->mac;
3644 struct hns3_pf *pf = &hns->pf;
3647 pf->support_sfp_query = true;
3648 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3649 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3651 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3655 mac->link_status = ETH_LINK_DOWN;
3657 return hns3_config_mtu(hw, pf->mps);
3661 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3663 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
3664 #define HNS3_ETHERTYPE_ALREADY_ADD 1
3665 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
3666 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
3671 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3676 switch (resp_code) {
3677 case HNS3_ETHERTYPE_SUCCESS_ADD:
3678 case HNS3_ETHERTYPE_ALREADY_ADD:
3681 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3683 "add mac ethertype failed for manager table overflow.");
3684 return_status = -EIO;
3686 case HNS3_ETHERTYPE_KEY_CONFLICT:
3687 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3688 return_status = -EIO;
3692 "add mac ethertype failed for undefined, code=%d.",
3694 return_status = -EIO;
3698 return return_status;
3702 hns3_add_mgr_tbl(struct hns3_hw *hw,
3703 const struct hns3_mac_mgr_tbl_entry_cmd *req)
3705 struct hns3_cmd_desc desc;
3710 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3711 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3713 ret = hns3_cmd_send(hw, &desc, 1);
3716 "add mac ethertype failed for cmd_send, ret =%d.",
3721 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3722 retval = rte_le_to_cpu_16(desc.retval);
3724 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3728 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3729 int *table_item_num)
3731 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3734 * In current version, we add one item in management table as below:
3735 * 0x0180C200000E -- LLDP MC address
3738 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3739 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3740 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3741 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3742 tbl->i_port_bitmap = 0x1;
3743 *table_item_num = 1;
3747 hns3_init_mgr_tbl(struct hns3_hw *hw)
3749 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
3750 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3755 memset(mgr_table, 0, sizeof(mgr_table));
3756 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3757 for (i = 0; i < table_item_num; i++) {
3758 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3760 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3770 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3771 bool en_mc, bool en_bc, int vport_id)
3776 memset(param, 0, sizeof(struct hns3_promisc_param));
3778 param->enable = HNS3_PROMISC_EN_UC;
3780 param->enable |= HNS3_PROMISC_EN_MC;
3782 param->enable |= HNS3_PROMISC_EN_BC;
3783 param->vf_id = vport_id;
3787 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3789 struct hns3_promisc_cfg_cmd *req;
3790 struct hns3_cmd_desc desc;
3793 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3795 req = (struct hns3_promisc_cfg_cmd *)desc.data;
3796 req->vf_id = param->vf_id;
3797 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3798 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3800 ret = hns3_cmd_send(hw, &desc, 1);
3802 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3808 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3810 struct hns3_promisc_param param;
3811 bool en_bc_pmc = true;
3815 * In current version VF is not supported when PF is driven by DPDK
3816 * driver, just need to configure parameters for PF vport.
3818 vf_id = HNS3_PF_FUNC_ID;
3820 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3821 return hns3_cmd_set_promisc_mode(hw, ¶m);
3825 hns3_promisc_init(struct hns3_hw *hw)
3827 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3828 struct hns3_pf *pf = &hns->pf;
3829 struct hns3_promisc_param param;
3833 ret = hns3_set_promisc_mode(hw, false, false);
3835 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
3840 * In current version VFs are not supported when PF is driven by DPDK
3841 * driver. After PF has been taken over by DPDK, the original VF will
3842 * be invalid. So, there is a possibility of entry residues. It should
3843 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
3846 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
3847 hns3_promisc_param_init(¶m, false, false, false, func_id);
3848 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
3850 PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode,"
3851 " ret = %d", func_id, ret);
3860 hns3_promisc_uninit(struct hns3_hw *hw)
3862 struct hns3_promisc_param param;
3866 func_id = HNS3_PF_FUNC_ID;
3869 * In current version VFs are not supported when PF is driven by
3870 * DPDK driver, and VFs' promisc mode status has been cleared during
3871 * init and their status will not change. So just clear PF's promisc
3872 * mode status during uninit.
3874 hns3_promisc_param_init(¶m, false, false, false, func_id);
3875 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
3877 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
3878 " uninit, ret = %d", ret);
3882 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3884 bool allmulti = dev->data->all_multicast ? true : false;
3885 struct hns3_adapter *hns = dev->data->dev_private;
3886 struct hns3_hw *hw = &hns->hw;
3891 rte_spinlock_lock(&hw->lock);
3892 ret = hns3_set_promisc_mode(hw, true, true);
3894 rte_spinlock_unlock(&hw->lock);
3895 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
3901 * When promiscuous mode was enabled, disable the vlan filter to let
3902 * all packets coming in in the receiving direction.
3904 offloads = dev->data->dev_conf.rxmode.offloads;
3905 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3906 ret = hns3_enable_vlan_filter(hns, false);
3908 hns3_err(hw, "failed to enable promiscuous mode due to "
3909 "failure to disable vlan filter, ret = %d",
3911 err = hns3_set_promisc_mode(hw, false, allmulti);
3913 hns3_err(hw, "failed to restore promiscuous "
3914 "status after disable vlan filter "
3915 "failed during enabling promiscuous "
3916 "mode, ret = %d", ret);
3920 rte_spinlock_unlock(&hw->lock);
3926 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3928 bool allmulti = dev->data->all_multicast ? true : false;
3929 struct hns3_adapter *hns = dev->data->dev_private;
3930 struct hns3_hw *hw = &hns->hw;
3935 /* If now in all_multicast mode, must remain in all_multicast mode. */
3936 rte_spinlock_lock(&hw->lock);
3937 ret = hns3_set_promisc_mode(hw, false, allmulti);
3939 rte_spinlock_unlock(&hw->lock);
3940 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
3944 /* when promiscuous mode was disabled, restore the vlan filter status */
3945 offloads = dev->data->dev_conf.rxmode.offloads;
3946 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3947 ret = hns3_enable_vlan_filter(hns, true);
3949 hns3_err(hw, "failed to disable promiscuous mode due to"
3950 " failure to restore vlan filter, ret = %d",
3952 err = hns3_set_promisc_mode(hw, true, true);
3954 hns3_err(hw, "failed to restore promiscuous "
3955 "status after enabling vlan filter "
3956 "failed during disabling promiscuous "
3957 "mode, ret = %d", ret);
3960 rte_spinlock_unlock(&hw->lock);
3966 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3968 struct hns3_adapter *hns = dev->data->dev_private;
3969 struct hns3_hw *hw = &hns->hw;
3972 if (dev->data->promiscuous)
3975 rte_spinlock_lock(&hw->lock);
3976 ret = hns3_set_promisc_mode(hw, false, true);
3977 rte_spinlock_unlock(&hw->lock);
3979 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
3986 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3988 struct hns3_adapter *hns = dev->data->dev_private;
3989 struct hns3_hw *hw = &hns->hw;
3992 /* If now in promiscuous mode, must remain in all_multicast mode. */
3993 if (dev->data->promiscuous)
3996 rte_spinlock_lock(&hw->lock);
3997 ret = hns3_set_promisc_mode(hw, false, false);
3998 rte_spinlock_unlock(&hw->lock);
4000 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4007 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4009 struct hns3_hw *hw = &hns->hw;
4010 bool allmulti = hw->data->all_multicast ? true : false;
4013 if (hw->data->promiscuous) {
4014 ret = hns3_set_promisc_mode(hw, true, true);
4016 hns3_err(hw, "failed to restore promiscuous mode, "
4021 ret = hns3_set_promisc_mode(hw, false, allmulti);
4023 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4029 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4031 struct hns3_sfp_speed_cmd *resp;
4032 struct hns3_cmd_desc desc;
4035 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4036 resp = (struct hns3_sfp_speed_cmd *)desc.data;
4037 ret = hns3_cmd_send(hw, &desc, 1);
4038 if (ret == -EOPNOTSUPP) {
4039 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4042 hns3_err(hw, "get sfp speed failed %d", ret);
4046 *speed = resp->sfp_speed;
4052 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4054 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4055 duplex = ETH_LINK_FULL_DUPLEX;
4061 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4063 struct hns3_mac *mac = &hw->mac;
4066 duplex = hns3_check_speed_dup(duplex, speed);
4067 if (mac->link_speed == speed && mac->link_duplex == duplex)
4070 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4074 mac->link_speed = speed;
4075 mac->link_duplex = duplex;
4081 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4083 struct hns3_adapter *hns = eth_dev->data->dev_private;
4084 struct hns3_hw *hw = &hns->hw;
4085 struct hns3_pf *pf = &hns->pf;
4089 /* If IMP do not support get SFP/qSFP speed, return directly */
4090 if (!pf->support_sfp_query)
4093 ret = hns3_get_sfp_speed(hw, &speed);
4094 if (ret == -EOPNOTSUPP) {
4095 pf->support_sfp_query = false;
4100 if (speed == ETH_SPEED_NUM_NONE)
4101 return 0; /* do nothing if no SFP */
4103 /* Config full duplex for SFP */
4104 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4108 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4110 struct hns3_config_mac_mode_cmd *req;
4111 struct hns3_cmd_desc desc;
4112 uint32_t loop_en = 0;
4116 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4118 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4121 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4122 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4123 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4124 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4125 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4126 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4127 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4128 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4129 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4130 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4131 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4132 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4133 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4134 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4135 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4137 ret = hns3_cmd_send(hw, &desc, 1);
4139 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4145 hns3_get_mac_link_status(struct hns3_hw *hw)
4147 struct hns3_link_status_cmd *req;
4148 struct hns3_cmd_desc desc;
4152 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4153 ret = hns3_cmd_send(hw, &desc, 1);
4155 hns3_err(hw, "get link status cmd failed %d", ret);
4156 return ETH_LINK_DOWN;
4159 req = (struct hns3_link_status_cmd *)desc.data;
4160 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4162 return !!link_status;
4166 hns3_update_link_status(struct hns3_hw *hw)
4170 state = hns3_get_mac_link_status(hw);
4171 if (state != hw->mac.link_status) {
4172 hw->mac.link_status = state;
4173 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4178 hns3_service_handler(void *param)
4180 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4181 struct hns3_adapter *hns = eth_dev->data->dev_private;
4182 struct hns3_hw *hw = &hns->hw;
4184 if (!hns3_is_reset_pending(hns)) {
4185 hns3_update_speed_duplex(eth_dev);
4186 hns3_update_link_status(hw);
4188 hns3_warn(hw, "Cancel the query when reset is pending");
4190 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4194 hns3_init_hardware(struct hns3_adapter *hns)
4196 struct hns3_hw *hw = &hns->hw;
4199 ret = hns3_map_tqp(hw);
4201 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4205 ret = hns3_init_umv_space(hw);
4207 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4211 ret = hns3_mac_init(hw);
4213 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4217 ret = hns3_init_mgr_tbl(hw);
4219 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4223 ret = hns3_promisc_init(hw);
4225 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4230 ret = hns3_init_vlan_config(hns);
4232 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4236 ret = hns3_dcb_init(hw);
4238 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4242 ret = hns3_init_fd_config(hns);
4244 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4248 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4250 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4254 ret = hns3_config_gro(hw, false);
4256 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4261 * In the initialization clearing the all hardware mapping relationship
4262 * configurations between queues and interrupt vectors is needed, so
4263 * some error caused by the residual configurations, such as the
4264 * unexpected interrupt, can be avoid.
4266 ret = hns3_init_ring_with_vector(hw);
4268 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4275 hns3_uninit_umv_space(hw);
4280 hns3_init_pf(struct rte_eth_dev *eth_dev)
4282 struct rte_device *dev = eth_dev->device;
4283 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4284 struct hns3_adapter *hns = eth_dev->data->dev_private;
4285 struct hns3_hw *hw = &hns->hw;
4288 PMD_INIT_FUNC_TRACE();
4290 /* Get hardware io base address from pcie BAR2 IO space */
4291 hw->io_base = pci_dev->mem_resource[2].addr;
4293 /* Firmware command queue initialize */
4294 ret = hns3_cmd_init_queue(hw);
4296 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4297 goto err_cmd_init_queue;
4300 hns3_clear_all_event_cause(hw);
4302 /* Firmware command initialize */
4303 ret = hns3_cmd_init(hw);
4305 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4309 ret = rte_intr_callback_register(&pci_dev->intr_handle,
4310 hns3_interrupt_handler,
4313 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4314 goto err_intr_callback_register;
4317 /* Enable interrupt */
4318 rte_intr_enable(&pci_dev->intr_handle);
4319 hns3_pf_enable_irq0(hw);
4321 /* Get configuration */
4322 ret = hns3_get_configuration(hw);
4324 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4325 goto err_get_config;
4328 ret = hns3_init_hardware(hns);
4330 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4331 goto err_get_config;
4334 /* Initialize flow director filter list & hash */
4335 ret = hns3_fdir_filter_init(hns);
4337 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4341 hns3_set_default_rss_args(hw);
4343 ret = hns3_enable_hw_error_intr(hns, true);
4345 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4353 hns3_fdir_filter_uninit(hns);
4355 hns3_uninit_umv_space(hw);
4358 hns3_pf_disable_irq0(hw);
4359 rte_intr_disable(&pci_dev->intr_handle);
4360 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4362 err_intr_callback_register:
4364 hns3_cmd_uninit(hw);
4365 hns3_cmd_destroy_queue(hw);
4373 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4375 struct hns3_adapter *hns = eth_dev->data->dev_private;
4376 struct rte_device *dev = eth_dev->device;
4377 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4378 struct hns3_hw *hw = &hns->hw;
4380 PMD_INIT_FUNC_TRACE();
4382 hns3_enable_hw_error_intr(hns, false);
4383 hns3_rss_uninit(hns);
4384 hns3_promisc_uninit(hw);
4385 hns3_fdir_filter_uninit(hns);
4386 hns3_uninit_umv_space(hw);
4387 hns3_pf_disable_irq0(hw);
4388 rte_intr_disable(&pci_dev->intr_handle);
4389 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4391 hns3_cmd_uninit(hw);
4392 hns3_cmd_destroy_queue(hw);
4397 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4399 struct hns3_hw *hw = &hns->hw;
4402 ret = hns3_dcb_cfg_update(hns);
4407 ret = hns3_start_queues(hns, reset_queue);
4409 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4414 ret = hns3_cfg_mac_mode(hw, true);
4416 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4417 goto err_config_mac_mode;
4421 err_config_mac_mode:
4422 hns3_stop_queues(hns, true);
4427 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4429 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4430 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4431 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4432 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4433 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4434 uint32_t intr_vector;
4438 if (dev->data->dev_conf.intr_conf.rxq == 0)
4441 /* disable uio/vfio intr/eventfd mapping */
4442 rte_intr_disable(intr_handle);
4444 /* check and configure queue intr-vector mapping */
4445 if (rte_intr_cap_multiple(intr_handle) ||
4446 !RTE_ETH_DEV_SRIOV(dev).active) {
4447 intr_vector = hw->used_rx_queues;
4448 /* creates event fd for each intr vector when MSIX is used */
4449 if (rte_intr_efd_enable(intr_handle, intr_vector))
4452 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4453 intr_handle->intr_vec =
4454 rte_zmalloc("intr_vec",
4455 hw->used_rx_queues * sizeof(int), 0);
4456 if (intr_handle->intr_vec == NULL) {
4457 hns3_err(hw, "Failed to allocate %d rx_queues"
4458 " intr_vec", hw->used_rx_queues);
4460 goto alloc_intr_vec_error;
4464 if (rte_intr_allow_others(intr_handle)) {
4465 vec = RTE_INTR_VEC_RXTX_OFFSET;
4466 base = RTE_INTR_VEC_RXTX_OFFSET;
4468 if (rte_intr_dp_is_en(intr_handle)) {
4469 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4470 ret = hns3_bind_ring_with_vector(hw, vec, true,
4474 goto bind_vector_error;
4475 intr_handle->intr_vec[q_id] = vec;
4476 if (vec < base + intr_handle->nb_efd - 1)
4480 rte_intr_enable(intr_handle);
4484 rte_intr_efd_disable(intr_handle);
4485 if (intr_handle->intr_vec) {
4486 free(intr_handle->intr_vec);
4487 intr_handle->intr_vec = NULL;
4490 alloc_intr_vec_error:
4491 rte_intr_efd_disable(intr_handle);
4496 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4498 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4499 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4500 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4504 if (dev->data->dev_conf.intr_conf.rxq == 0)
4507 if (rte_intr_dp_is_en(intr_handle)) {
4508 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4509 ret = hns3_bind_ring_with_vector(hw,
4510 intr_handle->intr_vec[q_id], true,
4511 HNS3_RING_TYPE_RX, q_id);
4521 hns3_restore_filter(struct rte_eth_dev *dev)
4523 hns3_restore_rss_filter(dev);
4527 hns3_dev_start(struct rte_eth_dev *dev)
4529 struct hns3_adapter *hns = dev->data->dev_private;
4530 struct hns3_hw *hw = &hns->hw;
4533 PMD_INIT_FUNC_TRACE();
4534 if (rte_atomic16_read(&hw->reset.resetting))
4537 rte_spinlock_lock(&hw->lock);
4538 hw->adapter_state = HNS3_NIC_STARTING;
4540 ret = hns3_do_start(hns, true);
4542 hw->adapter_state = HNS3_NIC_CONFIGURED;
4543 rte_spinlock_unlock(&hw->lock);
4546 ret = hns3_map_rx_interrupt(dev);
4548 hw->adapter_state = HNS3_NIC_CONFIGURED;
4549 rte_spinlock_unlock(&hw->lock);
4553 hw->adapter_state = HNS3_NIC_STARTED;
4554 rte_spinlock_unlock(&hw->lock);
4556 hns3_set_rxtx_function(dev);
4557 hns3_mp_req_start_rxtx(dev);
4558 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4560 hns3_restore_filter(dev);
4562 /* Enable interrupt of all rx queues before enabling queues */
4563 hns3_dev_all_rx_queue_intr_enable(hw, true);
4565 * When finished the initialization, enable queues to receive/transmit
4568 hns3_enable_all_queues(hw, true);
4570 hns3_info(hw, "hns3 dev start successful!");
4575 hns3_do_stop(struct hns3_adapter *hns)
4577 struct hns3_hw *hw = &hns->hw;
4581 ret = hns3_cfg_mac_mode(hw, false);
4584 hw->mac.link_status = ETH_LINK_DOWN;
4586 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4587 hns3_configure_all_mac_addr(hns, true);
4590 reset_queue = false;
4591 hw->mac.default_addr_setted = false;
4592 return hns3_stop_queues(hns, reset_queue);
4596 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4598 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4599 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4600 struct hns3_adapter *hns = dev->data->dev_private;
4601 struct hns3_hw *hw = &hns->hw;
4602 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4603 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4606 if (dev->data->dev_conf.intr_conf.rxq == 0)
4609 /* unmap the ring with vector */
4610 if (rte_intr_allow_others(intr_handle)) {
4611 vec = RTE_INTR_VEC_RXTX_OFFSET;
4612 base = RTE_INTR_VEC_RXTX_OFFSET;
4614 if (rte_intr_dp_is_en(intr_handle)) {
4615 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4616 (void)hns3_bind_ring_with_vector(hw, vec, false,
4619 if (vec < base + intr_handle->nb_efd - 1)
4623 /* Clean datapath event and queue/vec mapping */
4624 rte_intr_efd_disable(intr_handle);
4625 if (intr_handle->intr_vec) {
4626 rte_free(intr_handle->intr_vec);
4627 intr_handle->intr_vec = NULL;
4632 hns3_dev_stop(struct rte_eth_dev *dev)
4634 struct hns3_adapter *hns = dev->data->dev_private;
4635 struct hns3_hw *hw = &hns->hw;
4637 PMD_INIT_FUNC_TRACE();
4639 hw->adapter_state = HNS3_NIC_STOPPING;
4640 hns3_set_rxtx_function(dev);
4642 /* Disable datapath on secondary process. */
4643 hns3_mp_req_stop_rxtx(dev);
4644 /* Prevent crashes when queues are still in use. */
4645 rte_delay_ms(hw->tqps_num);
4647 rte_spinlock_lock(&hw->lock);
4648 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4650 hns3_unmap_rx_interrupt(dev);
4651 hns3_dev_release_mbufs(hns);
4652 hw->adapter_state = HNS3_NIC_CONFIGURED;
4654 rte_eal_alarm_cancel(hns3_service_handler, dev);
4655 rte_spinlock_unlock(&hw->lock);
4659 hns3_dev_close(struct rte_eth_dev *eth_dev)
4661 struct hns3_adapter *hns = eth_dev->data->dev_private;
4662 struct hns3_hw *hw = &hns->hw;
4664 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4665 rte_free(eth_dev->process_private);
4666 eth_dev->process_private = NULL;
4670 if (hw->adapter_state == HNS3_NIC_STARTED)
4671 hns3_dev_stop(eth_dev);
4673 hw->adapter_state = HNS3_NIC_CLOSING;
4674 hns3_reset_abort(hns);
4675 hw->adapter_state = HNS3_NIC_CLOSED;
4677 hns3_configure_all_mc_mac_addr(hns, true);
4678 hns3_remove_all_vlan_table(hns);
4679 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4680 hns3_uninit_pf(eth_dev);
4681 hns3_free_all_queues(eth_dev);
4682 rte_free(hw->reset.wait_data);
4683 rte_free(eth_dev->process_private);
4684 eth_dev->process_private = NULL;
4685 hns3_mp_uninit_primary();
4686 hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4690 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4692 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4693 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4695 fc_conf->pause_time = pf->pause_time;
4697 /* return fc current mode */
4698 switch (hw->current_mode) {
4700 fc_conf->mode = RTE_FC_FULL;
4702 case HNS3_FC_TX_PAUSE:
4703 fc_conf->mode = RTE_FC_TX_PAUSE;
4705 case HNS3_FC_RX_PAUSE:
4706 fc_conf->mode = RTE_FC_RX_PAUSE;
4710 fc_conf->mode = RTE_FC_NONE;
4718 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4722 hw->requested_mode = HNS3_FC_NONE;
4724 case RTE_FC_RX_PAUSE:
4725 hw->requested_mode = HNS3_FC_RX_PAUSE;
4727 case RTE_FC_TX_PAUSE:
4728 hw->requested_mode = HNS3_FC_TX_PAUSE;
4731 hw->requested_mode = HNS3_FC_FULL;
4734 hw->requested_mode = HNS3_FC_NONE;
4735 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4736 "configured to RTE_FC_NONE", mode);
4742 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4744 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4745 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4748 if (fc_conf->high_water || fc_conf->low_water ||
4749 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4750 hns3_err(hw, "Unsupported flow control settings specified, "
4751 "high_water(%u), low_water(%u), send_xon(%u) and "
4752 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4753 fc_conf->high_water, fc_conf->low_water,
4754 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4757 if (fc_conf->autoneg) {
4758 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4761 if (!fc_conf->pause_time) {
4762 hns3_err(hw, "Invalid pause time %d setting.",
4763 fc_conf->pause_time);
4767 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4768 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4769 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4770 "current_fc_status = %d", hw->current_fc_status);
4774 hns3_get_fc_mode(hw, fc_conf->mode);
4775 if (hw->requested_mode == hw->current_mode &&
4776 pf->pause_time == fc_conf->pause_time)
4779 rte_spinlock_lock(&hw->lock);
4780 ret = hns3_fc_enable(dev, fc_conf);
4781 rte_spinlock_unlock(&hw->lock);
4787 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4788 struct rte_eth_pfc_conf *pfc_conf)
4790 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4791 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4795 if (!hns3_dev_dcb_supported(hw)) {
4796 hns3_err(hw, "This port does not support dcb configurations.");
4800 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4801 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4802 hns3_err(hw, "Unsupported flow control settings specified, "
4803 "high_water(%u), low_water(%u), send_xon(%u) and "
4804 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4805 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4806 pfc_conf->fc.send_xon,
4807 pfc_conf->fc.mac_ctrl_frame_fwd);
4810 if (pfc_conf->fc.autoneg) {
4811 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4814 if (pfc_conf->fc.pause_time == 0) {
4815 hns3_err(hw, "Invalid pause time %d setting.",
4816 pfc_conf->fc.pause_time);
4820 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4821 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4822 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4823 "current_fc_status = %d", hw->current_fc_status);
4827 priority = pfc_conf->priority;
4828 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4829 if (hw->dcb_info.pfc_en & BIT(priority) &&
4830 hw->requested_mode == hw->current_mode &&
4831 pfc_conf->fc.pause_time == pf->pause_time)
4834 rte_spinlock_lock(&hw->lock);
4835 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4836 rte_spinlock_unlock(&hw->lock);
4842 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4844 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4846 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4849 rte_spinlock_lock(&hw->lock);
4850 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4851 dcb_info->nb_tcs = pf->local_max_tc;
4853 dcb_info->nb_tcs = 1;
4855 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4856 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4857 for (i = 0; i < dcb_info->nb_tcs; i++)
4858 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4860 for (i = 0; i < hw->num_tc; i++) {
4861 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4862 dcb_info->tc_queue.tc_txq[0][i].base =
4863 hw->tc_queue[i].tqp_offset;
4864 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4865 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4866 hw->tc_queue[i].tqp_count;
4868 rte_spinlock_unlock(&hw->lock);
4874 hns3_reinit_dev(struct hns3_adapter *hns)
4876 struct hns3_hw *hw = &hns->hw;
4879 ret = hns3_cmd_init(hw);
4881 hns3_err(hw, "Failed to init cmd: %d", ret);
4885 ret = hns3_reset_all_queues(hns);
4887 hns3_err(hw, "Failed to reset all queues: %d", ret);
4891 ret = hns3_init_hardware(hns);
4893 hns3_err(hw, "Failed to init hardware: %d", ret);
4897 ret = hns3_enable_hw_error_intr(hns, true);
4899 hns3_err(hw, "fail to enable hw error interrupts: %d",
4903 hns3_info(hw, "Reset done, driver initialization finished.");
4909 is_pf_reset_done(struct hns3_hw *hw)
4911 uint32_t val, reg, reg_bit;
4913 switch (hw->reset.level) {
4914 case HNS3_IMP_RESET:
4915 reg = HNS3_GLOBAL_RESET_REG;
4916 reg_bit = HNS3_IMP_RESET_BIT;
4918 case HNS3_GLOBAL_RESET:
4919 reg = HNS3_GLOBAL_RESET_REG;
4920 reg_bit = HNS3_GLOBAL_RESET_BIT;
4922 case HNS3_FUNC_RESET:
4923 reg = HNS3_FUN_RST_ING;
4924 reg_bit = HNS3_FUN_RST_ING_B;
4926 case HNS3_FLR_RESET:
4928 hns3_err(hw, "Wait for unsupported reset level: %d",
4932 val = hns3_read_dev(hw, reg);
4933 if (hns3_get_bit(val, reg_bit))
4940 hns3_is_reset_pending(struct hns3_adapter *hns)
4942 struct hns3_hw *hw = &hns->hw;
4943 enum hns3_reset_level reset;
4945 hns3_check_event_cause(hns, NULL);
4946 reset = hns3_get_reset_level(hns, &hw->reset.pending);
4947 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4948 hns3_warn(hw, "High level reset %d is pending", reset);
4951 reset = hns3_get_reset_level(hns, &hw->reset.request);
4952 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4953 hns3_warn(hw, "High level reset %d is request", reset);
4960 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4962 struct hns3_hw *hw = &hns->hw;
4963 struct hns3_wait_data *wait_data = hw->reset.wait_data;
4966 if (wait_data->result == HNS3_WAIT_SUCCESS)
4968 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4969 gettimeofday(&tv, NULL);
4970 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4971 tv.tv_sec, tv.tv_usec);
4973 } else if (wait_data->result == HNS3_WAIT_REQUEST)
4976 wait_data->hns = hns;
4977 wait_data->check_completion = is_pf_reset_done;
4978 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4979 HNS3_RESET_WAIT_MS + get_timeofday_ms();
4980 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4981 wait_data->count = HNS3_RESET_WAIT_CNT;
4982 wait_data->result = HNS3_WAIT_REQUEST;
4983 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4988 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4990 struct hns3_cmd_desc desc;
4991 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4993 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4994 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4995 req->fun_reset_vfid = func_id;
4997 return hns3_cmd_send(hw, &desc, 1);
5001 hns3_imp_reset_cmd(struct hns3_hw *hw)
5003 struct hns3_cmd_desc desc;
5005 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5006 desc.data[0] = 0xeedd;
5008 return hns3_cmd_send(hw, &desc, 1);
5012 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5014 struct hns3_hw *hw = &hns->hw;
5018 gettimeofday(&tv, NULL);
5019 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5020 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5021 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5022 tv.tv_sec, tv.tv_usec);
5026 switch (reset_level) {
5027 case HNS3_IMP_RESET:
5028 hns3_imp_reset_cmd(hw);
5029 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5030 tv.tv_sec, tv.tv_usec);
5032 case HNS3_GLOBAL_RESET:
5033 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5034 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5035 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5036 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5037 tv.tv_sec, tv.tv_usec);
5039 case HNS3_FUNC_RESET:
5040 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5041 tv.tv_sec, tv.tv_usec);
5042 /* schedule again to check later */
5043 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5044 hns3_schedule_reset(hns);
5047 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5050 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5053 static enum hns3_reset_level
5054 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5056 struct hns3_hw *hw = &hns->hw;
5057 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5059 /* Return the highest priority reset level amongst all */
5060 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5061 reset_level = HNS3_IMP_RESET;
5062 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5063 reset_level = HNS3_GLOBAL_RESET;
5064 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5065 reset_level = HNS3_FUNC_RESET;
5066 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5067 reset_level = HNS3_FLR_RESET;
5069 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5070 return HNS3_NONE_RESET;
5076 hns3_prepare_reset(struct hns3_adapter *hns)
5078 struct hns3_hw *hw = &hns->hw;
5082 switch (hw->reset.level) {
5083 case HNS3_FUNC_RESET:
5084 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5089 * After performaning pf reset, it is not necessary to do the
5090 * mailbox handling or send any command to firmware, because
5091 * any mailbox handling or command to firmware is only valid
5092 * after hns3_cmd_init is called.
5094 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5095 hw->reset.stats.request_cnt++;
5097 case HNS3_IMP_RESET:
5098 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5099 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5100 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5109 hns3_set_rst_done(struct hns3_hw *hw)
5111 struct hns3_pf_rst_done_cmd *req;
5112 struct hns3_cmd_desc desc;
5114 req = (struct hns3_pf_rst_done_cmd *)desc.data;
5115 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5116 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5117 return hns3_cmd_send(hw, &desc, 1);
5121 hns3_stop_service(struct hns3_adapter *hns)
5123 struct hns3_hw *hw = &hns->hw;
5124 struct rte_eth_dev *eth_dev;
5126 eth_dev = &rte_eth_devices[hw->data->port_id];
5127 if (hw->adapter_state == HNS3_NIC_STARTED)
5128 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5129 hw->mac.link_status = ETH_LINK_DOWN;
5131 hns3_set_rxtx_function(eth_dev);
5133 /* Disable datapath on secondary process. */
5134 hns3_mp_req_stop_rxtx(eth_dev);
5135 rte_delay_ms(hw->tqps_num);
5137 rte_spinlock_lock(&hw->lock);
5138 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5139 hw->adapter_state == HNS3_NIC_STOPPING) {
5141 hw->reset.mbuf_deferred_free = true;
5143 hw->reset.mbuf_deferred_free = false;
5146 * It is cumbersome for hardware to pick-and-choose entries for deletion
5147 * from table space. Hence, for function reset software intervention is
5148 * required to delete the entries
5150 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5151 hns3_configure_all_mc_mac_addr(hns, true);
5152 rte_spinlock_unlock(&hw->lock);
5158 hns3_start_service(struct hns3_adapter *hns)
5160 struct hns3_hw *hw = &hns->hw;
5161 struct rte_eth_dev *eth_dev;
5163 if (hw->reset.level == HNS3_IMP_RESET ||
5164 hw->reset.level == HNS3_GLOBAL_RESET)
5165 hns3_set_rst_done(hw);
5166 eth_dev = &rte_eth_devices[hw->data->port_id];
5167 hns3_set_rxtx_function(eth_dev);
5168 hns3_mp_req_start_rxtx(eth_dev);
5169 if (hw->adapter_state == HNS3_NIC_STARTED) {
5170 hns3_service_handler(eth_dev);
5172 /* Enable interrupt of all rx queues before enabling queues */
5173 hns3_dev_all_rx_queue_intr_enable(hw, true);
5175 * When finished the initialization, enable queues to receive
5176 * and transmit packets.
5178 hns3_enable_all_queues(hw, true);
5185 hns3_restore_conf(struct hns3_adapter *hns)
5187 struct hns3_hw *hw = &hns->hw;
5190 ret = hns3_configure_all_mac_addr(hns, false);
5194 ret = hns3_configure_all_mc_mac_addr(hns, false);
5198 ret = hns3_dev_promisc_restore(hns);
5202 ret = hns3_restore_vlan_table(hns);
5206 ret = hns3_restore_vlan_conf(hns);
5210 ret = hns3_restore_all_fdir_filter(hns);
5214 ret = hns3_restore_rx_interrupt(hw);
5218 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5219 ret = hns3_do_start(hns, false);
5222 hns3_info(hw, "hns3 dev restart successful!");
5223 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5224 hw->adapter_state = HNS3_NIC_CONFIGURED;
5228 hns3_configure_all_mc_mac_addr(hns, true);
5230 hns3_configure_all_mac_addr(hns, true);
5235 hns3_reset_service(void *param)
5237 struct hns3_adapter *hns = (struct hns3_adapter *)param;
5238 struct hns3_hw *hw = &hns->hw;
5239 enum hns3_reset_level reset_level;
5240 struct timeval tv_delta;
5241 struct timeval tv_start;
5247 * The interrupt is not triggered within the delay time.
5248 * The interrupt may have been lost. It is necessary to handle
5249 * the interrupt to recover from the error.
5251 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5252 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5253 hns3_err(hw, "Handling interrupts in delayed tasks");
5254 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5255 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5256 if (reset_level == HNS3_NONE_RESET) {
5257 hns3_err(hw, "No reset level is set, try IMP reset");
5258 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5261 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5264 * Check if there is any ongoing reset in the hardware. This status can
5265 * be checked from reset_pending. If there is then, we need to wait for
5266 * hardware to complete reset.
5267 * a. If we are able to figure out in reasonable time that hardware
5268 * has fully resetted then, we can proceed with driver, client
5270 * b. else, we can come back later to check this status so re-sched
5273 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5274 if (reset_level != HNS3_NONE_RESET) {
5275 gettimeofday(&tv_start, NULL);
5276 ret = hns3_reset_process(hns, reset_level);
5277 gettimeofday(&tv, NULL);
5278 timersub(&tv, &tv_start, &tv_delta);
5279 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5280 tv_delta.tv_usec / USEC_PER_MSEC;
5281 if (msec > HNS3_RESET_PROCESS_MS)
5282 hns3_err(hw, "%d handle long time delta %" PRIx64
5283 " ms time=%ld.%.6ld",
5284 hw->reset.level, msec,
5285 tv.tv_sec, tv.tv_usec);
5290 /* Check if we got any *new* reset requests to be honored */
5291 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5292 if (reset_level != HNS3_NONE_RESET)
5293 hns3_msix_process(hns, reset_level);
5296 static const struct eth_dev_ops hns3_eth_dev_ops = {
5297 .dev_start = hns3_dev_start,
5298 .dev_stop = hns3_dev_stop,
5299 .dev_close = hns3_dev_close,
5300 .promiscuous_enable = hns3_dev_promiscuous_enable,
5301 .promiscuous_disable = hns3_dev_promiscuous_disable,
5302 .allmulticast_enable = hns3_dev_allmulticast_enable,
5303 .allmulticast_disable = hns3_dev_allmulticast_disable,
5304 .mtu_set = hns3_dev_mtu_set,
5305 .stats_get = hns3_stats_get,
5306 .stats_reset = hns3_stats_reset,
5307 .xstats_get = hns3_dev_xstats_get,
5308 .xstats_get_names = hns3_dev_xstats_get_names,
5309 .xstats_reset = hns3_dev_xstats_reset,
5310 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
5311 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5312 .dev_infos_get = hns3_dev_infos_get,
5313 .fw_version_get = hns3_fw_version_get,
5314 .rx_queue_setup = hns3_rx_queue_setup,
5315 .tx_queue_setup = hns3_tx_queue_setup,
5316 .rx_queue_release = hns3_dev_rx_queue_release,
5317 .tx_queue_release = hns3_dev_tx_queue_release,
5318 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
5319 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
5320 .dev_configure = hns3_dev_configure,
5321 .flow_ctrl_get = hns3_flow_ctrl_get,
5322 .flow_ctrl_set = hns3_flow_ctrl_set,
5323 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5324 .mac_addr_add = hns3_add_mac_addr,
5325 .mac_addr_remove = hns3_remove_mac_addr,
5326 .mac_addr_set = hns3_set_default_mac_addr,
5327 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
5328 .link_update = hns3_dev_link_update,
5329 .rss_hash_update = hns3_dev_rss_hash_update,
5330 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
5331 .reta_update = hns3_dev_rss_reta_update,
5332 .reta_query = hns3_dev_rss_reta_query,
5333 .filter_ctrl = hns3_dev_filter_ctrl,
5334 .vlan_filter_set = hns3_vlan_filter_set,
5335 .vlan_tpid_set = hns3_vlan_tpid_set,
5336 .vlan_offload_set = hns3_vlan_offload_set,
5337 .vlan_pvid_set = hns3_vlan_pvid_set,
5338 .get_reg = hns3_get_regs,
5339 .get_dcb_info = hns3_get_dcb_info,
5340 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5343 static const struct hns3_reset_ops hns3_reset_ops = {
5344 .reset_service = hns3_reset_service,
5345 .stop_service = hns3_stop_service,
5346 .prepare_reset = hns3_prepare_reset,
5347 .wait_hardware_ready = hns3_wait_hardware_ready,
5348 .reinit_dev = hns3_reinit_dev,
5349 .restore_conf = hns3_restore_conf,
5350 .start_service = hns3_start_service,
5354 hns3_dev_init(struct rte_eth_dev *eth_dev)
5356 struct rte_device *dev = eth_dev->device;
5357 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5358 struct hns3_adapter *hns = eth_dev->data->dev_private;
5359 struct hns3_hw *hw = &hns->hw;
5360 uint16_t device_id = pci_dev->id.device_id;
5364 PMD_INIT_FUNC_TRACE();
5366 /* Get PCI revision id */
5367 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
5368 HNS3_PCI_REVISION_ID);
5369 if (ret != HNS3_PCI_REVISION_ID_LEN) {
5370 PMD_INIT_LOG(ERR, "Failed to read pci revision id, ret = %d",
5374 hw->revision = revision;
5376 eth_dev->process_private = (struct hns3_process_private *)
5377 rte_zmalloc_socket("hns3_filter_list",
5378 sizeof(struct hns3_process_private),
5379 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5380 if (eth_dev->process_private == NULL) {
5381 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5384 /* initialize flow filter lists */
5385 hns3_filterlist_init(eth_dev);
5387 hns3_set_rxtx_function(eth_dev);
5388 eth_dev->dev_ops = &hns3_eth_dev_ops;
5389 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5390 hns3_mp_init_secondary();
5391 hw->secondary_cnt++;
5395 hns3_mp_init_primary();
5396 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5398 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5399 device_id == HNS3_DEV_ID_50GE_RDMA ||
5400 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5401 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5404 hw->data = eth_dev->data;
5407 * Set default max packet size according to the mtu
5408 * default vale in DPDK frame.
5410 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5412 ret = hns3_reset_init(hw);
5414 goto err_init_reset;
5415 hw->reset.ops = &hns3_reset_ops;
5417 ret = hns3_init_pf(eth_dev);
5419 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5423 /* Allocate memory for storing MAC addresses */
5424 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5425 sizeof(struct rte_ether_addr) *
5426 HNS3_UC_MACADDR_NUM, 0);
5427 if (eth_dev->data->mac_addrs == NULL) {
5428 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5429 "to store MAC addresses",
5430 sizeof(struct rte_ether_addr) *
5431 HNS3_UC_MACADDR_NUM);
5433 goto err_rte_zmalloc;
5436 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5437 ð_dev->data->mac_addrs[0]);
5439 hw->adapter_state = HNS3_NIC_INITIALIZED;
5441 * Pass the information to the rte_eth_dev_close() that it should also
5442 * release the private port resources.
5444 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5446 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5447 hns3_err(hw, "Reschedule reset service after dev_init");
5448 hns3_schedule_reset(hns);
5450 /* IMP will wait ready flag before reset */
5451 hns3_notify_reset_ready(hw, false);
5454 hns3_info(hw, "hns3 dev initialization successful!");
5458 hns3_uninit_pf(eth_dev);
5461 rte_free(hw->reset.wait_data);
5463 eth_dev->dev_ops = NULL;
5464 eth_dev->rx_pkt_burst = NULL;
5465 eth_dev->tx_pkt_burst = NULL;
5466 eth_dev->tx_pkt_prepare = NULL;
5467 rte_free(eth_dev->process_private);
5468 eth_dev->process_private = NULL;
5473 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5475 struct hns3_adapter *hns = eth_dev->data->dev_private;
5476 struct hns3_hw *hw = &hns->hw;
5478 PMD_INIT_FUNC_TRACE();
5480 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5483 eth_dev->dev_ops = NULL;
5484 eth_dev->rx_pkt_burst = NULL;
5485 eth_dev->tx_pkt_burst = NULL;
5486 eth_dev->tx_pkt_prepare = NULL;
5487 if (hw->adapter_state < HNS3_NIC_CLOSING)
5488 hns3_dev_close(eth_dev);
5490 hw->adapter_state = HNS3_NIC_REMOVED;
5495 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5496 struct rte_pci_device *pci_dev)
5498 return rte_eth_dev_pci_generic_probe(pci_dev,
5499 sizeof(struct hns3_adapter),
5504 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5506 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5509 static const struct rte_pci_id pci_id_hns3_map[] = {
5510 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5511 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5512 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5513 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5514 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5515 { .vendor_id = 0, /* sentinel */ },
5518 static struct rte_pci_driver rte_hns3_pmd = {
5519 .id_table = pci_id_hns3_map,
5520 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5521 .probe = eth_hns3_pci_probe,
5522 .remove = eth_hns3_pci_remove,
5525 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5526 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5527 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5529 RTE_INIT(hns3_init_log)
5531 hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5532 if (hns3_logtype_init >= 0)
5533 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5534 hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5535 if (hns3_logtype_driver >= 0)
5536 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);