drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static void
  83 hns3_pf_disable_irq0(struct hns3_hw *hw)
  84 {
  85         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  86 }
  87
  88 static void
  89 hns3_pf_enable_irq0(struct hns3_hw *hw)
  90 {
  91         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  92 }
  93
  94 static enum hns3_evt_cause
  95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  96 {
  97         struct hns3_hw *hw = &hns->hw;
  98         uint32_t vector0_int_stats;
  99         uint32_t cmdq_src_val;
 100         uint32_t val;
 101         enum hns3_evt_cause ret;
 102
 103         /* fetch the events from their corresponding regs */
 104         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 105         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 106
 107         /*
 108          * Assumption: If by any chance reset and mailbox events are reported
 109          * together then we will only process reset event and defer the
 110          * processing of the mailbox events. Since, we would have not cleared
 111          * RX CMDQ event this time we would receive again another interrupt
 112          * from H/W just for the mailbox.
 113          */
 114         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 115                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 116                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 117                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 118                 if (clearval) {
 119                         hw->reset.stats.imp_cnt++;
 120                         hns3_warn(hw, "IMP reset detected, clear reset status");
 121                 } else {
 122                         hns3_schedule_delayed_reset(hns);
 123                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 124                 }
 125
 126                 ret = HNS3_VECTOR0_EVENT_RST;
 127                 goto out;
 128         }
 129
 130         /* Global reset */
 131         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 132                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 133                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 134                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 135                 if (clearval) {
 136                         hw->reset.stats.global_cnt++;
 137                         hns3_warn(hw, "Global reset detected, clear reset status");
 138                 } else {
 139                         hns3_schedule_delayed_reset(hns);
 140                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 141                 }
 142
 143                 ret = HNS3_VECTOR0_EVENT_RST;
 144                 goto out;
 145         }
 146
 147         /* check for vector0 msix event source */
 148         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 149                 val = vector0_int_stats;
 150                 ret = HNS3_VECTOR0_EVENT_ERR;
 151                 goto out;
 152         }
 153
 154         /* check for vector0 mailbox(=CMDQ RX) event source */
 155         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 156                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 157                 val = cmdq_src_val;
 158                 ret = HNS3_VECTOR0_EVENT_MBX;
 159                 goto out;
 160         }
 161
 162         if (clearval && (vector0_int_stats || cmdq_src_val))
 163                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 164                           vector0_int_stats, cmdq_src_val);
 165         val = vector0_int_stats;
 166         ret = HNS3_VECTOR0_EVENT_OTHER;
 167 out:
 168
 169         if (clearval)
 170                 *clearval = val;
 171         return ret;
 172 }
 173
 174 static void
 175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 176 {
 177         if (event_type == HNS3_VECTOR0_EVENT_RST)
 178                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 179         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 180                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 181 }
 182
 183 static void
 184 hns3_clear_all_event_cause(struct hns3_hw *hw)
 185 {
 186         uint32_t vector0_int_stats;
 187         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 188
 189         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 190                 hns3_warn(hw, "Probe during IMP reset interrupt");
 191
 192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 193                 hns3_warn(hw, "Probe during Global reset interrupt");
 194
 195         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 196                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 197                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 198                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 199         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 200 }
 201
 202 static void
 203 hns3_interrupt_handler(void *param)
 204 {
 205         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 206         struct hns3_adapter *hns = dev->data->dev_private;
 207         struct hns3_hw *hw = &hns->hw;
 208         enum hns3_evt_cause event_cause;
 209         uint32_t clearval = 0;
 210
 211         /* Disable interrupt */
 212         hns3_pf_disable_irq0(hw);
 213
 214         event_cause = hns3_check_event_cause(hns, &clearval);
 215
 216         /* vector 0 interrupt is shared with reset and mailbox source events. */
 217         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 218                 hns3_handle_msix_error(hns, &hw->reset.request);
 219                 hns3_schedule_reset(hns);
 220         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 221                 hns3_schedule_reset(hns);
 222         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 223                 hns3_dev_handle_mbx_msg(hw);
 224         else
 225                 hns3_err(hw, "Received unknown event");
 226
 227         hns3_clear_event_cause(hw, event_cause, clearval);
 228         /* Enable interrupt if it is not cause by reset */
 229         hns3_pf_enable_irq0(hw);
 230 }
 231
 232 static int
 233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 234 {
 235 #define HNS3_VLAN_OFFSET_160            160
 236         struct hns3_vlan_filter_pf_cfg_cmd *req;
 237         struct hns3_hw *hw = &hns->hw;
 238         uint8_t vlan_offset_byte_val;
 239         struct hns3_cmd_desc desc;
 240         uint8_t vlan_offset_byte;
 241         uint8_t vlan_offset_160;
 242         int ret;
 243
 244         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 245
 246         vlan_offset_160 = vlan_id / HNS3_VLAN_OFFSET_160;
 247         vlan_offset_byte = (vlan_id % HNS3_VLAN_OFFSET_160) / 8;
 248         vlan_offset_byte_val = 1 << (vlan_id % 8);
 249
 250         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 251         req->vlan_offset = vlan_offset_160;
 252         req->vlan_cfg = on ? 0 : 1;
 253         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 254
 255         ret = hns3_cmd_send(hw, &desc, 1);
 256         if (ret)
 257                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 258                          vlan_id, ret);
 259
 260         return ret;
 261 }
 262
 263 static void
 264 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 265 {
 266         struct hns3_user_vlan_table *vlan_entry;
 267         struct hns3_pf *pf = &hns->pf;
 268
 269         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 270                 if (vlan_entry->vlan_id == vlan_id) {
 271                         if (vlan_entry->hd_tbl_status)
 272                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 273                         LIST_REMOVE(vlan_entry, next);
 274                         rte_free(vlan_entry);
 275                         break;
 276                 }
 277         }
 278 }
 279
 280 static void
 281 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 282                         bool writen_to_tbl)
 283 {
 284         struct hns3_user_vlan_table *vlan_entry;
 285         struct hns3_hw *hw = &hns->hw;
 286         struct hns3_pf *pf = &hns->pf;
 287
 288         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 289                 if (vlan_entry->vlan_id == vlan_id)
 290                         return;
 291         }
 292
 293         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 294         if (vlan_entry == NULL) {
 295                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 296                 return;
 297         }
 298
 299         vlan_entry->hd_tbl_status = writen_to_tbl;
 300         vlan_entry->vlan_id = vlan_id;
 301
 302         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 303 }
 304
 305 static int
 306 hns3_restore_vlan_table(struct hns3_adapter *hns)
 307 {
 308         struct hns3_user_vlan_table *vlan_entry;
 309         struct hns3_pf *pf = &hns->pf;
 310         uint16_t vlan_id;
 311         int ret = 0;
 312
 313         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) {
 314                 ret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid,
 315                                                1);
 316                 return ret;
 317         }
 318
 319         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 320                 if (vlan_entry->hd_tbl_status) {
 321                         vlan_id = vlan_entry->vlan_id;
 322                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 323                         if (ret)
 324                                 break;
 325                 }
 326         }
 327
 328         return ret;
 329 }
 330
 331 static int
 332 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 333 {
 334         struct hns3_pf *pf = &hns->pf;
 335         bool writen_to_tbl = false;
 336         int ret = 0;
 337
 338         /*
 339          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 340          * for normal packet, deleting vlan id 0 is not allowed.
 341          */
 342         if (on == 0 && vlan_id == 0)
 343                 return 0;
 344
 345         /*
 346          * When port base vlan enabled, we use port base vlan as the vlan
 347          * filter condition. In this case, we don't update vlan filter table
 348          * when user add new vlan or remove exist vlan, just update the
 349          * vlan list. The vlan id in vlan list will be writen in vlan filter
 350          * table until port base vlan disabled
 351          */
 352         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 353                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 354                 writen_to_tbl = true;
 355         }
 356
 357         if (ret == 0 && vlan_id) {
 358                 if (on)
 359                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 360                 else
 361                         hns3_rm_dev_vlan_table(hns, vlan_id);
 362         }
 363         return ret;
 364 }
 365
 366 static int
 367 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 368 {
 369         struct hns3_adapter *hns = dev->data->dev_private;
 370         struct hns3_hw *hw = &hns->hw;
 371         int ret;
 372
 373         rte_spinlock_lock(&hw->lock);
 374         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 375         rte_spinlock_unlock(&hw->lock);
 376         return ret;
 377 }
 378
 379 static int
 380 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 381                          uint16_t tpid)
 382 {
 383         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 384         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 385         struct hns3_hw *hw = &hns->hw;
 386         struct hns3_cmd_desc desc;
 387         int ret;
 388
 389         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 390              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 391                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 392                 return -EINVAL;
 393         }
 394
 395         if (tpid != RTE_ETHER_TYPE_VLAN) {
 396                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 397                 return -EINVAL;
 398         }
 399
 400         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 401         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 402
 403         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 404                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 405                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 406         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 407                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 408                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 409                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411         }
 412
 413         ret = hns3_cmd_send(hw, &desc, 1);
 414         if (ret) {
 415                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 416                          ret);
 417                 return ret;
 418         }
 419
 420         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 421
 422         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 423         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 424         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 425
 426         ret = hns3_cmd_send(hw, &desc, 1);
 427         if (ret)
 428                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 429                          ret);
 430         return ret;
 431 }
 432
 433 static int
 434 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 435                    uint16_t tpid)
 436 {
 437         struct hns3_adapter *hns = dev->data->dev_private;
 438         struct hns3_hw *hw = &hns->hw;
 439         int ret;
 440
 441         rte_spinlock_lock(&hw->lock);
 442         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 443         rte_spinlock_unlock(&hw->lock);
 444         return ret;
 445 }
 446
 447 static int
 448 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 449                              struct hns3_rx_vtag_cfg *vcfg)
 450 {
 451         struct hns3_vport_vtag_rx_cfg_cmd *req;
 452         struct hns3_hw *hw = &hns->hw;
 453         struct hns3_cmd_desc desc;
 454         uint16_t vport_id;
 455         uint8_t bitmap;
 456         int ret;
 457
 458         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 459
 460         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 461         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 462                      vcfg->strip_tag1_en ? 1 : 0);
 463         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 464                      vcfg->strip_tag2_en ? 1 : 0);
 465         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 466                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 467         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 468                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 469
 470         /*
 471          * In current version VF is not supported when PF is driven by DPDK
 472          * driver, the PF-related vf_id is 0, just need to configure parameters
 473          * for vport_id 0.
 474          */
 475         vport_id = 0;
 476         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 477         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 478         req->vf_bitmap[req->vf_offset] = bitmap;
 479
 480         ret = hns3_cmd_send(hw, &desc, 1);
 481         if (ret)
 482                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 483         return ret;
 484 }
 485
 486 static void
 487 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 488                            struct hns3_rx_vtag_cfg *vcfg)
 489 {
 490         struct hns3_pf *pf = &hns->pf;
 491         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 492 }
 493
 494 static void
 495 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 496                            struct hns3_tx_vtag_cfg *vcfg)
 497 {
 498         struct hns3_pf *pf = &hns->pf;
 499         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 500 }
 501
 502 static int
 503 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 504 {
 505         struct hns3_rx_vtag_cfg rxvlan_cfg;
 506         struct hns3_pf *pf = &hns->pf;
 507         struct hns3_hw *hw = &hns->hw;
 508         int ret;
 509
 510         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 511                 rxvlan_cfg.strip_tag1_en = false;
 512                 rxvlan_cfg.strip_tag2_en = enable;
 513         } else {
 514                 rxvlan_cfg.strip_tag1_en = enable;
 515                 rxvlan_cfg.strip_tag2_en = true;
 516         }
 517
 518         rxvlan_cfg.vlan1_vlan_prionly = false;
 519         rxvlan_cfg.vlan2_vlan_prionly = false;
 520         rxvlan_cfg.rx_vlan_offload_en = enable;
 521
 522         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 523         if (ret) {
 524                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 525                 return ret;
 526         }
 527
 528         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 529
 530         return ret;
 531 }
 532
 533 static int
 534 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 535                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 536 {
 537         struct hns3_vlan_filter_ctrl_cmd *req;
 538         struct hns3_cmd_desc desc;
 539         int ret;
 540
 541         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 542
 543         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 544         req->vlan_type = vlan_type;
 545         req->vlan_fe = filter_en ? fe_type : 0;
 546         req->vf_id = vf_id;
 547
 548         ret = hns3_cmd_send(hw, &desc, 1);
 549         if (ret)
 550                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 551
 552         return ret;
 553 }
 554
 555 static int
 556 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 557 {
 558         struct hns3_hw *hw = &hns->hw;
 559         int ret;
 560
 561         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 562                                         HNS3_FILTER_FE_EGRESS, false, 0);
 563         if (ret) {
 564                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 565                 return ret;
 566         }
 567
 568         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 569                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 570         if (ret)
 571                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 572
 573         return ret;
 574 }
 575
 576 static int
 577 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 578 {
 579         struct hns3_adapter *hns = dev->data->dev_private;
 580         struct hns3_hw *hw = &hns->hw;
 581         struct rte_eth_rxmode *rxmode;
 582         unsigned int tmp_mask;
 583         bool enable;
 584         int ret = 0;
 585
 586         rte_spinlock_lock(&hw->lock);
 587         rxmode = &dev->data->dev_conf.rxmode;
 588         tmp_mask = (unsigned int)mask;
 589         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 590                 /* Enable or disable VLAN stripping */
 591                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 592                     true : false;
 593
 594                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 595                 if (ret) {
 596                         rte_spinlock_unlock(&hw->lock);
 597                         hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
 598                         return ret;
 599                 }
 600         }
 601
 602         rte_spinlock_unlock(&hw->lock);
 603
 604         return ret;
 605 }
 606
 607 static int
 608 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 609                              struct hns3_tx_vtag_cfg *vcfg)
 610 {
 611         struct hns3_vport_vtag_tx_cfg_cmd *req;
 612         struct hns3_cmd_desc desc;
 613         struct hns3_hw *hw = &hns->hw;
 614         uint16_t vport_id;
 615         uint8_t bitmap;
 616         int ret;
 617
 618         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 619
 620         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 621         req->def_vlan_tag1 = vcfg->default_tag1;
 622         req->def_vlan_tag2 = vcfg->default_tag2;
 623         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 624                      vcfg->accept_tag1 ? 1 : 0);
 625         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 626                      vcfg->accept_untag1 ? 1 : 0);
 627         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 628                      vcfg->accept_tag2 ? 1 : 0);
 629         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 630                      vcfg->accept_untag2 ? 1 : 0);
 631         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 632                      vcfg->insert_tag1_en ? 1 : 0);
 633         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 634                      vcfg->insert_tag2_en ? 1 : 0);
 635         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 636
 637         /*
 638          * In current version VF is not supported when PF is driven by DPDK
 639          * driver, the PF-related vf_id is 0, just need to configure parameters
 640          * for vport_id 0.
 641          */
 642         vport_id = 0;
 643         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 644         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 645         req->vf_bitmap[req->vf_offset] = bitmap;
 646
 647         ret = hns3_cmd_send(hw, &desc, 1);
 648         if (ret)
 649                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 650
 651         return ret;
 652 }
 653
 654 static int
 655 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 656                      uint16_t pvid)
 657 {
 658         struct hns3_hw *hw = &hns->hw;
 659         struct hns3_tx_vtag_cfg txvlan_cfg;
 660         int ret;
 661
 662         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 663                 txvlan_cfg.accept_tag1 = true;
 664                 txvlan_cfg.insert_tag1_en = false;
 665                 txvlan_cfg.default_tag1 = 0;
 666         } else {
 667                 txvlan_cfg.accept_tag1 = false;
 668                 txvlan_cfg.insert_tag1_en = true;
 669                 txvlan_cfg.default_tag1 = pvid;
 670         }
 671
 672         txvlan_cfg.accept_untag1 = true;
 673         txvlan_cfg.accept_tag2 = true;
 674         txvlan_cfg.accept_untag2 = true;
 675         txvlan_cfg.insert_tag2_en = false;
 676         txvlan_cfg.default_tag2 = 0;
 677
 678         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 679         if (ret) {
 680                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 681                          ret);
 682                 return ret;
 683         }
 684
 685         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 686         return ret;
 687 }
 688
 689 static void
 690 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 691 {
 692         struct hns3_pf *pf = &hns->pf;
 693
 694         pf->port_base_vlan_cfg.state = on ?
 695             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 696
 697         pf->port_base_vlan_cfg.pvid = pvid;
 698 }
 699
 700 static void
 701 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 702 {
 703         struct hns3_user_vlan_table *vlan_entry;
 704         struct hns3_pf *pf = &hns->pf;
 705
 706         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 707                 if (vlan_entry->hd_tbl_status)
 708                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 709
 710                 vlan_entry->hd_tbl_status = false;
 711         }
 712
 713         if (is_del_list) {
 714                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 715                 while (vlan_entry) {
 716                         LIST_REMOVE(vlan_entry, next);
 717                         rte_free(vlan_entry);
 718                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 719                 }
 720         }
 721 }
 722
 723 static void
 724 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 725 {
 726         struct hns3_user_vlan_table *vlan_entry;
 727         struct hns3_pf *pf = &hns->pf;
 728
 729         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 730                 if (!vlan_entry->hd_tbl_status)
 731                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 732
 733                 vlan_entry->hd_tbl_status = true;
 734         }
 735 }
 736
 737 static void
 738 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 739 {
 740         struct hns3_hw *hw = &hns->hw;
 741         struct hns3_pf *pf = &hns->pf;
 742         int ret;
 743
 744         hns3_rm_all_vlan_table(hns, true);
 745         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 746                 ret = hns3_set_port_vlan_filter(hns,
 747                                                 pf->port_base_vlan_cfg.pvid, 0);
 748                 if (ret) {
 749                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 750                                  ret);
 751                         return;
 752                 }
 753         }
 754 }
 755
 756 static int
 757 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 758                                 uint16_t port_base_vlan_state,
 759                                 uint16_t new_pvid, uint16_t old_pvid)
 760 {
 761         struct hns3_pf *pf = &hns->pf;
 762         struct hns3_hw *hw = &hns->hw;
 763         int ret = 0;
 764
 765         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 766                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 767                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 768                         if (ret) {
 769                                 hns3_err(hw,
 770                                          "Failed to clear clear old pvid filter, ret =%d",
 771                                          ret);
 772                                 return ret;
 773                         }
 774                 }
 775
 776                 hns3_rm_all_vlan_table(hns, false);
 777                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 778         }
 779
 780         if (new_pvid != 0) {
 781                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 782                 if (ret) {
 783                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 784                                  ret);
 785                         return ret;
 786                 }
 787         }
 788
 789         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 790                 hns3_add_all_vlan_table(hns);
 791
 792         return ret;
 793 }
 794
 795 static int
 796 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 797 {
 798         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 799         struct hns3_hw *hw = &hns->hw;
 800         bool rx_strip_en;
 801         int ret;
 802
 803         rx_strip_en = on ? true : false;
 804         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 805         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 806         rx_vlan_cfg.vlan1_vlan_prionly = false;
 807         rx_vlan_cfg.vlan2_vlan_prionly = false;
 808         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 809
 810         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 811         if (ret) {
 812                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 813                 return ret;
 814         }
 815
 816         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 817         return ret;
 818 }
 819
 820 static int
 821 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 822 {
 823         struct hns3_pf *pf = &hns->pf;
 824         struct hns3_hw *hw = &hns->hw;
 825         uint16_t port_base_vlan_state;
 826         uint16_t old_pvid;
 827         int ret;
 828
 829         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 830                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 831                         hns3_warn(hw, "Invalid operation! As current pvid set "
 832                                   "is %u, disable pvid %u is invalid",
 833                                   pf->port_base_vlan_cfg.pvid, pvid);
 834                 return 0;
 835         }
 836
 837         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 838                                     HNS3_PORT_BASE_VLAN_DISABLE;
 839         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 840         if (ret) {
 841                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 842                 return ret;
 843         }
 844
 845         ret = hns3_en_rx_strip_all(hns, on);
 846         if (ret) {
 847                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 848                 return ret;
 849         }
 850
 851         if (pvid == HNS3_INVLID_PVID)
 852                 goto out;
 853         old_pvid = pf->port_base_vlan_cfg.pvid;
 854         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 855                                               old_pvid);
 856         if (ret) {
 857                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 858                          ret);
 859                 return ret;
 860         }
 861
 862 out:
 863         hns3_store_port_base_vlan_info(hns, pvid, on);
 864         return ret;
 865 }
 866
 867 static int
 868 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 869 {
 870         struct hns3_adapter *hns = dev->data->dev_private;
 871         struct hns3_hw *hw = &hns->hw;
 872         int ret;
 873
 874         rte_spinlock_lock(&hw->lock);
 875         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 876         rte_spinlock_unlock(&hw->lock);
 877         return ret;
 878 }
 879
 880 static void
 881 init_port_base_vlan_info(struct hns3_hw *hw)
 882 {
 883         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 884         struct hns3_pf *pf = &hns->pf;
 885
 886         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 887         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 888 }
 889
 890 static int
 891 hns3_default_vlan_config(struct hns3_adapter *hns)
 892 {
 893         struct hns3_hw *hw = &hns->hw;
 894         int ret;
 895
 896         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 897         if (ret)
 898                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 899         return ret;
 900 }
 901
 902 static int
 903 hns3_init_vlan_config(struct hns3_adapter *hns)
 904 {
 905         struct hns3_hw *hw = &hns->hw;
 906         int ret;
 907
 908         /*
 909          * This function can be called in the initialization and reset process,
 910          * when in reset process, it means that hardware had been reseted
 911          * successfully and we need to restore the hardware configuration to
 912          * ensure that the hardware configuration remains unchanged before and
 913          * after reset.
 914          */
 915         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 916                 init_port_base_vlan_info(hw);
 917
 918         ret = hns3_enable_vlan_filter(hns, true);
 919         if (ret) {
 920                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 921                 return ret;
 922         }
 923
 924         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 925                                        RTE_ETHER_TYPE_VLAN);
 926         if (ret) {
 927                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 928                 return ret;
 929         }
 930
 931         /*
 932          * When in the reinit dev stage of the reset process, the following
 933          * vlan-related configurations may differ from those at initialization,
 934          * we will restore configurations to hardware in hns3_restore_vlan_table
 935          * and hns3_restore_vlan_conf later.
 936          */
 937         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 938                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 939                 if (ret) {
 940                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 941                         return ret;
 942                 }
 943
 944                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 945                 if (ret) {
 946                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 947                                  ret);
 948                         return ret;
 949                 }
 950         }
 951
 952         return hns3_default_vlan_config(hns);
 953 }
 954
 955 static int
 956 hns3_restore_vlan_conf(struct hns3_adapter *hns)
 957 {
 958         struct hns3_pf *pf = &hns->pf;
 959         struct hns3_hw *hw = &hns->hw;
 960         int ret;
 961
 962         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
 963         if (ret) {
 964                 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
 965                 return ret;
 966         }
 967
 968         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
 969         if (ret)
 970                 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
 971
 972         return ret;
 973 }
 974
 975 static int
 976 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
 977 {
 978         struct hns3_adapter *hns = dev->data->dev_private;
 979         struct rte_eth_dev_data *data = dev->data;
 980         struct rte_eth_txmode *txmode;
 981         struct hns3_hw *hw = &hns->hw;
 982         int ret;
 983
 984         txmode = &data->dev_conf.txmode;
 985         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
 986                 hns3_warn(hw,
 987                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
 988                           "configuration is not supported! Ignore these two "
 989                           "parameters: hw_vlan_reject_tagged(%d), "
 990                           "hw_vlan_reject_untagged(%d)",
 991                           txmode->hw_vlan_reject_tagged,
 992                           txmode->hw_vlan_reject_untagged);
 993
 994         /* Apply vlan offload setting */
 995         ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
 996         if (ret) {
 997                 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
 998                 return ret;
 999         }
1000
1001         /* Apply pvid setting */
1002         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1003                                  txmode->hw_vlan_insert_pvid);
1004         if (ret)
1005                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
1006                          txmode->pvid, ret);
1007
1008         return ret;
1009 }
1010
1011 static int
1012 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1013                 unsigned int tso_mss_max)
1014 {
1015         struct hns3_cfg_tso_status_cmd *req;
1016         struct hns3_cmd_desc desc;
1017         uint16_t tso_mss;
1018
1019         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1020
1021         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1022
1023         tso_mss = 0;
1024         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1025                        tso_mss_min);
1026         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1027
1028         tso_mss = 0;
1029         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1030                        tso_mss_max);
1031         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1032
1033         return hns3_cmd_send(hw, &desc, 1);
1034 }
1035
1036 int
1037 hns3_config_gro(struct hns3_hw *hw, bool en)
1038 {
1039         struct hns3_cfg_gro_status_cmd *req;
1040         struct hns3_cmd_desc desc;
1041         int ret;
1042
1043         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1044         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1045
1046         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1047
1048         ret = hns3_cmd_send(hw, &desc, 1);
1049         if (ret)
1050                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1051
1052         return ret;
1053 }
1054
1055 static int
1056 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1057                    uint16_t *allocated_size, bool is_alloc)
1058 {
1059         struct hns3_umv_spc_alc_cmd *req;
1060         struct hns3_cmd_desc desc;
1061         int ret;
1062
1063         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1064         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1065         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1066         req->space_size = rte_cpu_to_le_32(space_size);
1067
1068         ret = hns3_cmd_send(hw, &desc, 1);
1069         if (ret) {
1070                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1071                              is_alloc ? "allocate" : "free", ret);
1072                 return ret;
1073         }
1074
1075         if (is_alloc && allocated_size)
1076                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1077
1078         return 0;
1079 }
1080
1081 static int
1082 hns3_init_umv_space(struct hns3_hw *hw)
1083 {
1084         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1085         struct hns3_pf *pf = &hns->pf;
1086         uint16_t allocated_size = 0;
1087         int ret;
1088
1089         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1090                                  true);
1091         if (ret)
1092                 return ret;
1093
1094         if (allocated_size < pf->wanted_umv_size)
1095                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1096                              pf->wanted_umv_size, allocated_size);
1097
1098         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1099                                                 pf->wanted_umv_size;
1100         pf->used_umv_size = 0;
1101         return 0;
1102 }
1103
1104 static int
1105 hns3_uninit_umv_space(struct hns3_hw *hw)
1106 {
1107         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1108         struct hns3_pf *pf = &hns->pf;
1109         int ret;
1110
1111         if (pf->max_umv_size == 0)
1112                 return 0;
1113
1114         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1115         if (ret)
1116                 return ret;
1117
1118         pf->max_umv_size = 0;
1119
1120         return 0;
1121 }
1122
1123 static bool
1124 hns3_is_umv_space_full(struct hns3_hw *hw)
1125 {
1126         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1127         struct hns3_pf *pf = &hns->pf;
1128         bool is_full;
1129
1130         is_full = (pf->used_umv_size >= pf->max_umv_size);
1131
1132         return is_full;
1133 }
1134
1135 static void
1136 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1137 {
1138         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1139         struct hns3_pf *pf = &hns->pf;
1140
1141         if (is_free) {
1142                 if (pf->used_umv_size > 0)
1143                         pf->used_umv_size--;
1144         } else
1145                 pf->used_umv_size++;
1146 }
1147
1148 static void
1149 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1150                       const uint8_t *addr, bool is_mc)
1151 {
1152         const unsigned char *mac_addr = addr;
1153         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1154                             ((uint32_t)mac_addr[2] << 16) |
1155                             ((uint32_t)mac_addr[1] << 8) |
1156                             (uint32_t)mac_addr[0];
1157         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1158
1159         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1160         if (is_mc) {
1161                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1162                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1163                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1164         }
1165
1166         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1167         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1168 }
1169
1170 static int
1171 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1172                              uint8_t resp_code,
1173                              enum hns3_mac_vlan_tbl_opcode op)
1174 {
1175         if (cmdq_resp) {
1176                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1177                          cmdq_resp);
1178                 return -EIO;
1179         }
1180
1181         if (op == HNS3_MAC_VLAN_ADD) {
1182                 if (resp_code == 0 || resp_code == 1) {
1183                         return 0;
1184                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1185                         hns3_err(hw, "add mac addr failed for uc_overflow");
1186                         return -ENOSPC;
1187                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1188                         hns3_err(hw, "add mac addr failed for mc_overflow");
1189                         return -ENOSPC;
1190                 }
1191
1192                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1193                          resp_code);
1194                 return -EIO;
1195         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1196                 if (resp_code == 0) {
1197                         return 0;
1198                 } else if (resp_code == 1) {
1199                         hns3_dbg(hw, "remove mac addr failed for miss");
1200                         return -ENOENT;
1201                 }
1202
1203                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1204                          resp_code);
1205                 return -EIO;
1206         } else if (op == HNS3_MAC_VLAN_LKUP) {
1207                 if (resp_code == 0) {
1208                         return 0;
1209                 } else if (resp_code == 1) {
1210                         hns3_dbg(hw, "lookup mac addr failed for miss");
1211                         return -ENOENT;
1212                 }
1213
1214                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1215                          resp_code);
1216                 return -EIO;
1217         }
1218
1219         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1220                  op);
1221
1222         return -EINVAL;
1223 }
1224
1225 static int
1226 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1227                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1228                          struct hns3_cmd_desc *desc, bool is_mc)
1229 {
1230         uint8_t resp_code;
1231         uint16_t retval;
1232         int ret;
1233
1234         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1235         if (is_mc) {
1236                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1237                 memcpy(desc[0].data, req,
1238                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1239                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1240                                           true);
1241                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1242                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1243                                           true);
1244                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1245         } else {
1246                 memcpy(desc[0].data, req,
1247                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1248                 ret = hns3_cmd_send(hw, desc, 1);
1249         }
1250         if (ret) {
1251                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1252                          ret);
1253                 return ret;
1254         }
1255         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1256         retval = rte_le_to_cpu_16(desc[0].retval);
1257
1258         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1259                                             HNS3_MAC_VLAN_LKUP);
1260 }
1261
1262 static int
1263 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1264                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1265                       struct hns3_cmd_desc *mc_desc)
1266 {
1267         uint8_t resp_code;
1268         uint16_t retval;
1269         int cfg_status;
1270         int ret;
1271
1272         if (mc_desc == NULL) {
1273                 struct hns3_cmd_desc desc;
1274
1275                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1276                 memcpy(desc.data, req,
1277                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1278                 ret = hns3_cmd_send(hw, &desc, 1);
1279                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1280                 retval = rte_le_to_cpu_16(desc.retval);
1281
1282                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1283                                                           HNS3_MAC_VLAN_ADD);
1284         } else {
1285                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1286                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1287                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1288                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1289                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1290                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1291                 memcpy(mc_desc[0].data, req,
1292                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1293                 mc_desc[0].retval = 0;
1294                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1295                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1296                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1297
1298                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1299                                                           HNS3_MAC_VLAN_ADD);
1300         }
1301
1302         if (ret) {
1303                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1304                 return ret;
1305         }
1306
1307         return cfg_status;
1308 }
1309
1310 static int
1311 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1312                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1313 {
1314         struct hns3_cmd_desc desc;
1315         uint8_t resp_code;
1316         uint16_t retval;
1317         int ret;
1318
1319         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1320
1321         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1322
1323         ret = hns3_cmd_send(hw, &desc, 1);
1324         if (ret) {
1325                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1326                 return ret;
1327         }
1328         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1329         retval = rte_le_to_cpu_16(desc.retval);
1330
1331         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1332                                             HNS3_MAC_VLAN_REMOVE);
1333 }
1334
1335 static int
1336 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1337 {
1338         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1339         struct hns3_mac_vlan_tbl_entry_cmd req;
1340         struct hns3_pf *pf = &hns->pf;
1341         struct hns3_cmd_desc desc;
1342         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1343         uint16_t egress_port = 0;
1344         uint8_t vf_id;
1345         int ret;
1346
1347         /* check if mac addr is valid */
1348         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1349                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1350                                       mac_addr);
1351                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1352                          mac_str);
1353                 return -EINVAL;
1354         }
1355
1356         memset(&req, 0, sizeof(req));
1357
1358         /*
1359          * In current version VF is not supported when PF is driven by DPDK
1360          * driver, the PF-related vf_id is 0, just need to configure parameters
1361          * for vf_id 0.
1362          */
1363         vf_id = 0;
1364         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1365                        HNS3_MAC_EPORT_VFID_S, vf_id);
1366
1367         req.egress_port = rte_cpu_to_le_16(egress_port);
1368
1369         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1370
1371         /*
1372          * Lookup the mac address in the mac_vlan table, and add
1373          * it if the entry is inexistent. Repeated unicast entry
1374          * is not allowed in the mac vlan table.
1375          */
1376         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1377         if (ret == -ENOENT) {
1378                 if (!hns3_is_umv_space_full(hw)) {
1379                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1380                         if (!ret)
1381                                 hns3_update_umv_space(hw, false);
1382                         return ret;
1383                 }
1384
1385                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1386
1387                 return -ENOSPC;
1388         }
1389
1390         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1391
1392         /* check if we just hit the duplicate */
1393         if (ret == 0) {
1394                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1395                 return 0;
1396         }
1397
1398         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1399                  mac_str);
1400
1401         return ret;
1402 }
1403
1404 static int
1405 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1406                   uint32_t idx, __rte_unused uint32_t pool)
1407 {
1408         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1409         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1410         int ret;
1411
1412         rte_spinlock_lock(&hw->lock);
1413         ret = hns3_add_uc_addr_common(hw, mac_addr);
1414         if (ret) {
1415                 rte_spinlock_unlock(&hw->lock);
1416                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1417                                       mac_addr);
1418                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1419                 return ret;
1420         }
1421
1422         if (idx == 0)
1423                 hw->mac.default_addr_setted = true;
1424         rte_spinlock_unlock(&hw->lock);
1425
1426         return ret;
1427 }
1428
1429 static int
1430 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1431 {
1432         struct hns3_mac_vlan_tbl_entry_cmd req;
1433         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1434         int ret;
1435
1436         /* check if mac addr is valid */
1437         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1438                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1439                                       mac_addr);
1440                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1441                          mac_str);
1442                 return -EINVAL;
1443         }
1444
1445         memset(&req, 0, sizeof(req));
1446         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1447         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1448         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1449         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1450                 return 0;
1451         else if (ret == 0)
1452                 hns3_update_umv_space(hw, true);
1453
1454         return ret;
1455 }
1456
1457 static void
1458 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1459 {
1460         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1461         /* index will be checked by upper level rte interface */
1462         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1463         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1464         int ret;
1465
1466         rte_spinlock_lock(&hw->lock);
1467         ret = hns3_remove_uc_addr_common(hw, mac_addr);
1468         if (ret) {
1469                 rte_spinlock_unlock(&hw->lock);
1470                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1471                                       mac_addr);
1472                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1473                 return;
1474         }
1475
1476         rte_spinlock_unlock(&hw->lock);
1477 }
1478
1479 static int
1480 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1481                           struct rte_ether_addr *mac_addr)
1482 {
1483         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1484         struct rte_ether_addr *oaddr;
1485         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1486         bool default_addr_setted;
1487         bool rm_succes = false;
1488         int ret, ret_val;
1489
1490         /*
1491          * It has been guaranteed that input parameter named mac_addr is valid
1492          * address in the rte layer of DPDK framework.
1493          */
1494         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1495         default_addr_setted = hw->mac.default_addr_setted;
1496         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1497                 return 0;
1498
1499         rte_spinlock_lock(&hw->lock);
1500         if (default_addr_setted) {
1501                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1502                 if (ret) {
1503                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1504                                               oaddr);
1505                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1506                                   mac_str, ret);
1507                         rm_succes = false;
1508                 } else
1509                         rm_succes = true;
1510         }
1511
1512         ret = hns3_add_uc_addr_common(hw, mac_addr);
1513         if (ret) {
1514                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1515                                       mac_addr);
1516                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1517                 goto err_add_uc_addr;
1518         }
1519
1520         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1521         if (ret) {
1522                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1523                 goto err_pause_addr_cfg;
1524         }
1525
1526         rte_ether_addr_copy(mac_addr,
1527                             (struct rte_ether_addr *)hw->mac.mac_addr);
1528         hw->mac.default_addr_setted = true;
1529         rte_spinlock_unlock(&hw->lock);
1530
1531         return 0;
1532
1533 err_pause_addr_cfg:
1534         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1535         if (ret_val) {
1536                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1537                                       mac_addr);
1538                 hns3_warn(hw,
1539                           "Failed to roll back to del setted mac addr(%s): %d",
1540                           mac_str, ret_val);
1541         }
1542
1543 err_add_uc_addr:
1544         if (rm_succes) {
1545                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1546                 if (ret_val) {
1547                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1548                                               oaddr);
1549                         hns3_warn(hw,
1550                                   "Failed to restore old uc mac addr(%s): %d",
1551                                   mac_str, ret_val);
1552                         hw->mac.default_addr_setted = false;
1553                 }
1554         }
1555         rte_spinlock_unlock(&hw->lock);
1556
1557         return ret;
1558 }
1559
1560 static int
1561 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1562 {
1563         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1564         struct hns3_hw *hw = &hns->hw;
1565         struct rte_ether_addr *addr;
1566         int err = 0;
1567         int ret;
1568         int i;
1569
1570         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1571                 addr = &hw->data->mac_addrs[i];
1572                 if (!rte_is_valid_assigned_ether_addr(addr))
1573                         continue;
1574                 if (del)
1575                         ret = hns3_remove_uc_addr_common(hw, addr);
1576                 else
1577                         ret = hns3_add_uc_addr_common(hw, addr);
1578                 if (ret) {
1579                         err = ret;
1580                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1581                                               addr);
1582                         hns3_dbg(hw,
1583                                  "Failed to %s mac addr(%s). ret:%d i:%d",
1584                                  del ? "remove" : "restore", mac_str, ret, i);
1585                 }
1586         }
1587         return err;
1588 }
1589
1590 static void
1591 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1592 {
1593 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1594         uint8_t word_num;
1595         uint8_t bit_num;
1596
1597         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1598                 word_num = vfid / 32;
1599                 bit_num = vfid % 32;
1600                 if (clr)
1601                         desc[1].data[word_num] &=
1602                             rte_cpu_to_le_32(~(1UL << bit_num));
1603                 else
1604                         desc[1].data[word_num] |=
1605                             rte_cpu_to_le_32(1UL << bit_num);
1606         } else {
1607                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1608                 bit_num = vfid % 32;
1609                 if (clr)
1610                         desc[2].data[word_num] &=
1611                             rte_cpu_to_le_32(~(1UL << bit_num));
1612                 else
1613                         desc[2].data[word_num] |=
1614                             rte_cpu_to_le_32(1UL << bit_num);
1615         }
1616 }
1617
1618 static int
1619 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1620 {
1621         struct hns3_mac_vlan_tbl_entry_cmd req;
1622         struct hns3_cmd_desc desc[3];
1623         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1624         uint8_t vf_id;
1625         int ret;
1626
1627         /* Check if mac addr is valid */
1628         if (!rte_is_multicast_ether_addr(mac_addr)) {
1629                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1630                                       mac_addr);
1631                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1632                          mac_str);
1633                 return -EINVAL;
1634         }
1635
1636         memset(&req, 0, sizeof(req));
1637         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1638         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1639         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1640         if (ret) {
1641                 /* This mac addr do not exist, add new entry for it */
1642                 memset(desc[0].data, 0, sizeof(desc[0].data));
1643                 memset(desc[1].data, 0, sizeof(desc[0].data));
1644                 memset(desc[2].data, 0, sizeof(desc[0].data));
1645         }
1646
1647         /*
1648          * In current version VF is not supported when PF is driven by DPDK
1649          * driver, the PF-related vf_id is 0, just need to configure parameters
1650          * for vf_id 0.
1651          */
1652         vf_id = 0;
1653         hns3_update_desc_vfid(desc, vf_id, false);
1654         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1655         if (ret) {
1656                 if (ret == -ENOSPC)
1657                         hns3_err(hw, "mc mac vlan table is full");
1658                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1659                                       mac_addr);
1660                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1661         }
1662
1663         return ret;
1664 }
1665
1666 static int
1667 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1668 {
1669         struct hns3_mac_vlan_tbl_entry_cmd req;
1670         struct hns3_cmd_desc desc[3];
1671         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1672         uint8_t vf_id;
1673         int ret;
1674
1675         /* Check if mac addr is valid */
1676         if (!rte_is_multicast_ether_addr(mac_addr)) {
1677                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1678                                       mac_addr);
1679                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1680                          mac_str);
1681                 return -EINVAL;
1682         }
1683
1684         memset(&req, 0, sizeof(req));
1685         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1686         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1687         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1688         if (ret == 0) {
1689                 /*
1690                  * This mac addr exist, remove this handle's VFID for it.
1691                  * In current version VF is not supported when PF is driven by
1692                  * DPDK driver, the PF-related vf_id is 0, just need to
1693                  * configure parameters for vf_id 0.
1694                  */
1695                 vf_id = 0;
1696                 hns3_update_desc_vfid(desc, vf_id, true);
1697
1698                 /* All the vfid is zero, so need to delete this entry */
1699                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1700         } else if (ret == -ENOENT) {
1701                 /* This mac addr doesn't exist. */
1702                 return 0;
1703         }
1704
1705         if (ret) {
1706                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1707                                       mac_addr);
1708                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1709         }
1710
1711         return ret;
1712 }
1713
1714 static int
1715 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1716                            struct rte_ether_addr *mc_addr_set,
1717                            uint32_t nb_mc_addr)
1718 {
1719         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1720         struct rte_ether_addr *addr;
1721         uint32_t i;
1722         uint32_t j;
1723
1724         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1725                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1726                          "invalid. valid range: 0~%d",
1727                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1728                 return -EINVAL;
1729         }
1730
1731         /* Check if input mac addresses are valid */
1732         for (i = 0; i < nb_mc_addr; i++) {
1733                 addr = &mc_addr_set[i];
1734                 if (!rte_is_multicast_ether_addr(addr)) {
1735                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1736                                               addr);
1737                         hns3_err(hw,
1738                                  "Failed to set mc mac addr, addr(%s) invalid.",
1739                                  mac_str);
1740                         return -EINVAL;
1741                 }
1742
1743                 /* Check if there are duplicate addresses */
1744                 for (j = i + 1; j < nb_mc_addr; j++) {
1745                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1746                                 rte_ether_format_addr(mac_str,
1747                                                       RTE_ETHER_ADDR_FMT_SIZE,
1748                                                       addr);
1749                                 hns3_err(hw, "Failed to set mc mac addr, "
1750                                          "addrs invalid. two same addrs(%s).",
1751                                          mac_str);
1752                                 return -EINVAL;
1753                         }
1754                 }
1755         }
1756
1757         return 0;
1758 }
1759
1760 static void
1761 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1762                            struct rte_ether_addr *mc_addr_set,
1763                            int mc_addr_num,
1764                            struct rte_ether_addr *reserved_addr_list,
1765                            int *reserved_addr_num,
1766                            struct rte_ether_addr *add_addr_list,
1767                            int *add_addr_num,
1768                            struct rte_ether_addr *rm_addr_list,
1769                            int *rm_addr_num)
1770 {
1771         struct rte_ether_addr *addr;
1772         int current_addr_num;
1773         int reserved_num = 0;
1774         int add_num = 0;
1775         int rm_num = 0;
1776         int num;
1777         int i;
1778         int j;
1779         bool same_addr;
1780
1781         /* Calculate the mc mac address list that should be removed */
1782         current_addr_num = hw->mc_addrs_num;
1783         for (i = 0; i < current_addr_num; i++) {
1784                 addr = &hw->mc_addrs[i];
1785                 same_addr = false;
1786                 for (j = 0; j < mc_addr_num; j++) {
1787                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1788                                 same_addr = true;
1789                                 break;
1790                         }
1791                 }
1792
1793                 if (!same_addr) {
1794                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1795                         rm_num++;
1796                 } else {
1797                         rte_ether_addr_copy(addr,
1798                                             &reserved_addr_list[reserved_num]);
1799                         reserved_num++;
1800                 }
1801         }
1802
1803         /* Calculate the mc mac address list that should be added */
1804         for (i = 0; i < mc_addr_num; i++) {
1805                 addr = &mc_addr_set[i];
1806                 same_addr = false;
1807                 for (j = 0; j < current_addr_num; j++) {
1808                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1809                                 same_addr = true;
1810                                 break;
1811                         }
1812                 }
1813
1814                 if (!same_addr) {
1815                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1816                         add_num++;
1817                 }
1818         }
1819
1820         /* Reorder the mc mac address list maintained by driver */
1821         for (i = 0; i < reserved_num; i++)
1822                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1823
1824         for (i = 0; i < rm_num; i++) {
1825                 num = reserved_num + i;
1826                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1827         }
1828
1829         *reserved_addr_num = reserved_num;
1830         *add_addr_num = add_num;
1831         *rm_addr_num = rm_num;
1832 }
1833
1834 static int
1835 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1836                           struct rte_ether_addr *mc_addr_set,
1837                           uint32_t nb_mc_addr)
1838 {
1839         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1841         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1842         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1843         struct rte_ether_addr *addr;
1844         int reserved_addr_num;
1845         int add_addr_num;
1846         int rm_addr_num;
1847         int mc_addr_num;
1848         int num;
1849         int ret;
1850         int i;
1851
1852         /* Check if input parameters are valid */
1853         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1854         if (ret)
1855                 return ret;
1856
1857         rte_spinlock_lock(&hw->lock);
1858
1859         /*
1860          * Calculate the mc mac address lists those should be removed and be
1861          * added, Reorder the mc mac address list maintained by driver.
1862          */
1863         mc_addr_num = (int)nb_mc_addr;
1864         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1865                                    reserved_addr_list, &reserved_addr_num,
1866                                    add_addr_list, &add_addr_num,
1867                                    rm_addr_list, &rm_addr_num);
1868
1869         /* Remove mc mac addresses */
1870         for (i = 0; i < rm_addr_num; i++) {
1871                 num = rm_addr_num - i - 1;
1872                 addr = &rm_addr_list[num];
1873                 ret = hns3_remove_mc_addr(hw, addr);
1874                 if (ret) {
1875                         rte_spinlock_unlock(&hw->lock);
1876                         return ret;
1877                 }
1878                 hw->mc_addrs_num--;
1879         }
1880
1881         /* Add mc mac addresses */
1882         for (i = 0; i < add_addr_num; i++) {
1883                 addr = &add_addr_list[i];
1884                 ret = hns3_add_mc_addr(hw, addr);
1885                 if (ret) {
1886                         rte_spinlock_unlock(&hw->lock);
1887                         return ret;
1888                 }
1889
1890                 num = reserved_addr_num + i;
1891                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1892                 hw->mc_addrs_num++;
1893         }
1894         rte_spinlock_unlock(&hw->lock);
1895
1896         return 0;
1897 }
1898
1899 static int
1900 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1901 {
1902         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1903         struct hns3_hw *hw = &hns->hw;
1904         struct rte_ether_addr *addr;
1905         int err = 0;
1906         int ret;
1907         int i;
1908
1909         for (i = 0; i < hw->mc_addrs_num; i++) {
1910                 addr = &hw->mc_addrs[i];
1911                 if (!rte_is_multicast_ether_addr(addr))
1912                         continue;
1913                 if (del)
1914                         ret = hns3_remove_mc_addr(hw, addr);
1915                 else
1916                         ret = hns3_add_mc_addr(hw, addr);
1917                 if (ret) {
1918                         err = ret;
1919                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1920                                               addr);
1921                         hns3_dbg(hw, "%s mc mac addr: %s failed",
1922                                  del ? "Remove" : "Restore", mac_str);
1923                 }
1924         }
1925         return err;
1926 }
1927
1928 static int
1929 hns3_check_mq_mode(struct rte_eth_dev *dev)
1930 {
1931         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1932         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1933         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1934         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1935         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1936         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1937         uint8_t num_tc;
1938         int max_tc = 0;
1939         int i;
1940
1941         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1942         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1943
1944         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1945                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
1946                          "rx_mq_mode = %d", rx_mq_mode);
1947                 return -EINVAL;
1948         }
1949
1950         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
1951             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1952                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
1953                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
1954                          rx_mq_mode, tx_mq_mode);
1955                 return -EINVAL;
1956         }
1957
1958         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
1959                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1960                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1961                                  dcb_rx_conf->nb_tcs, pf->tc_max);
1962                         return -EINVAL;
1963                 }
1964
1965                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1966                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1967                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
1968                                  "nb_tcs(%d) != %d or %d in rx direction.",
1969                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1970                         return -EINVAL;
1971                 }
1972
1973                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1974                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1975                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1976                         return -EINVAL;
1977                 }
1978
1979                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1980                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1981                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
1982                                          "is not equal to one in tx direction.",
1983                                          i, dcb_rx_conf->dcb_tc[i]);
1984                                 return -EINVAL;
1985                         }
1986                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
1987                                 max_tc = dcb_rx_conf->dcb_tc[i];
1988                 }
1989
1990                 num_tc = max_tc + 1;
1991                 if (num_tc > dcb_rx_conf->nb_tcs) {
1992                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
1993                                  num_tc, dcb_rx_conf->nb_tcs);
1994                         return -EINVAL;
1995                 }
1996         }
1997
1998         return 0;
1999 }
2000
2001 static int
2002 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2003 {
2004         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2005
2006         if (!hns3_dev_dcb_supported(hw)) {
2007                 hns3_err(hw, "this port does not support dcb configurations.");
2008                 return -EOPNOTSUPP;
2009         }
2010
2011         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2012                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2013                 return -EOPNOTSUPP;
2014         }
2015
2016         /* Check multiple queue mode */
2017         return hns3_check_mq_mode(dev);
2018 }
2019
2020 static int
2021 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2022                            enum hns3_ring_type queue_type, uint16_t queue_id)
2023 {
2024         struct hns3_cmd_desc desc;
2025         struct hns3_ctrl_vector_chain_cmd *req =
2026                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2027         enum hns3_cmd_status status;
2028         enum hns3_opcode_type op;
2029         uint16_t tqp_type_and_id = 0;
2030         const char *op_str;
2031         uint16_t type;
2032         uint16_t gl;
2033
2034         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2035         hns3_cmd_setup_basic_desc(&desc, op, false);
2036         req->int_vector_id = vector_id;
2037
2038         if (queue_type == HNS3_RING_TYPE_RX)
2039                 gl = HNS3_RING_GL_RX;
2040         else
2041                 gl = HNS3_RING_GL_TX;
2042
2043         type = queue_type;
2044
2045         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2046                        type);
2047         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2048         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2049                        gl);
2050         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2051         req->int_cause_num = 1;
2052         op_str = mmap ? "Map" : "Unmap";
2053         status = hns3_cmd_send(hw, &desc, 1);
2054         if (status) {
2055                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2056                          op_str, queue_id, req->int_vector_id, status);
2057                 return status;
2058         }
2059
2060         return 0;
2061 }
2062
2063 static int
2064 hns3_init_ring_with_vector(struct hns3_hw *hw)
2065 {
2066         uint8_t vec;
2067         int ret;
2068         int i;
2069
2070         /*
2071          * In hns3 network engine, vector 0 is always the misc interrupt of this
2072          * function, vector 1~N can be used respectively for the queues of the
2073          * function. Tx and Rx queues with the same number share the interrupt
2074          * vector. In the initialization clearing the all hardware mapping
2075          * relationship configurations between queues and interrupt vectors is
2076          * needed, so some error caused by the residual configurations, such as
2077          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2078          * constraints in hns3 hardware engine, we have to implement clearing
2079          * the mapping relationship configurations by binding all queues to the
2080          * last interrupt vector and reserving the last interrupt vector. This
2081          * method results in a decrease of the maximum queues when upper
2082          * applications call the rte_eth_dev_configure API function to enable
2083          * Rx interrupt.
2084          */
2085         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2086         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
2087         for (i = 0; i < hw->intr_tqps_num; i++) {
2088                 /*
2089                  * Set gap limiter and rate limiter configuration of queue's
2090                  * interrupt.
2091                  */
2092                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2093                                        HNS3_TQP_INTR_GL_DEFAULT);
2094                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2095                                        HNS3_TQP_INTR_GL_DEFAULT);
2096                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2097
2098                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2099                                                  HNS3_RING_TYPE_TX, i);
2100                 if (ret) {
2101                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2102                                           "vector: %d, ret=%d", i, vec, ret);
2103                         return ret;
2104                 }
2105
2106                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2107                                                  HNS3_RING_TYPE_RX, i);
2108                 if (ret) {
2109                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2110                                           "vector: %d, ret=%d", i, vec, ret);
2111                         return ret;
2112                 }
2113         }
2114
2115         return 0;
2116 }
2117
2118 static int
2119 hns3_dev_configure(struct rte_eth_dev *dev)
2120 {
2121         struct hns3_adapter *hns = dev->data->dev_private;
2122         struct rte_eth_conf *conf = &dev->data->dev_conf;
2123         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2124         struct hns3_hw *hw = &hns->hw;
2125         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2126         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2127         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2128         struct rte_eth_rss_conf rss_conf;
2129         uint16_t mtu;
2130         int ret;
2131
2132         /*
2133          * Hardware does not support individually enable/disable/reset the Tx or
2134          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2135          * and Rx queues at the same time. When the numbers of Tx queues
2136          * allocated by upper applications are not equal to the numbers of Rx
2137          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2138          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2139          * these fake queues are imperceptible, and can not be used by upper
2140          * applications.
2141          */
2142         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2143         if (ret) {
2144                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2145                 return ret;
2146         }
2147
2148         hw->adapter_state = HNS3_NIC_CONFIGURING;
2149         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2150                 hns3_err(hw, "setting link speed/duplex not supported");
2151                 ret = -EINVAL;
2152                 goto cfg_err;
2153         }
2154
2155         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2156                 ret = hns3_check_dcb_cfg(dev);
2157                 if (ret)
2158                         goto cfg_err;
2159         }
2160
2161         /* When RSS is not configured, redirect the packet queue 0 */
2162         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2163                 rss_conf = conf->rx_adv_conf.rss_conf;
2164                 if (rss_conf.rss_key == NULL) {
2165                         rss_conf.rss_key = rss_cfg->key;
2166                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2167                 }
2168
2169                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2170                 if (ret)
2171                         goto cfg_err;
2172         }
2173
2174         /*
2175          * If jumbo frames are enabled, MTU needs to be refreshed
2176          * according to the maximum RX packet length.
2177          */
2178         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2179                 /*
2180                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2181                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2182                  * can safely assign to "uint16_t" type variable.
2183                  */
2184                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2185                 ret = hns3_dev_mtu_set(dev, mtu);
2186                 if (ret)
2187                         goto cfg_err;
2188                 dev->data->mtu = mtu;
2189         }
2190
2191         ret = hns3_dev_configure_vlan(dev);
2192         if (ret)
2193                 goto cfg_err;
2194
2195         hw->adapter_state = HNS3_NIC_CONFIGURED;
2196
2197         return 0;
2198
2199 cfg_err:
2200         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2201         hw->adapter_state = HNS3_NIC_INITIALIZED;
2202
2203         return ret;
2204 }
2205
2206 static int
2207 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2208 {
2209         struct hns3_config_max_frm_size_cmd *req;
2210         struct hns3_cmd_desc desc;
2211
2212         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2213
2214         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2215         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2216         req->min_frm_size = RTE_ETHER_MIN_LEN;
2217
2218         return hns3_cmd_send(hw, &desc, 1);
2219 }
2220
2221 static int
2222 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2223 {
2224         int ret;
2225
2226         ret = hns3_set_mac_mtu(hw, mps);
2227         if (ret) {
2228                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2229                 return ret;
2230         }
2231
2232         ret = hns3_buffer_alloc(hw);
2233         if (ret) {
2234                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2235                 return ret;
2236         }
2237
2238         return 0;
2239 }
2240
2241 static int
2242 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2243 {
2244         struct hns3_adapter *hns = dev->data->dev_private;
2245         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2246         struct hns3_hw *hw = &hns->hw;
2247         bool is_jumbo_frame;
2248         int ret;
2249
2250         if (dev->data->dev_started) {
2251                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2252                          "before configuration", dev->data->port_id);
2253                 return -EBUSY;
2254         }
2255
2256         rte_spinlock_lock(&hw->lock);
2257         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2258         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2259
2260         /*
2261          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2262          * assign to "uint16_t" type variable.
2263          */
2264         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2265         if (ret) {
2266                 rte_spinlock_unlock(&hw->lock);
2267                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2268                          dev->data->port_id, mtu, ret);
2269                 return ret;
2270         }
2271         hns->pf.mps = (uint16_t)frame_size;
2272         if (is_jumbo_frame)
2273                 dev->data->dev_conf.rxmode.offloads |=
2274                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2275         else
2276                 dev->data->dev_conf.rxmode.offloads &=
2277                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2278         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2279         rte_spinlock_unlock(&hw->lock);
2280
2281         return 0;
2282 }
2283
2284 static int
2285 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2286 {
2287         struct hns3_adapter *hns = eth_dev->data->dev_private;
2288         struct hns3_hw *hw = &hns->hw;
2289         uint16_t queue_num = hw->tqps_num;
2290
2291         /*
2292          * In interrupt mode, 'max_rx_queues' is set based on the number of
2293          * MSI-X interrupt resources of the hardware.
2294          */
2295         if (hw->data->dev_conf.intr_conf.rxq == 1)
2296                 queue_num = hw->intr_tqps_num;
2297
2298         info->max_rx_queues = queue_num;
2299         info->max_tx_queues = hw->tqps_num;
2300         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2301         info->min_rx_bufsize = hw->rx_buf_len;
2302         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2303         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2304         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2305                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2306                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2307                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2308                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2309                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2310                                  DEV_RX_OFFLOAD_KEEP_CRC |
2311                                  DEV_RX_OFFLOAD_SCATTER |
2312                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2313                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2314                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2315                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2316                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
2317         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2318         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2319                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2320                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2321                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2322                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2323                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2324                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2325                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2326                                  DEV_TX_OFFLOAD_TCP_TSO |
2327                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2328                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2329                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2330                                  info->tx_queue_offload_capa);
2331
2332         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2333                 .nb_max = HNS3_MAX_RING_DESC,
2334                 .nb_min = HNS3_MIN_RING_DESC,
2335                 .nb_align = HNS3_ALIGN_RING_DESC,
2336         };
2337
2338         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2339                 .nb_max = HNS3_MAX_RING_DESC,
2340                 .nb_min = HNS3_MIN_RING_DESC,
2341                 .nb_align = HNS3_ALIGN_RING_DESC,
2342         };
2343
2344         info->vmdq_queue_num = 0;
2345
2346         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2347         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2348         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2349
2350         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2351         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2352         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2353         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2354         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2355         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2356
2357         return 0;
2358 }
2359
2360 static int
2361 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2362                     size_t fw_size)
2363 {
2364         struct hns3_adapter *hns = eth_dev->data->dev_private;
2365         struct hns3_hw *hw = &hns->hw;
2366         int ret;
2367
2368         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2369         ret += 1; /* add the size of '\0' */
2370         if (fw_size < (uint32_t)ret)
2371                 return ret;
2372         else
2373                 return 0;
2374 }
2375
2376 static int
2377 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2378                      __rte_unused int wait_to_complete)
2379 {
2380         struct hns3_adapter *hns = eth_dev->data->dev_private;
2381         struct hns3_hw *hw = &hns->hw;
2382         struct hns3_mac *mac = &hw->mac;
2383         struct rte_eth_link new_link;
2384
2385         if (!hns3_is_reset_pending(hns)) {
2386                 hns3_update_speed_duplex(eth_dev);
2387                 hns3_update_link_status(hw);
2388         }
2389
2390         memset(&new_link, 0, sizeof(new_link));
2391         switch (mac->link_speed) {
2392         case ETH_SPEED_NUM_10M:
2393         case ETH_SPEED_NUM_100M:
2394         case ETH_SPEED_NUM_1G:
2395         case ETH_SPEED_NUM_10G:
2396         case ETH_SPEED_NUM_25G:
2397         case ETH_SPEED_NUM_40G:
2398         case ETH_SPEED_NUM_50G:
2399         case ETH_SPEED_NUM_100G:
2400                 new_link.link_speed = mac->link_speed;
2401                 break;
2402         default:
2403                 new_link.link_speed = ETH_SPEED_NUM_100M;
2404                 break;
2405         }
2406
2407         new_link.link_duplex = mac->link_duplex;
2408         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2409         new_link.link_autoneg =
2410             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2411
2412         return rte_eth_linkstatus_set(eth_dev, &new_link);
2413 }
2414
2415 static int
2416 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2417 {
2418         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2419         struct hns3_pf *pf = &hns->pf;
2420
2421         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2422                 return -EINVAL;
2423
2424         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2425
2426         return 0;
2427 }
2428
2429 static int
2430 hns3_query_function_status(struct hns3_hw *hw)
2431 {
2432 #define HNS3_QUERY_MAX_CNT              10
2433 #define HNS3_QUERY_SLEEP_MSCOEND        1
2434         struct hns3_func_status_cmd *req;
2435         struct hns3_cmd_desc desc;
2436         int timeout = 0;
2437         int ret;
2438
2439         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2440         req = (struct hns3_func_status_cmd *)desc.data;
2441
2442         do {
2443                 ret = hns3_cmd_send(hw, &desc, 1);
2444                 if (ret) {
2445                         PMD_INIT_LOG(ERR, "query function status failed %d",
2446                                      ret);
2447                         return ret;
2448                 }
2449
2450                 /* Check pf reset is done */
2451                 if (req->pf_state)
2452                         break;
2453
2454                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2455         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2456
2457         return hns3_parse_func_status(hw, req);
2458 }
2459
2460 static int
2461 hns3_query_pf_resource(struct hns3_hw *hw)
2462 {
2463         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2464         struct hns3_pf *pf = &hns->pf;
2465         struct hns3_pf_res_cmd *req;
2466         struct hns3_cmd_desc desc;
2467         uint16_t num_msi;
2468         int ret;
2469
2470         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2471         ret = hns3_cmd_send(hw, &desc, 1);
2472         if (ret) {
2473                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2474                 return ret;
2475         }
2476
2477         req = (struct hns3_pf_res_cmd *)desc.data;
2478         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2479         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2480         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2481         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2482
2483         if (req->tx_buf_size)
2484                 pf->tx_buf_size =
2485                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2486         else
2487                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2488
2489         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2490
2491         if (req->dv_buf_size)
2492                 pf->dv_buf_size =
2493                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2494         else
2495                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2496
2497         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2498
2499         num_msi = hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2500                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2501         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
2502
2503         return 0;
2504 }
2505
2506 static void
2507 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2508 {
2509         struct hns3_cfg_param_cmd *req;
2510         uint64_t mac_addr_tmp_high;
2511         uint64_t mac_addr_tmp;
2512         uint32_t i;
2513
2514         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2515
2516         /* get the configuration */
2517         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2518                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2519         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2520                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2521         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2522                                            HNS3_CFG_TQP_DESC_N_M,
2523                                            HNS3_CFG_TQP_DESC_N_S);
2524
2525         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2526                                        HNS3_CFG_PHY_ADDR_M,
2527                                        HNS3_CFG_PHY_ADDR_S);
2528         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2529                                          HNS3_CFG_MEDIA_TP_M,
2530                                          HNS3_CFG_MEDIA_TP_S);
2531         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2532                                          HNS3_CFG_RX_BUF_LEN_M,
2533                                          HNS3_CFG_RX_BUF_LEN_S);
2534         /* get mac address */
2535         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2536         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2537                                            HNS3_CFG_MAC_ADDR_H_M,
2538                                            HNS3_CFG_MAC_ADDR_H_S);
2539
2540         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2541
2542         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2543                                             HNS3_CFG_DEFAULT_SPEED_M,
2544                                             HNS3_CFG_DEFAULT_SPEED_S);
2545         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2546                                            HNS3_CFG_RSS_SIZE_M,
2547                                            HNS3_CFG_RSS_SIZE_S);
2548
2549         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2550                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2551
2552         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2553         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2554
2555         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2556                                             HNS3_CFG_SPEED_ABILITY_M,
2557                                             HNS3_CFG_SPEED_ABILITY_S);
2558         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2559                                         HNS3_CFG_UMV_TBL_SPACE_M,
2560                                         HNS3_CFG_UMV_TBL_SPACE_S);
2561         if (!cfg->umv_space)
2562                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2563 }
2564
2565 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2566  * @hw: pointer to struct hns3_hw
2567  * @hcfg: the config structure to be getted
2568  */
2569 static int
2570 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2571 {
2572         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2573         struct hns3_cfg_param_cmd *req;
2574         uint32_t offset;
2575         uint32_t i;
2576         int ret;
2577
2578         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2579                 offset = 0;
2580                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2581                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2582                                           true);
2583                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2584                                i * HNS3_CFG_RD_LEN_BYTES);
2585                 /* Len should be divided by 4 when send to hardware */
2586                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2587                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2588                 req->offset = rte_cpu_to_le_32(offset);
2589         }
2590
2591         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2592         if (ret) {
2593                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2594                 return ret;
2595         }
2596
2597         hns3_parse_cfg(hcfg, desc);
2598
2599         return 0;
2600 }
2601
2602 static int
2603 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2604 {
2605         switch (speed_cmd) {
2606         case HNS3_CFG_SPEED_10M:
2607                 *speed = ETH_SPEED_NUM_10M;
2608                 break;
2609         case HNS3_CFG_SPEED_100M:
2610                 *speed = ETH_SPEED_NUM_100M;
2611                 break;
2612         case HNS3_CFG_SPEED_1G:
2613                 *speed = ETH_SPEED_NUM_1G;
2614                 break;
2615         case HNS3_CFG_SPEED_10G:
2616                 *speed = ETH_SPEED_NUM_10G;
2617                 break;
2618         case HNS3_CFG_SPEED_25G:
2619                 *speed = ETH_SPEED_NUM_25G;
2620                 break;
2621         case HNS3_CFG_SPEED_40G:
2622                 *speed = ETH_SPEED_NUM_40G;
2623                 break;
2624         case HNS3_CFG_SPEED_50G:
2625                 *speed = ETH_SPEED_NUM_50G;
2626                 break;
2627         case HNS3_CFG_SPEED_100G:
2628                 *speed = ETH_SPEED_NUM_100G;
2629                 break;
2630         default:
2631                 return -EINVAL;
2632         }
2633
2634         return 0;
2635 }
2636
2637 static int
2638 hns3_get_board_configuration(struct hns3_hw *hw)
2639 {
2640         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2641         struct hns3_pf *pf = &hns->pf;
2642         struct hns3_cfg cfg;
2643         int ret;
2644
2645         ret = hns3_get_board_cfg(hw, &cfg);
2646         if (ret) {
2647                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2648                 return ret;
2649         }
2650
2651         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2652                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2653                 return -EOPNOTSUPP;
2654         }
2655
2656         hw->mac.media_type = cfg.media_type;
2657         hw->rss_size_max = cfg.rss_size_max;
2658         hw->rx_buf_len = cfg.rx_buf_len;
2659         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2660         hw->mac.phy_addr = cfg.phy_addr;
2661         hw->mac.default_addr_setted = false;
2662         hw->num_tx_desc = cfg.tqp_desc_num;
2663         hw->num_rx_desc = cfg.tqp_desc_num;
2664         hw->dcb_info.num_pg = 1;
2665         hw->dcb_info.hw_pfc_map = 0;
2666
2667         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2668         if (ret) {
2669                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2670                              cfg.default_speed, ret);
2671                 return ret;
2672         }
2673
2674         pf->tc_max = cfg.tc_num;
2675         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2676                 PMD_INIT_LOG(WARNING,
2677                              "Get TC num(%u) from flash, set TC num to 1",
2678                              pf->tc_max);
2679                 pf->tc_max = 1;
2680         }
2681
2682         /* Dev does not support DCB */
2683         if (!hns3_dev_dcb_supported(hw)) {
2684                 pf->tc_max = 1;
2685                 pf->pfc_max = 0;
2686         } else
2687                 pf->pfc_max = pf->tc_max;
2688
2689         hw->dcb_info.num_tc = 1;
2690         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2691                                      hw->tqps_num / hw->dcb_info.num_tc);
2692         hns3_set_bit(hw->hw_tc_map, 0, 1);
2693         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2694
2695         pf->wanted_umv_size = cfg.umv_space;
2696
2697         return ret;
2698 }
2699
2700 static int
2701 hns3_get_configuration(struct hns3_hw *hw)
2702 {
2703         int ret;
2704
2705         ret = hns3_query_function_status(hw);
2706         if (ret) {
2707                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2708                 return ret;
2709         }
2710
2711         /* Get pf resource */
2712         ret = hns3_query_pf_resource(hw);
2713         if (ret) {
2714                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2715                 return ret;
2716         }
2717
2718         ret = hns3_get_board_configuration(hw);
2719         if (ret) {
2720                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2721                 return ret;
2722         }
2723
2724         return 0;
2725 }
2726
2727 static int
2728 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2729                       uint16_t tqp_vid, bool is_pf)
2730 {
2731         struct hns3_tqp_map_cmd *req;
2732         struct hns3_cmd_desc desc;
2733         int ret;
2734
2735         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2736
2737         req = (struct hns3_tqp_map_cmd *)desc.data;
2738         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2739         req->tqp_vf = func_id;
2740         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2741         if (!is_pf)
2742                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2743         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2744
2745         ret = hns3_cmd_send(hw, &desc, 1);
2746         if (ret)
2747                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2748
2749         return ret;
2750 }
2751
2752 static int
2753 hns3_map_tqp(struct hns3_hw *hw)
2754 {
2755         uint16_t tqps_num = hw->total_tqps_num;
2756         uint16_t func_id;
2757         uint16_t tqp_id;
2758         bool is_pf;
2759         int num;
2760         int ret;
2761         int i;
2762
2763         /*
2764          * In current version VF is not supported when PF is driven by DPDK
2765          * driver, so we allocate tqps to PF as much as possible.
2766          */
2767         tqp_id = 0;
2768         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2769         for (func_id = 0; func_id < num; func_id++) {
2770                 is_pf = func_id == 0 ? true : false;
2771                 for (i = 0;
2772                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2773                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2774                                                     is_pf);
2775                         if (ret)
2776                                 return ret;
2777                 }
2778         }
2779
2780         return 0;
2781 }
2782
2783 static int
2784 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2785 {
2786         struct hns3_config_mac_speed_dup_cmd *req;
2787         struct hns3_cmd_desc desc;
2788         int ret;
2789
2790         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2791
2792         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2793
2794         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2795
2796         switch (speed) {
2797         case ETH_SPEED_NUM_10M:
2798                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2799                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2800                 break;
2801         case ETH_SPEED_NUM_100M:
2802                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2803                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2804                 break;
2805         case ETH_SPEED_NUM_1G:
2806                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2807                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2808                 break;
2809         case ETH_SPEED_NUM_10G:
2810                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2811                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2812                 break;
2813         case ETH_SPEED_NUM_25G:
2814                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2815                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2816                 break;
2817         case ETH_SPEED_NUM_40G:
2818                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2819                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2820                 break;
2821         case ETH_SPEED_NUM_50G:
2822                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2823                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2824                 break;
2825         case ETH_SPEED_NUM_100G:
2826                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2827                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2828                 break;
2829         default:
2830                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2831                 return -EINVAL;
2832         }
2833
2834         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2835
2836         ret = hns3_cmd_send(hw, &desc, 1);
2837         if (ret)
2838                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2839
2840         return ret;
2841 }
2842
2843 static int
2844 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2845 {
2846         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2847         struct hns3_pf *pf = &hns->pf;
2848         struct hns3_priv_buf *priv;
2849         uint32_t i, total_size;
2850
2851         total_size = pf->pkt_buf_size;
2852
2853         /* alloc tx buffer for all enabled tc */
2854         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2855                 priv = &buf_alloc->priv_buf[i];
2856
2857                 if (hw->hw_tc_map & BIT(i)) {
2858                         if (total_size < pf->tx_buf_size)
2859                                 return -ENOMEM;
2860
2861                         priv->tx_buf_size = pf->tx_buf_size;
2862                 } else
2863                         priv->tx_buf_size = 0;
2864
2865                 total_size -= priv->tx_buf_size;
2866         }
2867
2868         return 0;
2869 }
2870
2871 static int
2872 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2873 {
2874 /* TX buffer size is unit by 128 byte */
2875 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
2876 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
2877         struct hns3_tx_buff_alloc_cmd *req;
2878         struct hns3_cmd_desc desc;
2879         uint32_t buf_size;
2880         uint32_t i;
2881         int ret;
2882
2883         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2884
2885         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2886         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2887                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2888
2889                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2890                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2891                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2892         }
2893
2894         ret = hns3_cmd_send(hw, &desc, 1);
2895         if (ret)
2896                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2897
2898         return ret;
2899 }
2900
2901 static int
2902 hns3_get_tc_num(struct hns3_hw *hw)
2903 {
2904         int cnt = 0;
2905         uint8_t i;
2906
2907         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2908                 if (hw->hw_tc_map & BIT(i))
2909                         cnt++;
2910         return cnt;
2911 }
2912
2913 static uint32_t
2914 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2915 {
2916         struct hns3_priv_buf *priv;
2917         uint32_t rx_priv = 0;
2918         int i;
2919
2920         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2921                 priv = &buf_alloc->priv_buf[i];
2922                 if (priv->enable)
2923                         rx_priv += priv->buf_size;
2924         }
2925         return rx_priv;
2926 }
2927
2928 static uint32_t
2929 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2930 {
2931         uint32_t total_tx_size = 0;
2932         uint32_t i;
2933
2934         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2935                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2936
2937         return total_tx_size;
2938 }
2939
2940 /* Get the number of pfc enabled TCs, which have private buffer */
2941 static int
2942 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2943 {
2944         struct hns3_priv_buf *priv;
2945         int cnt = 0;
2946         uint8_t i;
2947
2948         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2949                 priv = &buf_alloc->priv_buf[i];
2950                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2951                         cnt++;
2952         }
2953
2954         return cnt;
2955 }
2956
2957 /* Get the number of pfc disabled TCs, which have private buffer */
2958 static int
2959 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2960                          struct hns3_pkt_buf_alloc *buf_alloc)
2961 {
2962         struct hns3_priv_buf *priv;
2963         int cnt = 0;
2964         uint8_t i;
2965
2966         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2967                 priv = &buf_alloc->priv_buf[i];
2968                 if (hw->hw_tc_map & BIT(i) &&
2969                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2970                         cnt++;
2971         }
2972
2973         return cnt;
2974 }
2975
2976 static bool
2977 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2978                   uint32_t rx_all)
2979 {
2980         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2981         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2982         struct hns3_pf *pf = &hns->pf;
2983         uint32_t shared_buf, aligned_mps;
2984         uint32_t rx_priv;
2985         uint8_t tc_num;
2986         uint8_t i;
2987
2988         tc_num = hns3_get_tc_num(hw);
2989         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2990
2991         if (hns3_dev_dcb_supported(hw))
2992                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
2993                                         pf->dv_buf_size;
2994         else
2995                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
2996                                         + pf->dv_buf_size;
2997
2998         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
2999         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3000                              HNS3_BUF_SIZE_UNIT);
3001
3002         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3003         if (rx_all < rx_priv + shared_std)
3004                 return false;
3005
3006         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3007         buf_alloc->s_buf.buf_size = shared_buf;
3008         if (hns3_dev_dcb_supported(hw)) {
3009                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3010                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3011                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3012                                   HNS3_BUF_SIZE_UNIT);
3013         } else {
3014                 buf_alloc->s_buf.self.high =
3015                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3016                 buf_alloc->s_buf.self.low = aligned_mps;
3017         }
3018
3019         if (hns3_dev_dcb_supported(hw)) {
3020                 hi_thrd = shared_buf - pf->dv_buf_size;
3021
3022                 if (tc_num <= NEED_RESERVE_TC_NUM)
3023                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3024                                         / BUF_MAX_PERCENT;
3025
3026                 if (tc_num)
3027                         hi_thrd = hi_thrd / tc_num;
3028
3029                 hi_thrd = max_t(uint32_t, hi_thrd,
3030                                 HNS3_BUF_MUL_BY * aligned_mps);
3031                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3032                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3033         } else {
3034                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3035                 lo_thrd = aligned_mps;
3036         }
3037
3038         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3039                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3040                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3041         }
3042
3043         return true;
3044 }
3045
3046 static bool
3047 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3048                      struct hns3_pkt_buf_alloc *buf_alloc)
3049 {
3050         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3051         struct hns3_pf *pf = &hns->pf;
3052         struct hns3_priv_buf *priv;
3053         uint32_t aligned_mps;
3054         uint32_t rx_all;
3055         uint8_t i;
3056
3057         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3058         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3059
3060         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3061                 priv = &buf_alloc->priv_buf[i];
3062
3063                 priv->enable = 0;
3064                 priv->wl.low = 0;
3065                 priv->wl.high = 0;
3066                 priv->buf_size = 0;
3067
3068                 if (!(hw->hw_tc_map & BIT(i)))
3069                         continue;
3070
3071                 priv->enable = 1;
3072                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3073                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3074                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3075                                                 HNS3_BUF_SIZE_UNIT);
3076                 } else {
3077                         priv->wl.low = 0;
3078                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3079                                         aligned_mps;
3080                 }
3081
3082                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3083         }
3084
3085         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3086 }
3087
3088 static bool
3089 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3090                              struct hns3_pkt_buf_alloc *buf_alloc)
3091 {
3092         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3093         struct hns3_pf *pf = &hns->pf;
3094         struct hns3_priv_buf *priv;
3095         int no_pfc_priv_num;
3096         uint32_t rx_all;
3097         uint8_t mask;
3098         int i;
3099
3100         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3101         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3102
3103         /* let the last to be cleared first */
3104         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3105                 priv = &buf_alloc->priv_buf[i];
3106                 mask = BIT((uint8_t)i);
3107
3108                 if (hw->hw_tc_map & mask &&
3109                     !(hw->dcb_info.hw_pfc_map & mask)) {
3110                         /* Clear the no pfc TC private buffer */
3111                         priv->wl.low = 0;
3112                         priv->wl.high = 0;
3113                         priv->buf_size = 0;
3114                         priv->enable = 0;
3115                         no_pfc_priv_num--;
3116                 }
3117
3118                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3119                     no_pfc_priv_num == 0)
3120                         break;
3121         }
3122
3123         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3124 }
3125
3126 static bool
3127 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3128                            struct hns3_pkt_buf_alloc *buf_alloc)
3129 {
3130         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3131         struct hns3_pf *pf = &hns->pf;
3132         struct hns3_priv_buf *priv;
3133         uint32_t rx_all;
3134         int pfc_priv_num;
3135         uint8_t mask;
3136         int i;
3137
3138         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3139         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3140
3141         /* let the last to be cleared first */
3142         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3143                 priv = &buf_alloc->priv_buf[i];
3144                 mask = BIT((uint8_t)i);
3145
3146                 if (hw->hw_tc_map & mask &&
3147                     hw->dcb_info.hw_pfc_map & mask) {
3148                         /* Reduce the number of pfc TC with private buffer */
3149                         priv->wl.low = 0;
3150                         priv->enable = 0;
3151                         priv->wl.high = 0;
3152                         priv->buf_size = 0;
3153                         pfc_priv_num--;
3154                 }
3155                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3156                     pfc_priv_num == 0)
3157                         break;
3158         }
3159
3160         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3161 }
3162
3163 static bool
3164 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3165                           struct hns3_pkt_buf_alloc *buf_alloc)
3166 {
3167 #define COMPENSATE_BUFFER       0x3C00
3168 #define COMPENSATE_HALF_MPS_NUM 5
3169 #define PRIV_WL_GAP             0x1800
3170         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3171         struct hns3_pf *pf = &hns->pf;
3172         uint32_t tc_num = hns3_get_tc_num(hw);
3173         uint32_t half_mps = pf->mps >> 1;
3174         struct hns3_priv_buf *priv;
3175         uint32_t min_rx_priv;
3176         uint32_t rx_priv;
3177         uint8_t i;
3178
3179         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3180         if (tc_num)
3181                 rx_priv = rx_priv / tc_num;
3182
3183         if (tc_num <= NEED_RESERVE_TC_NUM)
3184                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3185
3186         /*
3187          * Minimum value of private buffer in rx direction (min_rx_priv) is
3188          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3189          * buffer if rx_priv is greater than min_rx_priv.
3190          */
3191         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3192                         COMPENSATE_HALF_MPS_NUM * half_mps;
3193         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3194         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3195
3196         if (rx_priv < min_rx_priv)
3197                 return false;
3198
3199         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3200                 priv = &buf_alloc->priv_buf[i];
3201
3202                 priv->enable = 0;
3203                 priv->wl.low = 0;
3204                 priv->wl.high = 0;
3205                 priv->buf_size = 0;
3206
3207                 if (!(hw->hw_tc_map & BIT(i)))
3208                         continue;
3209
3210                 priv->enable = 1;
3211                 priv->buf_size = rx_priv;
3212                 priv->wl.high = rx_priv - pf->dv_buf_size;
3213                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3214         }
3215
3216         buf_alloc->s_buf.buf_size = 0;
3217
3218         return true;
3219 }
3220
3221 /*
3222  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3223  * @hw: pointer to struct hns3_hw
3224  * @buf_alloc: pointer to buffer calculation data
3225  * @return: 0: calculate sucessful, negative: fail
3226  */
3227 static int
3228 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3229 {
3230         /* When DCB is not supported, rx private buffer is not allocated. */
3231         if (!hns3_dev_dcb_supported(hw)) {
3232                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3233                 struct hns3_pf *pf = &hns->pf;
3234                 uint32_t rx_all = pf->pkt_buf_size;
3235
3236                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3237                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3238                         return -ENOMEM;
3239
3240                 return 0;
3241         }
3242
3243         /*
3244          * Try to allocate privated packet buffer for all TCs without share
3245          * buffer.
3246          */
3247         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3248                 return 0;
3249
3250         /*
3251          * Try to allocate privated packet buffer for all TCs with share
3252          * buffer.
3253          */
3254         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3255                 return 0;
3256
3257         /*
3258          * For different application scenes, the enabled port number, TC number
3259          * and no_drop TC number are different. In order to obtain the better
3260          * performance, software could allocate the buffer size and configure
3261          * the waterline by tring to decrease the private buffer size according
3262          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3263          * enabled tc.
3264          */
3265         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3266                 return 0;
3267
3268         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3269                 return 0;
3270
3271         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3272                 return 0;
3273
3274         return -ENOMEM;
3275 }
3276
3277 static int
3278 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3279 {
3280         struct hns3_rx_priv_buff_cmd *req;
3281         struct hns3_cmd_desc desc;
3282         uint32_t buf_size;
3283         int ret;
3284         int i;
3285
3286         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3287         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3288
3289         /* Alloc private buffer TCs */
3290         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3291                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3292
3293                 req->buf_num[i] =
3294                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3295                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3296         }
3297
3298         buf_size = buf_alloc->s_buf.buf_size;
3299         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3300                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3301
3302         ret = hns3_cmd_send(hw, &desc, 1);
3303         if (ret)
3304                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3305
3306         return ret;
3307 }
3308
3309 static int
3310 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3311 {
3312 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3313         struct hns3_rx_priv_wl_buf *req;
3314         struct hns3_priv_buf *priv;
3315         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3316         int i, j;
3317         int ret;
3318
3319         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3320                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3321                                           false);
3322                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3323
3324                 /* The first descriptor set the NEXT bit to 1 */
3325                 if (i == 0)
3326                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3327                 else
3328                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3329
3330                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3331                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3332
3333                         priv = &buf_alloc->priv_buf[idx];
3334                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3335                                                         HNS3_BUF_UNIT_S);
3336                         req->tc_wl[j].high |=
3337                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3338                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3339                                                         HNS3_BUF_UNIT_S);
3340                         req->tc_wl[j].low |=
3341                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3342                 }
3343         }
3344
3345         /* Send 2 descriptor at one time */
3346         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3347         if (ret)
3348                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3349                              ret);
3350         return ret;
3351 }
3352
3353 static int
3354 hns3_common_thrd_config(struct hns3_hw *hw,
3355                         struct hns3_pkt_buf_alloc *buf_alloc)
3356 {
3357 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3358         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3359         struct hns3_rx_com_thrd *req;
3360         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3361         struct hns3_tc_thrd *tc;
3362         int tc_idx;
3363         int i, j;
3364         int ret;
3365
3366         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3367                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3368                                           false);
3369                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3370
3371                 /* The first descriptor set the NEXT bit to 1 */
3372                 if (i == 0)
3373                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3374                 else
3375                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3376
3377                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3378                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3379                         tc = &s_buf->tc_thrd[tc_idx];
3380
3381                         req->com_thrd[j].high =
3382                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3383                         req->com_thrd[j].high |=
3384                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3385                         req->com_thrd[j].low =
3386                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3387                         req->com_thrd[j].low |=
3388                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3389                 }
3390         }
3391
3392         /* Send 2 descriptors at one time */
3393         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3394         if (ret)
3395                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3396
3397         return ret;
3398 }
3399
3400 static int
3401 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3402 {
3403         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3404         struct hns3_rx_com_wl *req;
3405         struct hns3_cmd_desc desc;
3406         int ret;
3407
3408         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3409
3410         req = (struct hns3_rx_com_wl *)desc.data;
3411         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3412         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3413
3414         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3415         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3416
3417         ret = hns3_cmd_send(hw, &desc, 1);
3418         if (ret)
3419                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3420
3421         return ret;
3422 }
3423
3424 int
3425 hns3_buffer_alloc(struct hns3_hw *hw)
3426 {
3427         struct hns3_pkt_buf_alloc pkt_buf;
3428         int ret;
3429
3430         memset(&pkt_buf, 0, sizeof(pkt_buf));
3431         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3432         if (ret) {
3433                 PMD_INIT_LOG(ERR,
3434                              "could not calc tx buffer size for all TCs %d",
3435                              ret);
3436                 return ret;
3437         }
3438
3439         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3440         if (ret) {
3441                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3442                 return ret;
3443         }
3444
3445         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3446         if (ret) {
3447                 PMD_INIT_LOG(ERR,
3448                              "could not calc rx priv buffer size for all TCs %d",
3449                              ret);
3450                 return ret;
3451         }
3452
3453         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3454         if (ret) {
3455                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3456                 return ret;
3457         }
3458
3459         if (hns3_dev_dcb_supported(hw)) {
3460                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3461                 if (ret) {
3462                         PMD_INIT_LOG(ERR,
3463                                      "could not configure rx private waterline %d",
3464                                      ret);
3465                         return ret;
3466                 }
3467
3468                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3469                 if (ret) {
3470                         PMD_INIT_LOG(ERR,
3471                                      "could not configure common threshold %d",
3472                                      ret);
3473                         return ret;
3474                 }
3475         }
3476
3477         ret = hns3_common_wl_config(hw, &pkt_buf);
3478         if (ret)
3479                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3480                              ret);
3481
3482         return ret;
3483 }
3484
3485 static int
3486 hns3_mac_init(struct hns3_hw *hw)
3487 {
3488         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3489         struct hns3_mac *mac = &hw->mac;
3490         struct hns3_pf *pf = &hns->pf;
3491         int ret;
3492
3493         pf->support_sfp_query = true;
3494         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3495         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3496         if (ret) {
3497                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3498                 return ret;
3499         }
3500
3501         mac->link_status = ETH_LINK_DOWN;
3502
3503         return hns3_config_mtu(hw, pf->mps);
3504 }
3505
3506 static int
3507 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3508 {
3509 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3510 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3511 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3512 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3513         int return_status;
3514
3515         if (cmdq_resp) {
3516                 PMD_INIT_LOG(ERR,
3517                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3518                              cmdq_resp);
3519                 return -EIO;
3520         }
3521
3522         switch (resp_code) {
3523         case HNS3_ETHERTYPE_SUCCESS_ADD:
3524         case HNS3_ETHERTYPE_ALREADY_ADD:
3525                 return_status = 0;
3526                 break;
3527         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3528                 PMD_INIT_LOG(ERR,
3529                              "add mac ethertype failed for manager table overflow.");
3530                 return_status = -EIO;
3531                 break;
3532         case HNS3_ETHERTYPE_KEY_CONFLICT:
3533                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3534                 return_status = -EIO;
3535                 break;
3536         default:
3537                 PMD_INIT_LOG(ERR,
3538                              "add mac ethertype failed for undefined, code=%d.",
3539                              resp_code);
3540                 return_status = -EIO;
3541         }
3542
3543         return return_status;
3544 }
3545
3546 static int
3547 hns3_add_mgr_tbl(struct hns3_hw *hw,
3548                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3549 {
3550         struct hns3_cmd_desc desc;
3551         uint8_t resp_code;
3552         uint16_t retval;
3553         int ret;
3554
3555         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3556         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3557
3558         ret = hns3_cmd_send(hw, &desc, 1);
3559         if (ret) {
3560                 PMD_INIT_LOG(ERR,
3561                              "add mac ethertype failed for cmd_send, ret =%d.",
3562                              ret);
3563                 return ret;
3564         }
3565
3566         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3567         retval = rte_le_to_cpu_16(desc.retval);
3568
3569         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3570 }
3571
3572 static void
3573 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3574                      int *table_item_num)
3575 {
3576         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3577
3578         /*
3579          * In current version, we add one item in management table as below:
3580          * 0x0180C200000E -- LLDP MC address
3581          */
3582         tbl = mgr_table;
3583         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3584         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3585         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3586         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3587         tbl->i_port_bitmap = 0x1;
3588         *table_item_num = 1;
3589 }
3590
3591 static int
3592 hns3_init_mgr_tbl(struct hns3_hw *hw)
3593 {
3594 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3595         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3596         int table_item_num;
3597         int ret;
3598         int i;
3599
3600         memset(mgr_table, 0, sizeof(mgr_table));
3601         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3602         for (i = 0; i < table_item_num; i++) {
3603                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3604                 if (ret) {
3605                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3606                                      ret);
3607                         return ret;
3608                 }
3609         }
3610
3611         return 0;
3612 }
3613
3614 static void
3615 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3616                         bool en_mc, bool en_bc, int vport_id)
3617 {
3618         if (!param)
3619                 return;
3620
3621         memset(param, 0, sizeof(struct hns3_promisc_param));
3622         if (en_uc)
3623                 param->enable = HNS3_PROMISC_EN_UC;
3624         if (en_mc)
3625                 param->enable |= HNS3_PROMISC_EN_MC;
3626         if (en_bc)
3627                 param->enable |= HNS3_PROMISC_EN_BC;
3628         param->vf_id = vport_id;
3629 }
3630
3631 static int
3632 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3633 {
3634         struct hns3_promisc_cfg_cmd *req;
3635         struct hns3_cmd_desc desc;
3636         int ret;
3637
3638         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3639
3640         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3641         req->vf_id = param->vf_id;
3642         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3643             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3644
3645         ret = hns3_cmd_send(hw, &desc, 1);
3646         if (ret)
3647                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3648
3649         return ret;
3650 }
3651
3652 static int
3653 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3654 {
3655         struct hns3_promisc_param param;
3656         bool en_bc_pmc = true;
3657         uint8_t vf_id;
3658         int ret;
3659
3660         /*
3661          * In current version VF is not supported when PF is driven by DPDK
3662          * driver, the PF-related vf_id is 0, just need to configure parameters
3663          * for vf_id 0.
3664          */
3665         vf_id = 0;
3666
3667         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3668         ret = hns3_cmd_set_promisc_mode(hw, &param);
3669         if (ret)
3670                 return ret;
3671
3672         return 0;
3673 }
3674
3675 static int
3676 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3677 {
3678         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3679         struct hns3_pf *pf = &hns->pf;
3680         struct hns3_promisc_param param;
3681         uint16_t func_id;
3682         int ret;
3683
3684         /* func_id 0 is denoted PF, the VFs start from 1 */
3685         for (func_id = 1; func_id < pf->func_num; func_id++) {
3686                 hns3_promisc_param_init(&param, false, false, false, func_id);
3687                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3688                 if (ret)
3689                         return ret;
3690         }
3691
3692         return 0;
3693 }
3694
3695 static int
3696 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3697 {
3698         struct hns3_adapter *hns = dev->data->dev_private;
3699         struct hns3_hw *hw = &hns->hw;
3700         int ret;
3701
3702         rte_spinlock_lock(&hw->lock);
3703         ret = hns3_set_promisc_mode(hw, true, true);
3704         rte_spinlock_unlock(&hw->lock);
3705         if (ret)
3706                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
3707                          ret);
3708
3709         return ret;
3710 }
3711
3712 static int
3713 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3714 {
3715         bool allmulti = dev->data->all_multicast ? true : false;
3716         struct hns3_adapter *hns = dev->data->dev_private;
3717         struct hns3_hw *hw = &hns->hw;
3718         int ret;
3719
3720         /* If now in all_multicast mode, must remain in all_multicast mode. */
3721         rte_spinlock_lock(&hw->lock);
3722         ret = hns3_set_promisc_mode(hw, false, allmulti);
3723         rte_spinlock_unlock(&hw->lock);
3724         if (ret)
3725                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
3726                          ret);
3727
3728         return ret;
3729 }
3730
3731 static int
3732 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3733 {
3734         struct hns3_adapter *hns = dev->data->dev_private;
3735         struct hns3_hw *hw = &hns->hw;
3736         int ret;
3737
3738         if (dev->data->promiscuous)
3739                 return 0;
3740
3741         rte_spinlock_lock(&hw->lock);
3742         ret = hns3_set_promisc_mode(hw, false, true);
3743         rte_spinlock_unlock(&hw->lock);
3744         if (ret)
3745                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
3746                          ret);
3747
3748         return ret;
3749 }
3750
3751 static int
3752 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3753 {
3754         struct hns3_adapter *hns = dev->data->dev_private;
3755         struct hns3_hw *hw = &hns->hw;
3756         int ret;
3757
3758         /* If now in promiscuous mode, must remain in all_multicast mode. */
3759         if (dev->data->promiscuous)
3760                 return 0;
3761
3762         rte_spinlock_lock(&hw->lock);
3763         ret = hns3_set_promisc_mode(hw, false, false);
3764         rte_spinlock_unlock(&hw->lock);
3765         if (ret)
3766                 hns3_err(hw, "Failed to disable allmulticast mode, ret =  %d",
3767                          ret);
3768
3769         return ret;
3770 }
3771
3772 static int
3773 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3774 {
3775         struct hns3_hw *hw = &hns->hw;
3776         bool allmulti = hw->data->all_multicast ? true : false;
3777
3778         if (hw->data->promiscuous)
3779                 return hns3_set_promisc_mode(hw, true, true);
3780
3781         return hns3_set_promisc_mode(hw, false, allmulti);
3782 }
3783
3784 static int
3785 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3786 {
3787         struct hns3_sfp_speed_cmd *resp;
3788         struct hns3_cmd_desc desc;
3789         int ret;
3790
3791         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3792         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3793         ret = hns3_cmd_send(hw, &desc, 1);
3794         if (ret == -EOPNOTSUPP) {
3795                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3796                 return ret;
3797         } else if (ret) {
3798                 hns3_err(hw, "get sfp speed failed %d", ret);
3799                 return ret;
3800         }
3801
3802         *speed = resp->sfp_speed;
3803
3804         return 0;
3805 }
3806
3807 static uint8_t
3808 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3809 {
3810         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3811                 duplex = ETH_LINK_FULL_DUPLEX;
3812
3813         return duplex;
3814 }
3815
3816 static int
3817 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3818 {
3819         struct hns3_mac *mac = &hw->mac;
3820         int ret;
3821
3822         duplex = hns3_check_speed_dup(duplex, speed);
3823         if (mac->link_speed == speed && mac->link_duplex == duplex)
3824                 return 0;
3825
3826         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3827         if (ret)
3828                 return ret;
3829
3830         mac->link_speed = speed;
3831         mac->link_duplex = duplex;
3832
3833         return 0;
3834 }
3835
3836 static int
3837 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3838 {
3839         struct hns3_adapter *hns = eth_dev->data->dev_private;
3840         struct hns3_hw *hw = &hns->hw;
3841         struct hns3_pf *pf = &hns->pf;
3842         uint32_t speed;
3843         int ret;
3844
3845         /* If IMP do not support get SFP/qSFP speed, return directly */
3846         if (!pf->support_sfp_query)
3847                 return 0;
3848
3849         ret = hns3_get_sfp_speed(hw, &speed);
3850         if (ret == -EOPNOTSUPP) {
3851                 pf->support_sfp_query = false;
3852                 return ret;
3853         } else if (ret)
3854                 return ret;
3855
3856         if (speed == ETH_SPEED_NUM_NONE)
3857                 return 0; /* do nothing if no SFP */
3858
3859         /* Config full duplex for SFP */
3860         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3861 }
3862
3863 static int
3864 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3865 {
3866         struct hns3_config_mac_mode_cmd *req;
3867         struct hns3_cmd_desc desc;
3868         uint32_t loop_en = 0;
3869         uint8_t val = 0;
3870         int ret;
3871
3872         req = (struct hns3_config_mac_mode_cmd *)desc.data;
3873
3874         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3875         if (enable)
3876                 val = 1;
3877         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3878         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3879         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3880         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3881         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3882         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3883         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3884         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3885         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3886         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3887         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3888         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3889         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3890         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3891         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3892
3893         ret = hns3_cmd_send(hw, &desc, 1);
3894         if (ret)
3895                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3896
3897         return ret;
3898 }
3899
3900 static int
3901 hns3_get_mac_link_status(struct hns3_hw *hw)
3902 {
3903         struct hns3_link_status_cmd *req;
3904         struct hns3_cmd_desc desc;
3905         int link_status;
3906         int ret;
3907
3908         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3909         ret = hns3_cmd_send(hw, &desc, 1);
3910         if (ret) {
3911                 hns3_err(hw, "get link status cmd failed %d", ret);
3912                 return ETH_LINK_DOWN;
3913         }
3914
3915         req = (struct hns3_link_status_cmd *)desc.data;
3916         link_status = req->status & HNS3_LINK_STATUS_UP_M;
3917
3918         return !!link_status;
3919 }
3920
3921 void
3922 hns3_update_link_status(struct hns3_hw *hw)
3923 {
3924         int state;
3925
3926         state = hns3_get_mac_link_status(hw);
3927         if (state != hw->mac.link_status) {
3928                 hw->mac.link_status = state;
3929                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
3930         }
3931 }
3932
3933 static void
3934 hns3_service_handler(void *param)
3935 {
3936         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3937         struct hns3_adapter *hns = eth_dev->data->dev_private;
3938         struct hns3_hw *hw = &hns->hw;
3939
3940         if (!hns3_is_reset_pending(hns)) {
3941                 hns3_update_speed_duplex(eth_dev);
3942                 hns3_update_link_status(hw);
3943         } else
3944                 hns3_warn(hw, "Cancel the query when reset is pending");
3945
3946         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3947 }
3948
3949 static int
3950 hns3_init_hardware(struct hns3_adapter *hns)
3951 {
3952         struct hns3_hw *hw = &hns->hw;
3953         int ret;
3954
3955         ret = hns3_map_tqp(hw);
3956         if (ret) {
3957                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3958                 return ret;
3959         }
3960
3961         ret = hns3_init_umv_space(hw);
3962         if (ret) {
3963                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3964                 return ret;
3965         }
3966
3967         ret = hns3_mac_init(hw);
3968         if (ret) {
3969                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3970                 goto err_mac_init;
3971         }
3972
3973         ret = hns3_init_mgr_tbl(hw);
3974         if (ret) {
3975                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3976                 goto err_mac_init;
3977         }
3978
3979         ret = hns3_set_promisc_mode(hw, false, false);
3980         if (ret) {
3981                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3982                 goto err_mac_init;
3983         }
3984
3985         ret = hns3_clear_all_vfs_promisc_mode(hw);
3986         if (ret) {
3987                 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
3988                              ret);
3989                 goto err_mac_init;
3990         }
3991
3992         ret = hns3_init_vlan_config(hns);
3993         if (ret) {
3994                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
3995                 goto err_mac_init;
3996         }
3997
3998         ret = hns3_dcb_init(hw);
3999         if (ret) {
4000                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4001                 goto err_mac_init;
4002         }
4003
4004         ret = hns3_init_fd_config(hns);
4005         if (ret) {
4006                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4007                 goto err_mac_init;
4008         }
4009
4010         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4011         if (ret) {
4012                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4013                 goto err_mac_init;
4014         }
4015
4016         ret = hns3_config_gro(hw, false);
4017         if (ret) {
4018                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4019                 goto err_mac_init;
4020         }
4021         return 0;
4022
4023 err_mac_init:
4024         hns3_uninit_umv_space(hw);
4025         return ret;
4026 }
4027
4028 static int
4029 hns3_init_pf(struct rte_eth_dev *eth_dev)
4030 {
4031         struct rte_device *dev = eth_dev->device;
4032         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4033         struct hns3_adapter *hns = eth_dev->data->dev_private;
4034         struct hns3_hw *hw = &hns->hw;
4035         int ret;
4036
4037         PMD_INIT_FUNC_TRACE();
4038
4039         /* Get hardware io base address from pcie BAR2 IO space */
4040         hw->io_base = pci_dev->mem_resource[2].addr;
4041
4042         /* Firmware command queue initialize */
4043         ret = hns3_cmd_init_queue(hw);
4044         if (ret) {
4045                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4046                 goto err_cmd_init_queue;
4047         }
4048
4049         hns3_clear_all_event_cause(hw);
4050
4051         /* Firmware command initialize */
4052         ret = hns3_cmd_init(hw);
4053         if (ret) {
4054                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4055                 goto err_cmd_init;
4056         }
4057
4058         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4059                                          hns3_interrupt_handler,
4060                                          eth_dev);
4061         if (ret) {
4062                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4063                 goto err_intr_callback_register;
4064         }
4065
4066         /* Enable interrupt */
4067         rte_intr_enable(&pci_dev->intr_handle);
4068         hns3_pf_enable_irq0(hw);
4069
4070         /* Get configuration */
4071         ret = hns3_get_configuration(hw);
4072         if (ret) {
4073                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4074                 goto err_get_config;
4075         }
4076
4077         ret = hns3_init_hardware(hns);
4078         if (ret) {
4079                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4080                 goto err_get_config;
4081         }
4082
4083         /* Initialize flow director filter list & hash */
4084         ret = hns3_fdir_filter_init(hns);
4085         if (ret) {
4086                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4087                 goto err_hw_init;
4088         }
4089
4090         hns3_set_default_rss_args(hw);
4091
4092         ret = hns3_enable_hw_error_intr(hns, true);
4093         if (ret) {
4094                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4095                              ret);
4096                 goto err_fdir;
4097         }
4098
4099         /*
4100          * In the initialization clearing the all hardware mapping relationship
4101          * configurations between queues and interrupt vectors is needed, so
4102          * some error caused by the residual configurations, such as the
4103          * unexpected interrupt, can be avoid.
4104          */
4105         ret = hns3_init_ring_with_vector(hw);
4106         if (ret)
4107                 goto err_fdir;
4108
4109         return 0;
4110
4111 err_fdir:
4112         hns3_fdir_filter_uninit(hns);
4113 err_hw_init:
4114         hns3_uninit_umv_space(hw);
4115
4116 err_get_config:
4117         hns3_pf_disable_irq0(hw);
4118         rte_intr_disable(&pci_dev->intr_handle);
4119         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4120                              eth_dev);
4121
4122 err_intr_callback_register:
4123         hns3_cmd_uninit(hw);
4124
4125 err_cmd_init:
4126         hns3_cmd_destroy_queue(hw);
4127
4128 err_cmd_init_queue:
4129         hw->io_base = NULL;
4130
4131         return ret;
4132 }
4133
4134 static void
4135 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4136 {
4137         struct hns3_adapter *hns = eth_dev->data->dev_private;
4138         struct rte_device *dev = eth_dev->device;
4139         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4140         struct hns3_hw *hw = &hns->hw;
4141
4142         PMD_INIT_FUNC_TRACE();
4143
4144         hns3_enable_hw_error_intr(hns, false);
4145         hns3_rss_uninit(hns);
4146         hns3_fdir_filter_uninit(hns);
4147         hns3_uninit_umv_space(hw);
4148         hns3_pf_disable_irq0(hw);
4149         rte_intr_disable(&pci_dev->intr_handle);
4150         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4151                              eth_dev);
4152         hns3_cmd_uninit(hw);
4153         hns3_cmd_destroy_queue(hw);
4154         hw->io_base = NULL;
4155 }
4156
4157 static int
4158 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4159 {
4160         struct hns3_hw *hw = &hns->hw;
4161         int ret;
4162
4163         ret = hns3_dcb_cfg_update(hns);
4164         if (ret)
4165                 return ret;
4166
4167         /* Enable queues */
4168         ret = hns3_start_queues(hns, reset_queue);
4169         if (ret) {
4170                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4171                 return ret;
4172         }
4173
4174         /* Enable MAC */
4175         ret = hns3_cfg_mac_mode(hw, true);
4176         if (ret) {
4177                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4178                 goto err_config_mac_mode;
4179         }
4180         return 0;
4181
4182 err_config_mac_mode:
4183         hns3_stop_queues(hns, true);
4184         return ret;
4185 }
4186
4187 static int
4188 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4189 {
4190         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4191         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4192         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4193         uint32_t intr_vector;
4194         uint8_t base = 0;
4195         uint8_t vec = 0;
4196         uint16_t q_id;
4197         int ret;
4198
4199         if (dev->data->dev_conf.intr_conf.rxq == 0)
4200                 return 0;
4201
4202         /* disable uio/vfio intr/eventfd mapping */
4203         rte_intr_disable(intr_handle);
4204
4205         /* check and configure queue intr-vector mapping */
4206         if (rte_intr_cap_multiple(intr_handle) ||
4207             !RTE_ETH_DEV_SRIOV(dev).active) {
4208                 intr_vector = hw->used_rx_queues;
4209                 /* creates event fd for each intr vector when MSIX is used */
4210                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4211                         return -EINVAL;
4212         }
4213         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4214                 intr_handle->intr_vec =
4215                         rte_zmalloc("intr_vec",
4216                                     hw->used_rx_queues * sizeof(int), 0);
4217                 if (intr_handle->intr_vec == NULL) {
4218                         hns3_err(hw, "Failed to allocate %d rx_queues"
4219                                      " intr_vec", hw->used_rx_queues);
4220                         ret = -ENOMEM;
4221                         goto alloc_intr_vec_error;
4222                 }
4223         }
4224
4225         if (rte_intr_allow_others(intr_handle)) {
4226                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4227                 base = RTE_INTR_VEC_RXTX_OFFSET;
4228         }
4229         if (rte_intr_dp_is_en(intr_handle)) {
4230                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4231                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4232                                                          HNS3_RING_TYPE_RX,
4233                                                          q_id);
4234                         if (ret)
4235                                 goto bind_vector_error;
4236                         intr_handle->intr_vec[q_id] = vec;
4237                         if (vec < base + intr_handle->nb_efd - 1)
4238                                 vec++;
4239                 }
4240         }
4241         rte_intr_enable(intr_handle);
4242         return 0;
4243
4244 bind_vector_error:
4245         rte_intr_efd_disable(intr_handle);
4246         if (intr_handle->intr_vec) {
4247                 free(intr_handle->intr_vec);
4248                 intr_handle->intr_vec = NULL;
4249         }
4250         return ret;
4251 alloc_intr_vec_error:
4252         rte_intr_efd_disable(intr_handle);
4253         return ret;
4254 }
4255
4256 static int
4257 hns3_dev_start(struct rte_eth_dev *dev)
4258 {
4259         struct hns3_adapter *hns = dev->data->dev_private;
4260         struct hns3_hw *hw = &hns->hw;
4261         int ret;
4262
4263         PMD_INIT_FUNC_TRACE();
4264         if (rte_atomic16_read(&hw->reset.resetting))
4265                 return -EBUSY;
4266
4267         rte_spinlock_lock(&hw->lock);
4268         hw->adapter_state = HNS3_NIC_STARTING;
4269
4270         ret = hns3_do_start(hns, true);
4271         if (ret) {
4272                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4273                 rte_spinlock_unlock(&hw->lock);
4274                 return ret;
4275         }
4276
4277         hw->adapter_state = HNS3_NIC_STARTED;
4278         rte_spinlock_unlock(&hw->lock);
4279
4280         ret = hns3_map_rx_interrupt(dev);
4281         if (ret)
4282                 return ret;
4283         hns3_set_rxtx_function(dev);
4284         hns3_mp_req_start_rxtx(dev);
4285         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4286
4287         hns3_info(hw, "hns3 dev start successful!");
4288         return 0;
4289 }
4290
4291 static int
4292 hns3_do_stop(struct hns3_adapter *hns)
4293 {
4294         struct hns3_hw *hw = &hns->hw;
4295         bool reset_queue;
4296         int ret;
4297
4298         ret = hns3_cfg_mac_mode(hw, false);
4299         if (ret)
4300                 return ret;
4301         hw->mac.link_status = ETH_LINK_DOWN;
4302
4303         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4304                 hns3_configure_all_mac_addr(hns, true);
4305                 reset_queue = true;
4306         } else
4307                 reset_queue = false;
4308         hw->mac.default_addr_setted = false;
4309         return hns3_stop_queues(hns, reset_queue);
4310 }
4311
4312 static void
4313 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4314 {
4315         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4316         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4317         struct hns3_adapter *hns = dev->data->dev_private;
4318         struct hns3_hw *hw = &hns->hw;
4319         uint8_t base = 0;
4320         uint8_t vec = 0;
4321         uint16_t q_id;
4322
4323         if (dev->data->dev_conf.intr_conf.rxq == 0)
4324                 return;
4325
4326         /* unmap the ring with vector */
4327         if (rte_intr_allow_others(intr_handle)) {
4328                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4329                 base = RTE_INTR_VEC_RXTX_OFFSET;
4330         }
4331         if (rte_intr_dp_is_en(intr_handle)) {
4332                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4333                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4334                                                          HNS3_RING_TYPE_RX,
4335                                                          q_id);
4336                         if (vec < base + intr_handle->nb_efd - 1)
4337                                 vec++;
4338                 }
4339         }
4340         /* Clean datapath event and queue/vec mapping */
4341         rte_intr_efd_disable(intr_handle);
4342         if (intr_handle->intr_vec) {
4343                 rte_free(intr_handle->intr_vec);
4344                 intr_handle->intr_vec = NULL;
4345         }
4346 }
4347
4348 static void
4349 hns3_dev_stop(struct rte_eth_dev *dev)
4350 {
4351         struct hns3_adapter *hns = dev->data->dev_private;
4352         struct hns3_hw *hw = &hns->hw;
4353
4354         PMD_INIT_FUNC_TRACE();
4355
4356         hw->adapter_state = HNS3_NIC_STOPPING;
4357         hns3_set_rxtx_function(dev);
4358         rte_wmb();
4359         /* Disable datapath on secondary process. */
4360         hns3_mp_req_stop_rxtx(dev);
4361         /* Prevent crashes when queues are still in use. */
4362         rte_delay_ms(hw->tqps_num);
4363
4364         rte_spinlock_lock(&hw->lock);
4365         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4366                 hns3_do_stop(hns);
4367                 hns3_dev_release_mbufs(hns);
4368                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4369         }
4370         rte_eal_alarm_cancel(hns3_service_handler, dev);
4371         rte_spinlock_unlock(&hw->lock);
4372         hns3_unmap_rx_interrupt(dev);
4373 }
4374
4375 static void
4376 hns3_dev_close(struct rte_eth_dev *eth_dev)
4377 {
4378         struct hns3_adapter *hns = eth_dev->data->dev_private;
4379         struct hns3_hw *hw = &hns->hw;
4380
4381         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4382                 rte_free(eth_dev->process_private);
4383                 eth_dev->process_private = NULL;
4384                 return;
4385         }
4386
4387         if (hw->adapter_state == HNS3_NIC_STARTED)
4388                 hns3_dev_stop(eth_dev);
4389
4390         hw->adapter_state = HNS3_NIC_CLOSING;
4391         hns3_reset_abort(hns);
4392         hw->adapter_state = HNS3_NIC_CLOSED;
4393
4394         hns3_configure_all_mc_mac_addr(hns, true);
4395         hns3_remove_all_vlan_table(hns);
4396         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4397         hns3_uninit_pf(eth_dev);
4398         hns3_free_all_queues(eth_dev);
4399         rte_free(hw->reset.wait_data);
4400         rte_free(eth_dev->process_private);
4401         eth_dev->process_private = NULL;
4402         hns3_mp_uninit_primary();
4403         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4404 }
4405
4406 static int
4407 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4408 {
4409         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4410         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4411
4412         fc_conf->pause_time = pf->pause_time;
4413
4414         /* return fc current mode */
4415         switch (hw->current_mode) {
4416         case HNS3_FC_FULL:
4417                 fc_conf->mode = RTE_FC_FULL;
4418                 break;
4419         case HNS3_FC_TX_PAUSE:
4420                 fc_conf->mode = RTE_FC_TX_PAUSE;
4421                 break;
4422         case HNS3_FC_RX_PAUSE:
4423                 fc_conf->mode = RTE_FC_RX_PAUSE;
4424                 break;
4425         case HNS3_FC_NONE:
4426         default:
4427                 fc_conf->mode = RTE_FC_NONE;
4428                 break;
4429         }
4430
4431         return 0;
4432 }
4433
4434 static void
4435 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4436 {
4437         switch (mode) {
4438         case RTE_FC_NONE:
4439                 hw->requested_mode = HNS3_FC_NONE;
4440                 break;
4441         case RTE_FC_RX_PAUSE:
4442                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4443                 break;
4444         case RTE_FC_TX_PAUSE:
4445                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4446                 break;
4447         case RTE_FC_FULL:
4448                 hw->requested_mode = HNS3_FC_FULL;
4449                 break;
4450         default:
4451                 hw->requested_mode = HNS3_FC_NONE;
4452                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4453                           "configured to RTE_FC_NONE", mode);
4454                 break;
4455         }
4456 }
4457
4458 static int
4459 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4460 {
4461         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4462         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4463         int ret;
4464
4465         if (fc_conf->high_water || fc_conf->low_water ||
4466             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4467                 hns3_err(hw, "Unsupported flow control settings specified, "
4468                          "high_water(%u), low_water(%u), send_xon(%u) and "
4469                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4470                          fc_conf->high_water, fc_conf->low_water,
4471                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4472                 return -EINVAL;
4473         }
4474         if (fc_conf->autoneg) {
4475                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4476                 return -EINVAL;
4477         }
4478         if (!fc_conf->pause_time) {
4479                 hns3_err(hw, "Invalid pause time %d setting.",
4480                          fc_conf->pause_time);
4481                 return -EINVAL;
4482         }
4483
4484         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4485             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4486                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4487                          "current_fc_status = %d", hw->current_fc_status);
4488                 return -EOPNOTSUPP;
4489         }
4490
4491         hns3_get_fc_mode(hw, fc_conf->mode);
4492         if (hw->requested_mode == hw->current_mode &&
4493             pf->pause_time == fc_conf->pause_time)
4494                 return 0;
4495
4496         rte_spinlock_lock(&hw->lock);
4497         ret = hns3_fc_enable(dev, fc_conf);
4498         rte_spinlock_unlock(&hw->lock);
4499
4500         return ret;
4501 }
4502
4503 static int
4504 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4505                             struct rte_eth_pfc_conf *pfc_conf)
4506 {
4507         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4508         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4509         uint8_t priority;
4510         int ret;
4511
4512         if (!hns3_dev_dcb_supported(hw)) {
4513                 hns3_err(hw, "This port does not support dcb configurations.");
4514                 return -EOPNOTSUPP;
4515         }
4516
4517         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4518             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4519                 hns3_err(hw, "Unsupported flow control settings specified, "
4520                          "high_water(%u), low_water(%u), send_xon(%u) and "
4521                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4522                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4523                          pfc_conf->fc.send_xon,
4524                          pfc_conf->fc.mac_ctrl_frame_fwd);
4525                 return -EINVAL;
4526         }
4527         if (pfc_conf->fc.autoneg) {
4528                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4529                 return -EINVAL;
4530         }
4531         if (pfc_conf->fc.pause_time == 0) {
4532                 hns3_err(hw, "Invalid pause time %d setting.",
4533                          pfc_conf->fc.pause_time);
4534                 return -EINVAL;
4535         }
4536
4537         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4538             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4539                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4540                              "current_fc_status = %d", hw->current_fc_status);
4541                 return -EOPNOTSUPP;
4542         }
4543
4544         priority = pfc_conf->priority;
4545         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4546         if (hw->dcb_info.pfc_en & BIT(priority) &&
4547             hw->requested_mode == hw->current_mode &&
4548             pfc_conf->fc.pause_time == pf->pause_time)
4549                 return 0;
4550
4551         rte_spinlock_lock(&hw->lock);
4552         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4553         rte_spinlock_unlock(&hw->lock);
4554
4555         return ret;
4556 }
4557
4558 static int
4559 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4560 {
4561         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4562         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4563         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4564         int i;
4565
4566         rte_spinlock_lock(&hw->lock);
4567         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4568                 dcb_info->nb_tcs = pf->local_max_tc;
4569         else
4570                 dcb_info->nb_tcs = 1;
4571
4572         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4573                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4574         for (i = 0; i < dcb_info->nb_tcs; i++)
4575                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4576
4577         for (i = 0; i < hw->num_tc; i++) {
4578                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4579                 dcb_info->tc_queue.tc_txq[0][i].base =
4580                                                 hw->tc_queue[i].tqp_offset;
4581                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4582                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4583                                                 hw->tc_queue[i].tqp_count;
4584         }
4585         rte_spinlock_unlock(&hw->lock);
4586
4587         return 0;
4588 }
4589
4590 static int
4591 hns3_reinit_dev(struct hns3_adapter *hns)
4592 {
4593         struct hns3_hw *hw = &hns->hw;
4594         int ret;
4595
4596         ret = hns3_cmd_init(hw);
4597         if (ret) {
4598                 hns3_err(hw, "Failed to init cmd: %d", ret);
4599                 return ret;
4600         }
4601
4602         ret = hns3_reset_all_queues(hns);
4603         if (ret) {
4604                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4605                 goto err_init;
4606         }
4607
4608         ret = hns3_init_hardware(hns);
4609         if (ret) {
4610                 hns3_err(hw, "Failed to init hardware: %d", ret);
4611                 goto err_init;
4612         }
4613
4614         ret = hns3_enable_hw_error_intr(hns, true);
4615         if (ret) {
4616                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4617                              ret);
4618                 goto err_mac_init;
4619         }
4620         hns3_info(hw, "Reset done, driver initialization finished.");
4621
4622         return 0;
4623
4624 err_mac_init:
4625         hns3_uninit_umv_space(hw);
4626 err_init:
4627         hns3_cmd_uninit(hw);
4628
4629         return ret;
4630 }
4631
4632 static bool
4633 is_pf_reset_done(struct hns3_hw *hw)
4634 {
4635         uint32_t val, reg, reg_bit;
4636
4637         switch (hw->reset.level) {
4638         case HNS3_IMP_RESET:
4639                 reg = HNS3_GLOBAL_RESET_REG;
4640                 reg_bit = HNS3_IMP_RESET_BIT;
4641                 break;
4642         case HNS3_GLOBAL_RESET:
4643                 reg = HNS3_GLOBAL_RESET_REG;
4644                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4645                 break;
4646         case HNS3_FUNC_RESET:
4647                 reg = HNS3_FUN_RST_ING;
4648                 reg_bit = HNS3_FUN_RST_ING_B;
4649                 break;
4650         case HNS3_FLR_RESET:
4651         default:
4652                 hns3_err(hw, "Wait for unsupported reset level: %d",
4653                          hw->reset.level);
4654                 return true;
4655         }
4656         val = hns3_read_dev(hw, reg);
4657         if (hns3_get_bit(val, reg_bit))
4658                 return false;
4659         else
4660                 return true;
4661 }
4662
4663 bool
4664 hns3_is_reset_pending(struct hns3_adapter *hns)
4665 {
4666         struct hns3_hw *hw = &hns->hw;
4667         enum hns3_reset_level reset;
4668
4669         hns3_check_event_cause(hns, NULL);
4670         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4671         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4672                 hns3_warn(hw, "High level reset %d is pending", reset);
4673                 return true;
4674         }
4675         reset = hns3_get_reset_level(hns, &hw->reset.request);
4676         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4677                 hns3_warn(hw, "High level reset %d is request", reset);
4678                 return true;
4679         }
4680         return false;
4681 }
4682
4683 static int
4684 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4685 {
4686         struct hns3_hw *hw = &hns->hw;
4687         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4688         struct timeval tv;
4689
4690         if (wait_data->result == HNS3_WAIT_SUCCESS)
4691                 return 0;
4692         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4693                 gettimeofday(&tv, NULL);
4694                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4695                           tv.tv_sec, tv.tv_usec);
4696                 return -ETIME;
4697         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4698                 return -EAGAIN;
4699
4700         wait_data->hns = hns;
4701         wait_data->check_completion = is_pf_reset_done;
4702         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4703                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4704         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4705         wait_data->count = HNS3_RESET_WAIT_CNT;
4706         wait_data->result = HNS3_WAIT_REQUEST;
4707         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4708         return -EAGAIN;
4709 }
4710
4711 static int
4712 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4713 {
4714         struct hns3_cmd_desc desc;
4715         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4716
4717         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4718         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4719         req->fun_reset_vfid = func_id;
4720
4721         return hns3_cmd_send(hw, &desc, 1);
4722 }
4723
4724 static int
4725 hns3_imp_reset_cmd(struct hns3_hw *hw)
4726 {
4727         struct hns3_cmd_desc desc;
4728
4729         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4730         desc.data[0] = 0xeedd;
4731
4732         return hns3_cmd_send(hw, &desc, 1);
4733 }
4734
4735 static void
4736 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4737 {
4738         struct hns3_hw *hw = &hns->hw;
4739         struct timeval tv;
4740         uint32_t val;
4741
4742         gettimeofday(&tv, NULL);
4743         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4744             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4745                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4746                           tv.tv_sec, tv.tv_usec);
4747                 return;
4748         }
4749
4750         switch (reset_level) {
4751         case HNS3_IMP_RESET:
4752                 hns3_imp_reset_cmd(hw);
4753                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4754                           tv.tv_sec, tv.tv_usec);
4755                 break;
4756         case HNS3_GLOBAL_RESET:
4757                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4758                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4759                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4760                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4761                           tv.tv_sec, tv.tv_usec);
4762                 break;
4763         case HNS3_FUNC_RESET:
4764                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4765                           tv.tv_sec, tv.tv_usec);
4766                 /* schedule again to check later */
4767                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4768                 hns3_schedule_reset(hns);
4769                 break;
4770         default:
4771                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4772                 return;
4773         }
4774         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4775 }
4776
4777 static enum hns3_reset_level
4778 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4779 {
4780         struct hns3_hw *hw = &hns->hw;
4781         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4782
4783         /* Return the highest priority reset level amongst all */
4784         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4785                 reset_level = HNS3_IMP_RESET;
4786         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4787                 reset_level = HNS3_GLOBAL_RESET;
4788         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4789                 reset_level = HNS3_FUNC_RESET;
4790         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4791                 reset_level = HNS3_FLR_RESET;
4792
4793         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4794                 return HNS3_NONE_RESET;
4795
4796         return reset_level;
4797 }
4798
4799 static int
4800 hns3_prepare_reset(struct hns3_adapter *hns)
4801 {
4802         struct hns3_hw *hw = &hns->hw;
4803         uint32_t reg_val;
4804         int ret;
4805
4806         switch (hw->reset.level) {
4807         case HNS3_FUNC_RESET:
4808                 ret = hns3_func_reset_cmd(hw, 0);
4809                 if (ret)
4810                         return ret;
4811
4812                 /*
4813                  * After performaning pf reset, it is not necessary to do the
4814                  * mailbox handling or send any command to firmware, because
4815                  * any mailbox handling or command to firmware is only valid
4816                  * after hns3_cmd_init is called.
4817                  */
4818                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4819                 hw->reset.stats.request_cnt++;
4820                 break;
4821         case HNS3_IMP_RESET:
4822                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4823                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4824                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4825                 break;
4826         default:
4827                 break;
4828         }
4829         return 0;
4830 }
4831
4832 static int
4833 hns3_set_rst_done(struct hns3_hw *hw)
4834 {
4835         struct hns3_pf_rst_done_cmd *req;
4836         struct hns3_cmd_desc desc;
4837
4838         req = (struct hns3_pf_rst_done_cmd *)desc.data;
4839         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4840         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4841         return hns3_cmd_send(hw, &desc, 1);
4842 }
4843
4844 static int
4845 hns3_stop_service(struct hns3_adapter *hns)
4846 {
4847         struct hns3_hw *hw = &hns->hw;
4848         struct rte_eth_dev *eth_dev;
4849
4850         eth_dev = &rte_eth_devices[hw->data->port_id];
4851         if (hw->adapter_state == HNS3_NIC_STARTED)
4852                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4853         hw->mac.link_status = ETH_LINK_DOWN;
4854
4855         hns3_set_rxtx_function(eth_dev);
4856         rte_wmb();
4857         /* Disable datapath on secondary process. */
4858         hns3_mp_req_stop_rxtx(eth_dev);
4859         rte_delay_ms(hw->tqps_num);
4860
4861         rte_spinlock_lock(&hw->lock);
4862         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4863             hw->adapter_state == HNS3_NIC_STOPPING) {
4864                 hns3_do_stop(hns);
4865                 hw->reset.mbuf_deferred_free = true;
4866         } else
4867                 hw->reset.mbuf_deferred_free = false;
4868
4869         /*
4870          * It is cumbersome for hardware to pick-and-choose entries for deletion
4871          * from table space. Hence, for function reset software intervention is
4872          * required to delete the entries
4873          */
4874         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
4875                 hns3_configure_all_mc_mac_addr(hns, true);
4876         rte_spinlock_unlock(&hw->lock);
4877
4878         return 0;
4879 }
4880
4881 static int
4882 hns3_start_service(struct hns3_adapter *hns)
4883 {
4884         struct hns3_hw *hw = &hns->hw;
4885         struct rte_eth_dev *eth_dev;
4886
4887         if (hw->reset.level == HNS3_IMP_RESET ||
4888             hw->reset.level == HNS3_GLOBAL_RESET)
4889                 hns3_set_rst_done(hw);
4890         eth_dev = &rte_eth_devices[hw->data->port_id];
4891         hns3_set_rxtx_function(eth_dev);
4892         hns3_mp_req_start_rxtx(eth_dev);
4893         if (hw->adapter_state == HNS3_NIC_STARTED)
4894                 hns3_service_handler(eth_dev);
4895
4896         return 0;
4897 }
4898
4899 static int
4900 hns3_restore_conf(struct hns3_adapter *hns)
4901 {
4902         struct hns3_hw *hw = &hns->hw;
4903         int ret;
4904
4905         ret = hns3_configure_all_mac_addr(hns, false);
4906         if (ret)
4907                 return ret;
4908
4909         ret = hns3_configure_all_mc_mac_addr(hns, false);
4910         if (ret)
4911                 goto err_mc_mac;
4912
4913         ret = hns3_dev_promisc_restore(hns);
4914         if (ret)
4915                 goto err_promisc;
4916
4917         ret = hns3_restore_vlan_table(hns);
4918         if (ret)
4919                 goto err_promisc;
4920
4921         ret = hns3_restore_vlan_conf(hns);
4922         if (ret)
4923                 goto err_promisc;
4924
4925         ret = hns3_restore_all_fdir_filter(hns);
4926         if (ret)
4927                 goto err_promisc;
4928
4929         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
4930                 ret = hns3_do_start(hns, false);
4931                 if (ret)
4932                         goto err_promisc;
4933                 hns3_info(hw, "hns3 dev restart successful!");
4934         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
4935                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4936         return 0;
4937
4938 err_promisc:
4939         hns3_configure_all_mc_mac_addr(hns, true);
4940 err_mc_mac:
4941         hns3_configure_all_mac_addr(hns, true);
4942         return ret;
4943 }
4944
4945 static void
4946 hns3_reset_service(void *param)
4947 {
4948         struct hns3_adapter *hns = (struct hns3_adapter *)param;
4949         struct hns3_hw *hw = &hns->hw;
4950         enum hns3_reset_level reset_level;
4951         struct timeval tv_delta;
4952         struct timeval tv_start;
4953         struct timeval tv;
4954         uint64_t msec;
4955         int ret;
4956
4957         /*
4958          * The interrupt is not triggered within the delay time.
4959          * The interrupt may have been lost. It is necessary to handle
4960          * the interrupt to recover from the error.
4961          */
4962         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
4963                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
4964                 hns3_err(hw, "Handling interrupts in delayed tasks");
4965                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
4966                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4967                 if (reset_level == HNS3_NONE_RESET) {
4968                         hns3_err(hw, "No reset level is set, try IMP reset");
4969                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
4970                 }
4971         }
4972         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
4973
4974         /*
4975          * Check if there is any ongoing reset in the hardware. This status can
4976          * be checked from reset_pending. If there is then, we need to wait for
4977          * hardware to complete reset.
4978          *    a. If we are able to figure out in reasonable time that hardware
4979          *       has fully resetted then, we can proceed with driver, client
4980          *       reset.
4981          *    b. else, we can come back later to check this status so re-sched
4982          *       now.
4983          */
4984         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4985         if (reset_level != HNS3_NONE_RESET) {
4986                 gettimeofday(&tv_start, NULL);
4987                 ret = hns3_reset_process(hns, reset_level);
4988                 gettimeofday(&tv, NULL);
4989                 timersub(&tv, &tv_start, &tv_delta);
4990                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
4991                        tv_delta.tv_usec / USEC_PER_MSEC;
4992                 if (msec > HNS3_RESET_PROCESS_MS)
4993                         hns3_err(hw, "%d handle long time delta %" PRIx64
4994                                      " ms time=%ld.%.6ld",
4995                                  hw->reset.level, msec,
4996                                  tv.tv_sec, tv.tv_usec);
4997                 if (ret == -EAGAIN)
4998                         return;
4999         }
5000
5001         /* Check if we got any *new* reset requests to be honored */
5002         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5003         if (reset_level != HNS3_NONE_RESET)
5004                 hns3_msix_process(hns, reset_level);
5005 }
5006
5007 static const struct eth_dev_ops hns3_eth_dev_ops = {
5008         .dev_start          = hns3_dev_start,
5009         .dev_stop           = hns3_dev_stop,
5010         .dev_close          = hns3_dev_close,
5011         .promiscuous_enable = hns3_dev_promiscuous_enable,
5012         .promiscuous_disable = hns3_dev_promiscuous_disable,
5013         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5014         .allmulticast_disable = hns3_dev_allmulticast_disable,
5015         .mtu_set            = hns3_dev_mtu_set,
5016         .stats_get          = hns3_stats_get,
5017         .stats_reset        = hns3_stats_reset,
5018         .xstats_get         = hns3_dev_xstats_get,
5019         .xstats_get_names   = hns3_dev_xstats_get_names,
5020         .xstats_reset       = hns3_dev_xstats_reset,
5021         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5022         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5023         .dev_infos_get          = hns3_dev_infos_get,
5024         .fw_version_get         = hns3_fw_version_get,
5025         .rx_queue_setup         = hns3_rx_queue_setup,
5026         .tx_queue_setup         = hns3_tx_queue_setup,
5027         .rx_queue_release       = hns3_dev_rx_queue_release,
5028         .tx_queue_release       = hns3_dev_tx_queue_release,
5029         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5030         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5031         .dev_configure          = hns3_dev_configure,
5032         .flow_ctrl_get          = hns3_flow_ctrl_get,
5033         .flow_ctrl_set          = hns3_flow_ctrl_set,
5034         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5035         .mac_addr_add           = hns3_add_mac_addr,
5036         .mac_addr_remove        = hns3_remove_mac_addr,
5037         .mac_addr_set           = hns3_set_default_mac_addr,
5038         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5039         .link_update            = hns3_dev_link_update,
5040         .rss_hash_update        = hns3_dev_rss_hash_update,
5041         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5042         .reta_update            = hns3_dev_rss_reta_update,
5043         .reta_query             = hns3_dev_rss_reta_query,
5044         .filter_ctrl            = hns3_dev_filter_ctrl,
5045         .vlan_filter_set        = hns3_vlan_filter_set,
5046         .vlan_tpid_set          = hns3_vlan_tpid_set,
5047         .vlan_offload_set       = hns3_vlan_offload_set,
5048         .vlan_pvid_set          = hns3_vlan_pvid_set,
5049         .get_reg                = hns3_get_regs,
5050         .get_dcb_info           = hns3_get_dcb_info,
5051         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5052 };
5053
5054 static const struct hns3_reset_ops hns3_reset_ops = {
5055         .reset_service       = hns3_reset_service,
5056         .stop_service        = hns3_stop_service,
5057         .prepare_reset       = hns3_prepare_reset,
5058         .wait_hardware_ready = hns3_wait_hardware_ready,
5059         .reinit_dev          = hns3_reinit_dev,
5060         .restore_conf        = hns3_restore_conf,
5061         .start_service       = hns3_start_service,
5062 };
5063
5064 static int
5065 hns3_dev_init(struct rte_eth_dev *eth_dev)
5066 {
5067         struct rte_device *dev = eth_dev->device;
5068         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5069         struct hns3_adapter *hns = eth_dev->data->dev_private;
5070         struct hns3_hw *hw = &hns->hw;
5071         uint16_t device_id = pci_dev->id.device_id;
5072         int ret;
5073
5074         PMD_INIT_FUNC_TRACE();
5075         eth_dev->process_private = (struct hns3_process_private *)
5076             rte_zmalloc_socket("hns3_filter_list",
5077                                sizeof(struct hns3_process_private),
5078                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5079         if (eth_dev->process_private == NULL) {
5080                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5081                 return -ENOMEM;
5082         }
5083         /* initialize flow filter lists */
5084         hns3_filterlist_init(eth_dev);
5085
5086         hns3_set_rxtx_function(eth_dev);
5087         eth_dev->dev_ops = &hns3_eth_dev_ops;
5088         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5089                 hns3_mp_init_secondary();
5090                 hw->secondary_cnt++;
5091                 return 0;
5092         }
5093
5094         hns3_mp_init_primary();
5095         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5096
5097         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5098             device_id == HNS3_DEV_ID_50GE_RDMA ||
5099             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5100                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5101
5102         hns->is_vf = false;
5103         hw->data = eth_dev->data;
5104
5105         /*
5106          * Set default max packet size according to the mtu
5107          * default vale in DPDK frame.
5108          */
5109         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5110
5111         ret = hns3_reset_init(hw);
5112         if (ret)
5113                 goto err_init_reset;
5114         hw->reset.ops = &hns3_reset_ops;
5115
5116         ret = hns3_init_pf(eth_dev);
5117         if (ret) {
5118                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5119                 goto err_init_pf;
5120         }
5121
5122         /* Allocate memory for storing MAC addresses */
5123         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5124                                                sizeof(struct rte_ether_addr) *
5125                                                HNS3_UC_MACADDR_NUM, 0);
5126         if (eth_dev->data->mac_addrs == NULL) {
5127                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5128                              "to store MAC addresses",
5129                              sizeof(struct rte_ether_addr) *
5130                              HNS3_UC_MACADDR_NUM);
5131                 ret = -ENOMEM;
5132                 goto err_rte_zmalloc;
5133         }
5134
5135         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5136                             &eth_dev->data->mac_addrs[0]);
5137
5138         hw->adapter_state = HNS3_NIC_INITIALIZED;
5139         /*
5140          * Pass the information to the rte_eth_dev_close() that it should also
5141          * release the private port resources.
5142          */
5143         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5144
5145         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5146                 hns3_err(hw, "Reschedule reset service after dev_init");
5147                 hns3_schedule_reset(hns);
5148         } else {
5149                 /* IMP will wait ready flag before reset */
5150                 hns3_notify_reset_ready(hw, false);
5151         }
5152
5153         hns3_info(hw, "hns3 dev initialization successful!");
5154         return 0;
5155
5156 err_rte_zmalloc:
5157         hns3_uninit_pf(eth_dev);
5158
5159 err_init_pf:
5160         rte_free(hw->reset.wait_data);
5161 err_init_reset:
5162         eth_dev->dev_ops = NULL;
5163         eth_dev->rx_pkt_burst = NULL;
5164         eth_dev->tx_pkt_burst = NULL;
5165         eth_dev->tx_pkt_prepare = NULL;
5166         rte_free(eth_dev->process_private);
5167         eth_dev->process_private = NULL;
5168         return ret;
5169 }
5170
5171 static int
5172 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5173 {
5174         struct hns3_adapter *hns = eth_dev->data->dev_private;
5175         struct hns3_hw *hw = &hns->hw;
5176
5177         PMD_INIT_FUNC_TRACE();
5178
5179         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5180                 return -EPERM;
5181
5182         eth_dev->dev_ops = NULL;
5183         eth_dev->rx_pkt_burst = NULL;
5184         eth_dev->tx_pkt_burst = NULL;
5185         eth_dev->tx_pkt_prepare = NULL;
5186         if (hw->adapter_state < HNS3_NIC_CLOSING)
5187                 hns3_dev_close(eth_dev);
5188
5189         hw->adapter_state = HNS3_NIC_REMOVED;
5190         return 0;
5191 }
5192
5193 static int
5194 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5195                    struct rte_pci_device *pci_dev)
5196 {
5197         return rte_eth_dev_pci_generic_probe(pci_dev,
5198                                              sizeof(struct hns3_adapter),
5199                                              hns3_dev_init);
5200 }
5201
5202 static int
5203 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5204 {
5205         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5206 }
5207
5208 static const struct rte_pci_id pci_id_hns3_map[] = {
5209         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5210         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5211         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5212         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5213         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5214         { .vendor_id = 0, /* sentinel */ },
5215 };
5216
5217 static struct rte_pci_driver rte_hns3_pmd = {
5218         .id_table = pci_id_hns3_map,
5219         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5220         .probe = eth_hns3_pci_probe,
5221         .remove = eth_hns3_pci_remove,
5222 };
5223
5224 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5225 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5226 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5227
5228 RTE_INIT(hns3_init_log)
5229 {
5230         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5231         if (hns3_logtype_init >= 0)
5232                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5233         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5234         if (hns3_logtype_driver >= 0)
5235                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5236 }