drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static int hns3_add_mc_addr(struct hns3_hw *hw,
  83                             struct rte_ether_addr *mac_addr);
  84 static int hns3_remove_mc_addr(struct hns3_hw *hw,
  85                             struct rte_ether_addr *mac_addr);
  86
  87 static void
  88 hns3_pf_disable_irq0(struct hns3_hw *hw)
  89 {
  90         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  91 }
  92
  93 static void
  94 hns3_pf_enable_irq0(struct hns3_hw *hw)
  95 {
  96         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  97 }
  98
  99 static enum hns3_evt_cause
 100 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 101 {
 102         struct hns3_hw *hw = &hns->hw;
 103         uint32_t vector0_int_stats;
 104         uint32_t cmdq_src_val;
 105         uint32_t val;
 106         enum hns3_evt_cause ret;
 107
 108         /* fetch the events from their corresponding regs */
 109         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 110         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 111
 112         /*
 113          * Assumption: If by any chance reset and mailbox events are reported
 114          * together then we will only process reset event and defer the
 115          * processing of the mailbox events. Since, we would have not cleared
 116          * RX CMDQ event this time we would receive again another interrupt
 117          * from H/W just for the mailbox.
 118          */
 119         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 120                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 121                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 122                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 123                 if (clearval) {
 124                         hw->reset.stats.imp_cnt++;
 125                         hns3_warn(hw, "IMP reset detected, clear reset status");
 126                 } else {
 127                         hns3_schedule_delayed_reset(hns);
 128                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 129                 }
 130
 131                 ret = HNS3_VECTOR0_EVENT_RST;
 132                 goto out;
 133         }
 134
 135         /* Global reset */
 136         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 137                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 138                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 139                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 140                 if (clearval) {
 141                         hw->reset.stats.global_cnt++;
 142                         hns3_warn(hw, "Global reset detected, clear reset status");
 143                 } else {
 144                         hns3_schedule_delayed_reset(hns);
 145                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 146                 }
 147
 148                 ret = HNS3_VECTOR0_EVENT_RST;
 149                 goto out;
 150         }
 151
 152         /* check for vector0 msix event source */
 153         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 154                 val = vector0_int_stats;
 155                 ret = HNS3_VECTOR0_EVENT_ERR;
 156                 goto out;
 157         }
 158
 159         /* check for vector0 mailbox(=CMDQ RX) event source */
 160         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 161                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 162                 val = cmdq_src_val;
 163                 ret = HNS3_VECTOR0_EVENT_MBX;
 164                 goto out;
 165         }
 166
 167         if (clearval && (vector0_int_stats || cmdq_src_val))
 168                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 169                           vector0_int_stats, cmdq_src_val);
 170         val = vector0_int_stats;
 171         ret = HNS3_VECTOR0_EVENT_OTHER;
 172 out:
 173
 174         if (clearval)
 175                 *clearval = val;
 176         return ret;
 177 }
 178
 179 static void
 180 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 181 {
 182         if (event_type == HNS3_VECTOR0_EVENT_RST)
 183                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 184         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 185                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 186 }
 187
 188 static void
 189 hns3_clear_all_event_cause(struct hns3_hw *hw)
 190 {
 191         uint32_t vector0_int_stats;
 192         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 193
 194         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 195                 hns3_warn(hw, "Probe during IMP reset interrupt");
 196
 197         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 198                 hns3_warn(hw, "Probe during Global reset interrupt");
 199
 200         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 201                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 202                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 203                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 204         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 205 }
 206
 207 static void
 208 hns3_interrupt_handler(void *param)
 209 {
 210         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 211         struct hns3_adapter *hns = dev->data->dev_private;
 212         struct hns3_hw *hw = &hns->hw;
 213         enum hns3_evt_cause event_cause;
 214         uint32_t clearval = 0;
 215
 216         /* Disable interrupt */
 217         hns3_pf_disable_irq0(hw);
 218
 219         event_cause = hns3_check_event_cause(hns, &clearval);
 220
 221         /* vector 0 interrupt is shared with reset and mailbox source events. */
 222         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 223                 hns3_handle_msix_error(hns, &hw->reset.request);
 224                 hns3_schedule_reset(hns);
 225         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 226                 hns3_schedule_reset(hns);
 227         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 228                 hns3_dev_handle_mbx_msg(hw);
 229         else
 230                 hns3_err(hw, "Received unknown event");
 231
 232         hns3_clear_event_cause(hw, event_cause, clearval);
 233         /* Enable interrupt if it is not cause by reset */
 234         hns3_pf_enable_irq0(hw);
 235 }
 236
 237 static int
 238 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 239 {
 240 #define HNS3_VLAN_ID_OFFSET_STEP        160
 241 #define HNS3_VLAN_BYTE_SIZE             8
 242         struct hns3_vlan_filter_pf_cfg_cmd *req;
 243         struct hns3_hw *hw = &hns->hw;
 244         uint8_t vlan_offset_byte_val;
 245         struct hns3_cmd_desc desc;
 246         uint8_t vlan_offset_byte;
 247         uint8_t vlan_offset_base;
 248         int ret;
 249
 250         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 251
 252         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 253         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 254                            HNS3_VLAN_BYTE_SIZE;
 255         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 256
 257         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 258         req->vlan_offset = vlan_offset_base;
 259         req->vlan_cfg = on ? 0 : 1;
 260         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 261
 262         ret = hns3_cmd_send(hw, &desc, 1);
 263         if (ret)
 264                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 265                          vlan_id, ret);
 266
 267         return ret;
 268 }
 269
 270 static void
 271 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 272 {
 273         struct hns3_user_vlan_table *vlan_entry;
 274         struct hns3_pf *pf = &hns->pf;
 275
 276         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 277                 if (vlan_entry->vlan_id == vlan_id) {
 278                         if (vlan_entry->hd_tbl_status)
 279                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 280                         LIST_REMOVE(vlan_entry, next);
 281                         rte_free(vlan_entry);
 282                         break;
 283                 }
 284         }
 285 }
 286
 287 static void
 288 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 289                         bool writen_to_tbl)
 290 {
 291         struct hns3_user_vlan_table *vlan_entry;
 292         struct hns3_hw *hw = &hns->hw;
 293         struct hns3_pf *pf = &hns->pf;
 294
 295         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 296                 if (vlan_entry->vlan_id == vlan_id)
 297                         return;
 298         }
 299
 300         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 301         if (vlan_entry == NULL) {
 302                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 303                 return;
 304         }
 305
 306         vlan_entry->hd_tbl_status = writen_to_tbl;
 307         vlan_entry->vlan_id = vlan_id;
 308
 309         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 310 }
 311
 312 static int
 313 hns3_restore_vlan_table(struct hns3_adapter *hns)
 314 {
 315         struct hns3_user_vlan_table *vlan_entry;
 316         struct hns3_pf *pf = &hns->pf;
 317         uint16_t vlan_id;
 318         int ret = 0;
 319
 320         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 321                 return hns3_vlan_pvid_configure(hns,
 322                                                 pf->port_base_vlan_cfg.pvid, 1);
 323
 324         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 325                 if (vlan_entry->hd_tbl_status) {
 326                         vlan_id = vlan_entry->vlan_id;
 327                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 328                         if (ret)
 329                                 break;
 330                 }
 331         }
 332
 333         return ret;
 334 }
 335
 336 static int
 337 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 338 {
 339         struct hns3_pf *pf = &hns->pf;
 340         bool writen_to_tbl = false;
 341         int ret = 0;
 342
 343         /*
 344          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 345          * for normal packet, deleting vlan id 0 is not allowed.
 346          */
 347         if (on == 0 && vlan_id == 0)
 348                 return 0;
 349
 350         /*
 351          * When port base vlan enabled, we use port base vlan as the vlan
 352          * filter condition. In this case, we don't update vlan filter table
 353          * when user add new vlan or remove exist vlan, just update the
 354          * vlan list. The vlan id in vlan list will be writen in vlan filter
 355          * table until port base vlan disabled
 356          */
 357         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 358                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 359                 writen_to_tbl = true;
 360         }
 361
 362         if (ret == 0 && vlan_id) {
 363                 if (on)
 364                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 365                 else
 366                         hns3_rm_dev_vlan_table(hns, vlan_id);
 367         }
 368         return ret;
 369 }
 370
 371 static int
 372 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 373 {
 374         struct hns3_adapter *hns = dev->data->dev_private;
 375         struct hns3_hw *hw = &hns->hw;
 376         int ret;
 377
 378         rte_spinlock_lock(&hw->lock);
 379         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 380         rte_spinlock_unlock(&hw->lock);
 381         return ret;
 382 }
 383
 384 static int
 385 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 386                          uint16_t tpid)
 387 {
 388         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 389         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 390         struct hns3_hw *hw = &hns->hw;
 391         struct hns3_cmd_desc desc;
 392         int ret;
 393
 394         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 395              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 396                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 397                 return -EINVAL;
 398         }
 399
 400         if (tpid != RTE_ETHER_TYPE_VLAN) {
 401                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 402                 return -EINVAL;
 403         }
 404
 405         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 406         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 407
 408         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 409                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 412                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 413                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 414                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 415                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 416         }
 417
 418         ret = hns3_cmd_send(hw, &desc, 1);
 419         if (ret) {
 420                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 421                          ret);
 422                 return ret;
 423         }
 424
 425         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 426
 427         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 428         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 429         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 430
 431         ret = hns3_cmd_send(hw, &desc, 1);
 432         if (ret)
 433                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 434                          ret);
 435         return ret;
 436 }
 437
 438 static int
 439 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 440                    uint16_t tpid)
 441 {
 442         struct hns3_adapter *hns = dev->data->dev_private;
 443         struct hns3_hw *hw = &hns->hw;
 444         int ret;
 445
 446         rte_spinlock_lock(&hw->lock);
 447         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 448         rte_spinlock_unlock(&hw->lock);
 449         return ret;
 450 }
 451
 452 static int
 453 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 454                              struct hns3_rx_vtag_cfg *vcfg)
 455 {
 456         struct hns3_vport_vtag_rx_cfg_cmd *req;
 457         struct hns3_hw *hw = &hns->hw;
 458         struct hns3_cmd_desc desc;
 459         uint16_t vport_id;
 460         uint8_t bitmap;
 461         int ret;
 462
 463         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 464
 465         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 466         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 467                      vcfg->strip_tag1_en ? 1 : 0);
 468         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 469                      vcfg->strip_tag2_en ? 1 : 0);
 470         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 471                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 472         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 473                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 474
 475         /*
 476          * In current version VF is not supported when PF is driven by DPDK
 477          * driver, just need to configure parameters for PF vport.
 478          */
 479         vport_id = HNS3_PF_FUNC_ID;
 480         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 481         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 482         req->vf_bitmap[req->vf_offset] = bitmap;
 483
 484         ret = hns3_cmd_send(hw, &desc, 1);
 485         if (ret)
 486                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 487         return ret;
 488 }
 489
 490 static void
 491 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 492                            struct hns3_rx_vtag_cfg *vcfg)
 493 {
 494         struct hns3_pf *pf = &hns->pf;
 495         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 496 }
 497
 498 static void
 499 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 500                            struct hns3_tx_vtag_cfg *vcfg)
 501 {
 502         struct hns3_pf *pf = &hns->pf;
 503         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 504 }
 505
 506 static int
 507 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 508 {
 509         struct hns3_rx_vtag_cfg rxvlan_cfg;
 510         struct hns3_pf *pf = &hns->pf;
 511         struct hns3_hw *hw = &hns->hw;
 512         int ret;
 513
 514         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 515                 rxvlan_cfg.strip_tag1_en = false;
 516                 rxvlan_cfg.strip_tag2_en = enable;
 517         } else {
 518                 rxvlan_cfg.strip_tag1_en = enable;
 519                 rxvlan_cfg.strip_tag2_en = true;
 520         }
 521
 522         rxvlan_cfg.vlan1_vlan_prionly = false;
 523         rxvlan_cfg.vlan2_vlan_prionly = false;
 524         rxvlan_cfg.rx_vlan_offload_en = enable;
 525
 526         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 527         if (ret) {
 528                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 529                 return ret;
 530         }
 531
 532         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 533
 534         return ret;
 535 }
 536
 537 static int
 538 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 539                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 540 {
 541         struct hns3_vlan_filter_ctrl_cmd *req;
 542         struct hns3_cmd_desc desc;
 543         int ret;
 544
 545         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 546
 547         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 548         req->vlan_type = vlan_type;
 549         req->vlan_fe = filter_en ? fe_type : 0;
 550         req->vf_id = vf_id;
 551
 552         ret = hns3_cmd_send(hw, &desc, 1);
 553         if (ret)
 554                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 555
 556         return ret;
 557 }
 558
 559 static int
 560 hns3_vlan_filter_init(struct hns3_adapter *hns)
 561 {
 562         struct hns3_hw *hw = &hns->hw;
 563         int ret;
 564
 565         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 566                                         HNS3_FILTER_FE_EGRESS, false,
 567                                         HNS3_PF_FUNC_ID);
 568         if (ret) {
 569                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 570                 return ret;
 571         }
 572
 573         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 574                                         HNS3_FILTER_FE_INGRESS, false,
 575                                         HNS3_PF_FUNC_ID);
 576         if (ret)
 577                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 578
 579         return ret;
 580 }
 581
 582 static int
 583 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 584 {
 585         struct hns3_hw *hw = &hns->hw;
 586         int ret;
 587
 588         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 589                                         HNS3_FILTER_FE_INGRESS, enable,
 590                                         HNS3_PF_FUNC_ID);
 591         if (ret)
 592                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 593                          enable ? "enable" : "disable", ret);
 594
 595         return ret;
 596 }
 597
 598 static int
 599 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 600 {
 601         struct hns3_adapter *hns = dev->data->dev_private;
 602         struct hns3_hw *hw = &hns->hw;
 603         struct rte_eth_rxmode *rxmode;
 604         unsigned int tmp_mask;
 605         bool enable;
 606         int ret = 0;
 607
 608         rte_spinlock_lock(&hw->lock);
 609         rxmode = &dev->data->dev_conf.rxmode;
 610         tmp_mask = (unsigned int)mask;
 611         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 612                 /* ignore vlan filter configuration during promiscuous mode */
 613                 if (!dev->data->promiscuous) {
 614                         /* Enable or disable VLAN filter */
 615                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 616                                  true : false;
 617
 618                         ret = hns3_enable_vlan_filter(hns, enable);
 619                         if (ret) {
 620                                 rte_spinlock_unlock(&hw->lock);
 621                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 622                                          enable ? "enable" : "disable", ret);
 623                                 return ret;
 624                         }
 625                 }
 626         }
 627
 628         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 629                 /* Enable or disable VLAN stripping */
 630                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 631                     true : false;
 632
 633                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 634                 if (ret) {
 635                         rte_spinlock_unlock(&hw->lock);
 636                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 637                                  enable ? "enable" : "disable", ret);
 638                         return ret;
 639                 }
 640         }
 641
 642         rte_spinlock_unlock(&hw->lock);
 643
 644         return ret;
 645 }
 646
 647 static int
 648 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 649                              struct hns3_tx_vtag_cfg *vcfg)
 650 {
 651         struct hns3_vport_vtag_tx_cfg_cmd *req;
 652         struct hns3_cmd_desc desc;
 653         struct hns3_hw *hw = &hns->hw;
 654         uint16_t vport_id;
 655         uint8_t bitmap;
 656         int ret;
 657
 658         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 659
 660         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 661         req->def_vlan_tag1 = vcfg->default_tag1;
 662         req->def_vlan_tag2 = vcfg->default_tag2;
 663         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 664                      vcfg->accept_tag1 ? 1 : 0);
 665         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 666                      vcfg->accept_untag1 ? 1 : 0);
 667         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 668                      vcfg->accept_tag2 ? 1 : 0);
 669         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 670                      vcfg->accept_untag2 ? 1 : 0);
 671         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 672                      vcfg->insert_tag1_en ? 1 : 0);
 673         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 674                      vcfg->insert_tag2_en ? 1 : 0);
 675         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 676
 677         /*
 678          * In current version VF is not supported when PF is driven by DPDK
 679          * driver, just need to configure parameters for PF vport.
 680          */
 681         vport_id = HNS3_PF_FUNC_ID;
 682         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 683         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 684         req->vf_bitmap[req->vf_offset] = bitmap;
 685
 686         ret = hns3_cmd_send(hw, &desc, 1);
 687         if (ret)
 688                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 695                      uint16_t pvid)
 696 {
 697         struct hns3_hw *hw = &hns->hw;
 698         struct hns3_tx_vtag_cfg txvlan_cfg;
 699         int ret;
 700
 701         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 702                 txvlan_cfg.accept_tag1 = true;
 703                 txvlan_cfg.insert_tag1_en = false;
 704                 txvlan_cfg.default_tag1 = 0;
 705         } else {
 706                 txvlan_cfg.accept_tag1 = false;
 707                 txvlan_cfg.insert_tag1_en = true;
 708                 txvlan_cfg.default_tag1 = pvid;
 709         }
 710
 711         txvlan_cfg.accept_untag1 = true;
 712         txvlan_cfg.accept_tag2 = true;
 713         txvlan_cfg.accept_untag2 = true;
 714         txvlan_cfg.insert_tag2_en = false;
 715         txvlan_cfg.default_tag2 = 0;
 716
 717         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 718         if (ret) {
 719                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 720                          ret);
 721                 return ret;
 722         }
 723
 724         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 725         return ret;
 726 }
 727
 728 static void
 729 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 730 {
 731         struct hns3_pf *pf = &hns->pf;
 732
 733         pf->port_base_vlan_cfg.state = on ?
 734             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 735
 736         pf->port_base_vlan_cfg.pvid = pvid;
 737 }
 738
 739 static void
 740 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 741 {
 742         struct hns3_user_vlan_table *vlan_entry;
 743         struct hns3_pf *pf = &hns->pf;
 744
 745         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 746                 if (vlan_entry->hd_tbl_status)
 747                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 748
 749                 vlan_entry->hd_tbl_status = false;
 750         }
 751
 752         if (is_del_list) {
 753                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 754                 while (vlan_entry) {
 755                         LIST_REMOVE(vlan_entry, next);
 756                         rte_free(vlan_entry);
 757                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 758                 }
 759         }
 760 }
 761
 762 static void
 763 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 764 {
 765         struct hns3_user_vlan_table *vlan_entry;
 766         struct hns3_pf *pf = &hns->pf;
 767
 768         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 769                 if (!vlan_entry->hd_tbl_status)
 770                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 771
 772                 vlan_entry->hd_tbl_status = true;
 773         }
 774 }
 775
 776 static void
 777 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 778 {
 779         struct hns3_hw *hw = &hns->hw;
 780         struct hns3_pf *pf = &hns->pf;
 781         int ret;
 782
 783         hns3_rm_all_vlan_table(hns, true);
 784         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 785                 ret = hns3_set_port_vlan_filter(hns,
 786                                                 pf->port_base_vlan_cfg.pvid, 0);
 787                 if (ret) {
 788                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 789                                  ret);
 790                         return;
 791                 }
 792         }
 793 }
 794
 795 static int
 796 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 797                                 uint16_t port_base_vlan_state,
 798                                 uint16_t new_pvid, uint16_t old_pvid)
 799 {
 800         struct hns3_pf *pf = &hns->pf;
 801         struct hns3_hw *hw = &hns->hw;
 802         int ret = 0;
 803
 804         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 805                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 806                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 807                         if (ret) {
 808                                 hns3_err(hw,
 809                                          "Failed to clear clear old pvid filter, ret =%d",
 810                                          ret);
 811                                 return ret;
 812                         }
 813                 }
 814
 815                 hns3_rm_all_vlan_table(hns, false);
 816                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 817         }
 818
 819         if (new_pvid != 0) {
 820                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 821                 if (ret) {
 822                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 823                                  ret);
 824                         return ret;
 825                 }
 826         }
 827
 828         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 829                 hns3_add_all_vlan_table(hns);
 830
 831         return ret;
 832 }
 833
 834 static int
 835 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 836 {
 837         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 838         struct hns3_hw *hw = &hns->hw;
 839         bool rx_strip_en;
 840         int ret;
 841
 842         rx_strip_en = on ? true : false;
 843         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 844         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 845         rx_vlan_cfg.vlan1_vlan_prionly = false;
 846         rx_vlan_cfg.vlan2_vlan_prionly = false;
 847         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 848
 849         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 850         if (ret) {
 851                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 852                 return ret;
 853         }
 854
 855         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 856         return ret;
 857 }
 858
 859 static int
 860 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 861 {
 862         struct hns3_pf *pf = &hns->pf;
 863         struct hns3_hw *hw = &hns->hw;
 864         uint16_t port_base_vlan_state;
 865         uint16_t old_pvid;
 866         int ret;
 867
 868         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 869                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 870                         hns3_warn(hw, "Invalid operation! As current pvid set "
 871                                   "is %u, disable pvid %u is invalid",
 872                                   pf->port_base_vlan_cfg.pvid, pvid);
 873                 return 0;
 874         }
 875
 876         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 877                                     HNS3_PORT_BASE_VLAN_DISABLE;
 878         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 879         if (ret) {
 880                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 881                 return ret;
 882         }
 883
 884         ret = hns3_en_rx_strip_all(hns, on);
 885         if (ret) {
 886                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 887                 return ret;
 888         }
 889
 890         if (pvid == HNS3_INVLID_PVID)
 891                 goto out;
 892         old_pvid = pf->port_base_vlan_cfg.pvid;
 893         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 894                                               old_pvid);
 895         if (ret) {
 896                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 897                          ret);
 898                 return ret;
 899         }
 900
 901 out:
 902         hns3_store_port_base_vlan_info(hns, pvid, on);
 903         return ret;
 904 }
 905
 906 static int
 907 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 908 {
 909         struct hns3_adapter *hns = dev->data->dev_private;
 910         struct hns3_hw *hw = &hns->hw;
 911         int ret;
 912
 913         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 914                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 915                          RTE_ETHER_MAX_VLAN_ID);
 916                 return -EINVAL;
 917         }
 918
 919         rte_spinlock_lock(&hw->lock);
 920         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 921         rte_spinlock_unlock(&hw->lock);
 922         return ret;
 923 }
 924
 925 static void
 926 init_port_base_vlan_info(struct hns3_hw *hw)
 927 {
 928         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 929         struct hns3_pf *pf = &hns->pf;
 930
 931         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 932         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 933 }
 934
 935 static int
 936 hns3_default_vlan_config(struct hns3_adapter *hns)
 937 {
 938         struct hns3_hw *hw = &hns->hw;
 939         int ret;
 940
 941         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 942         if (ret)
 943                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 944         return ret;
 945 }
 946
 947 static int
 948 hns3_init_vlan_config(struct hns3_adapter *hns)
 949 {
 950         struct hns3_hw *hw = &hns->hw;
 951         int ret;
 952
 953         /*
 954          * This function can be called in the initialization and reset process,
 955          * when in reset process, it means that hardware had been reseted
 956          * successfully and we need to restore the hardware configuration to
 957          * ensure that the hardware configuration remains unchanged before and
 958          * after reset.
 959          */
 960         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 961                 init_port_base_vlan_info(hw);
 962
 963         ret = hns3_vlan_filter_init(hns);
 964         if (ret) {
 965                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 966                 return ret;
 967         }
 968
 969         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 970                                        RTE_ETHER_TYPE_VLAN);
 971         if (ret) {
 972                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 973                 return ret;
 974         }
 975
 976         /*
 977          * When in the reinit dev stage of the reset process, the following
 978          * vlan-related configurations may differ from those at initialization,
 979          * we will restore configurations to hardware in hns3_restore_vlan_table
 980          * and hns3_restore_vlan_conf later.
 981          */
 982         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 983                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 984                 if (ret) {
 985                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 986                         return ret;
 987                 }
 988
 989                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 990                 if (ret) {
 991                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 992                                  ret);
 993                         return ret;
 994                 }
 995         }
 996
 997         return hns3_default_vlan_config(hns);
 998 }
 999
1000 static int
1001 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1002 {
1003         struct hns3_pf *pf = &hns->pf;
1004         struct hns3_hw *hw = &hns->hw;
1005         uint64_t offloads;
1006         bool enable;
1007         int ret;
1008
1009         if (!hw->data->promiscuous) {
1010                 /* restore vlan filter states */
1011                 offloads = hw->data->dev_conf.rxmode.offloads;
1012                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1013                 ret = hns3_enable_vlan_filter(hns, enable);
1014                 if (ret) {
1015                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1016                                  "ret = %d", ret);
1017                         return ret;
1018                 }
1019         }
1020
1021         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1022         if (ret) {
1023                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1024                 return ret;
1025         }
1026
1027         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1028         if (ret)
1029                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1030
1031         return ret;
1032 }
1033
1034 static int
1035 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1036 {
1037         struct hns3_adapter *hns = dev->data->dev_private;
1038         struct rte_eth_dev_data *data = dev->data;
1039         struct rte_eth_txmode *txmode;
1040         struct hns3_hw *hw = &hns->hw;
1041         int mask;
1042         int ret;
1043
1044         txmode = &data->dev_conf.txmode;
1045         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1046                 hns3_warn(hw,
1047                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1048                           "configuration is not supported! Ignore these two "
1049                           "parameters: hw_vlan_reject_tagged(%d), "
1050                           "hw_vlan_reject_untagged(%d)",
1051                           txmode->hw_vlan_reject_tagged,
1052                           txmode->hw_vlan_reject_untagged);
1053
1054         /* Apply vlan offload setting */
1055         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1056         ret = hns3_vlan_offload_set(dev, mask);
1057         if (ret) {
1058                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1059                          ret);
1060                 return ret;
1061         }
1062
1063         /*
1064          * If pvid config is not set in rte_eth_conf, driver needn't to set
1065          * VLAN pvid related configuration to hardware.
1066          */
1067         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1068                 return 0;
1069
1070         /* Apply pvid setting */
1071         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1072                                  txmode->hw_vlan_insert_pvid);
1073         if (ret)
1074                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1075                          txmode->pvid, ret);
1076
1077         return ret;
1078 }
1079
1080 static int
1081 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1082                 unsigned int tso_mss_max)
1083 {
1084         struct hns3_cfg_tso_status_cmd *req;
1085         struct hns3_cmd_desc desc;
1086         uint16_t tso_mss;
1087
1088         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1089
1090         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1091
1092         tso_mss = 0;
1093         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1094                        tso_mss_min);
1095         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1096
1097         tso_mss = 0;
1098         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1099                        tso_mss_max);
1100         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1101
1102         return hns3_cmd_send(hw, &desc, 1);
1103 }
1104
1105 int
1106 hns3_config_gro(struct hns3_hw *hw, bool en)
1107 {
1108         struct hns3_cfg_gro_status_cmd *req;
1109         struct hns3_cmd_desc desc;
1110         int ret;
1111
1112         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1113         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1114
1115         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1116
1117         ret = hns3_cmd_send(hw, &desc, 1);
1118         if (ret)
1119                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1120
1121         return ret;
1122 }
1123
1124 static int
1125 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1126                    uint16_t *allocated_size, bool is_alloc)
1127 {
1128         struct hns3_umv_spc_alc_cmd *req;
1129         struct hns3_cmd_desc desc;
1130         int ret;
1131
1132         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1133         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1134         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1135         req->space_size = rte_cpu_to_le_32(space_size);
1136
1137         ret = hns3_cmd_send(hw, &desc, 1);
1138         if (ret) {
1139                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1140                              is_alloc ? "allocate" : "free", ret);
1141                 return ret;
1142         }
1143
1144         if (is_alloc && allocated_size)
1145                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1146
1147         return 0;
1148 }
1149
1150 static int
1151 hns3_init_umv_space(struct hns3_hw *hw)
1152 {
1153         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1154         struct hns3_pf *pf = &hns->pf;
1155         uint16_t allocated_size = 0;
1156         int ret;
1157
1158         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1159                                  true);
1160         if (ret)
1161                 return ret;
1162
1163         if (allocated_size < pf->wanted_umv_size)
1164                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1165                              pf->wanted_umv_size, allocated_size);
1166
1167         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1168                                                 pf->wanted_umv_size;
1169         pf->used_umv_size = 0;
1170         return 0;
1171 }
1172
1173 static int
1174 hns3_uninit_umv_space(struct hns3_hw *hw)
1175 {
1176         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1177         struct hns3_pf *pf = &hns->pf;
1178         int ret;
1179
1180         if (pf->max_umv_size == 0)
1181                 return 0;
1182
1183         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1184         if (ret)
1185                 return ret;
1186
1187         pf->max_umv_size = 0;
1188
1189         return 0;
1190 }
1191
1192 static bool
1193 hns3_is_umv_space_full(struct hns3_hw *hw)
1194 {
1195         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1196         struct hns3_pf *pf = &hns->pf;
1197         bool is_full;
1198
1199         is_full = (pf->used_umv_size >= pf->max_umv_size);
1200
1201         return is_full;
1202 }
1203
1204 static void
1205 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1206 {
1207         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1208         struct hns3_pf *pf = &hns->pf;
1209
1210         if (is_free) {
1211                 if (pf->used_umv_size > 0)
1212                         pf->used_umv_size--;
1213         } else
1214                 pf->used_umv_size++;
1215 }
1216
1217 static void
1218 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1219                       const uint8_t *addr, bool is_mc)
1220 {
1221         const unsigned char *mac_addr = addr;
1222         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1223                             ((uint32_t)mac_addr[2] << 16) |
1224                             ((uint32_t)mac_addr[1] << 8) |
1225                             (uint32_t)mac_addr[0];
1226         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1227
1228         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1229         if (is_mc) {
1230                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1231                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1232                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1233         }
1234
1235         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1236         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1237 }
1238
1239 static int
1240 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1241                              uint8_t resp_code,
1242                              enum hns3_mac_vlan_tbl_opcode op)
1243 {
1244         if (cmdq_resp) {
1245                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1246                          cmdq_resp);
1247                 return -EIO;
1248         }
1249
1250         if (op == HNS3_MAC_VLAN_ADD) {
1251                 if (resp_code == 0 || resp_code == 1) {
1252                         return 0;
1253                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1254                         hns3_err(hw, "add mac addr failed for uc_overflow");
1255                         return -ENOSPC;
1256                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1257                         hns3_err(hw, "add mac addr failed for mc_overflow");
1258                         return -ENOSPC;
1259                 }
1260
1261                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1262                          resp_code);
1263                 return -EIO;
1264         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1265                 if (resp_code == 0) {
1266                         return 0;
1267                 } else if (resp_code == 1) {
1268                         hns3_dbg(hw, "remove mac addr failed for miss");
1269                         return -ENOENT;
1270                 }
1271
1272                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1273                          resp_code);
1274                 return -EIO;
1275         } else if (op == HNS3_MAC_VLAN_LKUP) {
1276                 if (resp_code == 0) {
1277                         return 0;
1278                 } else if (resp_code == 1) {
1279                         hns3_dbg(hw, "lookup mac addr failed for miss");
1280                         return -ENOENT;
1281                 }
1282
1283                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1284                          resp_code);
1285                 return -EIO;
1286         }
1287
1288         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1289                  op);
1290
1291         return -EINVAL;
1292 }
1293
1294 static int
1295 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1296                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1297                          struct hns3_cmd_desc *desc, bool is_mc)
1298 {
1299         uint8_t resp_code;
1300         uint16_t retval;
1301         int ret;
1302
1303         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1304         if (is_mc) {
1305                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1306                 memcpy(desc[0].data, req,
1307                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1308                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1309                                           true);
1310                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1311                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1312                                           true);
1313                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1314         } else {
1315                 memcpy(desc[0].data, req,
1316                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1317                 ret = hns3_cmd_send(hw, desc, 1);
1318         }
1319         if (ret) {
1320                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1321                          ret);
1322                 return ret;
1323         }
1324         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1325         retval = rte_le_to_cpu_16(desc[0].retval);
1326
1327         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1328                                             HNS3_MAC_VLAN_LKUP);
1329 }
1330
1331 static int
1332 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1333                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1334                       struct hns3_cmd_desc *mc_desc)
1335 {
1336         uint8_t resp_code;
1337         uint16_t retval;
1338         int cfg_status;
1339         int ret;
1340
1341         if (mc_desc == NULL) {
1342                 struct hns3_cmd_desc desc;
1343
1344                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1345                 memcpy(desc.data, req,
1346                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1347                 ret = hns3_cmd_send(hw, &desc, 1);
1348                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1349                 retval = rte_le_to_cpu_16(desc.retval);
1350
1351                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1352                                                           HNS3_MAC_VLAN_ADD);
1353         } else {
1354                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1355                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1356                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1357                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1358                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1359                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1360                 memcpy(mc_desc[0].data, req,
1361                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1362                 mc_desc[0].retval = 0;
1363                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1364                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1365                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1366
1367                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1368                                                           HNS3_MAC_VLAN_ADD);
1369         }
1370
1371         if (ret) {
1372                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1373                 return ret;
1374         }
1375
1376         return cfg_status;
1377 }
1378
1379 static int
1380 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1381                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1382 {
1383         struct hns3_cmd_desc desc;
1384         uint8_t resp_code;
1385         uint16_t retval;
1386         int ret;
1387
1388         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1389
1390         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1391
1392         ret = hns3_cmd_send(hw, &desc, 1);
1393         if (ret) {
1394                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1395                 return ret;
1396         }
1397         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1398         retval = rte_le_to_cpu_16(desc.retval);
1399
1400         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1401                                             HNS3_MAC_VLAN_REMOVE);
1402 }
1403
1404 static int
1405 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1406 {
1407         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1408         struct hns3_mac_vlan_tbl_entry_cmd req;
1409         struct hns3_pf *pf = &hns->pf;
1410         struct hns3_cmd_desc desc;
1411         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1412         uint16_t egress_port = 0;
1413         uint8_t vf_id;
1414         int ret;
1415
1416         /* check if mac addr is valid */
1417         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1418                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1419                                       mac_addr);
1420                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1421                          mac_str);
1422                 return -EINVAL;
1423         }
1424
1425         memset(&req, 0, sizeof(req));
1426
1427         /*
1428          * In current version VF is not supported when PF is driven by DPDK
1429          * driver, just need to configure parameters for PF vport.
1430          */
1431         vf_id = HNS3_PF_FUNC_ID;
1432         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1433                        HNS3_MAC_EPORT_VFID_S, vf_id);
1434
1435         req.egress_port = rte_cpu_to_le_16(egress_port);
1436
1437         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1438
1439         /*
1440          * Lookup the mac address in the mac_vlan table, and add
1441          * it if the entry is inexistent. Repeated unicast entry
1442          * is not allowed in the mac vlan table.
1443          */
1444         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1445         if (ret == -ENOENT) {
1446                 if (!hns3_is_umv_space_full(hw)) {
1447                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1448                         if (!ret)
1449                                 hns3_update_umv_space(hw, false);
1450                         return ret;
1451                 }
1452
1453                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1454
1455                 return -ENOSPC;
1456         }
1457
1458         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1459
1460         /* check if we just hit the duplicate */
1461         if (ret == 0) {
1462                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1463                 return 0;
1464         }
1465
1466         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1467                  mac_str);
1468
1469         return ret;
1470 }
1471
1472 static int
1473 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1474 {
1475         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1476         struct rte_ether_addr *addr;
1477         int ret;
1478         int i;
1479
1480         for (i = 0; i < hw->mc_addrs_num; i++) {
1481                 addr = &hw->mc_addrs[i];
1482                 /* Check if there are duplicate addresses */
1483                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1484                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1485                                               addr);
1486                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1487                                  "(%s) is added by the set_mc_mac_addr_list "
1488                                  "API", mac_str);
1489                         return -EINVAL;
1490                 }
1491         }
1492
1493         ret = hns3_add_mc_addr(hw, mac_addr);
1494         if (ret) {
1495                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1496                                       mac_addr);
1497                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1498                          mac_str, ret);
1499         }
1500         return ret;
1501 }
1502
1503 static int
1504 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1505 {
1506         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1507         int ret;
1508
1509         ret = hns3_remove_mc_addr(hw, mac_addr);
1510         if (ret) {
1511                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1512                                       mac_addr);
1513                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1514                          mac_str, ret);
1515         }
1516         return ret;
1517 }
1518
1519 static int
1520 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1521                   uint32_t idx, __rte_unused uint32_t pool)
1522 {
1523         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1525         int ret;
1526
1527         rte_spinlock_lock(&hw->lock);
1528
1529         /*
1530          * In hns3 network engine adding UC and MC mac address with different
1531          * commands with firmware. We need to determine whether the input
1532          * address is a UC or a MC address to call different commands.
1533          * By the way, it is recommended calling the API function named
1534          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1535          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1536          * may affect the specifications of UC mac addresses.
1537          */
1538         if (rte_is_multicast_ether_addr(mac_addr))
1539                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1540         else
1541                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1542
1543         if (ret) {
1544                 rte_spinlock_unlock(&hw->lock);
1545                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1546                                       mac_addr);
1547                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1548                          ret);
1549                 return ret;
1550         }
1551
1552         if (idx == 0)
1553                 hw->mac.default_addr_setted = true;
1554         rte_spinlock_unlock(&hw->lock);
1555
1556         return ret;
1557 }
1558
1559 static int
1560 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1561 {
1562         struct hns3_mac_vlan_tbl_entry_cmd req;
1563         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1564         int ret;
1565
1566         /* check if mac addr is valid */
1567         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1568                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1569                                       mac_addr);
1570                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1571                          mac_str);
1572                 return -EINVAL;
1573         }
1574
1575         memset(&req, 0, sizeof(req));
1576         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1577         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1578         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1579         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1580                 return 0;
1581         else if (ret == 0)
1582                 hns3_update_umv_space(hw, true);
1583
1584         return ret;
1585 }
1586
1587 static void
1588 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1589 {
1590         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1591         /* index will be checked by upper level rte interface */
1592         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1593         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1594         int ret;
1595
1596         rte_spinlock_lock(&hw->lock);
1597
1598         if (rte_is_multicast_ether_addr(mac_addr))
1599                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1600         else
1601                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1602         rte_spinlock_unlock(&hw->lock);
1603         if (ret) {
1604                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1605                                       mac_addr);
1606                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1607                          ret);
1608         }
1609 }
1610
1611 static int
1612 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1613                           struct rte_ether_addr *mac_addr)
1614 {
1615         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1616         struct rte_ether_addr *oaddr;
1617         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1618         bool default_addr_setted;
1619         bool rm_succes = false;
1620         int ret, ret_val;
1621
1622         /*
1623          * It has been guaranteed that input parameter named mac_addr is valid
1624          * address in the rte layer of DPDK framework.
1625          */
1626         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1627         default_addr_setted = hw->mac.default_addr_setted;
1628         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1629                 return 0;
1630
1631         rte_spinlock_lock(&hw->lock);
1632         if (default_addr_setted) {
1633                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1634                 if (ret) {
1635                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1636                                               oaddr);
1637                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1638                                   mac_str, ret);
1639                         rm_succes = false;
1640                 } else
1641                         rm_succes = true;
1642         }
1643
1644         ret = hns3_add_uc_addr_common(hw, mac_addr);
1645         if (ret) {
1646                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1647                                       mac_addr);
1648                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1649                 goto err_add_uc_addr;
1650         }
1651
1652         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1653         if (ret) {
1654                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1655                 goto err_pause_addr_cfg;
1656         }
1657
1658         rte_ether_addr_copy(mac_addr,
1659                             (struct rte_ether_addr *)hw->mac.mac_addr);
1660         hw->mac.default_addr_setted = true;
1661         rte_spinlock_unlock(&hw->lock);
1662
1663         return 0;
1664
1665 err_pause_addr_cfg:
1666         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1667         if (ret_val) {
1668                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1669                                       mac_addr);
1670                 hns3_warn(hw,
1671                           "Failed to roll back to del setted mac addr(%s): %d",
1672                           mac_str, ret_val);
1673         }
1674
1675 err_add_uc_addr:
1676         if (rm_succes) {
1677                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1678                 if (ret_val) {
1679                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1680                                               oaddr);
1681                         hns3_warn(hw,
1682                                   "Failed to restore old uc mac addr(%s): %d",
1683                                   mac_str, ret_val);
1684                         hw->mac.default_addr_setted = false;
1685                 }
1686         }
1687         rte_spinlock_unlock(&hw->lock);
1688
1689         return ret;
1690 }
1691
1692 static int
1693 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1694 {
1695         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1696         struct hns3_hw *hw = &hns->hw;
1697         struct rte_ether_addr *addr;
1698         int err = 0;
1699         int ret;
1700         int i;
1701
1702         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1703                 addr = &hw->data->mac_addrs[i];
1704                 if (rte_is_zero_ether_addr(addr))
1705                         continue;
1706                 if (rte_is_multicast_ether_addr(addr))
1707                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1708                               hns3_add_mc_addr(hw, addr);
1709                 else
1710                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1711                               hns3_add_uc_addr_common(hw, addr);
1712
1713                 if (ret) {
1714                         err = ret;
1715                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1716                                               addr);
1717                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1718                                  "ret = %d.", del ? "remove" : "restore",
1719                                  mac_str, i, ret);
1720                 }
1721         }
1722         return err;
1723 }
1724
1725 static void
1726 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1727 {
1728 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1729         uint8_t word_num;
1730         uint8_t bit_num;
1731
1732         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1733                 word_num = vfid / 32;
1734                 bit_num = vfid % 32;
1735                 if (clr)
1736                         desc[1].data[word_num] &=
1737                             rte_cpu_to_le_32(~(1UL << bit_num));
1738                 else
1739                         desc[1].data[word_num] |=
1740                             rte_cpu_to_le_32(1UL << bit_num);
1741         } else {
1742                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1743                 bit_num = vfid % 32;
1744                 if (clr)
1745                         desc[2].data[word_num] &=
1746                             rte_cpu_to_le_32(~(1UL << bit_num));
1747                 else
1748                         desc[2].data[word_num] |=
1749                             rte_cpu_to_le_32(1UL << bit_num);
1750         }
1751 }
1752
1753 static int
1754 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1755 {
1756         struct hns3_mac_vlan_tbl_entry_cmd req;
1757         struct hns3_cmd_desc desc[3];
1758         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1759         uint8_t vf_id;
1760         int ret;
1761
1762         /* Check if mac addr is valid */
1763         if (!rte_is_multicast_ether_addr(mac_addr)) {
1764                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1765                                       mac_addr);
1766                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1767                          mac_str);
1768                 return -EINVAL;
1769         }
1770
1771         memset(&req, 0, sizeof(req));
1772         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1773         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1774         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1775         if (ret) {
1776                 /* This mac addr do not exist, add new entry for it */
1777                 memset(desc[0].data, 0, sizeof(desc[0].data));
1778                 memset(desc[1].data, 0, sizeof(desc[0].data));
1779                 memset(desc[2].data, 0, sizeof(desc[0].data));
1780         }
1781
1782         /*
1783          * In current version VF is not supported when PF is driven by DPDK
1784          * driver, just need to configure parameters for PF vport.
1785          */
1786         vf_id = HNS3_PF_FUNC_ID;
1787         hns3_update_desc_vfid(desc, vf_id, false);
1788         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1789         if (ret) {
1790                 if (ret == -ENOSPC)
1791                         hns3_err(hw, "mc mac vlan table is full");
1792                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1793                                       mac_addr);
1794                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1795         }
1796
1797         return ret;
1798 }
1799
1800 static int
1801 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1802 {
1803         struct hns3_mac_vlan_tbl_entry_cmd req;
1804         struct hns3_cmd_desc desc[3];
1805         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1806         uint8_t vf_id;
1807         int ret;
1808
1809         /* Check if mac addr is valid */
1810         if (!rte_is_multicast_ether_addr(mac_addr)) {
1811                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1812                                       mac_addr);
1813                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1814                          mac_str);
1815                 return -EINVAL;
1816         }
1817
1818         memset(&req, 0, sizeof(req));
1819         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1820         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1821         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1822         if (ret == 0) {
1823                 /*
1824                  * This mac addr exist, remove this handle's VFID for it.
1825                  * In current version VF is not supported when PF is driven by
1826                  * DPDK driver, just need to configure parameters for PF vport.
1827                  */
1828                 vf_id = HNS3_PF_FUNC_ID;
1829                 hns3_update_desc_vfid(desc, vf_id, true);
1830
1831                 /* All the vfid is zero, so need to delete this entry */
1832                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1833         } else if (ret == -ENOENT) {
1834                 /* This mac addr doesn't exist. */
1835                 return 0;
1836         }
1837
1838         if (ret) {
1839                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1840                                       mac_addr);
1841                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1842         }
1843
1844         return ret;
1845 }
1846
1847 static int
1848 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1849                            struct rte_ether_addr *mc_addr_set,
1850                            uint32_t nb_mc_addr)
1851 {
1852         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1853         struct rte_ether_addr *addr;
1854         uint32_t i;
1855         uint32_t j;
1856
1857         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1858                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1859                          "invalid. valid range: 0~%d",
1860                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1861                 return -EINVAL;
1862         }
1863
1864         /* Check if input mac addresses are valid */
1865         for (i = 0; i < nb_mc_addr; i++) {
1866                 addr = &mc_addr_set[i];
1867                 if (!rte_is_multicast_ether_addr(addr)) {
1868                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1869                                               addr);
1870                         hns3_err(hw,
1871                                  "failed to set mc mac addr, addr(%s) invalid.",
1872                                  mac_str);
1873                         return -EINVAL;
1874                 }
1875
1876                 /* Check if there are duplicate addresses */
1877                 for (j = i + 1; j < nb_mc_addr; j++) {
1878                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1879                                 rte_ether_format_addr(mac_str,
1880                                                       RTE_ETHER_ADDR_FMT_SIZE,
1881                                                       addr);
1882                                 hns3_err(hw, "failed to set mc mac addr, "
1883                                          "addrs invalid. two same addrs(%s).",
1884                                          mac_str);
1885                                 return -EINVAL;
1886                         }
1887                 }
1888
1889                 /*
1890                  * Check if there are duplicate addresses between mac_addrs
1891                  * and mc_addr_set
1892                  */
1893                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1894                         if (rte_is_same_ether_addr(addr,
1895                                                    &hw->data->mac_addrs[j])) {
1896                                 rte_ether_format_addr(mac_str,
1897                                                       RTE_ETHER_ADDR_FMT_SIZE,
1898                                                       addr);
1899                                 hns3_err(hw, "failed to set mc mac addr, "
1900                                          "addrs invalid. addrs(%s) has already "
1901                                          "configured in mac_addr add API",
1902                                          mac_str);
1903                                 return -EINVAL;
1904                         }
1905                 }
1906         }
1907
1908         return 0;
1909 }
1910
1911 static void
1912 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1913                            struct rte_ether_addr *mc_addr_set,
1914                            int mc_addr_num,
1915                            struct rte_ether_addr *reserved_addr_list,
1916                            int *reserved_addr_num,
1917                            struct rte_ether_addr *add_addr_list,
1918                            int *add_addr_num,
1919                            struct rte_ether_addr *rm_addr_list,
1920                            int *rm_addr_num)
1921 {
1922         struct rte_ether_addr *addr;
1923         int current_addr_num;
1924         int reserved_num = 0;
1925         int add_num = 0;
1926         int rm_num = 0;
1927         int num;
1928         int i;
1929         int j;
1930         bool same_addr;
1931
1932         /* Calculate the mc mac address list that should be removed */
1933         current_addr_num = hw->mc_addrs_num;
1934         for (i = 0; i < current_addr_num; i++) {
1935                 addr = &hw->mc_addrs[i];
1936                 same_addr = false;
1937                 for (j = 0; j < mc_addr_num; j++) {
1938                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1939                                 same_addr = true;
1940                                 break;
1941                         }
1942                 }
1943
1944                 if (!same_addr) {
1945                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1946                         rm_num++;
1947                 } else {
1948                         rte_ether_addr_copy(addr,
1949                                             &reserved_addr_list[reserved_num]);
1950                         reserved_num++;
1951                 }
1952         }
1953
1954         /* Calculate the mc mac address list that should be added */
1955         for (i = 0; i < mc_addr_num; i++) {
1956                 addr = &mc_addr_set[i];
1957                 same_addr = false;
1958                 for (j = 0; j < current_addr_num; j++) {
1959                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1960                                 same_addr = true;
1961                                 break;
1962                         }
1963                 }
1964
1965                 if (!same_addr) {
1966                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1967                         add_num++;
1968                 }
1969         }
1970
1971         /* Reorder the mc mac address list maintained by driver */
1972         for (i = 0; i < reserved_num; i++)
1973                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1974
1975         for (i = 0; i < rm_num; i++) {
1976                 num = reserved_num + i;
1977                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1978         }
1979
1980         *reserved_addr_num = reserved_num;
1981         *add_addr_num = add_num;
1982         *rm_addr_num = rm_num;
1983 }
1984
1985 static int
1986 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1987                           struct rte_ether_addr *mc_addr_set,
1988                           uint32_t nb_mc_addr)
1989 {
1990         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1992         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1993         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1994         struct rte_ether_addr *addr;
1995         int reserved_addr_num;
1996         int add_addr_num;
1997         int rm_addr_num;
1998         int mc_addr_num;
1999         int num;
2000         int ret;
2001         int i;
2002
2003         /* Check if input parameters are valid */
2004         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2005         if (ret)
2006                 return ret;
2007
2008         rte_spinlock_lock(&hw->lock);
2009
2010         /*
2011          * Calculate the mc mac address lists those should be removed and be
2012          * added, Reorder the mc mac address list maintained by driver.
2013          */
2014         mc_addr_num = (int)nb_mc_addr;
2015         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2016                                    reserved_addr_list, &reserved_addr_num,
2017                                    add_addr_list, &add_addr_num,
2018                                    rm_addr_list, &rm_addr_num);
2019
2020         /* Remove mc mac addresses */
2021         for (i = 0; i < rm_addr_num; i++) {
2022                 num = rm_addr_num - i - 1;
2023                 addr = &rm_addr_list[num];
2024                 ret = hns3_remove_mc_addr(hw, addr);
2025                 if (ret) {
2026                         rte_spinlock_unlock(&hw->lock);
2027                         return ret;
2028                 }
2029                 hw->mc_addrs_num--;
2030         }
2031
2032         /* Add mc mac addresses */
2033         for (i = 0; i < add_addr_num; i++) {
2034                 addr = &add_addr_list[i];
2035                 ret = hns3_add_mc_addr(hw, addr);
2036                 if (ret) {
2037                         rte_spinlock_unlock(&hw->lock);
2038                         return ret;
2039                 }
2040
2041                 num = reserved_addr_num + i;
2042                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2043                 hw->mc_addrs_num++;
2044         }
2045         rte_spinlock_unlock(&hw->lock);
2046
2047         return 0;
2048 }
2049
2050 static int
2051 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2052 {
2053         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2054         struct hns3_hw *hw = &hns->hw;
2055         struct rte_ether_addr *addr;
2056         int err = 0;
2057         int ret;
2058         int i;
2059
2060         for (i = 0; i < hw->mc_addrs_num; i++) {
2061                 addr = &hw->mc_addrs[i];
2062                 if (!rte_is_multicast_ether_addr(addr))
2063                         continue;
2064                 if (del)
2065                         ret = hns3_remove_mc_addr(hw, addr);
2066                 else
2067                         ret = hns3_add_mc_addr(hw, addr);
2068                 if (ret) {
2069                         err = ret;
2070                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2071                                               addr);
2072                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2073                                  del ? "Remove" : "Restore", mac_str, ret);
2074                 }
2075         }
2076         return err;
2077 }
2078
2079 static int
2080 hns3_check_mq_mode(struct rte_eth_dev *dev)
2081 {
2082         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2083         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2084         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2086         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2087         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2088         uint8_t num_tc;
2089         int max_tc = 0;
2090         int i;
2091
2092         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2093         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2094
2095         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2096                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2097                          "rx_mq_mode = %d", rx_mq_mode);
2098                 return -EINVAL;
2099         }
2100
2101         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2102             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2103                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2104                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2105                          rx_mq_mode, tx_mq_mode);
2106                 return -EINVAL;
2107         }
2108
2109         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2110                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2111                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2112                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2113                         return -EINVAL;
2114                 }
2115
2116                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2117                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2118                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2119                                  "nb_tcs(%d) != %d or %d in rx direction.",
2120                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2121                         return -EINVAL;
2122                 }
2123
2124                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2125                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2126                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2127                         return -EINVAL;
2128                 }
2129
2130                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2131                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2132                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2133                                          "is not equal to one in tx direction.",
2134                                          i, dcb_rx_conf->dcb_tc[i]);
2135                                 return -EINVAL;
2136                         }
2137                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2138                                 max_tc = dcb_rx_conf->dcb_tc[i];
2139                 }
2140
2141                 num_tc = max_tc + 1;
2142                 if (num_tc > dcb_rx_conf->nb_tcs) {
2143                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2144                                  num_tc, dcb_rx_conf->nb_tcs);
2145                         return -EINVAL;
2146                 }
2147         }
2148
2149         return 0;
2150 }
2151
2152 static int
2153 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2154 {
2155         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2156
2157         if (!hns3_dev_dcb_supported(hw)) {
2158                 hns3_err(hw, "this port does not support dcb configurations.");
2159                 return -EOPNOTSUPP;
2160         }
2161
2162         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2163                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2164                 return -EOPNOTSUPP;
2165         }
2166
2167         /* Check multiple queue mode */
2168         return hns3_check_mq_mode(dev);
2169 }
2170
2171 static int
2172 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2173                            enum hns3_ring_type queue_type, uint16_t queue_id)
2174 {
2175         struct hns3_cmd_desc desc;
2176         struct hns3_ctrl_vector_chain_cmd *req =
2177                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2178         enum hns3_cmd_status status;
2179         enum hns3_opcode_type op;
2180         uint16_t tqp_type_and_id = 0;
2181         const char *op_str;
2182         uint16_t type;
2183         uint16_t gl;
2184
2185         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2186         hns3_cmd_setup_basic_desc(&desc, op, false);
2187         req->int_vector_id = vector_id;
2188
2189         if (queue_type == HNS3_RING_TYPE_RX)
2190                 gl = HNS3_RING_GL_RX;
2191         else
2192                 gl = HNS3_RING_GL_TX;
2193
2194         type = queue_type;
2195
2196         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2197                        type);
2198         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2199         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2200                        gl);
2201         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2202         req->int_cause_num = 1;
2203         op_str = mmap ? "Map" : "Unmap";
2204         status = hns3_cmd_send(hw, &desc, 1);
2205         if (status) {
2206                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2207                          op_str, queue_id, req->int_vector_id, status);
2208                 return status;
2209         }
2210
2211         return 0;
2212 }
2213
2214 static int
2215 hns3_init_ring_with_vector(struct hns3_hw *hw)
2216 {
2217         uint8_t vec;
2218         int ret;
2219         int i;
2220
2221         /*
2222          * In hns3 network engine, vector 0 is always the misc interrupt of this
2223          * function, vector 1~N can be used respectively for the queues of the
2224          * function. Tx and Rx queues with the same number share the interrupt
2225          * vector. In the initialization clearing the all hardware mapping
2226          * relationship configurations between queues and interrupt vectors is
2227          * needed, so some error caused by the residual configurations, such as
2228          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2229          * constraints in hns3 hardware engine, we have to implement clearing
2230          * the mapping relationship configurations by binding all queues to the
2231          * last interrupt vector and reserving the last interrupt vector. This
2232          * method results in a decrease of the maximum queues when upper
2233          * applications call the rte_eth_dev_configure API function to enable
2234          * Rx interrupt.
2235          */
2236         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2237         /* vec - 1: the last interrupt is reserved */
2238         hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;
2239         for (i = 0; i < hw->intr_tqps_num; i++) {
2240                 /*
2241                  * Set gap limiter and rate limiter configuration of queue's
2242                  * interrupt.
2243                  */
2244                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2245                                        HNS3_TQP_INTR_GL_DEFAULT);
2246                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2247                                        HNS3_TQP_INTR_GL_DEFAULT);
2248                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2249
2250                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2251                                                  HNS3_RING_TYPE_TX, i);
2252                 if (ret) {
2253                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2254                                           "vector: %d, ret=%d", i, vec, ret);
2255                         return ret;
2256                 }
2257
2258                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2259                                                  HNS3_RING_TYPE_RX, i);
2260                 if (ret) {
2261                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2262                                           "vector: %d, ret=%d", i, vec, ret);
2263                         return ret;
2264                 }
2265         }
2266
2267         return 0;
2268 }
2269
2270 static int
2271 hns3_dev_configure(struct rte_eth_dev *dev)
2272 {
2273         struct hns3_adapter *hns = dev->data->dev_private;
2274         struct rte_eth_conf *conf = &dev->data->dev_conf;
2275         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2276         struct hns3_hw *hw = &hns->hw;
2277         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2278         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2279         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2280         struct rte_eth_rss_conf rss_conf;
2281         uint16_t mtu;
2282         int ret;
2283
2284         /*
2285          * Hardware does not support individually enable/disable/reset the Tx or
2286          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2287          * and Rx queues at the same time. When the numbers of Tx queues
2288          * allocated by upper applications are not equal to the numbers of Rx
2289          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2290          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2291          * these fake queues are imperceptible, and can not be used by upper
2292          * applications.
2293          */
2294         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2295         if (ret) {
2296                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2297                 return ret;
2298         }
2299
2300         hw->adapter_state = HNS3_NIC_CONFIGURING;
2301         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2302                 hns3_err(hw, "setting link speed/duplex not supported");
2303                 ret = -EINVAL;
2304                 goto cfg_err;
2305         }
2306
2307         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2308                 ret = hns3_check_dcb_cfg(dev);
2309                 if (ret)
2310                         goto cfg_err;
2311         }
2312
2313         /* When RSS is not configured, redirect the packet queue 0 */
2314         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2315                 rss_conf = conf->rx_adv_conf.rss_conf;
2316                 if (rss_conf.rss_key == NULL) {
2317                         rss_conf.rss_key = rss_cfg->key;
2318                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2319                 }
2320
2321                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2322                 if (ret)
2323                         goto cfg_err;
2324         }
2325
2326         /*
2327          * If jumbo frames are enabled, MTU needs to be refreshed
2328          * according to the maximum RX packet length.
2329          */
2330         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2331                 /*
2332                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2333                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2334                  * can safely assign to "uint16_t" type variable.
2335                  */
2336                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2337                 ret = hns3_dev_mtu_set(dev, mtu);
2338                 if (ret)
2339                         goto cfg_err;
2340                 dev->data->mtu = mtu;
2341         }
2342
2343         ret = hns3_dev_configure_vlan(dev);
2344         if (ret)
2345                 goto cfg_err;
2346
2347         hw->adapter_state = HNS3_NIC_CONFIGURED;
2348
2349         return 0;
2350
2351 cfg_err:
2352         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2353         hw->adapter_state = HNS3_NIC_INITIALIZED;
2354
2355         return ret;
2356 }
2357
2358 static int
2359 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2360 {
2361         struct hns3_config_max_frm_size_cmd *req;
2362         struct hns3_cmd_desc desc;
2363
2364         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2365
2366         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2367         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2368         req->min_frm_size = RTE_ETHER_MIN_LEN;
2369
2370         return hns3_cmd_send(hw, &desc, 1);
2371 }
2372
2373 static int
2374 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2375 {
2376         int ret;
2377
2378         ret = hns3_set_mac_mtu(hw, mps);
2379         if (ret) {
2380                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2381                 return ret;
2382         }
2383
2384         ret = hns3_buffer_alloc(hw);
2385         if (ret)
2386                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2387
2388         return ret;
2389 }
2390
2391 static int
2392 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2393 {
2394         struct hns3_adapter *hns = dev->data->dev_private;
2395         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2396         struct hns3_hw *hw = &hns->hw;
2397         bool is_jumbo_frame;
2398         int ret;
2399
2400         if (dev->data->dev_started) {
2401                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2402                          "before configuration", dev->data->port_id);
2403                 return -EBUSY;
2404         }
2405
2406         rte_spinlock_lock(&hw->lock);
2407         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2408         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2409
2410         /*
2411          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2412          * assign to "uint16_t" type variable.
2413          */
2414         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2415         if (ret) {
2416                 rte_spinlock_unlock(&hw->lock);
2417                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2418                          dev->data->port_id, mtu, ret);
2419                 return ret;
2420         }
2421         hns->pf.mps = (uint16_t)frame_size;
2422         if (is_jumbo_frame)
2423                 dev->data->dev_conf.rxmode.offloads |=
2424                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2425         else
2426                 dev->data->dev_conf.rxmode.offloads &=
2427                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2428         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2429         rte_spinlock_unlock(&hw->lock);
2430
2431         return 0;
2432 }
2433
2434 static int
2435 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2436 {
2437         struct hns3_adapter *hns = eth_dev->data->dev_private;
2438         struct hns3_hw *hw = &hns->hw;
2439         uint16_t queue_num = hw->tqps_num;
2440
2441         /*
2442          * In interrupt mode, 'max_rx_queues' is set based on the number of
2443          * MSI-X interrupt resources of the hardware.
2444          */
2445         if (hw->data->dev_conf.intr_conf.rxq == 1)
2446                 queue_num = hw->intr_tqps_num;
2447
2448         info->max_rx_queues = queue_num;
2449         info->max_tx_queues = hw->tqps_num;
2450         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2451         info->min_rx_bufsize = hw->rx_buf_len;
2452         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2453         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2454         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2455                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2456                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2457                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2458                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2459                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2460                                  DEV_RX_OFFLOAD_KEEP_CRC |
2461                                  DEV_RX_OFFLOAD_SCATTER |
2462                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2463                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2464                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2465                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2466                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2467                                  DEV_RX_OFFLOAD_RSS_HASH);
2468         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2469         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2470                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2471                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2472                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2473                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2474                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2475                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2476                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2477                                  DEV_TX_OFFLOAD_TCP_TSO |
2478                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2479                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2480                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2481                                  info->tx_queue_offload_capa);
2482
2483         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2484                 .nb_max = HNS3_MAX_RING_DESC,
2485                 .nb_min = HNS3_MIN_RING_DESC,
2486                 .nb_align = HNS3_ALIGN_RING_DESC,
2487         };
2488
2489         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2490                 .nb_max = HNS3_MAX_RING_DESC,
2491                 .nb_min = HNS3_MIN_RING_DESC,
2492                 .nb_align = HNS3_ALIGN_RING_DESC,
2493         };
2494
2495         info->vmdq_queue_num = 0;
2496
2497         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2498         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2499         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2500
2501         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2502         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2503         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2504         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2505         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2506         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2507
2508         return 0;
2509 }
2510
2511 static int
2512 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2513                     size_t fw_size)
2514 {
2515         struct hns3_adapter *hns = eth_dev->data->dev_private;
2516         struct hns3_hw *hw = &hns->hw;
2517         uint32_t version = hw->fw_version;
2518         int ret;
2519
2520         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2521                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2522                                       HNS3_FW_VERSION_BYTE3_S),
2523                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2524                                       HNS3_FW_VERSION_BYTE2_S),
2525                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2526                                       HNS3_FW_VERSION_BYTE1_S),
2527                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2528                                       HNS3_FW_VERSION_BYTE0_S));
2529         ret += 1; /* add the size of '\0' */
2530         if (fw_size < (uint32_t)ret)
2531                 return ret;
2532         else
2533                 return 0;
2534 }
2535
2536 static int
2537 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2538                      __rte_unused int wait_to_complete)
2539 {
2540         struct hns3_adapter *hns = eth_dev->data->dev_private;
2541         struct hns3_hw *hw = &hns->hw;
2542         struct hns3_mac *mac = &hw->mac;
2543         struct rte_eth_link new_link;
2544
2545         if (!hns3_is_reset_pending(hns)) {
2546                 hns3_update_speed_duplex(eth_dev);
2547                 hns3_update_link_status(hw);
2548         }
2549
2550         memset(&new_link, 0, sizeof(new_link));
2551         switch (mac->link_speed) {
2552         case ETH_SPEED_NUM_10M:
2553         case ETH_SPEED_NUM_100M:
2554         case ETH_SPEED_NUM_1G:
2555         case ETH_SPEED_NUM_10G:
2556         case ETH_SPEED_NUM_25G:
2557         case ETH_SPEED_NUM_40G:
2558         case ETH_SPEED_NUM_50G:
2559         case ETH_SPEED_NUM_100G:
2560                 new_link.link_speed = mac->link_speed;
2561                 break;
2562         default:
2563                 new_link.link_speed = ETH_SPEED_NUM_100M;
2564                 break;
2565         }
2566
2567         new_link.link_duplex = mac->link_duplex;
2568         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2569         new_link.link_autoneg =
2570             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2571
2572         return rte_eth_linkstatus_set(eth_dev, &new_link);
2573 }
2574
2575 static int
2576 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2577 {
2578         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2579         struct hns3_pf *pf = &hns->pf;
2580
2581         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2582                 return -EINVAL;
2583
2584         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2585
2586         return 0;
2587 }
2588
2589 static int
2590 hns3_query_function_status(struct hns3_hw *hw)
2591 {
2592 #define HNS3_QUERY_MAX_CNT              10
2593 #define HNS3_QUERY_SLEEP_MSCOEND        1
2594         struct hns3_func_status_cmd *req;
2595         struct hns3_cmd_desc desc;
2596         int timeout = 0;
2597         int ret;
2598
2599         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2600         req = (struct hns3_func_status_cmd *)desc.data;
2601
2602         do {
2603                 ret = hns3_cmd_send(hw, &desc, 1);
2604                 if (ret) {
2605                         PMD_INIT_LOG(ERR, "query function status failed %d",
2606                                      ret);
2607                         return ret;
2608                 }
2609
2610                 /* Check pf reset is done */
2611                 if (req->pf_state)
2612                         break;
2613
2614                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2615         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2616
2617         return hns3_parse_func_status(hw, req);
2618 }
2619
2620 static int
2621 hns3_query_pf_resource(struct hns3_hw *hw)
2622 {
2623         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2624         struct hns3_pf *pf = &hns->pf;
2625         struct hns3_pf_res_cmd *req;
2626         struct hns3_cmd_desc desc;
2627         int ret;
2628
2629         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2630         ret = hns3_cmd_send(hw, &desc, 1);
2631         if (ret) {
2632                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2633                 return ret;
2634         }
2635
2636         req = (struct hns3_pf_res_cmd *)desc.data;
2637         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2638         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2639         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2640         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2641
2642         if (req->tx_buf_size)
2643                 pf->tx_buf_size =
2644                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2645         else
2646                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2647
2648         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2649
2650         if (req->dv_buf_size)
2651                 pf->dv_buf_size =
2652                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2653         else
2654                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2655
2656         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2657
2658         hw->num_msi =
2659             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2660                            HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2661
2662         return 0;
2663 }
2664
2665 static void
2666 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2667 {
2668         struct hns3_cfg_param_cmd *req;
2669         uint64_t mac_addr_tmp_high;
2670         uint64_t mac_addr_tmp;
2671         uint32_t i;
2672
2673         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2674
2675         /* get the configuration */
2676         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2677                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2678         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2679                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2680         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2681                                            HNS3_CFG_TQP_DESC_N_M,
2682                                            HNS3_CFG_TQP_DESC_N_S);
2683
2684         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2685                                        HNS3_CFG_PHY_ADDR_M,
2686                                        HNS3_CFG_PHY_ADDR_S);
2687         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2688                                          HNS3_CFG_MEDIA_TP_M,
2689                                          HNS3_CFG_MEDIA_TP_S);
2690         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2691                                          HNS3_CFG_RX_BUF_LEN_M,
2692                                          HNS3_CFG_RX_BUF_LEN_S);
2693         /* get mac address */
2694         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2695         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2696                                            HNS3_CFG_MAC_ADDR_H_M,
2697                                            HNS3_CFG_MAC_ADDR_H_S);
2698
2699         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2700
2701         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2702                                             HNS3_CFG_DEFAULT_SPEED_M,
2703                                             HNS3_CFG_DEFAULT_SPEED_S);
2704         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2705                                            HNS3_CFG_RSS_SIZE_M,
2706                                            HNS3_CFG_RSS_SIZE_S);
2707
2708         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2709                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2710
2711         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2712         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2713
2714         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2715                                             HNS3_CFG_SPEED_ABILITY_M,
2716                                             HNS3_CFG_SPEED_ABILITY_S);
2717         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2718                                         HNS3_CFG_UMV_TBL_SPACE_M,
2719                                         HNS3_CFG_UMV_TBL_SPACE_S);
2720         if (!cfg->umv_space)
2721                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2722 }
2723
2724 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2725  * @hw: pointer to struct hns3_hw
2726  * @hcfg: the config structure to be getted
2727  */
2728 static int
2729 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2730 {
2731         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2732         struct hns3_cfg_param_cmd *req;
2733         uint32_t offset;
2734         uint32_t i;
2735         int ret;
2736
2737         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2738                 offset = 0;
2739                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2740                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2741                                           true);
2742                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2743                                i * HNS3_CFG_RD_LEN_BYTES);
2744                 /* Len should be divided by 4 when send to hardware */
2745                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2746                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2747                 req->offset = rte_cpu_to_le_32(offset);
2748         }
2749
2750         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2751         if (ret) {
2752                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2753                 return ret;
2754         }
2755
2756         hns3_parse_cfg(hcfg, desc);
2757
2758         return 0;
2759 }
2760
2761 static int
2762 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2763 {
2764         switch (speed_cmd) {
2765         case HNS3_CFG_SPEED_10M:
2766                 *speed = ETH_SPEED_NUM_10M;
2767                 break;
2768         case HNS3_CFG_SPEED_100M:
2769                 *speed = ETH_SPEED_NUM_100M;
2770                 break;
2771         case HNS3_CFG_SPEED_1G:
2772                 *speed = ETH_SPEED_NUM_1G;
2773                 break;
2774         case HNS3_CFG_SPEED_10G:
2775                 *speed = ETH_SPEED_NUM_10G;
2776                 break;
2777         case HNS3_CFG_SPEED_25G:
2778                 *speed = ETH_SPEED_NUM_25G;
2779                 break;
2780         case HNS3_CFG_SPEED_40G:
2781                 *speed = ETH_SPEED_NUM_40G;
2782                 break;
2783         case HNS3_CFG_SPEED_50G:
2784                 *speed = ETH_SPEED_NUM_50G;
2785                 break;
2786         case HNS3_CFG_SPEED_100G:
2787                 *speed = ETH_SPEED_NUM_100G;
2788                 break;
2789         default:
2790                 return -EINVAL;
2791         }
2792
2793         return 0;
2794 }
2795
2796 static int
2797 hns3_get_board_configuration(struct hns3_hw *hw)
2798 {
2799         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2800         struct hns3_pf *pf = &hns->pf;
2801         struct hns3_cfg cfg;
2802         int ret;
2803
2804         ret = hns3_get_board_cfg(hw, &cfg);
2805         if (ret) {
2806                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2807                 return ret;
2808         }
2809
2810         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2811                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2812                 return -EOPNOTSUPP;
2813         }
2814
2815         hw->mac.media_type = cfg.media_type;
2816         hw->rss_size_max = cfg.rss_size_max;
2817         hw->rss_dis_flag = false;
2818         hw->rx_buf_len = cfg.rx_buf_len;
2819         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2820         hw->mac.phy_addr = cfg.phy_addr;
2821         hw->mac.default_addr_setted = false;
2822         hw->num_tx_desc = cfg.tqp_desc_num;
2823         hw->num_rx_desc = cfg.tqp_desc_num;
2824         hw->dcb_info.num_pg = 1;
2825         hw->dcb_info.hw_pfc_map = 0;
2826
2827         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2828         if (ret) {
2829                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2830                              cfg.default_speed, ret);
2831                 return ret;
2832         }
2833
2834         pf->tc_max = cfg.tc_num;
2835         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2836                 PMD_INIT_LOG(WARNING,
2837                              "Get TC num(%u) from flash, set TC num to 1",
2838                              pf->tc_max);
2839                 pf->tc_max = 1;
2840         }
2841
2842         /* Dev does not support DCB */
2843         if (!hns3_dev_dcb_supported(hw)) {
2844                 pf->tc_max = 1;
2845                 pf->pfc_max = 0;
2846         } else
2847                 pf->pfc_max = pf->tc_max;
2848
2849         hw->dcb_info.num_tc = 1;
2850         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2851                                      hw->tqps_num / hw->dcb_info.num_tc);
2852         hns3_set_bit(hw->hw_tc_map, 0, 1);
2853         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2854
2855         pf->wanted_umv_size = cfg.umv_space;
2856
2857         return ret;
2858 }
2859
2860 static int
2861 hns3_get_configuration(struct hns3_hw *hw)
2862 {
2863         int ret;
2864
2865         ret = hns3_query_function_status(hw);
2866         if (ret) {
2867                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2868                 return ret;
2869         }
2870
2871         /* Get pf resource */
2872         ret = hns3_query_pf_resource(hw);
2873         if (ret) {
2874                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2875                 return ret;
2876         }
2877
2878         ret = hns3_get_board_configuration(hw);
2879         if (ret)
2880                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2881
2882         return ret;
2883 }
2884
2885 static int
2886 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2887                       uint16_t tqp_vid, bool is_pf)
2888 {
2889         struct hns3_tqp_map_cmd *req;
2890         struct hns3_cmd_desc desc;
2891         int ret;
2892
2893         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2894
2895         req = (struct hns3_tqp_map_cmd *)desc.data;
2896         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2897         req->tqp_vf = func_id;
2898         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2899         if (!is_pf)
2900                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2901         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2902
2903         ret = hns3_cmd_send(hw, &desc, 1);
2904         if (ret)
2905                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2906
2907         return ret;
2908 }
2909
2910 static int
2911 hns3_map_tqp(struct hns3_hw *hw)
2912 {
2913         uint16_t tqps_num = hw->total_tqps_num;
2914         uint16_t func_id;
2915         uint16_t tqp_id;
2916         bool is_pf;
2917         int num;
2918         int ret;
2919         int i;
2920
2921         /*
2922          * In current version VF is not supported when PF is driven by DPDK
2923          * driver, so we allocate tqps to PF as much as possible.
2924          */
2925         tqp_id = 0;
2926         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2927         for (func_id = HNS3_PF_FUNC_ID; func_id < num; func_id++) {
2928                 is_pf = func_id == HNS3_PF_FUNC_ID ? true : false;
2929                 for (i = 0;
2930                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2931                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2932                                                     is_pf);
2933                         if (ret)
2934                                 return ret;
2935                 }
2936         }
2937
2938         return 0;
2939 }
2940
2941 static int
2942 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2943 {
2944         struct hns3_config_mac_speed_dup_cmd *req;
2945         struct hns3_cmd_desc desc;
2946         int ret;
2947
2948         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2949
2950         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2951
2952         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2953
2954         switch (speed) {
2955         case ETH_SPEED_NUM_10M:
2956                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2957                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2958                 break;
2959         case ETH_SPEED_NUM_100M:
2960                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2961                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2962                 break;
2963         case ETH_SPEED_NUM_1G:
2964                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2965                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2966                 break;
2967         case ETH_SPEED_NUM_10G:
2968                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2969                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2970                 break;
2971         case ETH_SPEED_NUM_25G:
2972                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2973                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2974                 break;
2975         case ETH_SPEED_NUM_40G:
2976                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2977                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2978                 break;
2979         case ETH_SPEED_NUM_50G:
2980                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2981                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2982                 break;
2983         case ETH_SPEED_NUM_100G:
2984                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2985                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2986                 break;
2987         default:
2988                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2989                 return -EINVAL;
2990         }
2991
2992         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2993
2994         ret = hns3_cmd_send(hw, &desc, 1);
2995         if (ret)
2996                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2997
2998         return ret;
2999 }
3000
3001 static int
3002 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3003 {
3004         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3005         struct hns3_pf *pf = &hns->pf;
3006         struct hns3_priv_buf *priv;
3007         uint32_t i, total_size;
3008
3009         total_size = pf->pkt_buf_size;
3010
3011         /* alloc tx buffer for all enabled tc */
3012         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3013                 priv = &buf_alloc->priv_buf[i];
3014
3015                 if (hw->hw_tc_map & BIT(i)) {
3016                         if (total_size < pf->tx_buf_size)
3017                                 return -ENOMEM;
3018
3019                         priv->tx_buf_size = pf->tx_buf_size;
3020                 } else
3021                         priv->tx_buf_size = 0;
3022
3023                 total_size -= priv->tx_buf_size;
3024         }
3025
3026         return 0;
3027 }
3028
3029 static int
3030 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3031 {
3032 /* TX buffer size is unit by 128 byte */
3033 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3034 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3035         struct hns3_tx_buff_alloc_cmd *req;
3036         struct hns3_cmd_desc desc;
3037         uint32_t buf_size;
3038         uint32_t i;
3039         int ret;
3040
3041         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3042
3043         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3044         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3045                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3046
3047                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3048                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3049                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3050         }
3051
3052         ret = hns3_cmd_send(hw, &desc, 1);
3053         if (ret)
3054                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3055
3056         return ret;
3057 }
3058
3059 static int
3060 hns3_get_tc_num(struct hns3_hw *hw)
3061 {
3062         int cnt = 0;
3063         uint8_t i;
3064
3065         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3066                 if (hw->hw_tc_map & BIT(i))
3067                         cnt++;
3068         return cnt;
3069 }
3070
3071 static uint32_t
3072 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3073 {
3074         struct hns3_priv_buf *priv;
3075         uint32_t rx_priv = 0;
3076         int i;
3077
3078         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3079                 priv = &buf_alloc->priv_buf[i];
3080                 if (priv->enable)
3081                         rx_priv += priv->buf_size;
3082         }
3083         return rx_priv;
3084 }
3085
3086 static uint32_t
3087 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3088 {
3089         uint32_t total_tx_size = 0;
3090         uint32_t i;
3091
3092         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3093                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3094
3095         return total_tx_size;
3096 }
3097
3098 /* Get the number of pfc enabled TCs, which have private buffer */
3099 static int
3100 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3101 {
3102         struct hns3_priv_buf *priv;
3103         int cnt = 0;
3104         uint8_t i;
3105
3106         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3107                 priv = &buf_alloc->priv_buf[i];
3108                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3109                         cnt++;
3110         }
3111
3112         return cnt;
3113 }
3114
3115 /* Get the number of pfc disabled TCs, which have private buffer */
3116 static int
3117 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3118                          struct hns3_pkt_buf_alloc *buf_alloc)
3119 {
3120         struct hns3_priv_buf *priv;
3121         int cnt = 0;
3122         uint8_t i;
3123
3124         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3125                 priv = &buf_alloc->priv_buf[i];
3126                 if (hw->hw_tc_map & BIT(i) &&
3127                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3128                         cnt++;
3129         }
3130
3131         return cnt;
3132 }
3133
3134 static bool
3135 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3136                   uint32_t rx_all)
3137 {
3138         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3139         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3140         struct hns3_pf *pf = &hns->pf;
3141         uint32_t shared_buf, aligned_mps;
3142         uint32_t rx_priv;
3143         uint8_t tc_num;
3144         uint8_t i;
3145
3146         tc_num = hns3_get_tc_num(hw);
3147         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3148
3149         if (hns3_dev_dcb_supported(hw))
3150                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3151                                         pf->dv_buf_size;
3152         else
3153                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3154                                         + pf->dv_buf_size;
3155
3156         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3157         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3158                              HNS3_BUF_SIZE_UNIT);
3159
3160         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3161         if (rx_all < rx_priv + shared_std)
3162                 return false;
3163
3164         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3165         buf_alloc->s_buf.buf_size = shared_buf;
3166         if (hns3_dev_dcb_supported(hw)) {
3167                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3168                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3169                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3170                                   HNS3_BUF_SIZE_UNIT);
3171         } else {
3172                 buf_alloc->s_buf.self.high =
3173                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3174                 buf_alloc->s_buf.self.low = aligned_mps;
3175         }
3176
3177         if (hns3_dev_dcb_supported(hw)) {
3178                 hi_thrd = shared_buf - pf->dv_buf_size;
3179
3180                 if (tc_num <= NEED_RESERVE_TC_NUM)
3181                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3182                                         / BUF_MAX_PERCENT;
3183
3184                 if (tc_num)
3185                         hi_thrd = hi_thrd / tc_num;
3186
3187                 hi_thrd = max_t(uint32_t, hi_thrd,
3188                                 HNS3_BUF_MUL_BY * aligned_mps);
3189                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3190                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3191         } else {
3192                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3193                 lo_thrd = aligned_mps;
3194         }
3195
3196         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3197                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3198                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3199         }
3200
3201         return true;
3202 }
3203
3204 static bool
3205 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3206                      struct hns3_pkt_buf_alloc *buf_alloc)
3207 {
3208         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3209         struct hns3_pf *pf = &hns->pf;
3210         struct hns3_priv_buf *priv;
3211         uint32_t aligned_mps;
3212         uint32_t rx_all;
3213         uint8_t i;
3214
3215         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3216         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3217
3218         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3219                 priv = &buf_alloc->priv_buf[i];
3220
3221                 priv->enable = 0;
3222                 priv->wl.low = 0;
3223                 priv->wl.high = 0;
3224                 priv->buf_size = 0;
3225
3226                 if (!(hw->hw_tc_map & BIT(i)))
3227                         continue;
3228
3229                 priv->enable = 1;
3230                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3231                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3232                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3233                                                 HNS3_BUF_SIZE_UNIT);
3234                 } else {
3235                         priv->wl.low = 0;
3236                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3237                                         aligned_mps;
3238                 }
3239
3240                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3241         }
3242
3243         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3244 }
3245
3246 static bool
3247 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3248                              struct hns3_pkt_buf_alloc *buf_alloc)
3249 {
3250         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3251         struct hns3_pf *pf = &hns->pf;
3252         struct hns3_priv_buf *priv;
3253         int no_pfc_priv_num;
3254         uint32_t rx_all;
3255         uint8_t mask;
3256         int i;
3257
3258         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3259         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3260
3261         /* let the last to be cleared first */
3262         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3263                 priv = &buf_alloc->priv_buf[i];
3264                 mask = BIT((uint8_t)i);
3265
3266                 if (hw->hw_tc_map & mask &&
3267                     !(hw->dcb_info.hw_pfc_map & mask)) {
3268                         /* Clear the no pfc TC private buffer */
3269                         priv->wl.low = 0;
3270                         priv->wl.high = 0;
3271                         priv->buf_size = 0;
3272                         priv->enable = 0;
3273                         no_pfc_priv_num--;
3274                 }
3275
3276                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3277                     no_pfc_priv_num == 0)
3278                         break;
3279         }
3280
3281         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3282 }
3283
3284 static bool
3285 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3286                            struct hns3_pkt_buf_alloc *buf_alloc)
3287 {
3288         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3289         struct hns3_pf *pf = &hns->pf;
3290         struct hns3_priv_buf *priv;
3291         uint32_t rx_all;
3292         int pfc_priv_num;
3293         uint8_t mask;
3294         int i;
3295
3296         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3297         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3298
3299         /* let the last to be cleared first */
3300         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3301                 priv = &buf_alloc->priv_buf[i];
3302                 mask = BIT((uint8_t)i);
3303
3304                 if (hw->hw_tc_map & mask &&
3305                     hw->dcb_info.hw_pfc_map & mask) {
3306                         /* Reduce the number of pfc TC with private buffer */
3307                         priv->wl.low = 0;
3308                         priv->enable = 0;
3309                         priv->wl.high = 0;
3310                         priv->buf_size = 0;
3311                         pfc_priv_num--;
3312                 }
3313                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3314                     pfc_priv_num == 0)
3315                         break;
3316         }
3317
3318         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3319 }
3320
3321 static bool
3322 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3323                           struct hns3_pkt_buf_alloc *buf_alloc)
3324 {
3325 #define COMPENSATE_BUFFER       0x3C00
3326 #define COMPENSATE_HALF_MPS_NUM 5
3327 #define PRIV_WL_GAP             0x1800
3328         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3329         struct hns3_pf *pf = &hns->pf;
3330         uint32_t tc_num = hns3_get_tc_num(hw);
3331         uint32_t half_mps = pf->mps >> 1;
3332         struct hns3_priv_buf *priv;
3333         uint32_t min_rx_priv;
3334         uint32_t rx_priv;
3335         uint8_t i;
3336
3337         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3338         if (tc_num)
3339                 rx_priv = rx_priv / tc_num;
3340
3341         if (tc_num <= NEED_RESERVE_TC_NUM)
3342                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3343
3344         /*
3345          * Minimum value of private buffer in rx direction (min_rx_priv) is
3346          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3347          * buffer if rx_priv is greater than min_rx_priv.
3348          */
3349         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3350                         COMPENSATE_HALF_MPS_NUM * half_mps;
3351         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3352         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3353
3354         if (rx_priv < min_rx_priv)
3355                 return false;
3356
3357         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3358                 priv = &buf_alloc->priv_buf[i];
3359
3360                 priv->enable = 0;
3361                 priv->wl.low = 0;
3362                 priv->wl.high = 0;
3363                 priv->buf_size = 0;
3364
3365                 if (!(hw->hw_tc_map & BIT(i)))
3366                         continue;
3367
3368                 priv->enable = 1;
3369                 priv->buf_size = rx_priv;
3370                 priv->wl.high = rx_priv - pf->dv_buf_size;
3371                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3372         }
3373
3374         buf_alloc->s_buf.buf_size = 0;
3375
3376         return true;
3377 }
3378
3379 /*
3380  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3381  * @hw: pointer to struct hns3_hw
3382  * @buf_alloc: pointer to buffer calculation data
3383  * @return: 0: calculate sucessful, negative: fail
3384  */
3385 static int
3386 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3387 {
3388         /* When DCB is not supported, rx private buffer is not allocated. */
3389         if (!hns3_dev_dcb_supported(hw)) {
3390                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3391                 struct hns3_pf *pf = &hns->pf;
3392                 uint32_t rx_all = pf->pkt_buf_size;
3393
3394                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3395                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3396                         return -ENOMEM;
3397
3398                 return 0;
3399         }
3400
3401         /*
3402          * Try to allocate privated packet buffer for all TCs without share
3403          * buffer.
3404          */
3405         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3406                 return 0;
3407
3408         /*
3409          * Try to allocate privated packet buffer for all TCs with share
3410          * buffer.
3411          */
3412         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3413                 return 0;
3414
3415         /*
3416          * For different application scenes, the enabled port number, TC number
3417          * and no_drop TC number are different. In order to obtain the better
3418          * performance, software could allocate the buffer size and configure
3419          * the waterline by tring to decrease the private buffer size according
3420          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3421          * enabled tc.
3422          */
3423         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3424                 return 0;
3425
3426         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3427                 return 0;
3428
3429         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3430                 return 0;
3431
3432         return -ENOMEM;
3433 }
3434
3435 static int
3436 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3437 {
3438         struct hns3_rx_priv_buff_cmd *req;
3439         struct hns3_cmd_desc desc;
3440         uint32_t buf_size;
3441         int ret;
3442         int i;
3443
3444         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3445         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3446
3447         /* Alloc private buffer TCs */
3448         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3449                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3450
3451                 req->buf_num[i] =
3452                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3453                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3454         }
3455
3456         buf_size = buf_alloc->s_buf.buf_size;
3457         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3458                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3459
3460         ret = hns3_cmd_send(hw, &desc, 1);
3461         if (ret)
3462                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3463
3464         return ret;
3465 }
3466
3467 static int
3468 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3469 {
3470 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3471         struct hns3_rx_priv_wl_buf *req;
3472         struct hns3_priv_buf *priv;
3473         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3474         int i, j;
3475         int ret;
3476
3477         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3478                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3479                                           false);
3480                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3481
3482                 /* The first descriptor set the NEXT bit to 1 */
3483                 if (i == 0)
3484                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3485                 else
3486                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3487
3488                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3489                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3490
3491                         priv = &buf_alloc->priv_buf[idx];
3492                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3493                                                         HNS3_BUF_UNIT_S);
3494                         req->tc_wl[j].high |=
3495                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3496                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3497                                                         HNS3_BUF_UNIT_S);
3498                         req->tc_wl[j].low |=
3499                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3500                 }
3501         }
3502
3503         /* Send 2 descriptor at one time */
3504         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3505         if (ret)
3506                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3507                              ret);
3508         return ret;
3509 }
3510
3511 static int
3512 hns3_common_thrd_config(struct hns3_hw *hw,
3513                         struct hns3_pkt_buf_alloc *buf_alloc)
3514 {
3515 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3516         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3517         struct hns3_rx_com_thrd *req;
3518         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3519         struct hns3_tc_thrd *tc;
3520         int tc_idx;
3521         int i, j;
3522         int ret;
3523
3524         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3525                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3526                                           false);
3527                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3528
3529                 /* The first descriptor set the NEXT bit to 1 */
3530                 if (i == 0)
3531                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3532                 else
3533                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3534
3535                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3536                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3537                         tc = &s_buf->tc_thrd[tc_idx];
3538
3539                         req->com_thrd[j].high =
3540                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3541                         req->com_thrd[j].high |=
3542                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3543                         req->com_thrd[j].low =
3544                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3545                         req->com_thrd[j].low |=
3546                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3547                 }
3548         }
3549
3550         /* Send 2 descriptors at one time */
3551         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3552         if (ret)
3553                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3554
3555         return ret;
3556 }
3557
3558 static int
3559 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3560 {
3561         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3562         struct hns3_rx_com_wl *req;
3563         struct hns3_cmd_desc desc;
3564         int ret;
3565
3566         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3567
3568         req = (struct hns3_rx_com_wl *)desc.data;
3569         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3570         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3571
3572         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3573         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3574
3575         ret = hns3_cmd_send(hw, &desc, 1);
3576         if (ret)
3577                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3578
3579         return ret;
3580 }
3581
3582 int
3583 hns3_buffer_alloc(struct hns3_hw *hw)
3584 {
3585         struct hns3_pkt_buf_alloc pkt_buf;
3586         int ret;
3587
3588         memset(&pkt_buf, 0, sizeof(pkt_buf));
3589         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3590         if (ret) {
3591                 PMD_INIT_LOG(ERR,
3592                              "could not calc tx buffer size for all TCs %d",
3593                              ret);
3594                 return ret;
3595         }
3596
3597         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3598         if (ret) {
3599                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3600                 return ret;
3601         }
3602
3603         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3604         if (ret) {
3605                 PMD_INIT_LOG(ERR,
3606                              "could not calc rx priv buffer size for all TCs %d",
3607                              ret);
3608                 return ret;
3609         }
3610
3611         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3612         if (ret) {
3613                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3614                 return ret;
3615         }
3616
3617         if (hns3_dev_dcb_supported(hw)) {
3618                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3619                 if (ret) {
3620                         PMD_INIT_LOG(ERR,
3621                                      "could not configure rx private waterline %d",
3622                                      ret);
3623                         return ret;
3624                 }
3625
3626                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3627                 if (ret) {
3628                         PMD_INIT_LOG(ERR,
3629                                      "could not configure common threshold %d",
3630                                      ret);
3631                         return ret;
3632                 }
3633         }
3634
3635         ret = hns3_common_wl_config(hw, &pkt_buf);
3636         if (ret)
3637                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3638                              ret);
3639
3640         return ret;
3641 }
3642
3643 static int
3644 hns3_mac_init(struct hns3_hw *hw)
3645 {
3646         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3647         struct hns3_mac *mac = &hw->mac;
3648         struct hns3_pf *pf = &hns->pf;
3649         int ret;
3650
3651         pf->support_sfp_query = true;
3652         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3653         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3654         if (ret) {
3655                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3656                 return ret;
3657         }
3658
3659         mac->link_status = ETH_LINK_DOWN;
3660
3661         return hns3_config_mtu(hw, pf->mps);
3662 }
3663
3664 static int
3665 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3666 {
3667 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3668 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3669 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3670 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3671         int return_status;
3672
3673         if (cmdq_resp) {
3674                 PMD_INIT_LOG(ERR,
3675                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3676                              cmdq_resp);
3677                 return -EIO;
3678         }
3679
3680         switch (resp_code) {
3681         case HNS3_ETHERTYPE_SUCCESS_ADD:
3682         case HNS3_ETHERTYPE_ALREADY_ADD:
3683                 return_status = 0;
3684                 break;
3685         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3686                 PMD_INIT_LOG(ERR,
3687                              "add mac ethertype failed for manager table overflow.");
3688                 return_status = -EIO;
3689                 break;
3690         case HNS3_ETHERTYPE_KEY_CONFLICT:
3691                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3692                 return_status = -EIO;
3693                 break;
3694         default:
3695                 PMD_INIT_LOG(ERR,
3696                              "add mac ethertype failed for undefined, code=%d.",
3697                              resp_code);
3698                 return_status = -EIO;
3699                 break;
3700         }
3701
3702         return return_status;
3703 }
3704
3705 static int
3706 hns3_add_mgr_tbl(struct hns3_hw *hw,
3707                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3708 {
3709         struct hns3_cmd_desc desc;
3710         uint8_t resp_code;
3711         uint16_t retval;
3712         int ret;
3713
3714         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3715         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3716
3717         ret = hns3_cmd_send(hw, &desc, 1);
3718         if (ret) {
3719                 PMD_INIT_LOG(ERR,
3720                              "add mac ethertype failed for cmd_send, ret =%d.",
3721                              ret);
3722                 return ret;
3723         }
3724
3725         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3726         retval = rte_le_to_cpu_16(desc.retval);
3727
3728         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3729 }
3730
3731 static void
3732 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3733                      int *table_item_num)
3734 {
3735         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3736
3737         /*
3738          * In current version, we add one item in management table as below:
3739          * 0x0180C200000E -- LLDP MC address
3740          */
3741         tbl = mgr_table;
3742         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3743         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3744         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3745         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3746         tbl->i_port_bitmap = 0x1;
3747         *table_item_num = 1;
3748 }
3749
3750 static int
3751 hns3_init_mgr_tbl(struct hns3_hw *hw)
3752 {
3753 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3754         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3755         int table_item_num;
3756         int ret;
3757         int i;
3758
3759         memset(mgr_table, 0, sizeof(mgr_table));
3760         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3761         for (i = 0; i < table_item_num; i++) {
3762                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3763                 if (ret) {
3764                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3765                                      ret);
3766                         return ret;
3767                 }
3768         }
3769
3770         return 0;
3771 }
3772
3773 static void
3774 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3775                         bool en_mc, bool en_bc, int vport_id)
3776 {
3777         if (!param)
3778                 return;
3779
3780         memset(param, 0, sizeof(struct hns3_promisc_param));
3781         if (en_uc)
3782                 param->enable = HNS3_PROMISC_EN_UC;
3783         if (en_mc)
3784                 param->enable |= HNS3_PROMISC_EN_MC;
3785         if (en_bc)
3786                 param->enable |= HNS3_PROMISC_EN_BC;
3787         param->vf_id = vport_id;
3788 }
3789
3790 static int
3791 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3792 {
3793         struct hns3_promisc_cfg_cmd *req;
3794         struct hns3_cmd_desc desc;
3795         int ret;
3796
3797         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3798
3799         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3800         req->vf_id = param->vf_id;
3801         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3802             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3803
3804         ret = hns3_cmd_send(hw, &desc, 1);
3805         if (ret)
3806                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3807
3808         return ret;
3809 }
3810
3811 static int
3812 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3813 {
3814         struct hns3_promisc_param param;
3815         bool en_bc_pmc = true;
3816         uint8_t vf_id;
3817
3818         /*
3819          * In current version VF is not supported when PF is driven by DPDK
3820          * driver, just need to configure parameters for PF vport.
3821          */
3822         vf_id = HNS3_PF_FUNC_ID;
3823
3824         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3825         return hns3_cmd_set_promisc_mode(hw, &param);
3826 }
3827
3828 static int
3829 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3830 {
3831         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3832         struct hns3_pf *pf = &hns->pf;
3833         struct hns3_promisc_param param;
3834         uint16_t func_id;
3835         int ret;
3836
3837         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
3838                 hns3_promisc_param_init(&param, false, false, false, func_id);
3839                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3840                 if (ret)
3841                         return ret;
3842         }
3843
3844         return 0;
3845 }
3846
3847 static int
3848 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3849 {
3850         bool allmulti = dev->data->all_multicast ? true : false;
3851         struct hns3_adapter *hns = dev->data->dev_private;
3852         struct hns3_hw *hw = &hns->hw;
3853         uint64_t offloads;
3854         int err;
3855         int ret;
3856
3857         rte_spinlock_lock(&hw->lock);
3858         ret = hns3_set_promisc_mode(hw, true, true);
3859         if (ret) {
3860                 rte_spinlock_unlock(&hw->lock);
3861                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
3862                          ret);
3863                 return ret;
3864         }
3865
3866         /*
3867          * When promiscuous mode was enabled, disable the vlan filter to let
3868          * all packets coming in in the receiving direction.
3869          */
3870         offloads = dev->data->dev_conf.rxmode.offloads;
3871         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3872                 ret = hns3_enable_vlan_filter(hns, false);
3873                 if (ret) {
3874                         hns3_err(hw, "failed to enable promiscuous mode due to "
3875                                      "failure to disable vlan filter, ret = %d",
3876                                  ret);
3877                         err = hns3_set_promisc_mode(hw, false, allmulti);
3878                         if (err)
3879                                 hns3_err(hw, "failed to restore promiscuous "
3880                                          "status after disable vlan filter "
3881                                          "failed during enabling promiscuous "
3882                                          "mode, ret = %d", ret);
3883                 }
3884         }
3885
3886         rte_spinlock_unlock(&hw->lock);
3887
3888         return ret;
3889 }
3890
3891 static int
3892 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3893 {
3894         bool allmulti = dev->data->all_multicast ? true : false;
3895         struct hns3_adapter *hns = dev->data->dev_private;
3896         struct hns3_hw *hw = &hns->hw;
3897         uint64_t offloads;
3898         int err;
3899         int ret;
3900
3901         /* If now in all_multicast mode, must remain in all_multicast mode. */
3902         rte_spinlock_lock(&hw->lock);
3903         ret = hns3_set_promisc_mode(hw, false, allmulti);
3904         if (ret) {
3905                 rte_spinlock_unlock(&hw->lock);
3906                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
3907                          ret);
3908                 return ret;
3909         }
3910         /* when promiscuous mode was disabled, restore the vlan filter status */
3911         offloads = dev->data->dev_conf.rxmode.offloads;
3912         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3913                 ret = hns3_enable_vlan_filter(hns, true);
3914                 if (ret) {
3915                         hns3_err(hw, "failed to disable promiscuous mode due to"
3916                                  " failure to restore vlan filter, ret = %d",
3917                                  ret);
3918                         err = hns3_set_promisc_mode(hw, true, true);
3919                         if (err)
3920                                 hns3_err(hw, "failed to restore promiscuous "
3921                                          "status after enabling vlan filter "
3922                                          "failed during disabling promiscuous "
3923                                          "mode, ret = %d", ret);
3924                 }
3925         }
3926         rte_spinlock_unlock(&hw->lock);
3927
3928         return ret;
3929 }
3930
3931 static int
3932 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3933 {
3934         struct hns3_adapter *hns = dev->data->dev_private;
3935         struct hns3_hw *hw = &hns->hw;
3936         int ret;
3937
3938         if (dev->data->promiscuous)
3939                 return 0;
3940
3941         rte_spinlock_lock(&hw->lock);
3942         ret = hns3_set_promisc_mode(hw, false, true);
3943         rte_spinlock_unlock(&hw->lock);
3944         if (ret)
3945                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
3946                          ret);
3947
3948         return ret;
3949 }
3950
3951 static int
3952 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3953 {
3954         struct hns3_adapter *hns = dev->data->dev_private;
3955         struct hns3_hw *hw = &hns->hw;
3956         int ret;
3957
3958         /* If now in promiscuous mode, must remain in all_multicast mode. */
3959         if (dev->data->promiscuous)
3960                 return 0;
3961
3962         rte_spinlock_lock(&hw->lock);
3963         ret = hns3_set_promisc_mode(hw, false, false);
3964         rte_spinlock_unlock(&hw->lock);
3965         if (ret)
3966                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
3967                          ret);
3968
3969         return ret;
3970 }
3971
3972 static int
3973 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3974 {
3975         struct hns3_hw *hw = &hns->hw;
3976         bool allmulti = hw->data->all_multicast ? true : false;
3977         int ret;
3978
3979         if (hw->data->promiscuous) {
3980                 ret = hns3_set_promisc_mode(hw, true, true);
3981                 if (ret)
3982                         hns3_err(hw, "failed to restore promiscuous mode, "
3983                                  "ret = %d", ret);
3984                 return ret;
3985         }
3986
3987         ret = hns3_set_promisc_mode(hw, false, allmulti);
3988         if (ret)
3989                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
3990                          ret);
3991         return ret;
3992 }
3993
3994 static int
3995 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3996 {
3997         struct hns3_sfp_speed_cmd *resp;
3998         struct hns3_cmd_desc desc;
3999         int ret;
4000
4001         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4002         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4003         ret = hns3_cmd_send(hw, &desc, 1);
4004         if (ret == -EOPNOTSUPP) {
4005                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4006                 return ret;
4007         } else if (ret) {
4008                 hns3_err(hw, "get sfp speed failed %d", ret);
4009                 return ret;
4010         }
4011
4012         *speed = resp->sfp_speed;
4013
4014         return 0;
4015 }
4016
4017 static uint8_t
4018 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4019 {
4020         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4021                 duplex = ETH_LINK_FULL_DUPLEX;
4022
4023         return duplex;
4024 }
4025
4026 static int
4027 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4028 {
4029         struct hns3_mac *mac = &hw->mac;
4030         int ret;
4031
4032         duplex = hns3_check_speed_dup(duplex, speed);
4033         if (mac->link_speed == speed && mac->link_duplex == duplex)
4034                 return 0;
4035
4036         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4037         if (ret)
4038                 return ret;
4039
4040         mac->link_speed = speed;
4041         mac->link_duplex = duplex;
4042
4043         return 0;
4044 }
4045
4046 static int
4047 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4048 {
4049         struct hns3_adapter *hns = eth_dev->data->dev_private;
4050         struct hns3_hw *hw = &hns->hw;
4051         struct hns3_pf *pf = &hns->pf;
4052         uint32_t speed;
4053         int ret;
4054
4055         /* If IMP do not support get SFP/qSFP speed, return directly */
4056         if (!pf->support_sfp_query)
4057                 return 0;
4058
4059         ret = hns3_get_sfp_speed(hw, &speed);
4060         if (ret == -EOPNOTSUPP) {
4061                 pf->support_sfp_query = false;
4062                 return ret;
4063         } else if (ret)
4064                 return ret;
4065
4066         if (speed == ETH_SPEED_NUM_NONE)
4067                 return 0; /* do nothing if no SFP */
4068
4069         /* Config full duplex for SFP */
4070         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4071 }
4072
4073 static int
4074 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4075 {
4076         struct hns3_config_mac_mode_cmd *req;
4077         struct hns3_cmd_desc desc;
4078         uint32_t loop_en = 0;
4079         uint8_t val = 0;
4080         int ret;
4081
4082         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4083
4084         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4085         if (enable)
4086                 val = 1;
4087         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4088         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4089         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4090         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4091         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4092         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4093         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4094         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4095         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4096         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4097         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4098         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4099         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4100         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4101         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4102
4103         ret = hns3_cmd_send(hw, &desc, 1);
4104         if (ret)
4105                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4106
4107         return ret;
4108 }
4109
4110 static int
4111 hns3_get_mac_link_status(struct hns3_hw *hw)
4112 {
4113         struct hns3_link_status_cmd *req;
4114         struct hns3_cmd_desc desc;
4115         int link_status;
4116         int ret;
4117
4118         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4119         ret = hns3_cmd_send(hw, &desc, 1);
4120         if (ret) {
4121                 hns3_err(hw, "get link status cmd failed %d", ret);
4122                 return ETH_LINK_DOWN;
4123         }
4124
4125         req = (struct hns3_link_status_cmd *)desc.data;
4126         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4127
4128         return !!link_status;
4129 }
4130
4131 void
4132 hns3_update_link_status(struct hns3_hw *hw)
4133 {
4134         int state;
4135
4136         state = hns3_get_mac_link_status(hw);
4137         if (state != hw->mac.link_status) {
4138                 hw->mac.link_status = state;
4139                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4140         }
4141 }
4142
4143 static void
4144 hns3_service_handler(void *param)
4145 {
4146         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4147         struct hns3_adapter *hns = eth_dev->data->dev_private;
4148         struct hns3_hw *hw = &hns->hw;
4149
4150         if (!hns3_is_reset_pending(hns)) {
4151                 hns3_update_speed_duplex(eth_dev);
4152                 hns3_update_link_status(hw);
4153         } else
4154                 hns3_warn(hw, "Cancel the query when reset is pending");
4155
4156         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4157 }
4158
4159 static int
4160 hns3_init_hardware(struct hns3_adapter *hns)
4161 {
4162         struct hns3_hw *hw = &hns->hw;
4163         int ret;
4164
4165         ret = hns3_map_tqp(hw);
4166         if (ret) {
4167                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4168                 return ret;
4169         }
4170
4171         ret = hns3_init_umv_space(hw);
4172         if (ret) {
4173                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4174                 return ret;
4175         }
4176
4177         ret = hns3_mac_init(hw);
4178         if (ret) {
4179                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4180                 goto err_mac_init;
4181         }
4182
4183         ret = hns3_init_mgr_tbl(hw);
4184         if (ret) {
4185                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4186                 goto err_mac_init;
4187         }
4188
4189         ret = hns3_set_promisc_mode(hw, false, false);
4190         if (ret) {
4191                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
4192                 goto err_mac_init;
4193         }
4194
4195         ret = hns3_clear_all_vfs_promisc_mode(hw);
4196         if (ret) {
4197                 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
4198                              ret);
4199                 goto err_mac_init;
4200         }
4201
4202         ret = hns3_init_vlan_config(hns);
4203         if (ret) {
4204                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4205                 goto err_mac_init;
4206         }
4207
4208         ret = hns3_dcb_init(hw);
4209         if (ret) {
4210                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4211                 goto err_mac_init;
4212         }
4213
4214         ret = hns3_init_fd_config(hns);
4215         if (ret) {
4216                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4217                 goto err_mac_init;
4218         }
4219
4220         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4221         if (ret) {
4222                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4223                 goto err_mac_init;
4224         }
4225
4226         ret = hns3_config_gro(hw, false);
4227         if (ret) {
4228                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4229                 goto err_mac_init;
4230         }
4231
4232         /*
4233          * In the initialization clearing the all hardware mapping relationship
4234          * configurations between queues and interrupt vectors is needed, so
4235          * some error caused by the residual configurations, such as the
4236          * unexpected interrupt, can be avoid.
4237          */
4238         ret = hns3_init_ring_with_vector(hw);
4239         if (ret) {
4240                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4241                 goto err_mac_init;
4242         }
4243
4244         return 0;
4245
4246 err_mac_init:
4247         hns3_uninit_umv_space(hw);
4248         return ret;
4249 }
4250
4251 static int
4252 hns3_init_pf(struct rte_eth_dev *eth_dev)
4253 {
4254         struct rte_device *dev = eth_dev->device;
4255         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4256         struct hns3_adapter *hns = eth_dev->data->dev_private;
4257         struct hns3_hw *hw = &hns->hw;
4258         int ret;
4259
4260         PMD_INIT_FUNC_TRACE();
4261
4262         /* Get hardware io base address from pcie BAR2 IO space */
4263         hw->io_base = pci_dev->mem_resource[2].addr;
4264
4265         /* Firmware command queue initialize */
4266         ret = hns3_cmd_init_queue(hw);
4267         if (ret) {
4268                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4269                 goto err_cmd_init_queue;
4270         }
4271
4272         hns3_clear_all_event_cause(hw);
4273
4274         /* Firmware command initialize */
4275         ret = hns3_cmd_init(hw);
4276         if (ret) {
4277                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4278                 goto err_cmd_init;
4279         }
4280
4281         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4282                                          hns3_interrupt_handler,
4283                                          eth_dev);
4284         if (ret) {
4285                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4286                 goto err_intr_callback_register;
4287         }
4288
4289         /* Enable interrupt */
4290         rte_intr_enable(&pci_dev->intr_handle);
4291         hns3_pf_enable_irq0(hw);
4292
4293         /* Get configuration */
4294         ret = hns3_get_configuration(hw);
4295         if (ret) {
4296                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4297                 goto err_get_config;
4298         }
4299
4300         ret = hns3_init_hardware(hns);
4301         if (ret) {
4302                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4303                 goto err_get_config;
4304         }
4305
4306         /* Initialize flow director filter list & hash */
4307         ret = hns3_fdir_filter_init(hns);
4308         if (ret) {
4309                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4310                 goto err_hw_init;
4311         }
4312
4313         hns3_set_default_rss_args(hw);
4314
4315         ret = hns3_enable_hw_error_intr(hns, true);
4316         if (ret) {
4317                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4318                              ret);
4319                 goto err_fdir;
4320         }
4321
4322         return 0;
4323
4324 err_fdir:
4325         hns3_fdir_filter_uninit(hns);
4326 err_hw_init:
4327         hns3_uninit_umv_space(hw);
4328
4329 err_get_config:
4330         hns3_pf_disable_irq0(hw);
4331         rte_intr_disable(&pci_dev->intr_handle);
4332         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4333                              eth_dev);
4334 err_intr_callback_register:
4335 err_cmd_init:
4336         hns3_cmd_uninit(hw);
4337         hns3_cmd_destroy_queue(hw);
4338 err_cmd_init_queue:
4339         hw->io_base = NULL;
4340
4341         return ret;
4342 }
4343
4344 static void
4345 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4346 {
4347         struct hns3_adapter *hns = eth_dev->data->dev_private;
4348         struct rte_device *dev = eth_dev->device;
4349         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4350         struct hns3_hw *hw = &hns->hw;
4351
4352         PMD_INIT_FUNC_TRACE();
4353
4354         hns3_enable_hw_error_intr(hns, false);
4355         hns3_rss_uninit(hns);
4356         hns3_fdir_filter_uninit(hns);
4357         hns3_uninit_umv_space(hw);
4358         hns3_pf_disable_irq0(hw);
4359         rte_intr_disable(&pci_dev->intr_handle);
4360         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4361                              eth_dev);
4362         hns3_cmd_uninit(hw);
4363         hns3_cmd_destroy_queue(hw);
4364         hw->io_base = NULL;
4365 }
4366
4367 static int
4368 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4369 {
4370         struct hns3_hw *hw = &hns->hw;
4371         int ret;
4372
4373         ret = hns3_dcb_cfg_update(hns);
4374         if (ret)
4375                 return ret;
4376
4377         /* Enable queues */
4378         ret = hns3_start_queues(hns, reset_queue);
4379         if (ret) {
4380                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4381                 return ret;
4382         }
4383
4384         /* Enable MAC */
4385         ret = hns3_cfg_mac_mode(hw, true);
4386         if (ret) {
4387                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4388                 goto err_config_mac_mode;
4389         }
4390         return 0;
4391
4392 err_config_mac_mode:
4393         hns3_stop_queues(hns, true);
4394         return ret;
4395 }
4396
4397 static int
4398 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4399 {
4400         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4401         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4402         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4403         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4404         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4405         uint32_t intr_vector;
4406         uint16_t q_id;
4407         int ret;
4408
4409         if (dev->data->dev_conf.intr_conf.rxq == 0)
4410                 return 0;
4411
4412         /* disable uio/vfio intr/eventfd mapping */
4413         rte_intr_disable(intr_handle);
4414
4415         /* check and configure queue intr-vector mapping */
4416         if (rte_intr_cap_multiple(intr_handle) ||
4417             !RTE_ETH_DEV_SRIOV(dev).active) {
4418                 intr_vector = hw->used_rx_queues;
4419                 /* creates event fd for each intr vector when MSIX is used */
4420                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4421                         return -EINVAL;
4422         }
4423         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4424                 intr_handle->intr_vec =
4425                         rte_zmalloc("intr_vec",
4426                                     hw->used_rx_queues * sizeof(int), 0);
4427                 if (intr_handle->intr_vec == NULL) {
4428                         hns3_err(hw, "Failed to allocate %d rx_queues"
4429                                      " intr_vec", hw->used_rx_queues);
4430                         ret = -ENOMEM;
4431                         goto alloc_intr_vec_error;
4432                 }
4433         }
4434
4435         if (rte_intr_allow_others(intr_handle)) {
4436                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4437                 base = RTE_INTR_VEC_RXTX_OFFSET;
4438         }
4439         if (rte_intr_dp_is_en(intr_handle)) {
4440                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4441                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4442                                                          HNS3_RING_TYPE_RX,
4443                                                          q_id);
4444                         if (ret)
4445                                 goto bind_vector_error;
4446                         intr_handle->intr_vec[q_id] = vec;
4447                         if (vec < base + intr_handle->nb_efd - 1)
4448                                 vec++;
4449                 }
4450         }
4451         rte_intr_enable(intr_handle);
4452         return 0;
4453
4454 bind_vector_error:
4455         rte_intr_efd_disable(intr_handle);
4456         if (intr_handle->intr_vec) {
4457                 free(intr_handle->intr_vec);
4458                 intr_handle->intr_vec = NULL;
4459         }
4460         return ret;
4461 alloc_intr_vec_error:
4462         rte_intr_efd_disable(intr_handle);
4463         return ret;
4464 }
4465
4466 static int
4467 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4468 {
4469         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4470         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4471         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4472         uint16_t q_id;
4473         int ret;
4474
4475         if (dev->data->dev_conf.intr_conf.rxq == 0)
4476                 return 0;
4477
4478         if (rte_intr_dp_is_en(intr_handle)) {
4479                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4480                         ret = hns3_bind_ring_with_vector(hw,
4481                                         intr_handle->intr_vec[q_id], true,
4482                                         HNS3_RING_TYPE_RX, q_id);
4483                         if (ret)
4484                                 return ret;
4485                 }
4486         }
4487
4488         return 0;
4489 }
4490
4491 static void
4492 hns3_restore_filter(struct rte_eth_dev *dev)
4493 {
4494         hns3_restore_rss_filter(dev);
4495 }
4496
4497 static int
4498 hns3_dev_start(struct rte_eth_dev *dev)
4499 {
4500         struct hns3_adapter *hns = dev->data->dev_private;
4501         struct hns3_hw *hw = &hns->hw;
4502         int ret;
4503
4504         PMD_INIT_FUNC_TRACE();
4505         if (rte_atomic16_read(&hw->reset.resetting))
4506                 return -EBUSY;
4507
4508         rte_spinlock_lock(&hw->lock);
4509         hw->adapter_state = HNS3_NIC_STARTING;
4510
4511         ret = hns3_do_start(hns, true);
4512         if (ret) {
4513                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4514                 rte_spinlock_unlock(&hw->lock);
4515                 return ret;
4516         }
4517         ret = hns3_map_rx_interrupt(dev);
4518         if (ret) {
4519                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4520                 rte_spinlock_unlock(&hw->lock);
4521                 return ret;
4522         }
4523
4524         hw->adapter_state = HNS3_NIC_STARTED;
4525         rte_spinlock_unlock(&hw->lock);
4526
4527         hns3_set_rxtx_function(dev);
4528         hns3_mp_req_start_rxtx(dev);
4529         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4530
4531         hns3_restore_filter(dev);
4532
4533         /* Enable interrupt of all rx queues before enabling queues */
4534         hns3_dev_all_rx_queue_intr_enable(hw, true);
4535         /*
4536          * When finished the initialization, enable queues to receive/transmit
4537          * packets.
4538          */
4539         hns3_enable_all_queues(hw, true);
4540
4541         hns3_info(hw, "hns3 dev start successful!");
4542         return 0;
4543 }
4544
4545 static int
4546 hns3_do_stop(struct hns3_adapter *hns)
4547 {
4548         struct hns3_hw *hw = &hns->hw;
4549         bool reset_queue;
4550         int ret;
4551
4552         ret = hns3_cfg_mac_mode(hw, false);
4553         if (ret)
4554                 return ret;
4555         hw->mac.link_status = ETH_LINK_DOWN;
4556
4557         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4558                 hns3_configure_all_mac_addr(hns, true);
4559                 reset_queue = true;
4560         } else
4561                 reset_queue = false;
4562         hw->mac.default_addr_setted = false;
4563         return hns3_stop_queues(hns, reset_queue);
4564 }
4565
4566 static void
4567 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4568 {
4569         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4570         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4571         struct hns3_adapter *hns = dev->data->dev_private;
4572         struct hns3_hw *hw = &hns->hw;
4573         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4574         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4575         uint16_t q_id;
4576
4577         if (dev->data->dev_conf.intr_conf.rxq == 0)
4578                 return;
4579
4580         /* unmap the ring with vector */
4581         if (rte_intr_allow_others(intr_handle)) {
4582                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4583                 base = RTE_INTR_VEC_RXTX_OFFSET;
4584         }
4585         if (rte_intr_dp_is_en(intr_handle)) {
4586                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4587                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4588                                                          HNS3_RING_TYPE_RX,
4589                                                          q_id);
4590                         if (vec < base + intr_handle->nb_efd - 1)
4591                                 vec++;
4592                 }
4593         }
4594         /* Clean datapath event and queue/vec mapping */
4595         rte_intr_efd_disable(intr_handle);
4596         if (intr_handle->intr_vec) {
4597                 rte_free(intr_handle->intr_vec);
4598                 intr_handle->intr_vec = NULL;
4599         }
4600 }
4601
4602 static void
4603 hns3_dev_stop(struct rte_eth_dev *dev)
4604 {
4605         struct hns3_adapter *hns = dev->data->dev_private;
4606         struct hns3_hw *hw = &hns->hw;
4607
4608         PMD_INIT_FUNC_TRACE();
4609
4610         hw->adapter_state = HNS3_NIC_STOPPING;
4611         hns3_set_rxtx_function(dev);
4612         rte_wmb();
4613         /* Disable datapath on secondary process. */
4614         hns3_mp_req_stop_rxtx(dev);
4615         /* Prevent crashes when queues are still in use. */
4616         rte_delay_ms(hw->tqps_num);
4617
4618         rte_spinlock_lock(&hw->lock);
4619         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4620                 hns3_do_stop(hns);
4621                 hns3_unmap_rx_interrupt(dev);
4622                 hns3_dev_release_mbufs(hns);
4623                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4624         }
4625         rte_eal_alarm_cancel(hns3_service_handler, dev);
4626         rte_spinlock_unlock(&hw->lock);
4627 }
4628
4629 static void
4630 hns3_dev_close(struct rte_eth_dev *eth_dev)
4631 {
4632         struct hns3_adapter *hns = eth_dev->data->dev_private;
4633         struct hns3_hw *hw = &hns->hw;
4634
4635         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4636                 rte_free(eth_dev->process_private);
4637                 eth_dev->process_private = NULL;
4638                 return;
4639         }
4640
4641         if (hw->adapter_state == HNS3_NIC_STARTED)
4642                 hns3_dev_stop(eth_dev);
4643
4644         hw->adapter_state = HNS3_NIC_CLOSING;
4645         hns3_reset_abort(hns);
4646         hw->adapter_state = HNS3_NIC_CLOSED;
4647
4648         hns3_configure_all_mc_mac_addr(hns, true);
4649         hns3_remove_all_vlan_table(hns);
4650         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4651         hns3_uninit_pf(eth_dev);
4652         hns3_free_all_queues(eth_dev);
4653         rte_free(hw->reset.wait_data);
4654         rte_free(eth_dev->process_private);
4655         eth_dev->process_private = NULL;
4656         hns3_mp_uninit_primary();
4657         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4658 }
4659
4660 static int
4661 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4662 {
4663         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4664         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4665
4666         fc_conf->pause_time = pf->pause_time;
4667
4668         /* return fc current mode */
4669         switch (hw->current_mode) {
4670         case HNS3_FC_FULL:
4671                 fc_conf->mode = RTE_FC_FULL;
4672                 break;
4673         case HNS3_FC_TX_PAUSE:
4674                 fc_conf->mode = RTE_FC_TX_PAUSE;
4675                 break;
4676         case HNS3_FC_RX_PAUSE:
4677                 fc_conf->mode = RTE_FC_RX_PAUSE;
4678                 break;
4679         case HNS3_FC_NONE:
4680         default:
4681                 fc_conf->mode = RTE_FC_NONE;
4682                 break;
4683         }
4684
4685         return 0;
4686 }
4687
4688 static void
4689 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4690 {
4691         switch (mode) {
4692         case RTE_FC_NONE:
4693                 hw->requested_mode = HNS3_FC_NONE;
4694                 break;
4695         case RTE_FC_RX_PAUSE:
4696                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4697                 break;
4698         case RTE_FC_TX_PAUSE:
4699                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4700                 break;
4701         case RTE_FC_FULL:
4702                 hw->requested_mode = HNS3_FC_FULL;
4703                 break;
4704         default:
4705                 hw->requested_mode = HNS3_FC_NONE;
4706                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4707                           "configured to RTE_FC_NONE", mode);
4708                 break;
4709         }
4710 }
4711
4712 static int
4713 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4714 {
4715         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4716         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4717         int ret;
4718
4719         if (fc_conf->high_water || fc_conf->low_water ||
4720             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4721                 hns3_err(hw, "Unsupported flow control settings specified, "
4722                          "high_water(%u), low_water(%u), send_xon(%u) and "
4723                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4724                          fc_conf->high_water, fc_conf->low_water,
4725                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4726                 return -EINVAL;
4727         }
4728         if (fc_conf->autoneg) {
4729                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4730                 return -EINVAL;
4731         }
4732         if (!fc_conf->pause_time) {
4733                 hns3_err(hw, "Invalid pause time %d setting.",
4734                          fc_conf->pause_time);
4735                 return -EINVAL;
4736         }
4737
4738         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4739             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4740                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4741                          "current_fc_status = %d", hw->current_fc_status);
4742                 return -EOPNOTSUPP;
4743         }
4744
4745         hns3_get_fc_mode(hw, fc_conf->mode);
4746         if (hw->requested_mode == hw->current_mode &&
4747             pf->pause_time == fc_conf->pause_time)
4748                 return 0;
4749
4750         rte_spinlock_lock(&hw->lock);
4751         ret = hns3_fc_enable(dev, fc_conf);
4752         rte_spinlock_unlock(&hw->lock);
4753
4754         return ret;
4755 }
4756
4757 static int
4758 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4759                             struct rte_eth_pfc_conf *pfc_conf)
4760 {
4761         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4762         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4763         uint8_t priority;
4764         int ret;
4765
4766         if (!hns3_dev_dcb_supported(hw)) {
4767                 hns3_err(hw, "This port does not support dcb configurations.");
4768                 return -EOPNOTSUPP;
4769         }
4770
4771         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4772             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4773                 hns3_err(hw, "Unsupported flow control settings specified, "
4774                          "high_water(%u), low_water(%u), send_xon(%u) and "
4775                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4776                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4777                          pfc_conf->fc.send_xon,
4778                          pfc_conf->fc.mac_ctrl_frame_fwd);
4779                 return -EINVAL;
4780         }
4781         if (pfc_conf->fc.autoneg) {
4782                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4783                 return -EINVAL;
4784         }
4785         if (pfc_conf->fc.pause_time == 0) {
4786                 hns3_err(hw, "Invalid pause time %d setting.",
4787                          pfc_conf->fc.pause_time);
4788                 return -EINVAL;
4789         }
4790
4791         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4792             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4793                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4794                              "current_fc_status = %d", hw->current_fc_status);
4795                 return -EOPNOTSUPP;
4796         }
4797
4798         priority = pfc_conf->priority;
4799         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4800         if (hw->dcb_info.pfc_en & BIT(priority) &&
4801             hw->requested_mode == hw->current_mode &&
4802             pfc_conf->fc.pause_time == pf->pause_time)
4803                 return 0;
4804
4805         rte_spinlock_lock(&hw->lock);
4806         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4807         rte_spinlock_unlock(&hw->lock);
4808
4809         return ret;
4810 }
4811
4812 static int
4813 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4814 {
4815         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4816         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4817         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4818         int i;
4819
4820         rte_spinlock_lock(&hw->lock);
4821         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4822                 dcb_info->nb_tcs = pf->local_max_tc;
4823         else
4824                 dcb_info->nb_tcs = 1;
4825
4826         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4827                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4828         for (i = 0; i < dcb_info->nb_tcs; i++)
4829                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4830
4831         for (i = 0; i < hw->num_tc; i++) {
4832                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4833                 dcb_info->tc_queue.tc_txq[0][i].base =
4834                                                 hw->tc_queue[i].tqp_offset;
4835                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4836                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4837                                                 hw->tc_queue[i].tqp_count;
4838         }
4839         rte_spinlock_unlock(&hw->lock);
4840
4841         return 0;
4842 }
4843
4844 static int
4845 hns3_reinit_dev(struct hns3_adapter *hns)
4846 {
4847         struct hns3_hw *hw = &hns->hw;
4848         int ret;
4849
4850         ret = hns3_cmd_init(hw);
4851         if (ret) {
4852                 hns3_err(hw, "Failed to init cmd: %d", ret);
4853                 return ret;
4854         }
4855
4856         ret = hns3_reset_all_queues(hns);
4857         if (ret) {
4858                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4859                 return ret;
4860         }
4861
4862         ret = hns3_init_hardware(hns);
4863         if (ret) {
4864                 hns3_err(hw, "Failed to init hardware: %d", ret);
4865                 return ret;
4866         }
4867
4868         ret = hns3_enable_hw_error_intr(hns, true);
4869         if (ret) {
4870                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4871                              ret);
4872                 return ret;
4873         }
4874         hns3_info(hw, "Reset done, driver initialization finished.");
4875
4876         return 0;
4877 }
4878
4879 static bool
4880 is_pf_reset_done(struct hns3_hw *hw)
4881 {
4882         uint32_t val, reg, reg_bit;
4883
4884         switch (hw->reset.level) {
4885         case HNS3_IMP_RESET:
4886                 reg = HNS3_GLOBAL_RESET_REG;
4887                 reg_bit = HNS3_IMP_RESET_BIT;
4888                 break;
4889         case HNS3_GLOBAL_RESET:
4890                 reg = HNS3_GLOBAL_RESET_REG;
4891                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4892                 break;
4893         case HNS3_FUNC_RESET:
4894                 reg = HNS3_FUN_RST_ING;
4895                 reg_bit = HNS3_FUN_RST_ING_B;
4896                 break;
4897         case HNS3_FLR_RESET:
4898         default:
4899                 hns3_err(hw, "Wait for unsupported reset level: %d",
4900                          hw->reset.level);
4901                 return true;
4902         }
4903         val = hns3_read_dev(hw, reg);
4904         if (hns3_get_bit(val, reg_bit))
4905                 return false;
4906         else
4907                 return true;
4908 }
4909
4910 bool
4911 hns3_is_reset_pending(struct hns3_adapter *hns)
4912 {
4913         struct hns3_hw *hw = &hns->hw;
4914         enum hns3_reset_level reset;
4915
4916         hns3_check_event_cause(hns, NULL);
4917         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4918         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4919                 hns3_warn(hw, "High level reset %d is pending", reset);
4920                 return true;
4921         }
4922         reset = hns3_get_reset_level(hns, &hw->reset.request);
4923         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4924                 hns3_warn(hw, "High level reset %d is request", reset);
4925                 return true;
4926         }
4927         return false;
4928 }
4929
4930 static int
4931 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4932 {
4933         struct hns3_hw *hw = &hns->hw;
4934         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4935         struct timeval tv;
4936
4937         if (wait_data->result == HNS3_WAIT_SUCCESS)
4938                 return 0;
4939         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4940                 gettimeofday(&tv, NULL);
4941                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4942                           tv.tv_sec, tv.tv_usec);
4943                 return -ETIME;
4944         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4945                 return -EAGAIN;
4946
4947         wait_data->hns = hns;
4948         wait_data->check_completion = is_pf_reset_done;
4949         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4950                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4951         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4952         wait_data->count = HNS3_RESET_WAIT_CNT;
4953         wait_data->result = HNS3_WAIT_REQUEST;
4954         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4955         return -EAGAIN;
4956 }
4957
4958 static int
4959 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4960 {
4961         struct hns3_cmd_desc desc;
4962         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4963
4964         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4965         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4966         req->fun_reset_vfid = func_id;
4967
4968         return hns3_cmd_send(hw, &desc, 1);
4969 }
4970
4971 static int
4972 hns3_imp_reset_cmd(struct hns3_hw *hw)
4973 {
4974         struct hns3_cmd_desc desc;
4975
4976         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4977         desc.data[0] = 0xeedd;
4978
4979         return hns3_cmd_send(hw, &desc, 1);
4980 }
4981
4982 static void
4983 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4984 {
4985         struct hns3_hw *hw = &hns->hw;
4986         struct timeval tv;
4987         uint32_t val;
4988
4989         gettimeofday(&tv, NULL);
4990         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4991             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4992                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4993                           tv.tv_sec, tv.tv_usec);
4994                 return;
4995         }
4996
4997         switch (reset_level) {
4998         case HNS3_IMP_RESET:
4999                 hns3_imp_reset_cmd(hw);
5000                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5001                           tv.tv_sec, tv.tv_usec);
5002                 break;
5003         case HNS3_GLOBAL_RESET:
5004                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5005                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5006                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5007                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5008                           tv.tv_sec, tv.tv_usec);
5009                 break;
5010         case HNS3_FUNC_RESET:
5011                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5012                           tv.tv_sec, tv.tv_usec);
5013                 /* schedule again to check later */
5014                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5015                 hns3_schedule_reset(hns);
5016                 break;
5017         default:
5018                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5019                 return;
5020         }
5021         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5022 }
5023
5024 static enum hns3_reset_level
5025 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5026 {
5027         struct hns3_hw *hw = &hns->hw;
5028         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5029
5030         /* Return the highest priority reset level amongst all */
5031         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5032                 reset_level = HNS3_IMP_RESET;
5033         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5034                 reset_level = HNS3_GLOBAL_RESET;
5035         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5036                 reset_level = HNS3_FUNC_RESET;
5037         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5038                 reset_level = HNS3_FLR_RESET;
5039
5040         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5041                 return HNS3_NONE_RESET;
5042
5043         return reset_level;
5044 }
5045
5046 static int
5047 hns3_prepare_reset(struct hns3_adapter *hns)
5048 {
5049         struct hns3_hw *hw = &hns->hw;
5050         uint32_t reg_val;
5051         int ret;
5052
5053         switch (hw->reset.level) {
5054         case HNS3_FUNC_RESET:
5055                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5056                 if (ret)
5057                         return ret;
5058
5059                 /*
5060                  * After performaning pf reset, it is not necessary to do the
5061                  * mailbox handling or send any command to firmware, because
5062                  * any mailbox handling or command to firmware is only valid
5063                  * after hns3_cmd_init is called.
5064                  */
5065                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5066                 hw->reset.stats.request_cnt++;
5067                 break;
5068         case HNS3_IMP_RESET:
5069                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5070                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5071                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5072                 break;
5073         default:
5074                 break;
5075         }
5076         return 0;
5077 }
5078
5079 static int
5080 hns3_set_rst_done(struct hns3_hw *hw)
5081 {
5082         struct hns3_pf_rst_done_cmd *req;
5083         struct hns3_cmd_desc desc;
5084
5085         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5086         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5087         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5088         return hns3_cmd_send(hw, &desc, 1);
5089 }
5090
5091 static int
5092 hns3_stop_service(struct hns3_adapter *hns)
5093 {
5094         struct hns3_hw *hw = &hns->hw;
5095         struct rte_eth_dev *eth_dev;
5096
5097         eth_dev = &rte_eth_devices[hw->data->port_id];
5098         if (hw->adapter_state == HNS3_NIC_STARTED)
5099                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5100         hw->mac.link_status = ETH_LINK_DOWN;
5101
5102         hns3_set_rxtx_function(eth_dev);
5103         rte_wmb();
5104         /* Disable datapath on secondary process. */
5105         hns3_mp_req_stop_rxtx(eth_dev);
5106         rte_delay_ms(hw->tqps_num);
5107
5108         rte_spinlock_lock(&hw->lock);
5109         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5110             hw->adapter_state == HNS3_NIC_STOPPING) {
5111                 hns3_do_stop(hns);
5112                 hw->reset.mbuf_deferred_free = true;
5113         } else
5114                 hw->reset.mbuf_deferred_free = false;
5115
5116         /*
5117          * It is cumbersome for hardware to pick-and-choose entries for deletion
5118          * from table space. Hence, for function reset software intervention is
5119          * required to delete the entries
5120          */
5121         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5122                 hns3_configure_all_mc_mac_addr(hns, true);
5123         rte_spinlock_unlock(&hw->lock);
5124
5125         return 0;
5126 }
5127
5128 static int
5129 hns3_start_service(struct hns3_adapter *hns)
5130 {
5131         struct hns3_hw *hw = &hns->hw;
5132         struct rte_eth_dev *eth_dev;
5133
5134         if (hw->reset.level == HNS3_IMP_RESET ||
5135             hw->reset.level == HNS3_GLOBAL_RESET)
5136                 hns3_set_rst_done(hw);
5137         eth_dev = &rte_eth_devices[hw->data->port_id];
5138         hns3_set_rxtx_function(eth_dev);
5139         hns3_mp_req_start_rxtx(eth_dev);
5140         if (hw->adapter_state == HNS3_NIC_STARTED) {
5141                 hns3_service_handler(eth_dev);
5142
5143                 /* Enable interrupt of all rx queues before enabling queues */
5144                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5145                 /*
5146                  * When finished the initialization, enable queues to receive
5147                  * and transmit packets.
5148                  */
5149                 hns3_enable_all_queues(hw, true);
5150         }
5151
5152         return 0;
5153 }
5154
5155 static int
5156 hns3_restore_conf(struct hns3_adapter *hns)
5157 {
5158         struct hns3_hw *hw = &hns->hw;
5159         int ret;
5160
5161         ret = hns3_configure_all_mac_addr(hns, false);
5162         if (ret)
5163                 return ret;
5164
5165         ret = hns3_configure_all_mc_mac_addr(hns, false);
5166         if (ret)
5167                 goto err_mc_mac;
5168
5169         ret = hns3_dev_promisc_restore(hns);
5170         if (ret)
5171                 goto err_promisc;
5172
5173         ret = hns3_restore_vlan_table(hns);
5174         if (ret)
5175                 goto err_promisc;
5176
5177         ret = hns3_restore_vlan_conf(hns);
5178         if (ret)
5179                 goto err_promisc;
5180
5181         ret = hns3_restore_all_fdir_filter(hns);
5182         if (ret)
5183                 goto err_promisc;
5184
5185         ret = hns3_restore_rx_interrupt(hw);
5186         if (ret)
5187                 goto err_promisc;
5188
5189         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5190                 ret = hns3_do_start(hns, false);
5191                 if (ret)
5192                         goto err_promisc;
5193                 hns3_info(hw, "hns3 dev restart successful!");
5194         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5195                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5196         return 0;
5197
5198 err_promisc:
5199         hns3_configure_all_mc_mac_addr(hns, true);
5200 err_mc_mac:
5201         hns3_configure_all_mac_addr(hns, true);
5202         return ret;
5203 }
5204
5205 static void
5206 hns3_reset_service(void *param)
5207 {
5208         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5209         struct hns3_hw *hw = &hns->hw;
5210         enum hns3_reset_level reset_level;
5211         struct timeval tv_delta;
5212         struct timeval tv_start;
5213         struct timeval tv;
5214         uint64_t msec;
5215         int ret;
5216
5217         /*
5218          * The interrupt is not triggered within the delay time.
5219          * The interrupt may have been lost. It is necessary to handle
5220          * the interrupt to recover from the error.
5221          */
5222         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5223                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5224                 hns3_err(hw, "Handling interrupts in delayed tasks");
5225                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5226                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5227                 if (reset_level == HNS3_NONE_RESET) {
5228                         hns3_err(hw, "No reset level is set, try IMP reset");
5229                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5230                 }
5231         }
5232         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5233
5234         /*
5235          * Check if there is any ongoing reset in the hardware. This status can
5236          * be checked from reset_pending. If there is then, we need to wait for
5237          * hardware to complete reset.
5238          *    a. If we are able to figure out in reasonable time that hardware
5239          *       has fully resetted then, we can proceed with driver, client
5240          *       reset.
5241          *    b. else, we can come back later to check this status so re-sched
5242          *       now.
5243          */
5244         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5245         if (reset_level != HNS3_NONE_RESET) {
5246                 gettimeofday(&tv_start, NULL);
5247                 ret = hns3_reset_process(hns, reset_level);
5248                 gettimeofday(&tv, NULL);
5249                 timersub(&tv, &tv_start, &tv_delta);
5250                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5251                        tv_delta.tv_usec / USEC_PER_MSEC;
5252                 if (msec > HNS3_RESET_PROCESS_MS)
5253                         hns3_err(hw, "%d handle long time delta %" PRIx64
5254                                      " ms time=%ld.%.6ld",
5255                                  hw->reset.level, msec,
5256                                  tv.tv_sec, tv.tv_usec);
5257                 if (ret == -EAGAIN)
5258                         return;
5259         }
5260
5261         /* Check if we got any *new* reset requests to be honored */
5262         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5263         if (reset_level != HNS3_NONE_RESET)
5264                 hns3_msix_process(hns, reset_level);
5265 }
5266
5267 static const struct eth_dev_ops hns3_eth_dev_ops = {
5268         .dev_start          = hns3_dev_start,
5269         .dev_stop           = hns3_dev_stop,
5270         .dev_close          = hns3_dev_close,
5271         .promiscuous_enable = hns3_dev_promiscuous_enable,
5272         .promiscuous_disable = hns3_dev_promiscuous_disable,
5273         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5274         .allmulticast_disable = hns3_dev_allmulticast_disable,
5275         .mtu_set            = hns3_dev_mtu_set,
5276         .stats_get          = hns3_stats_get,
5277         .stats_reset        = hns3_stats_reset,
5278         .xstats_get         = hns3_dev_xstats_get,
5279         .xstats_get_names   = hns3_dev_xstats_get_names,
5280         .xstats_reset       = hns3_dev_xstats_reset,
5281         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5282         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5283         .dev_infos_get          = hns3_dev_infos_get,
5284         .fw_version_get         = hns3_fw_version_get,
5285         .rx_queue_setup         = hns3_rx_queue_setup,
5286         .tx_queue_setup         = hns3_tx_queue_setup,
5287         .rx_queue_release       = hns3_dev_rx_queue_release,
5288         .tx_queue_release       = hns3_dev_tx_queue_release,
5289         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5290         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5291         .dev_configure          = hns3_dev_configure,
5292         .flow_ctrl_get          = hns3_flow_ctrl_get,
5293         .flow_ctrl_set          = hns3_flow_ctrl_set,
5294         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5295         .mac_addr_add           = hns3_add_mac_addr,
5296         .mac_addr_remove        = hns3_remove_mac_addr,
5297         .mac_addr_set           = hns3_set_default_mac_addr,
5298         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5299         .link_update            = hns3_dev_link_update,
5300         .rss_hash_update        = hns3_dev_rss_hash_update,
5301         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5302         .reta_update            = hns3_dev_rss_reta_update,
5303         .reta_query             = hns3_dev_rss_reta_query,
5304         .filter_ctrl            = hns3_dev_filter_ctrl,
5305         .vlan_filter_set        = hns3_vlan_filter_set,
5306         .vlan_tpid_set          = hns3_vlan_tpid_set,
5307         .vlan_offload_set       = hns3_vlan_offload_set,
5308         .vlan_pvid_set          = hns3_vlan_pvid_set,
5309         .get_reg                = hns3_get_regs,
5310         .get_dcb_info           = hns3_get_dcb_info,
5311         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5312 };
5313
5314 static const struct hns3_reset_ops hns3_reset_ops = {
5315         .reset_service       = hns3_reset_service,
5316         .stop_service        = hns3_stop_service,
5317         .prepare_reset       = hns3_prepare_reset,
5318         .wait_hardware_ready = hns3_wait_hardware_ready,
5319         .reinit_dev          = hns3_reinit_dev,
5320         .restore_conf        = hns3_restore_conf,
5321         .start_service       = hns3_start_service,
5322 };
5323
5324 static int
5325 hns3_dev_init(struct rte_eth_dev *eth_dev)
5326 {
5327         struct rte_device *dev = eth_dev->device;
5328         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5329         struct hns3_adapter *hns = eth_dev->data->dev_private;
5330         struct hns3_hw *hw = &hns->hw;
5331         uint16_t device_id = pci_dev->id.device_id;
5332         uint8_t revision;
5333         int ret;
5334
5335         PMD_INIT_FUNC_TRACE();
5336
5337         /* Get PCI revision id */
5338         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
5339                                   HNS3_PCI_REVISION_ID);
5340         if (ret != HNS3_PCI_REVISION_ID_LEN) {
5341                 PMD_INIT_LOG(ERR, "Failed to read pci revision id, ret = %d",
5342                              ret);
5343                 return -EIO;
5344         }
5345         hw->revision = revision;
5346
5347         eth_dev->process_private = (struct hns3_process_private *)
5348             rte_zmalloc_socket("hns3_filter_list",
5349                                sizeof(struct hns3_process_private),
5350                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5351         if (eth_dev->process_private == NULL) {
5352                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5353                 return -ENOMEM;
5354         }
5355         /* initialize flow filter lists */
5356         hns3_filterlist_init(eth_dev);
5357
5358         hns3_set_rxtx_function(eth_dev);
5359         eth_dev->dev_ops = &hns3_eth_dev_ops;
5360         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5361                 hns3_mp_init_secondary();
5362                 hw->secondary_cnt++;
5363                 return 0;
5364         }
5365
5366         hns3_mp_init_primary();
5367         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5368
5369         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5370             device_id == HNS3_DEV_ID_50GE_RDMA ||
5371             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5372                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5373
5374         hns->is_vf = false;
5375         hw->data = eth_dev->data;
5376
5377         /*
5378          * Set default max packet size according to the mtu
5379          * default vale in DPDK frame.
5380          */
5381         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5382
5383         ret = hns3_reset_init(hw);
5384         if (ret)
5385                 goto err_init_reset;
5386         hw->reset.ops = &hns3_reset_ops;
5387
5388         ret = hns3_init_pf(eth_dev);
5389         if (ret) {
5390                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5391                 goto err_init_pf;
5392         }
5393
5394         /* Allocate memory for storing MAC addresses */
5395         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5396                                                sizeof(struct rte_ether_addr) *
5397                                                HNS3_UC_MACADDR_NUM, 0);
5398         if (eth_dev->data->mac_addrs == NULL) {
5399                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5400                              "to store MAC addresses",
5401                              sizeof(struct rte_ether_addr) *
5402                              HNS3_UC_MACADDR_NUM);
5403                 ret = -ENOMEM;
5404                 goto err_rte_zmalloc;
5405         }
5406
5407         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5408                             &eth_dev->data->mac_addrs[0]);
5409
5410         hw->adapter_state = HNS3_NIC_INITIALIZED;
5411         /*
5412          * Pass the information to the rte_eth_dev_close() that it should also
5413          * release the private port resources.
5414          */
5415         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5416
5417         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5418                 hns3_err(hw, "Reschedule reset service after dev_init");
5419                 hns3_schedule_reset(hns);
5420         } else {
5421                 /* IMP will wait ready flag before reset */
5422                 hns3_notify_reset_ready(hw, false);
5423         }
5424
5425         hns3_info(hw, "hns3 dev initialization successful!");
5426         return 0;
5427
5428 err_rte_zmalloc:
5429         hns3_uninit_pf(eth_dev);
5430
5431 err_init_pf:
5432         rte_free(hw->reset.wait_data);
5433 err_init_reset:
5434         eth_dev->dev_ops = NULL;
5435         eth_dev->rx_pkt_burst = NULL;
5436         eth_dev->tx_pkt_burst = NULL;
5437         eth_dev->tx_pkt_prepare = NULL;
5438         rte_free(eth_dev->process_private);
5439         eth_dev->process_private = NULL;
5440         return ret;
5441 }
5442
5443 static int
5444 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5445 {
5446         struct hns3_adapter *hns = eth_dev->data->dev_private;
5447         struct hns3_hw *hw = &hns->hw;
5448
5449         PMD_INIT_FUNC_TRACE();
5450
5451         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5452                 return -EPERM;
5453
5454         eth_dev->dev_ops = NULL;
5455         eth_dev->rx_pkt_burst = NULL;
5456         eth_dev->tx_pkt_burst = NULL;
5457         eth_dev->tx_pkt_prepare = NULL;
5458         if (hw->adapter_state < HNS3_NIC_CLOSING)
5459                 hns3_dev_close(eth_dev);
5460
5461         hw->adapter_state = HNS3_NIC_REMOVED;
5462         return 0;
5463 }
5464
5465 static int
5466 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5467                    struct rte_pci_device *pci_dev)
5468 {
5469         return rte_eth_dev_pci_generic_probe(pci_dev,
5470                                              sizeof(struct hns3_adapter),
5471                                              hns3_dev_init);
5472 }
5473
5474 static int
5475 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5476 {
5477         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5478 }
5479
5480 static const struct rte_pci_id pci_id_hns3_map[] = {
5481         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5482         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5483         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5484         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5485         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5486         { .vendor_id = 0, /* sentinel */ },
5487 };
5488
5489 static struct rte_pci_driver rte_hns3_pmd = {
5490         .id_table = pci_id_hns3_map,
5491         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5492         .probe = eth_hns3_pci_probe,
5493         .remove = eth_hns3_pci_remove,
5494 };
5495
5496 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5497 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5498 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5499
5500 RTE_INIT(hns3_init_log)
5501 {
5502         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5503         if (hns3_logtype_init >= 0)
5504                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5505         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5506         if (hns3_logtype_driver >= 0)
5507                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5508 }