1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
12 #include <rte_atomic.h>
13 #include <rte_bus_pci.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_interrupts.h>
26 #include "hns3_ethdev.h"
27 #include "hns3_logs.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_intr.h"
30 #include "hns3_regs.h"
34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
37 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
38 #define HNS3_PORT_BASE_VLAN_DISABLE 0
39 #define HNS3_PORT_BASE_VLAN_ENABLE 1
40 #define HNS3_INVLID_PVID 0xFFFF
42 #define HNS3_FILTER_TYPE_VF 0
43 #define HNS3_FILTER_TYPE_PORT 1
44 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
45 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
46 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
47 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
48 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
49 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
50 | HNS3_FILTER_FE_ROCE_EGRESS_B)
51 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
52 | HNS3_FILTER_FE_ROCE_INGRESS_B)
54 /* Reset related Registers */
55 #define HNS3_GLOBAL_RESET_BIT 0
56 #define HNS3_CORE_RESET_BIT 1
57 #define HNS3_IMP_RESET_BIT 2
58 #define HNS3_FUN_RST_ING_B 0
60 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
62 #define HNS3_RESET_WAIT_MS 100
63 #define HNS3_RESET_WAIT_CNT 200
65 int hns3_logtype_init;
66 int hns3_logtype_driver;
69 HNS3_VECTOR0_EVENT_RST,
70 HNS3_VECTOR0_EVENT_MBX,
71 HNS3_VECTOR0_EVENT_ERR,
72 HNS3_VECTOR0_EVENT_OTHER,
75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
82 static int hns3_add_mc_addr(struct hns3_hw *hw,
83 struct rte_ether_addr *mac_addr);
84 static int hns3_remove_mc_addr(struct hns3_hw *hw,
85 struct rte_ether_addr *mac_addr);
88 hns3_pf_disable_irq0(struct hns3_hw *hw)
90 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
94 hns3_pf_enable_irq0(struct hns3_hw *hw)
96 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
99 static enum hns3_evt_cause
100 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
102 struct hns3_hw *hw = &hns->hw;
103 uint32_t vector0_int_stats;
104 uint32_t cmdq_src_val;
106 enum hns3_evt_cause ret;
108 /* fetch the events from their corresponding regs */
109 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
110 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
113 * Assumption: If by any chance reset and mailbox events are reported
114 * together then we will only process reset event and defer the
115 * processing of the mailbox events. Since, we would have not cleared
116 * RX CMDQ event this time we would receive again another interrupt
117 * from H/W just for the mailbox.
119 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
120 rte_atomic16_set(&hw->reset.disable_cmd, 1);
121 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
122 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
124 hw->reset.stats.imp_cnt++;
125 hns3_warn(hw, "IMP reset detected, clear reset status");
127 hns3_schedule_delayed_reset(hns);
128 hns3_warn(hw, "IMP reset detected, don't clear reset status");
131 ret = HNS3_VECTOR0_EVENT_RST;
136 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
137 rte_atomic16_set(&hw->reset.disable_cmd, 1);
138 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
139 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
141 hw->reset.stats.global_cnt++;
142 hns3_warn(hw, "Global reset detected, clear reset status");
144 hns3_schedule_delayed_reset(hns);
145 hns3_warn(hw, "Global reset detected, don't clear reset status");
148 ret = HNS3_VECTOR0_EVENT_RST;
152 /* check for vector0 msix event source */
153 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
154 val = vector0_int_stats;
155 ret = HNS3_VECTOR0_EVENT_ERR;
159 /* check for vector0 mailbox(=CMDQ RX) event source */
160 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
161 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
163 ret = HNS3_VECTOR0_EVENT_MBX;
167 if (clearval && (vector0_int_stats || cmdq_src_val))
168 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
169 vector0_int_stats, cmdq_src_val);
170 val = vector0_int_stats;
171 ret = HNS3_VECTOR0_EVENT_OTHER;
180 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
182 if (event_type == HNS3_VECTOR0_EVENT_RST)
183 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
184 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
185 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
189 hns3_clear_all_event_cause(struct hns3_hw *hw)
191 uint32_t vector0_int_stats;
192 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
194 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
195 hns3_warn(hw, "Probe during IMP reset interrupt");
197 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
198 hns3_warn(hw, "Probe during Global reset interrupt");
200 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
201 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
202 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
203 BIT(HNS3_VECTOR0_CORERESET_INT_B));
204 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
208 hns3_interrupt_handler(void *param)
210 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
211 struct hns3_adapter *hns = dev->data->dev_private;
212 struct hns3_hw *hw = &hns->hw;
213 enum hns3_evt_cause event_cause;
214 uint32_t clearval = 0;
216 /* Disable interrupt */
217 hns3_pf_disable_irq0(hw);
219 event_cause = hns3_check_event_cause(hns, &clearval);
221 /* vector 0 interrupt is shared with reset and mailbox source events. */
222 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
223 hns3_handle_msix_error(hns, &hw->reset.request);
224 hns3_schedule_reset(hns);
225 } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
226 hns3_schedule_reset(hns);
227 else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
228 hns3_dev_handle_mbx_msg(hw);
230 hns3_err(hw, "Received unknown event");
232 hns3_clear_event_cause(hw, event_cause, clearval);
233 /* Enable interrupt if it is not cause by reset */
234 hns3_pf_enable_irq0(hw);
238 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
240 #define HNS3_VLAN_ID_OFFSET_STEP 160
241 #define HNS3_VLAN_BYTE_SIZE 8
242 struct hns3_vlan_filter_pf_cfg_cmd *req;
243 struct hns3_hw *hw = &hns->hw;
244 uint8_t vlan_offset_byte_val;
245 struct hns3_cmd_desc desc;
246 uint8_t vlan_offset_byte;
247 uint8_t vlan_offset_base;
250 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
252 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
253 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
255 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
257 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
258 req->vlan_offset = vlan_offset_base;
259 req->vlan_cfg = on ? 0 : 1;
260 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
262 ret = hns3_cmd_send(hw, &desc, 1);
264 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
271 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
273 struct hns3_user_vlan_table *vlan_entry;
274 struct hns3_pf *pf = &hns->pf;
276 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
277 if (vlan_entry->vlan_id == vlan_id) {
278 if (vlan_entry->hd_tbl_status)
279 hns3_set_port_vlan_filter(hns, vlan_id, 0);
280 LIST_REMOVE(vlan_entry, next);
281 rte_free(vlan_entry);
288 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
291 struct hns3_user_vlan_table *vlan_entry;
292 struct hns3_hw *hw = &hns->hw;
293 struct hns3_pf *pf = &hns->pf;
295 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
296 if (vlan_entry->vlan_id == vlan_id)
300 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
301 if (vlan_entry == NULL) {
302 hns3_err(hw, "Failed to malloc hns3 vlan table");
306 vlan_entry->hd_tbl_status = writen_to_tbl;
307 vlan_entry->vlan_id = vlan_id;
309 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
313 hns3_restore_vlan_table(struct hns3_adapter *hns)
315 struct hns3_user_vlan_table *vlan_entry;
316 struct hns3_pf *pf = &hns->pf;
320 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
321 return hns3_vlan_pvid_configure(hns,
322 pf->port_base_vlan_cfg.pvid, 1);
324 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
325 if (vlan_entry->hd_tbl_status) {
326 vlan_id = vlan_entry->vlan_id;
327 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
337 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
339 struct hns3_pf *pf = &hns->pf;
340 bool writen_to_tbl = false;
344 * When vlan filter is enabled, hardware regards vlan id 0 as the entry
345 * for normal packet, deleting vlan id 0 is not allowed.
347 if (on == 0 && vlan_id == 0)
351 * When port base vlan enabled, we use port base vlan as the vlan
352 * filter condition. In this case, we don't update vlan filter table
353 * when user add new vlan or remove exist vlan, just update the
354 * vlan list. The vlan id in vlan list will be writen in vlan filter
355 * table until port base vlan disabled
357 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
358 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
359 writen_to_tbl = true;
362 if (ret == 0 && vlan_id) {
364 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
366 hns3_rm_dev_vlan_table(hns, vlan_id);
372 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
374 struct hns3_adapter *hns = dev->data->dev_private;
375 struct hns3_hw *hw = &hns->hw;
378 rte_spinlock_lock(&hw->lock);
379 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
380 rte_spinlock_unlock(&hw->lock);
385 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
388 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
389 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
390 struct hns3_hw *hw = &hns->hw;
391 struct hns3_cmd_desc desc;
394 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
395 vlan_type != ETH_VLAN_TYPE_OUTER)) {
396 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
400 if (tpid != RTE_ETHER_TYPE_VLAN) {
401 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
405 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
406 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
408 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
409 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
410 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
411 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
412 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
413 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
414 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
415 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
418 ret = hns3_cmd_send(hw, &desc, 1);
420 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
425 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
427 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
428 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
429 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
431 ret = hns3_cmd_send(hw, &desc, 1);
433 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
439 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
442 struct hns3_adapter *hns = dev->data->dev_private;
443 struct hns3_hw *hw = &hns->hw;
446 rte_spinlock_lock(&hw->lock);
447 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
448 rte_spinlock_unlock(&hw->lock);
453 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
454 struct hns3_rx_vtag_cfg *vcfg)
456 struct hns3_vport_vtag_rx_cfg_cmd *req;
457 struct hns3_hw *hw = &hns->hw;
458 struct hns3_cmd_desc desc;
463 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
465 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
466 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
467 vcfg->strip_tag1_en ? 1 : 0);
468 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
469 vcfg->strip_tag2_en ? 1 : 0);
470 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
471 vcfg->vlan1_vlan_prionly ? 1 : 0);
472 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
473 vcfg->vlan2_vlan_prionly ? 1 : 0);
476 * In current version VF is not supported when PF is driven by DPDK
477 * driver, the PF-related vf_id is 0, just need to configure parameters
481 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
482 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
483 req->vf_bitmap[req->vf_offset] = bitmap;
485 ret = hns3_cmd_send(hw, &desc, 1);
487 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
492 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
493 struct hns3_rx_vtag_cfg *vcfg)
495 struct hns3_pf *pf = &hns->pf;
496 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
500 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
501 struct hns3_tx_vtag_cfg *vcfg)
503 struct hns3_pf *pf = &hns->pf;
504 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
508 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
510 struct hns3_rx_vtag_cfg rxvlan_cfg;
511 struct hns3_pf *pf = &hns->pf;
512 struct hns3_hw *hw = &hns->hw;
515 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
516 rxvlan_cfg.strip_tag1_en = false;
517 rxvlan_cfg.strip_tag2_en = enable;
519 rxvlan_cfg.strip_tag1_en = enable;
520 rxvlan_cfg.strip_tag2_en = true;
523 rxvlan_cfg.vlan1_vlan_prionly = false;
524 rxvlan_cfg.vlan2_vlan_prionly = false;
525 rxvlan_cfg.rx_vlan_offload_en = enable;
527 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
529 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
533 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
539 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
540 uint8_t fe_type, bool filter_en, uint8_t vf_id)
542 struct hns3_vlan_filter_ctrl_cmd *req;
543 struct hns3_cmd_desc desc;
546 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
548 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
549 req->vlan_type = vlan_type;
550 req->vlan_fe = filter_en ? fe_type : 0;
553 ret = hns3_cmd_send(hw, &desc, 1);
555 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
561 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
563 struct hns3_hw *hw = &hns->hw;
566 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
567 HNS3_FILTER_FE_EGRESS, false, 0);
569 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
573 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
574 HNS3_FILTER_FE_INGRESS, enable, 0);
576 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
582 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
584 struct hns3_adapter *hns = dev->data->dev_private;
585 struct hns3_hw *hw = &hns->hw;
586 struct rte_eth_rxmode *rxmode;
587 unsigned int tmp_mask;
591 rte_spinlock_lock(&hw->lock);
592 rxmode = &dev->data->dev_conf.rxmode;
593 tmp_mask = (unsigned int)mask;
594 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
595 /* Enable or disable VLAN stripping */
596 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
599 ret = hns3_en_hw_strip_rxvtag(hns, enable);
601 rte_spinlock_unlock(&hw->lock);
602 hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
607 rte_spinlock_unlock(&hw->lock);
613 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
614 struct hns3_tx_vtag_cfg *vcfg)
616 struct hns3_vport_vtag_tx_cfg_cmd *req;
617 struct hns3_cmd_desc desc;
618 struct hns3_hw *hw = &hns->hw;
623 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
625 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
626 req->def_vlan_tag1 = vcfg->default_tag1;
627 req->def_vlan_tag2 = vcfg->default_tag2;
628 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
629 vcfg->accept_tag1 ? 1 : 0);
630 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
631 vcfg->accept_untag1 ? 1 : 0);
632 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
633 vcfg->accept_tag2 ? 1 : 0);
634 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
635 vcfg->accept_untag2 ? 1 : 0);
636 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
637 vcfg->insert_tag1_en ? 1 : 0);
638 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
639 vcfg->insert_tag2_en ? 1 : 0);
640 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
643 * In current version VF is not supported when PF is driven by DPDK
644 * driver, the PF-related vf_id is 0, just need to configure parameters
648 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
649 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
650 req->vf_bitmap[req->vf_offset] = bitmap;
652 ret = hns3_cmd_send(hw, &desc, 1);
654 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
660 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
663 struct hns3_hw *hw = &hns->hw;
664 struct hns3_tx_vtag_cfg txvlan_cfg;
667 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
668 txvlan_cfg.accept_tag1 = true;
669 txvlan_cfg.insert_tag1_en = false;
670 txvlan_cfg.default_tag1 = 0;
672 txvlan_cfg.accept_tag1 = false;
673 txvlan_cfg.insert_tag1_en = true;
674 txvlan_cfg.default_tag1 = pvid;
677 txvlan_cfg.accept_untag1 = true;
678 txvlan_cfg.accept_tag2 = true;
679 txvlan_cfg.accept_untag2 = true;
680 txvlan_cfg.insert_tag2_en = false;
681 txvlan_cfg.default_tag2 = 0;
683 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
685 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
690 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
695 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
697 struct hns3_pf *pf = &hns->pf;
699 pf->port_base_vlan_cfg.state = on ?
700 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
702 pf->port_base_vlan_cfg.pvid = pvid;
706 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
708 struct hns3_user_vlan_table *vlan_entry;
709 struct hns3_pf *pf = &hns->pf;
711 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
712 if (vlan_entry->hd_tbl_status)
713 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
715 vlan_entry->hd_tbl_status = false;
719 vlan_entry = LIST_FIRST(&pf->vlan_list);
721 LIST_REMOVE(vlan_entry, next);
722 rte_free(vlan_entry);
723 vlan_entry = LIST_FIRST(&pf->vlan_list);
729 hns3_add_all_vlan_table(struct hns3_adapter *hns)
731 struct hns3_user_vlan_table *vlan_entry;
732 struct hns3_pf *pf = &hns->pf;
734 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
735 if (!vlan_entry->hd_tbl_status)
736 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
738 vlan_entry->hd_tbl_status = true;
743 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
745 struct hns3_hw *hw = &hns->hw;
746 struct hns3_pf *pf = &hns->pf;
749 hns3_rm_all_vlan_table(hns, true);
750 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
751 ret = hns3_set_port_vlan_filter(hns,
752 pf->port_base_vlan_cfg.pvid, 0);
754 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
762 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
763 uint16_t port_base_vlan_state,
764 uint16_t new_pvid, uint16_t old_pvid)
766 struct hns3_pf *pf = &hns->pf;
767 struct hns3_hw *hw = &hns->hw;
770 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
771 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
772 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
775 "Failed to clear clear old pvid filter, ret =%d",
781 hns3_rm_all_vlan_table(hns, false);
782 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
786 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
788 hns3_err(hw, "Failed to set port vlan filter, ret =%d",
794 if (new_pvid == pf->port_base_vlan_cfg.pvid)
795 hns3_add_all_vlan_table(hns);
801 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
803 struct hns3_rx_vtag_cfg rx_vlan_cfg;
804 struct hns3_hw *hw = &hns->hw;
808 rx_strip_en = on ? true : false;
809 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
810 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
811 rx_vlan_cfg.vlan1_vlan_prionly = false;
812 rx_vlan_cfg.vlan2_vlan_prionly = false;
813 rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
815 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
817 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
821 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
826 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
828 struct hns3_pf *pf = &hns->pf;
829 struct hns3_hw *hw = &hns->hw;
830 uint16_t port_base_vlan_state;
834 if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
835 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
836 hns3_warn(hw, "Invalid operation! As current pvid set "
837 "is %u, disable pvid %u is invalid",
838 pf->port_base_vlan_cfg.pvid, pvid);
842 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
843 HNS3_PORT_BASE_VLAN_DISABLE;
844 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
846 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
850 ret = hns3_en_rx_strip_all(hns, on);
852 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
856 if (pvid == HNS3_INVLID_PVID)
858 old_pvid = pf->port_base_vlan_cfg.pvid;
859 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
862 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
868 hns3_store_port_base_vlan_info(hns, pvid, on);
873 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
875 struct hns3_adapter *hns = dev->data->dev_private;
876 struct hns3_hw *hw = &hns->hw;
879 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
880 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
881 RTE_ETHER_MAX_VLAN_ID);
885 rte_spinlock_lock(&hw->lock);
886 ret = hns3_vlan_pvid_configure(hns, pvid, on);
887 rte_spinlock_unlock(&hw->lock);
892 init_port_base_vlan_info(struct hns3_hw *hw)
894 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
895 struct hns3_pf *pf = &hns->pf;
897 pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
898 pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
902 hns3_default_vlan_config(struct hns3_adapter *hns)
904 struct hns3_hw *hw = &hns->hw;
907 ret = hns3_set_port_vlan_filter(hns, 0, 1);
909 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
914 hns3_init_vlan_config(struct hns3_adapter *hns)
916 struct hns3_hw *hw = &hns->hw;
920 * This function can be called in the initialization and reset process,
921 * when in reset process, it means that hardware had been reseted
922 * successfully and we need to restore the hardware configuration to
923 * ensure that the hardware configuration remains unchanged before and
926 if (rte_atomic16_read(&hw->reset.resetting) == 0)
927 init_port_base_vlan_info(hw);
929 ret = hns3_enable_vlan_filter(hns, true);
931 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
935 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
936 RTE_ETHER_TYPE_VLAN);
938 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
943 * When in the reinit dev stage of the reset process, the following
944 * vlan-related configurations may differ from those at initialization,
945 * we will restore configurations to hardware in hns3_restore_vlan_table
946 * and hns3_restore_vlan_conf later.
948 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
949 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
951 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
955 ret = hns3_en_hw_strip_rxvtag(hns, false);
957 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
963 return hns3_default_vlan_config(hns);
967 hns3_restore_vlan_conf(struct hns3_adapter *hns)
969 struct hns3_pf *pf = &hns->pf;
970 struct hns3_hw *hw = &hns->hw;
973 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
975 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
979 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
981 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
987 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
989 struct hns3_adapter *hns = dev->data->dev_private;
990 struct rte_eth_dev_data *data = dev->data;
991 struct rte_eth_txmode *txmode;
992 struct hns3_hw *hw = &hns->hw;
995 txmode = &data->dev_conf.txmode;
996 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
998 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
999 "configuration is not supported! Ignore these two "
1000 "parameters: hw_vlan_reject_tagged(%d), "
1001 "hw_vlan_reject_untagged(%d)",
1002 txmode->hw_vlan_reject_tagged,
1003 txmode->hw_vlan_reject_untagged);
1005 /* Apply vlan offload setting */
1006 ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1008 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
1012 /* Apply pvid setting */
1013 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1014 txmode->hw_vlan_insert_pvid);
1016 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
1023 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1024 unsigned int tso_mss_max)
1026 struct hns3_cfg_tso_status_cmd *req;
1027 struct hns3_cmd_desc desc;
1030 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1032 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1035 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1037 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1040 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1042 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1044 return hns3_cmd_send(hw, &desc, 1);
1048 hns3_config_gro(struct hns3_hw *hw, bool en)
1050 struct hns3_cfg_gro_status_cmd *req;
1051 struct hns3_cmd_desc desc;
1054 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1055 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1057 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1059 ret = hns3_cmd_send(hw, &desc, 1);
1061 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1067 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1068 uint16_t *allocated_size, bool is_alloc)
1070 struct hns3_umv_spc_alc_cmd *req;
1071 struct hns3_cmd_desc desc;
1074 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1075 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1076 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1077 req->space_size = rte_cpu_to_le_32(space_size);
1079 ret = hns3_cmd_send(hw, &desc, 1);
1081 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1082 is_alloc ? "allocate" : "free", ret);
1086 if (is_alloc && allocated_size)
1087 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1093 hns3_init_umv_space(struct hns3_hw *hw)
1095 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1096 struct hns3_pf *pf = &hns->pf;
1097 uint16_t allocated_size = 0;
1100 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1105 if (allocated_size < pf->wanted_umv_size)
1106 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1107 pf->wanted_umv_size, allocated_size);
1109 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1110 pf->wanted_umv_size;
1111 pf->used_umv_size = 0;
1116 hns3_uninit_umv_space(struct hns3_hw *hw)
1118 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1119 struct hns3_pf *pf = &hns->pf;
1122 if (pf->max_umv_size == 0)
1125 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1129 pf->max_umv_size = 0;
1135 hns3_is_umv_space_full(struct hns3_hw *hw)
1137 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1138 struct hns3_pf *pf = &hns->pf;
1141 is_full = (pf->used_umv_size >= pf->max_umv_size);
1147 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1149 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1150 struct hns3_pf *pf = &hns->pf;
1153 if (pf->used_umv_size > 0)
1154 pf->used_umv_size--;
1156 pf->used_umv_size++;
1160 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1161 const uint8_t *addr, bool is_mc)
1163 const unsigned char *mac_addr = addr;
1164 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1165 ((uint32_t)mac_addr[2] << 16) |
1166 ((uint32_t)mac_addr[1] << 8) |
1167 (uint32_t)mac_addr[0];
1168 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1170 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1172 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1173 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1174 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1177 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1178 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1182 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1184 enum hns3_mac_vlan_tbl_opcode op)
1187 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1192 if (op == HNS3_MAC_VLAN_ADD) {
1193 if (resp_code == 0 || resp_code == 1) {
1195 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1196 hns3_err(hw, "add mac addr failed for uc_overflow");
1198 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1199 hns3_err(hw, "add mac addr failed for mc_overflow");
1203 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1206 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1207 if (resp_code == 0) {
1209 } else if (resp_code == 1) {
1210 hns3_dbg(hw, "remove mac addr failed for miss");
1214 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1217 } else if (op == HNS3_MAC_VLAN_LKUP) {
1218 if (resp_code == 0) {
1220 } else if (resp_code == 1) {
1221 hns3_dbg(hw, "lookup mac addr failed for miss");
1225 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1230 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1237 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1238 struct hns3_mac_vlan_tbl_entry_cmd *req,
1239 struct hns3_cmd_desc *desc, bool is_mc)
1245 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1247 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1248 memcpy(desc[0].data, req,
1249 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1250 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1252 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1253 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1255 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1257 memcpy(desc[0].data, req,
1258 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1259 ret = hns3_cmd_send(hw, desc, 1);
1262 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1266 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1267 retval = rte_le_to_cpu_16(desc[0].retval);
1269 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1270 HNS3_MAC_VLAN_LKUP);
1274 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1275 struct hns3_mac_vlan_tbl_entry_cmd *req,
1276 struct hns3_cmd_desc *mc_desc)
1283 if (mc_desc == NULL) {
1284 struct hns3_cmd_desc desc;
1286 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1287 memcpy(desc.data, req,
1288 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1289 ret = hns3_cmd_send(hw, &desc, 1);
1290 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1291 retval = rte_le_to_cpu_16(desc.retval);
1293 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1296 hns3_cmd_reuse_desc(&mc_desc[0], false);
1297 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1298 hns3_cmd_reuse_desc(&mc_desc[1], false);
1299 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1300 hns3_cmd_reuse_desc(&mc_desc[2], false);
1301 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1302 memcpy(mc_desc[0].data, req,
1303 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1304 mc_desc[0].retval = 0;
1305 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1306 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1307 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1309 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1314 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1322 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1323 struct hns3_mac_vlan_tbl_entry_cmd *req)
1325 struct hns3_cmd_desc desc;
1330 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1332 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1334 ret = hns3_cmd_send(hw, &desc, 1);
1336 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1339 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1340 retval = rte_le_to_cpu_16(desc.retval);
1342 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1343 HNS3_MAC_VLAN_REMOVE);
1347 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1349 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1350 struct hns3_mac_vlan_tbl_entry_cmd req;
1351 struct hns3_pf *pf = &hns->pf;
1352 struct hns3_cmd_desc desc;
1353 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1354 uint16_t egress_port = 0;
1358 /* check if mac addr is valid */
1359 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1360 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1362 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1367 memset(&req, 0, sizeof(req));
1370 * In current version VF is not supported when PF is driven by DPDK
1371 * driver, the PF-related vf_id is 0, just need to configure parameters
1375 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1376 HNS3_MAC_EPORT_VFID_S, vf_id);
1378 req.egress_port = rte_cpu_to_le_16(egress_port);
1380 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1383 * Lookup the mac address in the mac_vlan table, and add
1384 * it if the entry is inexistent. Repeated unicast entry
1385 * is not allowed in the mac vlan table.
1387 ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1388 if (ret == -ENOENT) {
1389 if (!hns3_is_umv_space_full(hw)) {
1390 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1392 hns3_update_umv_space(hw, false);
1396 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1401 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1403 /* check if we just hit the duplicate */
1405 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1409 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1416 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1418 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1419 struct rte_ether_addr *addr;
1423 for (i = 0; i < hw->mc_addrs_num; i++) {
1424 addr = &hw->mc_addrs[i];
1425 /* Check if there are duplicate addresses */
1426 if (rte_is_same_ether_addr(addr, mac_addr)) {
1427 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1429 hns3_err(hw, "failed to add mc mac addr, same addrs"
1430 "(%s) is added by the set_mc_mac_addr_list "
1436 ret = hns3_add_mc_addr(hw, mac_addr);
1438 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1440 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1447 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1449 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1452 ret = hns3_remove_mc_addr(hw, mac_addr);
1454 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1456 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1463 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1464 uint32_t idx, __rte_unused uint32_t pool)
1466 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1467 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1470 rte_spinlock_lock(&hw->lock);
1473 * In hns3 network engine adding UC and MC mac address with different
1474 * commands with firmware. We need to determine whether the input
1475 * address is a UC or a MC address to call different commands.
1476 * By the way, it is recommended calling the API function named
1477 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1478 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1479 * may affect the specifications of UC mac addresses.
1481 if (rte_is_multicast_ether_addr(mac_addr))
1482 ret = hns3_add_mc_addr_common(hw, mac_addr);
1484 ret = hns3_add_uc_addr_common(hw, mac_addr);
1487 rte_spinlock_unlock(&hw->lock);
1488 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1490 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1496 hw->mac.default_addr_setted = true;
1497 rte_spinlock_unlock(&hw->lock);
1503 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1505 struct hns3_mac_vlan_tbl_entry_cmd req;
1506 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1509 /* check if mac addr is valid */
1510 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1511 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1513 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1518 memset(&req, 0, sizeof(req));
1519 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1520 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1521 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1522 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1525 hns3_update_umv_space(hw, true);
1531 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1533 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1534 /* index will be checked by upper level rte interface */
1535 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1536 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1539 rte_spinlock_lock(&hw->lock);
1541 if (rte_is_multicast_ether_addr(mac_addr))
1542 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1544 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1545 rte_spinlock_unlock(&hw->lock);
1547 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1549 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1555 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1556 struct rte_ether_addr *mac_addr)
1558 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1559 struct rte_ether_addr *oaddr;
1560 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1561 bool default_addr_setted;
1562 bool rm_succes = false;
1566 * It has been guaranteed that input parameter named mac_addr is valid
1567 * address in the rte layer of DPDK framework.
1569 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1570 default_addr_setted = hw->mac.default_addr_setted;
1571 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1574 rte_spinlock_lock(&hw->lock);
1575 if (default_addr_setted) {
1576 ret = hns3_remove_uc_addr_common(hw, oaddr);
1578 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1580 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1587 ret = hns3_add_uc_addr_common(hw, mac_addr);
1589 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1591 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1592 goto err_add_uc_addr;
1595 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1597 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1598 goto err_pause_addr_cfg;
1601 rte_ether_addr_copy(mac_addr,
1602 (struct rte_ether_addr *)hw->mac.mac_addr);
1603 hw->mac.default_addr_setted = true;
1604 rte_spinlock_unlock(&hw->lock);
1609 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1611 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1614 "Failed to roll back to del setted mac addr(%s): %d",
1620 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1622 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1625 "Failed to restore old uc mac addr(%s): %d",
1627 hw->mac.default_addr_setted = false;
1630 rte_spinlock_unlock(&hw->lock);
1636 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1638 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1639 struct hns3_hw *hw = &hns->hw;
1640 struct rte_ether_addr *addr;
1645 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1646 addr = &hw->data->mac_addrs[i];
1647 if (rte_is_zero_ether_addr(addr))
1649 if (rte_is_multicast_ether_addr(addr))
1650 ret = del ? hns3_remove_mc_addr(hw, addr) :
1651 hns3_add_mc_addr(hw, addr);
1653 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1654 hns3_add_uc_addr_common(hw, addr);
1658 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1660 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1661 "ret = %d.", del ? "remove" : "restore",
1669 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1671 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1675 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1676 word_num = vfid / 32;
1677 bit_num = vfid % 32;
1679 desc[1].data[word_num] &=
1680 rte_cpu_to_le_32(~(1UL << bit_num));
1682 desc[1].data[word_num] |=
1683 rte_cpu_to_le_32(1UL << bit_num);
1685 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1686 bit_num = vfid % 32;
1688 desc[2].data[word_num] &=
1689 rte_cpu_to_le_32(~(1UL << bit_num));
1691 desc[2].data[word_num] |=
1692 rte_cpu_to_le_32(1UL << bit_num);
1697 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1699 struct hns3_mac_vlan_tbl_entry_cmd req;
1700 struct hns3_cmd_desc desc[3];
1701 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1705 /* Check if mac addr is valid */
1706 if (!rte_is_multicast_ether_addr(mac_addr)) {
1707 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1709 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1714 memset(&req, 0, sizeof(req));
1715 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1716 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1717 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1719 /* This mac addr do not exist, add new entry for it */
1720 memset(desc[0].data, 0, sizeof(desc[0].data));
1721 memset(desc[1].data, 0, sizeof(desc[0].data));
1722 memset(desc[2].data, 0, sizeof(desc[0].data));
1726 * In current version VF is not supported when PF is driven by DPDK
1727 * driver, the PF-related vf_id is 0, just need to configure parameters
1731 hns3_update_desc_vfid(desc, vf_id, false);
1732 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1735 hns3_err(hw, "mc mac vlan table is full");
1736 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1738 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1745 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1747 struct hns3_mac_vlan_tbl_entry_cmd req;
1748 struct hns3_cmd_desc desc[3];
1749 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1753 /* Check if mac addr is valid */
1754 if (!rte_is_multicast_ether_addr(mac_addr)) {
1755 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1757 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1762 memset(&req, 0, sizeof(req));
1763 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1764 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1765 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1768 * This mac addr exist, remove this handle's VFID for it.
1769 * In current version VF is not supported when PF is driven by
1770 * DPDK driver, the PF-related vf_id is 0, just need to
1771 * configure parameters for vf_id 0.
1774 hns3_update_desc_vfid(desc, vf_id, true);
1776 /* All the vfid is zero, so need to delete this entry */
1777 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1778 } else if (ret == -ENOENT) {
1779 /* This mac addr doesn't exist. */
1784 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1786 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1793 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1794 struct rte_ether_addr *mc_addr_set,
1795 uint32_t nb_mc_addr)
1797 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1798 struct rte_ether_addr *addr;
1802 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1803 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1804 "invalid. valid range: 0~%d",
1805 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1809 /* Check if input mac addresses are valid */
1810 for (i = 0; i < nb_mc_addr; i++) {
1811 addr = &mc_addr_set[i];
1812 if (!rte_is_multicast_ether_addr(addr)) {
1813 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1816 "failed to set mc mac addr, addr(%s) invalid.",
1821 /* Check if there are duplicate addresses */
1822 for (j = i + 1; j < nb_mc_addr; j++) {
1823 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1824 rte_ether_format_addr(mac_str,
1825 RTE_ETHER_ADDR_FMT_SIZE,
1827 hns3_err(hw, "failed to set mc mac addr, "
1828 "addrs invalid. two same addrs(%s).",
1835 * Check if there are duplicate addresses between mac_addrs
1838 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1839 if (rte_is_same_ether_addr(addr,
1840 &hw->data->mac_addrs[j])) {
1841 rte_ether_format_addr(mac_str,
1842 RTE_ETHER_ADDR_FMT_SIZE,
1844 hns3_err(hw, "failed to set mc mac addr, "
1845 "addrs invalid. addrs(%s) has already "
1846 "configured in mac_addr add API",
1857 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1858 struct rte_ether_addr *mc_addr_set,
1860 struct rte_ether_addr *reserved_addr_list,
1861 int *reserved_addr_num,
1862 struct rte_ether_addr *add_addr_list,
1864 struct rte_ether_addr *rm_addr_list,
1867 struct rte_ether_addr *addr;
1868 int current_addr_num;
1869 int reserved_num = 0;
1877 /* Calculate the mc mac address list that should be removed */
1878 current_addr_num = hw->mc_addrs_num;
1879 for (i = 0; i < current_addr_num; i++) {
1880 addr = &hw->mc_addrs[i];
1882 for (j = 0; j < mc_addr_num; j++) {
1883 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1890 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1893 rte_ether_addr_copy(addr,
1894 &reserved_addr_list[reserved_num]);
1899 /* Calculate the mc mac address list that should be added */
1900 for (i = 0; i < mc_addr_num; i++) {
1901 addr = &mc_addr_set[i];
1903 for (j = 0; j < current_addr_num; j++) {
1904 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1911 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1916 /* Reorder the mc mac address list maintained by driver */
1917 for (i = 0; i < reserved_num; i++)
1918 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1920 for (i = 0; i < rm_num; i++) {
1921 num = reserved_num + i;
1922 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1925 *reserved_addr_num = reserved_num;
1926 *add_addr_num = add_num;
1927 *rm_addr_num = rm_num;
1931 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1932 struct rte_ether_addr *mc_addr_set,
1933 uint32_t nb_mc_addr)
1935 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1936 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1937 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1938 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1939 struct rte_ether_addr *addr;
1940 int reserved_addr_num;
1948 /* Check if input parameters are valid */
1949 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1953 rte_spinlock_lock(&hw->lock);
1956 * Calculate the mc mac address lists those should be removed and be
1957 * added, Reorder the mc mac address list maintained by driver.
1959 mc_addr_num = (int)nb_mc_addr;
1960 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1961 reserved_addr_list, &reserved_addr_num,
1962 add_addr_list, &add_addr_num,
1963 rm_addr_list, &rm_addr_num);
1965 /* Remove mc mac addresses */
1966 for (i = 0; i < rm_addr_num; i++) {
1967 num = rm_addr_num - i - 1;
1968 addr = &rm_addr_list[num];
1969 ret = hns3_remove_mc_addr(hw, addr);
1971 rte_spinlock_unlock(&hw->lock);
1977 /* Add mc mac addresses */
1978 for (i = 0; i < add_addr_num; i++) {
1979 addr = &add_addr_list[i];
1980 ret = hns3_add_mc_addr(hw, addr);
1982 rte_spinlock_unlock(&hw->lock);
1986 num = reserved_addr_num + i;
1987 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1990 rte_spinlock_unlock(&hw->lock);
1996 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1998 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1999 struct hns3_hw *hw = &hns->hw;
2000 struct rte_ether_addr *addr;
2005 for (i = 0; i < hw->mc_addrs_num; i++) {
2006 addr = &hw->mc_addrs[i];
2007 if (!rte_is_multicast_ether_addr(addr))
2010 ret = hns3_remove_mc_addr(hw, addr);
2012 ret = hns3_add_mc_addr(hw, addr);
2015 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2017 hns3_dbg(hw, "%s mc mac addr: %s failed",
2018 del ? "Remove" : "Restore", mac_str);
2025 hns3_check_mq_mode(struct rte_eth_dev *dev)
2027 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2028 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2029 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2030 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2031 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2032 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2037 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2038 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2040 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2041 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2042 "rx_mq_mode = %d", rx_mq_mode);
2046 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2047 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2048 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2049 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2050 rx_mq_mode, tx_mq_mode);
2054 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2055 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2056 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2057 dcb_rx_conf->nb_tcs, pf->tc_max);
2061 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2062 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2063 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2064 "nb_tcs(%d) != %d or %d in rx direction.",
2065 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2069 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2070 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2071 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2075 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2076 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2077 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2078 "is not equal to one in tx direction.",
2079 i, dcb_rx_conf->dcb_tc[i]);
2082 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2083 max_tc = dcb_rx_conf->dcb_tc[i];
2086 num_tc = max_tc + 1;
2087 if (num_tc > dcb_rx_conf->nb_tcs) {
2088 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2089 num_tc, dcb_rx_conf->nb_tcs);
2098 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2100 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2102 if (!hns3_dev_dcb_supported(hw)) {
2103 hns3_err(hw, "this port does not support dcb configurations.");
2107 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2108 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2112 /* Check multiple queue mode */
2113 return hns3_check_mq_mode(dev);
2117 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2118 enum hns3_ring_type queue_type, uint16_t queue_id)
2120 struct hns3_cmd_desc desc;
2121 struct hns3_ctrl_vector_chain_cmd *req =
2122 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2123 enum hns3_cmd_status status;
2124 enum hns3_opcode_type op;
2125 uint16_t tqp_type_and_id = 0;
2130 op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2131 hns3_cmd_setup_basic_desc(&desc, op, false);
2132 req->int_vector_id = vector_id;
2134 if (queue_type == HNS3_RING_TYPE_RX)
2135 gl = HNS3_RING_GL_RX;
2137 gl = HNS3_RING_GL_TX;
2141 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2143 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2144 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2146 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2147 req->int_cause_num = 1;
2148 op_str = mmap ? "Map" : "Unmap";
2149 status = hns3_cmd_send(hw, &desc, 1);
2151 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2152 op_str, queue_id, req->int_vector_id, status);
2160 hns3_init_ring_with_vector(struct hns3_hw *hw)
2167 * In hns3 network engine, vector 0 is always the misc interrupt of this
2168 * function, vector 1~N can be used respectively for the queues of the
2169 * function. Tx and Rx queues with the same number share the interrupt
2170 * vector. In the initialization clearing the all hardware mapping
2171 * relationship configurations between queues and interrupt vectors is
2172 * needed, so some error caused by the residual configurations, such as
2173 * the unexpected Tx interrupt, can be avoid. Because of the hardware
2174 * constraints in hns3 hardware engine, we have to implement clearing
2175 * the mapping relationship configurations by binding all queues to the
2176 * last interrupt vector and reserving the last interrupt vector. This
2177 * method results in a decrease of the maximum queues when upper
2178 * applications call the rte_eth_dev_configure API function to enable
2181 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2182 hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
2183 for (i = 0; i < hw->intr_tqps_num; i++) {
2185 * Set gap limiter and rate limiter configuration of queue's
2188 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2189 HNS3_TQP_INTR_GL_DEFAULT);
2190 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2191 HNS3_TQP_INTR_GL_DEFAULT);
2192 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2194 ret = hns3_bind_ring_with_vector(hw, vec, false,
2195 HNS3_RING_TYPE_TX, i);
2197 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2198 "vector: %d, ret=%d", i, vec, ret);
2202 ret = hns3_bind_ring_with_vector(hw, vec, false,
2203 HNS3_RING_TYPE_RX, i);
2205 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2206 "vector: %d, ret=%d", i, vec, ret);
2215 hns3_dev_configure(struct rte_eth_dev *dev)
2217 struct hns3_adapter *hns = dev->data->dev_private;
2218 struct rte_eth_conf *conf = &dev->data->dev_conf;
2219 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2220 struct hns3_hw *hw = &hns->hw;
2221 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2222 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2223 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2224 struct rte_eth_rss_conf rss_conf;
2229 * Hardware does not support individually enable/disable/reset the Tx or
2230 * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2231 * and Rx queues at the same time. When the numbers of Tx queues
2232 * allocated by upper applications are not equal to the numbers of Rx
2233 * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2234 * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2235 * these fake queues are imperceptible, and can not be used by upper
2238 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2240 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2244 hw->adapter_state = HNS3_NIC_CONFIGURING;
2245 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2246 hns3_err(hw, "setting link speed/duplex not supported");
2251 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2252 ret = hns3_check_dcb_cfg(dev);
2257 /* When RSS is not configured, redirect the packet queue 0 */
2258 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2259 rss_conf = conf->rx_adv_conf.rss_conf;
2260 if (rss_conf.rss_key == NULL) {
2261 rss_conf.rss_key = rss_cfg->key;
2262 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2265 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2271 * If jumbo frames are enabled, MTU needs to be refreshed
2272 * according to the maximum RX packet length.
2274 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2276 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2277 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2278 * can safely assign to "uint16_t" type variable.
2280 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2281 ret = hns3_dev_mtu_set(dev, mtu);
2284 dev->data->mtu = mtu;
2287 ret = hns3_dev_configure_vlan(dev);
2291 hw->adapter_state = HNS3_NIC_CONFIGURED;
2296 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2297 hw->adapter_state = HNS3_NIC_INITIALIZED;
2303 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2305 struct hns3_config_max_frm_size_cmd *req;
2306 struct hns3_cmd_desc desc;
2308 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2310 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2311 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2312 req->min_frm_size = RTE_ETHER_MIN_LEN;
2314 return hns3_cmd_send(hw, &desc, 1);
2318 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2322 ret = hns3_set_mac_mtu(hw, mps);
2324 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2328 ret = hns3_buffer_alloc(hw);
2330 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2336 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2338 struct hns3_adapter *hns = dev->data->dev_private;
2339 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2340 struct hns3_hw *hw = &hns->hw;
2341 bool is_jumbo_frame;
2344 if (dev->data->dev_started) {
2345 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2346 "before configuration", dev->data->port_id);
2350 rte_spinlock_lock(&hw->lock);
2351 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2352 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2355 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2356 * assign to "uint16_t" type variable.
2358 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2360 rte_spinlock_unlock(&hw->lock);
2361 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2362 dev->data->port_id, mtu, ret);
2365 hns->pf.mps = (uint16_t)frame_size;
2367 dev->data->dev_conf.rxmode.offloads |=
2368 DEV_RX_OFFLOAD_JUMBO_FRAME;
2370 dev->data->dev_conf.rxmode.offloads &=
2371 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2372 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2373 rte_spinlock_unlock(&hw->lock);
2379 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2381 struct hns3_adapter *hns = eth_dev->data->dev_private;
2382 struct hns3_hw *hw = &hns->hw;
2383 uint16_t queue_num = hw->tqps_num;
2386 * In interrupt mode, 'max_rx_queues' is set based on the number of
2387 * MSI-X interrupt resources of the hardware.
2389 if (hw->data->dev_conf.intr_conf.rxq == 1)
2390 queue_num = hw->intr_tqps_num;
2392 info->max_rx_queues = queue_num;
2393 info->max_tx_queues = hw->tqps_num;
2394 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2395 info->min_rx_bufsize = hw->rx_buf_len;
2396 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2397 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2398 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2399 DEV_RX_OFFLOAD_TCP_CKSUM |
2400 DEV_RX_OFFLOAD_UDP_CKSUM |
2401 DEV_RX_OFFLOAD_SCTP_CKSUM |
2402 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2403 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2404 DEV_RX_OFFLOAD_KEEP_CRC |
2405 DEV_RX_OFFLOAD_SCATTER |
2406 DEV_RX_OFFLOAD_VLAN_STRIP |
2407 DEV_RX_OFFLOAD_QINQ_STRIP |
2408 DEV_RX_OFFLOAD_VLAN_FILTER |
2409 DEV_RX_OFFLOAD_VLAN_EXTEND |
2410 DEV_RX_OFFLOAD_JUMBO_FRAME);
2411 info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2412 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2413 DEV_TX_OFFLOAD_IPV4_CKSUM |
2414 DEV_TX_OFFLOAD_TCP_CKSUM |
2415 DEV_TX_OFFLOAD_UDP_CKSUM |
2416 DEV_TX_OFFLOAD_SCTP_CKSUM |
2417 DEV_TX_OFFLOAD_VLAN_INSERT |
2418 DEV_TX_OFFLOAD_QINQ_INSERT |
2419 DEV_TX_OFFLOAD_MULTI_SEGS |
2420 DEV_TX_OFFLOAD_TCP_TSO |
2421 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2422 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2423 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2424 info->tx_queue_offload_capa);
2426 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2427 .nb_max = HNS3_MAX_RING_DESC,
2428 .nb_min = HNS3_MIN_RING_DESC,
2429 .nb_align = HNS3_ALIGN_RING_DESC,
2432 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2433 .nb_max = HNS3_MAX_RING_DESC,
2434 .nb_min = HNS3_MIN_RING_DESC,
2435 .nb_align = HNS3_ALIGN_RING_DESC,
2438 info->vmdq_queue_num = 0;
2440 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2441 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2442 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2444 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2445 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2446 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2447 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2448 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2449 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2455 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2458 struct hns3_adapter *hns = eth_dev->data->dev_private;
2459 struct hns3_hw *hw = &hns->hw;
2462 ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2463 ret += 1; /* add the size of '\0' */
2464 if (fw_size < (uint32_t)ret)
2471 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2472 __rte_unused int wait_to_complete)
2474 struct hns3_adapter *hns = eth_dev->data->dev_private;
2475 struct hns3_hw *hw = &hns->hw;
2476 struct hns3_mac *mac = &hw->mac;
2477 struct rte_eth_link new_link;
2479 if (!hns3_is_reset_pending(hns)) {
2480 hns3_update_speed_duplex(eth_dev);
2481 hns3_update_link_status(hw);
2484 memset(&new_link, 0, sizeof(new_link));
2485 switch (mac->link_speed) {
2486 case ETH_SPEED_NUM_10M:
2487 case ETH_SPEED_NUM_100M:
2488 case ETH_SPEED_NUM_1G:
2489 case ETH_SPEED_NUM_10G:
2490 case ETH_SPEED_NUM_25G:
2491 case ETH_SPEED_NUM_40G:
2492 case ETH_SPEED_NUM_50G:
2493 case ETH_SPEED_NUM_100G:
2494 new_link.link_speed = mac->link_speed;
2497 new_link.link_speed = ETH_SPEED_NUM_100M;
2501 new_link.link_duplex = mac->link_duplex;
2502 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2503 new_link.link_autoneg =
2504 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2506 return rte_eth_linkstatus_set(eth_dev, &new_link);
2510 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2512 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2513 struct hns3_pf *pf = &hns->pf;
2515 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2518 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2524 hns3_query_function_status(struct hns3_hw *hw)
2526 #define HNS3_QUERY_MAX_CNT 10
2527 #define HNS3_QUERY_SLEEP_MSCOEND 1
2528 struct hns3_func_status_cmd *req;
2529 struct hns3_cmd_desc desc;
2533 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2534 req = (struct hns3_func_status_cmd *)desc.data;
2537 ret = hns3_cmd_send(hw, &desc, 1);
2539 PMD_INIT_LOG(ERR, "query function status failed %d",
2544 /* Check pf reset is done */
2548 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2549 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2551 return hns3_parse_func_status(hw, req);
2555 hns3_query_pf_resource(struct hns3_hw *hw)
2557 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2558 struct hns3_pf *pf = &hns->pf;
2559 struct hns3_pf_res_cmd *req;
2560 struct hns3_cmd_desc desc;
2564 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2565 ret = hns3_cmd_send(hw, &desc, 1);
2567 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2571 req = (struct hns3_pf_res_cmd *)desc.data;
2572 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2573 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2574 hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2575 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2577 if (req->tx_buf_size)
2579 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2581 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2583 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2585 if (req->dv_buf_size)
2587 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2589 pf->dv_buf_size = HNS3_DEFAULT_DV;
2591 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2593 num_msi = hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2594 HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2595 hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
2601 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2603 struct hns3_cfg_param_cmd *req;
2604 uint64_t mac_addr_tmp_high;
2605 uint64_t mac_addr_tmp;
2608 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2610 /* get the configuration */
2611 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2612 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2613 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2614 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2615 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2616 HNS3_CFG_TQP_DESC_N_M,
2617 HNS3_CFG_TQP_DESC_N_S);
2619 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2620 HNS3_CFG_PHY_ADDR_M,
2621 HNS3_CFG_PHY_ADDR_S);
2622 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2623 HNS3_CFG_MEDIA_TP_M,
2624 HNS3_CFG_MEDIA_TP_S);
2625 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2626 HNS3_CFG_RX_BUF_LEN_M,
2627 HNS3_CFG_RX_BUF_LEN_S);
2628 /* get mac address */
2629 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2630 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2631 HNS3_CFG_MAC_ADDR_H_M,
2632 HNS3_CFG_MAC_ADDR_H_S);
2634 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2636 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2637 HNS3_CFG_DEFAULT_SPEED_M,
2638 HNS3_CFG_DEFAULT_SPEED_S);
2639 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2640 HNS3_CFG_RSS_SIZE_M,
2641 HNS3_CFG_RSS_SIZE_S);
2643 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2644 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2646 req = (struct hns3_cfg_param_cmd *)desc[1].data;
2647 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2649 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2650 HNS3_CFG_SPEED_ABILITY_M,
2651 HNS3_CFG_SPEED_ABILITY_S);
2652 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2653 HNS3_CFG_UMV_TBL_SPACE_M,
2654 HNS3_CFG_UMV_TBL_SPACE_S);
2655 if (!cfg->umv_space)
2656 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2659 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2660 * @hw: pointer to struct hns3_hw
2661 * @hcfg: the config structure to be getted
2664 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2666 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2667 struct hns3_cfg_param_cmd *req;
2672 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2674 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2675 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2677 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2678 i * HNS3_CFG_RD_LEN_BYTES);
2679 /* Len should be divided by 4 when send to hardware */
2680 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2681 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2682 req->offset = rte_cpu_to_le_32(offset);
2685 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2687 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2691 hns3_parse_cfg(hcfg, desc);
2697 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2699 switch (speed_cmd) {
2700 case HNS3_CFG_SPEED_10M:
2701 *speed = ETH_SPEED_NUM_10M;
2703 case HNS3_CFG_SPEED_100M:
2704 *speed = ETH_SPEED_NUM_100M;
2706 case HNS3_CFG_SPEED_1G:
2707 *speed = ETH_SPEED_NUM_1G;
2709 case HNS3_CFG_SPEED_10G:
2710 *speed = ETH_SPEED_NUM_10G;
2712 case HNS3_CFG_SPEED_25G:
2713 *speed = ETH_SPEED_NUM_25G;
2715 case HNS3_CFG_SPEED_40G:
2716 *speed = ETH_SPEED_NUM_40G;
2718 case HNS3_CFG_SPEED_50G:
2719 *speed = ETH_SPEED_NUM_50G;
2721 case HNS3_CFG_SPEED_100G:
2722 *speed = ETH_SPEED_NUM_100G;
2732 hns3_get_board_configuration(struct hns3_hw *hw)
2734 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2735 struct hns3_pf *pf = &hns->pf;
2736 struct hns3_cfg cfg;
2739 ret = hns3_get_board_cfg(hw, &cfg);
2741 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2745 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2746 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2750 hw->mac.media_type = cfg.media_type;
2751 hw->rss_size_max = cfg.rss_size_max;
2752 hw->rss_dis_flag = false;
2753 hw->rx_buf_len = cfg.rx_buf_len;
2754 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2755 hw->mac.phy_addr = cfg.phy_addr;
2756 hw->mac.default_addr_setted = false;
2757 hw->num_tx_desc = cfg.tqp_desc_num;
2758 hw->num_rx_desc = cfg.tqp_desc_num;
2759 hw->dcb_info.num_pg = 1;
2760 hw->dcb_info.hw_pfc_map = 0;
2762 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2764 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2765 cfg.default_speed, ret);
2769 pf->tc_max = cfg.tc_num;
2770 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2771 PMD_INIT_LOG(WARNING,
2772 "Get TC num(%u) from flash, set TC num to 1",
2777 /* Dev does not support DCB */
2778 if (!hns3_dev_dcb_supported(hw)) {
2782 pf->pfc_max = pf->tc_max;
2784 hw->dcb_info.num_tc = 1;
2785 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2786 hw->tqps_num / hw->dcb_info.num_tc);
2787 hns3_set_bit(hw->hw_tc_map, 0, 1);
2788 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2790 pf->wanted_umv_size = cfg.umv_space;
2796 hns3_get_configuration(struct hns3_hw *hw)
2800 ret = hns3_query_function_status(hw);
2802 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2806 /* Get pf resource */
2807 ret = hns3_query_pf_resource(hw);
2809 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2813 ret = hns3_get_board_configuration(hw);
2815 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2821 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2822 uint16_t tqp_vid, bool is_pf)
2824 struct hns3_tqp_map_cmd *req;
2825 struct hns3_cmd_desc desc;
2828 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2830 req = (struct hns3_tqp_map_cmd *)desc.data;
2831 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2832 req->tqp_vf = func_id;
2833 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2835 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2836 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2838 ret = hns3_cmd_send(hw, &desc, 1);
2840 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2846 hns3_map_tqp(struct hns3_hw *hw)
2848 uint16_t tqps_num = hw->total_tqps_num;
2857 * In current version VF is not supported when PF is driven by DPDK
2858 * driver, so we allocate tqps to PF as much as possible.
2861 num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2862 for (func_id = 0; func_id < num; func_id++) {
2863 is_pf = func_id == 0 ? true : false;
2865 i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2866 ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2877 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2879 struct hns3_config_mac_speed_dup_cmd *req;
2880 struct hns3_cmd_desc desc;
2883 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2885 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2887 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2890 case ETH_SPEED_NUM_10M:
2891 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2892 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2894 case ETH_SPEED_NUM_100M:
2895 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2896 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2898 case ETH_SPEED_NUM_1G:
2899 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2900 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2902 case ETH_SPEED_NUM_10G:
2903 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2904 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2906 case ETH_SPEED_NUM_25G:
2907 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2908 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2910 case ETH_SPEED_NUM_40G:
2911 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2912 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2914 case ETH_SPEED_NUM_50G:
2915 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2916 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2918 case ETH_SPEED_NUM_100G:
2919 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2920 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2923 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2927 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2929 ret = hns3_cmd_send(hw, &desc, 1);
2931 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2937 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2939 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2940 struct hns3_pf *pf = &hns->pf;
2941 struct hns3_priv_buf *priv;
2942 uint32_t i, total_size;
2944 total_size = pf->pkt_buf_size;
2946 /* alloc tx buffer for all enabled tc */
2947 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2948 priv = &buf_alloc->priv_buf[i];
2950 if (hw->hw_tc_map & BIT(i)) {
2951 if (total_size < pf->tx_buf_size)
2954 priv->tx_buf_size = pf->tx_buf_size;
2956 priv->tx_buf_size = 0;
2958 total_size -= priv->tx_buf_size;
2965 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2967 /* TX buffer size is unit by 128 byte */
2968 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
2969 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
2970 struct hns3_tx_buff_alloc_cmd *req;
2971 struct hns3_cmd_desc desc;
2976 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2978 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2979 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2980 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2982 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2983 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2984 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2987 ret = hns3_cmd_send(hw, &desc, 1);
2989 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2995 hns3_get_tc_num(struct hns3_hw *hw)
3000 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3001 if (hw->hw_tc_map & BIT(i))
3007 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3009 struct hns3_priv_buf *priv;
3010 uint32_t rx_priv = 0;
3013 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3014 priv = &buf_alloc->priv_buf[i];
3016 rx_priv += priv->buf_size;
3022 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3024 uint32_t total_tx_size = 0;
3027 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3028 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3030 return total_tx_size;
3033 /* Get the number of pfc enabled TCs, which have private buffer */
3035 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3037 struct hns3_priv_buf *priv;
3041 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3042 priv = &buf_alloc->priv_buf[i];
3043 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3050 /* Get the number of pfc disabled TCs, which have private buffer */
3052 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3053 struct hns3_pkt_buf_alloc *buf_alloc)
3055 struct hns3_priv_buf *priv;
3059 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3060 priv = &buf_alloc->priv_buf[i];
3061 if (hw->hw_tc_map & BIT(i) &&
3062 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3070 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3073 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3074 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3075 struct hns3_pf *pf = &hns->pf;
3076 uint32_t shared_buf, aligned_mps;
3081 tc_num = hns3_get_tc_num(hw);
3082 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3084 if (hns3_dev_dcb_supported(hw))
3085 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3088 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3091 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3092 shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3093 HNS3_BUF_SIZE_UNIT);
3095 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3096 if (rx_all < rx_priv + shared_std)
3099 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3100 buf_alloc->s_buf.buf_size = shared_buf;
3101 if (hns3_dev_dcb_supported(hw)) {
3102 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3103 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3104 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3105 HNS3_BUF_SIZE_UNIT);
3107 buf_alloc->s_buf.self.high =
3108 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3109 buf_alloc->s_buf.self.low = aligned_mps;
3112 if (hns3_dev_dcb_supported(hw)) {
3113 hi_thrd = shared_buf - pf->dv_buf_size;
3115 if (tc_num <= NEED_RESERVE_TC_NUM)
3116 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3120 hi_thrd = hi_thrd / tc_num;
3122 hi_thrd = max_t(uint32_t, hi_thrd,
3123 HNS3_BUF_MUL_BY * aligned_mps);
3124 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3125 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3127 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3128 lo_thrd = aligned_mps;
3131 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3132 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3133 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3140 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3141 struct hns3_pkt_buf_alloc *buf_alloc)
3143 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3144 struct hns3_pf *pf = &hns->pf;
3145 struct hns3_priv_buf *priv;
3146 uint32_t aligned_mps;
3150 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3151 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3153 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3154 priv = &buf_alloc->priv_buf[i];
3161 if (!(hw->hw_tc_map & BIT(i)))
3165 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3166 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3167 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3168 HNS3_BUF_SIZE_UNIT);
3171 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3175 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3178 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3182 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3183 struct hns3_pkt_buf_alloc *buf_alloc)
3185 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3186 struct hns3_pf *pf = &hns->pf;
3187 struct hns3_priv_buf *priv;
3188 int no_pfc_priv_num;
3193 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3194 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3196 /* let the last to be cleared first */
3197 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3198 priv = &buf_alloc->priv_buf[i];
3199 mask = BIT((uint8_t)i);
3201 if (hw->hw_tc_map & mask &&
3202 !(hw->dcb_info.hw_pfc_map & mask)) {
3203 /* Clear the no pfc TC private buffer */
3211 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3212 no_pfc_priv_num == 0)
3216 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3220 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3221 struct hns3_pkt_buf_alloc *buf_alloc)
3223 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3224 struct hns3_pf *pf = &hns->pf;
3225 struct hns3_priv_buf *priv;
3231 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3232 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3234 /* let the last to be cleared first */
3235 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3236 priv = &buf_alloc->priv_buf[i];
3237 mask = BIT((uint8_t)i);
3239 if (hw->hw_tc_map & mask &&
3240 hw->dcb_info.hw_pfc_map & mask) {
3241 /* Reduce the number of pfc TC with private buffer */
3248 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3253 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3257 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3258 struct hns3_pkt_buf_alloc *buf_alloc)
3260 #define COMPENSATE_BUFFER 0x3C00
3261 #define COMPENSATE_HALF_MPS_NUM 5
3262 #define PRIV_WL_GAP 0x1800
3263 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3264 struct hns3_pf *pf = &hns->pf;
3265 uint32_t tc_num = hns3_get_tc_num(hw);
3266 uint32_t half_mps = pf->mps >> 1;
3267 struct hns3_priv_buf *priv;
3268 uint32_t min_rx_priv;
3272 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3274 rx_priv = rx_priv / tc_num;
3276 if (tc_num <= NEED_RESERVE_TC_NUM)
3277 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3280 * Minimum value of private buffer in rx direction (min_rx_priv) is
3281 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3282 * buffer if rx_priv is greater than min_rx_priv.
3284 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3285 COMPENSATE_HALF_MPS_NUM * half_mps;
3286 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3287 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3289 if (rx_priv < min_rx_priv)
3292 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3293 priv = &buf_alloc->priv_buf[i];
3300 if (!(hw->hw_tc_map & BIT(i)))
3304 priv->buf_size = rx_priv;
3305 priv->wl.high = rx_priv - pf->dv_buf_size;
3306 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3309 buf_alloc->s_buf.buf_size = 0;
3315 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3316 * @hw: pointer to struct hns3_hw
3317 * @buf_alloc: pointer to buffer calculation data
3318 * @return: 0: calculate sucessful, negative: fail
3321 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3323 /* When DCB is not supported, rx private buffer is not allocated. */
3324 if (!hns3_dev_dcb_supported(hw)) {
3325 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3326 struct hns3_pf *pf = &hns->pf;
3327 uint32_t rx_all = pf->pkt_buf_size;
3329 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3330 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3337 * Try to allocate privated packet buffer for all TCs without share
3340 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3344 * Try to allocate privated packet buffer for all TCs with share
3347 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3351 * For different application scenes, the enabled port number, TC number
3352 * and no_drop TC number are different. In order to obtain the better
3353 * performance, software could allocate the buffer size and configure
3354 * the waterline by tring to decrease the private buffer size according
3355 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3358 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3361 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3364 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3371 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3373 struct hns3_rx_priv_buff_cmd *req;
3374 struct hns3_cmd_desc desc;
3379 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3380 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3382 /* Alloc private buffer TCs */
3383 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3384 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3387 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3388 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3391 buf_size = buf_alloc->s_buf.buf_size;
3392 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3393 (1 << HNS3_TC0_PRI_BUF_EN_B));
3395 ret = hns3_cmd_send(hw, &desc, 1);
3397 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3403 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3405 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3406 struct hns3_rx_priv_wl_buf *req;
3407 struct hns3_priv_buf *priv;
3408 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3412 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3413 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3415 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3417 /* The first descriptor set the NEXT bit to 1 */
3419 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3421 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3423 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3424 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3426 priv = &buf_alloc->priv_buf[idx];
3427 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3429 req->tc_wl[j].high |=
3430 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3431 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3433 req->tc_wl[j].low |=
3434 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3438 /* Send 2 descriptor at one time */
3439 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3441 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3447 hns3_common_thrd_config(struct hns3_hw *hw,
3448 struct hns3_pkt_buf_alloc *buf_alloc)
3450 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3451 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3452 struct hns3_rx_com_thrd *req;
3453 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3454 struct hns3_tc_thrd *tc;
3459 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3460 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3462 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3464 /* The first descriptor set the NEXT bit to 1 */
3466 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3468 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3470 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3471 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3472 tc = &s_buf->tc_thrd[tc_idx];
3474 req->com_thrd[j].high =
3475 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3476 req->com_thrd[j].high |=
3477 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3478 req->com_thrd[j].low =
3479 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3480 req->com_thrd[j].low |=
3481 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3485 /* Send 2 descriptors at one time */
3486 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3488 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3494 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3496 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3497 struct hns3_rx_com_wl *req;
3498 struct hns3_cmd_desc desc;
3501 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3503 req = (struct hns3_rx_com_wl *)desc.data;
3504 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3505 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3507 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3508 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3510 ret = hns3_cmd_send(hw, &desc, 1);
3512 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3518 hns3_buffer_alloc(struct hns3_hw *hw)
3520 struct hns3_pkt_buf_alloc pkt_buf;
3523 memset(&pkt_buf, 0, sizeof(pkt_buf));
3524 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3527 "could not calc tx buffer size for all TCs %d",
3532 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3534 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3538 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3541 "could not calc rx priv buffer size for all TCs %d",
3546 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3548 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3552 if (hns3_dev_dcb_supported(hw)) {
3553 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3556 "could not configure rx private waterline %d",
3561 ret = hns3_common_thrd_config(hw, &pkt_buf);
3564 "could not configure common threshold %d",
3570 ret = hns3_common_wl_config(hw, &pkt_buf);
3572 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3579 hns3_mac_init(struct hns3_hw *hw)
3581 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3582 struct hns3_mac *mac = &hw->mac;
3583 struct hns3_pf *pf = &hns->pf;
3586 pf->support_sfp_query = true;
3587 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3588 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3590 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3594 mac->link_status = ETH_LINK_DOWN;
3596 return hns3_config_mtu(hw, pf->mps);
3600 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3602 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
3603 #define HNS3_ETHERTYPE_ALREADY_ADD 1
3604 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
3605 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
3610 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3615 switch (resp_code) {
3616 case HNS3_ETHERTYPE_SUCCESS_ADD:
3617 case HNS3_ETHERTYPE_ALREADY_ADD:
3620 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3622 "add mac ethertype failed for manager table overflow.");
3623 return_status = -EIO;
3625 case HNS3_ETHERTYPE_KEY_CONFLICT:
3626 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3627 return_status = -EIO;
3631 "add mac ethertype failed for undefined, code=%d.",
3633 return_status = -EIO;
3637 return return_status;
3641 hns3_add_mgr_tbl(struct hns3_hw *hw,
3642 const struct hns3_mac_mgr_tbl_entry_cmd *req)
3644 struct hns3_cmd_desc desc;
3649 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3650 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3652 ret = hns3_cmd_send(hw, &desc, 1);
3655 "add mac ethertype failed for cmd_send, ret =%d.",
3660 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3661 retval = rte_le_to_cpu_16(desc.retval);
3663 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3667 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3668 int *table_item_num)
3670 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3673 * In current version, we add one item in management table as below:
3674 * 0x0180C200000E -- LLDP MC address
3677 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3678 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3679 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3680 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3681 tbl->i_port_bitmap = 0x1;
3682 *table_item_num = 1;
3686 hns3_init_mgr_tbl(struct hns3_hw *hw)
3688 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
3689 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3694 memset(mgr_table, 0, sizeof(mgr_table));
3695 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3696 for (i = 0; i < table_item_num; i++) {
3697 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3699 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3709 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3710 bool en_mc, bool en_bc, int vport_id)
3715 memset(param, 0, sizeof(struct hns3_promisc_param));
3717 param->enable = HNS3_PROMISC_EN_UC;
3719 param->enable |= HNS3_PROMISC_EN_MC;
3721 param->enable |= HNS3_PROMISC_EN_BC;
3722 param->vf_id = vport_id;
3726 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3728 struct hns3_promisc_cfg_cmd *req;
3729 struct hns3_cmd_desc desc;
3732 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3734 req = (struct hns3_promisc_cfg_cmd *)desc.data;
3735 req->vf_id = param->vf_id;
3736 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3737 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3739 ret = hns3_cmd_send(hw, &desc, 1);
3741 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3747 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3749 struct hns3_promisc_param param;
3750 bool en_bc_pmc = true;
3754 * In current version VF is not supported when PF is driven by DPDK
3755 * driver, the PF-related vf_id is 0, just need to configure parameters
3760 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3761 return hns3_cmd_set_promisc_mode(hw, ¶m);
3765 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3767 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3768 struct hns3_pf *pf = &hns->pf;
3769 struct hns3_promisc_param param;
3773 /* func_id 0 is denoted PF, the VFs start from 1 */
3774 for (func_id = 1; func_id < pf->func_num; func_id++) {
3775 hns3_promisc_param_init(¶m, false, false, false, func_id);
3776 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
3785 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3787 struct hns3_adapter *hns = dev->data->dev_private;
3788 struct hns3_hw *hw = &hns->hw;
3791 rte_spinlock_lock(&hw->lock);
3792 ret = hns3_set_promisc_mode(hw, true, true);
3793 rte_spinlock_unlock(&hw->lock);
3795 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
3802 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3804 bool allmulti = dev->data->all_multicast ? true : false;
3805 struct hns3_adapter *hns = dev->data->dev_private;
3806 struct hns3_hw *hw = &hns->hw;
3809 /* If now in all_multicast mode, must remain in all_multicast mode. */
3810 rte_spinlock_lock(&hw->lock);
3811 ret = hns3_set_promisc_mode(hw, false, allmulti);
3812 rte_spinlock_unlock(&hw->lock);
3814 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
3821 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3823 struct hns3_adapter *hns = dev->data->dev_private;
3824 struct hns3_hw *hw = &hns->hw;
3827 if (dev->data->promiscuous)
3830 rte_spinlock_lock(&hw->lock);
3831 ret = hns3_set_promisc_mode(hw, false, true);
3832 rte_spinlock_unlock(&hw->lock);
3834 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
3841 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3843 struct hns3_adapter *hns = dev->data->dev_private;
3844 struct hns3_hw *hw = &hns->hw;
3847 /* If now in promiscuous mode, must remain in all_multicast mode. */
3848 if (dev->data->promiscuous)
3851 rte_spinlock_lock(&hw->lock);
3852 ret = hns3_set_promisc_mode(hw, false, false);
3853 rte_spinlock_unlock(&hw->lock);
3855 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
3862 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3864 struct hns3_hw *hw = &hns->hw;
3865 bool allmulti = hw->data->all_multicast ? true : false;
3867 if (hw->data->promiscuous)
3868 return hns3_set_promisc_mode(hw, true, true);
3870 return hns3_set_promisc_mode(hw, false, allmulti);
3874 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3876 struct hns3_sfp_speed_cmd *resp;
3877 struct hns3_cmd_desc desc;
3880 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3881 resp = (struct hns3_sfp_speed_cmd *)desc.data;
3882 ret = hns3_cmd_send(hw, &desc, 1);
3883 if (ret == -EOPNOTSUPP) {
3884 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3887 hns3_err(hw, "get sfp speed failed %d", ret);
3891 *speed = resp->sfp_speed;
3897 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3899 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3900 duplex = ETH_LINK_FULL_DUPLEX;
3906 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3908 struct hns3_mac *mac = &hw->mac;
3911 duplex = hns3_check_speed_dup(duplex, speed);
3912 if (mac->link_speed == speed && mac->link_duplex == duplex)
3915 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3919 mac->link_speed = speed;
3920 mac->link_duplex = duplex;
3926 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3928 struct hns3_adapter *hns = eth_dev->data->dev_private;
3929 struct hns3_hw *hw = &hns->hw;
3930 struct hns3_pf *pf = &hns->pf;
3934 /* If IMP do not support get SFP/qSFP speed, return directly */
3935 if (!pf->support_sfp_query)
3938 ret = hns3_get_sfp_speed(hw, &speed);
3939 if (ret == -EOPNOTSUPP) {
3940 pf->support_sfp_query = false;
3945 if (speed == ETH_SPEED_NUM_NONE)
3946 return 0; /* do nothing if no SFP */
3948 /* Config full duplex for SFP */
3949 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3953 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3955 struct hns3_config_mac_mode_cmd *req;
3956 struct hns3_cmd_desc desc;
3957 uint32_t loop_en = 0;
3961 req = (struct hns3_config_mac_mode_cmd *)desc.data;
3963 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3966 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3967 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3968 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3969 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3970 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3971 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3972 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3973 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3974 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3975 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3976 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3977 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3978 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3979 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3980 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3982 ret = hns3_cmd_send(hw, &desc, 1);
3984 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3990 hns3_get_mac_link_status(struct hns3_hw *hw)
3992 struct hns3_link_status_cmd *req;
3993 struct hns3_cmd_desc desc;
3997 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3998 ret = hns3_cmd_send(hw, &desc, 1);
4000 hns3_err(hw, "get link status cmd failed %d", ret);
4001 return ETH_LINK_DOWN;
4004 req = (struct hns3_link_status_cmd *)desc.data;
4005 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4007 return !!link_status;
4011 hns3_update_link_status(struct hns3_hw *hw)
4015 state = hns3_get_mac_link_status(hw);
4016 if (state != hw->mac.link_status) {
4017 hw->mac.link_status = state;
4018 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4023 hns3_service_handler(void *param)
4025 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4026 struct hns3_adapter *hns = eth_dev->data->dev_private;
4027 struct hns3_hw *hw = &hns->hw;
4029 if (!hns3_is_reset_pending(hns)) {
4030 hns3_update_speed_duplex(eth_dev);
4031 hns3_update_link_status(hw);
4033 hns3_warn(hw, "Cancel the query when reset is pending");
4035 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4039 hns3_init_hardware(struct hns3_adapter *hns)
4041 struct hns3_hw *hw = &hns->hw;
4044 ret = hns3_map_tqp(hw);
4046 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4050 ret = hns3_init_umv_space(hw);
4052 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4056 ret = hns3_mac_init(hw);
4058 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4062 ret = hns3_init_mgr_tbl(hw);
4064 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4068 ret = hns3_set_promisc_mode(hw, false, false);
4070 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
4074 ret = hns3_clear_all_vfs_promisc_mode(hw);
4076 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
4081 ret = hns3_init_vlan_config(hns);
4083 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4087 ret = hns3_dcb_init(hw);
4089 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4093 ret = hns3_init_fd_config(hns);
4095 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4099 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4101 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4105 ret = hns3_config_gro(hw, false);
4107 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4113 hns3_uninit_umv_space(hw);
4118 hns3_init_pf(struct rte_eth_dev *eth_dev)
4120 struct rte_device *dev = eth_dev->device;
4121 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4122 struct hns3_adapter *hns = eth_dev->data->dev_private;
4123 struct hns3_hw *hw = &hns->hw;
4126 PMD_INIT_FUNC_TRACE();
4128 /* Get hardware io base address from pcie BAR2 IO space */
4129 hw->io_base = pci_dev->mem_resource[2].addr;
4131 /* Firmware command queue initialize */
4132 ret = hns3_cmd_init_queue(hw);
4134 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4135 goto err_cmd_init_queue;
4138 hns3_clear_all_event_cause(hw);
4140 /* Firmware command initialize */
4141 ret = hns3_cmd_init(hw);
4143 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4147 ret = rte_intr_callback_register(&pci_dev->intr_handle,
4148 hns3_interrupt_handler,
4151 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4152 goto err_intr_callback_register;
4155 /* Enable interrupt */
4156 rte_intr_enable(&pci_dev->intr_handle);
4157 hns3_pf_enable_irq0(hw);
4159 /* Get configuration */
4160 ret = hns3_get_configuration(hw);
4162 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4163 goto err_get_config;
4166 ret = hns3_init_hardware(hns);
4168 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4169 goto err_get_config;
4172 /* Initialize flow director filter list & hash */
4173 ret = hns3_fdir_filter_init(hns);
4175 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4179 hns3_set_default_rss_args(hw);
4181 ret = hns3_enable_hw_error_intr(hns, true);
4183 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4189 * In the initialization clearing the all hardware mapping relationship
4190 * configurations between queues and interrupt vectors is needed, so
4191 * some error caused by the residual configurations, such as the
4192 * unexpected interrupt, can be avoid.
4194 ret = hns3_init_ring_with_vector(hw);
4201 hns3_fdir_filter_uninit(hns);
4203 hns3_uninit_umv_space(hw);
4206 hns3_pf_disable_irq0(hw);
4207 rte_intr_disable(&pci_dev->intr_handle);
4208 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4210 err_intr_callback_register:
4212 hns3_cmd_uninit(hw);
4213 hns3_cmd_destroy_queue(hw);
4221 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4223 struct hns3_adapter *hns = eth_dev->data->dev_private;
4224 struct rte_device *dev = eth_dev->device;
4225 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4226 struct hns3_hw *hw = &hns->hw;
4228 PMD_INIT_FUNC_TRACE();
4230 hns3_enable_hw_error_intr(hns, false);
4231 hns3_rss_uninit(hns);
4232 hns3_fdir_filter_uninit(hns);
4233 hns3_uninit_umv_space(hw);
4234 hns3_pf_disable_irq0(hw);
4235 rte_intr_disable(&pci_dev->intr_handle);
4236 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4238 hns3_cmd_uninit(hw);
4239 hns3_cmd_destroy_queue(hw);
4244 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4246 struct hns3_hw *hw = &hns->hw;
4249 ret = hns3_dcb_cfg_update(hns);
4254 ret = hns3_start_queues(hns, reset_queue);
4256 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4261 ret = hns3_cfg_mac_mode(hw, true);
4263 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4264 goto err_config_mac_mode;
4268 err_config_mac_mode:
4269 hns3_stop_queues(hns, true);
4274 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4276 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4277 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4278 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4279 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4280 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4281 uint32_t intr_vector;
4285 if (dev->data->dev_conf.intr_conf.rxq == 0)
4288 /* disable uio/vfio intr/eventfd mapping */
4289 rte_intr_disable(intr_handle);
4291 /* check and configure queue intr-vector mapping */
4292 if (rte_intr_cap_multiple(intr_handle) ||
4293 !RTE_ETH_DEV_SRIOV(dev).active) {
4294 intr_vector = hw->used_rx_queues;
4295 /* creates event fd for each intr vector when MSIX is used */
4296 if (rte_intr_efd_enable(intr_handle, intr_vector))
4299 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4300 intr_handle->intr_vec =
4301 rte_zmalloc("intr_vec",
4302 hw->used_rx_queues * sizeof(int), 0);
4303 if (intr_handle->intr_vec == NULL) {
4304 hns3_err(hw, "Failed to allocate %d rx_queues"
4305 " intr_vec", hw->used_rx_queues);
4307 goto alloc_intr_vec_error;
4311 if (rte_intr_allow_others(intr_handle)) {
4312 vec = RTE_INTR_VEC_RXTX_OFFSET;
4313 base = RTE_INTR_VEC_RXTX_OFFSET;
4315 if (rte_intr_dp_is_en(intr_handle)) {
4316 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4317 ret = hns3_bind_ring_with_vector(hw, vec, true,
4321 goto bind_vector_error;
4322 intr_handle->intr_vec[q_id] = vec;
4323 if (vec < base + intr_handle->nb_efd - 1)
4327 rte_intr_enable(intr_handle);
4331 rte_intr_efd_disable(intr_handle);
4332 if (intr_handle->intr_vec) {
4333 free(intr_handle->intr_vec);
4334 intr_handle->intr_vec = NULL;
4337 alloc_intr_vec_error:
4338 rte_intr_efd_disable(intr_handle);
4343 hns3_restore_filter(struct rte_eth_dev *dev)
4345 hns3_restore_rss_filter(dev);
4349 hns3_dev_start(struct rte_eth_dev *dev)
4351 struct hns3_adapter *hns = dev->data->dev_private;
4352 struct hns3_hw *hw = &hns->hw;
4355 PMD_INIT_FUNC_TRACE();
4356 if (rte_atomic16_read(&hw->reset.resetting))
4359 rte_spinlock_lock(&hw->lock);
4360 hw->adapter_state = HNS3_NIC_STARTING;
4362 ret = hns3_do_start(hns, true);
4364 hw->adapter_state = HNS3_NIC_CONFIGURED;
4365 rte_spinlock_unlock(&hw->lock);
4369 hw->adapter_state = HNS3_NIC_STARTED;
4370 rte_spinlock_unlock(&hw->lock);
4372 ret = hns3_map_rx_interrupt(dev);
4375 hns3_set_rxtx_function(dev);
4376 hns3_mp_req_start_rxtx(dev);
4377 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4379 hns3_restore_filter(dev);
4381 hns3_info(hw, "hns3 dev start successful!");
4386 hns3_do_stop(struct hns3_adapter *hns)
4388 struct hns3_hw *hw = &hns->hw;
4392 ret = hns3_cfg_mac_mode(hw, false);
4395 hw->mac.link_status = ETH_LINK_DOWN;
4397 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4398 hns3_configure_all_mac_addr(hns, true);
4401 reset_queue = false;
4402 hw->mac.default_addr_setted = false;
4403 return hns3_stop_queues(hns, reset_queue);
4407 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4409 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4410 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4411 struct hns3_adapter *hns = dev->data->dev_private;
4412 struct hns3_hw *hw = &hns->hw;
4413 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4414 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4417 if (dev->data->dev_conf.intr_conf.rxq == 0)
4420 /* unmap the ring with vector */
4421 if (rte_intr_allow_others(intr_handle)) {
4422 vec = RTE_INTR_VEC_RXTX_OFFSET;
4423 base = RTE_INTR_VEC_RXTX_OFFSET;
4425 if (rte_intr_dp_is_en(intr_handle)) {
4426 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4427 (void)hns3_bind_ring_with_vector(hw, vec, false,
4430 if (vec < base + intr_handle->nb_efd - 1)
4434 /* Clean datapath event and queue/vec mapping */
4435 rte_intr_efd_disable(intr_handle);
4436 if (intr_handle->intr_vec) {
4437 rte_free(intr_handle->intr_vec);
4438 intr_handle->intr_vec = NULL;
4443 hns3_dev_stop(struct rte_eth_dev *dev)
4445 struct hns3_adapter *hns = dev->data->dev_private;
4446 struct hns3_hw *hw = &hns->hw;
4448 PMD_INIT_FUNC_TRACE();
4450 hw->adapter_state = HNS3_NIC_STOPPING;
4451 hns3_set_rxtx_function(dev);
4453 /* Disable datapath on secondary process. */
4454 hns3_mp_req_stop_rxtx(dev);
4455 /* Prevent crashes when queues are still in use. */
4456 rte_delay_ms(hw->tqps_num);
4458 rte_spinlock_lock(&hw->lock);
4459 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4461 hns3_dev_release_mbufs(hns);
4462 hw->adapter_state = HNS3_NIC_CONFIGURED;
4464 rte_eal_alarm_cancel(hns3_service_handler, dev);
4465 rte_spinlock_unlock(&hw->lock);
4466 hns3_unmap_rx_interrupt(dev);
4470 hns3_dev_close(struct rte_eth_dev *eth_dev)
4472 struct hns3_adapter *hns = eth_dev->data->dev_private;
4473 struct hns3_hw *hw = &hns->hw;
4475 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4476 rte_free(eth_dev->process_private);
4477 eth_dev->process_private = NULL;
4481 if (hw->adapter_state == HNS3_NIC_STARTED)
4482 hns3_dev_stop(eth_dev);
4484 hw->adapter_state = HNS3_NIC_CLOSING;
4485 hns3_reset_abort(hns);
4486 hw->adapter_state = HNS3_NIC_CLOSED;
4488 hns3_configure_all_mc_mac_addr(hns, true);
4489 hns3_remove_all_vlan_table(hns);
4490 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4491 hns3_uninit_pf(eth_dev);
4492 hns3_free_all_queues(eth_dev);
4493 rte_free(hw->reset.wait_data);
4494 rte_free(eth_dev->process_private);
4495 eth_dev->process_private = NULL;
4496 hns3_mp_uninit_primary();
4497 hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4501 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4503 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4504 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4506 fc_conf->pause_time = pf->pause_time;
4508 /* return fc current mode */
4509 switch (hw->current_mode) {
4511 fc_conf->mode = RTE_FC_FULL;
4513 case HNS3_FC_TX_PAUSE:
4514 fc_conf->mode = RTE_FC_TX_PAUSE;
4516 case HNS3_FC_RX_PAUSE:
4517 fc_conf->mode = RTE_FC_RX_PAUSE;
4521 fc_conf->mode = RTE_FC_NONE;
4529 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4533 hw->requested_mode = HNS3_FC_NONE;
4535 case RTE_FC_RX_PAUSE:
4536 hw->requested_mode = HNS3_FC_RX_PAUSE;
4538 case RTE_FC_TX_PAUSE:
4539 hw->requested_mode = HNS3_FC_TX_PAUSE;
4542 hw->requested_mode = HNS3_FC_FULL;
4545 hw->requested_mode = HNS3_FC_NONE;
4546 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4547 "configured to RTE_FC_NONE", mode);
4553 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4555 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4556 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4559 if (fc_conf->high_water || fc_conf->low_water ||
4560 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4561 hns3_err(hw, "Unsupported flow control settings specified, "
4562 "high_water(%u), low_water(%u), send_xon(%u) and "
4563 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4564 fc_conf->high_water, fc_conf->low_water,
4565 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4568 if (fc_conf->autoneg) {
4569 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4572 if (!fc_conf->pause_time) {
4573 hns3_err(hw, "Invalid pause time %d setting.",
4574 fc_conf->pause_time);
4578 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4579 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4580 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4581 "current_fc_status = %d", hw->current_fc_status);
4585 hns3_get_fc_mode(hw, fc_conf->mode);
4586 if (hw->requested_mode == hw->current_mode &&
4587 pf->pause_time == fc_conf->pause_time)
4590 rte_spinlock_lock(&hw->lock);
4591 ret = hns3_fc_enable(dev, fc_conf);
4592 rte_spinlock_unlock(&hw->lock);
4598 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4599 struct rte_eth_pfc_conf *pfc_conf)
4601 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4602 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4606 if (!hns3_dev_dcb_supported(hw)) {
4607 hns3_err(hw, "This port does not support dcb configurations.");
4611 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4612 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4613 hns3_err(hw, "Unsupported flow control settings specified, "
4614 "high_water(%u), low_water(%u), send_xon(%u) and "
4615 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4616 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4617 pfc_conf->fc.send_xon,
4618 pfc_conf->fc.mac_ctrl_frame_fwd);
4621 if (pfc_conf->fc.autoneg) {
4622 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4625 if (pfc_conf->fc.pause_time == 0) {
4626 hns3_err(hw, "Invalid pause time %d setting.",
4627 pfc_conf->fc.pause_time);
4631 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4632 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4633 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4634 "current_fc_status = %d", hw->current_fc_status);
4638 priority = pfc_conf->priority;
4639 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4640 if (hw->dcb_info.pfc_en & BIT(priority) &&
4641 hw->requested_mode == hw->current_mode &&
4642 pfc_conf->fc.pause_time == pf->pause_time)
4645 rte_spinlock_lock(&hw->lock);
4646 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4647 rte_spinlock_unlock(&hw->lock);
4653 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4655 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4656 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4657 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4660 rte_spinlock_lock(&hw->lock);
4661 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4662 dcb_info->nb_tcs = pf->local_max_tc;
4664 dcb_info->nb_tcs = 1;
4666 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4667 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4668 for (i = 0; i < dcb_info->nb_tcs; i++)
4669 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4671 for (i = 0; i < hw->num_tc; i++) {
4672 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4673 dcb_info->tc_queue.tc_txq[0][i].base =
4674 hw->tc_queue[i].tqp_offset;
4675 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4676 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4677 hw->tc_queue[i].tqp_count;
4679 rte_spinlock_unlock(&hw->lock);
4685 hns3_reinit_dev(struct hns3_adapter *hns)
4687 struct hns3_hw *hw = &hns->hw;
4690 ret = hns3_cmd_init(hw);
4692 hns3_err(hw, "Failed to init cmd: %d", ret);
4696 ret = hns3_reset_all_queues(hns);
4698 hns3_err(hw, "Failed to reset all queues: %d", ret);
4702 ret = hns3_init_hardware(hns);
4704 hns3_err(hw, "Failed to init hardware: %d", ret);
4708 ret = hns3_enable_hw_error_intr(hns, true);
4710 hns3_err(hw, "fail to enable hw error interrupts: %d",
4714 hns3_info(hw, "Reset done, driver initialization finished.");
4720 is_pf_reset_done(struct hns3_hw *hw)
4722 uint32_t val, reg, reg_bit;
4724 switch (hw->reset.level) {
4725 case HNS3_IMP_RESET:
4726 reg = HNS3_GLOBAL_RESET_REG;
4727 reg_bit = HNS3_IMP_RESET_BIT;
4729 case HNS3_GLOBAL_RESET:
4730 reg = HNS3_GLOBAL_RESET_REG;
4731 reg_bit = HNS3_GLOBAL_RESET_BIT;
4733 case HNS3_FUNC_RESET:
4734 reg = HNS3_FUN_RST_ING;
4735 reg_bit = HNS3_FUN_RST_ING_B;
4737 case HNS3_FLR_RESET:
4739 hns3_err(hw, "Wait for unsupported reset level: %d",
4743 val = hns3_read_dev(hw, reg);
4744 if (hns3_get_bit(val, reg_bit))
4751 hns3_is_reset_pending(struct hns3_adapter *hns)
4753 struct hns3_hw *hw = &hns->hw;
4754 enum hns3_reset_level reset;
4756 hns3_check_event_cause(hns, NULL);
4757 reset = hns3_get_reset_level(hns, &hw->reset.pending);
4758 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4759 hns3_warn(hw, "High level reset %d is pending", reset);
4762 reset = hns3_get_reset_level(hns, &hw->reset.request);
4763 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4764 hns3_warn(hw, "High level reset %d is request", reset);
4771 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4773 struct hns3_hw *hw = &hns->hw;
4774 struct hns3_wait_data *wait_data = hw->reset.wait_data;
4777 if (wait_data->result == HNS3_WAIT_SUCCESS)
4779 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4780 gettimeofday(&tv, NULL);
4781 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4782 tv.tv_sec, tv.tv_usec);
4784 } else if (wait_data->result == HNS3_WAIT_REQUEST)
4787 wait_data->hns = hns;
4788 wait_data->check_completion = is_pf_reset_done;
4789 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4790 HNS3_RESET_WAIT_MS + get_timeofday_ms();
4791 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4792 wait_data->count = HNS3_RESET_WAIT_CNT;
4793 wait_data->result = HNS3_WAIT_REQUEST;
4794 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4799 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4801 struct hns3_cmd_desc desc;
4802 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4804 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4805 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4806 req->fun_reset_vfid = func_id;
4808 return hns3_cmd_send(hw, &desc, 1);
4812 hns3_imp_reset_cmd(struct hns3_hw *hw)
4814 struct hns3_cmd_desc desc;
4816 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4817 desc.data[0] = 0xeedd;
4819 return hns3_cmd_send(hw, &desc, 1);
4823 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4825 struct hns3_hw *hw = &hns->hw;
4829 gettimeofday(&tv, NULL);
4830 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4831 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4832 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4833 tv.tv_sec, tv.tv_usec);
4837 switch (reset_level) {
4838 case HNS3_IMP_RESET:
4839 hns3_imp_reset_cmd(hw);
4840 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4841 tv.tv_sec, tv.tv_usec);
4843 case HNS3_GLOBAL_RESET:
4844 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4845 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4846 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4847 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4848 tv.tv_sec, tv.tv_usec);
4850 case HNS3_FUNC_RESET:
4851 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4852 tv.tv_sec, tv.tv_usec);
4853 /* schedule again to check later */
4854 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4855 hns3_schedule_reset(hns);
4858 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4861 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4864 static enum hns3_reset_level
4865 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4867 struct hns3_hw *hw = &hns->hw;
4868 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4870 /* Return the highest priority reset level amongst all */
4871 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4872 reset_level = HNS3_IMP_RESET;
4873 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4874 reset_level = HNS3_GLOBAL_RESET;
4875 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4876 reset_level = HNS3_FUNC_RESET;
4877 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4878 reset_level = HNS3_FLR_RESET;
4880 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4881 return HNS3_NONE_RESET;
4887 hns3_prepare_reset(struct hns3_adapter *hns)
4889 struct hns3_hw *hw = &hns->hw;
4893 switch (hw->reset.level) {
4894 case HNS3_FUNC_RESET:
4895 ret = hns3_func_reset_cmd(hw, 0);
4900 * After performaning pf reset, it is not necessary to do the
4901 * mailbox handling or send any command to firmware, because
4902 * any mailbox handling or command to firmware is only valid
4903 * after hns3_cmd_init is called.
4905 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4906 hw->reset.stats.request_cnt++;
4908 case HNS3_IMP_RESET:
4909 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4910 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4911 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4920 hns3_set_rst_done(struct hns3_hw *hw)
4922 struct hns3_pf_rst_done_cmd *req;
4923 struct hns3_cmd_desc desc;
4925 req = (struct hns3_pf_rst_done_cmd *)desc.data;
4926 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4927 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4928 return hns3_cmd_send(hw, &desc, 1);
4932 hns3_stop_service(struct hns3_adapter *hns)
4934 struct hns3_hw *hw = &hns->hw;
4935 struct rte_eth_dev *eth_dev;
4937 eth_dev = &rte_eth_devices[hw->data->port_id];
4938 if (hw->adapter_state == HNS3_NIC_STARTED)
4939 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4940 hw->mac.link_status = ETH_LINK_DOWN;
4942 hns3_set_rxtx_function(eth_dev);
4944 /* Disable datapath on secondary process. */
4945 hns3_mp_req_stop_rxtx(eth_dev);
4946 rte_delay_ms(hw->tqps_num);
4948 rte_spinlock_lock(&hw->lock);
4949 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4950 hw->adapter_state == HNS3_NIC_STOPPING) {
4952 hw->reset.mbuf_deferred_free = true;
4954 hw->reset.mbuf_deferred_free = false;
4957 * It is cumbersome for hardware to pick-and-choose entries for deletion
4958 * from table space. Hence, for function reset software intervention is
4959 * required to delete the entries
4961 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
4962 hns3_configure_all_mc_mac_addr(hns, true);
4963 rte_spinlock_unlock(&hw->lock);
4969 hns3_start_service(struct hns3_adapter *hns)
4971 struct hns3_hw *hw = &hns->hw;
4972 struct rte_eth_dev *eth_dev;
4974 if (hw->reset.level == HNS3_IMP_RESET ||
4975 hw->reset.level == HNS3_GLOBAL_RESET)
4976 hns3_set_rst_done(hw);
4977 eth_dev = &rte_eth_devices[hw->data->port_id];
4978 hns3_set_rxtx_function(eth_dev);
4979 hns3_mp_req_start_rxtx(eth_dev);
4980 if (hw->adapter_state == HNS3_NIC_STARTED)
4981 hns3_service_handler(eth_dev);
4987 hns3_restore_conf(struct hns3_adapter *hns)
4989 struct hns3_hw *hw = &hns->hw;
4992 ret = hns3_configure_all_mac_addr(hns, false);
4996 ret = hns3_configure_all_mc_mac_addr(hns, false);
5000 ret = hns3_dev_promisc_restore(hns);
5004 ret = hns3_restore_vlan_table(hns);
5008 ret = hns3_restore_vlan_conf(hns);
5012 ret = hns3_restore_all_fdir_filter(hns);
5016 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5017 ret = hns3_do_start(hns, false);
5020 hns3_info(hw, "hns3 dev restart successful!");
5021 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5022 hw->adapter_state = HNS3_NIC_CONFIGURED;
5026 hns3_configure_all_mc_mac_addr(hns, true);
5028 hns3_configure_all_mac_addr(hns, true);
5033 hns3_reset_service(void *param)
5035 struct hns3_adapter *hns = (struct hns3_adapter *)param;
5036 struct hns3_hw *hw = &hns->hw;
5037 enum hns3_reset_level reset_level;
5038 struct timeval tv_delta;
5039 struct timeval tv_start;
5045 * The interrupt is not triggered within the delay time.
5046 * The interrupt may have been lost. It is necessary to handle
5047 * the interrupt to recover from the error.
5049 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5050 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5051 hns3_err(hw, "Handling interrupts in delayed tasks");
5052 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5053 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5054 if (reset_level == HNS3_NONE_RESET) {
5055 hns3_err(hw, "No reset level is set, try IMP reset");
5056 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5059 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5062 * Check if there is any ongoing reset in the hardware. This status can
5063 * be checked from reset_pending. If there is then, we need to wait for
5064 * hardware to complete reset.
5065 * a. If we are able to figure out in reasonable time that hardware
5066 * has fully resetted then, we can proceed with driver, client
5068 * b. else, we can come back later to check this status so re-sched
5071 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5072 if (reset_level != HNS3_NONE_RESET) {
5073 gettimeofday(&tv_start, NULL);
5074 ret = hns3_reset_process(hns, reset_level);
5075 gettimeofday(&tv, NULL);
5076 timersub(&tv, &tv_start, &tv_delta);
5077 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5078 tv_delta.tv_usec / USEC_PER_MSEC;
5079 if (msec > HNS3_RESET_PROCESS_MS)
5080 hns3_err(hw, "%d handle long time delta %" PRIx64
5081 " ms time=%ld.%.6ld",
5082 hw->reset.level, msec,
5083 tv.tv_sec, tv.tv_usec);
5088 /* Check if we got any *new* reset requests to be honored */
5089 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5090 if (reset_level != HNS3_NONE_RESET)
5091 hns3_msix_process(hns, reset_level);
5094 static const struct eth_dev_ops hns3_eth_dev_ops = {
5095 .dev_start = hns3_dev_start,
5096 .dev_stop = hns3_dev_stop,
5097 .dev_close = hns3_dev_close,
5098 .promiscuous_enable = hns3_dev_promiscuous_enable,
5099 .promiscuous_disable = hns3_dev_promiscuous_disable,
5100 .allmulticast_enable = hns3_dev_allmulticast_enable,
5101 .allmulticast_disable = hns3_dev_allmulticast_disable,
5102 .mtu_set = hns3_dev_mtu_set,
5103 .stats_get = hns3_stats_get,
5104 .stats_reset = hns3_stats_reset,
5105 .xstats_get = hns3_dev_xstats_get,
5106 .xstats_get_names = hns3_dev_xstats_get_names,
5107 .xstats_reset = hns3_dev_xstats_reset,
5108 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
5109 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5110 .dev_infos_get = hns3_dev_infos_get,
5111 .fw_version_get = hns3_fw_version_get,
5112 .rx_queue_setup = hns3_rx_queue_setup,
5113 .tx_queue_setup = hns3_tx_queue_setup,
5114 .rx_queue_release = hns3_dev_rx_queue_release,
5115 .tx_queue_release = hns3_dev_tx_queue_release,
5116 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
5117 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
5118 .dev_configure = hns3_dev_configure,
5119 .flow_ctrl_get = hns3_flow_ctrl_get,
5120 .flow_ctrl_set = hns3_flow_ctrl_set,
5121 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5122 .mac_addr_add = hns3_add_mac_addr,
5123 .mac_addr_remove = hns3_remove_mac_addr,
5124 .mac_addr_set = hns3_set_default_mac_addr,
5125 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
5126 .link_update = hns3_dev_link_update,
5127 .rss_hash_update = hns3_dev_rss_hash_update,
5128 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
5129 .reta_update = hns3_dev_rss_reta_update,
5130 .reta_query = hns3_dev_rss_reta_query,
5131 .filter_ctrl = hns3_dev_filter_ctrl,
5132 .vlan_filter_set = hns3_vlan_filter_set,
5133 .vlan_tpid_set = hns3_vlan_tpid_set,
5134 .vlan_offload_set = hns3_vlan_offload_set,
5135 .vlan_pvid_set = hns3_vlan_pvid_set,
5136 .get_reg = hns3_get_regs,
5137 .get_dcb_info = hns3_get_dcb_info,
5138 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5141 static const struct hns3_reset_ops hns3_reset_ops = {
5142 .reset_service = hns3_reset_service,
5143 .stop_service = hns3_stop_service,
5144 .prepare_reset = hns3_prepare_reset,
5145 .wait_hardware_ready = hns3_wait_hardware_ready,
5146 .reinit_dev = hns3_reinit_dev,
5147 .restore_conf = hns3_restore_conf,
5148 .start_service = hns3_start_service,
5152 hns3_dev_init(struct rte_eth_dev *eth_dev)
5154 struct rte_device *dev = eth_dev->device;
5155 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5156 struct hns3_adapter *hns = eth_dev->data->dev_private;
5157 struct hns3_hw *hw = &hns->hw;
5158 uint16_t device_id = pci_dev->id.device_id;
5161 PMD_INIT_FUNC_TRACE();
5162 eth_dev->process_private = (struct hns3_process_private *)
5163 rte_zmalloc_socket("hns3_filter_list",
5164 sizeof(struct hns3_process_private),
5165 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5166 if (eth_dev->process_private == NULL) {
5167 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5170 /* initialize flow filter lists */
5171 hns3_filterlist_init(eth_dev);
5173 hns3_set_rxtx_function(eth_dev);
5174 eth_dev->dev_ops = &hns3_eth_dev_ops;
5175 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5176 hns3_mp_init_secondary();
5177 hw->secondary_cnt++;
5181 hns3_mp_init_primary();
5182 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5184 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5185 device_id == HNS3_DEV_ID_50GE_RDMA ||
5186 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5187 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5190 hw->data = eth_dev->data;
5193 * Set default max packet size according to the mtu
5194 * default vale in DPDK frame.
5196 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5198 ret = hns3_reset_init(hw);
5200 goto err_init_reset;
5201 hw->reset.ops = &hns3_reset_ops;
5203 ret = hns3_init_pf(eth_dev);
5205 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5209 /* Allocate memory for storing MAC addresses */
5210 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5211 sizeof(struct rte_ether_addr) *
5212 HNS3_UC_MACADDR_NUM, 0);
5213 if (eth_dev->data->mac_addrs == NULL) {
5214 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5215 "to store MAC addresses",
5216 sizeof(struct rte_ether_addr) *
5217 HNS3_UC_MACADDR_NUM);
5219 goto err_rte_zmalloc;
5222 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5223 ð_dev->data->mac_addrs[0]);
5225 hw->adapter_state = HNS3_NIC_INITIALIZED;
5227 * Pass the information to the rte_eth_dev_close() that it should also
5228 * release the private port resources.
5230 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5232 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5233 hns3_err(hw, "Reschedule reset service after dev_init");
5234 hns3_schedule_reset(hns);
5236 /* IMP will wait ready flag before reset */
5237 hns3_notify_reset_ready(hw, false);
5240 hns3_info(hw, "hns3 dev initialization successful!");
5244 hns3_uninit_pf(eth_dev);
5247 rte_free(hw->reset.wait_data);
5249 eth_dev->dev_ops = NULL;
5250 eth_dev->rx_pkt_burst = NULL;
5251 eth_dev->tx_pkt_burst = NULL;
5252 eth_dev->tx_pkt_prepare = NULL;
5253 rte_free(eth_dev->process_private);
5254 eth_dev->process_private = NULL;
5259 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5261 struct hns3_adapter *hns = eth_dev->data->dev_private;
5262 struct hns3_hw *hw = &hns->hw;
5264 PMD_INIT_FUNC_TRACE();
5266 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5269 eth_dev->dev_ops = NULL;
5270 eth_dev->rx_pkt_burst = NULL;
5271 eth_dev->tx_pkt_burst = NULL;
5272 eth_dev->tx_pkt_prepare = NULL;
5273 if (hw->adapter_state < HNS3_NIC_CLOSING)
5274 hns3_dev_close(eth_dev);
5276 hw->adapter_state = HNS3_NIC_REMOVED;
5281 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5282 struct rte_pci_device *pci_dev)
5284 return rte_eth_dev_pci_generic_probe(pci_dev,
5285 sizeof(struct hns3_adapter),
5290 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5292 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5295 static const struct rte_pci_id pci_id_hns3_map[] = {
5296 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5297 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5298 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5299 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5300 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5301 { .vendor_id = 0, /* sentinel */ },
5304 static struct rte_pci_driver rte_hns3_pmd = {
5305 .id_table = pci_id_hns3_map,
5306 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5307 .probe = eth_hns3_pci_probe,
5308 .remove = eth_hns3_pci_remove,
5311 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5312 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5313 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5315 RTE_INIT(hns3_init_log)
5317 hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5318 if (hns3_logtype_init >= 0)
5319 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5320 hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5321 if (hns3_logtype_driver >= 0)
5322 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);