1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #ifndef _HNS3_ETHDEV_H_
6 #define _HNS3_ETHDEV_H_
14 #include "hns3_fdir.h"
15 #include "hns3_stats.h"
18 #define PCI_VENDOR_ID_HUAWEI 0x19e5
21 #define HNS3_DEV_ID_GE 0xA220
22 #define HNS3_DEV_ID_25GE 0xA221
23 #define HNS3_DEV_ID_25GE_RDMA 0xA222
24 #define HNS3_DEV_ID_50GE_RDMA 0xA224
25 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226
26 #define HNS3_DEV_ID_100G_VF 0xA22E
27 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
29 #define HNS3_UC_MACADDR_NUM 128
30 #define HNS3_VF_UC_MACADDR_NUM 48
31 #define HNS3_MC_MACADDR_NUM 128
33 #define HNS3_MAX_BD_SIZE 65535
34 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8
35 #define HNS3_MAX_TSO_BD_PER_PKT 63
36 #define HNS3_MAX_FRAME_LEN 9728
37 #define HNS3_VLAN_TAG_SIZE 4
38 #define HNS3_DEFAULT_RX_BUF_LEN 2048
39 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
40 #define HNS3_MAX_TSO_HDR_SIZE 512
41 #define HNS3_MAX_TSO_HDR_BD_NUM 3
43 #define HNS3_ETH_OVERHEAD \
44 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
45 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD)
46 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
47 #define HNS3_DEFAULT_MTU 1500UL
48 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
49 #define HNS3_MIN_PKT_SIZE 60
54 #define HNS3_MAX_PF_NUM 8
55 #define HNS3_UMV_TBL_SIZE 3072
56 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \
57 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM)
59 #define HNS3_PF_CFG_BLOCK_SIZE 32
60 #define HNS3_PF_CFG_DESC_NUM \
61 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES)
63 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0
65 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5
66 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500
68 #define HNS3_QUIT_RESET_CNT 10
69 #define HNS3_QUIT_RESET_DELAY_MS 100
71 #define HNS3_POLL_RESPONE_MS 1
73 #define HNS3_MAX_USER_PRIO 8
83 #define HNS3_SCH_MODE_SP 0
84 #define HNS3_SCH_MODE_DWRR 1
87 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */
90 uint8_t tc_dwrr[HNS3_MAX_TC_NUM];
95 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */
98 uint8_t up_to_tc_map; /* user priority maping on the TC */
101 struct hns3_dcb_info {
103 uint8_t num_pg; /* It must be 1 if vNET-Base schd */
104 uint8_t pg_dwrr[HNS3_PG_NUM];
105 uint8_t prio_tc[HNS3_MAX_USER_PRIO];
106 struct hns3_pg_info pg_info[HNS3_PG_NUM];
107 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM];
108 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */
109 uint8_t pfc_en; /* Pfc enabled or not for user priority */
112 enum hns3_fc_status {
114 HNS3_FC_STATUS_MAC_PAUSE,
118 struct hns3_tc_queue_info {
119 uint8_t tqp_offset; /* TQP offset from base TQP */
120 uint8_t tqp_count; /* Total TQPs */
121 uint8_t tc; /* TC index */
122 bool enable; /* If this TC is enable or not */
126 uint8_t vmdq_vport_num;
128 uint16_t tqp_desc_num;
130 uint16_t rss_size_max;
133 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
134 uint8_t default_speed;
135 uint32_t numa_node_map;
136 uint8_t speed_ability;
141 enum hns3_media_type {
142 HNS3_MEDIA_TYPE_UNKNOWN,
143 HNS3_MEDIA_TYPE_FIBER,
144 HNS3_MEDIA_TYPE_COPPER,
145 HNS3_MEDIA_TYPE_BACKPLANE,
146 HNS3_MEDIA_TYPE_NONE,
150 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
151 bool default_addr_setted; /* whether default addr(mac_addr) is setted */
154 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
155 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
156 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
157 uint32_t link_speed; /* ETH_SPEED_NUM_ */
160 struct hns3_fake_queue_data {
161 void **rx_queues; /* Array of pointers to fake RX queues. */
162 void **tx_queues; /* Array of pointers to fake TX queues. */
163 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */
164 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
167 /* Primary process maintains driver state in main thread.
170 * | UNINITIALIZED |<-----------+
171 * +---------------+ |
172 * |.eth_dev_init |.eth_dev_uninit
174 * +---------------+------------+
176 * +---------------+<-----------<---------------+
177 * |.dev_configure | |
179 * +---------------+------------+ |
181 * +---------------+----+ |
183 * | | +---------------+
185 * | | +---------------+
187 * V |.dev_configure |
188 * +---------------+----+ |.dev_close
189 * | CONFIGURED |----------------------------+
190 * +---------------+<-----------+
193 * +---------------+ |
194 * | STARTING |------------^
195 * +---------------+ failed |
197 * | +---------------+
199 * | +---------------+
202 * +---------------+------------+
206 enum hns3_adapter_state {
207 HNS3_NIC_UNINITIALIZED = 0,
208 HNS3_NIC_INITIALIZED,
209 HNS3_NIC_CONFIGURING,
220 /* Reset various stages, execute in order */
221 enum hns3_reset_stage {
222 /* Stop query services, stop transceiver, disable MAC */
224 /* Clear reset completion flags, disable send command */
226 /* Inform IMP to start resetting */
227 RESET_STAGE_REQ_HW_RESET,
228 /* Waiting for hardware reset to complete */
230 /* Reinitialize hardware */
231 RESET_STAGE_DEV_INIT,
232 /* Restore user settings and enable MAC */
234 /* Restart query services, start transceiver */
236 /* Not in reset state */
240 enum hns3_reset_level {
242 HNS3_VF_FUNC_RESET, /* A VF function reset */
244 * All VFs under a PF perform function reset.
245 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
246 * of the reset level and the one defined in kernel driver should be
249 HNS3_VF_PF_FUNC_RESET = 2,
251 * All VFs under a PF perform FLR reset.
252 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
253 * of the reset level and the one defined in kernel driver should be
256 HNS3_VF_FULL_RESET = 3,
257 HNS3_FLR_RESET, /* A VF perform FLR reset */
258 /* All VFs under the rootport perform a global or IMP reset */
260 HNS3_FUNC_RESET, /* A PF function reset */
261 /* All PFs under the rootport perform a global reset */
263 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
267 enum hns3_wait_result {
274 #define HNS3_RESET_SYNC_US 100000
276 struct hns3_reset_stats {
277 uint64_t request_cnt; /* Total request reset times */
278 uint64_t global_cnt; /* Total GLOBAL reset times */
279 uint64_t imp_cnt; /* Total IMP reset times */
280 uint64_t exec_cnt; /* Total reset executive times */
281 uint64_t success_cnt; /* Total reset successful times */
282 uint64_t fail_cnt; /* Total reset failed times */
283 uint64_t merge_cnt; /* Total merged in high reset times */
286 typedef bool (*check_completion_func)(struct hns3_hw *hw);
288 struct hns3_wait_data {
293 enum hns3_wait_result result;
294 check_completion_func check_completion;
297 struct hns3_reset_ops {
298 void (*reset_service)(void *arg);
299 int (*stop_service)(struct hns3_adapter *hns);
300 int (*prepare_reset)(struct hns3_adapter *hns);
301 int (*wait_hardware_ready)(struct hns3_adapter *hns);
302 int (*reinit_dev)(struct hns3_adapter *hns);
303 int (*restore_conf)(struct hns3_adapter *hns);
304 int (*start_service)(struct hns3_adapter *hns);
314 struct hns3_reset_data {
315 enum hns3_reset_stage stage;
316 rte_atomic16_t schedule;
317 /* Reset flag, covering the entire reset process */
318 rte_atomic16_t resetting;
319 /* Used to disable sending cmds during reset */
320 rte_atomic16_t disable_cmd;
321 /* The reset level being processed */
322 enum hns3_reset_level level;
323 /* Reset level set, each bit represents a reset level */
325 /* Request reset level set, from interrupt or mailbox */
327 int attempts; /* Reset failure retry */
328 int retries; /* Timeout failure retry in reset_post */
330 * At the time of global or IMP reset, the command cannot be sent to
331 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the
332 * reset process, so the mbuf is required to be released after the reset
333 * is completed.The mbuf_deferred_free is used to mark whether mbuf
334 * needs to be released.
336 bool mbuf_deferred_free;
337 struct timeval start_time;
338 struct hns3_reset_stats stats;
339 const struct hns3_reset_ops *ops;
340 struct hns3_wait_data *wait_data;
344 struct rte_eth_dev_data *data;
347 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
348 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */
349 pthread_t irq_thread_id;
351 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
352 struct hns3_tqp_stats tqp_stats;
353 /* Include Mac stats | Rx stats | Tx stats */
354 struct hns3_mac_stats mac_stats;
358 uint16_t total_tqps_num; /* total task queue pairs of this PF */
359 uint16_t tqps_num; /* num task queue pairs of this function */
360 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
361 uint16_t rss_size_max; /* HW defined max RSS task queue */
363 uint16_t num_tx_desc; /* desc num of per tx queue */
364 uint16_t num_rx_desc; /* desc num of per rx queue */
366 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
367 int mc_addrs_num; /* Multicast mac addresses number */
369 /* The configuration info of RSS */
370 struct hns3_rss_conf rss_info;
371 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
373 uint8_t num_tc; /* Total number of enabled TCs */
375 enum hns3_fc_mode current_mode;
376 enum hns3_fc_mode requested_mode;
377 struct hns3_dcb_info dcb_info;
378 enum hns3_fc_status current_fc_status; /* current flow control status */
379 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
380 uint16_t used_rx_queues;
381 uint16_t used_tx_queues;
383 /* Config max queue numbers between rx and tx queues from user */
384 uint16_t cfg_max_queues;
385 struct hns3_fake_queue_data fkq_data; /* fake queue data */
386 uint16_t alloc_rss_size; /* RX queue number per TC */
387 uint16_t tx_qnum_per_tc; /* TX queue number per TC */
391 * PMD setup and configuration is not thread safe. Since it is not
392 * performance sensitive, it is better to guarantee thread-safety
393 * and add device level lock. Adapter control operations which
394 * change its state should acquire the lock.
397 enum hns3_adapter_state adapter_state;
398 struct hns3_reset_data reset;
401 #define HNS3_FLAG_TC_BASE_SCH_MODE 1
402 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2
404 struct hns3_err_msix_intr_stats {
405 uint64_t mac_afifo_tnl_intr_cnt;
406 uint64_t ppu_mpf_abnormal_intr_st2_cnt;
407 uint64_t ssu_port_based_pf_intr_cnt;
408 uint64_t ppp_pf_abnormal_intr_cnt;
409 uint64_t ppu_pf_abnormal_intr_cnt;
412 /* vlan entry information. */
413 struct hns3_user_vlan_table {
414 LIST_ENTRY(hns3_user_vlan_table) next;
419 struct hns3_port_base_vlan_config {
424 /* Vlan tag configuration for RX direction */
425 struct hns3_rx_vtag_cfg {
426 uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */
427 uint8_t strip_tag1_en; /* Whether strip inner vlan tag */
428 uint8_t strip_tag2_en; /* Whether strip outer vlan tag */
429 uint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */
430 uint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */
433 /* Vlan tag configuration for TX direction */
434 struct hns3_tx_vtag_cfg {
435 bool accept_tag1; /* Whether accept tag1 packet from host */
436 bool accept_untag1; /* Whether accept untag1 packet from host */
439 bool insert_tag1_en; /* Whether insert inner vlan tag */
440 bool insert_tag2_en; /* Whether insert outer vlan tag */
441 uint16_t default_tag1; /* The default inner vlan tag to insert */
442 uint16_t default_tag2; /* The default outer vlan tag to insert */
445 struct hns3_vtag_cfg {
446 struct hns3_rx_vtag_cfg rx_vcfg;
447 struct hns3_tx_vtag_cfg tx_vcfg;
450 /* Request types for IPC. */
451 enum hns3_mp_req_type {
452 HNS3_MP_REQ_START_RXTX = 1,
453 HNS3_MP_REQ_STOP_RXTX,
457 /* Pameters for IPC. */
458 struct hns3_mp_param {
459 enum hns3_mp_req_type type;
464 /* Request timeout for IPC. */
465 #define HNS3_MP_REQ_TIMEOUT_SEC 5
467 /* Key string for IPC. */
468 #define HNS3_MP_NAME "net_hns3_mp"
471 struct hns3_adapter *adapter;
473 uint16_t func_num; /* num functions of this pf, include pf and vfs */
475 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
476 uint32_t tx_buf_size; /* Tx buffer size for each TC */
477 uint32_t dv_buf_size; /* Dv buffer size for each TC */
479 uint16_t mps; /* Max packet size */
482 uint8_t tc_max; /* max number of tc driver supported */
483 uint8_t local_max_tc; /* max number of local tc */
485 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */
487 bool support_fc_autoneg; /* support FC autonegotiate */
489 uint16_t wanted_umv_size;
490 uint16_t max_umv_size;
491 uint16_t used_umv_size;
493 /* Statistics information for abnormal interrupt */
494 struct hns3_err_msix_intr_stats abn_int_stats;
496 bool support_sfp_query;
498 struct hns3_vtag_cfg vtag_config;
499 struct hns3_port_base_vlan_config port_base_vlan_cfg;
500 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
502 struct hns3_fdir_info fdir; /* flow director info */
503 LIST_HEAD(counters, hns3_flow_counter) flow_counters;
507 struct hns3_adapter *adapter;
510 struct hns3_adapter {
513 /* Specific for PF or VF */
514 bool is_vf; /* false - PF, true - VF */
521 #define HNS3_DEV_SUPPORT_DCB_B 0x0
523 #define hns3_dev_dcb_supported(hw) \
524 hns3_get_bit((hw)->flag, HNS3_DEV_SUPPORT_DCB_B)
526 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
527 (&((struct hns3_adapter *)adapter)->hw)
528 #define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \
529 ((struct hns3_adapter *)adapter)
530 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \
531 (&((struct hns3_adapter *)adapter)->pf)
532 #define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \
533 (&((struct hns3_adapter *)adapter)->vf)
534 #define HNS3_DEV_HW_TO_ADAPTER(hw) \
535 container_of(hw, struct hns3_adapter, hw)
537 #define hns3_set_field(origin, mask, shift, val) \
539 (origin) &= (~(mask)); \
540 (origin) |= ((val) << (shift)) & (mask); \
542 #define hns3_get_field(origin, mask, shift) \
543 (((origin) & (mask)) >> (shift))
544 #define hns3_set_bit(origin, shift, val) \
545 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val))
546 #define hns3_get_bit(origin, shift) \
547 hns3_get_field((origin), (0x1UL << (shift)), (shift))
550 * upper_32_bits - return bits 32-63 of a number
551 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
552 * the "right shift count >= width of type" warning when that quantity is
555 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
557 /* lower_32_bits - return bits 0-31 of a number */
558 #define lower_32_bits(n) ((uint32_t)(n))
560 #define BIT(nr) (1UL << (nr))
562 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
563 #define GENMASK(h, l) \
564 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
566 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
567 #define rounddown(x, y) ((x) - ((x) % (y)))
569 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
571 #define max_t(type, x, y) ({ \
574 __max1 > __max2 ? __max1 : __max2; })
576 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
578 rte_write32(value, (volatile void *)((char *)base + reg));
581 static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
583 return rte_read32((volatile void *)((char *)base + reg));
586 #define hns3_write_dev(a, reg, value) \
587 hns3_write_reg((a)->io_base, (reg), (value))
589 #define hns3_read_dev(a, reg) \
590 hns3_read_reg((a)->io_base, (reg))
592 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
594 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
596 act = (actions) + (index); \
597 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
599 act = actions + index; \
603 #define MSEC_PER_SEC 1000L
604 #define USEC_PER_MSEC 1000L
606 static inline uint64_t
607 get_timeofday_ms(void)
611 (void)gettimeofday(&tv, NULL);
613 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
616 static inline uint64_t
617 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
621 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;
626 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)
628 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);
632 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)
634 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);
637 static inline int64_t
638 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)
640 uint64_t mask = (1UL << nr);
642 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
645 int hns3_buffer_alloc(struct hns3_hw *hw);
646 int hns3_config_gro(struct hns3_hw *hw, bool en);
647 int hns3_dev_filter_ctrl(struct rte_eth_dev *dev,
648 enum rte_filter_type filter_type,
649 enum rte_filter_op filter_op, void *arg);
650 bool hns3_is_reset_pending(struct hns3_adapter *hns);
651 bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
652 void hns3_update_link_status(struct hns3_hw *hw);
655 is_reset_pending(struct hns3_adapter *hns)
659 ret = hns3vf_is_reset_pending(hns);
661 ret = hns3_is_reset_pending(hns);
665 #endif /* _HNS3_ETHDEV_H_ */