1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
5 #ifndef _HNS3_ETHDEV_H_
6 #define _HNS3_ETHDEV_H_
9 #include <ethdev_driver.h>
10 #include <rte_byteorder.h>
12 #include <rte_spinlock.h>
17 #include "hns3_fdir.h"
18 #include "hns3_stats.h"
22 #define PCI_VENDOR_ID_HUAWEI 0x19e5
25 #define HNS3_DEV_ID_GE 0xA220
26 #define HNS3_DEV_ID_25GE 0xA221
27 #define HNS3_DEV_ID_25GE_RDMA 0xA222
28 #define HNS3_DEV_ID_50GE_RDMA 0xA224
29 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226
30 #define HNS3_DEV_ID_200G_RDMA 0xA228
31 #define HNS3_DEV_ID_100G_VF 0xA22E
32 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
34 /* PCI Config offsets */
35 #define HNS3_PCI_REVISION_ID 0x08
36 #define HNS3_PCI_REVISION_ID_LEN 1
38 #define PCI_REVISION_ID_HIP08_B 0x21
39 #define PCI_REVISION_ID_HIP09_A 0x30
41 #define HNS3_PF_FUNC_ID 0
42 #define HNS3_1ST_VF_FUNC_ID 1
44 #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0
45 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1
47 #define HNS3_UNLIMIT_PROMISC_MODE 0
48 #define HNS3_LIMIT_PROMISC_MODE 1
50 #define HNS3_SPECIAL_PORT_SW_CKSUM_MODE 0
51 #define HNS3_SPECIAL_PORT_HW_CKSUM_MODE 1
53 #define HNS3_UC_MACADDR_NUM 128
54 #define HNS3_VF_UC_MACADDR_NUM 48
55 #define HNS3_MC_MACADDR_NUM 128
57 #define HNS3_MAX_BD_SIZE 65535
58 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8
59 #define HNS3_MAX_TSO_BD_PER_PKT 63
60 #define HNS3_MAX_FRAME_LEN 9728
61 #define HNS3_VLAN_TAG_SIZE 4
62 #define HNS3_DEFAULT_RX_BUF_LEN 2048
63 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
64 #define HNS3_MAX_TSO_HDR_SIZE 512
65 #define HNS3_MAX_TSO_HDR_BD_NUM 3
66 #define HNS3_MAX_LRO_SIZE 64512
68 #define HNS3_ETH_OVERHEAD \
69 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
70 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD)
71 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
72 #define HNS3_DEFAULT_MTU 1500UL
73 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
74 #define HNS3_HIP08_MIN_TX_PKT_LEN 33
75 #define HNS3_HIP09_MIN_TX_PKT_LEN 9
77 #define HNS3_BITS_PER_BYTE 8
82 #define HNS3_MAX_PF_NUM 8
83 #define HNS3_UMV_TBL_SIZE 3072
84 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \
85 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM)
87 #define HNS3_PF_CFG_BLOCK_SIZE 32
88 #define HNS3_PF_CFG_DESC_NUM \
89 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES)
91 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0
93 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5
94 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500
96 #define HNS3_QUIT_RESET_CNT 10
97 #define HNS3_QUIT_RESET_DELAY_MS 100
99 #define HNS3_POLL_RESPONE_MS 1
101 #define HNS3_MAX_USER_PRIO 8
102 #define HNS3_PG_NUM 4
111 #define HNS3_SCH_MODE_SP 0
112 #define HNS3_SCH_MODE_DWRR 1
113 struct hns3_pg_info {
115 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */
118 uint8_t tc_dwrr[HNS3_MAX_TC_NUM];
121 struct hns3_tc_info {
123 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */
126 uint8_t up_to_tc_map; /* user priority maping on the TC */
129 struct hns3_dcb_info {
131 uint8_t num_pg; /* It must be 1 if vNET-Base schd */
132 uint8_t pg_dwrr[HNS3_PG_NUM];
133 uint8_t prio_tc[HNS3_MAX_USER_PRIO];
134 struct hns3_pg_info pg_info[HNS3_PG_NUM];
135 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM];
136 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */
137 uint8_t pfc_en; /* Pfc enabled or not for user priority */
140 enum hns3_fc_status {
142 HNS3_FC_STATUS_MAC_PAUSE,
146 struct hns3_tc_queue_info {
147 uint16_t tqp_offset; /* TQP offset from base TQP */
148 uint16_t tqp_count; /* Total TQPs */
149 uint8_t tc; /* TC index */
150 bool enable; /* If this TC is enable or not */
154 uint8_t vmdq_vport_num;
156 uint16_t tqp_desc_num;
158 uint16_t rss_size_max;
161 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
162 uint8_t default_speed;
163 uint32_t numa_node_map;
164 uint8_t speed_ability;
169 enum hns3_media_type {
170 HNS3_MEDIA_TYPE_UNKNOWN,
171 HNS3_MEDIA_TYPE_FIBER,
172 HNS3_MEDIA_TYPE_COPPER,
173 HNS3_MEDIA_TYPE_BACKPLANE,
174 HNS3_MEDIA_TYPE_NONE,
178 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
179 bool default_addr_setted; /* whether default addr(mac_addr) is set */
182 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
183 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
184 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
185 uint32_t link_speed; /* ETH_SPEED_NUM_ */
186 uint32_t supported_capa; /* supported capability for current media */
187 uint32_t advertising; /* advertised capability in the local part */
188 /* advertised capability in the link partner */
189 uint32_t lp_advertising;
190 uint8_t support_autoneg;
193 struct hns3_fake_queue_data {
194 void **rx_queues; /* Array of pointers to fake RX queues. */
195 void **tx_queues; /* Array of pointers to fake TX queues. */
196 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */
197 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
200 #define HNS3_PORT_BASE_VLAN_DISABLE 0
201 #define HNS3_PORT_BASE_VLAN_ENABLE 1
202 struct hns3_port_base_vlan_config {
207 /* Primary process maintains driver state in main thread.
210 * | UNINITIALIZED |<-----------+
211 * +---------------+ |
212 * |.eth_dev_init |.eth_dev_uninit
214 * +---------------+------------+
216 * +---------------+<-----------<---------------+
217 * |.dev_configure | |
219 * +---------------+------------+ |
221 * +---------------+----+ |
223 * | | +---------------+
225 * | | +---------------+
227 * V |.dev_configure |
228 * +---------------+----+ |.dev_close
229 * | CONFIGURED |----------------------------+
230 * +---------------+<-----------+
233 * +---------------+ |
234 * | STARTING |------------^
235 * +---------------+ failed |
237 * | +---------------+
239 * | +---------------+
242 * +---------------+------------+
246 enum hns3_adapter_state {
247 HNS3_NIC_UNINITIALIZED = 0,
248 HNS3_NIC_INITIALIZED,
249 HNS3_NIC_CONFIGURING,
260 /* Reset various stages, execute in order */
261 enum hns3_reset_stage {
262 /* Stop query services, stop transceiver, disable MAC */
264 /* Clear reset completion flags, disable send command */
266 /* Inform IMP to start resetting */
267 RESET_STAGE_REQ_HW_RESET,
268 /* Waiting for hardware reset to complete */
270 /* Reinitialize hardware */
271 RESET_STAGE_DEV_INIT,
272 /* Restore user settings and enable MAC */
274 /* Restart query services, start transceiver */
276 /* Not in reset state */
280 enum hns3_reset_level {
282 HNS3_VF_FUNC_RESET, /* A VF function reset */
284 * All VFs under a PF perform function reset.
285 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
286 * of the reset level and the one defined in kernel driver should be
289 HNS3_VF_PF_FUNC_RESET = 2,
291 * All VFs under a PF perform FLR reset.
292 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
293 * of the reset level and the one defined in kernel driver should be
296 * According to the protocol of PCIe, FLR to a PF resets the PF state as
297 * well as the SR-IOV extended capability including VF Enable which
298 * means that VFs no longer exist.
300 * In PF FLR, the register state of VF is not reliable, VF's driver
301 * should not access the registers of the VF device.
303 HNS3_VF_FULL_RESET = 3,
304 HNS3_FLR_RESET, /* A VF perform FLR reset */
305 /* All VFs under the rootport perform a global or IMP reset */
307 HNS3_FUNC_RESET, /* A PF function reset */
308 /* All PFs under the rootport perform a global reset */
310 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
314 enum hns3_wait_result {
321 #define HNS3_RESET_SYNC_US 100000
323 struct hns3_reset_stats {
324 uint64_t request_cnt; /* Total request reset times */
325 uint64_t global_cnt; /* Total GLOBAL reset times */
326 uint64_t imp_cnt; /* Total IMP reset times */
327 uint64_t exec_cnt; /* Total reset executive times */
328 uint64_t success_cnt; /* Total reset successful times */
329 uint64_t fail_cnt; /* Total reset failed times */
330 uint64_t merge_cnt; /* Total merged in high reset times */
333 typedef bool (*check_completion_func)(struct hns3_hw *hw);
335 struct hns3_wait_data {
340 enum hns3_wait_result result;
341 check_completion_func check_completion;
344 struct hns3_reset_ops {
345 void (*reset_service)(void *arg);
346 int (*stop_service)(struct hns3_adapter *hns);
347 int (*prepare_reset)(struct hns3_adapter *hns);
348 int (*wait_hardware_ready)(struct hns3_adapter *hns);
349 int (*reinit_dev)(struct hns3_adapter *hns);
350 int (*restore_conf)(struct hns3_adapter *hns);
351 int (*start_service)(struct hns3_adapter *hns);
361 struct hns3_reset_data {
362 enum hns3_reset_stage stage;
364 /* Reset flag, covering the entire reset process */
366 /* Used to disable sending cmds during reset */
367 uint16_t disable_cmd;
368 /* The reset level being processed */
369 enum hns3_reset_level level;
370 /* Reset level set, each bit represents a reset level */
372 /* Request reset level set, from interrupt or mailbox */
374 int attempts; /* Reset failure retry */
375 int retries; /* Timeout failure retry in reset_post */
377 * At the time of global or IMP reset, the command cannot be sent to
378 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the
379 * reset process, so the mbuf is required to be released after the reset
380 * is completed.The mbuf_deferred_free is used to mark whether mbuf
381 * needs to be released.
383 bool mbuf_deferred_free;
384 struct timeval start_time;
385 struct hns3_reset_stats stats;
386 const struct hns3_reset_ops *ops;
387 struct hns3_wait_data *wait_data;
390 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0
391 #define HNS3_INTR_MAPPING_VEC_ALL 1
393 #define HNS3_INTR_COALESCE_GL_UINT_2US 0
394 #define HNS3_INTR_COALESCE_GL_UINT_1US 1
396 #define HNS3_INTR_QL_NONE 0
398 struct hns3_queue_intr {
400 * interrupt mapping mode.
402 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL
404 * - HNS3_INTR_MAPPING_VEC_RSV_ONE
405 * For some versions of hardware network engine, because of the
406 * hardware constraint, we need implement clearing the mapping
407 * relationship configurations by binding all queues to the last
408 * interrupt vector and reserving the last interrupt vector. This
409 * method results in a decrease of the maximum queues when upper
410 * applications call the rte_eth_dev_configure API function to
411 * enable Rx interrupt.
413 * - HNS3_INTR_MAPPING_VEC_ALL
414 * PMD driver can map/unmmap all interrupt vectors with queues When
415 * Rx interrupt in enabled.
417 uint8_t mapping_mode;
419 * The unit of GL(gap limiter) configuration for interrupt coalesce of
422 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US
425 /* The max QL(quantity limiter) value */
429 #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0
430 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1
432 #define HNS3_PKTS_DROP_STATS_MODE1 0
433 #define HNS3_PKTS_DROP_STATS_MODE2 1
436 struct rte_eth_dev_data *data;
438 uint8_t revision; /* PCI revision, low byte of class word */
440 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
441 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */
443 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
444 struct hns3_tqp_stats tqp_stats;
445 /* Include Mac stats | Rx stats | Tx stats */
446 struct hns3_mac_stats mac_stats;
447 struct hns3_rx_missed_stats imissed_stats;
448 uint64_t oerror_stats;
452 uint16_t total_tqps_num; /* total task queue pairs of this PF */
453 uint16_t tqps_num; /* num task queue pairs of this function */
454 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
455 uint16_t rss_size_max; /* HW defined max RSS task queue */
456 uint16_t rx_buf_len; /* hold min hardware rx buf len */
457 uint16_t num_tx_desc; /* desc num of per tx queue */
458 uint16_t num_rx_desc; /* desc num of per rx queue */
459 uint32_t mng_entry_num; /* number of manager table entry */
460 uint32_t mac_entry_num; /* number of mac-vlan table entry */
462 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
463 int mc_addrs_num; /* Multicast mac addresses number */
465 /* The configuration info of RSS */
466 struct hns3_rss_conf rss_info;
467 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
468 uint16_t rss_ind_tbl_size;
469 uint16_t rss_key_size;
471 uint8_t num_tc; /* Total number of enabled TCs */
473 enum hns3_fc_mode current_mode;
474 enum hns3_fc_mode requested_mode;
475 struct hns3_dcb_info dcb_info;
476 enum hns3_fc_status current_fc_status; /* current flow control status */
477 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
478 uint16_t used_rx_queues;
479 uint16_t used_tx_queues;
481 /* Config max queue numbers between rx and tx queues from user */
482 uint16_t cfg_max_queues;
483 struct hns3_fake_queue_data fkq_data; /* fake queue data */
484 uint16_t alloc_rss_size; /* RX queue number per TC */
485 uint16_t tx_qnum_per_tc; /* TX queue number per TC */
488 uint32_t max_tm_rate;
490 * The minimum length of the packet supported by hardware in the Tx
493 uint32_t min_tx_pkt_len;
495 struct hns3_queue_intr intr;
499 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
501 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM
502 * In this mode, because of the hardware constraint, network driver
503 * software need erase the L4 len value of the TCP pseudo header
504 * and recalculate the TCP pseudo header checksum of packets that
507 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
508 * In this mode, hardware support recalculate the TCP pseudo header
509 * checksum of packets that need TSO, so network driver software
510 * not need to recalculate it.
516 * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE
518 * - HNS3_SW_SHIFT_AND_DISCARD_MODE
519 * For some versions of hardware network engine, because of the
520 * hardware limitation, PMD driver needs to detect the PVID status
521 * to work with haredware to implement PVID-related functions.
522 * For example, driver need discard the stripped PVID tag to ensure
523 * the PVID will not report to mbuf and shift the inserted VLAN tag
524 * to avoid port based VLAN covering it.
526 * - HNS3_HW_SHIT_AND_DISCARD_MODE
527 * PMD driver does not need to process PVID-related functions in
528 * I/O process, Hardware will adjust the sequence between port based
529 * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by
530 * PVID will be invisible to driver. And in this mode, hns3 is able
531 * to send a multi-layer VLAN packets when hw VLAN insert offload
538 * HNS3_UNLIMIT_PROMISC_MODE/HNS3_LIMIT_PROMISC_MODE
540 * - HNS3_UNLIMIT_PROMISC_MODE
541 * In this mode, TX unicast promisc will be configured when promisc
542 * is set, driver can receive all the ingress and outgoing traffic.
543 * In the words, all the ingress packets, all the packets sent from
544 * the PF and other VFs on the same physical port.
546 * - HNS3_LIMIT_PROMISC_MODE
547 * In this mode, TX unicast promisc is shutdown when promisc mode
548 * is set. So, driver will only receive all the ingress traffic.
549 * The packets sent from the PF and other VFs on the same physical
550 * port won't be copied to the function which has set promisc mode.
552 uint8_t promisc_mode;
555 * drop_stats_mode mode.
557 * HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2
559 * - HNS3_PKTS_DROP_STATS_MODE1
560 * This mode for kunpeng920. In this mode, port level imissed stats
561 * is supported. It only includes RPU drop stats.
563 * - HNS3_PKTS_DROP_STATS_MODE2
564 * This mode for kunpeng930. In this mode, imissed stats and oerrors
565 * stats is supported. Function level imissed stats is supported. It
566 * includes RPU drop stats in VF, and includes both RPU drop stats
567 * and SSU drop stats in PF. Oerror stats is also supported in PF.
569 uint8_t drop_stats_mode;
571 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
575 * HNS3_SPECIAL_PORT_HW_CKSUM_MODE/HNS3_SPECIAL_PORT_SW_CKSUM_MODE
577 * - HNS3_SPECIAL_PORT_SW_CKSUM_MODE
578 * In this mode, HW can not do checksum for special UDP port like
579 * 4789, 4790, 6081 for non-tunnel UDP packets and UDP tunnel
580 * packets without the PKT_TX_TUNEL_MASK in the mbuf. So, PMD need
581 * do the checksum for these packets to avoid a checksum error.
583 * - HNS3_SPECIAL_PORT_HW_CKSUM_MODE
584 * In this mode, HW does not have the preceding problems and can
585 * directly calculate the checksum of these UDP packets.
587 uint8_t udp_cksum_mode;
589 struct hns3_port_base_vlan_config port_base_vlan_cfg;
591 * PMD setup and configuration is not thread safe. Since it is not
592 * performance sensitive, it is better to guarantee thread-safety
593 * and add device level lock. Adapter control operations which
594 * change its state should acquire the lock.
597 enum hns3_adapter_state adapter_state;
598 struct hns3_reset_data reset;
601 #define HNS3_FLAG_TC_BASE_SCH_MODE 1
602 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2
604 /* vlan entry information. */
605 struct hns3_user_vlan_table {
606 LIST_ENTRY(hns3_user_vlan_table) next;
611 /* Vlan tag configuration for RX direction */
612 struct hns3_rx_vtag_cfg {
613 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */
614 bool strip_tag1_en; /* Whether strip inner vlan tag */
615 bool strip_tag2_en; /* Whether strip outer vlan tag */
617 * If strip_tag_en is enabled, this bit decide whether to map the vlan
620 bool strip_tag1_discard_en;
621 bool strip_tag2_discard_en;
623 * If this bit is enabled, only map inner/outer priority to descriptor
624 * and the vlan tag is always 0.
626 bool vlan1_vlan_prionly;
627 bool vlan2_vlan_prionly;
630 /* Vlan tag configuration for TX direction */
631 struct hns3_tx_vtag_cfg {
632 bool accept_tag1; /* Whether accept tag1 packet from host */
633 bool accept_untag1; /* Whether accept untag1 packet from host */
636 bool insert_tag1_en; /* Whether insert outer vlan tag */
637 bool insert_tag2_en; /* Whether insert inner vlan tag */
639 * In shift mode, hw will shift the sequence of port based VLAN and
642 bool tag_shift_mode_en; /* hw shift vlan tag automatically */
643 uint16_t default_tag1; /* The default outer vlan tag to insert */
644 uint16_t default_tag2; /* The default inner vlan tag to insert */
647 struct hns3_vtag_cfg {
648 struct hns3_rx_vtag_cfg rx_vcfg;
649 struct hns3_tx_vtag_cfg tx_vcfg;
652 /* Request types for IPC. */
653 enum hns3_mp_req_type {
654 HNS3_MP_REQ_START_RXTX = 1,
655 HNS3_MP_REQ_STOP_RXTX,
659 /* Pameters for IPC. */
660 struct hns3_mp_param {
661 enum hns3_mp_req_type type;
666 /* Request timeout for IPC. */
667 #define HNS3_MP_REQ_TIMEOUT_SEC 5
669 /* Key string for IPC. */
670 #define HNS3_MP_NAME "net_hns3_mp"
672 #define HNS3_L2TBL_NUM 4
673 #define HNS3_L3TBL_NUM 16
674 #define HNS3_L4TBL_NUM 16
675 #define HNS3_OL2TBL_NUM 4
676 #define HNS3_OL3TBL_NUM 16
677 #define HNS3_OL4TBL_NUM 16
678 #define HNS3_PTYPE_NUM 256
680 struct hns3_ptype_table {
682 * The next fields used to calc packet-type by the
683 * L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor.
685 uint32_t l2l3table[HNS3_L2TBL_NUM][HNS3_L3TBL_NUM];
686 uint32_t l4table[HNS3_L4TBL_NUM];
687 uint32_t inner_l2table[HNS3_L2TBL_NUM];
688 uint32_t inner_l3table[HNS3_L3TBL_NUM];
689 uint32_t inner_l4table[HNS3_L4TBL_NUM];
690 uint32_t ol2table[HNS3_OL2TBL_NUM];
691 uint32_t ol3table[HNS3_OL3TBL_NUM];
692 uint32_t ol4table[HNS3_OL4TBL_NUM];
695 * The next field used to calc packet-type by the PTYPE from the Rx
696 * descriptor, it functions only when firmware report the capability of
697 * HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it.
699 uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_min_aligned;
702 #define HNS3_FIXED_MAX_TQP_NUM_MODE 0
703 #define HNS3_FLEX_MAX_TQP_NUM_MODE 1
706 struct hns3_adapter *adapter;
708 uint16_t func_num; /* num functions of this pf, include pf and vfs */
712 * tqp_config_mode value range:
713 * HNS3_FIXED_MAX_TQP_NUM_MODE,
714 * HNS3_FLEX_MAX_TQP_NUM_MODE
716 * - HNS3_FIXED_MAX_TQP_NUM_MODE
717 * There is a limitation on the number of pf interrupts available for
718 * on some versions of network engines. In this case, the maximum
719 * queue number of pf can not be greater than the interrupt number,
720 * such as pf of network engine with revision_id 0x21. So the maximum
721 * number of queues must be fixed.
723 * - HNS3_FLEX_MAX_TQP_NUM_MODE
724 * In this mode, the maximum queue number of pf has not any constraint
725 * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF
726 * in the config file. Users can modify the macro according to their
727 * own application scenarios, which is more flexible to use.
729 uint8_t tqp_config_mode;
731 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
732 uint32_t tx_buf_size; /* Tx buffer size for each TC */
733 uint32_t dv_buf_size; /* Dv buffer size for each TC */
735 uint16_t mps; /* Max packet size */
738 uint8_t tc_max; /* max number of tc driver supported */
739 uint8_t local_max_tc; /* max number of local tc */
741 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */
743 bool support_fc_autoneg; /* support FC autonegotiate */
745 uint16_t wanted_umv_size;
746 uint16_t max_umv_size;
747 uint16_t used_umv_size;
749 bool support_sfp_query;
750 uint32_t fec_mode; /* current FEC mode for ethdev */
754 /* Stores timestamp of last received packet on dev */
755 uint64_t rx_timestamp;
757 struct hns3_vtag_cfg vtag_config;
758 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
760 struct hns3_fdir_info fdir; /* flow director info */
761 LIST_HEAD(counters, hns3_flow_counter) flow_counters;
763 struct hns3_tm_conf tm_conf;
767 HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED,
768 HNS3_PF_PUSH_LSC_CAP_SUPPORTED,
769 HNS3_PF_PUSH_LSC_CAP_UNKNOWN
773 struct hns3_adapter *adapter;
775 /* Whether PF support push link status change to VF */
776 uint16_t pf_push_lsc_cap;
779 * If PF support push link status change, VF still need send request to
780 * get link status in some cases (such as reset recover stage), so use
781 * the req_link_info_cnt to control max request count.
783 uint16_t req_link_info_cnt;
785 uint16_t poll_job_started; /* whether poll job is started */
788 struct hns3_adapter {
791 /* Specific for PF or VF */
792 bool is_vf; /* false - PF, true - VF */
798 uint32_t rx_func_hint;
799 uint32_t tx_func_hint;
801 struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
805 HNS3_IO_FUNC_HINT_NONE = 0,
806 HNS3_IO_FUNC_HINT_VEC,
807 HNS3_IO_FUNC_HINT_SVE,
808 HNS3_IO_FUNC_HINT_SIMPLE,
809 HNS3_IO_FUNC_HINT_COMMON
812 #define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint"
813 #define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint"
815 #define HNS3_DEV_SUPPORT_DCB_B 0x0
816 #define HNS3_DEV_SUPPORT_COPPER_B 0x1
817 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
818 #define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3
819 #define HNS3_DEV_SUPPORT_PTP_B 0x4
820 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5
821 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6
822 #define HNS3_DEV_SUPPORT_STASH_B 0x7
823 #define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9
824 #define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA
826 #define hns3_dev_dcb_supported(hw) \
827 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
829 /* Support copper media type */
830 #define hns3_dev_copper_supported(hw) \
831 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B)
833 /* Support UDP GSO offload */
834 #define hns3_dev_udp_gso_supported(hw) \
835 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
837 /* Support the queue region action rule of flow directory */
838 #define hns3_dev_fd_queue_region_supported(hw) \
839 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B)
841 /* Support PTP timestamp offload */
842 #define hns3_dev_ptp_supported(hw) \
843 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B)
845 #define hns3_dev_tx_push_supported(hw) \
846 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)
848 /* Support to Independently enable/disable/reset Tx or Rx queues */
849 #define hns3_dev_indep_txrx_supported(hw) \
850 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B)
852 #define hns3_dev_stash_supported(hw) \
853 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B)
855 #define hns3_dev_rxd_adv_layout_supported(hw) \
856 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B)
858 #define hns3_dev_outer_udp_cksum_supported(hw) \
859 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B)
861 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
862 (&((struct hns3_adapter *)adapter)->hw)
863 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \
864 (&((struct hns3_adapter *)adapter)->pf)
865 #define HNS3_DEV_PRIVATE_TO_VF(adapter) \
866 (&((struct hns3_adapter *)adapter)->vf)
867 #define HNS3_DEV_HW_TO_ADAPTER(hw) \
868 container_of(hw, struct hns3_adapter, hw)
870 static inline struct hns3_pf *HNS3_DEV_HW_TO_PF(struct hns3_hw *hw)
872 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw);
876 static inline struct hns3_vf *HNS3_DEV_HW_TO_VF(struct hns3_hw *hw)
878 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw);
882 #define hns3_set_field(origin, mask, shift, val) \
884 (origin) &= (~(mask)); \
885 (origin) |= ((val) << (shift)) & (mask); \
887 #define hns3_get_field(origin, mask, shift) \
888 (((origin) & (mask)) >> (shift))
889 #define hns3_set_bit(origin, shift, val) \
890 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val))
891 #define hns3_get_bit(origin, shift) \
892 hns3_get_field((origin), (0x1UL << (shift)), (shift))
894 #define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask))
897 * upper_32_bits - return bits 32-63 of a number
898 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
899 * the "right shift count >= width of type" warning when that quantity is
902 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
904 /* lower_32_bits - return bits 0-31 of a number */
905 #define lower_32_bits(n) ((uint32_t)(n))
907 #define BIT(nr) (1UL << (nr))
909 #define BIT_ULL(x) (1ULL << (x))
911 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
912 #define GENMASK(h, l) \
913 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
915 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
916 #define rounddown(x, y) ((x) - ((x) % (y)))
918 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
921 * Because hardware always access register in little-endian mode based on hns3
922 * network engine, so driver should also call rte_cpu_to_le_32 to convert data
923 * in little-endian mode before writing register and call rte_le_to_cpu_32 to
924 * convert data after reading from register.
926 * Here the driver encapsulates the data conversion operation in the register
927 * read/write operation function as below:
931 * Therefore, when calling these functions, conversion is not required again.
933 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
935 rte_write32(rte_cpu_to_le_32(value),
936 (volatile void *)((char *)base + reg));
940 * The optimized function for writing registers used in the '.rx_pkt_burst' and
941 * '.tx_pkt_burst' ops implementation function.
943 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value)
946 rte_write32_relaxed(rte_cpu_to_le_32(value), addr);
949 static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
951 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg));
952 return rte_le_to_cpu_32(read_val);
955 #define hns3_write_dev(a, reg, value) \
956 hns3_write_reg((a)->io_base, (reg), (value))
958 #define hns3_read_dev(a, reg) \
959 hns3_read_reg((a)->io_base, (reg))
961 #define ARRAY_SIZE(x) RTE_DIM(x)
963 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
965 act = (actions) + (index); \
966 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
968 act = actions + index; \
972 #define MSEC_PER_SEC 1000L
973 #define USEC_PER_MSEC 1000L
975 static inline uint64_t
976 get_timeofday_ms(void)
980 (void)gettimeofday(&tv, NULL);
982 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
985 static inline uint64_t
986 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
990 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;
995 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)
997 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);
1001 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)
1003 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);
1006 static inline int64_t
1007 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)
1009 uint64_t mask = (1UL << nr);
1011 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
1014 int hns3_buffer_alloc(struct hns3_hw *hw);
1015 int hns3_dev_flow_ops_get(struct rte_eth_dev *dev,
1016 const struct rte_flow_ops **ops);
1017 bool hns3_is_reset_pending(struct hns3_adapter *hns);
1018 bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
1019 void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query);
1020 void hns3_ether_format_addr(char *buf, uint16_t size,
1021 const struct rte_ether_addr *ether_addr);
1022 int hns3_dev_infos_get(struct rte_eth_dev *eth_dev,
1023 struct rte_eth_dev_info *info);
1024 void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1025 uint32_t link_speed, uint8_t link_duplex);
1026 void hns3_parse_devargs(struct rte_eth_dev *dev);
1027 void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported);
1028 int hns3_restore_ptp(struct hns3_adapter *hns);
1029 int hns3_mbuf_dyn_rx_timestamp_register(struct rte_eth_dev *dev,
1030 struct rte_eth_conf *conf);
1031 int hns3_ptp_init(struct hns3_hw *hw);
1032 int hns3_timesync_enable(struct rte_eth_dev *dev);
1033 int hns3_timesync_disable(struct rte_eth_dev *dev);
1034 int hns3_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
1035 struct timespec *timestamp,
1036 uint32_t flags __rte_unused);
1037 int hns3_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
1038 struct timespec *timestamp);
1039 int hns3_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts);
1040 int hns3_timesync_write_time(struct rte_eth_dev *dev,
1041 const struct timespec *ts);
1042 int hns3_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
1045 is_reset_pending(struct hns3_adapter *hns)
1049 ret = hns3vf_is_reset_pending(hns);
1051 ret = hns3_is_reset_pending(hns);
1055 static inline uint64_t
1056 hns3_txvlan_cap_get(struct hns3_hw *hw)
1058 if (hw->port_base_vlan_cfg.state)
1059 return DEV_TX_OFFLOAD_VLAN_INSERT;
1061 return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT;
1064 #endif /* _HNS3_ETHDEV_H_ */