1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #ifndef _HNS3_ETHDEV_H_
6 #define _HNS3_ETHDEV_H_
14 #include "hns3_fdir.h"
15 #include "hns3_stats.h"
18 #define PCI_VENDOR_ID_HUAWEI 0x19e5
21 #define HNS3_DEV_ID_GE 0xA220
22 #define HNS3_DEV_ID_25GE 0xA221
23 #define HNS3_DEV_ID_25GE_RDMA 0xA222
24 #define HNS3_DEV_ID_50GE_RDMA 0xA224
25 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226
26 #define HNS3_DEV_ID_100G_VF 0xA22E
27 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
29 /* PCI Config offsets */
30 #define HNS3_PCI_REVISION_ID 0x08
31 #define HNS3_PCI_REVISION_ID_LEN 1
33 #define HNS3_PF_FUNC_ID 0
34 #define HNS3_1ST_VF_FUNC_ID 1
36 #define HNS3_UC_MACADDR_NUM 128
37 #define HNS3_VF_UC_MACADDR_NUM 48
38 #define HNS3_MC_MACADDR_NUM 128
40 #define HNS3_MAX_BD_SIZE 65535
41 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8
42 #define HNS3_MAX_TSO_BD_PER_PKT 63
43 #define HNS3_MAX_FRAME_LEN 9728
44 #define HNS3_VLAN_TAG_SIZE 4
45 #define HNS3_DEFAULT_RX_BUF_LEN 2048
46 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
47 #define HNS3_MAX_TSO_HDR_SIZE 512
48 #define HNS3_MAX_TSO_HDR_BD_NUM 3
50 #define HNS3_ETH_OVERHEAD \
51 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
52 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD)
53 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
54 #define HNS3_DEFAULT_MTU 1500UL
55 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
56 #define HNS3_MIN_PKT_SIZE 60
61 #define HNS3_MAX_PF_NUM 8
62 #define HNS3_UMV_TBL_SIZE 3072
63 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \
64 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM)
66 #define HNS3_PF_CFG_BLOCK_SIZE 32
67 #define HNS3_PF_CFG_DESC_NUM \
68 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES)
70 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0
72 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5
73 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500
75 #define HNS3_QUIT_RESET_CNT 10
76 #define HNS3_QUIT_RESET_DELAY_MS 100
78 #define HNS3_POLL_RESPONE_MS 1
80 #define HNS3_MAX_USER_PRIO 8
90 #define HNS3_SCH_MODE_SP 0
91 #define HNS3_SCH_MODE_DWRR 1
94 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */
97 uint8_t tc_dwrr[HNS3_MAX_TC_NUM];
100 struct hns3_tc_info {
102 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */
105 uint8_t up_to_tc_map; /* user priority maping on the TC */
108 struct hns3_dcb_info {
110 uint8_t num_pg; /* It must be 1 if vNET-Base schd */
111 uint8_t pg_dwrr[HNS3_PG_NUM];
112 uint8_t prio_tc[HNS3_MAX_USER_PRIO];
113 struct hns3_pg_info pg_info[HNS3_PG_NUM];
114 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM];
115 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */
116 uint8_t pfc_en; /* Pfc enabled or not for user priority */
119 enum hns3_fc_status {
121 HNS3_FC_STATUS_MAC_PAUSE,
125 struct hns3_tc_queue_info {
126 uint8_t tqp_offset; /* TQP offset from base TQP */
127 uint8_t tqp_count; /* Total TQPs */
128 uint8_t tc; /* TC index */
129 bool enable; /* If this TC is enable or not */
133 uint8_t vmdq_vport_num;
135 uint16_t tqp_desc_num;
137 uint16_t rss_size_max;
140 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
141 uint8_t default_speed;
142 uint32_t numa_node_map;
143 uint8_t speed_ability;
148 enum hns3_media_type {
149 HNS3_MEDIA_TYPE_UNKNOWN,
150 HNS3_MEDIA_TYPE_FIBER,
151 HNS3_MEDIA_TYPE_COPPER,
152 HNS3_MEDIA_TYPE_BACKPLANE,
153 HNS3_MEDIA_TYPE_NONE,
157 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
158 bool default_addr_setted; /* whether default addr(mac_addr) is setted */
161 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
162 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
163 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
164 uint32_t link_speed; /* ETH_SPEED_NUM_ */
167 struct hns3_fake_queue_data {
168 void **rx_queues; /* Array of pointers to fake RX queues. */
169 void **tx_queues; /* Array of pointers to fake TX queues. */
170 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */
171 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
174 #define HNS3_PORT_BASE_VLAN_DISABLE 0
175 #define HNS3_PORT_BASE_VLAN_ENABLE 1
176 struct hns3_port_base_vlan_config {
181 /* Primary process maintains driver state in main thread.
184 * | UNINITIALIZED |<-----------+
185 * +---------------+ |
186 * |.eth_dev_init |.eth_dev_uninit
188 * +---------------+------------+
190 * +---------------+<-----------<---------------+
191 * |.dev_configure | |
193 * +---------------+------------+ |
195 * +---------------+----+ |
197 * | | +---------------+
199 * | | +---------------+
201 * V |.dev_configure |
202 * +---------------+----+ |.dev_close
203 * | CONFIGURED |----------------------------+
204 * +---------------+<-----------+
207 * +---------------+ |
208 * | STARTING |------------^
209 * +---------------+ failed |
211 * | +---------------+
213 * | +---------------+
216 * +---------------+------------+
220 enum hns3_adapter_state {
221 HNS3_NIC_UNINITIALIZED = 0,
222 HNS3_NIC_INITIALIZED,
223 HNS3_NIC_CONFIGURING,
234 /* Reset various stages, execute in order */
235 enum hns3_reset_stage {
236 /* Stop query services, stop transceiver, disable MAC */
238 /* Clear reset completion flags, disable send command */
240 /* Inform IMP to start resetting */
241 RESET_STAGE_REQ_HW_RESET,
242 /* Waiting for hardware reset to complete */
244 /* Reinitialize hardware */
245 RESET_STAGE_DEV_INIT,
246 /* Restore user settings and enable MAC */
248 /* Restart query services, start transceiver */
250 /* Not in reset state */
254 enum hns3_reset_level {
256 HNS3_VF_FUNC_RESET, /* A VF function reset */
258 * All VFs under a PF perform function reset.
259 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
260 * of the reset level and the one defined in kernel driver should be
263 HNS3_VF_PF_FUNC_RESET = 2,
265 * All VFs under a PF perform FLR reset.
266 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
267 * of the reset level and the one defined in kernel driver should be
270 HNS3_VF_FULL_RESET = 3,
271 HNS3_FLR_RESET, /* A VF perform FLR reset */
272 /* All VFs under the rootport perform a global or IMP reset */
274 HNS3_FUNC_RESET, /* A PF function reset */
275 /* All PFs under the rootport perform a global reset */
277 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
281 enum hns3_wait_result {
288 #define HNS3_RESET_SYNC_US 100000
290 struct hns3_reset_stats {
291 uint64_t request_cnt; /* Total request reset times */
292 uint64_t global_cnt; /* Total GLOBAL reset times */
293 uint64_t imp_cnt; /* Total IMP reset times */
294 uint64_t exec_cnt; /* Total reset executive times */
295 uint64_t success_cnt; /* Total reset successful times */
296 uint64_t fail_cnt; /* Total reset failed times */
297 uint64_t merge_cnt; /* Total merged in high reset times */
300 typedef bool (*check_completion_func)(struct hns3_hw *hw);
302 struct hns3_wait_data {
307 enum hns3_wait_result result;
308 check_completion_func check_completion;
311 struct hns3_reset_ops {
312 void (*reset_service)(void *arg);
313 int (*stop_service)(struct hns3_adapter *hns);
314 int (*prepare_reset)(struct hns3_adapter *hns);
315 int (*wait_hardware_ready)(struct hns3_adapter *hns);
316 int (*reinit_dev)(struct hns3_adapter *hns);
317 int (*restore_conf)(struct hns3_adapter *hns);
318 int (*start_service)(struct hns3_adapter *hns);
328 struct hns3_reset_data {
329 enum hns3_reset_stage stage;
330 rte_atomic16_t schedule;
331 /* Reset flag, covering the entire reset process */
332 rte_atomic16_t resetting;
333 /* Used to disable sending cmds during reset */
334 rte_atomic16_t disable_cmd;
335 /* The reset level being processed */
336 enum hns3_reset_level level;
337 /* Reset level set, each bit represents a reset level */
339 /* Request reset level set, from interrupt or mailbox */
341 int attempts; /* Reset failure retry */
342 int retries; /* Timeout failure retry in reset_post */
344 * At the time of global or IMP reset, the command cannot be sent to
345 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the
346 * reset process, so the mbuf is required to be released after the reset
347 * is completed.The mbuf_deferred_free is used to mark whether mbuf
348 * needs to be released.
350 bool mbuf_deferred_free;
351 struct timeval start_time;
352 struct hns3_reset_stats stats;
353 const struct hns3_reset_ops *ops;
354 struct hns3_wait_data *wait_data;
358 struct rte_eth_dev_data *data;
360 uint8_t revision; /* PCI revision, low byte of class word */
362 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
363 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */
364 pthread_t irq_thread_id;
366 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
367 struct hns3_tqp_stats tqp_stats;
368 /* Include Mac stats | Rx stats | Tx stats */
369 struct hns3_mac_stats mac_stats;
373 uint16_t total_tqps_num; /* total task queue pairs of this PF */
374 uint16_t tqps_num; /* num task queue pairs of this function */
375 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
376 uint16_t rss_size_max; /* HW defined max RSS task queue */
378 uint16_t num_tx_desc; /* desc num of per tx queue */
379 uint16_t num_rx_desc; /* desc num of per rx queue */
381 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
382 int mc_addrs_num; /* Multicast mac addresses number */
384 /* The configuration info of RSS */
385 struct hns3_rss_conf rss_info;
386 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
388 uint8_t num_tc; /* Total number of enabled TCs */
390 enum hns3_fc_mode current_mode;
391 enum hns3_fc_mode requested_mode;
392 struct hns3_dcb_info dcb_info;
393 enum hns3_fc_status current_fc_status; /* current flow control status */
394 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
395 uint16_t used_rx_queues;
396 uint16_t used_tx_queues;
398 /* Config max queue numbers between rx and tx queues from user */
399 uint16_t cfg_max_queues;
400 struct hns3_fake_queue_data fkq_data; /* fake queue data */
401 uint16_t alloc_rss_size; /* RX queue number per TC */
402 uint16_t tx_qnum_per_tc; /* TX queue number per TC */
406 struct hns3_port_base_vlan_config port_base_vlan_cfg;
408 * PMD setup and configuration is not thread safe. Since it is not
409 * performance sensitive, it is better to guarantee thread-safety
410 * and add device level lock. Adapter control operations which
411 * change its state should acquire the lock.
414 enum hns3_adapter_state adapter_state;
415 struct hns3_reset_data reset;
418 #define HNS3_FLAG_TC_BASE_SCH_MODE 1
419 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2
421 struct hns3_err_msix_intr_stats {
422 uint64_t mac_afifo_tnl_intr_cnt;
423 uint64_t ppu_mpf_abnormal_intr_st2_cnt;
424 uint64_t ssu_port_based_pf_intr_cnt;
425 uint64_t ppp_pf_abnormal_intr_cnt;
426 uint64_t ppu_pf_abnormal_intr_cnt;
429 /* vlan entry information. */
430 struct hns3_user_vlan_table {
431 LIST_ENTRY(hns3_user_vlan_table) next;
436 /* Vlan tag configuration for RX direction */
437 struct hns3_rx_vtag_cfg {
438 uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */
439 uint8_t strip_tag1_en; /* Whether strip inner vlan tag */
440 uint8_t strip_tag2_en; /* Whether strip outer vlan tag */
441 uint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */
442 uint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */
445 /* Vlan tag configuration for TX direction */
446 struct hns3_tx_vtag_cfg {
447 bool accept_tag1; /* Whether accept tag1 packet from host */
448 bool accept_untag1; /* Whether accept untag1 packet from host */
451 bool insert_tag1_en; /* Whether insert inner vlan tag */
452 bool insert_tag2_en; /* Whether insert outer vlan tag */
453 uint16_t default_tag1; /* The default inner vlan tag to insert */
454 uint16_t default_tag2; /* The default outer vlan tag to insert */
457 struct hns3_vtag_cfg {
458 struct hns3_rx_vtag_cfg rx_vcfg;
459 struct hns3_tx_vtag_cfg tx_vcfg;
462 /* Request types for IPC. */
463 enum hns3_mp_req_type {
464 HNS3_MP_REQ_START_RXTX = 1,
465 HNS3_MP_REQ_STOP_RXTX,
469 /* Pameters for IPC. */
470 struct hns3_mp_param {
471 enum hns3_mp_req_type type;
476 /* Request timeout for IPC. */
477 #define HNS3_MP_REQ_TIMEOUT_SEC 5
479 /* Key string for IPC. */
480 #define HNS3_MP_NAME "net_hns3_mp"
483 struct hns3_adapter *adapter;
485 uint16_t func_num; /* num functions of this pf, include pf and vfs */
487 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
488 uint32_t tx_buf_size; /* Tx buffer size for each TC */
489 uint32_t dv_buf_size; /* Dv buffer size for each TC */
491 uint16_t mps; /* Max packet size */
494 uint8_t tc_max; /* max number of tc driver supported */
495 uint8_t local_max_tc; /* max number of local tc */
497 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */
499 bool support_fc_autoneg; /* support FC autonegotiate */
501 uint16_t wanted_umv_size;
502 uint16_t max_umv_size;
503 uint16_t used_umv_size;
505 /* Statistics information for abnormal interrupt */
506 struct hns3_err_msix_intr_stats abn_int_stats;
508 bool support_sfp_query;
510 struct hns3_vtag_cfg vtag_config;
511 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
513 struct hns3_fdir_info fdir; /* flow director info */
514 LIST_HEAD(counters, hns3_flow_counter) flow_counters;
518 struct hns3_adapter *adapter;
521 struct hns3_adapter {
524 /* Specific for PF or VF */
525 bool is_vf; /* false - PF, true - VF */
532 #define HNS3_DEV_SUPPORT_DCB_B 0x0
534 #define hns3_dev_dcb_supported(hw) \
535 hns3_get_bit((hw)->flag, HNS3_DEV_SUPPORT_DCB_B)
537 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
538 (&((struct hns3_adapter *)adapter)->hw)
539 #define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \
540 ((struct hns3_adapter *)adapter)
541 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \
542 (&((struct hns3_adapter *)adapter)->pf)
543 #define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \
544 (&((struct hns3_adapter *)adapter)->vf)
545 #define HNS3_DEV_HW_TO_ADAPTER(hw) \
546 container_of(hw, struct hns3_adapter, hw)
548 #define hns3_set_field(origin, mask, shift, val) \
550 (origin) &= (~(mask)); \
551 (origin) |= ((val) << (shift)) & (mask); \
553 #define hns3_get_field(origin, mask, shift) \
554 (((origin) & (mask)) >> (shift))
555 #define hns3_set_bit(origin, shift, val) \
556 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val))
557 #define hns3_get_bit(origin, shift) \
558 hns3_get_field((origin), (0x1UL << (shift)), (shift))
561 * upper_32_bits - return bits 32-63 of a number
562 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
563 * the "right shift count >= width of type" warning when that quantity is
566 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
568 /* lower_32_bits - return bits 0-31 of a number */
569 #define lower_32_bits(n) ((uint32_t)(n))
571 #define BIT(nr) (1UL << (nr))
573 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
574 #define GENMASK(h, l) \
575 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
577 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
578 #define rounddown(x, y) ((x) - ((x) % (y)))
580 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
582 #define max_t(type, x, y) ({ \
585 __max1 > __max2 ? __max1 : __max2; })
587 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
589 rte_write32(value, (volatile void *)((char *)base + reg));
592 static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
594 return rte_read32((volatile void *)((char *)base + reg));
597 #define hns3_write_dev(a, reg, value) \
598 hns3_write_reg((a)->io_base, (reg), (value))
600 #define hns3_read_dev(a, reg) \
601 hns3_read_reg((a)->io_base, (reg))
603 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
605 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
607 act = (actions) + (index); \
608 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
610 act = actions + index; \
614 #define MSEC_PER_SEC 1000L
615 #define USEC_PER_MSEC 1000L
617 static inline uint64_t
618 get_timeofday_ms(void)
622 (void)gettimeofday(&tv, NULL);
624 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
627 static inline uint64_t
628 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
632 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;
637 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)
639 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);
643 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)
645 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);
648 static inline int64_t
649 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)
651 uint64_t mask = (1UL << nr);
653 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
656 int hns3_buffer_alloc(struct hns3_hw *hw);
657 int hns3_config_gro(struct hns3_hw *hw, bool en);
658 int hns3_dev_filter_ctrl(struct rte_eth_dev *dev,
659 enum rte_filter_type filter_type,
660 enum rte_filter_op filter_op, void *arg);
661 bool hns3_is_reset_pending(struct hns3_adapter *hns);
662 bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
663 void hns3_update_link_status(struct hns3_hw *hw);
666 is_reset_pending(struct hns3_adapter *hns)
670 ret = hns3vf_is_reset_pending(hns);
672 ret = hns3_is_reset_pending(hns);
676 #endif /* _HNS3_ETHDEV_H_ */