1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #ifndef _HNS3_ETHDEV_H_
6 #define _HNS3_ETHDEV_H_
14 #include "hns3_fdir.h"
15 #include "hns3_stats.h"
18 #define PCI_VENDOR_ID_HUAWEI 0x19e5
21 #define HNS3_DEV_ID_GE 0xA220
22 #define HNS3_DEV_ID_25GE 0xA221
23 #define HNS3_DEV_ID_25GE_RDMA 0xA222
24 #define HNS3_DEV_ID_50GE_RDMA 0xA224
25 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226
26 #define HNS3_DEV_ID_100G_VF 0xA22E
27 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
29 #define HNS3_UC_MACADDR_NUM 128
30 #define HNS3_VF_UC_MACADDR_NUM 48
31 #define HNS3_MC_MACADDR_NUM 128
33 #define HNS3_MAX_BD_SIZE 65535
34 #define HNS3_MAX_TX_BD_PER_PKT 8
35 #define HNS3_MAX_FRAME_LEN 9728
36 #define HNS3_VLAN_TAG_SIZE 4
37 #define HNS3_DEFAULT_RX_BUF_LEN 2048
39 #define HNS3_ETH_OVERHEAD \
40 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
41 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD)
42 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
43 #define HNS3_DEFAULT_MTU 1500UL
44 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
45 #define HNS3_MIN_PKT_SIZE 60
50 #define HNS3_MAX_PF_NUM 8
51 #define HNS3_UMV_TBL_SIZE 3072
52 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \
53 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM)
55 #define HNS3_PF_CFG_BLOCK_SIZE 32
56 #define HNS3_PF_CFG_DESC_NUM \
57 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES)
59 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0
61 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5
62 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500
64 #define HNS3_QUIT_RESET_CNT 10
65 #define HNS3_QUIT_RESET_DELAY_MS 100
67 #define HNS3_POLL_RESPONE_MS 1
69 #define HNS3_MAX_USER_PRIO 8
79 #define HNS3_SCH_MODE_SP 0
80 #define HNS3_SCH_MODE_DWRR 1
83 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */
86 uint8_t tc_dwrr[HNS3_MAX_TC_NUM];
91 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */
94 uint8_t up_to_tc_map; /* user priority maping on the TC */
97 struct hns3_dcb_info {
99 uint8_t num_pg; /* It must be 1 if vNET-Base schd */
100 uint8_t pg_dwrr[HNS3_PG_NUM];
101 uint8_t prio_tc[HNS3_MAX_USER_PRIO];
102 struct hns3_pg_info pg_info[HNS3_PG_NUM];
103 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM];
104 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */
105 uint8_t pfc_en; /* Pfc enabled or not for user priority */
108 enum hns3_fc_status {
110 HNS3_FC_STATUS_MAC_PAUSE,
114 struct hns3_tc_queue_info {
115 uint8_t tqp_offset; /* TQP offset from base TQP */
116 uint8_t tqp_count; /* Total TQPs */
117 uint8_t tc; /* TC index */
118 bool enable; /* If this TC is enable or not */
122 uint8_t vmdq_vport_num;
124 uint16_t tqp_desc_num;
126 uint16_t rss_size_max;
129 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
130 uint8_t default_speed;
131 uint32_t numa_node_map;
132 uint8_t speed_ability;
137 enum hns3_media_type {
138 HNS3_MEDIA_TYPE_UNKNOWN,
139 HNS3_MEDIA_TYPE_FIBER,
140 HNS3_MEDIA_TYPE_COPPER,
141 HNS3_MEDIA_TYPE_BACKPLANE,
142 HNS3_MEDIA_TYPE_NONE,
146 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
147 bool default_addr_setted; /* whether default addr(mac_addr) is setted */
150 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
151 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
152 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
153 uint32_t link_speed; /* ETH_SPEED_NUM_ */
156 struct hns3_fake_queue_data {
157 void **rx_queues; /* Array of pointers to fake RX queues. */
158 void **tx_queues; /* Array of pointers to fake TX queues. */
159 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */
160 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
163 /* Primary process maintains driver state in main thread.
166 * | UNINITIALIZED |<-----------+
167 * +---------------+ |
168 * |.eth_dev_init |.eth_dev_uninit
170 * +---------------+------------+
172 * +---------------+<-----------<---------------+
173 * |.dev_configure | |
175 * +---------------+------------+ |
177 * +---------------+----+ |
179 * | | +---------------+
181 * | | +---------------+
183 * V |.dev_configure |
184 * +---------------+----+ |.dev_close
185 * | CONFIGURED |----------------------------+
186 * +---------------+<-----------+
189 * +---------------+ |
190 * | STARTING |------------^
191 * +---------------+ failed |
193 * | +---------------+
195 * | +---------------+
198 * +---------------+------------+
202 enum hns3_adapter_state {
203 HNS3_NIC_UNINITIALIZED = 0,
204 HNS3_NIC_INITIALIZED,
205 HNS3_NIC_CONFIGURING,
216 /* Reset various stages, execute in order */
217 enum hns3_reset_stage {
218 /* Stop query services, stop transceiver, disable MAC */
220 /* Clear reset completion flags, disable send command */
222 /* Inform IMP to start resetting */
223 RESET_STAGE_REQ_HW_RESET,
224 /* Waiting for hardware reset to complete */
226 /* Reinitialize hardware */
227 RESET_STAGE_DEV_INIT,
228 /* Restore user settings and enable MAC */
230 /* Restart query services, start transceiver */
232 /* Not in reset state */
236 enum hns3_reset_level {
238 HNS3_VF_FUNC_RESET, /* A VF function reset */
240 * All VFs under a PF perform function reset.
241 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
242 * of the reset level and the one defined in kernel driver should be
245 HNS3_VF_PF_FUNC_RESET = 2,
247 * All VFs under a PF perform FLR reset.
248 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
249 * of the reset level and the one defined in kernel driver should be
252 HNS3_VF_FULL_RESET = 3,
253 HNS3_FLR_RESET, /* A VF perform FLR reset */
254 /* All VFs under the rootport perform a global or IMP reset */
256 HNS3_FUNC_RESET, /* A PF function reset */
257 /* All PFs under the rootport perform a global reset */
259 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
263 enum hns3_wait_result {
270 #define HNS3_RESET_SYNC_US 100000
272 struct hns3_reset_stats {
273 uint64_t request_cnt; /* Total request reset times */
274 uint64_t global_cnt; /* Total GLOBAL reset times */
275 uint64_t imp_cnt; /* Total IMP reset times */
276 uint64_t exec_cnt; /* Total reset executive times */
277 uint64_t success_cnt; /* Total reset successful times */
278 uint64_t fail_cnt; /* Total reset failed times */
279 uint64_t merge_cnt; /* Total merged in high reset times */
282 typedef bool (*check_completion_func)(struct hns3_hw *hw);
284 struct hns3_wait_data {
289 enum hns3_wait_result result;
290 check_completion_func check_completion;
293 struct hns3_reset_ops {
294 void (*reset_service)(void *arg);
295 int (*stop_service)(struct hns3_adapter *hns);
296 int (*prepare_reset)(struct hns3_adapter *hns);
297 int (*wait_hardware_ready)(struct hns3_adapter *hns);
298 int (*reinit_dev)(struct hns3_adapter *hns);
299 int (*restore_conf)(struct hns3_adapter *hns);
300 int (*start_service)(struct hns3_adapter *hns);
310 struct hns3_reset_data {
311 enum hns3_reset_stage stage;
312 rte_atomic16_t schedule;
313 /* Reset flag, covering the entire reset process */
314 rte_atomic16_t resetting;
315 /* Used to disable sending cmds during reset */
316 rte_atomic16_t disable_cmd;
317 /* The reset level being processed */
318 enum hns3_reset_level level;
319 /* Reset level set, each bit represents a reset level */
321 /* Request reset level set, from interrupt or mailbox */
323 int attempts; /* Reset failure retry */
324 int retries; /* Timeout failure retry in reset_post */
326 * At the time of global or IMP reset, the command cannot be sent to
327 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the
328 * reset process, so the mbuf is required to be released after the reset
329 * is completed.The mbuf_deferred_free is used to mark whether mbuf
330 * needs to be released.
332 bool mbuf_deferred_free;
333 struct timeval start_time;
334 struct hns3_reset_stats stats;
335 const struct hns3_reset_ops *ops;
336 struct hns3_wait_data *wait_data;
340 struct rte_eth_dev_data *data;
343 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
344 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */
345 pthread_t irq_thread_id;
347 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
348 struct hns3_tqp_stats tqp_stats;
349 /* Include Mac stats | Rx stats | Tx stats */
350 struct hns3_mac_stats mac_stats;
354 uint16_t total_tqps_num; /* total task queue pairs of this PF */
355 uint16_t tqps_num; /* num task queue pairs of this function */
356 uint16_t rss_size_max; /* HW defined max RSS task queue */
358 uint16_t num_tx_desc; /* desc num of per tx queue */
359 uint16_t num_rx_desc; /* desc num of per rx queue */
361 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
362 int mc_addrs_num; /* Multicast mac addresses number */
364 /* The configuration info of RSS */
365 struct hns3_rss_conf rss_info;
367 uint8_t num_tc; /* Total number of enabled TCs */
369 enum hns3_fc_mode current_mode;
370 enum hns3_fc_mode requested_mode;
371 struct hns3_dcb_info dcb_info;
372 enum hns3_fc_status current_fc_status; /* current flow control status */
373 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
374 uint16_t used_rx_queues;
375 uint16_t used_tx_queues;
377 /* Config max queue numbers between rx and tx queues from user */
378 uint16_t cfg_max_queues;
379 struct hns3_fake_queue_data fkq_data; /* fake queue data */
380 uint16_t alloc_rss_size; /* RX queue number per TC */
381 uint16_t tx_qnum_per_tc; /* TX queue number per TC */
385 * PMD setup and configuration is not thread safe. Since it is not
386 * performance sensitive, it is better to guarantee thread-safety
387 * and add device level lock. Adapter control operations which
388 * change its state should acquire the lock.
391 enum hns3_adapter_state adapter_state;
392 struct hns3_reset_data reset;
395 #define HNS3_FLAG_TC_BASE_SCH_MODE 1
396 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2
398 struct hns3_err_msix_intr_stats {
399 uint64_t mac_afifo_tnl_intr_cnt;
400 uint64_t ppu_mpf_abnormal_intr_st2_cnt;
401 uint64_t ssu_port_based_pf_intr_cnt;
402 uint64_t ppp_pf_abnormal_intr_cnt;
403 uint64_t ppu_pf_abnormal_intr_cnt;
406 /* vlan entry information. */
407 struct hns3_user_vlan_table {
408 LIST_ENTRY(hns3_user_vlan_table) next;
413 struct hns3_port_base_vlan_config {
418 /* Vlan tag configuration for RX direction */
419 struct hns3_rx_vtag_cfg {
420 uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */
421 uint8_t strip_tag1_en; /* Whether strip inner vlan tag */
422 uint8_t strip_tag2_en; /* Whether strip outer vlan tag */
423 uint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */
424 uint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */
427 /* Vlan tag configuration for TX direction */
428 struct hns3_tx_vtag_cfg {
429 bool accept_tag1; /* Whether accept tag1 packet from host */
430 bool accept_untag1; /* Whether accept untag1 packet from host */
433 bool insert_tag1_en; /* Whether insert inner vlan tag */
434 bool insert_tag2_en; /* Whether insert outer vlan tag */
435 uint16_t default_tag1; /* The default inner vlan tag to insert */
436 uint16_t default_tag2; /* The default outer vlan tag to insert */
439 struct hns3_vtag_cfg {
440 struct hns3_rx_vtag_cfg rx_vcfg;
441 struct hns3_tx_vtag_cfg tx_vcfg;
444 /* Request types for IPC. */
445 enum hns3_mp_req_type {
446 HNS3_MP_REQ_START_RXTX = 1,
447 HNS3_MP_REQ_STOP_RXTX,
451 /* Pameters for IPC. */
452 struct hns3_mp_param {
453 enum hns3_mp_req_type type;
458 /* Request timeout for IPC. */
459 #define HNS3_MP_REQ_TIMEOUT_SEC 5
461 /* Key string for IPC. */
462 #define HNS3_MP_NAME "net_hns3_mp"
465 struct hns3_adapter *adapter;
468 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
469 uint32_t tx_buf_size; /* Tx buffer size for each TC */
470 uint32_t dv_buf_size; /* Dv buffer size for each TC */
472 uint16_t mps; /* Max packet size */
475 uint8_t tc_max; /* max number of tc driver supported */
476 uint8_t local_max_tc; /* max number of local tc */
478 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */
480 bool support_fc_autoneg; /* support FC autonegotiate */
482 uint16_t wanted_umv_size;
483 uint16_t max_umv_size;
484 uint16_t used_umv_size;
486 /* Statistics information for abnormal interrupt */
487 struct hns3_err_msix_intr_stats abn_int_stats;
489 bool support_sfp_query;
491 struct hns3_vtag_cfg vtag_config;
492 struct hns3_port_base_vlan_config port_base_vlan_cfg;
493 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
495 struct hns3_fdir_info fdir; /* flow director info */
496 LIST_HEAD(counters, hns3_flow_counter) flow_counters;
500 struct hns3_adapter *adapter;
503 struct hns3_adapter {
506 /* Specific for PF or VF */
507 bool is_vf; /* false - PF, true - VF */
514 #define HNS3_DEV_SUPPORT_DCB_B 0x0
516 #define hns3_dev_dcb_supported(hw) \
517 hns3_get_bit((hw)->flag, HNS3_DEV_SUPPORT_DCB_B)
519 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
520 (&((struct hns3_adapter *)adapter)->hw)
521 #define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \
522 ((struct hns3_adapter *)adapter)
523 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \
524 (&((struct hns3_adapter *)adapter)->pf)
525 #define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \
526 (&((struct hns3_adapter *)adapter)->vf)
527 #define HNS3_DEV_HW_TO_ADAPTER(hw) \
528 container_of(hw, struct hns3_adapter, hw)
530 #define hns3_set_field(origin, mask, shift, val) \
532 (origin) &= (~(mask)); \
533 (origin) |= ((val) << (shift)) & (mask); \
535 #define hns3_get_field(origin, mask, shift) \
536 (((origin) & (mask)) >> (shift))
537 #define hns3_set_bit(origin, shift, val) \
538 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val))
539 #define hns3_get_bit(origin, shift) \
540 hns3_get_field((origin), (0x1UL << (shift)), (shift))
543 * upper_32_bits - return bits 32-63 of a number
544 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
545 * the "right shift count >= width of type" warning when that quantity is
548 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
550 /* lower_32_bits - return bits 0-31 of a number */
551 #define lower_32_bits(n) ((uint32_t)(n))
553 #define BIT(nr) (1UL << (nr))
555 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
556 #define GENMASK(h, l) \
557 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
559 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
560 #define rounddown(x, y) ((x) - ((x) % (y)))
562 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
564 #define max_t(type, x, y) ({ \
567 __max1 > __max2 ? __max1 : __max2; })
569 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
571 rte_write32(value, (volatile void *)((char *)base + reg));
574 static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
576 return rte_read32((volatile void *)((char *)base + reg));
579 #define hns3_write_dev(a, reg, value) \
580 hns3_write_reg((a)->io_base, (reg), (value))
582 #define hns3_read_dev(a, reg) \
583 hns3_read_reg((a)->io_base, (reg))
585 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
587 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
589 act = (actions) + (index); \
590 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
592 act = actions + index; \
596 #define MSEC_PER_SEC 1000L
597 #define USEC_PER_MSEC 1000L
599 static inline uint64_t
600 get_timeofday_ms(void)
604 (void)gettimeofday(&tv, NULL);
606 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
609 static inline uint64_t
610 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
614 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;
619 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)
621 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);
625 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)
627 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);
630 static inline int64_t
631 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)
633 uint64_t mask = (1UL << nr);
635 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
638 int hns3_buffer_alloc(struct hns3_hw *hw);
639 int hns3_config_gro(struct hns3_hw *hw, bool en);
640 int hns3_dev_filter_ctrl(struct rte_eth_dev *dev,
641 enum rte_filter_type filter_type,
642 enum rte_filter_op filter_op, void *arg);
643 bool hns3_is_reset_pending(struct hns3_adapter *hns);
644 bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
645 void hns3_update_link_status(struct hns3_hw *hw);
648 is_reset_pending(struct hns3_adapter *hns)
652 ret = hns3vf_is_reset_pending(hns);
654 ret = hns3_is_reset_pending(hns);
658 #endif /* _HNS3_ETHDEV_H_ */