1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #ifndef _HNS3_ETHDEV_H_
6 #define _HNS3_ETHDEV_H_
14 #include "hns3_fdir.h"
15 #include "hns3_stats.h"
18 #define PCI_VENDOR_ID_HUAWEI 0x19e5
21 #define HNS3_DEV_ID_GE 0xA220
22 #define HNS3_DEV_ID_25GE 0xA221
23 #define HNS3_DEV_ID_25GE_RDMA 0xA222
24 #define HNS3_DEV_ID_50GE_RDMA 0xA224
25 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226
26 #define HNS3_DEV_ID_200G_RDMA 0xA228
27 #define HNS3_DEV_ID_100G_VF 0xA22E
28 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
30 /* PCI Config offsets */
31 #define HNS3_PCI_REVISION_ID 0x08
32 #define HNS3_PCI_REVISION_ID_LEN 1
34 #define PCI_REVISION_ID_HIP08_B 0x21
35 #define PCI_REVISION_ID_HIP09_A 0x30
37 #define HNS3_PF_FUNC_ID 0
38 #define HNS3_1ST_VF_FUNC_ID 1
40 #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0
41 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1
43 #define HNS3_UC_MACADDR_NUM 128
44 #define HNS3_VF_UC_MACADDR_NUM 48
45 #define HNS3_MC_MACADDR_NUM 128
47 #define HNS3_MAX_BD_SIZE 65535
48 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8
49 #define HNS3_MAX_TSO_BD_PER_PKT 63
50 #define HNS3_MAX_FRAME_LEN 9728
51 #define HNS3_VLAN_TAG_SIZE 4
52 #define HNS3_DEFAULT_RX_BUF_LEN 2048
53 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
54 #define HNS3_MAX_TSO_HDR_SIZE 512
55 #define HNS3_MAX_TSO_HDR_BD_NUM 3
56 #define HNS3_MAX_LRO_SIZE 64512
58 #define HNS3_ETH_OVERHEAD \
59 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
60 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD)
61 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
62 #define HNS3_DEFAULT_MTU 1500UL
63 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
64 #define HNS3_HIP08_MIN_TX_PKT_LEN 33
65 #define HNS3_HIP09_MIN_TX_PKT_LEN 9
67 #define HNS3_BITS_PER_BYTE 8
72 #define HNS3_MAX_PF_NUM 8
73 #define HNS3_UMV_TBL_SIZE 3072
74 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \
75 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM)
77 #define HNS3_PF_CFG_BLOCK_SIZE 32
78 #define HNS3_PF_CFG_DESC_NUM \
79 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES)
81 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0
83 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5
84 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500
86 #define HNS3_QUIT_RESET_CNT 10
87 #define HNS3_QUIT_RESET_DELAY_MS 100
89 #define HNS3_POLL_RESPONE_MS 1
91 #define HNS3_MAX_USER_PRIO 8
101 #define HNS3_SCH_MODE_SP 0
102 #define HNS3_SCH_MODE_DWRR 1
103 struct hns3_pg_info {
105 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */
108 uint8_t tc_dwrr[HNS3_MAX_TC_NUM];
111 struct hns3_tc_info {
113 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */
116 uint8_t up_to_tc_map; /* user priority maping on the TC */
119 struct hns3_dcb_info {
121 uint8_t num_pg; /* It must be 1 if vNET-Base schd */
122 uint8_t pg_dwrr[HNS3_PG_NUM];
123 uint8_t prio_tc[HNS3_MAX_USER_PRIO];
124 struct hns3_pg_info pg_info[HNS3_PG_NUM];
125 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM];
126 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */
127 uint8_t pfc_en; /* Pfc enabled or not for user priority */
130 enum hns3_fc_status {
132 HNS3_FC_STATUS_MAC_PAUSE,
136 struct hns3_tc_queue_info {
137 uint8_t tqp_offset; /* TQP offset from base TQP */
138 uint8_t tqp_count; /* Total TQPs */
139 uint8_t tc; /* TC index */
140 bool enable; /* If this TC is enable or not */
144 uint8_t vmdq_vport_num;
146 uint16_t tqp_desc_num;
148 uint16_t rss_size_max;
151 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
152 uint8_t default_speed;
153 uint32_t numa_node_map;
154 uint8_t speed_ability;
159 enum hns3_media_type {
160 HNS3_MEDIA_TYPE_UNKNOWN,
161 HNS3_MEDIA_TYPE_FIBER,
162 HNS3_MEDIA_TYPE_COPPER,
163 HNS3_MEDIA_TYPE_BACKPLANE,
164 HNS3_MEDIA_TYPE_NONE,
168 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
169 bool default_addr_setted; /* whether default addr(mac_addr) is setted */
172 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
173 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
174 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
175 uint32_t link_speed; /* ETH_SPEED_NUM_ */
178 struct hns3_fake_queue_data {
179 void **rx_queues; /* Array of pointers to fake RX queues. */
180 void **tx_queues; /* Array of pointers to fake TX queues. */
181 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */
182 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
185 #define HNS3_PORT_BASE_VLAN_DISABLE 0
186 #define HNS3_PORT_BASE_VLAN_ENABLE 1
187 struct hns3_port_base_vlan_config {
192 /* Primary process maintains driver state in main thread.
195 * | UNINITIALIZED |<-----------+
196 * +---------------+ |
197 * |.eth_dev_init |.eth_dev_uninit
199 * +---------------+------------+
201 * +---------------+<-----------<---------------+
202 * |.dev_configure | |
204 * +---------------+------------+ |
206 * +---------------+----+ |
208 * | | +---------------+
210 * | | +---------------+
212 * V |.dev_configure |
213 * +---------------+----+ |.dev_close
214 * | CONFIGURED |----------------------------+
215 * +---------------+<-----------+
218 * +---------------+ |
219 * | STARTING |------------^
220 * +---------------+ failed |
222 * | +---------------+
224 * | +---------------+
227 * +---------------+------------+
231 enum hns3_adapter_state {
232 HNS3_NIC_UNINITIALIZED = 0,
233 HNS3_NIC_INITIALIZED,
234 HNS3_NIC_CONFIGURING,
245 /* Reset various stages, execute in order */
246 enum hns3_reset_stage {
247 /* Stop query services, stop transceiver, disable MAC */
249 /* Clear reset completion flags, disable send command */
251 /* Inform IMP to start resetting */
252 RESET_STAGE_REQ_HW_RESET,
253 /* Waiting for hardware reset to complete */
255 /* Reinitialize hardware */
256 RESET_STAGE_DEV_INIT,
257 /* Restore user settings and enable MAC */
259 /* Restart query services, start transceiver */
261 /* Not in reset state */
265 enum hns3_reset_level {
267 HNS3_VF_FUNC_RESET, /* A VF function reset */
269 * All VFs under a PF perform function reset.
270 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
271 * of the reset level and the one defined in kernel driver should be
274 HNS3_VF_PF_FUNC_RESET = 2,
276 * All VFs under a PF perform FLR reset.
277 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
278 * of the reset level and the one defined in kernel driver should be
281 * According to the protocol of PCIe, FLR to a PF resets the PF state as
282 * well as the SR-IOV extended capability including VF Enable which
283 * means that VFs no longer exist.
285 * In PF FLR, the register state of VF is not reliable, VF's driver
286 * should not access the registers of the VF device.
288 HNS3_VF_FULL_RESET = 3,
289 HNS3_FLR_RESET, /* A VF perform FLR reset */
290 /* All VFs under the rootport perform a global or IMP reset */
292 HNS3_FUNC_RESET, /* A PF function reset */
293 /* All PFs under the rootport perform a global reset */
295 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
299 enum hns3_wait_result {
306 #define HNS3_RESET_SYNC_US 100000
308 struct hns3_reset_stats {
309 uint64_t request_cnt; /* Total request reset times */
310 uint64_t global_cnt; /* Total GLOBAL reset times */
311 uint64_t imp_cnt; /* Total IMP reset times */
312 uint64_t exec_cnt; /* Total reset executive times */
313 uint64_t success_cnt; /* Total reset successful times */
314 uint64_t fail_cnt; /* Total reset failed times */
315 uint64_t merge_cnt; /* Total merged in high reset times */
318 typedef bool (*check_completion_func)(struct hns3_hw *hw);
320 struct hns3_wait_data {
325 enum hns3_wait_result result;
326 check_completion_func check_completion;
329 struct hns3_reset_ops {
330 void (*reset_service)(void *arg);
331 int (*stop_service)(struct hns3_adapter *hns);
332 int (*prepare_reset)(struct hns3_adapter *hns);
333 int (*wait_hardware_ready)(struct hns3_adapter *hns);
334 int (*reinit_dev)(struct hns3_adapter *hns);
335 int (*restore_conf)(struct hns3_adapter *hns);
336 int (*start_service)(struct hns3_adapter *hns);
346 struct hns3_reset_data {
347 enum hns3_reset_stage stage;
348 rte_atomic16_t schedule;
349 /* Reset flag, covering the entire reset process */
350 rte_atomic16_t resetting;
351 /* Used to disable sending cmds during reset */
352 rte_atomic16_t disable_cmd;
353 /* The reset level being processed */
354 enum hns3_reset_level level;
355 /* Reset level set, each bit represents a reset level */
357 /* Request reset level set, from interrupt or mailbox */
359 int attempts; /* Reset failure retry */
360 int retries; /* Timeout failure retry in reset_post */
362 * At the time of global or IMP reset, the command cannot be sent to
363 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the
364 * reset process, so the mbuf is required to be released after the reset
365 * is completed.The mbuf_deferred_free is used to mark whether mbuf
366 * needs to be released.
368 bool mbuf_deferred_free;
369 struct timeval start_time;
370 struct hns3_reset_stats stats;
371 const struct hns3_reset_ops *ops;
372 struct hns3_wait_data *wait_data;
375 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0
376 #define HNS3_INTR_MAPPING_VEC_ALL 1
378 #define HNS3_INTR_COALESCE_NON_QL 0
379 #define HNS3_INTR_COALESCE_QL 1
381 #define HNS3_INTR_COALESCE_GL_UINT_2US 0
382 #define HNS3_INTR_COALESCE_GL_UINT_1US 1
384 struct hns3_queue_intr {
386 * interrupt mapping mode.
388 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL
390 * - HNS3_INTR_MAPPING_VEC_RSV_ONE
391 * For some versions of hardware network engine, because of the
392 * hardware constraint, we need implement clearing the mapping
393 * relationship configurations by binding all queues to the last
394 * interrupt vector and reserving the last interrupt vector. This
395 * method results in a decrease of the maximum queues when upper
396 * applications call the rte_eth_dev_configure API function to
397 * enable Rx interrupt.
399 * - HNS3_INTR_MAPPING_VEC_ALL
400 * PMD driver can map/unmmap all interrupt vectors with queues When
401 * Rx interrupt in enabled.
403 uint8_t mapping_mode;
405 * interrupt coalesce mode.
407 * HNS3_INTR_COALESCE_NON_QL/HNS3_INTR_COALESCE_QL
409 * - HNS3_INTR_COALESCE_NON_QL
410 * For some versions of hardware network engine, hardware doesn't
411 * support QL(quanity limiter) algorithm for interrupt coalesce
412 * of queue's interrupt.
414 * - HNS3_INTR_COALESCE_QL
415 * In this mode, hardware support QL(quanity limiter) algorithm for
416 * interrupt coalesce of queue's interrupt.
418 uint8_t coalesce_mode;
420 * The unit of GL(gap limiter) configuration for interrupt coalesce of
423 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US
428 #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0
429 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1
432 struct rte_eth_dev_data *data;
434 uint8_t revision; /* PCI revision, low byte of class word */
436 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
437 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */
438 pthread_t irq_thread_id;
440 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
441 struct hns3_tqp_stats tqp_stats;
442 /* Include Mac stats | Rx stats | Tx stats */
443 struct hns3_mac_stats mac_stats;
447 uint16_t total_tqps_num; /* total task queue pairs of this PF */
448 uint16_t tqps_num; /* num task queue pairs of this function */
449 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
450 uint16_t rss_size_max; /* HW defined max RSS task queue */
451 uint16_t rx_buf_len; /* hold min hardware rx buf len */
452 uint16_t num_tx_desc; /* desc num of per tx queue */
453 uint16_t num_rx_desc; /* desc num of per rx queue */
454 uint32_t mng_entry_num; /* number of manager table entry */
455 uint32_t mac_entry_num; /* number of mac-vlan table entry */
457 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
458 int mc_addrs_num; /* Multicast mac addresses number */
460 /* The configuration info of RSS */
461 struct hns3_rss_conf rss_info;
462 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
463 uint16_t rss_ind_tbl_size;
464 uint16_t rss_key_size;
466 uint8_t num_tc; /* Total number of enabled TCs */
468 enum hns3_fc_mode current_mode;
469 enum hns3_fc_mode requested_mode;
470 struct hns3_dcb_info dcb_info;
471 enum hns3_fc_status current_fc_status; /* current flow control status */
472 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
473 uint16_t used_rx_queues;
474 uint16_t used_tx_queues;
476 /* Config max queue numbers between rx and tx queues from user */
477 uint16_t cfg_max_queues;
478 struct hns3_fake_queue_data fkq_data; /* fake queue data */
479 uint16_t alloc_rss_size; /* RX queue number per TC */
480 uint16_t tx_qnum_per_tc; /* TX queue number per TC */
483 uint32_t max_tm_rate;
485 * The minimum length of the packet supported by hardware in the Tx
488 uint32_t min_tx_pkt_len;
490 struct hns3_queue_intr intr;
494 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
496 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM
497 * In this mode, because of the hardware constraint, network driver
498 * software need erase the L4 len value of the TCP pseudo header
499 * and recalculate the TCP pseudo header checksum of packets that
502 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
503 * In this mode, hardware support recalculate the TCP pseudo header
504 * checksum of packets that need TSO, so network driver software
505 * not need to recalculate it.
511 * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE
513 * - HNS3_SW_SHIFT_AND_DISCARD_MODE
514 * For some versions of hardware network engine, because of the
515 * hardware limitation, PMD driver needs to detect the PVID status
516 * to work with haredware to implement PVID-related functions.
517 * For example, driver need discard the stripped PVID tag to ensure
518 * the PVID will not report to mbuf and shift the inserted VLAN tag
519 * to avoid port based VLAN covering it.
521 * - HNS3_HW_SHIT_AND_DISCARD_MODE
522 * PMD driver does not need to process PVID-related functions in
523 * I/O process, Hardware will adjust the sequence between port based
524 * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by
525 * PVID will be invisible to driver. And in this mode, hns3 is able
526 * to send a multi-layer VLAN packets when hw VLAN insert offload
530 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
532 struct hns3_port_base_vlan_config port_base_vlan_cfg;
534 * PMD setup and configuration is not thread safe. Since it is not
535 * performance sensitive, it is better to guarantee thread-safety
536 * and add device level lock. Adapter control operations which
537 * change its state should acquire the lock.
540 enum hns3_adapter_state adapter_state;
541 struct hns3_reset_data reset;
544 #define HNS3_FLAG_TC_BASE_SCH_MODE 1
545 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2
547 struct hns3_err_msix_intr_stats {
548 uint64_t mac_afifo_tnl_int_cnt;
549 uint64_t ppu_mpf_abn_int_st2_msix_cnt;
550 uint64_t ssu_port_based_pf_int_cnt;
551 uint64_t ppp_pf_abnormal_int_cnt;
552 uint64_t ppu_pf_abnormal_int_msix_cnt;
554 uint64_t imp_tcm_ecc_int_cnt;
555 uint64_t cmdq_mem_ecc_int_cnt;
556 uint64_t imp_rd_poison_int_cnt;
557 uint64_t tqp_int_ecc_int_cnt;
558 uint64_t msix_ecc_int_cnt;
559 uint64_t ssu_ecc_multi_bit_int_0_cnt;
560 uint64_t ssu_ecc_multi_bit_int_1_cnt;
561 uint64_t ssu_common_ecc_int_cnt;
562 uint64_t igu_int_cnt;
563 uint64_t ppp_mpf_abnormal_int_st1_cnt;
564 uint64_t ppp_mpf_abnormal_int_st3_cnt;
565 uint64_t ppu_mpf_abnormal_int_st1_cnt;
566 uint64_t ppu_mpf_abn_int_st2_ras_cnt;
567 uint64_t ppu_mpf_abnormal_int_st3_cnt;
568 uint64_t tm_sch_int_cnt;
569 uint64_t qcn_fifo_int_cnt;
570 uint64_t qcn_ecc_int_cnt;
571 uint64_t ncsi_ecc_int_cnt;
572 uint64_t ssu_port_based_err_int_cnt;
573 uint64_t ssu_fifo_overflow_int_cnt;
574 uint64_t ssu_ets_tcg_int_cnt;
575 uint64_t igu_egu_tnl_int_cnt;
576 uint64_t ppu_pf_abnormal_int_ras_cnt;
579 /* vlan entry information. */
580 struct hns3_user_vlan_table {
581 LIST_ENTRY(hns3_user_vlan_table) next;
586 /* Vlan tag configuration for RX direction */
587 struct hns3_rx_vtag_cfg {
588 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */
589 bool strip_tag1_en; /* Whether strip inner vlan tag */
590 bool strip_tag2_en; /* Whether strip outer vlan tag */
592 * If strip_tag_en is enabled, this bit decide whether to map the vlan
595 bool strip_tag1_discard_en;
596 bool strip_tag2_discard_en;
598 * If this bit is enabled, only map inner/outer priority to descriptor
599 * and the vlan tag is always 0.
601 bool vlan1_vlan_prionly;
602 bool vlan2_vlan_prionly;
605 /* Vlan tag configuration for TX direction */
606 struct hns3_tx_vtag_cfg {
607 bool accept_tag1; /* Whether accept tag1 packet from host */
608 bool accept_untag1; /* Whether accept untag1 packet from host */
611 bool insert_tag1_en; /* Whether insert outer vlan tag */
612 bool insert_tag2_en; /* Whether insert inner vlan tag */
614 * In shift mode, hw will shift the sequence of port based VLAN and
617 bool tag_shift_mode_en; /* hw shift vlan tag automatically */
618 uint16_t default_tag1; /* The default outer vlan tag to insert */
619 uint16_t default_tag2; /* The default inner vlan tag to insert */
622 struct hns3_vtag_cfg {
623 struct hns3_rx_vtag_cfg rx_vcfg;
624 struct hns3_tx_vtag_cfg tx_vcfg;
627 /* Request types for IPC. */
628 enum hns3_mp_req_type {
629 HNS3_MP_REQ_START_RXTX = 1,
630 HNS3_MP_REQ_STOP_RXTX,
634 /* Pameters for IPC. */
635 struct hns3_mp_param {
636 enum hns3_mp_req_type type;
641 /* Request timeout for IPC. */
642 #define HNS3_MP_REQ_TIMEOUT_SEC 5
644 /* Key string for IPC. */
645 #define HNS3_MP_NAME "net_hns3_mp"
647 #define HNS3_L2TBL_NUM 4
648 #define HNS3_L3TBL_NUM 16
649 #define HNS3_L4TBL_NUM 16
650 #define HNS3_OL3TBL_NUM 16
651 #define HNS3_OL4TBL_NUM 16
653 struct hns3_ptype_table {
654 uint32_t l2table[HNS3_L2TBL_NUM];
655 uint32_t l3table[HNS3_L3TBL_NUM];
656 uint32_t l4table[HNS3_L4TBL_NUM];
657 uint32_t inner_l2table[HNS3_L2TBL_NUM];
658 uint32_t inner_l3table[HNS3_L3TBL_NUM];
659 uint32_t inner_l4table[HNS3_L4TBL_NUM];
660 uint32_t ol3table[HNS3_OL3TBL_NUM];
661 uint32_t ol4table[HNS3_OL4TBL_NUM];
665 struct hns3_adapter *adapter;
667 uint16_t func_num; /* num functions of this pf, include pf and vfs */
669 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
670 uint32_t tx_buf_size; /* Tx buffer size for each TC */
671 uint32_t dv_buf_size; /* Dv buffer size for each TC */
673 uint16_t mps; /* Max packet size */
676 uint8_t tc_max; /* max number of tc driver supported */
677 uint8_t local_max_tc; /* max number of local tc */
679 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */
681 bool support_fc_autoneg; /* support FC autonegotiate */
683 uint16_t wanted_umv_size;
684 uint16_t max_umv_size;
685 uint16_t used_umv_size;
687 /* Statistics information for abnormal interrupt */
688 struct hns3_err_msix_intr_stats abn_int_stats;
690 bool support_sfp_query;
692 struct hns3_vtag_cfg vtag_config;
693 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
695 struct hns3_fdir_info fdir; /* flow director info */
696 LIST_HEAD(counters, hns3_flow_counter) flow_counters;
700 struct hns3_adapter *adapter;
703 struct hns3_adapter {
706 /* Specific for PF or VF */
707 bool is_vf; /* false - PF, true - VF */
713 bool rx_simple_allowed;
715 bool tx_simple_allowed;
718 struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
721 #define HNS3_DEV_SUPPORT_DCB_B 0x0
722 #define HNS3_DEV_SUPPORT_COPPER_B 0x1
723 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
724 #define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3
725 #define HNS3_DEV_SUPPORT_PTP_B 0x4
726 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5
727 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6
728 #define HNS3_DEV_SUPPORT_STASH_B 0x7
730 #define hns3_dev_dcb_supported(hw) \
731 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
733 /* Support copper media type */
734 #define hns3_dev_copper_supported(hw) \
735 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B)
737 /* Support UDP GSO offload */
738 #define hns3_dev_udp_gso_supported(hw) \
739 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
741 /* Support the queue region action rule of flow directory */
742 #define hns3_dev_fd_queue_region_supported(hw) \
743 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B)
745 /* Support PTP timestamp offload */
746 #define hns3_dev_ptp_supported(hw) \
747 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B)
749 #define hns3_dev_tx_push_supported(hw) \
750 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)
752 /* Support to Independently enable/disable/reset Tx or Rx queues */
753 #define hns3_dev_indep_txrx_supported(hw) \
754 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B)
756 #define hns3_dev_stash_supported(hw) \
757 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B)
759 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
760 (&((struct hns3_adapter *)adapter)->hw)
761 #define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \
762 ((struct hns3_adapter *)adapter)
763 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \
764 (&((struct hns3_adapter *)adapter)->pf)
765 #define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \
766 (&((struct hns3_adapter *)adapter)->vf)
767 #define HNS3_DEV_HW_TO_ADAPTER(hw) \
768 container_of(hw, struct hns3_adapter, hw)
770 #define hns3_set_field(origin, mask, shift, val) \
772 (origin) &= (~(mask)); \
773 (origin) |= ((val) << (shift)) & (mask); \
775 #define hns3_get_field(origin, mask, shift) \
776 (((origin) & (mask)) >> (shift))
777 #define hns3_set_bit(origin, shift, val) \
778 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val))
779 #define hns3_get_bit(origin, shift) \
780 hns3_get_field((origin), (0x1UL << (shift)), (shift))
783 * upper_32_bits - return bits 32-63 of a number
784 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
785 * the "right shift count >= width of type" warning when that quantity is
788 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
790 /* lower_32_bits - return bits 0-31 of a number */
791 #define lower_32_bits(n) ((uint32_t)(n))
793 #define BIT(nr) (1UL << (nr))
795 #define BIT_ULL(x) (1ULL << (x))
797 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
798 #define GENMASK(h, l) \
799 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
801 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
802 #define rounddown(x, y) ((x) - ((x) % (y)))
804 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
807 * Because hardware always access register in little-endian mode based on hns3
808 * network engine, so driver should also call rte_cpu_to_le_32 to convert data
809 * in little-endian mode before writing register and call rte_le_to_cpu_32 to
810 * convert data after reading from register.
812 * Here the driver encapsulates the data conversion operation in the register
813 * read/write operation function as below:
817 * Therefore, when calling these functions, conversion is not required again.
819 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
821 rte_write32(rte_cpu_to_le_32(value),
822 (volatile void *)((char *)base + reg));
826 * The optimized function for writing registers used in the '.rx_pkt_burst' and
827 * '.tx_pkt_burst' ops implementation function.
829 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value)
832 rte_write32_relaxed(rte_cpu_to_le_32(value), addr);
835 static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
837 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg));
838 return rte_le_to_cpu_32(read_val);
841 #define hns3_write_dev(a, reg, value) \
842 hns3_write_reg((a)->io_base, (reg), (value))
844 #define hns3_read_dev(a, reg) \
845 hns3_read_reg((a)->io_base, (reg))
847 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
849 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
851 act = (actions) + (index); \
852 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
854 act = actions + index; \
858 #define MSEC_PER_SEC 1000L
859 #define USEC_PER_MSEC 1000L
861 static inline uint64_t
862 get_timeofday_ms(void)
866 (void)gettimeofday(&tv, NULL);
868 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
871 static inline uint64_t
872 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
876 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;
881 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)
883 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);
887 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)
889 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);
892 static inline int64_t
893 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)
895 uint64_t mask = (1UL << nr);
897 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
900 int hns3_buffer_alloc(struct hns3_hw *hw);
901 int hns3_dev_filter_ctrl(struct rte_eth_dev *dev,
902 enum rte_filter_type filter_type,
903 enum rte_filter_op filter_op, void *arg);
904 bool hns3_is_reset_pending(struct hns3_adapter *hns);
905 bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
906 void hns3_update_link_status(struct hns3_hw *hw);
909 is_reset_pending(struct hns3_adapter *hns)
913 ret = hns3vf_is_reset_pending(hns);
915 ret = hns3_is_reset_pending(hns);
919 static inline uint64_t
920 hns3_txvlan_cap_get(struct hns3_hw *hw)
922 if (hw->port_base_vlan_cfg.state)
923 return DEV_TX_OFFLOAD_VLAN_INSERT;
925 return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT;
928 #endif /* _HNS3_ETHDEV_H_ */