1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
5 #ifndef _HNS3_ETHDEV_H_
6 #define _HNS3_ETHDEV_H_
10 #include <ethdev_driver.h>
11 #include <rte_byteorder.h>
13 #include <rte_spinlock.h>
18 #include "hns3_fdir.h"
19 #include "hns3_stats.h"
23 #define PCI_VENDOR_ID_HUAWEI 0x19e5
26 #define HNS3_DEV_ID_GE 0xA220
27 #define HNS3_DEV_ID_25GE 0xA221
28 #define HNS3_DEV_ID_25GE_RDMA 0xA222
29 #define HNS3_DEV_ID_50GE_RDMA 0xA224
30 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226
31 #define HNS3_DEV_ID_200G_RDMA 0xA228
32 #define HNS3_DEV_ID_100G_VF 0xA22E
33 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
35 /* PCI Config offsets */
36 #define HNS3_PCI_REVISION_ID 0x08
37 #define HNS3_PCI_REVISION_ID_LEN 1
39 #define PCI_REVISION_ID_HIP08_B 0x21
40 #define PCI_REVISION_ID_HIP09_A 0x30
42 #define HNS3_PF_FUNC_ID 0
43 #define HNS3_1ST_VF_FUNC_ID 1
45 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
46 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
48 #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0
49 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1
51 #define HNS3_UNLIMIT_PROMISC_MODE 0
52 #define HNS3_LIMIT_PROMISC_MODE 1
54 #define HNS3_SPECIAL_PORT_SW_CKSUM_MODE 0
55 #define HNS3_SPECIAL_PORT_HW_CKSUM_MODE 1
57 #define HNS3_UC_MACADDR_NUM 128
58 #define HNS3_VF_UC_MACADDR_NUM 48
59 #define HNS3_MC_MACADDR_NUM 128
61 #define HNS3_MAX_BD_SIZE 65535
62 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8
63 #define HNS3_MAX_TSO_BD_PER_PKT 63
64 #define HNS3_MAX_FRAME_LEN 9728
65 #define HNS3_VLAN_TAG_SIZE 4
66 #define HNS3_DEFAULT_RX_BUF_LEN 2048
67 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
68 #define HNS3_MAX_TSO_HDR_SIZE 512
69 #define HNS3_MAX_TSO_HDR_BD_NUM 3
70 #define HNS3_MAX_LRO_SIZE 64512
72 #define HNS3_ETH_OVERHEAD \
73 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
74 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD)
75 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
76 #define HNS3_DEFAULT_MTU 1500UL
77 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
78 #define HNS3_HIP08_MIN_TX_PKT_LEN 33
79 #define HNS3_HIP09_MIN_TX_PKT_LEN 9
81 #define HNS3_BITS_PER_BYTE 8
86 #define HNS3_MAX_PF_NUM 8
87 #define HNS3_UMV_TBL_SIZE 3072
88 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \
89 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM)
91 #define HNS3_PF_CFG_BLOCK_SIZE 32
92 #define HNS3_PF_CFG_DESC_NUM \
93 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES)
95 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0
97 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5
98 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500
100 #define HNS3_QUIT_RESET_CNT 10
101 #define HNS3_QUIT_RESET_DELAY_MS 100
103 #define HNS3_POLL_RESPONE_MS 1
105 #define HNS3_MAX_USER_PRIO 8
106 #define HNS3_PG_NUM 4
115 #define HNS3_SCH_MODE_SP 0
116 #define HNS3_SCH_MODE_DWRR 1
117 struct hns3_pg_info {
119 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */
122 uint8_t tc_dwrr[HNS3_MAX_TC_NUM];
125 struct hns3_tc_info {
127 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */
130 uint8_t up_to_tc_map; /* user priority maping on the TC */
133 struct hns3_dcb_info {
135 uint8_t num_pg; /* It must be 1 if vNET-Base schd */
136 uint8_t pg_dwrr[HNS3_PG_NUM];
137 uint8_t prio_tc[HNS3_MAX_USER_PRIO];
138 struct hns3_pg_info pg_info[HNS3_PG_NUM];
139 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM];
140 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */
141 uint8_t pfc_en; /* Pfc enabled or not for user priority */
144 enum hns3_fc_status {
146 HNS3_FC_STATUS_MAC_PAUSE,
150 struct hns3_tc_queue_info {
151 uint16_t tqp_offset; /* TQP offset from base TQP */
152 uint16_t tqp_count; /* Total TQPs */
153 uint8_t tc; /* TC index */
154 bool enable; /* If this TC is enable or not */
159 uint16_t tqp_desc_num;
161 uint16_t rss_size_max;
164 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
165 uint8_t default_speed;
166 uint32_t numa_node_map;
167 uint8_t speed_ability;
171 struct hns3_set_link_speed_cfg {
178 enum hns3_media_type {
179 HNS3_MEDIA_TYPE_UNKNOWN,
180 HNS3_MEDIA_TYPE_FIBER,
181 HNS3_MEDIA_TYPE_COPPER,
182 HNS3_MEDIA_TYPE_BACKPLANE,
183 HNS3_MEDIA_TYPE_NONE,
186 #define HNS3_DEFAULT_QUERY 0
187 #define HNS3_ACTIVE_QUERY 1
190 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
193 uint8_t link_duplex : 1; /* RTE_ETH_LINK_[HALF/FULL]_DUPLEX */
194 uint8_t link_autoneg : 1; /* RTE_ETH_LINK_[AUTONEG/FIXED] */
195 uint8_t link_status : 1; /* RTE_ETH_LINK_[DOWN/UP] */
196 uint32_t link_speed; /* RTE_ETH_SPEED_NUM_ */
198 * Some firmware versions support only the SFP speed query. In addition
199 * to the SFP speed query, some firmware supports the query of the speed
200 * capability, auto-negotiation capability, and FEC mode, which can be
201 * selected by the 'query_type' filed in the HNS3_OPC_GET_SFP_INFO CMD.
202 * This field is used to record the SFP information query mode.
204 * HNS3_DEFAULT_QUERY/HNS3_ACTIVE_QUERY
206 * - HNS3_DEFAULT_QUERY
207 * Speed obtained is from SFP. When the queried speed changes, the MAC
208 * speed needs to be reconfigured.
210 * - HNS3_ACTIVE_QUERY
211 * Speed obtained is from MAC. At this time, it is unnecessary for
212 * driver to reconfigured the MAC speed. In addition, more information,
213 * such as, the speed capability, auto-negotiation capability and FEC
214 * mode, can be obtained by the HNS3_OPC_GET_SFP_INFO CMD.
217 uint32_t supported_speed; /* supported speed for current media type */
218 uint32_t advertising; /* advertised capability in the local part */
219 uint32_t lp_advertising; /* advertised capability in the link partner */
220 uint8_t support_autoneg;
223 struct hns3_fake_queue_data {
224 void **rx_queues; /* Array of pointers to fake RX queues. */
225 void **tx_queues; /* Array of pointers to fake TX queues. */
226 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */
227 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
230 #define HNS3_PORT_BASE_VLAN_DISABLE 0
231 #define HNS3_PORT_BASE_VLAN_ENABLE 1
232 struct hns3_port_base_vlan_config {
237 /* Primary process maintains driver state in main thread.
240 * | UNINITIALIZED |<-----------+
241 * +---------------+ |
242 * |.eth_dev_init |.eth_dev_uninit
244 * +---------------+------------+
246 * +---------------+<-----------<---------------+
247 * |.dev_configure | |
249 * +---------------+------------+ |
251 * +---------------+----+ |
253 * | | +---------------+
255 * | | +---------------+
257 * V |.dev_configure |
258 * +---------------+----+ |.dev_close
259 * | CONFIGURED |----------------------------+
260 * +---------------+<-----------+
263 * +---------------+ |
264 * | STARTING |------------^
265 * +---------------+ failed |
267 * | +---------------+
269 * | +---------------+
272 * +---------------+------------+
276 enum hns3_adapter_state {
277 HNS3_NIC_UNINITIALIZED = 0,
278 HNS3_NIC_INITIALIZED,
279 HNS3_NIC_CONFIGURING,
290 /* Reset various stages, execute in order */
291 enum hns3_reset_stage {
292 /* Stop query services, stop transceiver, disable MAC */
294 /* Clear reset completion flags, disable send command */
296 /* Inform IMP to start resetting */
297 RESET_STAGE_REQ_HW_RESET,
298 /* Waiting for hardware reset to complete */
300 /* Reinitialize hardware */
301 RESET_STAGE_DEV_INIT,
302 /* Restore user settings and enable MAC */
304 /* Restart query services, start transceiver */
306 /* Not in reset state */
310 enum hns3_reset_level {
311 HNS3_FLR_RESET, /* A VF perform FLR reset */
312 HNS3_VF_FUNC_RESET, /* A VF function reset */
315 * All VFs under a PF perform function reset.
316 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
317 * of the reset level and the one defined in kernel driver should be
320 HNS3_VF_PF_FUNC_RESET = 2,
323 * All VFs under a PF perform FLR reset.
324 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
325 * of the reset level and the one defined in kernel driver should be
328 * According to the protocol of PCIe, FLR to a PF resets the PF state as
329 * well as the SR-IOV extended capability including VF Enable which
330 * means that VFs no longer exist.
332 * In PF FLR, the register state of VF is not reliable, VF's driver
333 * should not access the registers of the VF device.
337 /* All VFs under the rootport perform a global or IMP reset */
341 * The enumeration value of HNS3_FUNC_RESET/HNS3_GLOBAL_RESET/
342 * HNS3_IMP_RESET/HNS3_NONE_RESET are also used by firmware, and
343 * can not be changed.
346 HNS3_FUNC_RESET = 5, /* A PF function reset */
348 /* All PFs under the rootport perform a global reset */
350 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
355 enum hns3_wait_result {
362 #define HNS3_RESET_SYNC_US 100000
364 struct hns3_reset_stats {
365 uint64_t request_cnt; /* Total request reset times */
366 uint64_t global_cnt; /* Total GLOBAL reset times */
367 uint64_t imp_cnt; /* Total IMP reset times */
368 uint64_t exec_cnt; /* Total reset executive times */
369 uint64_t success_cnt; /* Total reset successful times */
370 uint64_t fail_cnt; /* Total reset failed times */
371 uint64_t merge_cnt; /* Total merged in high reset times */
374 typedef bool (*check_completion_func)(struct hns3_hw *hw);
376 struct hns3_wait_data {
381 enum hns3_wait_result result;
382 check_completion_func check_completion;
385 struct hns3_reset_ops {
386 void (*reset_service)(void *arg);
387 int (*stop_service)(struct hns3_adapter *hns);
388 int (*prepare_reset)(struct hns3_adapter *hns);
389 int (*wait_hardware_ready)(struct hns3_adapter *hns);
390 int (*reinit_dev)(struct hns3_adapter *hns);
391 int (*restore_conf)(struct hns3_adapter *hns);
392 int (*start_service)(struct hns3_adapter *hns);
402 struct hns3_reset_data {
403 enum hns3_reset_stage stage;
405 /* Reset flag, covering the entire reset process */
407 /* Used to disable sending cmds during reset */
408 uint16_t disable_cmd;
409 /* The reset level being processed */
410 enum hns3_reset_level level;
411 /* Reset level set, each bit represents a reset level */
413 /* Request reset level set, from interrupt or mailbox */
415 int attempts; /* Reset failure retry */
416 int retries; /* Timeout failure retry in reset_post */
418 * At the time of global or IMP reset, the command cannot be sent to
419 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the
420 * reset process, so the mbuf is required to be released after the reset
421 * is completed.The mbuf_deferred_free is used to mark whether mbuf
422 * needs to be released.
424 bool mbuf_deferred_free;
425 struct timeval start_time;
426 struct hns3_reset_stats stats;
427 const struct hns3_reset_ops *ops;
428 struct hns3_wait_data *wait_data;
431 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0
432 #define HNS3_INTR_MAPPING_VEC_ALL 1
434 #define HNS3_INTR_COALESCE_GL_UINT_2US 0
435 #define HNS3_INTR_COALESCE_GL_UINT_1US 1
437 #define HNS3_INTR_QL_NONE 0
439 struct hns3_queue_intr {
441 * interrupt mapping mode.
443 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL
445 * - HNS3_INTR_MAPPING_VEC_RSV_ONE
446 * For some versions of hardware network engine, because of the
447 * hardware constraint, we need implement clearing the mapping
448 * relationship configurations by binding all queues to the last
449 * interrupt vector and reserving the last interrupt vector. This
450 * method results in a decrease of the maximum queues when upper
451 * applications call the rte_eth_dev_configure API function to
452 * enable Rx interrupt.
454 * - HNS3_INTR_MAPPING_VEC_ALL
455 * PMD driver can map/unmmap all interrupt vectors with queues When
456 * Rx interrupt in enabled.
458 uint8_t mapping_mode;
460 * The unit of GL(gap limiter) configuration for interrupt coalesce of
463 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US
466 /* The max QL(quantity limiter) value */
470 #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0
471 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1
473 #define HNS3_PKTS_DROP_STATS_MODE1 0
474 #define HNS3_PKTS_DROP_STATS_MODE2 1
477 struct rte_eth_dev_data *data;
479 uint8_t revision; /* PCI revision, low byte of class word */
481 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
484 * This flag indicates dev_set_link_down() API is called, and is cleared
485 * by dev_set_link_up() or dev_start().
488 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
489 struct hns3_tqp_stats tqp_stats;
490 /* Include Mac stats | Rx stats | Tx stats */
491 struct hns3_mac_stats mac_stats;
492 struct hns3_rx_missed_stats imissed_stats;
493 uint64_t oerror_stats;
495 uint16_t pf_vf_if_version; /* version of communication interface */
498 uint16_t total_tqps_num; /* total task queue pairs of this PF */
499 uint16_t tqps_num; /* num task queue pairs of this function */
500 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
501 uint16_t rss_size_max; /* HW defined max RSS task queue */
502 uint16_t rx_buf_len; /* hold min hardware rx buf len */
503 uint16_t num_tx_desc; /* desc num of per tx queue */
504 uint16_t num_rx_desc; /* desc num of per rx queue */
505 uint32_t mng_entry_num; /* number of manager table entry */
506 uint32_t mac_entry_num; /* number of mac-vlan table entry */
508 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
509 int mc_addrs_num; /* Multicast mac addresses number */
511 /* The configuration info of RSS */
512 struct hns3_rss_conf rss_info;
513 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
514 uint16_t rss_ind_tbl_size;
515 uint16_t rss_key_size;
517 uint8_t num_tc; /* Total number of enabled TCs */
519 enum hns3_fc_mode requested_fc_mode; /* FC mode requested by user */
520 struct hns3_dcb_info dcb_info;
521 enum hns3_fc_status current_fc_status; /* current flow control status */
522 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
523 uint16_t used_rx_queues;
524 uint16_t used_tx_queues;
526 /* Config max queue numbers between rx and tx queues from user */
527 uint16_t cfg_max_queues;
528 struct hns3_fake_queue_data fkq_data; /* fake queue data */
529 uint16_t alloc_rss_size; /* RX queue number per TC */
530 uint16_t tx_qnum_per_tc; /* TX queue number per TC */
533 uint32_t max_tm_rate;
535 * The minimum length of the packet supported by hardware in the Tx
538 uint32_t min_tx_pkt_len;
540 struct hns3_queue_intr intr;
544 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
546 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM
547 * In this mode, because of the hardware constraint, network driver
548 * software need erase the L4 len value of the TCP pseudo header
549 * and recalculate the TCP pseudo header checksum of packets that
552 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
553 * In this mode, hardware support recalculate the TCP pseudo header
554 * checksum of packets that need TSO, so network driver software
555 * not need to recalculate it.
561 * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE
563 * - HNS3_SW_SHIFT_AND_DISCARD_MODE
564 * For some versions of hardware network engine, because of the
565 * hardware limitation, PMD driver needs to detect the PVID status
566 * to work with haredware to implement PVID-related functions.
567 * For example, driver need discard the stripped PVID tag to ensure
568 * the PVID will not report to mbuf and shift the inserted VLAN tag
569 * to avoid port based VLAN covering it.
571 * - HNS3_HW_SHIT_AND_DISCARD_MODE
572 * PMD driver does not need to process PVID-related functions in
573 * I/O process, Hardware will adjust the sequence between port based
574 * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by
575 * PVID will be invisible to driver. And in this mode, hns3 is able
576 * to send a multi-layer VLAN packets when hw VLAN insert offload
583 * HNS3_UNLIMIT_PROMISC_MODE/HNS3_LIMIT_PROMISC_MODE
585 * - HNS3_UNLIMIT_PROMISC_MODE
586 * In this mode, TX unicast promisc will be configured when promisc
587 * is set, driver can receive all the ingress and outgoing traffic.
588 * In the words, all the ingress packets, all the packets sent from
589 * the PF and other VFs on the same physical port.
591 * - HNS3_LIMIT_PROMISC_MODE
592 * In this mode, TX unicast promisc is shutdown when promisc mode
593 * is set. So, driver will only receive all the ingress traffic.
594 * The packets sent from the PF and other VFs on the same physical
595 * port won't be copied to the function which has set promisc mode.
597 uint8_t promisc_mode;
600 * drop_stats_mode mode.
602 * HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2
604 * - HNS3_PKTS_DROP_STATS_MODE1
605 * This mode for kunpeng920. In this mode, port level imissed stats
606 * is supported. It only includes RPU drop stats.
608 * - HNS3_PKTS_DROP_STATS_MODE2
609 * This mode for kunpeng930. In this mode, imissed stats and oerrors
610 * stats is supported. Function level imissed stats is supported. It
611 * includes RPU drop stats in VF, and includes both RPU drop stats
612 * and SSU drop stats in PF. Oerror stats is also supported in PF.
614 uint8_t drop_stats_mode;
616 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
620 * HNS3_SPECIAL_PORT_HW_CKSUM_MODE/HNS3_SPECIAL_PORT_SW_CKSUM_MODE
622 * - HNS3_SPECIAL_PORT_SW_CKSUM_MODE
623 * In this mode, HW can not do checksum for special UDP port like
624 * 4789, 4790, 6081 for non-tunnel UDP packets and UDP tunnel
625 * packets without the RTE_MBUF_F_TX_TUNEL_MASK in the mbuf. So, PMD need
626 * do the checksum for these packets to avoid a checksum error.
628 * - HNS3_SPECIAL_PORT_HW_CKSUM_MODE
629 * In this mode, HW does not have the preceding problems and can
630 * directly calculate the checksum of these UDP packets.
632 uint8_t udp_cksum_mode;
634 struct hns3_port_base_vlan_config port_base_vlan_cfg;
636 pthread_mutex_t flows_lock; /* rte_flow ops lock */
637 struct hns3_fdir_rule_list flow_fdir_list; /* flow fdir rule list */
638 struct hns3_rss_filter_list flow_rss_list; /* flow RSS rule list */
639 struct hns3_flow_mem_list flow_list;
642 * PMD setup and configuration is not thread safe. Since it is not
643 * performance sensitive, it is better to guarantee thread-safety
644 * and add device level lock. Adapter control operations which
645 * change its state should acquire the lock.
648 enum hns3_adapter_state adapter_state;
649 struct hns3_reset_data reset;
652 #define HNS3_FLAG_TC_BASE_SCH_MODE 1
653 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2
655 /* vlan entry information. */
656 struct hns3_user_vlan_table {
657 LIST_ENTRY(hns3_user_vlan_table) next;
662 /* Vlan tag configuration for RX direction */
663 struct hns3_rx_vtag_cfg {
664 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */
665 bool strip_tag1_en; /* Whether strip inner vlan tag */
666 bool strip_tag2_en; /* Whether strip outer vlan tag */
668 * If strip_tag_en is enabled, this bit decide whether to map the vlan
671 bool strip_tag1_discard_en;
672 bool strip_tag2_discard_en;
674 * If this bit is enabled, only map inner/outer priority to descriptor
675 * and the vlan tag is always 0.
677 bool vlan1_vlan_prionly;
678 bool vlan2_vlan_prionly;
681 /* Vlan tag configuration for TX direction */
682 struct hns3_tx_vtag_cfg {
683 bool accept_tag1; /* Whether accept tag1 packet from host */
684 bool accept_untag1; /* Whether accept untag1 packet from host */
687 bool insert_tag1_en; /* Whether insert outer vlan tag */
688 bool insert_tag2_en; /* Whether insert inner vlan tag */
690 * In shift mode, hw will shift the sequence of port based VLAN and
693 bool tag_shift_mode_en; /* hw shift vlan tag automatically */
694 uint16_t default_tag1; /* The default outer vlan tag to insert */
695 uint16_t default_tag2; /* The default inner vlan tag to insert */
698 struct hns3_vtag_cfg {
699 struct hns3_rx_vtag_cfg rx_vcfg;
700 struct hns3_tx_vtag_cfg tx_vcfg;
703 /* Request types for IPC. */
704 enum hns3_mp_req_type {
705 HNS3_MP_REQ_START_RXTX = 1,
706 HNS3_MP_REQ_STOP_RXTX,
707 HNS3_MP_REQ_START_TX,
712 /* Pameters for IPC. */
713 struct hns3_mp_param {
714 enum hns3_mp_req_type type;
719 /* Request timeout for IPC. */
720 #define HNS3_MP_REQ_TIMEOUT_SEC 5
722 /* Key string for IPC. */
723 #define HNS3_MP_NAME "net_hns3_mp"
725 #define HNS3_L2TBL_NUM 4
726 #define HNS3_L3TBL_NUM 16
727 #define HNS3_L4TBL_NUM 16
728 #define HNS3_OL2TBL_NUM 4
729 #define HNS3_OL3TBL_NUM 16
730 #define HNS3_OL4TBL_NUM 16
731 #define HNS3_PTYPE_NUM 256
733 struct hns3_ptype_table {
735 * The next fields used to calc packet-type by the
736 * L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor.
738 uint32_t l3table[HNS3_L3TBL_NUM];
739 uint32_t l4table[HNS3_L4TBL_NUM];
740 uint32_t inner_l3table[HNS3_L3TBL_NUM];
741 uint32_t inner_l4table[HNS3_L4TBL_NUM];
742 uint32_t ol3table[HNS3_OL3TBL_NUM];
743 uint32_t ol4table[HNS3_OL4TBL_NUM];
746 * The next field used to calc packet-type by the PTYPE from the Rx
747 * descriptor, it functions only when firmware report the capability of
748 * HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it.
750 uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_aligned;
753 #define HNS3_FIXED_MAX_TQP_NUM_MODE 0
754 #define HNS3_FLEX_MAX_TQP_NUM_MODE 1
757 struct hns3_adapter *adapter;
759 uint16_t func_num; /* num functions of this pf, include pf and vfs */
763 * tqp_config_mode value range:
764 * HNS3_FIXED_MAX_TQP_NUM_MODE,
765 * HNS3_FLEX_MAX_TQP_NUM_MODE
767 * - HNS3_FIXED_MAX_TQP_NUM_MODE
768 * There is a limitation on the number of pf interrupts available for
769 * on some versions of network engines. In this case, the maximum
770 * queue number of pf can not be greater than the interrupt number,
771 * such as pf of network engine with revision_id 0x21. So the maximum
772 * number of queues must be fixed.
774 * - HNS3_FLEX_MAX_TQP_NUM_MODE
775 * In this mode, the maximum queue number of pf has not any constraint
776 * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF
777 * in the config file. Users can modify the macro according to their
778 * own application scenarios, which is more flexible to use.
780 uint8_t tqp_config_mode;
782 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
783 uint32_t tx_buf_size; /* Tx buffer size for each TC */
784 uint32_t dv_buf_size; /* Dv buffer size for each TC */
786 uint16_t mps; /* Max packet size */
789 uint8_t tc_max; /* max number of tc driver supported */
790 uint8_t local_max_tc; /* max number of local tc */
792 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */
794 bool support_fc_autoneg; /* support FC autonegotiate */
795 bool support_multi_tc_pause;
797 uint16_t wanted_umv_size;
798 uint16_t max_umv_size;
799 uint16_t used_umv_size;
801 bool support_sfp_query;
802 uint32_t fec_mode; /* current FEC mode for ethdev */
806 /* Stores timestamp of last received packet on dev */
807 uint64_t rx_timestamp;
809 struct hns3_vtag_cfg vtag_config;
810 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
812 struct hns3_fdir_info fdir; /* flow director info */
813 LIST_HEAD(counters, hns3_flow_counter) flow_counters;
815 struct hns3_tm_conf tm_conf;
819 HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED,
820 HNS3_PF_PUSH_LSC_CAP_SUPPORTED,
821 HNS3_PF_PUSH_LSC_CAP_UNKNOWN
825 struct hns3_adapter *adapter;
827 /* Whether PF support push link status change to VF */
828 uint16_t pf_push_lsc_cap;
831 * If PF support push link status change, VF still need send request to
832 * get link status in some cases (such as reset recover stage), so use
833 * the req_link_info_cnt to control max request count.
835 uint16_t req_link_info_cnt;
837 uint16_t poll_job_started; /* whether poll job is started */
840 struct hns3_adapter {
843 /* Specific for PF or VF */
844 bool is_vf; /* false - PF, true - VF */
850 uint32_t rx_func_hint;
851 uint32_t tx_func_hint;
853 uint64_t dev_caps_mask;
854 uint16_t mbx_time_limit_ms; /* wait time for mbx message */
856 struct hns3_ptype_table ptype_tbl __rte_cache_aligned;
860 HNS3_IO_FUNC_HINT_NONE = 0,
861 HNS3_IO_FUNC_HINT_VEC,
862 HNS3_IO_FUNC_HINT_SVE,
863 HNS3_IO_FUNC_HINT_SIMPLE,
864 HNS3_IO_FUNC_HINT_COMMON
867 #define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint"
868 #define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint"
870 #define HNS3_DEVARG_DEV_CAPS_MASK "dev_caps_mask"
872 #define HNS3_DEVARG_MBX_TIME_LIMIT_MS "mbx_time_limit_ms"
875 HNS3_DEV_SUPPORT_DCB_B,
876 HNS3_DEV_SUPPORT_COPPER_B,
877 HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B,
878 HNS3_DEV_SUPPORT_PTP_B,
879 HNS3_DEV_SUPPORT_TX_PUSH_B,
880 HNS3_DEV_SUPPORT_INDEP_TXRX_B,
881 HNS3_DEV_SUPPORT_STASH_B,
882 HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
883 HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B,
884 HNS3_DEV_SUPPORT_RAS_IMP_B,
885 HNS3_DEV_SUPPORT_TM_B,
886 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B,
889 #define hns3_dev_get_support(hw, _name) \
890 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_##_name##_B)
892 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
893 (&((struct hns3_adapter *)adapter)->hw)
894 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \
895 (&((struct hns3_adapter *)adapter)->pf)
896 #define HNS3_DEV_PRIVATE_TO_VF(adapter) \
897 (&((struct hns3_adapter *)adapter)->vf)
898 #define HNS3_DEV_HW_TO_ADAPTER(hw) \
899 container_of(hw, struct hns3_adapter, hw)
901 static inline struct hns3_pf *HNS3_DEV_HW_TO_PF(struct hns3_hw *hw)
903 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw);
907 static inline struct hns3_vf *HNS3_DEV_HW_TO_VF(struct hns3_hw *hw)
909 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw);
913 #define hns3_set_field(origin, mask, shift, val) \
915 (origin) &= (~(mask)); \
916 (origin) |= ((val) << (shift)) & (mask); \
918 #define hns3_get_field(origin, mask, shift) \
919 (((origin) & (mask)) >> (shift))
920 #define hns3_set_bit(origin, shift, val) \
921 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val))
922 #define hns3_get_bit(origin, shift) \
923 hns3_get_field((origin), (0x1UL << (shift)), (shift))
925 #define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask))
928 * upper_32_bits - return bits 32-63 of a number
929 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
930 * the "right shift count >= width of type" warning when that quantity is
933 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
935 /* lower_32_bits - return bits 0-31 of a number */
936 #define lower_32_bits(n) ((uint32_t)(n))
938 #define BIT(nr) (1UL << (nr))
940 #define BIT_ULL(x) (1ULL << (x))
942 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
943 #define GENMASK(h, l) \
944 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
946 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
947 #define rounddown(x, y) ((x) - ((x) % (y)))
949 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
952 * Because hardware always access register in little-endian mode based on hns3
953 * network engine, so driver should also call rte_cpu_to_le_32 to convert data
954 * in little-endian mode before writing register and call rte_le_to_cpu_32 to
955 * convert data after reading from register.
957 * Here the driver encapsulates the data conversion operation in the register
958 * read/write operation function as below:
962 * Therefore, when calling these functions, conversion is not required again.
964 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
966 rte_write32(rte_cpu_to_le_32(value),
967 (volatile void *)((char *)base + reg));
971 * The optimized function for writing registers reduces one address addition
972 * calculation, it was used in the '.rx_pkt_burst' and '.tx_pkt_burst' ops
973 * implementation function.
975 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value)
977 rte_write32(rte_cpu_to_le_32(value), addr);
980 static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
982 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg));
983 return rte_le_to_cpu_32(read_val);
986 #define hns3_write_dev(a, reg, value) \
987 hns3_write_reg((a)->io_base, (reg), (value))
989 #define hns3_read_dev(a, reg) \
990 hns3_read_reg((a)->io_base, (reg))
992 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
994 act = (actions) + (index); \
995 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
997 act = actions + index; \
1001 #define MSEC_PER_SEC 1000L
1002 #define USEC_PER_MSEC 1000L
1004 void hns3_clock_gettime(struct timeval *tv);
1005 uint64_t hns3_clock_calctime_ms(struct timeval *tv);
1006 uint64_t hns3_clock_gettime_ms(void);
1008 static inline uint64_t
1009 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
1013 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;
1018 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)
1020 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);
1024 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)
1026 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);
1029 static inline int64_t
1030 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)
1032 uint64_t mask = (1UL << nr);
1034 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
1037 int hns3_buffer_alloc(struct hns3_hw *hw);
1038 int hns3_dev_flow_ops_get(struct rte_eth_dev *dev,
1039 const struct rte_flow_ops **ops);
1040 bool hns3_is_reset_pending(struct hns3_adapter *hns);
1041 bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
1042 void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query);
1043 void hns3_ether_format_addr(char *buf, uint16_t size,
1044 const struct rte_ether_addr *ether_addr);
1045 int hns3_dev_infos_get(struct rte_eth_dev *eth_dev,
1046 struct rte_eth_dev_info *info);
1047 void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1048 uint32_t link_speed, uint8_t link_duplex);
1049 void hns3_parse_devargs(struct rte_eth_dev *dev);
1050 void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported);
1051 int hns3_restore_ptp(struct hns3_adapter *hns);
1052 int hns3_mbuf_dyn_rx_timestamp_register(struct rte_eth_dev *dev,
1053 struct rte_eth_conf *conf);
1054 int hns3_ptp_init(struct hns3_hw *hw);
1055 int hns3_timesync_enable(struct rte_eth_dev *dev);
1056 int hns3_timesync_disable(struct rte_eth_dev *dev);
1057 int hns3_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
1058 struct timespec *timestamp,
1059 uint32_t flags __rte_unused);
1060 int hns3_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
1061 struct timespec *timestamp);
1062 int hns3_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts);
1063 int hns3_timesync_write_time(struct rte_eth_dev *dev,
1064 const struct timespec *ts);
1065 int hns3_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
1068 is_reset_pending(struct hns3_adapter *hns)
1072 ret = hns3vf_is_reset_pending(hns);
1074 ret = hns3_is_reset_pending(hns);
1078 static inline uint64_t
1079 hns3_txvlan_cap_get(struct hns3_hw *hw)
1081 if (hw->port_base_vlan_cfg.state)
1082 return RTE_ETH_TX_OFFLOAD_VLAN_INSERT;
1084 return RTE_ETH_TX_OFFLOAD_VLAN_INSERT | RTE_ETH_TX_OFFLOAD_QINQ_INSERT;
1087 #endif /* _HNS3_ETHDEV_H_ */