1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #ifndef _HNS3_ETHDEV_H_
6 #define _HNS3_ETHDEV_H_
14 #define PCI_VENDOR_ID_HUAWEI 0x19e5
17 #define HNS3_DEV_ID_GE 0xA220
18 #define HNS3_DEV_ID_25GE 0xA221
19 #define HNS3_DEV_ID_25GE_RDMA 0xA222
20 #define HNS3_DEV_ID_50GE_RDMA 0xA224
21 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226
22 #define HNS3_DEV_ID_100G_VF 0xA22E
23 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
25 #define HNS3_UC_MACADDR_NUM 128
26 #define HNS3_VF_UC_MACADDR_NUM 48
27 #define HNS3_MC_MACADDR_NUM 128
29 #define HNS3_MAX_BD_SIZE 65535
30 #define HNS3_MAX_TX_BD_PER_PKT 8
31 #define HNS3_MAX_FRAME_LEN 9728
32 #define HNS3_MIN_FRAME_LEN 64
33 #define HNS3_VLAN_TAG_SIZE 4
34 #define HNS3_DEFAULT_RX_BUF_LEN 2048
36 #define HNS3_ETH_OVERHEAD \
37 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
38 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD)
39 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
40 #define HNS3_DEFAULT_MTU 1500UL
41 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
46 #define HNS3_MAX_PF_NUM 8
47 #define HNS3_UMV_TBL_SIZE 3072
48 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \
49 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM)
51 #define HNS3_PF_CFG_BLOCK_SIZE 32
52 #define HNS3_PF_CFG_DESC_NUM \
53 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES)
55 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0
57 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5
58 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500
60 #define HNS3_QUIT_RESET_CNT 10
61 #define HNS3_QUIT_RESET_DELAY_MS 100
63 #define HNS3_POLL_RESPONE_MS 1
65 #define HNS3_MAX_USER_PRIO 8
75 #define HNS3_SCH_MODE_SP 0
76 #define HNS3_SCH_MODE_DWRR 1
79 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */
82 uint8_t tc_dwrr[HNS3_MAX_TC_NUM];
87 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */
90 uint8_t up_to_tc_map; /* user priority maping on the TC */
93 struct hns3_dcb_info {
95 uint8_t num_pg; /* It must be 1 if vNET-Base schd */
96 uint8_t pg_dwrr[HNS3_PG_NUM];
97 uint8_t prio_tc[HNS3_MAX_USER_PRIO];
98 struct hns3_pg_info pg_info[HNS3_PG_NUM];
99 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM];
100 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */
101 uint8_t pfc_en; /* Pfc enabled or not for user priority */
104 enum hns3_fc_status {
106 HNS3_FC_STATUS_MAC_PAUSE,
110 struct hns3_tc_queue_info {
111 uint8_t tqp_offset; /* TQP offset from base TQP */
112 uint8_t tqp_count; /* Total TQPs */
113 uint8_t tc; /* TC index */
114 bool enable; /* If this TC is enable or not */
118 uint8_t vmdq_vport_num;
120 uint16_t tqp_desc_num;
122 uint16_t rss_size_max;
125 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
126 uint8_t default_speed;
127 uint32_t numa_node_map;
128 uint8_t speed_ability;
133 enum hns3_media_type {
134 HNS3_MEDIA_TYPE_UNKNOWN,
135 HNS3_MEDIA_TYPE_FIBER,
136 HNS3_MEDIA_TYPE_COPPER,
137 HNS3_MEDIA_TYPE_BACKPLANE,
138 HNS3_MEDIA_TYPE_NONE,
142 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
143 bool default_addr_setted; /* whether default addr(mac_addr) is setted */
146 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
147 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
148 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
149 uint32_t link_speed; /* ETH_SPEED_NUM_ */
153 /* Primary process maintains driver state in main thread.
156 * | UNINITIALIZED |<-----------+
157 * +---------------+ |
158 * |.eth_dev_init |.eth_dev_uninit
160 * +---------------+------------+
162 * +---------------+<-----------<---------------+
163 * |.dev_configure | |
165 * +---------------+------------+ |
167 * +---------------+----+ |
169 * | | +---------------+
171 * | | +---------------+
173 * V |.dev_configure |
174 * +---------------+----+ |.dev_close
175 * | CONFIGURED |----------------------------+
176 * +---------------+<-----------+
179 * +---------------+ |
180 * | STARTING |------------^
181 * +---------------+ failed |
183 * | +---------------+
185 * | +---------------+
188 * +---------------+------------+
192 enum hns3_adapter_state {
193 HNS3_NIC_UNINITIALIZED = 0,
194 HNS3_NIC_INITIALIZED,
195 HNS3_NIC_CONFIGURING,
206 /* Reset various stages, execute in order */
207 enum hns3_reset_stage {
208 /* Stop query services, stop transceiver, disable MAC */
210 /* Clear reset completion flags, disable send command */
212 /* Inform IMP to start resetting */
213 RESET_STAGE_REQ_HW_RESET,
214 /* Waiting for hardware reset to complete */
216 /* Reinitialize hardware */
217 RESET_STAGE_DEV_INIT,
218 /* Restore user settings and enable MAC */
220 /* Restart query services, start transceiver */
222 /* Not in reset state */
226 enum hns3_reset_level {
228 HNS3_VF_FUNC_RESET, /* A VF function reset */
230 * All VFs under a PF perform function reset.
231 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
232 * of the reset level and the one defined in kernel driver should be
235 HNS3_VF_PF_FUNC_RESET = 2,
237 * All VFs under a PF perform FLR reset.
238 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
239 * of the reset level and the one defined in kernel driver should be
242 HNS3_VF_FULL_RESET = 3,
243 HNS3_FLR_RESET, /* A VF perform FLR reset */
244 /* All VFs under the rootport perform a global or IMP reset */
246 HNS3_FUNC_RESET, /* A PF function reset */
247 /* All PFs under the rootport perform a global reset */
249 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
253 enum hns3_wait_result {
260 #define HNS3_RESET_SYNC_US 100000
262 struct hns3_reset_stats {
263 uint64_t request_cnt; /* Total request reset times */
264 uint64_t global_cnt; /* Total GLOBAL reset times */
265 uint64_t imp_cnt; /* Total IMP reset times */
266 uint64_t exec_cnt; /* Total reset executive times */
267 uint64_t success_cnt; /* Total reset successful times */
268 uint64_t fail_cnt; /* Total reset failed times */
269 uint64_t merge_cnt; /* Total merged in high reset times */
274 typedef bool (*check_completion_func)(struct hns3_hw *hw);
276 struct hns3_wait_data {
281 enum hns3_wait_result result;
282 check_completion_func check_completion;
285 struct hns3_reset_ops {
286 void (*reset_service)(void *arg);
287 int (*stop_service)(struct hns3_adapter *hns);
288 int (*prepare_reset)(struct hns3_adapter *hns);
289 int (*wait_hardware_ready)(struct hns3_adapter *hns);
290 int (*reinit_dev)(struct hns3_adapter *hns);
291 int (*restore_conf)(struct hns3_adapter *hns);
292 int (*start_service)(struct hns3_adapter *hns);
302 struct hns3_reset_data {
303 enum hns3_reset_stage stage;
304 rte_atomic16_t schedule;
305 /* Reset flag, covering the entire reset process */
306 rte_atomic16_t resetting;
307 /* Used to disable sending cmds during reset */
308 rte_atomic16_t disable_cmd;
309 /* The reset level being processed */
310 enum hns3_reset_level level;
311 /* Reset level set, each bit represents a reset level */
313 /* Request reset level set, from interrupt or mailbox */
315 int attempts; /* Reset failure retry */
316 int retries; /* Timeout failure retry in reset_post */
318 * At the time of global or IMP reset, the command cannot be sent to
319 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the
320 * reset process, so the mbuf is required to be released after the reset
321 * is completed.The mbuf_deferred_free is used to mark whether mbuf
322 * needs to be released.
324 bool mbuf_deferred_free;
325 struct timeval start_time;
326 struct hns3_reset_stats stats;
327 const struct hns3_reset_ops *ops;
328 struct hns3_wait_data *wait_data;
332 struct rte_eth_dev_data *data;
336 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
340 uint16_t total_tqps_num; /* total task queue pairs of this PF */
341 uint16_t tqps_num; /* num task queue pairs of this function */
342 uint16_t rss_size_max; /* HW defined max RSS task queue */
344 uint16_t num_tx_desc; /* desc num of per tx queue */
345 uint16_t num_rx_desc; /* desc num of per rx queue */
347 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
348 int mc_addrs_num; /* Multicast mac addresses number */
350 uint8_t num_tc; /* Total number of enabled TCs */
352 enum hns3_fc_mode current_mode;
353 enum hns3_fc_mode requested_mode;
354 struct hns3_dcb_info dcb_info;
355 enum hns3_fc_status current_fc_status; /* current flow control status */
356 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
358 uint16_t alloc_rss_size; /* Queue number per TC */
362 * PMD setup and configuration is not thread safe. Since it is not
363 * performance sensitive, it is better to guarantee thread-safety
364 * and add device level lock. Adapter control operations which
365 * change its state should acquire the lock.
368 enum hns3_adapter_state adapter_state;
369 struct hns3_reset_data reset;
372 #define HNS3_FLAG_TC_BASE_SCH_MODE 1
373 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2
375 struct hns3_err_msix_intr_stats {
376 uint64_t mac_afifo_tnl_intr_cnt;
377 uint64_t ppu_mpf_abnormal_intr_st2_cnt;
378 uint64_t ssu_port_based_pf_intr_cnt;
379 uint64_t ppp_pf_abnormal_intr_cnt;
380 uint64_t ppu_pf_abnormal_intr_cnt;
383 /* vlan entry information. */
384 struct hns3_user_vlan_table {
385 LIST_ENTRY(hns3_user_vlan_table) next;
390 struct hns3_port_base_vlan_config {
395 /* Vlan tag configuration for RX direction */
396 struct hns3_rx_vtag_cfg {
397 uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */
398 uint8_t strip_tag1_en; /* Whether strip inner vlan tag */
399 uint8_t strip_tag2_en; /* Whether strip outer vlan tag */
400 uint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */
401 uint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */
404 /* Vlan tag configuration for TX direction */
405 struct hns3_tx_vtag_cfg {
406 bool accept_tag1; /* Whether accept tag1 packet from host */
407 bool accept_untag1; /* Whether accept untag1 packet from host */
410 bool insert_tag1_en; /* Whether insert inner vlan tag */
411 bool insert_tag2_en; /* Whether insert outer vlan tag */
412 uint16_t default_tag1; /* The default inner vlan tag to insert */
413 uint16_t default_tag2; /* The default outer vlan tag to insert */
416 struct hns3_vtag_cfg {
417 struct hns3_rx_vtag_cfg rx_vcfg;
418 struct hns3_tx_vtag_cfg tx_vcfg;
421 /* Request types for IPC. */
422 enum hns3_mp_req_type {
423 HNS3_MP_REQ_START_RXTX = 1,
424 HNS3_MP_REQ_STOP_RXTX,
428 /* Pameters for IPC. */
429 struct hns3_mp_param {
430 enum hns3_mp_req_type type;
435 /* Request timeout for IPC. */
436 #define HNS3_MP_REQ_TIMEOUT_SEC 5
438 /* Key string for IPC. */
439 #define HNS3_MP_NAME "net_hns3_mp"
442 struct hns3_adapter *adapter;
445 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
446 uint32_t tx_buf_size; /* Tx buffer size for each TC */
447 uint32_t dv_buf_size; /* Dv buffer size for each TC */
449 uint16_t mps; /* Max packet size */
452 uint8_t tc_max; /* max number of tc driver supported */
453 uint8_t local_max_tc; /* max number of local tc */
455 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */
457 bool support_fc_autoneg; /* support FC autonegotiate */
459 uint16_t wanted_umv_size;
460 uint16_t max_umv_size;
461 uint16_t used_umv_size;
463 /* Statistics information for abnormal interrupt */
464 struct hns3_err_msix_intr_stats abn_int_stats;
466 bool support_sfp_query;
468 struct hns3_vtag_cfg vtag_config;
469 struct hns3_port_base_vlan_config port_base_vlan_cfg;
470 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
474 struct hns3_adapter *adapter;
477 struct hns3_adapter {
480 /* Specific for PF or VF */
481 bool is_vf; /* false - PF, true - VF */
488 #define HNS3_DEV_SUPPORT_DCB_B 0x0
490 #define hns3_dev_dcb_supported(hw) \
491 hns3_get_bit((hw)->flag, HNS3_DEV_SUPPORT_DCB_B)
493 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
494 (&((struct hns3_adapter *)adapter)->hw)
495 #define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \
496 ((struct hns3_adapter *)adapter)
497 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \
498 (&((struct hns3_adapter *)adapter)->pf)
499 #define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \
500 (&((struct hns3_adapter *)adapter)->vf)
501 #define HNS3_DEV_HW_TO_ADAPTER(hw) \
502 container_of(hw, struct hns3_adapter, hw)
504 #define hns3_set_field(origin, mask, shift, val) \
506 (origin) &= (~(mask)); \
507 (origin) |= ((val) << (shift)) & (mask); \
509 #define hns3_get_field(origin, mask, shift) \
510 (((origin) & (mask)) >> (shift))
511 #define hns3_set_bit(origin, shift, val) \
512 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val))
513 #define hns3_get_bit(origin, shift) \
514 hns3_get_field((origin), (0x1UL << (shift)), (shift))
517 * upper_32_bits - return bits 32-63 of a number
518 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
519 * the "right shift count >= width of type" warning when that quantity is
522 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
524 /* lower_32_bits - return bits 0-31 of a number */
525 #define lower_32_bits(n) ((uint32_t)(n))
527 #define BIT(nr) (1UL << (nr))
529 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
530 #define GENMASK(h, l) \
531 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
533 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
534 #define rounddown(x, y) ((x) - ((x) % (y)))
536 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
538 #define max_t(type, x, y) ({ \
541 __max1 > __max2 ? __max1 : __max2; })
543 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
545 rte_write32(value, (volatile void *)((char *)base + reg));
548 static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
550 return rte_read32((volatile void *)((char *)base + reg));
553 #define hns3_write_dev(a, reg, value) \
554 hns3_write_reg((a)->io_base, (reg), (value))
556 #define hns3_read_dev(a, reg) \
557 hns3_read_reg((a)->io_base, (reg))
559 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
561 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
563 act = (actions) + (index); \
564 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
566 act = actions + index; \
570 #define MSEC_PER_SEC 1000L
571 #define USEC_PER_MSEC 1000L
573 static inline uint64_t
574 get_timeofday_ms(void)
578 (void)gettimeofday(&tv, NULL);
580 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
583 static inline uint64_t
584 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
588 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;
593 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)
595 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);
599 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)
601 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);
604 static inline int64_t
605 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)
607 uint64_t mask = (1UL << nr);
609 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
612 int hns3_buffer_alloc(struct hns3_hw *hw);
613 int hns3_config_gro(struct hns3_hw *hw, bool en);
615 #endif /* _HNS3_ETHDEV_H_ */