1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #ifndef _HNS3_ETHDEV_H_
6 #define _HNS3_ETHDEV_H_
10 #include <rte_ethdev_driver.h>
15 #include "hns3_fdir.h"
16 #include "hns3_stats.h"
19 #define PCI_VENDOR_ID_HUAWEI 0x19e5
22 #define HNS3_DEV_ID_GE 0xA220
23 #define HNS3_DEV_ID_25GE 0xA221
24 #define HNS3_DEV_ID_25GE_RDMA 0xA222
25 #define HNS3_DEV_ID_50GE_RDMA 0xA224
26 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226
27 #define HNS3_DEV_ID_200G_RDMA 0xA228
28 #define HNS3_DEV_ID_100G_VF 0xA22E
29 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
31 /* PCI Config offsets */
32 #define HNS3_PCI_REVISION_ID 0x08
33 #define HNS3_PCI_REVISION_ID_LEN 1
35 #define PCI_REVISION_ID_HIP08_B 0x21
36 #define PCI_REVISION_ID_HIP09_A 0x30
38 #define HNS3_PF_FUNC_ID 0
39 #define HNS3_1ST_VF_FUNC_ID 1
41 #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0
42 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1
44 #define HNS3_UNLIMIT_PROMISC_MODE 0
45 #define HNS3_LIMIT_PROMISC_MODE 1
47 #define HNS3_UC_MACADDR_NUM 128
48 #define HNS3_VF_UC_MACADDR_NUM 48
49 #define HNS3_MC_MACADDR_NUM 128
51 #define HNS3_MAX_BD_SIZE 65535
52 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8
53 #define HNS3_MAX_TSO_BD_PER_PKT 63
54 #define HNS3_MAX_FRAME_LEN 9728
55 #define HNS3_VLAN_TAG_SIZE 4
56 #define HNS3_DEFAULT_RX_BUF_LEN 2048
57 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
58 #define HNS3_MAX_TSO_HDR_SIZE 512
59 #define HNS3_MAX_TSO_HDR_BD_NUM 3
60 #define HNS3_MAX_LRO_SIZE 64512
62 #define HNS3_ETH_OVERHEAD \
63 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
64 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD)
65 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
66 #define HNS3_DEFAULT_MTU 1500UL
67 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
68 #define HNS3_HIP08_MIN_TX_PKT_LEN 33
69 #define HNS3_HIP09_MIN_TX_PKT_LEN 9
71 #define HNS3_BITS_PER_BYTE 8
76 #define HNS3_MAX_PF_NUM 8
77 #define HNS3_UMV_TBL_SIZE 3072
78 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \
79 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM)
81 #define HNS3_PF_CFG_BLOCK_SIZE 32
82 #define HNS3_PF_CFG_DESC_NUM \
83 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES)
85 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0
87 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5
88 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500
90 #define HNS3_QUIT_RESET_CNT 10
91 #define HNS3_QUIT_RESET_DELAY_MS 100
93 #define HNS3_POLL_RESPONE_MS 1
95 #define HNS3_MAX_USER_PRIO 8
105 #define HNS3_SCH_MODE_SP 0
106 #define HNS3_SCH_MODE_DWRR 1
107 struct hns3_pg_info {
109 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */
112 uint8_t tc_dwrr[HNS3_MAX_TC_NUM];
115 struct hns3_tc_info {
117 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */
120 uint8_t up_to_tc_map; /* user priority maping on the TC */
123 struct hns3_dcb_info {
125 uint8_t num_pg; /* It must be 1 if vNET-Base schd */
126 uint8_t pg_dwrr[HNS3_PG_NUM];
127 uint8_t prio_tc[HNS3_MAX_USER_PRIO];
128 struct hns3_pg_info pg_info[HNS3_PG_NUM];
129 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM];
130 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */
131 uint8_t pfc_en; /* Pfc enabled or not for user priority */
134 enum hns3_fc_status {
136 HNS3_FC_STATUS_MAC_PAUSE,
140 struct hns3_tc_queue_info {
141 uint16_t tqp_offset; /* TQP offset from base TQP */
142 uint16_t tqp_count; /* Total TQPs */
143 uint8_t tc; /* TC index */
144 bool enable; /* If this TC is enable or not */
148 uint8_t vmdq_vport_num;
150 uint16_t tqp_desc_num;
152 uint16_t rss_size_max;
155 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
156 uint8_t default_speed;
157 uint32_t numa_node_map;
158 uint8_t speed_ability;
163 enum hns3_media_type {
164 HNS3_MEDIA_TYPE_UNKNOWN,
165 HNS3_MEDIA_TYPE_FIBER,
166 HNS3_MEDIA_TYPE_COPPER,
167 HNS3_MEDIA_TYPE_BACKPLANE,
168 HNS3_MEDIA_TYPE_NONE,
172 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
173 bool default_addr_setted; /* whether default addr(mac_addr) is setted */
176 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
177 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
178 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
179 uint32_t link_speed; /* ETH_SPEED_NUM_ */
182 struct hns3_fake_queue_data {
183 void **rx_queues; /* Array of pointers to fake RX queues. */
184 void **tx_queues; /* Array of pointers to fake TX queues. */
185 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */
186 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
189 #define HNS3_PORT_BASE_VLAN_DISABLE 0
190 #define HNS3_PORT_BASE_VLAN_ENABLE 1
191 struct hns3_port_base_vlan_config {
196 /* Primary process maintains driver state in main thread.
199 * | UNINITIALIZED |<-----------+
200 * +---------------+ |
201 * |.eth_dev_init |.eth_dev_uninit
203 * +---------------+------------+
205 * +---------------+<-----------<---------------+
206 * |.dev_configure | |
208 * +---------------+------------+ |
210 * +---------------+----+ |
212 * | | +---------------+
214 * | | +---------------+
216 * V |.dev_configure |
217 * +---------------+----+ |.dev_close
218 * | CONFIGURED |----------------------------+
219 * +---------------+<-----------+
222 * +---------------+ |
223 * | STARTING |------------^
224 * +---------------+ failed |
226 * | +---------------+
228 * | +---------------+
231 * +---------------+------------+
235 enum hns3_adapter_state {
236 HNS3_NIC_UNINITIALIZED = 0,
237 HNS3_NIC_INITIALIZED,
238 HNS3_NIC_CONFIGURING,
249 /* Reset various stages, execute in order */
250 enum hns3_reset_stage {
251 /* Stop query services, stop transceiver, disable MAC */
253 /* Clear reset completion flags, disable send command */
255 /* Inform IMP to start resetting */
256 RESET_STAGE_REQ_HW_RESET,
257 /* Waiting for hardware reset to complete */
259 /* Reinitialize hardware */
260 RESET_STAGE_DEV_INIT,
261 /* Restore user settings and enable MAC */
263 /* Restart query services, start transceiver */
265 /* Not in reset state */
269 enum hns3_reset_level {
271 HNS3_VF_FUNC_RESET, /* A VF function reset */
273 * All VFs under a PF perform function reset.
274 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
275 * of the reset level and the one defined in kernel driver should be
278 HNS3_VF_PF_FUNC_RESET = 2,
280 * All VFs under a PF perform FLR reset.
281 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
282 * of the reset level and the one defined in kernel driver should be
285 * According to the protocol of PCIe, FLR to a PF resets the PF state as
286 * well as the SR-IOV extended capability including VF Enable which
287 * means that VFs no longer exist.
289 * In PF FLR, the register state of VF is not reliable, VF's driver
290 * should not access the registers of the VF device.
292 HNS3_VF_FULL_RESET = 3,
293 HNS3_FLR_RESET, /* A VF perform FLR reset */
294 /* All VFs under the rootport perform a global or IMP reset */
296 HNS3_FUNC_RESET, /* A PF function reset */
297 /* All PFs under the rootport perform a global reset */
299 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
303 enum hns3_wait_result {
310 #define HNS3_RESET_SYNC_US 100000
312 struct hns3_reset_stats {
313 uint64_t request_cnt; /* Total request reset times */
314 uint64_t global_cnt; /* Total GLOBAL reset times */
315 uint64_t imp_cnt; /* Total IMP reset times */
316 uint64_t exec_cnt; /* Total reset executive times */
317 uint64_t success_cnt; /* Total reset successful times */
318 uint64_t fail_cnt; /* Total reset failed times */
319 uint64_t merge_cnt; /* Total merged in high reset times */
322 typedef bool (*check_completion_func)(struct hns3_hw *hw);
324 struct hns3_wait_data {
329 enum hns3_wait_result result;
330 check_completion_func check_completion;
333 struct hns3_reset_ops {
334 void (*reset_service)(void *arg);
335 int (*stop_service)(struct hns3_adapter *hns);
336 int (*prepare_reset)(struct hns3_adapter *hns);
337 int (*wait_hardware_ready)(struct hns3_adapter *hns);
338 int (*reinit_dev)(struct hns3_adapter *hns);
339 int (*restore_conf)(struct hns3_adapter *hns);
340 int (*start_service)(struct hns3_adapter *hns);
350 struct hns3_reset_data {
351 enum hns3_reset_stage stage;
352 rte_atomic16_t schedule;
353 /* Reset flag, covering the entire reset process */
354 rte_atomic16_t resetting;
355 /* Used to disable sending cmds during reset */
356 rte_atomic16_t disable_cmd;
357 /* The reset level being processed */
358 enum hns3_reset_level level;
359 /* Reset level set, each bit represents a reset level */
361 /* Request reset level set, from interrupt or mailbox */
363 int attempts; /* Reset failure retry */
364 int retries; /* Timeout failure retry in reset_post */
366 * At the time of global or IMP reset, the command cannot be sent to
367 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the
368 * reset process, so the mbuf is required to be released after the reset
369 * is completed.The mbuf_deferred_free is used to mark whether mbuf
370 * needs to be released.
372 bool mbuf_deferred_free;
373 struct timeval start_time;
374 struct hns3_reset_stats stats;
375 const struct hns3_reset_ops *ops;
376 struct hns3_wait_data *wait_data;
379 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0
380 #define HNS3_INTR_MAPPING_VEC_ALL 1
382 #define HNS3_INTR_COALESCE_NON_QL 0
383 #define HNS3_INTR_COALESCE_QL 1
385 #define HNS3_INTR_COALESCE_GL_UINT_2US 0
386 #define HNS3_INTR_COALESCE_GL_UINT_1US 1
388 struct hns3_queue_intr {
390 * interrupt mapping mode.
392 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL
394 * - HNS3_INTR_MAPPING_VEC_RSV_ONE
395 * For some versions of hardware network engine, because of the
396 * hardware constraint, we need implement clearing the mapping
397 * relationship configurations by binding all queues to the last
398 * interrupt vector and reserving the last interrupt vector. This
399 * method results in a decrease of the maximum queues when upper
400 * applications call the rte_eth_dev_configure API function to
401 * enable Rx interrupt.
403 * - HNS3_INTR_MAPPING_VEC_ALL
404 * PMD driver can map/unmmap all interrupt vectors with queues When
405 * Rx interrupt in enabled.
407 uint8_t mapping_mode;
409 * interrupt coalesce mode.
411 * HNS3_INTR_COALESCE_NON_QL/HNS3_INTR_COALESCE_QL
413 * - HNS3_INTR_COALESCE_NON_QL
414 * For some versions of hardware network engine, hardware doesn't
415 * support QL(quanity limiter) algorithm for interrupt coalesce
416 * of queue's interrupt.
418 * - HNS3_INTR_COALESCE_QL
419 * In this mode, hardware support QL(quanity limiter) algorithm for
420 * interrupt coalesce of queue's interrupt.
422 uint8_t coalesce_mode;
424 * The unit of GL(gap limiter) configuration for interrupt coalesce of
427 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US
432 #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0
433 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1
436 struct rte_eth_dev_data *data;
438 uint8_t revision; /* PCI revision, low byte of class word */
440 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
441 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */
442 pthread_t irq_thread_id;
444 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
445 struct hns3_tqp_stats tqp_stats;
446 /* Include Mac stats | Rx stats | Tx stats */
447 struct hns3_mac_stats mac_stats;
451 uint16_t total_tqps_num; /* total task queue pairs of this PF */
452 uint16_t tqps_num; /* num task queue pairs of this function */
453 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
454 uint16_t rss_size_max; /* HW defined max RSS task queue */
455 uint16_t rx_buf_len; /* hold min hardware rx buf len */
456 uint16_t num_tx_desc; /* desc num of per tx queue */
457 uint16_t num_rx_desc; /* desc num of per rx queue */
458 uint32_t mng_entry_num; /* number of manager table entry */
459 uint32_t mac_entry_num; /* number of mac-vlan table entry */
461 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
462 int mc_addrs_num; /* Multicast mac addresses number */
464 /* The configuration info of RSS */
465 struct hns3_rss_conf rss_info;
466 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
467 uint16_t rss_ind_tbl_size;
468 uint16_t rss_key_size;
470 uint8_t num_tc; /* Total number of enabled TCs */
472 enum hns3_fc_mode current_mode;
473 enum hns3_fc_mode requested_mode;
474 struct hns3_dcb_info dcb_info;
475 enum hns3_fc_status current_fc_status; /* current flow control status */
476 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
477 uint16_t used_rx_queues;
478 uint16_t used_tx_queues;
480 /* Config max queue numbers between rx and tx queues from user */
481 uint16_t cfg_max_queues;
482 struct hns3_fake_queue_data fkq_data; /* fake queue data */
483 uint16_t alloc_rss_size; /* RX queue number per TC */
484 uint16_t tx_qnum_per_tc; /* TX queue number per TC */
487 uint32_t max_tm_rate;
489 * The minimum length of the packet supported by hardware in the Tx
492 uint32_t min_tx_pkt_len;
494 struct hns3_queue_intr intr;
498 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
500 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM
501 * In this mode, because of the hardware constraint, network driver
502 * software need erase the L4 len value of the TCP pseudo header
503 * and recalculate the TCP pseudo header checksum of packets that
506 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
507 * In this mode, hardware support recalculate the TCP pseudo header
508 * checksum of packets that need TSO, so network driver software
509 * not need to recalculate it.
515 * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE
517 * - HNS3_SW_SHIFT_AND_DISCARD_MODE
518 * For some versions of hardware network engine, because of the
519 * hardware limitation, PMD driver needs to detect the PVID status
520 * to work with haredware to implement PVID-related functions.
521 * For example, driver need discard the stripped PVID tag to ensure
522 * the PVID will not report to mbuf and shift the inserted VLAN tag
523 * to avoid port based VLAN covering it.
525 * - HNS3_HW_SHIT_AND_DISCARD_MODE
526 * PMD driver does not need to process PVID-related functions in
527 * I/O process, Hardware will adjust the sequence between port based
528 * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by
529 * PVID will be invisible to driver. And in this mode, hns3 is able
530 * to send a multi-layer VLAN packets when hw VLAN insert offload
537 * HNS3_UNLIMIT_PROMISC_MODE/HNS3_LIMIT_PROMISC_MODE
539 * - HNS3_UNLIMIT_PROMISC_MODE
540 * In this mode, TX unicast promisc will be configured when promisc
541 * is set, driver can receive all the ingress and outgoing traffic.
542 * In the words, all the ingress packets, all the packets sent from
543 * the PF and other VFs on the same physical port.
545 * - HNS3_LIMIT_PROMISC_MODE
546 * In this mode, TX unicast promisc is shutdown when promisc mode
547 * is set. So, driver will only receive all the ingress traffic.
548 * The packets sent from the PF and other VFs on the same physical
549 * port won't be copied to the function which has set promisc mode.
551 uint8_t promisc_mode;
552 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
554 struct hns3_port_base_vlan_config port_base_vlan_cfg;
556 * PMD setup and configuration is not thread safe. Since it is not
557 * performance sensitive, it is better to guarantee thread-safety
558 * and add device level lock. Adapter control operations which
559 * change its state should acquire the lock.
562 enum hns3_adapter_state adapter_state;
563 struct hns3_reset_data reset;
566 #define HNS3_FLAG_TC_BASE_SCH_MODE 1
567 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2
569 struct hns3_err_msix_intr_stats {
570 uint64_t mac_afifo_tnl_int_cnt;
571 uint64_t ppu_mpf_abn_int_st2_msix_cnt;
572 uint64_t ssu_port_based_pf_int_cnt;
573 uint64_t ppp_pf_abnormal_int_cnt;
574 uint64_t ppu_pf_abnormal_int_msix_cnt;
576 uint64_t imp_tcm_ecc_int_cnt;
577 uint64_t cmdq_mem_ecc_int_cnt;
578 uint64_t imp_rd_poison_int_cnt;
579 uint64_t tqp_int_ecc_int_cnt;
580 uint64_t msix_ecc_int_cnt;
581 uint64_t ssu_ecc_multi_bit_int_0_cnt;
582 uint64_t ssu_ecc_multi_bit_int_1_cnt;
583 uint64_t ssu_common_ecc_int_cnt;
584 uint64_t igu_int_cnt;
585 uint64_t ppp_mpf_abnormal_int_st1_cnt;
586 uint64_t ppp_mpf_abnormal_int_st3_cnt;
587 uint64_t ppu_mpf_abnormal_int_st1_cnt;
588 uint64_t ppu_mpf_abn_int_st2_ras_cnt;
589 uint64_t ppu_mpf_abnormal_int_st3_cnt;
590 uint64_t tm_sch_int_cnt;
591 uint64_t qcn_fifo_int_cnt;
592 uint64_t qcn_ecc_int_cnt;
593 uint64_t ncsi_ecc_int_cnt;
594 uint64_t ssu_port_based_err_int_cnt;
595 uint64_t ssu_fifo_overflow_int_cnt;
596 uint64_t ssu_ets_tcg_int_cnt;
597 uint64_t igu_egu_tnl_int_cnt;
598 uint64_t ppu_pf_abnormal_int_ras_cnt;
601 /* vlan entry information. */
602 struct hns3_user_vlan_table {
603 LIST_ENTRY(hns3_user_vlan_table) next;
608 /* Vlan tag configuration for RX direction */
609 struct hns3_rx_vtag_cfg {
610 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */
611 bool strip_tag1_en; /* Whether strip inner vlan tag */
612 bool strip_tag2_en; /* Whether strip outer vlan tag */
614 * If strip_tag_en is enabled, this bit decide whether to map the vlan
617 bool strip_tag1_discard_en;
618 bool strip_tag2_discard_en;
620 * If this bit is enabled, only map inner/outer priority to descriptor
621 * and the vlan tag is always 0.
623 bool vlan1_vlan_prionly;
624 bool vlan2_vlan_prionly;
627 /* Vlan tag configuration for TX direction */
628 struct hns3_tx_vtag_cfg {
629 bool accept_tag1; /* Whether accept tag1 packet from host */
630 bool accept_untag1; /* Whether accept untag1 packet from host */
633 bool insert_tag1_en; /* Whether insert outer vlan tag */
634 bool insert_tag2_en; /* Whether insert inner vlan tag */
636 * In shift mode, hw will shift the sequence of port based VLAN and
639 bool tag_shift_mode_en; /* hw shift vlan tag automatically */
640 uint16_t default_tag1; /* The default outer vlan tag to insert */
641 uint16_t default_tag2; /* The default inner vlan tag to insert */
644 struct hns3_vtag_cfg {
645 struct hns3_rx_vtag_cfg rx_vcfg;
646 struct hns3_tx_vtag_cfg tx_vcfg;
649 /* Request types for IPC. */
650 enum hns3_mp_req_type {
651 HNS3_MP_REQ_START_RXTX = 1,
652 HNS3_MP_REQ_STOP_RXTX,
656 /* Pameters for IPC. */
657 struct hns3_mp_param {
658 enum hns3_mp_req_type type;
663 /* Request timeout for IPC. */
664 #define HNS3_MP_REQ_TIMEOUT_SEC 5
666 /* Key string for IPC. */
667 #define HNS3_MP_NAME "net_hns3_mp"
669 #define HNS3_L2TBL_NUM 4
670 #define HNS3_L3TBL_NUM 16
671 #define HNS3_L4TBL_NUM 16
672 #define HNS3_OL2TBL_NUM 4
673 #define HNS3_OL3TBL_NUM 16
674 #define HNS3_OL4TBL_NUM 16
676 struct hns3_ptype_table {
677 uint32_t l2l3table[HNS3_L2TBL_NUM][HNS3_L3TBL_NUM];
678 uint32_t l4table[HNS3_L4TBL_NUM];
679 uint32_t inner_l2table[HNS3_L2TBL_NUM];
680 uint32_t inner_l3table[HNS3_L3TBL_NUM];
681 uint32_t inner_l4table[HNS3_L4TBL_NUM];
682 uint32_t ol2table[HNS3_OL2TBL_NUM];
683 uint32_t ol3table[HNS3_OL3TBL_NUM];
684 uint32_t ol4table[HNS3_OL4TBL_NUM];
687 #define HNS3_FIXED_MAX_TQP_NUM_MODE 0
688 #define HNS3_FLEX_MAX_TQP_NUM_MODE 1
691 struct hns3_adapter *adapter;
693 uint16_t func_num; /* num functions of this pf, include pf and vfs */
697 * tqp_config_mode value range:
698 * HNS3_FIXED_MAX_TQP_NUM_MODE,
699 * HNS3_FLEX_MAX_TQP_NUM_MODE
701 * - HNS3_FIXED_MAX_TQP_NUM_MODE
702 * There is a limitation on the number of pf interrupts available for
703 * on some versions of network engines. In this case, the maximum
704 * queue number of pf can not be greater than the interrupt number,
705 * such as pf of network engine with revision_id 0x21. So the maximum
706 * number of queues must be fixed.
708 * - HNS3_FLEX_MAX_TQP_NUM_MODE
709 * In this mode, the maximum queue number of pf has not any constraint
710 * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF
711 * in the config file. Users can modify the macro according to their
712 * own application scenarios, which is more flexible to use.
714 uint8_t tqp_config_mode;
716 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
717 uint32_t tx_buf_size; /* Tx buffer size for each TC */
718 uint32_t dv_buf_size; /* Dv buffer size for each TC */
720 uint16_t mps; /* Max packet size */
723 uint8_t tc_max; /* max number of tc driver supported */
724 uint8_t local_max_tc; /* max number of local tc */
726 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */
728 bool support_fc_autoneg; /* support FC autonegotiate */
730 uint16_t wanted_umv_size;
731 uint16_t max_umv_size;
732 uint16_t used_umv_size;
734 /* Statistics information for abnormal interrupt */
735 struct hns3_err_msix_intr_stats abn_int_stats;
737 bool support_sfp_query;
738 uint32_t fec_mode; /* current FEC mode for ethdev */
740 struct hns3_vtag_cfg vtag_config;
741 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
743 struct hns3_fdir_info fdir; /* flow director info */
744 LIST_HEAD(counters, hns3_flow_counter) flow_counters;
748 struct hns3_adapter *adapter;
751 struct hns3_adapter {
754 /* Specific for PF or VF */
755 bool is_vf; /* false - PF, true - VF */
761 bool rx_simple_allowed;
763 bool tx_simple_allowed;
766 struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
769 #define HNS3_DEV_SUPPORT_DCB_B 0x0
770 #define HNS3_DEV_SUPPORT_COPPER_B 0x1
771 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
772 #define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3
773 #define HNS3_DEV_SUPPORT_PTP_B 0x4
774 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5
775 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6
776 #define HNS3_DEV_SUPPORT_STASH_B 0x7
778 #define hns3_dev_dcb_supported(hw) \
779 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
781 /* Support copper media type */
782 #define hns3_dev_copper_supported(hw) \
783 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B)
785 /* Support UDP GSO offload */
786 #define hns3_dev_udp_gso_supported(hw) \
787 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
789 /* Support the queue region action rule of flow directory */
790 #define hns3_dev_fd_queue_region_supported(hw) \
791 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B)
793 /* Support PTP timestamp offload */
794 #define hns3_dev_ptp_supported(hw) \
795 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B)
797 #define hns3_dev_tx_push_supported(hw) \
798 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)
800 /* Support to Independently enable/disable/reset Tx or Rx queues */
801 #define hns3_dev_indep_txrx_supported(hw) \
802 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B)
804 #define hns3_dev_stash_supported(hw) \
805 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B)
807 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
808 (&((struct hns3_adapter *)adapter)->hw)
809 #define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \
810 ((struct hns3_adapter *)adapter)
811 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \
812 (&((struct hns3_adapter *)adapter)->pf)
813 #define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \
814 (&((struct hns3_adapter *)adapter)->vf)
815 #define HNS3_DEV_HW_TO_ADAPTER(hw) \
816 container_of(hw, struct hns3_adapter, hw)
818 #define hns3_set_field(origin, mask, shift, val) \
820 (origin) &= (~(mask)); \
821 (origin) |= ((val) << (shift)) & (mask); \
823 #define hns3_get_field(origin, mask, shift) \
824 (((origin) & (mask)) >> (shift))
825 #define hns3_set_bit(origin, shift, val) \
826 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val))
827 #define hns3_get_bit(origin, shift) \
828 hns3_get_field((origin), (0x1UL << (shift)), (shift))
830 #define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask))
833 * upper_32_bits - return bits 32-63 of a number
834 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
835 * the "right shift count >= width of type" warning when that quantity is
838 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
840 /* lower_32_bits - return bits 0-31 of a number */
841 #define lower_32_bits(n) ((uint32_t)(n))
843 #define BIT(nr) (1UL << (nr))
845 #define BIT_ULL(x) (1ULL << (x))
847 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
848 #define GENMASK(h, l) \
849 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
851 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
852 #define rounddown(x, y) ((x) - ((x) % (y)))
854 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
857 * Because hardware always access register in little-endian mode based on hns3
858 * network engine, so driver should also call rte_cpu_to_le_32 to convert data
859 * in little-endian mode before writing register and call rte_le_to_cpu_32 to
860 * convert data after reading from register.
862 * Here the driver encapsulates the data conversion operation in the register
863 * read/write operation function as below:
867 * Therefore, when calling these functions, conversion is not required again.
869 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
871 rte_write32(rte_cpu_to_le_32(value),
872 (volatile void *)((char *)base + reg));
876 * The optimized function for writing registers used in the '.rx_pkt_burst' and
877 * '.tx_pkt_burst' ops implementation function.
879 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value)
882 rte_write32_relaxed(rte_cpu_to_le_32(value), addr);
885 static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
887 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg));
888 return rte_le_to_cpu_32(read_val);
891 #define hns3_write_dev(a, reg, value) \
892 hns3_write_reg((a)->io_base, (reg), (value))
894 #define hns3_read_dev(a, reg) \
895 hns3_read_reg((a)->io_base, (reg))
897 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
899 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
901 act = (actions) + (index); \
902 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
904 act = actions + index; \
908 #define MSEC_PER_SEC 1000L
909 #define USEC_PER_MSEC 1000L
911 static inline uint64_t
912 get_timeofday_ms(void)
916 (void)gettimeofday(&tv, NULL);
918 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
921 static inline uint64_t
922 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
926 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;
931 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)
933 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);
937 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)
939 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);
942 static inline int64_t
943 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)
945 uint64_t mask = (1UL << nr);
947 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
950 int hns3_buffer_alloc(struct hns3_hw *hw);
951 int hns3_dev_filter_ctrl(struct rte_eth_dev *dev,
952 enum rte_filter_type filter_type,
953 enum rte_filter_op filter_op, void *arg);
954 bool hns3_is_reset_pending(struct hns3_adapter *hns);
955 bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
956 void hns3_update_link_status(struct hns3_hw *hw);
959 is_reset_pending(struct hns3_adapter *hns)
963 ret = hns3vf_is_reset_pending(hns);
965 ret = hns3_is_reset_pending(hns);
969 static inline uint64_t
970 hns3_txvlan_cap_get(struct hns3_hw *hw)
972 if (hw->port_base_vlan_cfg.state)
973 return DEV_TX_OFFLOAD_VLAN_INSERT;
975 return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT;
978 #endif /* _HNS3_ETHDEV_H_ */