1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
5 #ifndef _HNS3_ETHDEV_H_
6 #define _HNS3_ETHDEV_H_
10 #include <ethdev_driver.h>
11 #include <rte_byteorder.h>
13 #include <rte_spinlock.h>
18 #include "hns3_fdir.h"
19 #include "hns3_stats.h"
23 #define PCI_VENDOR_ID_HUAWEI 0x19e5
26 #define HNS3_DEV_ID_GE 0xA220
27 #define HNS3_DEV_ID_25GE 0xA221
28 #define HNS3_DEV_ID_25GE_RDMA 0xA222
29 #define HNS3_DEV_ID_50GE_RDMA 0xA224
30 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226
31 #define HNS3_DEV_ID_200G_RDMA 0xA228
32 #define HNS3_DEV_ID_100G_VF 0xA22E
33 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
35 /* PCI Config offsets */
36 #define HNS3_PCI_REVISION_ID 0x08
37 #define HNS3_PCI_REVISION_ID_LEN 1
39 #define PCI_REVISION_ID_HIP08_B 0x21
40 #define PCI_REVISION_ID_HIP09_A 0x30
42 #define HNS3_PF_FUNC_ID 0
43 #define HNS3_1ST_VF_FUNC_ID 1
45 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
46 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
48 #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0
49 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1
51 #define HNS3_UNLIMIT_PROMISC_MODE 0
52 #define HNS3_LIMIT_PROMISC_MODE 1
54 #define HNS3_SPECIAL_PORT_SW_CKSUM_MODE 0
55 #define HNS3_SPECIAL_PORT_HW_CKSUM_MODE 1
57 #define HNS3_UC_MACADDR_NUM 128
58 #define HNS3_VF_UC_MACADDR_NUM 48
59 #define HNS3_MC_MACADDR_NUM 128
61 #define HNS3_MAX_BD_SIZE 65535
62 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8
63 #define HNS3_MAX_TSO_BD_PER_PKT 63
64 #define HNS3_MAX_FRAME_LEN 9728
65 #define HNS3_VLAN_TAG_SIZE 4
66 #define HNS3_DEFAULT_RX_BUF_LEN 2048
67 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
68 #define HNS3_MAX_TSO_HDR_SIZE 512
69 #define HNS3_MAX_TSO_HDR_BD_NUM 3
70 #define HNS3_MAX_LRO_SIZE 64512
72 #define HNS3_ETH_OVERHEAD \
73 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
74 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD)
75 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
76 #define HNS3_DEFAULT_MTU 1500UL
77 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
78 #define HNS3_HIP08_MIN_TX_PKT_LEN 33
79 #define HNS3_HIP09_MIN_TX_PKT_LEN 9
81 #define HNS3_BITS_PER_BYTE 8
86 #define HNS3_MAX_PF_NUM 8
87 #define HNS3_UMV_TBL_SIZE 3072
88 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \
89 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM)
91 #define HNS3_PF_CFG_BLOCK_SIZE 32
92 #define HNS3_PF_CFG_DESC_NUM \
93 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES)
95 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0
97 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5
98 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500
100 #define HNS3_QUIT_RESET_CNT 10
101 #define HNS3_QUIT_RESET_DELAY_MS 100
103 #define HNS3_POLL_RESPONE_MS 1
105 #define HNS3_MAX_USER_PRIO 8
106 #define HNS3_PG_NUM 4
115 #define HNS3_SCH_MODE_SP 0
116 #define HNS3_SCH_MODE_DWRR 1
117 struct hns3_pg_info {
119 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */
122 uint8_t tc_dwrr[HNS3_MAX_TC_NUM];
125 struct hns3_tc_info {
127 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */
130 uint8_t up_to_tc_map; /* user priority maping on the TC */
133 struct hns3_dcb_info {
135 uint8_t num_pg; /* It must be 1 if vNET-Base schd */
136 uint8_t pg_dwrr[HNS3_PG_NUM];
137 uint8_t prio_tc[HNS3_MAX_USER_PRIO];
138 struct hns3_pg_info pg_info[HNS3_PG_NUM];
139 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM];
140 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */
141 uint8_t pfc_en; /* Pfc enabled or not for user priority */
144 enum hns3_fc_status {
146 HNS3_FC_STATUS_MAC_PAUSE,
150 struct hns3_tc_queue_info {
151 uint16_t tqp_offset; /* TQP offset from base TQP */
152 uint16_t tqp_count; /* Total TQPs */
153 uint8_t tc; /* TC index */
154 bool enable; /* If this TC is enable or not */
158 uint8_t vmdq_vport_num;
160 uint16_t tqp_desc_num;
162 uint16_t rss_size_max;
165 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
166 uint8_t default_speed;
167 uint32_t numa_node_map;
168 uint8_t speed_ability;
172 struct hns3_set_link_speed_cfg {
179 enum hns3_media_type {
180 HNS3_MEDIA_TYPE_UNKNOWN,
181 HNS3_MEDIA_TYPE_FIBER,
182 HNS3_MEDIA_TYPE_COPPER,
183 HNS3_MEDIA_TYPE_BACKPLANE,
184 HNS3_MEDIA_TYPE_NONE,
187 #define HNS3_DEFAULT_QUERY 0
188 #define HNS3_ACTIVE_QUERY 1
191 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
192 bool default_addr_setted; /* whether default addr(mac_addr) is set */
195 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
196 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
197 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
198 uint32_t link_speed; /* ETH_SPEED_NUM_ */
200 * Some firmware versions support only the SFP speed query. In addition
201 * to the SFP speed query, some firmware supports the query of the speed
202 * capability, auto-negotiation capability, and FEC mode, which can be
203 * selected by the 'query_type' filed in the HNS3_OPC_GET_SFP_INFO CMD.
204 * This field is used to record the SFP information query mode.
206 * HNS3_DEFAULT_QUERY/HNS3_ACTIVE_QUERY
208 * - HNS3_DEFAULT_QUERY
209 * Speed obtained is from SFP. When the queried speed changes, the MAC
210 * speed needs to be reconfigured.
212 * - HNS3_ACTIVE_QUERY
213 * Speed obtained is from MAC. At this time, it is unnecessary for
214 * driver to reconfigured the MAC speed. In addition, more information,
215 * such as, the speed capability, auto-negotiation capability and FEC
216 * mode, can be obtained by the HNS3_OPC_GET_SFP_INFO CMD.
219 uint32_t supported_speed; /* supported speed for current media type */
220 uint32_t advertising; /* advertised capability in the local part */
221 uint32_t lp_advertising; /* advertised capability in the link partner */
222 uint8_t support_autoneg;
225 struct hns3_fake_queue_data {
226 void **rx_queues; /* Array of pointers to fake RX queues. */
227 void **tx_queues; /* Array of pointers to fake TX queues. */
228 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */
229 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
232 #define HNS3_PORT_BASE_VLAN_DISABLE 0
233 #define HNS3_PORT_BASE_VLAN_ENABLE 1
234 struct hns3_port_base_vlan_config {
239 /* Primary process maintains driver state in main thread.
242 * | UNINITIALIZED |<-----------+
243 * +---------------+ |
244 * |.eth_dev_init |.eth_dev_uninit
246 * +---------------+------------+
248 * +---------------+<-----------<---------------+
249 * |.dev_configure | |
251 * +---------------+------------+ |
253 * +---------------+----+ |
255 * | | +---------------+
257 * | | +---------------+
259 * V |.dev_configure |
260 * +---------------+----+ |.dev_close
261 * | CONFIGURED |----------------------------+
262 * +---------------+<-----------+
265 * +---------------+ |
266 * | STARTING |------------^
267 * +---------------+ failed |
269 * | +---------------+
271 * | +---------------+
274 * +---------------+------------+
278 enum hns3_adapter_state {
279 HNS3_NIC_UNINITIALIZED = 0,
280 HNS3_NIC_INITIALIZED,
281 HNS3_NIC_CONFIGURING,
292 /* Reset various stages, execute in order */
293 enum hns3_reset_stage {
294 /* Stop query services, stop transceiver, disable MAC */
296 /* Clear reset completion flags, disable send command */
298 /* Inform IMP to start resetting */
299 RESET_STAGE_REQ_HW_RESET,
300 /* Waiting for hardware reset to complete */
302 /* Reinitialize hardware */
303 RESET_STAGE_DEV_INIT,
304 /* Restore user settings and enable MAC */
306 /* Restart query services, start transceiver */
308 /* Not in reset state */
312 enum hns3_reset_level {
313 HNS3_FLR_RESET, /* A VF perform FLR reset */
314 HNS3_VF_FUNC_RESET, /* A VF function reset */
317 * All VFs under a PF perform function reset.
318 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
319 * of the reset level and the one defined in kernel driver should be
322 HNS3_VF_PF_FUNC_RESET = 2,
325 * All VFs under a PF perform FLR reset.
326 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
327 * of the reset level and the one defined in kernel driver should be
330 * According to the protocol of PCIe, FLR to a PF resets the PF state as
331 * well as the SR-IOV extended capability including VF Enable which
332 * means that VFs no longer exist.
334 * In PF FLR, the register state of VF is not reliable, VF's driver
335 * should not access the registers of the VF device.
339 /* All VFs under the rootport perform a global or IMP reset */
343 * The enumeration value of HNS3_FUNC_RESET/HNS3_GLOBAL_RESET/
344 * HNS3_IMP_RESET/HNS3_NONE_RESET are also used by firmware, and
345 * can not be changed.
348 HNS3_FUNC_RESET = 5, /* A PF function reset */
350 /* All PFs under the rootport perform a global reset */
352 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
357 enum hns3_wait_result {
364 #define HNS3_RESET_SYNC_US 100000
366 struct hns3_reset_stats {
367 uint64_t request_cnt; /* Total request reset times */
368 uint64_t global_cnt; /* Total GLOBAL reset times */
369 uint64_t imp_cnt; /* Total IMP reset times */
370 uint64_t exec_cnt; /* Total reset executive times */
371 uint64_t success_cnt; /* Total reset successful times */
372 uint64_t fail_cnt; /* Total reset failed times */
373 uint64_t merge_cnt; /* Total merged in high reset times */
376 typedef bool (*check_completion_func)(struct hns3_hw *hw);
378 struct hns3_wait_data {
383 enum hns3_wait_result result;
384 check_completion_func check_completion;
387 struct hns3_reset_ops {
388 void (*reset_service)(void *arg);
389 int (*stop_service)(struct hns3_adapter *hns);
390 int (*prepare_reset)(struct hns3_adapter *hns);
391 int (*wait_hardware_ready)(struct hns3_adapter *hns);
392 int (*reinit_dev)(struct hns3_adapter *hns);
393 int (*restore_conf)(struct hns3_adapter *hns);
394 int (*start_service)(struct hns3_adapter *hns);
404 struct hns3_reset_data {
405 enum hns3_reset_stage stage;
407 /* Reset flag, covering the entire reset process */
409 /* Used to disable sending cmds during reset */
410 uint16_t disable_cmd;
411 /* The reset level being processed */
412 enum hns3_reset_level level;
413 /* Reset level set, each bit represents a reset level */
415 /* Request reset level set, from interrupt or mailbox */
417 int attempts; /* Reset failure retry */
418 int retries; /* Timeout failure retry in reset_post */
420 * At the time of global or IMP reset, the command cannot be sent to
421 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the
422 * reset process, so the mbuf is required to be released after the reset
423 * is completed.The mbuf_deferred_free is used to mark whether mbuf
424 * needs to be released.
426 bool mbuf_deferred_free;
427 struct timeval start_time;
428 struct hns3_reset_stats stats;
429 const struct hns3_reset_ops *ops;
430 struct hns3_wait_data *wait_data;
433 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0
434 #define HNS3_INTR_MAPPING_VEC_ALL 1
436 #define HNS3_INTR_COALESCE_GL_UINT_2US 0
437 #define HNS3_INTR_COALESCE_GL_UINT_1US 1
439 #define HNS3_INTR_QL_NONE 0
441 struct hns3_queue_intr {
443 * interrupt mapping mode.
445 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL
447 * - HNS3_INTR_MAPPING_VEC_RSV_ONE
448 * For some versions of hardware network engine, because of the
449 * hardware constraint, we need implement clearing the mapping
450 * relationship configurations by binding all queues to the last
451 * interrupt vector and reserving the last interrupt vector. This
452 * method results in a decrease of the maximum queues when upper
453 * applications call the rte_eth_dev_configure API function to
454 * enable Rx interrupt.
456 * - HNS3_INTR_MAPPING_VEC_ALL
457 * PMD driver can map/unmmap all interrupt vectors with queues When
458 * Rx interrupt in enabled.
460 uint8_t mapping_mode;
462 * The unit of GL(gap limiter) configuration for interrupt coalesce of
465 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US
468 /* The max QL(quantity limiter) value */
472 #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0
473 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1
475 #define HNS3_PKTS_DROP_STATS_MODE1 0
476 #define HNS3_PKTS_DROP_STATS_MODE2 1
479 struct rte_eth_dev_data *data;
481 uint8_t revision; /* PCI revision, low byte of class word */
483 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
485 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
486 struct hns3_tqp_stats tqp_stats;
487 /* Include Mac stats | Rx stats | Tx stats */
488 struct hns3_mac_stats mac_stats;
489 struct hns3_rx_missed_stats imissed_stats;
490 uint64_t oerror_stats;
494 uint16_t total_tqps_num; /* total task queue pairs of this PF */
495 uint16_t tqps_num; /* num task queue pairs of this function */
496 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
497 uint16_t rss_size_max; /* HW defined max RSS task queue */
498 uint16_t rx_buf_len; /* hold min hardware rx buf len */
499 uint16_t num_tx_desc; /* desc num of per tx queue */
500 uint16_t num_rx_desc; /* desc num of per rx queue */
501 uint32_t mng_entry_num; /* number of manager table entry */
502 uint32_t mac_entry_num; /* number of mac-vlan table entry */
504 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
505 int mc_addrs_num; /* Multicast mac addresses number */
507 /* The configuration info of RSS */
508 struct hns3_rss_conf rss_info;
509 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
510 uint16_t rss_ind_tbl_size;
511 uint16_t rss_key_size;
513 uint8_t num_tc; /* Total number of enabled TCs */
515 enum hns3_fc_mode requested_fc_mode; /* FC mode requested by user */
516 struct hns3_dcb_info dcb_info;
517 enum hns3_fc_status current_fc_status; /* current flow control status */
518 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
519 uint16_t used_rx_queues;
520 uint16_t used_tx_queues;
522 /* Config max queue numbers between rx and tx queues from user */
523 uint16_t cfg_max_queues;
524 struct hns3_fake_queue_data fkq_data; /* fake queue data */
525 uint16_t alloc_rss_size; /* RX queue number per TC */
526 uint16_t tx_qnum_per_tc; /* TX queue number per TC */
529 uint32_t max_tm_rate;
531 * The minimum length of the packet supported by hardware in the Tx
534 uint32_t min_tx_pkt_len;
536 struct hns3_queue_intr intr;
540 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
542 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM
543 * In this mode, because of the hardware constraint, network driver
544 * software need erase the L4 len value of the TCP pseudo header
545 * and recalculate the TCP pseudo header checksum of packets that
548 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
549 * In this mode, hardware support recalculate the TCP pseudo header
550 * checksum of packets that need TSO, so network driver software
551 * not need to recalculate it.
557 * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE
559 * - HNS3_SW_SHIFT_AND_DISCARD_MODE
560 * For some versions of hardware network engine, because of the
561 * hardware limitation, PMD driver needs to detect the PVID status
562 * to work with haredware to implement PVID-related functions.
563 * For example, driver need discard the stripped PVID tag to ensure
564 * the PVID will not report to mbuf and shift the inserted VLAN tag
565 * to avoid port based VLAN covering it.
567 * - HNS3_HW_SHIT_AND_DISCARD_MODE
568 * PMD driver does not need to process PVID-related functions in
569 * I/O process, Hardware will adjust the sequence between port based
570 * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by
571 * PVID will be invisible to driver. And in this mode, hns3 is able
572 * to send a multi-layer VLAN packets when hw VLAN insert offload
579 * HNS3_UNLIMIT_PROMISC_MODE/HNS3_LIMIT_PROMISC_MODE
581 * - HNS3_UNLIMIT_PROMISC_MODE
582 * In this mode, TX unicast promisc will be configured when promisc
583 * is set, driver can receive all the ingress and outgoing traffic.
584 * In the words, all the ingress packets, all the packets sent from
585 * the PF and other VFs on the same physical port.
587 * - HNS3_LIMIT_PROMISC_MODE
588 * In this mode, TX unicast promisc is shutdown when promisc mode
589 * is set. So, driver will only receive all the ingress traffic.
590 * The packets sent from the PF and other VFs on the same physical
591 * port won't be copied to the function which has set promisc mode.
593 uint8_t promisc_mode;
596 * drop_stats_mode mode.
598 * HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2
600 * - HNS3_PKTS_DROP_STATS_MODE1
601 * This mode for kunpeng920. In this mode, port level imissed stats
602 * is supported. It only includes RPU drop stats.
604 * - HNS3_PKTS_DROP_STATS_MODE2
605 * This mode for kunpeng930. In this mode, imissed stats and oerrors
606 * stats is supported. Function level imissed stats is supported. It
607 * includes RPU drop stats in VF, and includes both RPU drop stats
608 * and SSU drop stats in PF. Oerror stats is also supported in PF.
610 uint8_t drop_stats_mode;
612 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
616 * HNS3_SPECIAL_PORT_HW_CKSUM_MODE/HNS3_SPECIAL_PORT_SW_CKSUM_MODE
618 * - HNS3_SPECIAL_PORT_SW_CKSUM_MODE
619 * In this mode, HW can not do checksum for special UDP port like
620 * 4789, 4790, 6081 for non-tunnel UDP packets and UDP tunnel
621 * packets without the PKT_TX_TUNEL_MASK in the mbuf. So, PMD need
622 * do the checksum for these packets to avoid a checksum error.
624 * - HNS3_SPECIAL_PORT_HW_CKSUM_MODE
625 * In this mode, HW does not have the preceding problems and can
626 * directly calculate the checksum of these UDP packets.
628 uint8_t udp_cksum_mode;
630 struct hns3_port_base_vlan_config port_base_vlan_cfg;
632 pthread_mutex_t flows_lock; /* rte_flow ops lock */
635 * PMD setup and configuration is not thread safe. Since it is not
636 * performance sensitive, it is better to guarantee thread-safety
637 * and add device level lock. Adapter control operations which
638 * change its state should acquire the lock.
641 enum hns3_adapter_state adapter_state;
642 struct hns3_reset_data reset;
645 #define HNS3_FLAG_TC_BASE_SCH_MODE 1
646 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2
648 /* vlan entry information. */
649 struct hns3_user_vlan_table {
650 LIST_ENTRY(hns3_user_vlan_table) next;
655 /* Vlan tag configuration for RX direction */
656 struct hns3_rx_vtag_cfg {
657 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */
658 bool strip_tag1_en; /* Whether strip inner vlan tag */
659 bool strip_tag2_en; /* Whether strip outer vlan tag */
661 * If strip_tag_en is enabled, this bit decide whether to map the vlan
664 bool strip_tag1_discard_en;
665 bool strip_tag2_discard_en;
667 * If this bit is enabled, only map inner/outer priority to descriptor
668 * and the vlan tag is always 0.
670 bool vlan1_vlan_prionly;
671 bool vlan2_vlan_prionly;
674 /* Vlan tag configuration for TX direction */
675 struct hns3_tx_vtag_cfg {
676 bool accept_tag1; /* Whether accept tag1 packet from host */
677 bool accept_untag1; /* Whether accept untag1 packet from host */
680 bool insert_tag1_en; /* Whether insert outer vlan tag */
681 bool insert_tag2_en; /* Whether insert inner vlan tag */
683 * In shift mode, hw will shift the sequence of port based VLAN and
686 bool tag_shift_mode_en; /* hw shift vlan tag automatically */
687 uint16_t default_tag1; /* The default outer vlan tag to insert */
688 uint16_t default_tag2; /* The default inner vlan tag to insert */
691 struct hns3_vtag_cfg {
692 struct hns3_rx_vtag_cfg rx_vcfg;
693 struct hns3_tx_vtag_cfg tx_vcfg;
696 /* Request types for IPC. */
697 enum hns3_mp_req_type {
698 HNS3_MP_REQ_START_RXTX = 1,
699 HNS3_MP_REQ_STOP_RXTX,
703 /* Pameters for IPC. */
704 struct hns3_mp_param {
705 enum hns3_mp_req_type type;
710 /* Request timeout for IPC. */
711 #define HNS3_MP_REQ_TIMEOUT_SEC 5
713 /* Key string for IPC. */
714 #define HNS3_MP_NAME "net_hns3_mp"
716 #define HNS3_L2TBL_NUM 4
717 #define HNS3_L3TBL_NUM 16
718 #define HNS3_L4TBL_NUM 16
719 #define HNS3_OL2TBL_NUM 4
720 #define HNS3_OL3TBL_NUM 16
721 #define HNS3_OL4TBL_NUM 16
722 #define HNS3_PTYPE_NUM 256
724 struct hns3_ptype_table {
726 * The next fields used to calc packet-type by the
727 * L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor.
729 uint32_t l3table[HNS3_L3TBL_NUM];
730 uint32_t l4table[HNS3_L4TBL_NUM];
731 uint32_t inner_l3table[HNS3_L3TBL_NUM];
732 uint32_t inner_l4table[HNS3_L4TBL_NUM];
733 uint32_t ol3table[HNS3_OL3TBL_NUM];
734 uint32_t ol4table[HNS3_OL4TBL_NUM];
737 * The next field used to calc packet-type by the PTYPE from the Rx
738 * descriptor, it functions only when firmware report the capability of
739 * HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it.
741 uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_min_aligned;
744 #define HNS3_FIXED_MAX_TQP_NUM_MODE 0
745 #define HNS3_FLEX_MAX_TQP_NUM_MODE 1
748 struct hns3_adapter *adapter;
750 uint16_t func_num; /* num functions of this pf, include pf and vfs */
754 * tqp_config_mode value range:
755 * HNS3_FIXED_MAX_TQP_NUM_MODE,
756 * HNS3_FLEX_MAX_TQP_NUM_MODE
758 * - HNS3_FIXED_MAX_TQP_NUM_MODE
759 * There is a limitation on the number of pf interrupts available for
760 * on some versions of network engines. In this case, the maximum
761 * queue number of pf can not be greater than the interrupt number,
762 * such as pf of network engine with revision_id 0x21. So the maximum
763 * number of queues must be fixed.
765 * - HNS3_FLEX_MAX_TQP_NUM_MODE
766 * In this mode, the maximum queue number of pf has not any constraint
767 * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF
768 * in the config file. Users can modify the macro according to their
769 * own application scenarios, which is more flexible to use.
771 uint8_t tqp_config_mode;
773 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
774 uint32_t tx_buf_size; /* Tx buffer size for each TC */
775 uint32_t dv_buf_size; /* Dv buffer size for each TC */
777 uint16_t mps; /* Max packet size */
780 uint8_t tc_max; /* max number of tc driver supported */
781 uint8_t local_max_tc; /* max number of local tc */
783 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */
785 bool support_fc_autoneg; /* support FC autonegotiate */
787 uint16_t wanted_umv_size;
788 uint16_t max_umv_size;
789 uint16_t used_umv_size;
791 bool support_sfp_query;
792 uint32_t fec_mode; /* current FEC mode for ethdev */
796 /* Stores timestamp of last received packet on dev */
797 uint64_t rx_timestamp;
799 struct hns3_vtag_cfg vtag_config;
800 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
802 struct hns3_fdir_info fdir; /* flow director info */
803 LIST_HEAD(counters, hns3_flow_counter) flow_counters;
805 struct hns3_tm_conf tm_conf;
809 HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED,
810 HNS3_PF_PUSH_LSC_CAP_SUPPORTED,
811 HNS3_PF_PUSH_LSC_CAP_UNKNOWN
815 struct hns3_adapter *adapter;
817 /* Whether PF support push link status change to VF */
818 uint16_t pf_push_lsc_cap;
821 * If PF support push link status change, VF still need send request to
822 * get link status in some cases (such as reset recover stage), so use
823 * the req_link_info_cnt to control max request count.
825 uint16_t req_link_info_cnt;
827 uint16_t poll_job_started; /* whether poll job is started */
830 struct hns3_adapter {
833 /* Specific for PF or VF */
834 bool is_vf; /* false - PF, true - VF */
840 uint32_t rx_func_hint;
841 uint32_t tx_func_hint;
843 uint64_t dev_caps_mask;
845 struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
849 HNS3_IO_FUNC_HINT_NONE = 0,
850 HNS3_IO_FUNC_HINT_VEC,
851 HNS3_IO_FUNC_HINT_SVE,
852 HNS3_IO_FUNC_HINT_SIMPLE,
853 HNS3_IO_FUNC_HINT_COMMON
856 #define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint"
857 #define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint"
859 #define HNS3_DEVARG_DEV_CAPS_MASK "dev_caps_mask"
861 #define HNS3_DEV_SUPPORT_DCB_B 0x0
862 #define HNS3_DEV_SUPPORT_COPPER_B 0x1
863 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
864 #define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3
865 #define HNS3_DEV_SUPPORT_PTP_B 0x4
866 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5
867 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6
868 #define HNS3_DEV_SUPPORT_STASH_B 0x7
869 #define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9
870 #define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA
871 #define HNS3_DEV_SUPPORT_RAS_IMP_B 0xB
873 #define hns3_dev_dcb_supported(hw) \
874 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
876 /* Support copper media type */
877 #define hns3_dev_copper_supported(hw) \
878 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B)
880 /* Support UDP GSO offload */
881 #define hns3_dev_udp_gso_supported(hw) \
882 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
884 /* Support the queue region action rule of flow directory */
885 #define hns3_dev_fd_queue_region_supported(hw) \
886 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B)
888 /* Support PTP timestamp offload */
889 #define hns3_dev_ptp_supported(hw) \
890 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B)
892 #define hns3_dev_tx_push_supported(hw) \
893 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)
895 /* Support to Independently enable/disable/reset Tx or Rx queues */
896 #define hns3_dev_indep_txrx_supported(hw) \
897 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B)
899 #define hns3_dev_stash_supported(hw) \
900 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B)
902 #define hns3_dev_rxd_adv_layout_supported(hw) \
903 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B)
905 #define hns3_dev_outer_udp_cksum_supported(hw) \
906 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B)
908 #define hns3_dev_ras_imp_supported(hw) \
909 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RAS_IMP_B)
911 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
912 (&((struct hns3_adapter *)adapter)->hw)
913 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \
914 (&((struct hns3_adapter *)adapter)->pf)
915 #define HNS3_DEV_PRIVATE_TO_VF(adapter) \
916 (&((struct hns3_adapter *)adapter)->vf)
917 #define HNS3_DEV_HW_TO_ADAPTER(hw) \
918 container_of(hw, struct hns3_adapter, hw)
920 static inline struct hns3_pf *HNS3_DEV_HW_TO_PF(struct hns3_hw *hw)
922 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw);
926 static inline struct hns3_vf *HNS3_DEV_HW_TO_VF(struct hns3_hw *hw)
928 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw);
932 #define hns3_set_field(origin, mask, shift, val) \
934 (origin) &= (~(mask)); \
935 (origin) |= ((val) << (shift)) & (mask); \
937 #define hns3_get_field(origin, mask, shift) \
938 (((origin) & (mask)) >> (shift))
939 #define hns3_set_bit(origin, shift, val) \
940 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val))
941 #define hns3_get_bit(origin, shift) \
942 hns3_get_field((origin), (0x1UL << (shift)), (shift))
944 #define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask))
947 * upper_32_bits - return bits 32-63 of a number
948 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
949 * the "right shift count >= width of type" warning when that quantity is
952 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
954 /* lower_32_bits - return bits 0-31 of a number */
955 #define lower_32_bits(n) ((uint32_t)(n))
957 #define BIT(nr) (1UL << (nr))
959 #define BIT_ULL(x) (1ULL << (x))
961 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
962 #define GENMASK(h, l) \
963 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
965 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
966 #define rounddown(x, y) ((x) - ((x) % (y)))
968 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
971 * Because hardware always access register in little-endian mode based on hns3
972 * network engine, so driver should also call rte_cpu_to_le_32 to convert data
973 * in little-endian mode before writing register and call rte_le_to_cpu_32 to
974 * convert data after reading from register.
976 * Here the driver encapsulates the data conversion operation in the register
977 * read/write operation function as below:
981 * Therefore, when calling these functions, conversion is not required again.
983 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
985 rte_write32(rte_cpu_to_le_32(value),
986 (volatile void *)((char *)base + reg));
990 * The optimized function for writing registers used in the '.rx_pkt_burst' and
991 * '.tx_pkt_burst' ops implementation function.
993 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value)
996 rte_write32_relaxed(rte_cpu_to_le_32(value), addr);
999 static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
1001 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg));
1002 return rte_le_to_cpu_32(read_val);
1005 #define hns3_write_dev(a, reg, value) \
1006 hns3_write_reg((a)->io_base, (reg), (value))
1008 #define hns3_read_dev(a, reg) \
1009 hns3_read_reg((a)->io_base, (reg))
1011 #define ARRAY_SIZE(x) RTE_DIM(x)
1013 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
1015 act = (actions) + (index); \
1016 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
1018 act = actions + index; \
1022 #define MSEC_PER_SEC 1000L
1023 #define USEC_PER_MSEC 1000L
1025 void hns3_clock_gettime(struct timeval *tv);
1026 uint64_t hns3_clock_calctime_ms(struct timeval *tv);
1027 uint64_t hns3_clock_gettime_ms(void);
1029 static inline uint64_t
1030 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
1034 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;
1039 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)
1041 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);
1045 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)
1047 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);
1050 static inline int64_t
1051 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)
1053 uint64_t mask = (1UL << nr);
1055 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
1058 int hns3_buffer_alloc(struct hns3_hw *hw);
1059 int hns3_dev_flow_ops_get(struct rte_eth_dev *dev,
1060 const struct rte_flow_ops **ops);
1061 bool hns3_is_reset_pending(struct hns3_adapter *hns);
1062 bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
1063 void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query);
1064 void hns3_ether_format_addr(char *buf, uint16_t size,
1065 const struct rte_ether_addr *ether_addr);
1066 int hns3_dev_infos_get(struct rte_eth_dev *eth_dev,
1067 struct rte_eth_dev_info *info);
1068 void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1069 uint32_t link_speed, uint8_t link_duplex);
1070 void hns3_parse_devargs(struct rte_eth_dev *dev);
1071 void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported);
1072 int hns3_restore_ptp(struct hns3_adapter *hns);
1073 int hns3_mbuf_dyn_rx_timestamp_register(struct rte_eth_dev *dev,
1074 struct rte_eth_conf *conf);
1075 int hns3_ptp_init(struct hns3_hw *hw);
1076 int hns3_timesync_enable(struct rte_eth_dev *dev);
1077 int hns3_timesync_disable(struct rte_eth_dev *dev);
1078 int hns3_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
1079 struct timespec *timestamp,
1080 uint32_t flags __rte_unused);
1081 int hns3_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
1082 struct timespec *timestamp);
1083 int hns3_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts);
1084 int hns3_timesync_write_time(struct rte_eth_dev *dev,
1085 const struct timespec *ts);
1086 int hns3_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
1089 is_reset_pending(struct hns3_adapter *hns)
1093 ret = hns3vf_is_reset_pending(hns);
1095 ret = hns3_is_reset_pending(hns);
1099 static inline uint64_t
1100 hns3_txvlan_cap_get(struct hns3_hw *hw)
1102 if (hw->port_base_vlan_cfg.state)
1103 return DEV_TX_OFFLOAD_VLAN_INSERT;
1105 return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT;
1108 #endif /* _HNS3_ETHDEV_H_ */