1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #ifndef _HNS3_ETHDEV_H_
6 #define _HNS3_ETHDEV_H_
14 #include "hns3_fdir.h"
15 #include "hns3_stats.h"
18 #define PCI_VENDOR_ID_HUAWEI 0x19e5
21 #define HNS3_DEV_ID_GE 0xA220
22 #define HNS3_DEV_ID_25GE 0xA221
23 #define HNS3_DEV_ID_25GE_RDMA 0xA222
24 #define HNS3_DEV_ID_50GE_RDMA 0xA224
25 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226
26 #define HNS3_DEV_ID_100G_VF 0xA22E
27 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
29 /* PCI Config offsets */
30 #define HNS3_PCI_REVISION_ID 0x08
31 #define HNS3_PCI_REVISION_ID_LEN 1
33 #define HNS3_PF_FUNC_ID 0
34 #define HNS3_1ST_VF_FUNC_ID 1
36 #define HNS3_UC_MACADDR_NUM 128
37 #define HNS3_VF_UC_MACADDR_NUM 48
38 #define HNS3_MC_MACADDR_NUM 128
40 #define HNS3_MAX_BD_SIZE 65535
41 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8
42 #define HNS3_MAX_TSO_BD_PER_PKT 63
43 #define HNS3_MAX_FRAME_LEN 9728
44 #define HNS3_VLAN_TAG_SIZE 4
45 #define HNS3_DEFAULT_RX_BUF_LEN 2048
46 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
47 #define HNS3_MAX_TSO_HDR_SIZE 512
48 #define HNS3_MAX_TSO_HDR_BD_NUM 3
50 #define HNS3_ETH_OVERHEAD \
51 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
52 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD)
53 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
54 #define HNS3_DEFAULT_MTU 1500UL
55 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
56 #define HNS3_MIN_PKT_SIZE 60
61 #define HNS3_MAX_PF_NUM 8
62 #define HNS3_UMV_TBL_SIZE 3072
63 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \
64 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM)
66 #define HNS3_PF_CFG_BLOCK_SIZE 32
67 #define HNS3_PF_CFG_DESC_NUM \
68 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES)
70 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0
72 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5
73 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500
75 #define HNS3_QUIT_RESET_CNT 10
76 #define HNS3_QUIT_RESET_DELAY_MS 100
78 #define HNS3_POLL_RESPONE_MS 1
80 #define HNS3_MAX_USER_PRIO 8
90 #define HNS3_SCH_MODE_SP 0
91 #define HNS3_SCH_MODE_DWRR 1
94 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */
97 uint8_t tc_dwrr[HNS3_MAX_TC_NUM];
100 struct hns3_tc_info {
102 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */
105 uint8_t up_to_tc_map; /* user priority maping on the TC */
108 struct hns3_dcb_info {
110 uint8_t num_pg; /* It must be 1 if vNET-Base schd */
111 uint8_t pg_dwrr[HNS3_PG_NUM];
112 uint8_t prio_tc[HNS3_MAX_USER_PRIO];
113 struct hns3_pg_info pg_info[HNS3_PG_NUM];
114 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM];
115 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */
116 uint8_t pfc_en; /* Pfc enabled or not for user priority */
119 enum hns3_fc_status {
121 HNS3_FC_STATUS_MAC_PAUSE,
125 struct hns3_tc_queue_info {
126 uint8_t tqp_offset; /* TQP offset from base TQP */
127 uint8_t tqp_count; /* Total TQPs */
128 uint8_t tc; /* TC index */
129 bool enable; /* If this TC is enable or not */
133 uint8_t vmdq_vport_num;
135 uint16_t tqp_desc_num;
137 uint16_t rss_size_max;
140 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
141 uint8_t default_speed;
142 uint32_t numa_node_map;
143 uint8_t speed_ability;
148 enum hns3_media_type {
149 HNS3_MEDIA_TYPE_UNKNOWN,
150 HNS3_MEDIA_TYPE_FIBER,
151 HNS3_MEDIA_TYPE_COPPER,
152 HNS3_MEDIA_TYPE_BACKPLANE,
153 HNS3_MEDIA_TYPE_NONE,
157 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
158 bool default_addr_setted; /* whether default addr(mac_addr) is setted */
161 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
162 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
163 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
164 uint32_t link_speed; /* ETH_SPEED_NUM_ */
167 struct hns3_fake_queue_data {
168 void **rx_queues; /* Array of pointers to fake RX queues. */
169 void **tx_queues; /* Array of pointers to fake TX queues. */
170 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */
171 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
174 /* Primary process maintains driver state in main thread.
177 * | UNINITIALIZED |<-----------+
178 * +---------------+ |
179 * |.eth_dev_init |.eth_dev_uninit
181 * +---------------+------------+
183 * +---------------+<-----------<---------------+
184 * |.dev_configure | |
186 * +---------------+------------+ |
188 * +---------------+----+ |
190 * | | +---------------+
192 * | | +---------------+
194 * V |.dev_configure |
195 * +---------------+----+ |.dev_close
196 * | CONFIGURED |----------------------------+
197 * +---------------+<-----------+
200 * +---------------+ |
201 * | STARTING |------------^
202 * +---------------+ failed |
204 * | +---------------+
206 * | +---------------+
209 * +---------------+------------+
213 enum hns3_adapter_state {
214 HNS3_NIC_UNINITIALIZED = 0,
215 HNS3_NIC_INITIALIZED,
216 HNS3_NIC_CONFIGURING,
227 /* Reset various stages, execute in order */
228 enum hns3_reset_stage {
229 /* Stop query services, stop transceiver, disable MAC */
231 /* Clear reset completion flags, disable send command */
233 /* Inform IMP to start resetting */
234 RESET_STAGE_REQ_HW_RESET,
235 /* Waiting for hardware reset to complete */
237 /* Reinitialize hardware */
238 RESET_STAGE_DEV_INIT,
239 /* Restore user settings and enable MAC */
241 /* Restart query services, start transceiver */
243 /* Not in reset state */
247 enum hns3_reset_level {
249 HNS3_VF_FUNC_RESET, /* A VF function reset */
251 * All VFs under a PF perform function reset.
252 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
253 * of the reset level and the one defined in kernel driver should be
256 HNS3_VF_PF_FUNC_RESET = 2,
258 * All VFs under a PF perform FLR reset.
259 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
260 * of the reset level and the one defined in kernel driver should be
263 HNS3_VF_FULL_RESET = 3,
264 HNS3_FLR_RESET, /* A VF perform FLR reset */
265 /* All VFs under the rootport perform a global or IMP reset */
267 HNS3_FUNC_RESET, /* A PF function reset */
268 /* All PFs under the rootport perform a global reset */
270 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
274 enum hns3_wait_result {
281 #define HNS3_RESET_SYNC_US 100000
283 struct hns3_reset_stats {
284 uint64_t request_cnt; /* Total request reset times */
285 uint64_t global_cnt; /* Total GLOBAL reset times */
286 uint64_t imp_cnt; /* Total IMP reset times */
287 uint64_t exec_cnt; /* Total reset executive times */
288 uint64_t success_cnt; /* Total reset successful times */
289 uint64_t fail_cnt; /* Total reset failed times */
290 uint64_t merge_cnt; /* Total merged in high reset times */
293 typedef bool (*check_completion_func)(struct hns3_hw *hw);
295 struct hns3_wait_data {
300 enum hns3_wait_result result;
301 check_completion_func check_completion;
304 struct hns3_reset_ops {
305 void (*reset_service)(void *arg);
306 int (*stop_service)(struct hns3_adapter *hns);
307 int (*prepare_reset)(struct hns3_adapter *hns);
308 int (*wait_hardware_ready)(struct hns3_adapter *hns);
309 int (*reinit_dev)(struct hns3_adapter *hns);
310 int (*restore_conf)(struct hns3_adapter *hns);
311 int (*start_service)(struct hns3_adapter *hns);
321 struct hns3_reset_data {
322 enum hns3_reset_stage stage;
323 rte_atomic16_t schedule;
324 /* Reset flag, covering the entire reset process */
325 rte_atomic16_t resetting;
326 /* Used to disable sending cmds during reset */
327 rte_atomic16_t disable_cmd;
328 /* The reset level being processed */
329 enum hns3_reset_level level;
330 /* Reset level set, each bit represents a reset level */
332 /* Request reset level set, from interrupt or mailbox */
334 int attempts; /* Reset failure retry */
335 int retries; /* Timeout failure retry in reset_post */
337 * At the time of global or IMP reset, the command cannot be sent to
338 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the
339 * reset process, so the mbuf is required to be released after the reset
340 * is completed.The mbuf_deferred_free is used to mark whether mbuf
341 * needs to be released.
343 bool mbuf_deferred_free;
344 struct timeval start_time;
345 struct hns3_reset_stats stats;
346 const struct hns3_reset_ops *ops;
347 struct hns3_wait_data *wait_data;
351 struct rte_eth_dev_data *data;
353 uint8_t revision; /* PCI revision, low byte of class word */
355 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
356 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */
357 pthread_t irq_thread_id;
359 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
360 struct hns3_tqp_stats tqp_stats;
361 /* Include Mac stats | Rx stats | Tx stats */
362 struct hns3_mac_stats mac_stats;
366 uint16_t total_tqps_num; /* total task queue pairs of this PF */
367 uint16_t tqps_num; /* num task queue pairs of this function */
368 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
369 uint16_t rss_size_max; /* HW defined max RSS task queue */
371 uint16_t num_tx_desc; /* desc num of per tx queue */
372 uint16_t num_rx_desc; /* desc num of per rx queue */
374 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
375 int mc_addrs_num; /* Multicast mac addresses number */
377 /* The configuration info of RSS */
378 struct hns3_rss_conf rss_info;
379 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
381 uint8_t num_tc; /* Total number of enabled TCs */
383 enum hns3_fc_mode current_mode;
384 enum hns3_fc_mode requested_mode;
385 struct hns3_dcb_info dcb_info;
386 enum hns3_fc_status current_fc_status; /* current flow control status */
387 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
388 uint16_t used_rx_queues;
389 uint16_t used_tx_queues;
391 /* Config max queue numbers between rx and tx queues from user */
392 uint16_t cfg_max_queues;
393 struct hns3_fake_queue_data fkq_data; /* fake queue data */
394 uint16_t alloc_rss_size; /* RX queue number per TC */
395 uint16_t tx_qnum_per_tc; /* TX queue number per TC */
399 * PMD setup and configuration is not thread safe. Since it is not
400 * performance sensitive, it is better to guarantee thread-safety
401 * and add device level lock. Adapter control operations which
402 * change its state should acquire the lock.
405 enum hns3_adapter_state adapter_state;
406 struct hns3_reset_data reset;
409 #define HNS3_FLAG_TC_BASE_SCH_MODE 1
410 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2
412 struct hns3_err_msix_intr_stats {
413 uint64_t mac_afifo_tnl_intr_cnt;
414 uint64_t ppu_mpf_abnormal_intr_st2_cnt;
415 uint64_t ssu_port_based_pf_intr_cnt;
416 uint64_t ppp_pf_abnormal_intr_cnt;
417 uint64_t ppu_pf_abnormal_intr_cnt;
420 /* vlan entry information. */
421 struct hns3_user_vlan_table {
422 LIST_ENTRY(hns3_user_vlan_table) next;
427 struct hns3_port_base_vlan_config {
432 /* Vlan tag configuration for RX direction */
433 struct hns3_rx_vtag_cfg {
434 uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */
435 uint8_t strip_tag1_en; /* Whether strip inner vlan tag */
436 uint8_t strip_tag2_en; /* Whether strip outer vlan tag */
437 uint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */
438 uint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */
441 /* Vlan tag configuration for TX direction */
442 struct hns3_tx_vtag_cfg {
443 bool accept_tag1; /* Whether accept tag1 packet from host */
444 bool accept_untag1; /* Whether accept untag1 packet from host */
447 bool insert_tag1_en; /* Whether insert inner vlan tag */
448 bool insert_tag2_en; /* Whether insert outer vlan tag */
449 uint16_t default_tag1; /* The default inner vlan tag to insert */
450 uint16_t default_tag2; /* The default outer vlan tag to insert */
453 struct hns3_vtag_cfg {
454 struct hns3_rx_vtag_cfg rx_vcfg;
455 struct hns3_tx_vtag_cfg tx_vcfg;
458 /* Request types for IPC. */
459 enum hns3_mp_req_type {
460 HNS3_MP_REQ_START_RXTX = 1,
461 HNS3_MP_REQ_STOP_RXTX,
465 /* Pameters for IPC. */
466 struct hns3_mp_param {
467 enum hns3_mp_req_type type;
472 /* Request timeout for IPC. */
473 #define HNS3_MP_REQ_TIMEOUT_SEC 5
475 /* Key string for IPC. */
476 #define HNS3_MP_NAME "net_hns3_mp"
479 struct hns3_adapter *adapter;
481 uint16_t func_num; /* num functions of this pf, include pf and vfs */
483 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
484 uint32_t tx_buf_size; /* Tx buffer size for each TC */
485 uint32_t dv_buf_size; /* Dv buffer size for each TC */
487 uint16_t mps; /* Max packet size */
490 uint8_t tc_max; /* max number of tc driver supported */
491 uint8_t local_max_tc; /* max number of local tc */
493 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */
495 bool support_fc_autoneg; /* support FC autonegotiate */
497 uint16_t wanted_umv_size;
498 uint16_t max_umv_size;
499 uint16_t used_umv_size;
501 /* Statistics information for abnormal interrupt */
502 struct hns3_err_msix_intr_stats abn_int_stats;
504 bool support_sfp_query;
506 struct hns3_vtag_cfg vtag_config;
507 struct hns3_port_base_vlan_config port_base_vlan_cfg;
508 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
510 struct hns3_fdir_info fdir; /* flow director info */
511 LIST_HEAD(counters, hns3_flow_counter) flow_counters;
515 struct hns3_adapter *adapter;
518 struct hns3_adapter {
521 /* Specific for PF or VF */
522 bool is_vf; /* false - PF, true - VF */
529 #define HNS3_DEV_SUPPORT_DCB_B 0x0
531 #define hns3_dev_dcb_supported(hw) \
532 hns3_get_bit((hw)->flag, HNS3_DEV_SUPPORT_DCB_B)
534 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
535 (&((struct hns3_adapter *)adapter)->hw)
536 #define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \
537 ((struct hns3_adapter *)adapter)
538 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \
539 (&((struct hns3_adapter *)adapter)->pf)
540 #define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \
541 (&((struct hns3_adapter *)adapter)->vf)
542 #define HNS3_DEV_HW_TO_ADAPTER(hw) \
543 container_of(hw, struct hns3_adapter, hw)
545 #define hns3_set_field(origin, mask, shift, val) \
547 (origin) &= (~(mask)); \
548 (origin) |= ((val) << (shift)) & (mask); \
550 #define hns3_get_field(origin, mask, shift) \
551 (((origin) & (mask)) >> (shift))
552 #define hns3_set_bit(origin, shift, val) \
553 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val))
554 #define hns3_get_bit(origin, shift) \
555 hns3_get_field((origin), (0x1UL << (shift)), (shift))
558 * upper_32_bits - return bits 32-63 of a number
559 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
560 * the "right shift count >= width of type" warning when that quantity is
563 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
565 /* lower_32_bits - return bits 0-31 of a number */
566 #define lower_32_bits(n) ((uint32_t)(n))
568 #define BIT(nr) (1UL << (nr))
570 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
571 #define GENMASK(h, l) \
572 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
574 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
575 #define rounddown(x, y) ((x) - ((x) % (y)))
577 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
579 #define max_t(type, x, y) ({ \
582 __max1 > __max2 ? __max1 : __max2; })
584 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
586 rte_write32(value, (volatile void *)((char *)base + reg));
589 static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
591 return rte_read32((volatile void *)((char *)base + reg));
594 #define hns3_write_dev(a, reg, value) \
595 hns3_write_reg((a)->io_base, (reg), (value))
597 #define hns3_read_dev(a, reg) \
598 hns3_read_reg((a)->io_base, (reg))
600 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
602 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
604 act = (actions) + (index); \
605 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
607 act = actions + index; \
611 #define MSEC_PER_SEC 1000L
612 #define USEC_PER_MSEC 1000L
614 static inline uint64_t
615 get_timeofday_ms(void)
619 (void)gettimeofday(&tv, NULL);
621 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
624 static inline uint64_t
625 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
629 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;
634 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)
636 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);
640 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)
642 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);
645 static inline int64_t
646 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)
648 uint64_t mask = (1UL << nr);
650 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
653 int hns3_buffer_alloc(struct hns3_hw *hw);
654 int hns3_config_gro(struct hns3_hw *hw, bool en);
655 int hns3_dev_filter_ctrl(struct rte_eth_dev *dev,
656 enum rte_filter_type filter_type,
657 enum rte_filter_op filter_op, void *arg);
658 bool hns3_is_reset_pending(struct hns3_adapter *hns);
659 bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
660 void hns3_update_link_status(struct hns3_hw *hw);
663 is_reset_pending(struct hns3_adapter *hns)
667 ret = hns3vf_is_reset_pending(hns);
669 ret = hns3_is_reset_pending(hns);
673 #endif /* _HNS3_ETHDEV_H_ */