1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
5 #ifndef _HNS3_ETHDEV_H_
6 #define _HNS3_ETHDEV_H_
10 #include <ethdev_driver.h>
11 #include <rte_byteorder.h>
13 #include <rte_spinlock.h>
18 #include "hns3_fdir.h"
19 #include "hns3_stats.h"
23 #define PCI_VENDOR_ID_HUAWEI 0x19e5
26 #define HNS3_DEV_ID_GE 0xA220
27 #define HNS3_DEV_ID_25GE 0xA221
28 #define HNS3_DEV_ID_25GE_RDMA 0xA222
29 #define HNS3_DEV_ID_50GE_RDMA 0xA224
30 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226
31 #define HNS3_DEV_ID_200G_RDMA 0xA228
32 #define HNS3_DEV_ID_100G_VF 0xA22E
33 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
35 /* PCI Config offsets */
36 #define HNS3_PCI_REVISION_ID 0x08
37 #define HNS3_PCI_REVISION_ID_LEN 1
39 #define PCI_REVISION_ID_HIP08_B 0x21
40 #define PCI_REVISION_ID_HIP09_A 0x30
42 #define HNS3_PF_FUNC_ID 0
43 #define HNS3_1ST_VF_FUNC_ID 1
45 #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0
46 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1
48 #define HNS3_UNLIMIT_PROMISC_MODE 0
49 #define HNS3_LIMIT_PROMISC_MODE 1
51 #define HNS3_SPECIAL_PORT_SW_CKSUM_MODE 0
52 #define HNS3_SPECIAL_PORT_HW_CKSUM_MODE 1
54 #define HNS3_UC_MACADDR_NUM 128
55 #define HNS3_VF_UC_MACADDR_NUM 48
56 #define HNS3_MC_MACADDR_NUM 128
58 #define HNS3_MAX_BD_SIZE 65535
59 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8
60 #define HNS3_MAX_TSO_BD_PER_PKT 63
61 #define HNS3_MAX_FRAME_LEN 9728
62 #define HNS3_VLAN_TAG_SIZE 4
63 #define HNS3_DEFAULT_RX_BUF_LEN 2048
64 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
65 #define HNS3_MAX_TSO_HDR_SIZE 512
66 #define HNS3_MAX_TSO_HDR_BD_NUM 3
67 #define HNS3_MAX_LRO_SIZE 64512
69 #define HNS3_ETH_OVERHEAD \
70 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
71 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD)
72 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
73 #define HNS3_DEFAULT_MTU 1500UL
74 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
75 #define HNS3_HIP08_MIN_TX_PKT_LEN 33
76 #define HNS3_HIP09_MIN_TX_PKT_LEN 9
78 #define HNS3_BITS_PER_BYTE 8
83 #define HNS3_MAX_PF_NUM 8
84 #define HNS3_UMV_TBL_SIZE 3072
85 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \
86 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM)
88 #define HNS3_PF_CFG_BLOCK_SIZE 32
89 #define HNS3_PF_CFG_DESC_NUM \
90 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES)
92 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0
94 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5
95 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500
97 #define HNS3_QUIT_RESET_CNT 10
98 #define HNS3_QUIT_RESET_DELAY_MS 100
100 #define HNS3_POLL_RESPONE_MS 1
102 #define HNS3_MAX_USER_PRIO 8
103 #define HNS3_PG_NUM 4
112 #define HNS3_SCH_MODE_SP 0
113 #define HNS3_SCH_MODE_DWRR 1
114 struct hns3_pg_info {
116 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */
119 uint8_t tc_dwrr[HNS3_MAX_TC_NUM];
122 struct hns3_tc_info {
124 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */
127 uint8_t up_to_tc_map; /* user priority maping on the TC */
130 struct hns3_dcb_info {
132 uint8_t num_pg; /* It must be 1 if vNET-Base schd */
133 uint8_t pg_dwrr[HNS3_PG_NUM];
134 uint8_t prio_tc[HNS3_MAX_USER_PRIO];
135 struct hns3_pg_info pg_info[HNS3_PG_NUM];
136 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM];
137 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */
138 uint8_t pfc_en; /* Pfc enabled or not for user priority */
141 enum hns3_fc_status {
143 HNS3_FC_STATUS_MAC_PAUSE,
147 struct hns3_tc_queue_info {
148 uint16_t tqp_offset; /* TQP offset from base TQP */
149 uint16_t tqp_count; /* Total TQPs */
150 uint8_t tc; /* TC index */
151 bool enable; /* If this TC is enable or not */
155 uint8_t vmdq_vport_num;
157 uint16_t tqp_desc_num;
159 uint16_t rss_size_max;
162 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
163 uint8_t default_speed;
164 uint32_t numa_node_map;
165 uint8_t speed_ability;
169 struct hns3_set_link_speed_cfg {
176 enum hns3_media_type {
177 HNS3_MEDIA_TYPE_UNKNOWN,
178 HNS3_MEDIA_TYPE_FIBER,
179 HNS3_MEDIA_TYPE_COPPER,
180 HNS3_MEDIA_TYPE_BACKPLANE,
181 HNS3_MEDIA_TYPE_NONE,
184 #define HNS3_DEFAULT_QUERY 0
185 #define HNS3_ACTIVE_QUERY 1
188 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
189 bool default_addr_setted; /* whether default addr(mac_addr) is set */
192 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
193 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
194 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
195 uint32_t link_speed; /* ETH_SPEED_NUM_ */
197 * Some firmware versions support only the SFP speed query. In addition
198 * to the SFP speed query, some firmware supports the query of the speed
199 * capability, auto-negotiation capability, and FEC mode, which can be
200 * selected by the 'query_type' filed in the HNS3_OPC_GET_SFP_INFO CMD.
201 * This field is used to record the SFP information query mode.
203 * HNS3_DEFAULT_QUERY/HNS3_ACTIVE_QUERY
205 * - HNS3_DEFAULT_QUERY
206 * Speed obtained is from SFP. When the queried speed changes, the MAC
207 * speed needs to be reconfigured.
209 * - HNS3_ACTIVE_QUERY
210 * Speed obtained is from MAC. At this time, it is unnecessary for
211 * driver to reconfigured the MAC speed. In addition, more information,
212 * such as, the speed capability, auto-negotiation capability and FEC
213 * mode, can be obtained by the HNS3_OPC_GET_SFP_INFO CMD.
216 uint32_t supported_speed; /* supported speed for current media type */
217 uint32_t advertising; /* advertised capability in the local part */
218 uint32_t lp_advertising; /* advertised capability in the link partner */
219 uint8_t support_autoneg;
222 struct hns3_fake_queue_data {
223 void **rx_queues; /* Array of pointers to fake RX queues. */
224 void **tx_queues; /* Array of pointers to fake TX queues. */
225 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */
226 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
229 #define HNS3_PORT_BASE_VLAN_DISABLE 0
230 #define HNS3_PORT_BASE_VLAN_ENABLE 1
231 struct hns3_port_base_vlan_config {
236 /* Primary process maintains driver state in main thread.
239 * | UNINITIALIZED |<-----------+
240 * +---------------+ |
241 * |.eth_dev_init |.eth_dev_uninit
243 * +---------------+------------+
245 * +---------------+<-----------<---------------+
246 * |.dev_configure | |
248 * +---------------+------------+ |
250 * +---------------+----+ |
252 * | | +---------------+
254 * | | +---------------+
256 * V |.dev_configure |
257 * +---------------+----+ |.dev_close
258 * | CONFIGURED |----------------------------+
259 * +---------------+<-----------+
262 * +---------------+ |
263 * | STARTING |------------^
264 * +---------------+ failed |
266 * | +---------------+
268 * | +---------------+
271 * +---------------+------------+
275 enum hns3_adapter_state {
276 HNS3_NIC_UNINITIALIZED = 0,
277 HNS3_NIC_INITIALIZED,
278 HNS3_NIC_CONFIGURING,
289 /* Reset various stages, execute in order */
290 enum hns3_reset_stage {
291 /* Stop query services, stop transceiver, disable MAC */
293 /* Clear reset completion flags, disable send command */
295 /* Inform IMP to start resetting */
296 RESET_STAGE_REQ_HW_RESET,
297 /* Waiting for hardware reset to complete */
299 /* Reinitialize hardware */
300 RESET_STAGE_DEV_INIT,
301 /* Restore user settings and enable MAC */
303 /* Restart query services, start transceiver */
305 /* Not in reset state */
309 enum hns3_reset_level {
310 HNS3_FLR_RESET, /* A VF perform FLR reset */
311 HNS3_VF_FUNC_RESET, /* A VF function reset */
314 * All VFs under a PF perform function reset.
315 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
316 * of the reset level and the one defined in kernel driver should be
319 HNS3_VF_PF_FUNC_RESET = 2,
322 * All VFs under a PF perform FLR reset.
323 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
324 * of the reset level and the one defined in kernel driver should be
327 * According to the protocol of PCIe, FLR to a PF resets the PF state as
328 * well as the SR-IOV extended capability including VF Enable which
329 * means that VFs no longer exist.
331 * In PF FLR, the register state of VF is not reliable, VF's driver
332 * should not access the registers of the VF device.
336 /* All VFs under the rootport perform a global or IMP reset */
340 * The enumeration value of HNS3_FUNC_RESET/HNS3_GLOBAL_RESET/
341 * HNS3_IMP_RESET/HNS3_NONE_RESET are also used by firmware, and
342 * can not be changed.
345 HNS3_FUNC_RESET = 5, /* A PF function reset */
347 /* All PFs under the rootport perform a global reset */
349 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
354 enum hns3_wait_result {
361 #define HNS3_RESET_SYNC_US 100000
363 struct hns3_reset_stats {
364 uint64_t request_cnt; /* Total request reset times */
365 uint64_t global_cnt; /* Total GLOBAL reset times */
366 uint64_t imp_cnt; /* Total IMP reset times */
367 uint64_t exec_cnt; /* Total reset executive times */
368 uint64_t success_cnt; /* Total reset successful times */
369 uint64_t fail_cnt; /* Total reset failed times */
370 uint64_t merge_cnt; /* Total merged in high reset times */
373 typedef bool (*check_completion_func)(struct hns3_hw *hw);
375 struct hns3_wait_data {
380 enum hns3_wait_result result;
381 check_completion_func check_completion;
384 struct hns3_reset_ops {
385 void (*reset_service)(void *arg);
386 int (*stop_service)(struct hns3_adapter *hns);
387 int (*prepare_reset)(struct hns3_adapter *hns);
388 int (*wait_hardware_ready)(struct hns3_adapter *hns);
389 int (*reinit_dev)(struct hns3_adapter *hns);
390 int (*restore_conf)(struct hns3_adapter *hns);
391 int (*start_service)(struct hns3_adapter *hns);
401 struct hns3_reset_data {
402 enum hns3_reset_stage stage;
404 /* Reset flag, covering the entire reset process */
406 /* Used to disable sending cmds during reset */
407 uint16_t disable_cmd;
408 /* The reset level being processed */
409 enum hns3_reset_level level;
410 /* Reset level set, each bit represents a reset level */
412 /* Request reset level set, from interrupt or mailbox */
414 int attempts; /* Reset failure retry */
415 int retries; /* Timeout failure retry in reset_post */
417 * At the time of global or IMP reset, the command cannot be sent to
418 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the
419 * reset process, so the mbuf is required to be released after the reset
420 * is completed.The mbuf_deferred_free is used to mark whether mbuf
421 * needs to be released.
423 bool mbuf_deferred_free;
424 struct timeval start_time;
425 struct hns3_reset_stats stats;
426 const struct hns3_reset_ops *ops;
427 struct hns3_wait_data *wait_data;
430 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0
431 #define HNS3_INTR_MAPPING_VEC_ALL 1
433 #define HNS3_INTR_COALESCE_GL_UINT_2US 0
434 #define HNS3_INTR_COALESCE_GL_UINT_1US 1
436 #define HNS3_INTR_QL_NONE 0
438 struct hns3_queue_intr {
440 * interrupt mapping mode.
442 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL
444 * - HNS3_INTR_MAPPING_VEC_RSV_ONE
445 * For some versions of hardware network engine, because of the
446 * hardware constraint, we need implement clearing the mapping
447 * relationship configurations by binding all queues to the last
448 * interrupt vector and reserving the last interrupt vector. This
449 * method results in a decrease of the maximum queues when upper
450 * applications call the rte_eth_dev_configure API function to
451 * enable Rx interrupt.
453 * - HNS3_INTR_MAPPING_VEC_ALL
454 * PMD driver can map/unmmap all interrupt vectors with queues When
455 * Rx interrupt in enabled.
457 uint8_t mapping_mode;
459 * The unit of GL(gap limiter) configuration for interrupt coalesce of
462 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US
465 /* The max QL(quantity limiter) value */
469 #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0
470 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1
472 #define HNS3_PKTS_DROP_STATS_MODE1 0
473 #define HNS3_PKTS_DROP_STATS_MODE2 1
476 struct rte_eth_dev_data *data;
478 uint8_t revision; /* PCI revision, low byte of class word */
480 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
482 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
483 struct hns3_tqp_stats tqp_stats;
484 /* Include Mac stats | Rx stats | Tx stats */
485 struct hns3_mac_stats mac_stats;
486 struct hns3_rx_missed_stats imissed_stats;
487 uint64_t oerror_stats;
491 uint16_t total_tqps_num; /* total task queue pairs of this PF */
492 uint16_t tqps_num; /* num task queue pairs of this function */
493 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
494 uint16_t rss_size_max; /* HW defined max RSS task queue */
495 uint16_t rx_buf_len; /* hold min hardware rx buf len */
496 uint16_t num_tx_desc; /* desc num of per tx queue */
497 uint16_t num_rx_desc; /* desc num of per rx queue */
498 uint32_t mng_entry_num; /* number of manager table entry */
499 uint32_t mac_entry_num; /* number of mac-vlan table entry */
501 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
502 int mc_addrs_num; /* Multicast mac addresses number */
504 /* The configuration info of RSS */
505 struct hns3_rss_conf rss_info;
506 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
507 uint16_t rss_ind_tbl_size;
508 uint16_t rss_key_size;
510 uint8_t num_tc; /* Total number of enabled TCs */
512 enum hns3_fc_mode requested_fc_mode; /* FC mode requested by user */
513 struct hns3_dcb_info dcb_info;
514 enum hns3_fc_status current_fc_status; /* current flow control status */
515 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
516 uint16_t used_rx_queues;
517 uint16_t used_tx_queues;
519 /* Config max queue numbers between rx and tx queues from user */
520 uint16_t cfg_max_queues;
521 struct hns3_fake_queue_data fkq_data; /* fake queue data */
522 uint16_t alloc_rss_size; /* RX queue number per TC */
523 uint16_t tx_qnum_per_tc; /* TX queue number per TC */
526 uint32_t max_tm_rate;
528 * The minimum length of the packet supported by hardware in the Tx
531 uint32_t min_tx_pkt_len;
533 struct hns3_queue_intr intr;
537 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
539 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM
540 * In this mode, because of the hardware constraint, network driver
541 * software need erase the L4 len value of the TCP pseudo header
542 * and recalculate the TCP pseudo header checksum of packets that
545 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
546 * In this mode, hardware support recalculate the TCP pseudo header
547 * checksum of packets that need TSO, so network driver software
548 * not need to recalculate it.
554 * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE
556 * - HNS3_SW_SHIFT_AND_DISCARD_MODE
557 * For some versions of hardware network engine, because of the
558 * hardware limitation, PMD driver needs to detect the PVID status
559 * to work with haredware to implement PVID-related functions.
560 * For example, driver need discard the stripped PVID tag to ensure
561 * the PVID will not report to mbuf and shift the inserted VLAN tag
562 * to avoid port based VLAN covering it.
564 * - HNS3_HW_SHIT_AND_DISCARD_MODE
565 * PMD driver does not need to process PVID-related functions in
566 * I/O process, Hardware will adjust the sequence between port based
567 * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by
568 * PVID will be invisible to driver. And in this mode, hns3 is able
569 * to send a multi-layer VLAN packets when hw VLAN insert offload
576 * HNS3_UNLIMIT_PROMISC_MODE/HNS3_LIMIT_PROMISC_MODE
578 * - HNS3_UNLIMIT_PROMISC_MODE
579 * In this mode, TX unicast promisc will be configured when promisc
580 * is set, driver can receive all the ingress and outgoing traffic.
581 * In the words, all the ingress packets, all the packets sent from
582 * the PF and other VFs on the same physical port.
584 * - HNS3_LIMIT_PROMISC_MODE
585 * In this mode, TX unicast promisc is shutdown when promisc mode
586 * is set. So, driver will only receive all the ingress traffic.
587 * The packets sent from the PF and other VFs on the same physical
588 * port won't be copied to the function which has set promisc mode.
590 uint8_t promisc_mode;
593 * drop_stats_mode mode.
595 * HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2
597 * - HNS3_PKTS_DROP_STATS_MODE1
598 * This mode for kunpeng920. In this mode, port level imissed stats
599 * is supported. It only includes RPU drop stats.
601 * - HNS3_PKTS_DROP_STATS_MODE2
602 * This mode for kunpeng930. In this mode, imissed stats and oerrors
603 * stats is supported. Function level imissed stats is supported. It
604 * includes RPU drop stats in VF, and includes both RPU drop stats
605 * and SSU drop stats in PF. Oerror stats is also supported in PF.
607 uint8_t drop_stats_mode;
609 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
613 * HNS3_SPECIAL_PORT_HW_CKSUM_MODE/HNS3_SPECIAL_PORT_SW_CKSUM_MODE
615 * - HNS3_SPECIAL_PORT_SW_CKSUM_MODE
616 * In this mode, HW can not do checksum for special UDP port like
617 * 4789, 4790, 6081 for non-tunnel UDP packets and UDP tunnel
618 * packets without the PKT_TX_TUNEL_MASK in the mbuf. So, PMD need
619 * do the checksum for these packets to avoid a checksum error.
621 * - HNS3_SPECIAL_PORT_HW_CKSUM_MODE
622 * In this mode, HW does not have the preceding problems and can
623 * directly calculate the checksum of these UDP packets.
625 uint8_t udp_cksum_mode;
627 struct hns3_port_base_vlan_config port_base_vlan_cfg;
629 pthread_mutex_t flows_lock; /* rte_flow ops lock */
632 * PMD setup and configuration is not thread safe. Since it is not
633 * performance sensitive, it is better to guarantee thread-safety
634 * and add device level lock. Adapter control operations which
635 * change its state should acquire the lock.
638 enum hns3_adapter_state adapter_state;
639 struct hns3_reset_data reset;
642 #define HNS3_FLAG_TC_BASE_SCH_MODE 1
643 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2
645 /* vlan entry information. */
646 struct hns3_user_vlan_table {
647 LIST_ENTRY(hns3_user_vlan_table) next;
652 /* Vlan tag configuration for RX direction */
653 struct hns3_rx_vtag_cfg {
654 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */
655 bool strip_tag1_en; /* Whether strip inner vlan tag */
656 bool strip_tag2_en; /* Whether strip outer vlan tag */
658 * If strip_tag_en is enabled, this bit decide whether to map the vlan
661 bool strip_tag1_discard_en;
662 bool strip_tag2_discard_en;
664 * If this bit is enabled, only map inner/outer priority to descriptor
665 * and the vlan tag is always 0.
667 bool vlan1_vlan_prionly;
668 bool vlan2_vlan_prionly;
671 /* Vlan tag configuration for TX direction */
672 struct hns3_tx_vtag_cfg {
673 bool accept_tag1; /* Whether accept tag1 packet from host */
674 bool accept_untag1; /* Whether accept untag1 packet from host */
677 bool insert_tag1_en; /* Whether insert outer vlan tag */
678 bool insert_tag2_en; /* Whether insert inner vlan tag */
680 * In shift mode, hw will shift the sequence of port based VLAN and
683 bool tag_shift_mode_en; /* hw shift vlan tag automatically */
684 uint16_t default_tag1; /* The default outer vlan tag to insert */
685 uint16_t default_tag2; /* The default inner vlan tag to insert */
688 struct hns3_vtag_cfg {
689 struct hns3_rx_vtag_cfg rx_vcfg;
690 struct hns3_tx_vtag_cfg tx_vcfg;
693 /* Request types for IPC. */
694 enum hns3_mp_req_type {
695 HNS3_MP_REQ_START_RXTX = 1,
696 HNS3_MP_REQ_STOP_RXTX,
700 /* Pameters for IPC. */
701 struct hns3_mp_param {
702 enum hns3_mp_req_type type;
707 /* Request timeout for IPC. */
708 #define HNS3_MP_REQ_TIMEOUT_SEC 5
710 /* Key string for IPC. */
711 #define HNS3_MP_NAME "net_hns3_mp"
713 #define HNS3_L2TBL_NUM 4
714 #define HNS3_L3TBL_NUM 16
715 #define HNS3_L4TBL_NUM 16
716 #define HNS3_OL2TBL_NUM 4
717 #define HNS3_OL3TBL_NUM 16
718 #define HNS3_OL4TBL_NUM 16
719 #define HNS3_PTYPE_NUM 256
721 struct hns3_ptype_table {
723 * The next fields used to calc packet-type by the
724 * L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor.
726 uint32_t l3table[HNS3_L3TBL_NUM];
727 uint32_t l4table[HNS3_L4TBL_NUM];
728 uint32_t inner_l3table[HNS3_L3TBL_NUM];
729 uint32_t inner_l4table[HNS3_L4TBL_NUM];
730 uint32_t ol3table[HNS3_OL3TBL_NUM];
731 uint32_t ol4table[HNS3_OL4TBL_NUM];
734 * The next field used to calc packet-type by the PTYPE from the Rx
735 * descriptor, it functions only when firmware report the capability of
736 * HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it.
738 uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_min_aligned;
741 #define HNS3_FIXED_MAX_TQP_NUM_MODE 0
742 #define HNS3_FLEX_MAX_TQP_NUM_MODE 1
745 struct hns3_adapter *adapter;
747 uint16_t func_num; /* num functions of this pf, include pf and vfs */
751 * tqp_config_mode value range:
752 * HNS3_FIXED_MAX_TQP_NUM_MODE,
753 * HNS3_FLEX_MAX_TQP_NUM_MODE
755 * - HNS3_FIXED_MAX_TQP_NUM_MODE
756 * There is a limitation on the number of pf interrupts available for
757 * on some versions of network engines. In this case, the maximum
758 * queue number of pf can not be greater than the interrupt number,
759 * such as pf of network engine with revision_id 0x21. So the maximum
760 * number of queues must be fixed.
762 * - HNS3_FLEX_MAX_TQP_NUM_MODE
763 * In this mode, the maximum queue number of pf has not any constraint
764 * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF
765 * in the config file. Users can modify the macro according to their
766 * own application scenarios, which is more flexible to use.
768 uint8_t tqp_config_mode;
770 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
771 uint32_t tx_buf_size; /* Tx buffer size for each TC */
772 uint32_t dv_buf_size; /* Dv buffer size for each TC */
774 uint16_t mps; /* Max packet size */
777 uint8_t tc_max; /* max number of tc driver supported */
778 uint8_t local_max_tc; /* max number of local tc */
780 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */
782 bool support_fc_autoneg; /* support FC autonegotiate */
784 uint16_t wanted_umv_size;
785 uint16_t max_umv_size;
786 uint16_t used_umv_size;
788 bool support_sfp_query;
789 uint32_t fec_mode; /* current FEC mode for ethdev */
793 /* Stores timestamp of last received packet on dev */
794 uint64_t rx_timestamp;
796 struct hns3_vtag_cfg vtag_config;
797 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
799 struct hns3_fdir_info fdir; /* flow director info */
800 LIST_HEAD(counters, hns3_flow_counter) flow_counters;
802 struct hns3_tm_conf tm_conf;
806 HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED,
807 HNS3_PF_PUSH_LSC_CAP_SUPPORTED,
808 HNS3_PF_PUSH_LSC_CAP_UNKNOWN
812 struct hns3_adapter *adapter;
814 /* Whether PF support push link status change to VF */
815 uint16_t pf_push_lsc_cap;
818 * If PF support push link status change, VF still need send request to
819 * get link status in some cases (such as reset recover stage), so use
820 * the req_link_info_cnt to control max request count.
822 uint16_t req_link_info_cnt;
824 uint16_t poll_job_started; /* whether poll job is started */
827 struct hns3_adapter {
830 /* Specific for PF or VF */
831 bool is_vf; /* false - PF, true - VF */
837 uint32_t rx_func_hint;
838 uint32_t tx_func_hint;
840 uint64_t dev_caps_mask;
842 struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
846 HNS3_IO_FUNC_HINT_NONE = 0,
847 HNS3_IO_FUNC_HINT_VEC,
848 HNS3_IO_FUNC_HINT_SVE,
849 HNS3_IO_FUNC_HINT_SIMPLE,
850 HNS3_IO_FUNC_HINT_COMMON
853 #define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint"
854 #define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint"
856 #define HNS3_DEVARG_DEV_CAPS_MASK "dev_caps_mask"
858 #define HNS3_DEV_SUPPORT_DCB_B 0x0
859 #define HNS3_DEV_SUPPORT_COPPER_B 0x1
860 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
861 #define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3
862 #define HNS3_DEV_SUPPORT_PTP_B 0x4
863 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5
864 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6
865 #define HNS3_DEV_SUPPORT_STASH_B 0x7
866 #define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9
867 #define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA
868 #define HNS3_DEV_SUPPORT_RAS_IMP_B 0xB
870 #define hns3_dev_dcb_supported(hw) \
871 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
873 /* Support copper media type */
874 #define hns3_dev_copper_supported(hw) \
875 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B)
877 /* Support UDP GSO offload */
878 #define hns3_dev_udp_gso_supported(hw) \
879 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
881 /* Support the queue region action rule of flow directory */
882 #define hns3_dev_fd_queue_region_supported(hw) \
883 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B)
885 /* Support PTP timestamp offload */
886 #define hns3_dev_ptp_supported(hw) \
887 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B)
889 #define hns3_dev_tx_push_supported(hw) \
890 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)
892 /* Support to Independently enable/disable/reset Tx or Rx queues */
893 #define hns3_dev_indep_txrx_supported(hw) \
894 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B)
896 #define hns3_dev_stash_supported(hw) \
897 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B)
899 #define hns3_dev_rxd_adv_layout_supported(hw) \
900 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B)
902 #define hns3_dev_outer_udp_cksum_supported(hw) \
903 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B)
905 #define hns3_dev_ras_imp_supported(hw) \
906 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RAS_IMP_B)
908 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
909 (&((struct hns3_adapter *)adapter)->hw)
910 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \
911 (&((struct hns3_adapter *)adapter)->pf)
912 #define HNS3_DEV_PRIVATE_TO_VF(adapter) \
913 (&((struct hns3_adapter *)adapter)->vf)
914 #define HNS3_DEV_HW_TO_ADAPTER(hw) \
915 container_of(hw, struct hns3_adapter, hw)
917 static inline struct hns3_pf *HNS3_DEV_HW_TO_PF(struct hns3_hw *hw)
919 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw);
923 static inline struct hns3_vf *HNS3_DEV_HW_TO_VF(struct hns3_hw *hw)
925 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw);
929 #define hns3_set_field(origin, mask, shift, val) \
931 (origin) &= (~(mask)); \
932 (origin) |= ((val) << (shift)) & (mask); \
934 #define hns3_get_field(origin, mask, shift) \
935 (((origin) & (mask)) >> (shift))
936 #define hns3_set_bit(origin, shift, val) \
937 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val))
938 #define hns3_get_bit(origin, shift) \
939 hns3_get_field((origin), (0x1UL << (shift)), (shift))
941 #define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask))
944 * upper_32_bits - return bits 32-63 of a number
945 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
946 * the "right shift count >= width of type" warning when that quantity is
949 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
951 /* lower_32_bits - return bits 0-31 of a number */
952 #define lower_32_bits(n) ((uint32_t)(n))
954 #define BIT(nr) (1UL << (nr))
956 #define BIT_ULL(x) (1ULL << (x))
958 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
959 #define GENMASK(h, l) \
960 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
962 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
963 #define rounddown(x, y) ((x) - ((x) % (y)))
965 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
968 * Because hardware always access register in little-endian mode based on hns3
969 * network engine, so driver should also call rte_cpu_to_le_32 to convert data
970 * in little-endian mode before writing register and call rte_le_to_cpu_32 to
971 * convert data after reading from register.
973 * Here the driver encapsulates the data conversion operation in the register
974 * read/write operation function as below:
978 * Therefore, when calling these functions, conversion is not required again.
980 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
982 rte_write32(rte_cpu_to_le_32(value),
983 (volatile void *)((char *)base + reg));
987 * The optimized function for writing registers used in the '.rx_pkt_burst' and
988 * '.tx_pkt_burst' ops implementation function.
990 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value)
993 rte_write32_relaxed(rte_cpu_to_le_32(value), addr);
996 static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
998 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg));
999 return rte_le_to_cpu_32(read_val);
1002 #define hns3_write_dev(a, reg, value) \
1003 hns3_write_reg((a)->io_base, (reg), (value))
1005 #define hns3_read_dev(a, reg) \
1006 hns3_read_reg((a)->io_base, (reg))
1008 #define ARRAY_SIZE(x) RTE_DIM(x)
1010 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
1012 act = (actions) + (index); \
1013 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
1015 act = actions + index; \
1019 #define MSEC_PER_SEC 1000L
1020 #define USEC_PER_MSEC 1000L
1022 static inline uint64_t
1023 get_timeofday_ms(void)
1027 (void)gettimeofday(&tv, NULL);
1029 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
1032 static inline uint64_t
1033 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
1037 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;
1042 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)
1044 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);
1048 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)
1050 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);
1053 static inline int64_t
1054 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)
1056 uint64_t mask = (1UL << nr);
1058 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
1061 int hns3_buffer_alloc(struct hns3_hw *hw);
1062 int hns3_dev_flow_ops_get(struct rte_eth_dev *dev,
1063 const struct rte_flow_ops **ops);
1064 bool hns3_is_reset_pending(struct hns3_adapter *hns);
1065 bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
1066 void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query);
1067 void hns3_ether_format_addr(char *buf, uint16_t size,
1068 const struct rte_ether_addr *ether_addr);
1069 int hns3_dev_infos_get(struct rte_eth_dev *eth_dev,
1070 struct rte_eth_dev_info *info);
1071 void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1072 uint32_t link_speed, uint8_t link_duplex);
1073 void hns3_parse_devargs(struct rte_eth_dev *dev);
1074 void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported);
1075 int hns3_restore_ptp(struct hns3_adapter *hns);
1076 int hns3_mbuf_dyn_rx_timestamp_register(struct rte_eth_dev *dev,
1077 struct rte_eth_conf *conf);
1078 int hns3_ptp_init(struct hns3_hw *hw);
1079 int hns3_timesync_enable(struct rte_eth_dev *dev);
1080 int hns3_timesync_disable(struct rte_eth_dev *dev);
1081 int hns3_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
1082 struct timespec *timestamp,
1083 uint32_t flags __rte_unused);
1084 int hns3_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
1085 struct timespec *timestamp);
1086 int hns3_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts);
1087 int hns3_timesync_write_time(struct rte_eth_dev *dev,
1088 const struct timespec *ts);
1089 int hns3_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
1092 is_reset_pending(struct hns3_adapter *hns)
1096 ret = hns3vf_is_reset_pending(hns);
1098 ret = hns3_is_reset_pending(hns);
1102 static inline uint64_t
1103 hns3_txvlan_cap_get(struct hns3_hw *hw)
1105 if (hw->port_base_vlan_cfg.state)
1106 return DEV_TX_OFFLOAD_VLAN_INSERT;
1108 return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT;
1111 #endif /* _HNS3_ETHDEV_H_ */