1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #ifndef _HNS3_ETHDEV_H_
6 #define _HNS3_ETHDEV_H_
10 #include <rte_ethdev_driver.h>
15 #include "hns3_fdir.h"
16 #include "hns3_stats.h"
19 #define PCI_VENDOR_ID_HUAWEI 0x19e5
22 #define HNS3_DEV_ID_GE 0xA220
23 #define HNS3_DEV_ID_25GE 0xA221
24 #define HNS3_DEV_ID_25GE_RDMA 0xA222
25 #define HNS3_DEV_ID_50GE_RDMA 0xA224
26 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226
27 #define HNS3_DEV_ID_200G_RDMA 0xA228
28 #define HNS3_DEV_ID_100G_VF 0xA22E
29 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
31 /* PCI Config offsets */
32 #define HNS3_PCI_REVISION_ID 0x08
33 #define HNS3_PCI_REVISION_ID_LEN 1
35 #define PCI_REVISION_ID_HIP08_B 0x21
36 #define PCI_REVISION_ID_HIP09_A 0x30
38 #define HNS3_PF_FUNC_ID 0
39 #define HNS3_1ST_VF_FUNC_ID 1
41 #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0
42 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1
44 #define HNS3_UC_MACADDR_NUM 128
45 #define HNS3_VF_UC_MACADDR_NUM 48
46 #define HNS3_MC_MACADDR_NUM 128
48 #define HNS3_MAX_BD_SIZE 65535
49 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8
50 #define HNS3_MAX_TSO_BD_PER_PKT 63
51 #define HNS3_MAX_FRAME_LEN 9728
52 #define HNS3_VLAN_TAG_SIZE 4
53 #define HNS3_DEFAULT_RX_BUF_LEN 2048
54 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
55 #define HNS3_MAX_TSO_HDR_SIZE 512
56 #define HNS3_MAX_TSO_HDR_BD_NUM 3
57 #define HNS3_MAX_LRO_SIZE 64512
59 #define HNS3_ETH_OVERHEAD \
60 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
61 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD)
62 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
63 #define HNS3_DEFAULT_MTU 1500UL
64 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
65 #define HNS3_HIP08_MIN_TX_PKT_LEN 33
66 #define HNS3_HIP09_MIN_TX_PKT_LEN 9
68 #define HNS3_BITS_PER_BYTE 8
73 #define HNS3_MAX_PF_NUM 8
74 #define HNS3_UMV_TBL_SIZE 3072
75 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \
76 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM)
78 #define HNS3_PF_CFG_BLOCK_SIZE 32
79 #define HNS3_PF_CFG_DESC_NUM \
80 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES)
82 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0
84 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5
85 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500
87 #define HNS3_QUIT_RESET_CNT 10
88 #define HNS3_QUIT_RESET_DELAY_MS 100
90 #define HNS3_POLL_RESPONE_MS 1
92 #define HNS3_MAX_USER_PRIO 8
102 #define HNS3_SCH_MODE_SP 0
103 #define HNS3_SCH_MODE_DWRR 1
104 struct hns3_pg_info {
106 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */
109 uint8_t tc_dwrr[HNS3_MAX_TC_NUM];
112 struct hns3_tc_info {
114 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */
117 uint8_t up_to_tc_map; /* user priority maping on the TC */
120 struct hns3_dcb_info {
122 uint8_t num_pg; /* It must be 1 if vNET-Base schd */
123 uint8_t pg_dwrr[HNS3_PG_NUM];
124 uint8_t prio_tc[HNS3_MAX_USER_PRIO];
125 struct hns3_pg_info pg_info[HNS3_PG_NUM];
126 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM];
127 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */
128 uint8_t pfc_en; /* Pfc enabled or not for user priority */
131 enum hns3_fc_status {
133 HNS3_FC_STATUS_MAC_PAUSE,
137 struct hns3_tc_queue_info {
138 uint16_t tqp_offset; /* TQP offset from base TQP */
139 uint16_t tqp_count; /* Total TQPs */
140 uint8_t tc; /* TC index */
141 bool enable; /* If this TC is enable or not */
145 uint8_t vmdq_vport_num;
147 uint16_t tqp_desc_num;
149 uint16_t rss_size_max;
152 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
153 uint8_t default_speed;
154 uint32_t numa_node_map;
155 uint8_t speed_ability;
160 enum hns3_media_type {
161 HNS3_MEDIA_TYPE_UNKNOWN,
162 HNS3_MEDIA_TYPE_FIBER,
163 HNS3_MEDIA_TYPE_COPPER,
164 HNS3_MEDIA_TYPE_BACKPLANE,
165 HNS3_MEDIA_TYPE_NONE,
169 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
170 bool default_addr_setted; /* whether default addr(mac_addr) is setted */
173 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
174 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
175 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
176 uint32_t link_speed; /* ETH_SPEED_NUM_ */
179 struct hns3_fake_queue_data {
180 void **rx_queues; /* Array of pointers to fake RX queues. */
181 void **tx_queues; /* Array of pointers to fake TX queues. */
182 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */
183 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
186 #define HNS3_PORT_BASE_VLAN_DISABLE 0
187 #define HNS3_PORT_BASE_VLAN_ENABLE 1
188 struct hns3_port_base_vlan_config {
193 /* Primary process maintains driver state in main thread.
196 * | UNINITIALIZED |<-----------+
197 * +---------------+ |
198 * |.eth_dev_init |.eth_dev_uninit
200 * +---------------+------------+
202 * +---------------+<-----------<---------------+
203 * |.dev_configure | |
205 * +---------------+------------+ |
207 * +---------------+----+ |
209 * | | +---------------+
211 * | | +---------------+
213 * V |.dev_configure |
214 * +---------------+----+ |.dev_close
215 * | CONFIGURED |----------------------------+
216 * +---------------+<-----------+
219 * +---------------+ |
220 * | STARTING |------------^
221 * +---------------+ failed |
223 * | +---------------+
225 * | +---------------+
228 * +---------------+------------+
232 enum hns3_adapter_state {
233 HNS3_NIC_UNINITIALIZED = 0,
234 HNS3_NIC_INITIALIZED,
235 HNS3_NIC_CONFIGURING,
246 /* Reset various stages, execute in order */
247 enum hns3_reset_stage {
248 /* Stop query services, stop transceiver, disable MAC */
250 /* Clear reset completion flags, disable send command */
252 /* Inform IMP to start resetting */
253 RESET_STAGE_REQ_HW_RESET,
254 /* Waiting for hardware reset to complete */
256 /* Reinitialize hardware */
257 RESET_STAGE_DEV_INIT,
258 /* Restore user settings and enable MAC */
260 /* Restart query services, start transceiver */
262 /* Not in reset state */
266 enum hns3_reset_level {
268 HNS3_VF_FUNC_RESET, /* A VF function reset */
270 * All VFs under a PF perform function reset.
271 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
272 * of the reset level and the one defined in kernel driver should be
275 HNS3_VF_PF_FUNC_RESET = 2,
277 * All VFs under a PF perform FLR reset.
278 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
279 * of the reset level and the one defined in kernel driver should be
282 * According to the protocol of PCIe, FLR to a PF resets the PF state as
283 * well as the SR-IOV extended capability including VF Enable which
284 * means that VFs no longer exist.
286 * In PF FLR, the register state of VF is not reliable, VF's driver
287 * should not access the registers of the VF device.
289 HNS3_VF_FULL_RESET = 3,
290 HNS3_FLR_RESET, /* A VF perform FLR reset */
291 /* All VFs under the rootport perform a global or IMP reset */
293 HNS3_FUNC_RESET, /* A PF function reset */
294 /* All PFs under the rootport perform a global reset */
296 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
300 enum hns3_wait_result {
307 #define HNS3_RESET_SYNC_US 100000
309 struct hns3_reset_stats {
310 uint64_t request_cnt; /* Total request reset times */
311 uint64_t global_cnt; /* Total GLOBAL reset times */
312 uint64_t imp_cnt; /* Total IMP reset times */
313 uint64_t exec_cnt; /* Total reset executive times */
314 uint64_t success_cnt; /* Total reset successful times */
315 uint64_t fail_cnt; /* Total reset failed times */
316 uint64_t merge_cnt; /* Total merged in high reset times */
319 typedef bool (*check_completion_func)(struct hns3_hw *hw);
321 struct hns3_wait_data {
326 enum hns3_wait_result result;
327 check_completion_func check_completion;
330 struct hns3_reset_ops {
331 void (*reset_service)(void *arg);
332 int (*stop_service)(struct hns3_adapter *hns);
333 int (*prepare_reset)(struct hns3_adapter *hns);
334 int (*wait_hardware_ready)(struct hns3_adapter *hns);
335 int (*reinit_dev)(struct hns3_adapter *hns);
336 int (*restore_conf)(struct hns3_adapter *hns);
337 int (*start_service)(struct hns3_adapter *hns);
347 struct hns3_reset_data {
348 enum hns3_reset_stage stage;
349 rte_atomic16_t schedule;
350 /* Reset flag, covering the entire reset process */
351 rte_atomic16_t resetting;
352 /* Used to disable sending cmds during reset */
353 rte_atomic16_t disable_cmd;
354 /* The reset level being processed */
355 enum hns3_reset_level level;
356 /* Reset level set, each bit represents a reset level */
358 /* Request reset level set, from interrupt or mailbox */
360 int attempts; /* Reset failure retry */
361 int retries; /* Timeout failure retry in reset_post */
363 * At the time of global or IMP reset, the command cannot be sent to
364 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the
365 * reset process, so the mbuf is required to be released after the reset
366 * is completed.The mbuf_deferred_free is used to mark whether mbuf
367 * needs to be released.
369 bool mbuf_deferred_free;
370 struct timeval start_time;
371 struct hns3_reset_stats stats;
372 const struct hns3_reset_ops *ops;
373 struct hns3_wait_data *wait_data;
376 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0
377 #define HNS3_INTR_MAPPING_VEC_ALL 1
379 #define HNS3_INTR_COALESCE_NON_QL 0
380 #define HNS3_INTR_COALESCE_QL 1
382 #define HNS3_INTR_COALESCE_GL_UINT_2US 0
383 #define HNS3_INTR_COALESCE_GL_UINT_1US 1
385 struct hns3_queue_intr {
387 * interrupt mapping mode.
389 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL
391 * - HNS3_INTR_MAPPING_VEC_RSV_ONE
392 * For some versions of hardware network engine, because of the
393 * hardware constraint, we need implement clearing the mapping
394 * relationship configurations by binding all queues to the last
395 * interrupt vector and reserving the last interrupt vector. This
396 * method results in a decrease of the maximum queues when upper
397 * applications call the rte_eth_dev_configure API function to
398 * enable Rx interrupt.
400 * - HNS3_INTR_MAPPING_VEC_ALL
401 * PMD driver can map/unmmap all interrupt vectors with queues When
402 * Rx interrupt in enabled.
404 uint8_t mapping_mode;
406 * interrupt coalesce mode.
408 * HNS3_INTR_COALESCE_NON_QL/HNS3_INTR_COALESCE_QL
410 * - HNS3_INTR_COALESCE_NON_QL
411 * For some versions of hardware network engine, hardware doesn't
412 * support QL(quanity limiter) algorithm for interrupt coalesce
413 * of queue's interrupt.
415 * - HNS3_INTR_COALESCE_QL
416 * In this mode, hardware support QL(quanity limiter) algorithm for
417 * interrupt coalesce of queue's interrupt.
419 uint8_t coalesce_mode;
421 * The unit of GL(gap limiter) configuration for interrupt coalesce of
424 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US
429 #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0
430 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1
433 struct rte_eth_dev_data *data;
435 uint8_t revision; /* PCI revision, low byte of class word */
437 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
438 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */
439 pthread_t irq_thread_id;
441 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
442 struct hns3_tqp_stats tqp_stats;
443 /* Include Mac stats | Rx stats | Tx stats */
444 struct hns3_mac_stats mac_stats;
448 uint16_t total_tqps_num; /* total task queue pairs of this PF */
449 uint16_t tqps_num; /* num task queue pairs of this function */
450 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
451 uint16_t rss_size_max; /* HW defined max RSS task queue */
452 uint16_t rx_buf_len; /* hold min hardware rx buf len */
453 uint16_t num_tx_desc; /* desc num of per tx queue */
454 uint16_t num_rx_desc; /* desc num of per rx queue */
455 uint32_t mng_entry_num; /* number of manager table entry */
456 uint32_t mac_entry_num; /* number of mac-vlan table entry */
458 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
459 int mc_addrs_num; /* Multicast mac addresses number */
461 /* The configuration info of RSS */
462 struct hns3_rss_conf rss_info;
463 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
464 uint16_t rss_ind_tbl_size;
465 uint16_t rss_key_size;
467 uint8_t num_tc; /* Total number of enabled TCs */
469 enum hns3_fc_mode current_mode;
470 enum hns3_fc_mode requested_mode;
471 struct hns3_dcb_info dcb_info;
472 enum hns3_fc_status current_fc_status; /* current flow control status */
473 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
474 uint16_t used_rx_queues;
475 uint16_t used_tx_queues;
477 /* Config max queue numbers between rx and tx queues from user */
478 uint16_t cfg_max_queues;
479 struct hns3_fake_queue_data fkq_data; /* fake queue data */
480 uint16_t alloc_rss_size; /* RX queue number per TC */
481 uint16_t tx_qnum_per_tc; /* TX queue number per TC */
484 uint32_t max_tm_rate;
486 * The minimum length of the packet supported by hardware in the Tx
489 uint32_t min_tx_pkt_len;
491 struct hns3_queue_intr intr;
495 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
497 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM
498 * In this mode, because of the hardware constraint, network driver
499 * software need erase the L4 len value of the TCP pseudo header
500 * and recalculate the TCP pseudo header checksum of packets that
503 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
504 * In this mode, hardware support recalculate the TCP pseudo header
505 * checksum of packets that need TSO, so network driver software
506 * not need to recalculate it.
512 * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE
514 * - HNS3_SW_SHIFT_AND_DISCARD_MODE
515 * For some versions of hardware network engine, because of the
516 * hardware limitation, PMD driver needs to detect the PVID status
517 * to work with haredware to implement PVID-related functions.
518 * For example, driver need discard the stripped PVID tag to ensure
519 * the PVID will not report to mbuf and shift the inserted VLAN tag
520 * to avoid port based VLAN covering it.
522 * - HNS3_HW_SHIT_AND_DISCARD_MODE
523 * PMD driver does not need to process PVID-related functions in
524 * I/O process, Hardware will adjust the sequence between port based
525 * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by
526 * PVID will be invisible to driver. And in this mode, hns3 is able
527 * to send a multi-layer VLAN packets when hw VLAN insert offload
531 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
533 struct hns3_port_base_vlan_config port_base_vlan_cfg;
535 * PMD setup and configuration is not thread safe. Since it is not
536 * performance sensitive, it is better to guarantee thread-safety
537 * and add device level lock. Adapter control operations which
538 * change its state should acquire the lock.
541 enum hns3_adapter_state adapter_state;
542 struct hns3_reset_data reset;
545 #define HNS3_FLAG_TC_BASE_SCH_MODE 1
546 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2
548 struct hns3_err_msix_intr_stats {
549 uint64_t mac_afifo_tnl_int_cnt;
550 uint64_t ppu_mpf_abn_int_st2_msix_cnt;
551 uint64_t ssu_port_based_pf_int_cnt;
552 uint64_t ppp_pf_abnormal_int_cnt;
553 uint64_t ppu_pf_abnormal_int_msix_cnt;
555 uint64_t imp_tcm_ecc_int_cnt;
556 uint64_t cmdq_mem_ecc_int_cnt;
557 uint64_t imp_rd_poison_int_cnt;
558 uint64_t tqp_int_ecc_int_cnt;
559 uint64_t msix_ecc_int_cnt;
560 uint64_t ssu_ecc_multi_bit_int_0_cnt;
561 uint64_t ssu_ecc_multi_bit_int_1_cnt;
562 uint64_t ssu_common_ecc_int_cnt;
563 uint64_t igu_int_cnt;
564 uint64_t ppp_mpf_abnormal_int_st1_cnt;
565 uint64_t ppp_mpf_abnormal_int_st3_cnt;
566 uint64_t ppu_mpf_abnormal_int_st1_cnt;
567 uint64_t ppu_mpf_abn_int_st2_ras_cnt;
568 uint64_t ppu_mpf_abnormal_int_st3_cnt;
569 uint64_t tm_sch_int_cnt;
570 uint64_t qcn_fifo_int_cnt;
571 uint64_t qcn_ecc_int_cnt;
572 uint64_t ncsi_ecc_int_cnt;
573 uint64_t ssu_port_based_err_int_cnt;
574 uint64_t ssu_fifo_overflow_int_cnt;
575 uint64_t ssu_ets_tcg_int_cnt;
576 uint64_t igu_egu_tnl_int_cnt;
577 uint64_t ppu_pf_abnormal_int_ras_cnt;
580 /* vlan entry information. */
581 struct hns3_user_vlan_table {
582 LIST_ENTRY(hns3_user_vlan_table) next;
587 /* Vlan tag configuration for RX direction */
588 struct hns3_rx_vtag_cfg {
589 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */
590 bool strip_tag1_en; /* Whether strip inner vlan tag */
591 bool strip_tag2_en; /* Whether strip outer vlan tag */
593 * If strip_tag_en is enabled, this bit decide whether to map the vlan
596 bool strip_tag1_discard_en;
597 bool strip_tag2_discard_en;
599 * If this bit is enabled, only map inner/outer priority to descriptor
600 * and the vlan tag is always 0.
602 bool vlan1_vlan_prionly;
603 bool vlan2_vlan_prionly;
606 /* Vlan tag configuration for TX direction */
607 struct hns3_tx_vtag_cfg {
608 bool accept_tag1; /* Whether accept tag1 packet from host */
609 bool accept_untag1; /* Whether accept untag1 packet from host */
612 bool insert_tag1_en; /* Whether insert outer vlan tag */
613 bool insert_tag2_en; /* Whether insert inner vlan tag */
615 * In shift mode, hw will shift the sequence of port based VLAN and
618 bool tag_shift_mode_en; /* hw shift vlan tag automatically */
619 uint16_t default_tag1; /* The default outer vlan tag to insert */
620 uint16_t default_tag2; /* The default inner vlan tag to insert */
623 struct hns3_vtag_cfg {
624 struct hns3_rx_vtag_cfg rx_vcfg;
625 struct hns3_tx_vtag_cfg tx_vcfg;
628 /* Request types for IPC. */
629 enum hns3_mp_req_type {
630 HNS3_MP_REQ_START_RXTX = 1,
631 HNS3_MP_REQ_STOP_RXTX,
635 /* Pameters for IPC. */
636 struct hns3_mp_param {
637 enum hns3_mp_req_type type;
642 /* Request timeout for IPC. */
643 #define HNS3_MP_REQ_TIMEOUT_SEC 5
645 /* Key string for IPC. */
646 #define HNS3_MP_NAME "net_hns3_mp"
648 #define HNS3_L2TBL_NUM 4
649 #define HNS3_L3TBL_NUM 16
650 #define HNS3_L4TBL_NUM 16
651 #define HNS3_OL2TBL_NUM 4
652 #define HNS3_OL3TBL_NUM 16
653 #define HNS3_OL4TBL_NUM 16
655 struct hns3_ptype_table {
656 uint32_t l2l3table[HNS3_L2TBL_NUM][HNS3_L3TBL_NUM];
657 uint32_t l4table[HNS3_L4TBL_NUM];
658 uint32_t inner_l2table[HNS3_L2TBL_NUM];
659 uint32_t inner_l3table[HNS3_L3TBL_NUM];
660 uint32_t inner_l4table[HNS3_L4TBL_NUM];
661 uint32_t ol2table[HNS3_OL2TBL_NUM];
662 uint32_t ol3table[HNS3_OL3TBL_NUM];
663 uint32_t ol4table[HNS3_OL4TBL_NUM];
666 #define HNS3_FIXED_MAX_TQP_NUM_MODE 0
667 #define HNS3_FLEX_MAX_TQP_NUM_MODE 1
670 struct hns3_adapter *adapter;
672 uint16_t func_num; /* num functions of this pf, include pf and vfs */
676 * tqp_config_mode value range:
677 * HNS3_FIXED_MAX_TQP_NUM_MODE,
678 * HNS3_FLEX_MAX_TQP_NUM_MODE
680 * - HNS3_FIXED_MAX_TQP_NUM_MODE
681 * There is a limitation on the number of pf interrupts available for
682 * on some versions of network engines. In this case, the maximum
683 * queue number of pf can not be greater than the interrupt number,
684 * such as pf of network engine with revision_id 0x21. So the maximum
685 * number of queues must be fixed.
687 * - HNS3_FLEX_MAX_TQP_NUM_MODE
688 * In this mode, the maximum queue number of pf has not any constraint
689 * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF
690 * in the config file. Users can modify the macro according to their
691 * own application scenarios, which is more flexible to use.
693 uint8_t tqp_config_mode;
695 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
696 uint32_t tx_buf_size; /* Tx buffer size for each TC */
697 uint32_t dv_buf_size; /* Dv buffer size for each TC */
699 uint16_t mps; /* Max packet size */
702 uint8_t tc_max; /* max number of tc driver supported */
703 uint8_t local_max_tc; /* max number of local tc */
705 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */
707 bool support_fc_autoneg; /* support FC autonegotiate */
709 uint16_t wanted_umv_size;
710 uint16_t max_umv_size;
711 uint16_t used_umv_size;
713 /* Statistics information for abnormal interrupt */
714 struct hns3_err_msix_intr_stats abn_int_stats;
716 bool support_sfp_query;
717 uint32_t fec_mode; /* current FEC mode for ethdev */
719 struct hns3_vtag_cfg vtag_config;
720 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
722 struct hns3_fdir_info fdir; /* flow director info */
723 LIST_HEAD(counters, hns3_flow_counter) flow_counters;
727 struct hns3_adapter *adapter;
730 struct hns3_adapter {
733 /* Specific for PF or VF */
734 bool is_vf; /* false - PF, true - VF */
740 bool rx_simple_allowed;
742 bool tx_simple_allowed;
745 struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
748 #define HNS3_DEV_SUPPORT_DCB_B 0x0
749 #define HNS3_DEV_SUPPORT_COPPER_B 0x1
750 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
751 #define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3
752 #define HNS3_DEV_SUPPORT_PTP_B 0x4
753 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5
754 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6
755 #define HNS3_DEV_SUPPORT_STASH_B 0x7
757 #define hns3_dev_dcb_supported(hw) \
758 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
760 /* Support copper media type */
761 #define hns3_dev_copper_supported(hw) \
762 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B)
764 /* Support UDP GSO offload */
765 #define hns3_dev_udp_gso_supported(hw) \
766 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
768 /* Support the queue region action rule of flow directory */
769 #define hns3_dev_fd_queue_region_supported(hw) \
770 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B)
772 /* Support PTP timestamp offload */
773 #define hns3_dev_ptp_supported(hw) \
774 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B)
776 #define hns3_dev_tx_push_supported(hw) \
777 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)
779 /* Support to Independently enable/disable/reset Tx or Rx queues */
780 #define hns3_dev_indep_txrx_supported(hw) \
781 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B)
783 #define hns3_dev_stash_supported(hw) \
784 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B)
786 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
787 (&((struct hns3_adapter *)adapter)->hw)
788 #define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \
789 ((struct hns3_adapter *)adapter)
790 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \
791 (&((struct hns3_adapter *)adapter)->pf)
792 #define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \
793 (&((struct hns3_adapter *)adapter)->vf)
794 #define HNS3_DEV_HW_TO_ADAPTER(hw) \
795 container_of(hw, struct hns3_adapter, hw)
797 #define hns3_set_field(origin, mask, shift, val) \
799 (origin) &= (~(mask)); \
800 (origin) |= ((val) << (shift)) & (mask); \
802 #define hns3_get_field(origin, mask, shift) \
803 (((origin) & (mask)) >> (shift))
804 #define hns3_set_bit(origin, shift, val) \
805 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val))
806 #define hns3_get_bit(origin, shift) \
807 hns3_get_field((origin), (0x1UL << (shift)), (shift))
810 * upper_32_bits - return bits 32-63 of a number
811 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
812 * the "right shift count >= width of type" warning when that quantity is
815 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
817 /* lower_32_bits - return bits 0-31 of a number */
818 #define lower_32_bits(n) ((uint32_t)(n))
820 #define BIT(nr) (1UL << (nr))
822 #define BIT_ULL(x) (1ULL << (x))
824 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
825 #define GENMASK(h, l) \
826 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
828 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
829 #define rounddown(x, y) ((x) - ((x) % (y)))
831 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
834 * Because hardware always access register in little-endian mode based on hns3
835 * network engine, so driver should also call rte_cpu_to_le_32 to convert data
836 * in little-endian mode before writing register and call rte_le_to_cpu_32 to
837 * convert data after reading from register.
839 * Here the driver encapsulates the data conversion operation in the register
840 * read/write operation function as below:
844 * Therefore, when calling these functions, conversion is not required again.
846 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
848 rte_write32(rte_cpu_to_le_32(value),
849 (volatile void *)((char *)base + reg));
853 * The optimized function for writing registers used in the '.rx_pkt_burst' and
854 * '.tx_pkt_burst' ops implementation function.
856 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value)
859 rte_write32_relaxed(rte_cpu_to_le_32(value), addr);
862 static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
864 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg));
865 return rte_le_to_cpu_32(read_val);
868 #define hns3_write_dev(a, reg, value) \
869 hns3_write_reg((a)->io_base, (reg), (value))
871 #define hns3_read_dev(a, reg) \
872 hns3_read_reg((a)->io_base, (reg))
874 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
876 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
878 act = (actions) + (index); \
879 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
881 act = actions + index; \
885 #define MSEC_PER_SEC 1000L
886 #define USEC_PER_MSEC 1000L
888 static inline uint64_t
889 get_timeofday_ms(void)
893 (void)gettimeofday(&tv, NULL);
895 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
898 static inline uint64_t
899 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
903 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;
908 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)
910 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);
914 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)
916 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);
919 static inline int64_t
920 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)
922 uint64_t mask = (1UL << nr);
924 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
927 int hns3_buffer_alloc(struct hns3_hw *hw);
928 int hns3_dev_filter_ctrl(struct rte_eth_dev *dev,
929 enum rte_filter_type filter_type,
930 enum rte_filter_op filter_op, void *arg);
931 bool hns3_is_reset_pending(struct hns3_adapter *hns);
932 bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
933 void hns3_update_link_status(struct hns3_hw *hw);
936 is_reset_pending(struct hns3_adapter *hns)
940 ret = hns3vf_is_reset_pending(hns);
942 ret = hns3_is_reset_pending(hns);
946 static inline uint64_t
947 hns3_txvlan_cap_get(struct hns3_hw *hw)
949 if (hw->port_base_vlan_cfg.state)
950 return DEV_TX_OFFLOAD_VLAN_INSERT;
952 return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT;
955 #endif /* _HNS3_ETHDEV_H_ */