drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
  48                                    __rte_unused int wait_to_complete);
  49
  50 /* set PCI bus mastering */
  51 static int
  52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  53 {
  54         uint16_t reg;
  55         int ret;
  56
  57         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  58         if (ret < 0) {
  59                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  60                              PCI_COMMAND);
  61                 return ret;
  62         }
  63
  64         if (op)
  65                 /* set the master bit */
  66                 reg |= PCI_COMMAND_MASTER;
  67         else
  68                 reg &= ~(PCI_COMMAND_MASTER);
  69
  70         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  71 }
  72
  73 /**
  74  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  75  * @cap: the capability
  76  *
  77  * Return the address of the given capability within the PCI capability list.
  78  */
  79 static int
  80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  81 {
  82 #define MAX_PCIE_CAPABILITY 48
  83         uint16_t status;
  84         uint8_t pos;
  85         uint8_t id;
  86         int ttl;
  87         int ret;
  88
  89         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  90         if (ret < 0) {
  91                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  92                 return 0;
  93         }
  94
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 100                                   PCI_CAPABILITY_LIST);
 101         if (ret < 0) {
 102                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 103                              PCI_CAPABILITY_LIST);
 104                 return 0;
 105         }
 106
 107         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 108                 ret = rte_pci_read_config(device, &id, sizeof(id),
 109                                           (pos + PCI_CAP_LIST_ID));
 110                 if (ret < 0) {
 111                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 112                                      (pos + PCI_CAP_LIST_ID));
 113                         break;
 114                 }
 115
 116                 if (id == 0xFF)
 117                         break;
 118
 119                 if (id == cap)
 120                         return (int)pos;
 121
 122                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 123                                           (pos + PCI_CAP_LIST_NEXT));
 124                 if (ret < 0) {
 125                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 126                                      (pos + PCI_CAP_LIST_NEXT));
 127                         break;
 128                 }
 129         }
 130         return 0;
 131 }
 132
 133 static int
 134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 135 {
 136         uint16_t control;
 137         int pos;
 138         int ret;
 139
 140         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 141         if (pos) {
 142                 ret = rte_pci_read_config(device, &control, sizeof(control),
 143                                     (pos + PCI_MSIX_FLAGS));
 144                 if (ret < 0) {
 145                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 146                                      (pos + PCI_MSIX_FLAGS));
 147                         return -ENXIO;
 148                 }
 149
 150                 if (op)
 151                         control |= PCI_MSIX_FLAGS_ENABLE;
 152                 else
 153                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 154                 ret = rte_pci_write_config(device, &control, sizeof(control),
 155                                           (pos + PCI_MSIX_FLAGS));
 156                 if (ret < 0) {
 157                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 158                                     (pos + PCI_MSIX_FLAGS));
 159                         return -ENXIO;
 160                 }
 161
 162                 return 0;
 163         }
 164
 165         return -ENXIO;
 166 }
 167
 168 static int
 169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 170 {
 171         /* mac address was checked by upper level interface */
 172         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 173         int ret;
 174
 175         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 176                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 177                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 178         if (ret) {
 179                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 180                                       mac_addr);
 181                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 182                          mac_str, ret);
 183         }
 184         return ret;
 185 }
 186
 187 static int
 188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 189 {
 190         /* mac address was checked by upper level interface */
 191         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 192         int ret;
 193
 194         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 195                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 196                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 197                                 false, NULL, 0);
 198         if (ret) {
 199                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 200                                       mac_addr);
 201                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 202                          mac_str, ret);
 203         }
 204         return ret;
 205 }
 206
 207 static int
 208 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 209                             struct rte_ether_addr *mac_addr)
 210 {
 211 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 212         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 213         struct rte_ether_addr *old_addr;
 214         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 215         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 216         int ret;
 217
 218         /*
 219          * It has been guaranteed that input parameter named mac_addr is valid
 220          * address in the rte layer of DPDK framework.
 221          */
 222         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 223         rte_spinlock_lock(&hw->lock);
 224         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 225         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 226                RTE_ETHER_ADDR_LEN);
 227
 228         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 229                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 230                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 231         if (ret) {
 232                 /*
 233                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 234                  * driver. When user has configured a MAC address for VF device
 235                  * by "ip link set ..." command based on the PF device, the hns3
 236                  * PF kernel ethdev driver does not allow VF driver to request
 237                  * reconfiguring a different default MAC address, and return
 238                  * -EPREM to VF driver through mailbox.
 239                  */
 240                 if (ret == -EPERM) {
 241                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 242                                               old_addr);
 243                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 244                                   mac_str);
 245                 } else {
 246                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 247                                               mac_addr);
 248                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 249                                  mac_str, ret);
 250                 }
 251         }
 252
 253         rte_ether_addr_copy(mac_addr,
 254                             (struct rte_ether_addr *)hw->mac.mac_addr);
 255         rte_spinlock_unlock(&hw->lock);
 256
 257         return ret;
 258 }
 259
 260 static int
 261 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 262                        struct rte_ether_addr *mac_addr)
 263 {
 264         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 265         int ret;
 266
 267         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 268                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 269                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 270                                 NULL, 0);
 271         if (ret) {
 272                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 273                                       mac_addr);
 274                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 275                          mac_str, ret);
 276         }
 277
 278         return ret;
 279 }
 280
 281 static int
 282 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 283                           struct rte_ether_addr *mac_addr)
 284 {
 285         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 286         int ret;
 287
 288         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 289                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 290                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 291                                 NULL, 0);
 292         if (ret) {
 293                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 294                                       mac_addr);
 295                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 296                          mac_str, ret);
 297         }
 298
 299         return ret;
 300 }
 301
 302 static int
 303 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 304                         bool en_uc_pmc, bool en_mc_pmc)
 305 {
 306         struct hns3_mbx_vf_to_pf_cmd *req;
 307         struct hns3_cmd_desc desc;
 308         int ret;
 309
 310         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 311
 312         /*
 313          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 314          * so there are some features for promiscuous/allmulticast mode in hns3
 315          * VF PMD driver as below:
 316          * 1. The promiscuous/allmulticast mode can be configured successfully
 317          *    only based on the trusted VF device. If based on the non trusted
 318          *    VF device, configuring promiscuous/allmulticast mode will fail.
 319          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 320          *    kernel ethdev driver on the host by the following command:
 321          *      "ip link set <eth num> vf <vf id> turst on"
 322          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 323          *    driver can receive the ingress and outgoing traffic. In the words,
 324          *    all the ingress packets, all the packets sent from the PF and
 325          *    other VFs on the same physical port.
 326          * 3. Note: Because of the hardware constraints, By default vlan filter
 327          *    is enabled and couldn't be turned off based on VF device, so vlan
 328          *    filter is still effective even in promiscuous mode. If upper
 329          *    applications don't call rte_eth_dev_vlan_filter API function to
 330          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 331          *    the packets with vlan tag in promiscuoue mode.
 332          */
 333         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 334         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 335         req->msg[1] = en_bc_pmc ? 1 : 0;
 336         req->msg[2] = en_uc_pmc ? 1 : 0;
 337         req->msg[3] = en_mc_pmc ? 1 : 0;
 338         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 339
 340         ret = hns3_cmd_send(hw, &desc, 1);
 341         if (ret)
 342                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 343
 344         return ret;
 345 }
 346
 347 static int
 348 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 349 {
 350         struct hns3_adapter *hns = dev->data->dev_private;
 351         struct hns3_hw *hw = &hns->hw;
 352         int ret;
 353
 354         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 355         if (ret)
 356                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 357                         ret);
 358         return ret;
 359 }
 360
 361 static int
 362 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 363 {
 364         bool allmulti = dev->data->all_multicast ? true : false;
 365         struct hns3_adapter *hns = dev->data->dev_private;
 366         struct hns3_hw *hw = &hns->hw;
 367         int ret;
 368
 369         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 370         if (ret)
 371                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 372                         ret);
 373         return ret;
 374 }
 375
 376 static int
 377 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 378 {
 379         struct hns3_adapter *hns = dev->data->dev_private;
 380         struct hns3_hw *hw = &hns->hw;
 381         int ret;
 382
 383         if (dev->data->promiscuous)
 384                 return 0;
 385
 386         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 387         if (ret)
 388                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 389                         ret);
 390         return ret;
 391 }
 392
 393 static int
 394 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 395 {
 396         struct hns3_adapter *hns = dev->data->dev_private;
 397         struct hns3_hw *hw = &hns->hw;
 398         int ret;
 399
 400         if (dev->data->promiscuous)
 401                 return 0;
 402
 403         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 404         if (ret)
 405                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 406                         ret);
 407         return ret;
 408 }
 409
 410 static int
 411 hns3vf_restore_promisc(struct hns3_adapter *hns)
 412 {
 413         struct hns3_hw *hw = &hns->hw;
 414         bool allmulti = hw->data->all_multicast ? true : false;
 415
 416         if (hw->data->promiscuous)
 417                 return hns3vf_set_promisc_mode(hw, true, true, true);
 418
 419         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 420 }
 421
 422 static int
 423 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 424                              bool mmap, enum hns3_ring_type queue_type,
 425                              uint16_t queue_id)
 426 {
 427         struct hns3_vf_bind_vector_msg bind_msg;
 428         const char *op_str;
 429         uint16_t code;
 430         int ret;
 431
 432         memset(&bind_msg, 0, sizeof(bind_msg));
 433         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 434                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 435         bind_msg.vector_id = vector_id;
 436
 437         if (queue_type == HNS3_RING_TYPE_RX)
 438                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 439         else
 440                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 441
 442         bind_msg.param[0].ring_type = queue_type;
 443         bind_msg.ring_num = 1;
 444         bind_msg.param[0].tqp_index = queue_id;
 445         op_str = mmap ? "Map" : "Unmap";
 446         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 447                                 sizeof(bind_msg), false, NULL, 0);
 448         if (ret)
 449                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 450                          op_str, queue_id, bind_msg.vector_id, ret);
 451
 452         return ret;
 453 }
 454
 455 static int
 456 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 457 {
 458         uint16_t vec;
 459         int ret;
 460         int i;
 461
 462         /*
 463          * In hns3 network engine, vector 0 is always the misc interrupt of this
 464          * function, vector 1~N can be used respectively for the queues of the
 465          * function. Tx and Rx queues with the same number share the interrupt
 466          * vector. In the initialization clearing the all hardware mapping
 467          * relationship configurations between queues and interrupt vectors is
 468          * needed, so some error caused by the residual configurations, such as
 469          * the unexpected Tx interrupt, can be avoid.
 470          */
 471         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 472         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 473                 vec = vec - 1; /* the last interrupt is reserved */
 474         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 475         for (i = 0; i < hw->intr_tqps_num; i++) {
 476                 /*
 477                  * Set gap limiter/rate limiter/quanity limiter algorithm
 478                  * configuration for interrupt coalesce of queue's interrupt.
 479                  */
 480                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 481                                        HNS3_TQP_INTR_GL_DEFAULT);
 482                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 483                                        HNS3_TQP_INTR_GL_DEFAULT);
 484                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 485                 /*
 486                  * QL(quantity limiter) is not used currently, just set 0 to
 487                  * close it.
 488                  */
 489                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 490
 491                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 492                                                    HNS3_RING_TYPE_TX, i);
 493                 if (ret) {
 494                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 495                                           "vector: %u, ret=%d", i, vec, ret);
 496                         return ret;
 497                 }
 498
 499                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 500                                                    HNS3_RING_TYPE_RX, i);
 501                 if (ret) {
 502                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 503                                           "vector: %u, ret=%d", i, vec, ret);
 504                         return ret;
 505                 }
 506         }
 507
 508         return 0;
 509 }
 510
 511 static int
 512 hns3vf_dev_configure(struct rte_eth_dev *dev)
 513 {
 514         struct hns3_adapter *hns = dev->data->dev_private;
 515         struct hns3_hw *hw = &hns->hw;
 516         struct rte_eth_conf *conf = &dev->data->dev_conf;
 517         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 518         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 519         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 520         struct rte_eth_rss_conf rss_conf;
 521         bool gro_en;
 522         int ret;
 523
 524         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 525
 526         /*
 527          * Some versions of hardware network engine does not support
 528          * individually enable/disable/reset the Tx or Rx queue. These devices
 529          * must enable/disable/reset Tx and Rx queues at the same time. When the
 530          * numbers of Tx queues allocated by upper applications are not equal to
 531          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 532          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 533          * work as usual. But these fake queues are imperceptible, and can not
 534          * be used by upper applications.
 535          */
 536         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 537         if (ret) {
 538                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
 539                 hw->cfg_max_queues = 0;
 540                 return ret;
 541         }
 542
 543         hw->adapter_state = HNS3_NIC_CONFIGURING;
 544         if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
 545                 hns3_err(hw, "setting link speed/duplex not supported");
 546                 ret = -EINVAL;
 547                 goto cfg_err;
 548         }
 549
 550         /* When RSS is not configured, redirect the packet queue 0 */
 551         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
 552                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
 553                 hw->rss_dis_flag = false;
 554                 rss_conf = conf->rx_adv_conf.rss_conf;
 555                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 556                 if (ret)
 557                         goto cfg_err;
 558         }
 559
 560         ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
 561         if (ret != 0)
 562                 goto cfg_err;
 563
 564         ret = hns3vf_dev_configure_vlan(dev);
 565         if (ret)
 566                 goto cfg_err;
 567
 568         /* config hardware GRO */
 569         gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
 570         ret = hns3_config_gro(hw, gro_en);
 571         if (ret)
 572                 goto cfg_err;
 573
 574         hns3_init_rx_ptype_tble(dev);
 575
 576         hw->adapter_state = HNS3_NIC_CONFIGURED;
 577         return 0;
 578
 579 cfg_err:
 580         hw->cfg_max_queues = 0;
 581         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 582         hw->adapter_state = HNS3_NIC_INITIALIZED;
 583
 584         return ret;
 585 }
 586
 587 static int
 588 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 589 {
 590         int ret;
 591
 592         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 593                                 sizeof(mtu), true, NULL, 0);
 594         if (ret)
 595                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 596
 597         return ret;
 598 }
 599
 600 static int
 601 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 602 {
 603         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 604         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 605         int ret;
 606
 607         /*
 608          * The hns3 PF/VF devices on the same port share the hardware MTU
 609          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 610          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 611          * driver, there is no need to stop the port for hns3 VF device, and the
 612          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 613          * PF's MTU.
 614          */
 615         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 616                 hns3_err(hw, "Failed to set mtu during resetting");
 617                 return -EIO;
 618         }
 619
 620         /*
 621          * when Rx of scattered packets is off, we have some possibility of
 622          * using vector Rx process function or simple Rx functions in hns3 PMD
 623          * driver. If the input MTU is increased and the maximum length of
 624          * received packets is greater than the length of a buffer for Rx
 625          * packet, the hardware network engine needs to use multiple BDs and
 626          * buffers to store these packets. This will cause problems when still
 627          * using vector Rx process function or simple Rx function to receiving
 628          * packets. So, when Rx of scattered packets is off and device is
 629          * started, it is not permitted to increase MTU so that the maximum
 630          * length of Rx packets is greater than Rx buffer length.
 631          */
 632         if (dev->data->dev_started && !dev->data->scattered_rx &&
 633             frame_size > hw->rx_buf_len) {
 634                 hns3_err(hw, "failed to set mtu because current is "
 635                         "not scattered rx mode");
 636                 return -EOPNOTSUPP;
 637         }
 638
 639         rte_spinlock_lock(&hw->lock);
 640         ret = hns3vf_config_mtu(hw, mtu);
 641         if (ret) {
 642                 rte_spinlock_unlock(&hw->lock);
 643                 return ret;
 644         }
 645         rte_spinlock_unlock(&hw->lock);
 646
 647         return 0;
 648 }
 649
 650 static int
 651 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 652 {
 653         struct hns3_adapter *hns = eth_dev->data->dev_private;
 654         struct hns3_hw *hw = &hns->hw;
 655         uint16_t q_num = hw->tqps_num;
 656
 657         /*
 658          * In interrupt mode, 'max_rx_queues' is set based on the number of
 659          * MSI-X interrupt resources of the hardware.
 660          */
 661         if (hw->data->dev_conf.intr_conf.rxq == 1)
 662                 q_num = hw->intr_tqps_num;
 663
 664         info->max_rx_queues = q_num;
 665         info->max_tx_queues = hw->tqps_num;
 666         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 667         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 668         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 669         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 670         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 671
 672         info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
 673                                  RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
 674                                  RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
 675                                  RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
 676                                  RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 677                                  RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
 678                                  RTE_ETH_RX_OFFLOAD_SCATTER |
 679                                  RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
 680                                  RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
 681                                  RTE_ETH_RX_OFFLOAD_RSS_HASH |
 682                                  RTE_ETH_RX_OFFLOAD_TCP_LRO);
 683         info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 684                                  RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
 685                                  RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
 686                                  RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
 687                                  RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
 688                                  RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
 689                                  RTE_ETH_TX_OFFLOAD_TCP_TSO |
 690                                  RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
 691                                  RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
 692                                  RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
 693                                  RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
 694                                  hns3_txvlan_cap_get(hw));
 695
 696         if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
 697                 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
 698
 699         if (hns3_dev_get_support(hw, INDEP_TXRX))
 700                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 701                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 702         info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 703
 704         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 705                 .nb_max = HNS3_MAX_RING_DESC,
 706                 .nb_min = HNS3_MIN_RING_DESC,
 707                 .nb_align = HNS3_ALIGN_RING_DESC,
 708         };
 709
 710         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 711                 .nb_max = HNS3_MAX_RING_DESC,
 712                 .nb_min = HNS3_MIN_RING_DESC,
 713                 .nb_align = HNS3_ALIGN_RING_DESC,
 714                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 715                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
 716         };
 717
 718         info->default_rxconf = (struct rte_eth_rxconf) {
 719                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 720                 /*
 721                  * If there are no available Rx buffer descriptors, incoming
 722                  * packets are always dropped by hardware based on hns3 network
 723                  * engine.
 724                  */
 725                 .rx_drop_en = 1,
 726                 .offloads = 0,
 727         };
 728         info->default_txconf = (struct rte_eth_txconf) {
 729                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 730                 .offloads = 0,
 731         };
 732
 733         info->reta_size = hw->rss_ind_tbl_size;
 734         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 735         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 736
 737         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
 738         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
 739         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
 740         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
 741         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 742         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 743
 744         return 0;
 745 }
 746
 747 static void
 748 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 749 {
 750         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 751 }
 752
 753 static void
 754 hns3vf_disable_irq0(struct hns3_hw *hw)
 755 {
 756         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 757 }
 758
 759 static void
 760 hns3vf_enable_irq0(struct hns3_hw *hw)
 761 {
 762         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 763 }
 764
 765 static enum hns3vf_evt_cause
 766 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 767 {
 768         struct hns3_hw *hw = &hns->hw;
 769         enum hns3vf_evt_cause ret;
 770         uint32_t cmdq_stat_reg;
 771         uint32_t rst_ing_reg;
 772         uint32_t val;
 773
 774         /* Fetch the events from their corresponding regs */
 775         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 776         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 777                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 778                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 779                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 780                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 781                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 782                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 783                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
 784                 if (clearval) {
 785                         hw->reset.stats.global_cnt++;
 786                         hns3_warn(hw, "Global reset detected, clear reset status");
 787                 } else {
 788                         hns3_schedule_delayed_reset(hns);
 789                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 790                 }
 791
 792                 ret = HNS3VF_VECTOR0_EVENT_RST;
 793                 goto out;
 794         }
 795
 796         /* Check for vector0 mailbox(=CMDQ RX) event source */
 797         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
 798                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 799                 ret = HNS3VF_VECTOR0_EVENT_MBX;
 800                 goto out;
 801         }
 802
 803         val = 0;
 804         ret = HNS3VF_VECTOR0_EVENT_OTHER;
 805 out:
 806         if (clearval)
 807                 *clearval = val;
 808         return ret;
 809 }
 810
 811 static void
 812 hns3vf_interrupt_handler(void *param)
 813 {
 814         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 815         struct hns3_adapter *hns = dev->data->dev_private;
 816         struct hns3_hw *hw = &hns->hw;
 817         enum hns3vf_evt_cause event_cause;
 818         uint32_t clearval;
 819
 820         /* Disable interrupt */
 821         hns3vf_disable_irq0(hw);
 822
 823         /* Read out interrupt causes */
 824         event_cause = hns3vf_check_event_cause(hns, &clearval);
 825         /* Clear interrupt causes */
 826         hns3vf_clear_event_cause(hw, clearval);
 827
 828         switch (event_cause) {
 829         case HNS3VF_VECTOR0_EVENT_RST:
 830                 hns3_schedule_reset(hns);
 831                 break;
 832         case HNS3VF_VECTOR0_EVENT_MBX:
 833                 hns3_dev_handle_mbx_msg(hw);
 834                 break;
 835         default:
 836                 break;
 837         }
 838
 839         /* Enable interrupt */
 840         hns3vf_enable_irq0(hw);
 841 }
 842
 843 static void
 844 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
 845 {
 846         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
 847         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
 848         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
 849         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
 850 }
 851
 852 static void
 853 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
 854 {
 855         struct hns3_dev_specs_0_cmd *req0;
 856
 857         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
 858
 859         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
 860         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
 861         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
 862         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
 863 }
 864
 865 static int
 866 hns3vf_check_dev_specifications(struct hns3_hw *hw)
 867 {
 868         if (hw->rss_ind_tbl_size == 0 ||
 869             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
 870                 hns3_warn(hw, "the size of hash lookup table configured (%u)"
 871                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
 872                               HNS3_RSS_IND_TBL_SIZE_MAX);
 873                 return -EINVAL;
 874         }
 875
 876         return 0;
 877 }
 878
 879 static int
 880 hns3vf_query_dev_specifications(struct hns3_hw *hw)
 881 {
 882         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
 883         int ret;
 884         int i;
 885
 886         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
 887                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
 888                                           true);
 889                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 890         }
 891         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
 892
 893         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
 894         if (ret)
 895                 return ret;
 896
 897         hns3vf_parse_dev_specifications(hw, desc);
 898
 899         return hns3vf_check_dev_specifications(hw);
 900 }
 901
 902 void
 903 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
 904 {
 905         uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
 906                                    HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
 907         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
 908         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
 909
 910         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
 911                 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
 912                                           __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
 913 }
 914
 915 static void
 916 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
 917 {
 918 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS      500
 919
 920         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
 921         int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
 922         uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
 923         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
 924         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
 925
 926         __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
 927                          __ATOMIC_RELEASE);
 928
 929         (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
 930                                 NULL, 0);
 931
 932         while (remain_ms > 0) {
 933                 rte_delay_ms(HNS3_POLL_RESPONE_MS);
 934                 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
 935                         HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
 936                         break;
 937                 remain_ms--;
 938         }
 939
 940         /*
 941          * When exit above loop, the pf_push_lsc_cap could be one of the three
 942          * state: unknown (means pf not ack), not_supported, supported.
 943          * Here config it as 'not_supported' when it's 'unknown' state.
 944          */
 945         __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
 946                                   __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
 947
 948         if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
 949                 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
 950                 hns3_info(hw, "detect PF support push link status change!");
 951         } else {
 952                 /*
 953                  * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
 954                  * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
 955                  * the RTE_ETH_DEV_INTR_LSC capability.
 956                  */
 957                 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
 958         }
 959 }
 960
 961 static int
 962 hns3vf_get_capability(struct hns3_hw *hw)
 963 {
 964         struct rte_pci_device *pci_dev;
 965         struct rte_eth_dev *eth_dev;
 966         uint8_t revision;
 967         int ret;
 968
 969         eth_dev = &rte_eth_devices[hw->data->port_id];
 970         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 971
 972         /* Get PCI revision id */
 973         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
 974                                   HNS3_PCI_REVISION_ID);
 975         if (ret != HNS3_PCI_REVISION_ID_LEN) {
 976                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
 977                              ret);
 978                 return -EIO;
 979         }
 980         hw->revision = revision;
 981
 982         if (revision < PCI_REVISION_ID_HIP09_A) {
 983                 hns3vf_set_default_dev_specifications(hw);
 984                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
 985                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
 986                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
 987                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
 988                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
 989                 hw->rss_info.ipv6_sctp_offload_supported = false;
 990                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
 991                 return 0;
 992         }
 993
 994         ret = hns3vf_query_dev_specifications(hw);
 995         if (ret) {
 996                 PMD_INIT_LOG(ERR,
 997                              "failed to query dev specifications, ret = %d",
 998                              ret);
 999                 return ret;
1000         }
1001
1002         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1003         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1004         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1005         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1006         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1007         hw->rss_info.ipv6_sctp_offload_supported = true;
1008         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1009
1010         return 0;
1011 }
1012
1013 static int
1014 hns3vf_check_tqp_info(struct hns3_hw *hw)
1015 {
1016         if (hw->tqps_num == 0) {
1017                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1018                 return -EINVAL;
1019         }
1020
1021         if (hw->rss_size_max == 0) {
1022                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1023                 return -EINVAL;
1024         }
1025
1026         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1027
1028         return 0;
1029 }
1030
1031 static int
1032 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1033 {
1034         uint8_t resp_msg;
1035         int ret;
1036
1037         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1038                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1039                                 true, &resp_msg, sizeof(resp_msg));
1040         if (ret) {
1041                 if (ret == -ETIME) {
1042                         /*
1043                          * Getting current port based VLAN state from PF driver
1044                          * will not affect VF driver's basic function. Because
1045                          * the VF driver relies on hns3 PF kernel ether driver,
1046                          * to avoid introducing compatibility issues with older
1047                          * version of PF driver, no failure will be returned
1048                          * when the return value is ETIME. This return value has
1049                          * the following scenarios:
1050                          * 1) Firmware didn't return the results in time
1051                          * 2) the result return by firmware is timeout
1052                          * 3) the older version of kernel side PF driver does
1053                          *    not support this mailbox message.
1054                          * For scenarios 1 and 2, it is most likely that a
1055                          * hardware error has occurred, or a hardware reset has
1056                          * occurred. In this case, these errors will be caught
1057                          * by other functions.
1058                          */
1059                         PMD_INIT_LOG(WARNING,
1060                                 "failed to get PVID state for timeout, maybe "
1061                                 "kernel side PF driver doesn't support this "
1062                                 "mailbox message, or firmware didn't respond.");
1063                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1064                 } else {
1065                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1066                                 " ret = %d", ret);
1067                         return ret;
1068                 }
1069         }
1070         hw->port_base_vlan_cfg.state = resp_msg ?
1071                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1072         return 0;
1073 }
1074
1075 static int
1076 hns3vf_get_queue_info(struct hns3_hw *hw)
1077 {
1078 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1079         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1080         int ret;
1081
1082         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1083                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1084         if (ret) {
1085                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1086                 return ret;
1087         }
1088
1089         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1090         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1091
1092         return hns3vf_check_tqp_info(hw);
1093 }
1094
1095 static int
1096 hns3vf_get_queue_depth(struct hns3_hw *hw)
1097 {
1098 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1099         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1100         int ret;
1101
1102         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1103                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1104         if (ret) {
1105                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1106                              ret);
1107                 return ret;
1108         }
1109
1110         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1111         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1112
1113         return 0;
1114 }
1115
1116 static void
1117 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
1118 {
1119         if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
1120                 hns3_set_bit(hw->capability,
1121                                 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
1122 }
1123
1124 static int
1125 hns3vf_get_num_tc(struct hns3_hw *hw)
1126 {
1127         uint8_t num_tc = 0;
1128         uint32_t i;
1129
1130         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1131                 if (hw->hw_tc_map & BIT(i))
1132                         num_tc++;
1133         }
1134         return num_tc;
1135 }
1136
1137 static int
1138 hns3vf_get_basic_info(struct hns3_hw *hw)
1139 {
1140         uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
1141         struct hns3_basic_info *basic_info;
1142         int ret;
1143
1144         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
1145                                 true, resp_msg, sizeof(resp_msg));
1146         if (ret) {
1147                 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
1148                                 ret);
1149                 return ret;
1150         }
1151
1152         basic_info = (struct hns3_basic_info *)resp_msg;
1153         hw->hw_tc_map = basic_info->hw_tc_map;
1154         hw->num_tc = hns3vf_get_num_tc(hw);
1155         hw->pf_vf_if_version = basic_info->pf_vf_if_version;
1156         hns3vf_update_caps(hw, basic_info->caps);
1157
1158         return 0;
1159 }
1160
1161 static int
1162 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1163 {
1164         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1165         int ret;
1166
1167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1168                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1169         if (ret) {
1170                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1171                 return ret;
1172         }
1173
1174         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1175
1176         return 0;
1177 }
1178
1179 static int
1180 hns3vf_get_configuration(struct hns3_hw *hw)
1181 {
1182         int ret;
1183
1184         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1185         hw->rss_dis_flag = false;
1186
1187         /* Get device capability */
1188         ret = hns3vf_get_capability(hw);
1189         if (ret) {
1190                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1191                 return ret;
1192         }
1193
1194         hns3vf_get_push_lsc_cap(hw);
1195
1196         /* Get basic info from PF */
1197         ret = hns3vf_get_basic_info(hw);
1198         if (ret)
1199                 return ret;
1200
1201         /* Get queue configuration from PF */
1202         ret = hns3vf_get_queue_info(hw);
1203         if (ret)
1204                 return ret;
1205
1206         /* Get queue depth info from PF */
1207         ret = hns3vf_get_queue_depth(hw);
1208         if (ret)
1209                 return ret;
1210
1211         /* Get user defined VF MAC addr from PF */
1212         ret = hns3vf_get_host_mac_addr(hw);
1213         if (ret)
1214                 return ret;
1215
1216         return hns3vf_get_port_base_vlan_filter_state(hw);
1217 }
1218
1219 static int
1220 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1221                             uint16_t nb_tx_q)
1222 {
1223         struct hns3_hw *hw = &hns->hw;
1224
1225         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1226 }
1227
1228 static void
1229 hns3vf_request_link_info(struct hns3_hw *hw)
1230 {
1231         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1232         bool send_req;
1233         int ret;
1234
1235         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1236                 return;
1237
1238         send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1239                    vf->req_link_info_cnt > 0;
1240         if (!send_req)
1241                 return;
1242
1243         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1244                                 NULL, 0);
1245         if (ret) {
1246                 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1247                 return;
1248         }
1249
1250         if (vf->req_link_info_cnt > 0)
1251                 vf->req_link_info_cnt--;
1252 }
1253
1254 void
1255 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1256                           uint32_t link_speed, uint8_t link_duplex)
1257 {
1258         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1259         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1260         struct hns3_mac *mac = &hw->mac;
1261         int ret;
1262
1263         /*
1264          * PF kernel driver may push link status when VF driver is in resetting,
1265          * driver will stop polling job in this case, after resetting done
1266          * driver will start polling job again.
1267          * When polling job started, driver will get initial link status by
1268          * sending request to PF kernel driver, then could update link status by
1269          * process PF kernel driver's link status mailbox message.
1270          */
1271         if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1272                 return;
1273
1274         if (hw->adapter_state != HNS3_NIC_STARTED)
1275                 return;
1276
1277         mac->link_status = link_status;
1278         mac->link_speed = link_speed;
1279         mac->link_duplex = link_duplex;
1280         ret = hns3vf_dev_link_update(dev, 0);
1281         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1282                 hns3_start_report_lse(dev);
1283 }
1284
1285 static int
1286 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1287 {
1288 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1289         struct hns3_hw *hw = &hns->hw;
1290         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1291         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1292         uint8_t is_kill = on ? 0 : 1;
1293
1294         msg_data[0] = is_kill;
1295         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1296         memcpy(&msg_data[3], &proto, sizeof(proto));
1297
1298         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1299                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1300                                  0);
1301 }
1302
1303 static int
1304 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1305 {
1306         struct hns3_adapter *hns = dev->data->dev_private;
1307         struct hns3_hw *hw = &hns->hw;
1308         int ret;
1309
1310         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1311                 hns3_err(hw,
1312                          "vf set vlan id failed during resetting, vlan_id =%u",
1313                          vlan_id);
1314                 return -EIO;
1315         }
1316         rte_spinlock_lock(&hw->lock);
1317         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1318         rte_spinlock_unlock(&hw->lock);
1319         if (ret)
1320                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1321                          vlan_id, ret);
1322
1323         return ret;
1324 }
1325
1326 static int
1327 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1328 {
1329         uint8_t msg_data;
1330         int ret;
1331
1332         if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1333                 return 0;
1334
1335         msg_data = enable ? 1 : 0;
1336         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1337                         HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1338                         sizeof(msg_data), true, NULL, 0);
1339         if (ret)
1340                 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1341                                 enable ? "enable" : "disable", ret);
1342
1343         return ret;
1344 }
1345
1346 static int
1347 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1348 {
1349         uint8_t msg_data;
1350         int ret;
1351
1352         msg_data = enable ? 1 : 0;
1353         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1354                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1355         if (ret)
1356                 hns3_err(hw, "vf %s strip failed, ret = %d.",
1357                                 enable ? "enable" : "disable", ret);
1358
1359         return ret;
1360 }
1361
1362 static int
1363 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1364 {
1365         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1366         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1367         unsigned int tmp_mask;
1368         int ret = 0;
1369
1370         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1371                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1372                              "mask = 0x%x", mask);
1373                 return -EIO;
1374         }
1375
1376         tmp_mask = (unsigned int)mask;
1377
1378         if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
1379                 rte_spinlock_lock(&hw->lock);
1380                 /* Enable or disable VLAN filter */
1381                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1382                         ret = hns3vf_en_vlan_filter(hw, true);
1383                 else
1384                         ret = hns3vf_en_vlan_filter(hw, false);
1385                 rte_spinlock_unlock(&hw->lock);
1386                 if (ret)
1387                         return ret;
1388         }
1389
1390         /* Vlan stripping setting */
1391         if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
1392                 rte_spinlock_lock(&hw->lock);
1393                 /* Enable or disable VLAN stripping */
1394                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1395                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1396                 else
1397                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1398                 rte_spinlock_unlock(&hw->lock);
1399         }
1400
1401         return ret;
1402 }
1403
1404 static int
1405 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1406 {
1407         struct rte_vlan_filter_conf *vfc;
1408         struct hns3_hw *hw = &hns->hw;
1409         uint16_t vlan_id;
1410         uint64_t vbit;
1411         uint64_t ids;
1412         int ret = 0;
1413         uint32_t i;
1414
1415         vfc = &hw->data->vlan_filter_conf;
1416         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1417                 if (vfc->ids[i] == 0)
1418                         continue;
1419                 ids = vfc->ids[i];
1420                 while (ids) {
1421                         /*
1422                          * 64 means the num bits of ids, one bit corresponds to
1423                          * one vlan id
1424                          */
1425                         vlan_id = 64 * i;
1426                         /* count trailing zeroes */
1427                         vbit = ~ids & (ids - 1);
1428                         /* clear least significant bit set */
1429                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1430                         for (; vbit;) {
1431                                 vbit >>= 1;
1432                                 vlan_id++;
1433                         }
1434                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1435                         if (ret) {
1436                                 hns3_err(hw,
1437                                          "VF handle vlan table failed, ret =%d, on = %d",
1438                                          ret, on);
1439                                 return ret;
1440                         }
1441                 }
1442         }
1443
1444         return ret;
1445 }
1446
1447 static int
1448 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1449 {
1450         return hns3vf_handle_all_vlan_table(hns, 0);
1451 }
1452
1453 static int
1454 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1455 {
1456         struct hns3_hw *hw = &hns->hw;
1457         struct rte_eth_conf *dev_conf;
1458         bool en;
1459         int ret;
1460
1461         dev_conf = &hw->data->dev_conf;
1462         en = dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? true
1463                                                                    : false;
1464         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1465         if (ret)
1466                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1467                          ret);
1468         return ret;
1469 }
1470
1471 static int
1472 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1473 {
1474         struct hns3_adapter *hns = dev->data->dev_private;
1475         struct rte_eth_dev_data *data = dev->data;
1476         struct hns3_hw *hw = &hns->hw;
1477         int ret;
1478
1479         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1480             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1481             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1482                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1483                               "or hw_vlan_insert_pvid is not support!");
1484         }
1485
1486         /* Apply vlan offload setting */
1487         ret = hns3vf_vlan_offload_set(dev, RTE_ETH_VLAN_STRIP_MASK |
1488                                         RTE_ETH_VLAN_FILTER_MASK);
1489         if (ret)
1490                 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1491
1492         return ret;
1493 }
1494
1495 static int
1496 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1497 {
1498         uint8_t msg_data;
1499
1500         msg_data = alive ? 1 : 0;
1501         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1502                                  sizeof(msg_data), false, NULL, 0);
1503 }
1504
1505 static void
1506 hns3vf_keep_alive_handler(void *param)
1507 {
1508         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1509         struct hns3_adapter *hns = eth_dev->data->dev_private;
1510         struct hns3_hw *hw = &hns->hw;
1511         int ret;
1512
1513         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1514                                 false, NULL, 0);
1515         if (ret)
1516                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1517                          ret);
1518
1519         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1520                           eth_dev);
1521 }
1522
1523 static void
1524 hns3vf_service_handler(void *param)
1525 {
1526         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1527         struct hns3_adapter *hns = eth_dev->data->dev_private;
1528         struct hns3_hw *hw = &hns->hw;
1529
1530         /*
1531          * The query link status and reset processing are executed in the
1532          * interrupt thread. When the IMP reset occurs, IMP will not respond,
1533          * and the query operation will timeout after 30ms. In the case of
1534          * multiple PF/VFs, each query failure timeout causes the IMP reset
1535          * interrupt to fail to respond within 100ms.
1536          * Before querying the link status, check whether there is a reset
1537          * pending, and if so, abandon the query.
1538          */
1539         if (!hns3vf_is_reset_pending(hns))
1540                 hns3vf_request_link_info(hw);
1541         else
1542                 hns3_warn(hw, "Cancel the query when reset is pending");
1543
1544         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1545                           eth_dev);
1546 }
1547
1548 static void
1549 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1550 {
1551 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT      3
1552
1553         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1554
1555         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1556                 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1557
1558         __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1559
1560         hns3vf_service_handler(dev);
1561 }
1562
1563 static void
1564 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1565 {
1566         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1567
1568         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1569
1570         __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1571 }
1572
1573 static int
1574 hns3_query_vf_resource(struct hns3_hw *hw)
1575 {
1576         struct hns3_vf_res_cmd *req;
1577         struct hns3_cmd_desc desc;
1578         uint16_t num_msi;
1579         int ret;
1580
1581         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1582         ret = hns3_cmd_send(hw, &desc, 1);
1583         if (ret) {
1584                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1585                 return ret;
1586         }
1587
1588         req = (struct hns3_vf_res_cmd *)desc.data;
1589         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1590                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1591         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1592                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1593                          num_msi, HNS3_MIN_VECTOR_NUM);
1594                 return -EINVAL;
1595         }
1596
1597         hw->num_msi = num_msi;
1598
1599         return 0;
1600 }
1601
1602 static int
1603 hns3vf_init_hardware(struct hns3_adapter *hns)
1604 {
1605         struct hns3_hw *hw = &hns->hw;
1606         uint16_t mtu = hw->data->mtu;
1607         int ret;
1608
1609         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1610         if (ret)
1611                 return ret;
1612
1613         ret = hns3vf_config_mtu(hw, mtu);
1614         if (ret)
1615                 goto err_init_hardware;
1616
1617         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1618         if (ret) {
1619                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1620                 goto err_init_hardware;
1621         }
1622
1623         ret = hns3_config_gro(hw, false);
1624         if (ret) {
1625                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1626                 goto err_init_hardware;
1627         }
1628
1629         /*
1630          * In the initialization clearing the all hardware mapping relationship
1631          * configurations between queues and interrupt vectors is needed, so
1632          * some error caused by the residual configurations, such as the
1633          * unexpected interrupt, can be avoid.
1634          */
1635         ret = hns3vf_init_ring_with_vector(hw);
1636         if (ret) {
1637                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1638                 goto err_init_hardware;
1639         }
1640
1641         return 0;
1642
1643 err_init_hardware:
1644         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1645         return ret;
1646 }
1647
1648 static int
1649 hns3vf_clear_vport_list(struct hns3_hw *hw)
1650 {
1651         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1652                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1653                                  NULL, 0);
1654 }
1655
1656 static int
1657 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1658 {
1659         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1660         struct hns3_adapter *hns = eth_dev->data->dev_private;
1661         struct hns3_hw *hw = &hns->hw;
1662         int ret;
1663
1664         PMD_INIT_FUNC_TRACE();
1665
1666         /* Get hardware io base address from pcie BAR2 IO space */
1667         hw->io_base = pci_dev->mem_resource[2].addr;
1668
1669         /* Firmware command queue initialize */
1670         ret = hns3_cmd_init_queue(hw);
1671         if (ret) {
1672                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1673                 goto err_cmd_init_queue;
1674         }
1675
1676         /* Firmware command initialize */
1677         ret = hns3_cmd_init(hw);
1678         if (ret) {
1679                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1680                 goto err_cmd_init;
1681         }
1682
1683         hns3_tx_push_init(eth_dev);
1684
1685         /* Get VF resource */
1686         ret = hns3_query_vf_resource(hw);
1687         if (ret)
1688                 goto err_cmd_init;
1689
1690         rte_spinlock_init(&hw->mbx_resp.lock);
1691
1692         hns3vf_clear_event_cause(hw, 0);
1693
1694         ret = rte_intr_callback_register(pci_dev->intr_handle,
1695                                          hns3vf_interrupt_handler, eth_dev);
1696         if (ret) {
1697                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1698                 goto err_intr_callback_register;
1699         }
1700
1701         /* Enable interrupt */
1702         rte_intr_enable(pci_dev->intr_handle);
1703         hns3vf_enable_irq0(hw);
1704
1705         /* Get configuration from PF */
1706         ret = hns3vf_get_configuration(hw);
1707         if (ret) {
1708                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1709                 goto err_get_config;
1710         }
1711
1712         ret = hns3_tqp_stats_init(hw);
1713         if (ret)
1714                 goto err_get_config;
1715
1716         /* Hardware statistics of imissed registers cleared. */
1717         ret = hns3_update_imissed_stats(hw, true);
1718         if (ret) {
1719                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1720                 goto err_set_tc_queue;
1721         }
1722
1723         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1724         if (ret) {
1725                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1726                 goto err_set_tc_queue;
1727         }
1728
1729         ret = hns3vf_clear_vport_list(hw);
1730         if (ret) {
1731                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1732                 goto err_set_tc_queue;
1733         }
1734
1735         ret = hns3vf_init_hardware(hns);
1736         if (ret)
1737                 goto err_set_tc_queue;
1738
1739         hns3_rss_set_default_args(hw);
1740
1741         ret = hns3vf_set_alive(hw, true);
1742         if (ret) {
1743                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1744                 goto err_set_tc_queue;
1745         }
1746
1747         return 0;
1748
1749 err_set_tc_queue:
1750         hns3_tqp_stats_uninit(hw);
1751
1752 err_get_config:
1753         hns3vf_disable_irq0(hw);
1754         rte_intr_disable(pci_dev->intr_handle);
1755         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1756                              eth_dev);
1757 err_intr_callback_register:
1758 err_cmd_init:
1759         hns3_cmd_uninit(hw);
1760         hns3_cmd_destroy_queue(hw);
1761 err_cmd_init_queue:
1762         hw->io_base = NULL;
1763
1764         return ret;
1765 }
1766
1767 static void
1768 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1769 {
1770         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1771         struct hns3_adapter *hns = eth_dev->data->dev_private;
1772         struct hns3_hw *hw = &hns->hw;
1773
1774         PMD_INIT_FUNC_TRACE();
1775
1776         hns3_rss_uninit(hns);
1777         (void)hns3_config_gro(hw, false);
1778         (void)hns3vf_set_alive(hw, false);
1779         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1780         hns3_flow_uninit(eth_dev);
1781         hns3_tqp_stats_uninit(hw);
1782         hns3vf_disable_irq0(hw);
1783         rte_intr_disable(pci_dev->intr_handle);
1784         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1785                              eth_dev);
1786         hns3_cmd_uninit(hw);
1787         hns3_cmd_destroy_queue(hw);
1788         hw->io_base = NULL;
1789 }
1790
1791 static int
1792 hns3vf_do_stop(struct hns3_adapter *hns)
1793 {
1794         struct hns3_hw *hw = &hns->hw;
1795         int ret;
1796
1797         hw->mac.link_status = RTE_ETH_LINK_DOWN;
1798
1799         /*
1800          * The "hns3vf_do_stop" function will also be called by .stop_service to
1801          * prepare reset. At the time of global or IMP reset, the command cannot
1802          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
1803          * accessed during the reset process. So the mbuf can not be released
1804          * during reset and is required to be released after the reset is
1805          * completed.
1806          */
1807         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
1808                 hns3_dev_release_mbufs(hns);
1809
1810         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
1811                 hns3_configure_all_mac_addr(hns, true);
1812                 ret = hns3_reset_all_tqps(hns);
1813                 if (ret) {
1814                         hns3_err(hw, "failed to reset all queues ret = %d",
1815                                  ret);
1816                         return ret;
1817                 }
1818         }
1819         return 0;
1820 }
1821
1822 static void
1823 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1824 {
1825         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1826         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1827         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1828         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1829         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1830         uint16_t q_id;
1831
1832         if (dev->data->dev_conf.intr_conf.rxq == 0)
1833                 return;
1834
1835         /* unmap the ring with vector */
1836         if (rte_intr_allow_others(intr_handle)) {
1837                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1838                 base = RTE_INTR_VEC_RXTX_OFFSET;
1839         }
1840         if (rte_intr_dp_is_en(intr_handle)) {
1841                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1842                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1843                                                            HNS3_RING_TYPE_RX,
1844                                                            q_id);
1845                         if (vec < base + rte_intr_nb_efd_get(intr_handle)
1846                             - 1)
1847                                 vec++;
1848                 }
1849         }
1850         /* Clean datapath event and queue/vec mapping */
1851         rte_intr_efd_disable(intr_handle);
1852
1853         /* Cleanup vector list */
1854         rte_intr_vec_list_free(intr_handle);
1855 }
1856
1857 static int
1858 hns3vf_dev_stop(struct rte_eth_dev *dev)
1859 {
1860         struct hns3_adapter *hns = dev->data->dev_private;
1861         struct hns3_hw *hw = &hns->hw;
1862
1863         PMD_INIT_FUNC_TRACE();
1864         dev->data->dev_started = 0;
1865
1866         hw->adapter_state = HNS3_NIC_STOPPING;
1867         hns3_set_rxtx_function(dev);
1868         rte_wmb();
1869         /* Disable datapath on secondary process. */
1870         hns3_mp_req_stop_rxtx(dev);
1871         /* Prevent crashes when queues are still in use. */
1872         rte_delay_ms(hw->cfg_max_queues);
1873
1874         rte_spinlock_lock(&hw->lock);
1875         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1876                 hns3_stop_tqps(hw);
1877                 hns3vf_do_stop(hns);
1878                 hns3vf_unmap_rx_interrupt(dev);
1879                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1880         }
1881         hns3_rx_scattered_reset(dev);
1882         hns3vf_stop_poll_job(dev);
1883         hns3_stop_report_lse(dev);
1884         rte_spinlock_unlock(&hw->lock);
1885
1886         return 0;
1887 }
1888
1889 static int
1890 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1891 {
1892         struct hns3_adapter *hns = eth_dev->data->dev_private;
1893         struct hns3_hw *hw = &hns->hw;
1894         int ret = 0;
1895
1896         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1897                 return 0;
1898
1899         if (hw->adapter_state == HNS3_NIC_STARTED)
1900                 ret = hns3vf_dev_stop(eth_dev);
1901
1902         hw->adapter_state = HNS3_NIC_CLOSING;
1903         hns3_reset_abort(hns);
1904         hw->adapter_state = HNS3_NIC_CLOSED;
1905         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1906         hns3_configure_all_mc_mac_addr(hns, true);
1907         hns3vf_remove_all_vlan_table(hns);
1908         hns3vf_uninit_vf(eth_dev);
1909         hns3_free_all_queues(eth_dev);
1910         rte_free(hw->reset.wait_data);
1911         hns3_mp_uninit_primary();
1912         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
1913
1914         return ret;
1915 }
1916
1917 static int
1918 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1919                       size_t fw_size)
1920 {
1921         struct hns3_adapter *hns = eth_dev->data->dev_private;
1922         struct hns3_hw *hw = &hns->hw;
1923         uint32_t version = hw->fw_version;
1924         int ret;
1925
1926         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1927                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1928                                       HNS3_FW_VERSION_BYTE3_S),
1929                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1930                                       HNS3_FW_VERSION_BYTE2_S),
1931                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1932                                       HNS3_FW_VERSION_BYTE1_S),
1933                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1934                                       HNS3_FW_VERSION_BYTE0_S));
1935         if (ret < 0)
1936                 return -EINVAL;
1937
1938         ret += 1; /* add the size of '\0' */
1939         if (fw_size < (size_t)ret)
1940                 return ret;
1941         else
1942                 return 0;
1943 }
1944
1945 static int
1946 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1947                        __rte_unused int wait_to_complete)
1948 {
1949         struct hns3_adapter *hns = eth_dev->data->dev_private;
1950         struct hns3_hw *hw = &hns->hw;
1951         struct hns3_mac *mac = &hw->mac;
1952         struct rte_eth_link new_link;
1953
1954         memset(&new_link, 0, sizeof(new_link));
1955         switch (mac->link_speed) {
1956         case RTE_ETH_SPEED_NUM_10M:
1957         case RTE_ETH_SPEED_NUM_100M:
1958         case RTE_ETH_SPEED_NUM_1G:
1959         case RTE_ETH_SPEED_NUM_10G:
1960         case RTE_ETH_SPEED_NUM_25G:
1961         case RTE_ETH_SPEED_NUM_40G:
1962         case RTE_ETH_SPEED_NUM_50G:
1963         case RTE_ETH_SPEED_NUM_100G:
1964         case RTE_ETH_SPEED_NUM_200G:
1965                 if (mac->link_status)
1966                         new_link.link_speed = mac->link_speed;
1967                 break;
1968         default:
1969                 if (mac->link_status)
1970                         new_link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
1971                 break;
1972         }
1973
1974         if (!mac->link_status)
1975                 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
1976
1977         new_link.link_duplex = mac->link_duplex;
1978         new_link.link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
1979         new_link.link_autoneg =
1980             !(eth_dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED);
1981
1982         return rte_eth_linkstatus_set(eth_dev, &new_link);
1983 }
1984
1985 static int
1986 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1987 {
1988         struct hns3_hw *hw = &hns->hw;
1989         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1990         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1991         int ret;
1992
1993         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
1994         if (ret)
1995                 return ret;
1996
1997         hns3_enable_rxd_adv_layout(hw);
1998
1999         ret = hns3_init_queues(hns, reset_queue);
2000         if (ret)
2001                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2002
2003         return ret;
2004 }
2005
2006 static int
2007 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2008 {
2009         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2010         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2011         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2012         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2013         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2014         uint32_t intr_vector;
2015         uint16_t q_id;
2016         int ret;
2017
2018         /*
2019          * hns3 needs a separate interrupt to be used as event interrupt which
2020          * could not be shared with task queue pair, so KERNEL drivers need
2021          * support multiple interrupt vectors.
2022          */
2023         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2024             !rte_intr_cap_multiple(intr_handle))
2025                 return 0;
2026
2027         rte_intr_disable(intr_handle);
2028         intr_vector = hw->used_rx_queues;
2029         /* It creates event fd for each intr vector when MSIX is used */
2030         if (rte_intr_efd_enable(intr_handle, intr_vector))
2031                 return -EINVAL;
2032
2033         /* Allocate vector list */
2034         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
2035                                     hw->used_rx_queues)) {
2036                 hns3_err(hw, "Failed to allocate %u rx_queues"
2037                          " intr_vec", hw->used_rx_queues);
2038                 ret = -ENOMEM;
2039                 goto vf_alloc_intr_vec_error;
2040         }
2041
2042         if (rte_intr_allow_others(intr_handle)) {
2043                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2044                 base = RTE_INTR_VEC_RXTX_OFFSET;
2045         }
2046
2047         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2048                 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2049                                                    HNS3_RING_TYPE_RX, q_id);
2050                 if (ret)
2051                         goto vf_bind_vector_error;
2052
2053                 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
2054                         goto vf_bind_vector_error;
2055
2056                 /*
2057                  * If there are not enough efds (e.g. not enough interrupt),
2058                  * remaining queues will be bond to the last interrupt.
2059                  */
2060                 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
2061                         vec++;
2062         }
2063         rte_intr_enable(intr_handle);
2064         return 0;
2065
2066 vf_bind_vector_error:
2067         rte_intr_vec_list_free(intr_handle);
2068 vf_alloc_intr_vec_error:
2069         rte_intr_efd_disable(intr_handle);
2070         return ret;
2071 }
2072
2073 static int
2074 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2075 {
2076         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2077         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2078         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2079         uint16_t q_id;
2080         int ret;
2081
2082         if (dev->data->dev_conf.intr_conf.rxq == 0)
2083                 return 0;
2084
2085         if (rte_intr_dp_is_en(intr_handle)) {
2086                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2087                         ret = hns3vf_bind_ring_with_vector(hw,
2088                                 rte_intr_vec_list_index_get(intr_handle,
2089                                                                    q_id),
2090                                 true, HNS3_RING_TYPE_RX, q_id);
2091                         if (ret)
2092                                 return ret;
2093                 }
2094         }
2095
2096         return 0;
2097 }
2098
2099 static void
2100 hns3vf_restore_filter(struct rte_eth_dev *dev)
2101 {
2102         hns3_restore_rss_filter(dev);
2103 }
2104
2105 static int
2106 hns3vf_dev_start(struct rte_eth_dev *dev)
2107 {
2108         struct hns3_adapter *hns = dev->data->dev_private;
2109         struct hns3_hw *hw = &hns->hw;
2110         int ret;
2111
2112         PMD_INIT_FUNC_TRACE();
2113         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2114                 return -EBUSY;
2115
2116         rte_spinlock_lock(&hw->lock);
2117         hw->adapter_state = HNS3_NIC_STARTING;
2118         ret = hns3vf_do_start(hns, true);
2119         if (ret) {
2120                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2121                 rte_spinlock_unlock(&hw->lock);
2122                 return ret;
2123         }
2124         ret = hns3vf_map_rx_interrupt(dev);
2125         if (ret)
2126                 goto map_rx_inter_err;
2127
2128         /*
2129          * There are three register used to control the status of a TQP
2130          * (contains a pair of Tx queue and Rx queue) in the new version network
2131          * engine. One is used to control the enabling of Tx queue, the other is
2132          * used to control the enabling of Rx queue, and the last is the master
2133          * switch used to control the enabling of the tqp. The Tx register and
2134          * TQP register must be enabled at the same time to enable a Tx queue.
2135          * The same applies to the Rx queue. For the older network enginem, this
2136          * function only refresh the enabled flag, and it is used to update the
2137          * status of queue in the dpdk framework.
2138          */
2139         ret = hns3_start_all_txqs(dev);
2140         if (ret)
2141                 goto map_rx_inter_err;
2142
2143         ret = hns3_start_all_rxqs(dev);
2144         if (ret)
2145                 goto start_all_rxqs_fail;
2146
2147         hw->adapter_state = HNS3_NIC_STARTED;
2148         rte_spinlock_unlock(&hw->lock);
2149
2150         hns3_rx_scattered_calc(dev);
2151         hns3_set_rxtx_function(dev);
2152         hns3_mp_req_start_rxtx(dev);
2153
2154         hns3vf_restore_filter(dev);
2155
2156         /* Enable interrupt of all rx queues before enabling queues */
2157         hns3_dev_all_rx_queue_intr_enable(hw, true);
2158         hns3_start_tqps(hw);
2159
2160         if (dev->data->dev_conf.intr_conf.lsc != 0)
2161                 hns3vf_dev_link_update(dev, 0);
2162         hns3vf_start_poll_job(dev);
2163
2164         return ret;
2165
2166 start_all_rxqs_fail:
2167         hns3_stop_all_txqs(dev);
2168 map_rx_inter_err:
2169         (void)hns3vf_do_stop(hns);
2170         hw->adapter_state = HNS3_NIC_CONFIGURED;
2171         rte_spinlock_unlock(&hw->lock);
2172
2173         return ret;
2174 }
2175
2176 static bool
2177 is_vf_reset_done(struct hns3_hw *hw)
2178 {
2179 #define HNS3_FUN_RST_ING_BITS \
2180         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2181          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2182          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2183          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2184
2185         uint32_t val;
2186
2187         if (hw->reset.level == HNS3_VF_RESET) {
2188                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2189                 if (val & HNS3_VF_RST_ING_BIT)
2190                         return false;
2191         } else {
2192                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2193                 if (val & HNS3_FUN_RST_ING_BITS)
2194                         return false;
2195         }
2196         return true;
2197 }
2198
2199 bool
2200 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2201 {
2202         struct hns3_hw *hw = &hns->hw;
2203         enum hns3_reset_level reset;
2204
2205         /*
2206          * According to the protocol of PCIe, FLR to a PF device resets the PF
2207          * state as well as the SR-IOV extended capability including VF Enable
2208          * which means that VFs no longer exist.
2209          *
2210          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2211          * is in FLR stage, the register state of VF device is not reliable,
2212          * so register states detection can not be carried out. In this case,
2213          * we just ignore the register states and return false to indicate that
2214          * there are no other reset states that need to be processed by driver.
2215          */
2216         if (hw->reset.level == HNS3_VF_FULL_RESET)
2217                 return false;
2218
2219         /* Check the registers to confirm whether there is reset pending */
2220         hns3vf_check_event_cause(hns, NULL);
2221         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2222         if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2223             hw->reset.level < reset) {
2224                 hns3_warn(hw, "High level reset %d is pending", reset);
2225                 return true;
2226         }
2227         return false;
2228 }
2229
2230 static int
2231 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2232 {
2233         struct hns3_hw *hw = &hns->hw;
2234         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2235         struct timeval tv;
2236
2237         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2238                 /*
2239                  * After vf reset is ready, the PF may not have completed
2240                  * the reset processing. The vf sending mbox to PF may fail
2241                  * during the pf reset, so it is better to add extra delay.
2242                  */
2243                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2244                     hw->reset.level == HNS3_FLR_RESET)
2245                         return 0;
2246                 /* Reset retry process, no need to add extra delay. */
2247                 if (hw->reset.attempts)
2248                         return 0;
2249                 if (wait_data->check_completion == NULL)
2250                         return 0;
2251
2252                 wait_data->check_completion = NULL;
2253                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2254                 wait_data->count = 1;
2255                 wait_data->result = HNS3_WAIT_REQUEST;
2256                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2257                                   wait_data);
2258                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2259                 return -EAGAIN;
2260         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2261                 hns3_clock_gettime(&tv);
2262                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2263                           tv.tv_sec, tv.tv_usec);
2264                 return -ETIME;
2265         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2266                 return -EAGAIN;
2267
2268         wait_data->hns = hns;
2269         wait_data->check_completion = is_vf_reset_done;
2270         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2271                                 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2272         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2273         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2274         wait_data->result = HNS3_WAIT_REQUEST;
2275         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2276         return -EAGAIN;
2277 }
2278
2279 static int
2280 hns3vf_prepare_reset(struct hns3_adapter *hns)
2281 {
2282         struct hns3_hw *hw = &hns->hw;
2283         int ret;
2284
2285         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2286                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2287                                         0, true, NULL, 0);
2288                 if (ret)
2289                         return ret;
2290         }
2291         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2292
2293         return 0;
2294 }
2295
2296 static int
2297 hns3vf_stop_service(struct hns3_adapter *hns)
2298 {
2299         struct hns3_hw *hw = &hns->hw;
2300         struct rte_eth_dev *eth_dev;
2301
2302         eth_dev = &rte_eth_devices[hw->data->port_id];
2303         if (hw->adapter_state == HNS3_NIC_STARTED) {
2304                 /*
2305                  * Make sure call update link status before hns3vf_stop_poll_job
2306                  * because update link status depend on polling job exist.
2307                  */
2308                 hns3vf_update_link_status(hw, RTE_ETH_LINK_DOWN, hw->mac.link_speed,
2309                                           hw->mac.link_duplex);
2310                 hns3vf_stop_poll_job(eth_dev);
2311         }
2312         hw->mac.link_status = RTE_ETH_LINK_DOWN;
2313
2314         hns3_set_rxtx_function(eth_dev);
2315         rte_wmb();
2316         /* Disable datapath on secondary process. */
2317         hns3_mp_req_stop_rxtx(eth_dev);
2318         rte_delay_ms(hw->cfg_max_queues);
2319
2320         rte_spinlock_lock(&hw->lock);
2321         if (hw->adapter_state == HNS3_NIC_STARTED ||
2322             hw->adapter_state == HNS3_NIC_STOPPING) {
2323                 hns3_enable_all_queues(hw, false);
2324                 hns3vf_do_stop(hns);
2325                 hw->reset.mbuf_deferred_free = true;
2326         } else
2327                 hw->reset.mbuf_deferred_free = false;
2328
2329         /*
2330          * It is cumbersome for hardware to pick-and-choose entries for deletion
2331          * from table space. Hence, for function reset software intervention is
2332          * required to delete the entries.
2333          */
2334         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2335                 hns3_configure_all_mc_mac_addr(hns, true);
2336         rte_spinlock_unlock(&hw->lock);
2337
2338         return 0;
2339 }
2340
2341 static int
2342 hns3vf_start_service(struct hns3_adapter *hns)
2343 {
2344         struct hns3_hw *hw = &hns->hw;
2345         struct rte_eth_dev *eth_dev;
2346
2347         eth_dev = &rte_eth_devices[hw->data->port_id];
2348         hns3_set_rxtx_function(eth_dev);
2349         hns3_mp_req_start_rxtx(eth_dev);
2350         if (hw->adapter_state == HNS3_NIC_STARTED) {
2351                 hns3vf_start_poll_job(eth_dev);
2352
2353                 /* Enable interrupt of all rx queues before enabling queues */
2354                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2355                 /*
2356                  * Enable state of each rxq and txq will be recovered after
2357                  * reset, so we need to restore them before enable all tqps;
2358                  */
2359                 hns3_restore_tqp_enable_state(hw);
2360                 /*
2361                  * When finished the initialization, enable queues to receive
2362                  * and transmit packets.
2363                  */
2364                 hns3_enable_all_queues(hw, true);
2365         }
2366
2367         return 0;
2368 }
2369
2370 static int
2371 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2372 {
2373         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2374         struct rte_ether_addr *hw_mac;
2375         int ret;
2376
2377         /*
2378          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2379          * on the host by "ip link set ..." command. If the hns3 PF kernel
2380          * ethdev driver sets the MAC address for VF device after the
2381          * initialization of the related VF device, the PF driver will notify
2382          * VF driver to reset VF device to make the new MAC address effective
2383          * immediately. The hns3 VF PMD driver should check whether the MAC
2384          * address has been changed by the PF kernel ethdev driver, if changed
2385          * VF driver should configure hardware using the new MAC address in the
2386          * recovering hardware configuration stage of the reset process.
2387          */
2388         ret = hns3vf_get_host_mac_addr(hw);
2389         if (ret)
2390                 return ret;
2391
2392         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2393         ret = rte_is_zero_ether_addr(hw_mac);
2394         if (ret) {
2395                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2396         } else {
2397                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2398                 if (!ret) {
2399                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2400                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2401                                               &hw->data->mac_addrs[0]);
2402                         hns3_warn(hw, "Default MAC address has been changed to:"
2403                                   " %s by the host PF kernel ethdev driver",
2404                                   mac_str);
2405                 }
2406         }
2407
2408         return 0;
2409 }
2410
2411 static int
2412 hns3vf_restore_conf(struct hns3_adapter *hns)
2413 {
2414         struct hns3_hw *hw = &hns->hw;
2415         int ret;
2416
2417         ret = hns3vf_check_default_mac_change(hw);
2418         if (ret)
2419                 return ret;
2420
2421         ret = hns3_configure_all_mac_addr(hns, false);
2422         if (ret)
2423                 return ret;
2424
2425         ret = hns3_configure_all_mc_mac_addr(hns, false);
2426         if (ret)
2427                 goto err_mc_mac;
2428
2429         ret = hns3vf_restore_promisc(hns);
2430         if (ret)
2431                 goto err_vlan_table;
2432
2433         ret = hns3vf_restore_vlan_conf(hns);
2434         if (ret)
2435                 goto err_vlan_table;
2436
2437         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2438         if (ret)
2439                 goto err_vlan_table;
2440
2441         ret = hns3vf_restore_rx_interrupt(hw);
2442         if (ret)
2443                 goto err_vlan_table;
2444
2445         ret = hns3_restore_gro_conf(hw);
2446         if (ret)
2447                 goto err_vlan_table;
2448
2449         if (hw->adapter_state == HNS3_NIC_STARTED) {
2450                 ret = hns3vf_do_start(hns, false);
2451                 if (ret)
2452                         goto err_vlan_table;
2453                 hns3_info(hw, "hns3vf dev restart successful!");
2454         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2455                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2456
2457         ret = hns3vf_set_alive(hw, true);
2458         if (ret) {
2459                 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2460                 goto err_vlan_table;
2461         }
2462
2463         return 0;
2464
2465 err_vlan_table:
2466         hns3_configure_all_mc_mac_addr(hns, true);
2467 err_mc_mac:
2468         hns3_configure_all_mac_addr(hns, true);
2469         return ret;
2470 }
2471
2472 static enum hns3_reset_level
2473 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2474 {
2475         enum hns3_reset_level reset_level;
2476
2477         /* return the highest priority reset level amongst all */
2478         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2479                 reset_level = HNS3_VF_RESET;
2480         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2481                 reset_level = HNS3_VF_FULL_RESET;
2482         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2483                 reset_level = HNS3_VF_PF_FUNC_RESET;
2484         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2485                 reset_level = HNS3_VF_FUNC_RESET;
2486         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2487                 reset_level = HNS3_FLR_RESET;
2488         else
2489                 reset_level = HNS3_NONE_RESET;
2490
2491         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2492                 return HNS3_NONE_RESET;
2493
2494         return reset_level;
2495 }
2496
2497 static void
2498 hns3vf_reset_service(void *param)
2499 {
2500         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2501         struct hns3_hw *hw = &hns->hw;
2502         enum hns3_reset_level reset_level;
2503         struct timeval tv_delta;
2504         struct timeval tv_start;
2505         struct timeval tv;
2506         uint64_t msec;
2507
2508         /*
2509          * The interrupt is not triggered within the delay time.
2510          * The interrupt may have been lost. It is necessary to handle
2511          * the interrupt to recover from the error.
2512          */
2513         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2514                             SCHEDULE_DEFERRED) {
2515                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2516                                  __ATOMIC_RELAXED);
2517                 hns3_err(hw, "Handling interrupts in delayed tasks");
2518                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2519                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2520                 if (reset_level == HNS3_NONE_RESET) {
2521                         hns3_err(hw, "No reset level is set, try global reset");
2522                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2523                 }
2524         }
2525         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2526
2527         /*
2528          * Hardware reset has been notified, we now have to poll & check if
2529          * hardware has actually completed the reset sequence.
2530          */
2531         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2532         if (reset_level != HNS3_NONE_RESET) {
2533                 hns3_clock_gettime(&tv_start);
2534                 hns3_reset_process(hns, reset_level);
2535                 hns3_clock_gettime(&tv);
2536                 timersub(&tv, &tv_start, &tv_delta);
2537                 msec = hns3_clock_calctime_ms(&tv_delta);
2538                 if (msec > HNS3_RESET_PROCESS_MS)
2539                         hns3_err(hw, "%d handle long time delta %" PRIu64
2540                                  " ms time=%ld.%.6ld",
2541                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2542         }
2543 }
2544
2545 static int
2546 hns3vf_reinit_dev(struct hns3_adapter *hns)
2547 {
2548         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2549         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2550         struct hns3_hw *hw = &hns->hw;
2551         int ret;
2552
2553         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2554                 rte_intr_disable(pci_dev->intr_handle);
2555                 ret = hns3vf_set_bus_master(pci_dev, true);
2556                 if (ret < 0) {
2557                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2558                         return ret;
2559                 }
2560         }
2561
2562         /* Firmware command initialize */
2563         ret = hns3_cmd_init(hw);
2564         if (ret) {
2565                 hns3_err(hw, "Failed to init cmd: %d", ret);
2566                 return ret;
2567         }
2568
2569         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2570                 /*
2571                  * UIO enables msix by writing the pcie configuration space
2572                  * vfio_pci enables msix in rte_intr_enable.
2573                  */
2574                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2575                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2576                         if (hns3vf_enable_msix(pci_dev, true))
2577                                 hns3_err(hw, "Failed to enable msix");
2578                 }
2579
2580                 rte_intr_enable(pci_dev->intr_handle);
2581         }
2582
2583         ret = hns3_reset_all_tqps(hns);
2584         if (ret) {
2585                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2586                 return ret;
2587         }
2588
2589         ret = hns3vf_init_hardware(hns);
2590         if (ret) {
2591                 hns3_err(hw, "Failed to init hardware: %d", ret);
2592                 return ret;
2593         }
2594
2595         return 0;
2596 }
2597
2598 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2599         .dev_configure      = hns3vf_dev_configure,
2600         .dev_start          = hns3vf_dev_start,
2601         .dev_stop           = hns3vf_dev_stop,
2602         .dev_close          = hns3vf_dev_close,
2603         .mtu_set            = hns3vf_dev_mtu_set,
2604         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2605         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2606         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2607         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2608         .stats_get          = hns3_stats_get,
2609         .stats_reset        = hns3_stats_reset,
2610         .xstats_get         = hns3_dev_xstats_get,
2611         .xstats_get_names   = hns3_dev_xstats_get_names,
2612         .xstats_reset       = hns3_dev_xstats_reset,
2613         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2614         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2615         .dev_infos_get      = hns3vf_dev_infos_get,
2616         .fw_version_get     = hns3vf_fw_version_get,
2617         .rx_queue_setup     = hns3_rx_queue_setup,
2618         .tx_queue_setup     = hns3_tx_queue_setup,
2619         .rx_queue_release   = hns3_dev_rx_queue_release,
2620         .tx_queue_release   = hns3_dev_tx_queue_release,
2621         .rx_queue_start     = hns3_dev_rx_queue_start,
2622         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2623         .tx_queue_start     = hns3_dev_tx_queue_start,
2624         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2625         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2626         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2627         .rxq_info_get       = hns3_rxq_info_get,
2628         .txq_info_get       = hns3_txq_info_get,
2629         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2630         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2631         .mac_addr_add       = hns3_add_mac_addr,
2632         .mac_addr_remove    = hns3_remove_mac_addr,
2633         .mac_addr_set       = hns3vf_set_default_mac_addr,
2634         .set_mc_addr_list   = hns3_set_mc_mac_addr_list,
2635         .link_update        = hns3vf_dev_link_update,
2636         .rss_hash_update    = hns3_dev_rss_hash_update,
2637         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2638         .reta_update        = hns3_dev_rss_reta_update,
2639         .reta_query         = hns3_dev_rss_reta_query,
2640         .flow_ops_get       = hns3_dev_flow_ops_get,
2641         .vlan_filter_set    = hns3vf_vlan_filter_set,
2642         .vlan_offload_set   = hns3vf_vlan_offload_set,
2643         .get_reg            = hns3_get_regs,
2644         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2645         .tx_done_cleanup    = hns3_tx_done_cleanup,
2646 };
2647
2648 static const struct hns3_reset_ops hns3vf_reset_ops = {
2649         .reset_service       = hns3vf_reset_service,
2650         .stop_service        = hns3vf_stop_service,
2651         .prepare_reset       = hns3vf_prepare_reset,
2652         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2653         .reinit_dev          = hns3vf_reinit_dev,
2654         .restore_conf        = hns3vf_restore_conf,
2655         .start_service       = hns3vf_start_service,
2656 };
2657
2658 static void
2659 hns3vf_init_hw_ops(struct hns3_hw *hw)
2660 {
2661         hw->ops.add_mc_mac_addr = hns3vf_add_mc_mac_addr;
2662         hw->ops.del_mc_mac_addr = hns3vf_remove_mc_mac_addr;
2663         hw->ops.add_uc_mac_addr = hns3vf_add_uc_mac_addr;
2664         hw->ops.del_uc_mac_addr = hns3vf_remove_uc_mac_addr;
2665 }
2666
2667 static int
2668 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2669 {
2670         struct hns3_adapter *hns = eth_dev->data->dev_private;
2671         struct hns3_hw *hw = &hns->hw;
2672         int ret;
2673
2674         PMD_INIT_FUNC_TRACE();
2675
2676         hns3_flow_init(eth_dev);
2677
2678         hns3_set_rxtx_function(eth_dev);
2679         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2680         eth_dev->rx_queue_count = hns3_rx_queue_count;
2681         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2682                 ret = hns3_mp_init_secondary();
2683                 if (ret) {
2684                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2685                                           "process, ret = %d", ret);
2686                         goto err_mp_init_secondary;
2687                 }
2688                 hw->secondary_cnt++;
2689                 hns3_tx_push_init(eth_dev);
2690                 return 0;
2691         }
2692
2693         ret = hns3_mp_init_primary();
2694         if (ret) {
2695                 PMD_INIT_LOG(ERR,
2696                              "Failed to init for primary process, ret = %d",
2697                              ret);
2698                 goto err_mp_init_primary;
2699         }
2700
2701         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2702         hns->is_vf = true;
2703         hw->data = eth_dev->data;
2704         hns3_parse_devargs(eth_dev);
2705
2706         ret = hns3_reset_init(hw);
2707         if (ret)
2708                 goto err_init_reset;
2709         hw->reset.ops = &hns3vf_reset_ops;
2710
2711         hns3vf_init_hw_ops(hw);
2712         ret = hns3vf_init_vf(eth_dev);
2713         if (ret) {
2714                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2715                 goto err_init_vf;
2716         }
2717
2718         /* Allocate memory for storing MAC addresses */
2719         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2720                                                sizeof(struct rte_ether_addr) *
2721                                                HNS3_VF_UC_MACADDR_NUM, 0);
2722         if (eth_dev->data->mac_addrs == NULL) {
2723                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2724                              "to store MAC addresses",
2725                              sizeof(struct rte_ether_addr) *
2726                              HNS3_VF_UC_MACADDR_NUM);
2727                 ret = -ENOMEM;
2728                 goto err_rte_zmalloc;
2729         }
2730
2731         /*
2732          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2733          * on the host by "ip link set ..." command. To avoid some incorrect
2734          * scenes, for example, hns3 VF PMD driver fails to receive and send
2735          * packets after user configure the MAC address by using the
2736          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2737          * address strategy as the hns3 kernel ethdev driver in the
2738          * initialization. If user configure a MAC address by the ip command
2739          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2740          * start with a random MAC address in the initialization.
2741          */
2742         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2743                 rte_eth_random_addr(hw->mac.mac_addr);
2744         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2745                             &eth_dev->data->mac_addrs[0]);
2746
2747         hw->adapter_state = HNS3_NIC_INITIALIZED;
2748
2749         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2750                             SCHEDULE_PENDING) {
2751                 hns3_err(hw, "Reschedule reset service after dev_init");
2752                 hns3_schedule_reset(hns);
2753         } else {
2754                 /* IMP will wait ready flag before reset */
2755                 hns3_notify_reset_ready(hw, false);
2756         }
2757         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2758                           eth_dev);
2759         return 0;
2760
2761 err_rte_zmalloc:
2762         hns3vf_uninit_vf(eth_dev);
2763
2764 err_init_vf:
2765         rte_free(hw->reset.wait_data);
2766
2767 err_init_reset:
2768         hns3_mp_uninit_primary();
2769
2770 err_mp_init_primary:
2771 err_mp_init_secondary:
2772         eth_dev->dev_ops = NULL;
2773         eth_dev->rx_pkt_burst = NULL;
2774         eth_dev->rx_descriptor_status = NULL;
2775         eth_dev->tx_pkt_burst = NULL;
2776         eth_dev->tx_pkt_prepare = NULL;
2777         eth_dev->tx_descriptor_status = NULL;
2778
2779         return ret;
2780 }
2781
2782 static int
2783 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2784 {
2785         struct hns3_adapter *hns = eth_dev->data->dev_private;
2786         struct hns3_hw *hw = &hns->hw;
2787
2788         PMD_INIT_FUNC_TRACE();
2789
2790         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2791                 return 0;
2792
2793         if (hw->adapter_state < HNS3_NIC_CLOSING)
2794                 hns3vf_dev_close(eth_dev);
2795
2796         hw->adapter_state = HNS3_NIC_REMOVED;
2797         return 0;
2798 }
2799
2800 static int
2801 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2802                      struct rte_pci_device *pci_dev)
2803 {
2804         return rte_eth_dev_pci_generic_probe(pci_dev,
2805                                              sizeof(struct hns3_adapter),
2806                                              hns3vf_dev_init);
2807 }
2808
2809 static int
2810 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2811 {
2812         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2813 }
2814
2815 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2816         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2817         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2818         { .vendor_id = 0, }, /* sentinel */
2819 };
2820
2821 static struct rte_pci_driver rte_hns3vf_pmd = {
2822         .id_table = pci_id_hns3vf_map,
2823         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2824         .probe = eth_hns3vf_pci_probe,
2825         .remove = eth_hns3vf_pci_remove,
2826 };
2827
2828 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2829 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2830 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
2831 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
2832                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
2833                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
2834                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
2835                 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16_t> ");