1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
5 #include <linux/pci_regs.h>
7 #include <ethdev_pci.h>
12 #include "hns3_ethdev.h"
13 #include "hns3_logs.h"
14 #include "hns3_rxtx.h"
15 #include "hns3_regs.h"
16 #include "hns3_intr.h"
20 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */
21 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */
23 #define HNS3VF_RESET_WAIT_MS 20
24 #define HNS3VF_RESET_WAIT_CNT 2000
26 /* Reset related Registers */
27 #define HNS3_GLOBAL_RESET_BIT 0
28 #define HNS3_CORE_RESET_BIT 1
29 #define HNS3_IMP_RESET_BIT 2
30 #define HNS3_FUN_RST_ING_B 0
32 enum hns3vf_evt_cause {
33 HNS3VF_VECTOR0_EVENT_RST,
34 HNS3VF_VECTOR0_EVENT_MBX,
35 HNS3VF_VECTOR0_EVENT_OTHER,
38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
44 struct rte_ether_addr *mac_addr);
45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
46 struct rte_ether_addr *mac_addr);
47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
48 __rte_unused int wait_to_complete);
50 /* set PCI bus mastering */
52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
57 ret = rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND);
59 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
65 /* set the master bit */
66 reg |= PCI_COMMAND_MASTER;
68 reg &= ~(PCI_COMMAND_MASTER);
70 return rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND);
74 * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
75 * @cap: the capability
77 * Return the address of the given capability within the PCI capability list.
80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
82 #define MAX_PCIE_CAPABILITY 48
89 ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
91 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
95 if (!(status & PCI_STATUS_CAP_LIST))
98 ttl = MAX_PCIE_CAPABILITY;
99 ret = rte_pci_read_config(device, &pos, sizeof(pos),
100 PCI_CAPABILITY_LIST);
102 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
103 PCI_CAPABILITY_LIST);
107 while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
108 ret = rte_pci_read_config(device, &id, sizeof(id),
109 (pos + PCI_CAP_LIST_ID));
111 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
112 (pos + PCI_CAP_LIST_ID));
122 ret = rte_pci_read_config(device, &pos, sizeof(pos),
123 (pos + PCI_CAP_LIST_NEXT));
125 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
126 (pos + PCI_CAP_LIST_NEXT));
134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
140 pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
142 ret = rte_pci_read_config(device, &control, sizeof(control),
143 (pos + PCI_MSIX_FLAGS));
145 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
146 (pos + PCI_MSIX_FLAGS));
151 control |= PCI_MSIX_FLAGS_ENABLE;
153 control &= ~PCI_MSIX_FLAGS_ENABLE;
154 ret = rte_pci_write_config(device, &control, sizeof(control),
155 (pos + PCI_MSIX_FLAGS));
157 PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
158 (pos + PCI_MSIX_FLAGS));
166 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
168 /* mac address was checked by upper level interface */
169 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
172 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
173 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
174 RTE_ETHER_ADDR_LEN, false, NULL, 0);
176 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
178 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
185 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
187 /* mac address was checked by upper level interface */
188 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
191 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
192 HNS3_MBX_MAC_VLAN_UC_REMOVE,
193 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
196 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
198 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
205 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
207 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
208 struct rte_ether_addr *addr;
212 for (i = 0; i < hw->mc_addrs_num; i++) {
213 addr = &hw->mc_addrs[i];
214 /* Check if there are duplicate addresses */
215 if (rte_is_same_ether_addr(addr, mac_addr)) {
216 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
218 hns3_err(hw, "failed to add mc mac addr, same addrs"
219 "(%s) is added by the set_mc_mac_addr_list "
225 ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
227 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
229 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
236 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
237 __rte_unused uint32_t idx,
238 __rte_unused uint32_t pool)
240 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
241 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
244 rte_spinlock_lock(&hw->lock);
247 * In hns3 network engine adding UC and MC mac address with different
248 * commands with firmware. We need to determine whether the input
249 * address is a UC or a MC address to call different commands.
250 * By the way, it is recommended calling the API function named
251 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
252 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
253 * may affect the specifications of UC mac addresses.
255 if (rte_is_multicast_ether_addr(mac_addr))
256 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
258 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
260 rte_spinlock_unlock(&hw->lock);
262 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
264 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
272 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
274 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
275 /* index will be checked by upper level rte interface */
276 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
277 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
280 rte_spinlock_lock(&hw->lock);
282 if (rte_is_multicast_ether_addr(mac_addr))
283 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
285 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
287 rte_spinlock_unlock(&hw->lock);
289 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
291 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
297 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
298 struct rte_ether_addr *mac_addr)
300 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
301 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
302 struct rte_ether_addr *old_addr;
303 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
304 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
308 * It has been guaranteed that input parameter named mac_addr is valid
309 * address in the rte layer of DPDK framework.
311 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
312 rte_spinlock_lock(&hw->lock);
313 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
314 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
317 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
318 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
319 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
322 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
323 * driver. When user has configured a MAC address for VF device
324 * by "ip link set ..." command based on the PF device, the hns3
325 * PF kernel ethdev driver does not allow VF driver to request
326 * reconfiguring a different default MAC address, and return
327 * -EPREM to VF driver through mailbox.
330 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
332 hns3_warn(hw, "Has permanet mac addr(%s) for vf",
335 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
337 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
342 rte_ether_addr_copy(mac_addr,
343 (struct rte_ether_addr *)hw->mac.mac_addr);
344 rte_spinlock_unlock(&hw->lock);
350 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
352 struct hns3_hw *hw = &hns->hw;
353 struct rte_ether_addr *addr;
354 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
359 for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
360 addr = &hw->data->mac_addrs[i];
361 if (rte_is_zero_ether_addr(addr))
363 if (rte_is_multicast_ether_addr(addr))
364 ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
365 hns3vf_add_mc_mac_addr(hw, addr);
367 ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
368 hns3vf_add_uc_mac_addr(hw, addr);
372 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
374 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
375 "ret = %d.", del ? "remove" : "restore",
383 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
384 struct rte_ether_addr *mac_addr)
386 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
389 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
390 HNS3_MBX_MAC_VLAN_MC_ADD,
391 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
394 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
396 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
404 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
405 struct rte_ether_addr *mac_addr)
407 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
410 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
411 HNS3_MBX_MAC_VLAN_MC_REMOVE,
412 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
415 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
417 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
425 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
426 struct rte_ether_addr *mc_addr_set,
429 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
430 struct rte_ether_addr *addr;
434 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
435 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
436 "invalid. valid range: 0~%d",
437 nb_mc_addr, HNS3_MC_MACADDR_NUM);
441 /* Check if input mac addresses are valid */
442 for (i = 0; i < nb_mc_addr; i++) {
443 addr = &mc_addr_set[i];
444 if (!rte_is_multicast_ether_addr(addr)) {
445 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
448 "failed to set mc mac addr, addr(%s) invalid.",
453 /* Check if there are duplicate addresses */
454 for (j = i + 1; j < nb_mc_addr; j++) {
455 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
456 hns3_ether_format_addr(mac_str,
457 RTE_ETHER_ADDR_FMT_SIZE,
459 hns3_err(hw, "failed to set mc mac addr, "
460 "addrs invalid. two same addrs(%s).",
467 * Check if there are duplicate addresses between mac_addrs
470 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
471 if (rte_is_same_ether_addr(addr,
472 &hw->data->mac_addrs[j])) {
473 hns3_ether_format_addr(mac_str,
474 RTE_ETHER_ADDR_FMT_SIZE,
476 hns3_err(hw, "failed to set mc mac addr, "
477 "addrs invalid. addrs(%s) has already "
478 "configured in mac_addr add API",
489 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
490 struct rte_ether_addr *mc_addr_set,
493 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
494 struct rte_ether_addr *addr;
501 ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
505 rte_spinlock_lock(&hw->lock);
506 cur_addr_num = hw->mc_addrs_num;
507 for (i = 0; i < cur_addr_num; i++) {
508 num = cur_addr_num - i - 1;
509 addr = &hw->mc_addrs[num];
510 ret = hns3vf_remove_mc_mac_addr(hw, addr);
512 rte_spinlock_unlock(&hw->lock);
519 set_addr_num = (int)nb_mc_addr;
520 for (i = 0; i < set_addr_num; i++) {
521 addr = &mc_addr_set[i];
522 ret = hns3vf_add_mc_mac_addr(hw, addr);
524 rte_spinlock_unlock(&hw->lock);
528 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
531 rte_spinlock_unlock(&hw->lock);
537 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
539 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
540 struct hns3_hw *hw = &hns->hw;
541 struct rte_ether_addr *addr;
546 for (i = 0; i < hw->mc_addrs_num; i++) {
547 addr = &hw->mc_addrs[i];
548 if (!rte_is_multicast_ether_addr(addr))
551 ret = hns3vf_remove_mc_mac_addr(hw, addr);
553 ret = hns3vf_add_mc_mac_addr(hw, addr);
556 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
558 hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
559 del ? "Remove" : "Restore", mac_str, ret);
566 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
567 bool en_uc_pmc, bool en_mc_pmc)
569 struct hns3_mbx_vf_to_pf_cmd *req;
570 struct hns3_cmd_desc desc;
573 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
576 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
577 * so there are some features for promiscuous/allmulticast mode in hns3
578 * VF PMD driver as below:
579 * 1. The promiscuous/allmulticast mode can be configured successfully
580 * only based on the trusted VF device. If based on the non trusted
581 * VF device, configuring promiscuous/allmulticast mode will fail.
582 * The hns3 VF device can be confiruged as trusted device by hns3 PF
583 * kernel ethdev driver on the host by the following command:
584 * "ip link set <eth num> vf <vf id> turst on"
585 * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
586 * driver can receive the ingress and outgoing traffic. In the words,
587 * all the ingress packets, all the packets sent from the PF and
588 * other VFs on the same physical port.
589 * 3. Note: Because of the hardware constraints, By default vlan filter
590 * is enabled and couldn't be turned off based on VF device, so vlan
591 * filter is still effective even in promiscuous mode. If upper
592 * applications don't call rte_eth_dev_vlan_filter API function to
593 * set vlan based on VF device, hns3 VF PMD driver will can't receive
594 * the packets with vlan tag in promiscuoue mode.
596 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
597 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
598 req->msg[1] = en_bc_pmc ? 1 : 0;
599 req->msg[2] = en_uc_pmc ? 1 : 0;
600 req->msg[3] = en_mc_pmc ? 1 : 0;
601 req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
603 ret = hns3_cmd_send(hw, &desc, 1);
605 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
611 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
613 struct hns3_adapter *hns = dev->data->dev_private;
614 struct hns3_hw *hw = &hns->hw;
617 ret = hns3vf_set_promisc_mode(hw, true, true, true);
619 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
625 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
627 bool allmulti = dev->data->all_multicast ? true : false;
628 struct hns3_adapter *hns = dev->data->dev_private;
629 struct hns3_hw *hw = &hns->hw;
632 ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
634 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
640 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
642 struct hns3_adapter *hns = dev->data->dev_private;
643 struct hns3_hw *hw = &hns->hw;
646 if (dev->data->promiscuous)
649 ret = hns3vf_set_promisc_mode(hw, true, false, true);
651 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
657 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
659 struct hns3_adapter *hns = dev->data->dev_private;
660 struct hns3_hw *hw = &hns->hw;
663 if (dev->data->promiscuous)
666 ret = hns3vf_set_promisc_mode(hw, true, false, false);
668 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
674 hns3vf_restore_promisc(struct hns3_adapter *hns)
676 struct hns3_hw *hw = &hns->hw;
677 bool allmulti = hw->data->all_multicast ? true : false;
679 if (hw->data->promiscuous)
680 return hns3vf_set_promisc_mode(hw, true, true, true);
682 return hns3vf_set_promisc_mode(hw, true, false, allmulti);
686 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
687 bool mmap, enum hns3_ring_type queue_type,
690 struct hns3_vf_bind_vector_msg bind_msg;
695 memset(&bind_msg, 0, sizeof(bind_msg));
696 code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
697 HNS3_MBX_UNMAP_RING_TO_VECTOR;
698 bind_msg.vector_id = vector_id;
700 if (queue_type == HNS3_RING_TYPE_RX)
701 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
703 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
705 bind_msg.param[0].ring_type = queue_type;
706 bind_msg.ring_num = 1;
707 bind_msg.param[0].tqp_index = queue_id;
708 op_str = mmap ? "Map" : "Unmap";
709 ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
710 sizeof(bind_msg), false, NULL, 0);
712 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
713 op_str, queue_id, bind_msg.vector_id, ret);
719 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
726 * In hns3 network engine, vector 0 is always the misc interrupt of this
727 * function, vector 1~N can be used respectively for the queues of the
728 * function. Tx and Rx queues with the same number share the interrupt
729 * vector. In the initialization clearing the all hardware mapping
730 * relationship configurations between queues and interrupt vectors is
731 * needed, so some error caused by the residual configurations, such as
732 * the unexpected Tx interrupt, can be avoid.
734 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
735 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
736 vec = vec - 1; /* the last interrupt is reserved */
737 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
738 for (i = 0; i < hw->intr_tqps_num; i++) {
740 * Set gap limiter/rate limiter/quanity limiter algorithm
741 * configuration for interrupt coalesce of queue's interrupt.
743 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
744 HNS3_TQP_INTR_GL_DEFAULT);
745 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
746 HNS3_TQP_INTR_GL_DEFAULT);
747 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
749 * QL(quantity limiter) is not used currently, just set 0 to
752 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
754 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
755 HNS3_RING_TYPE_TX, i);
757 PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
758 "vector: %u, ret=%d", i, vec, ret);
762 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
763 HNS3_RING_TYPE_RX, i);
765 PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
766 "vector: %u, ret=%d", i, vec, ret);
775 hns3vf_dev_configure(struct rte_eth_dev *dev)
777 struct hns3_adapter *hns = dev->data->dev_private;
778 struct hns3_hw *hw = &hns->hw;
779 struct rte_eth_conf *conf = &dev->data->dev_conf;
780 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
781 uint16_t nb_rx_q = dev->data->nb_rx_queues;
782 uint16_t nb_tx_q = dev->data->nb_tx_queues;
783 struct rte_eth_rss_conf rss_conf;
784 uint32_t max_rx_pkt_len;
789 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
792 * Some versions of hardware network engine does not support
793 * individually enable/disable/reset the Tx or Rx queue. These devices
794 * must enable/disable/reset Tx and Rx queues at the same time. When the
795 * numbers of Tx queues allocated by upper applications are not equal to
796 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
797 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
798 * work as usual. But these fake queues are imperceptible, and can not
799 * be used by upper applications.
801 if (!hns3_dev_indep_txrx_supported(hw)) {
802 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
804 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
810 hw->adapter_state = HNS3_NIC_CONFIGURING;
811 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
812 hns3_err(hw, "setting link speed/duplex not supported");
817 /* When RSS is not configured, redirect the packet queue 0 */
818 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
819 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
820 hw->rss_dis_flag = false;
821 rss_conf = conf->rx_adv_conf.rss_conf;
822 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
828 * If jumbo frames are enabled, MTU needs to be refreshed
829 * according to the maximum RX packet length.
831 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
832 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
833 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
834 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
835 hns3_err(hw, "maximum Rx packet length must be greater "
836 "than %u and less than %u when jumbo frame enabled.",
837 (uint16_t)HNS3_DEFAULT_FRAME_LEN,
838 (uint16_t)HNS3_MAX_FRAME_LEN);
843 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
844 ret = hns3vf_dev_mtu_set(dev, mtu);
847 dev->data->mtu = mtu;
850 ret = hns3vf_dev_configure_vlan(dev);
854 /* config hardware GRO */
855 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
856 ret = hns3_config_gro(hw, gro_en);
860 hns3_init_rx_ptype_tble(dev);
862 hw->adapter_state = HNS3_NIC_CONFIGURED;
866 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
867 hw->adapter_state = HNS3_NIC_INITIALIZED;
873 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
877 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
878 sizeof(mtu), true, NULL, 0);
880 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
886 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
888 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
889 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
893 * The hns3 PF/VF devices on the same port share the hardware MTU
894 * configuration. Currently, we send mailbox to inform hns3 PF kernel
895 * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
896 * driver, there is no need to stop the port for hns3 VF device, and the
897 * MTU value issued by hns3 VF PMD driver must be less than or equal to
900 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
901 hns3_err(hw, "Failed to set mtu during resetting");
906 * when Rx of scattered packets is off, we have some possibility of
907 * using vector Rx process function or simple Rx functions in hns3 PMD
908 * driver. If the input MTU is increased and the maximum length of
909 * received packets is greater than the length of a buffer for Rx
910 * packet, the hardware network engine needs to use multiple BDs and
911 * buffers to store these packets. This will cause problems when still
912 * using vector Rx process function or simple Rx function to receiving
913 * packets. So, when Rx of scattered packets is off and device is
914 * started, it is not permitted to increase MTU so that the maximum
915 * length of Rx packets is greater than Rx buffer length.
917 if (dev->data->dev_started && !dev->data->scattered_rx &&
918 frame_size > hw->rx_buf_len) {
919 hns3_err(hw, "failed to set mtu because current is "
920 "not scattered rx mode");
924 rte_spinlock_lock(&hw->lock);
925 ret = hns3vf_config_mtu(hw, mtu);
927 rte_spinlock_unlock(&hw->lock);
930 if (mtu > RTE_ETHER_MTU)
931 dev->data->dev_conf.rxmode.offloads |=
932 DEV_RX_OFFLOAD_JUMBO_FRAME;
934 dev->data->dev_conf.rxmode.offloads &=
935 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
936 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
937 rte_spinlock_unlock(&hw->lock);
943 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
945 struct hns3_adapter *hns = eth_dev->data->dev_private;
946 struct hns3_hw *hw = &hns->hw;
947 uint16_t q_num = hw->tqps_num;
950 * In interrupt mode, 'max_rx_queues' is set based on the number of
951 * MSI-X interrupt resources of the hardware.
953 if (hw->data->dev_conf.intr_conf.rxq == 1)
954 q_num = hw->intr_tqps_num;
956 info->max_rx_queues = q_num;
957 info->max_tx_queues = hw->tqps_num;
958 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
959 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
960 info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
961 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
962 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
964 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
965 DEV_RX_OFFLOAD_UDP_CKSUM |
966 DEV_RX_OFFLOAD_TCP_CKSUM |
967 DEV_RX_OFFLOAD_SCTP_CKSUM |
968 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
969 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
970 DEV_RX_OFFLOAD_SCATTER |
971 DEV_RX_OFFLOAD_VLAN_STRIP |
972 DEV_RX_OFFLOAD_VLAN_FILTER |
973 DEV_RX_OFFLOAD_JUMBO_FRAME |
974 DEV_RX_OFFLOAD_RSS_HASH |
975 DEV_RX_OFFLOAD_TCP_LRO);
976 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
977 DEV_TX_OFFLOAD_IPV4_CKSUM |
978 DEV_TX_OFFLOAD_TCP_CKSUM |
979 DEV_TX_OFFLOAD_UDP_CKSUM |
980 DEV_TX_OFFLOAD_SCTP_CKSUM |
981 DEV_TX_OFFLOAD_MULTI_SEGS |
982 DEV_TX_OFFLOAD_TCP_TSO |
983 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
984 DEV_TX_OFFLOAD_GRE_TNL_TSO |
985 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
986 DEV_TX_OFFLOAD_MBUF_FAST_FREE |
987 hns3_txvlan_cap_get(hw));
989 if (hns3_dev_outer_udp_cksum_supported(hw))
990 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
992 if (hns3_dev_indep_txrx_supported(hw))
993 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
994 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
996 info->rx_desc_lim = (struct rte_eth_desc_lim) {
997 .nb_max = HNS3_MAX_RING_DESC,
998 .nb_min = HNS3_MIN_RING_DESC,
999 .nb_align = HNS3_ALIGN_RING_DESC,
1002 info->tx_desc_lim = (struct rte_eth_desc_lim) {
1003 .nb_max = HNS3_MAX_RING_DESC,
1004 .nb_min = HNS3_MIN_RING_DESC,
1005 .nb_align = HNS3_ALIGN_RING_DESC,
1006 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
1007 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
1010 info->default_rxconf = (struct rte_eth_rxconf) {
1011 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
1013 * If there are no available Rx buffer descriptors, incoming
1014 * packets are always dropped by hardware based on hns3 network
1020 info->default_txconf = (struct rte_eth_txconf) {
1021 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
1025 info->vmdq_queue_num = 0;
1027 info->reta_size = hw->rss_ind_tbl_size;
1028 info->hash_key_size = HNS3_RSS_KEY_SIZE;
1029 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1030 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1031 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1037 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1039 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1043 hns3vf_disable_irq0(struct hns3_hw *hw)
1045 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1049 hns3vf_enable_irq0(struct hns3_hw *hw)
1051 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1054 static enum hns3vf_evt_cause
1055 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1057 struct hns3_hw *hw = &hns->hw;
1058 enum hns3vf_evt_cause ret;
1059 uint32_t cmdq_stat_reg;
1060 uint32_t rst_ing_reg;
1063 /* Fetch the events from their corresponding regs */
1064 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1065 if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1066 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1067 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1068 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1069 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
1070 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1071 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1072 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1074 hw->reset.stats.global_cnt++;
1075 hns3_warn(hw, "Global reset detected, clear reset status");
1077 hns3_schedule_delayed_reset(hns);
1078 hns3_warn(hw, "Global reset detected, don't clear reset status");
1081 ret = HNS3VF_VECTOR0_EVENT_RST;
1085 /* Check for vector0 mailbox(=CMDQ RX) event source */
1086 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1087 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1088 ret = HNS3VF_VECTOR0_EVENT_MBX;
1093 ret = HNS3VF_VECTOR0_EVENT_OTHER;
1101 hns3vf_interrupt_handler(void *param)
1103 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1104 struct hns3_adapter *hns = dev->data->dev_private;
1105 struct hns3_hw *hw = &hns->hw;
1106 enum hns3vf_evt_cause event_cause;
1109 /* Disable interrupt */
1110 hns3vf_disable_irq0(hw);
1112 /* Read out interrupt causes */
1113 event_cause = hns3vf_check_event_cause(hns, &clearval);
1115 switch (event_cause) {
1116 case HNS3VF_VECTOR0_EVENT_RST:
1117 hns3_schedule_reset(hns);
1119 case HNS3VF_VECTOR0_EVENT_MBX:
1120 hns3_dev_handle_mbx_msg(hw);
1126 /* Clear interrupt causes */
1127 hns3vf_clear_event_cause(hw, clearval);
1129 /* Enable interrupt */
1130 hns3vf_enable_irq0(hw);
1134 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1136 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1137 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1138 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1139 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
1143 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1145 struct hns3_dev_specs_0_cmd *req0;
1147 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1149 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1150 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1151 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1152 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
1156 hns3vf_check_dev_specifications(struct hns3_hw *hw)
1158 if (hw->rss_ind_tbl_size == 0 ||
1159 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
1160 hns3_warn(hw, "the size of hash lookup table configured (%u)"
1161 " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
1162 HNS3_RSS_IND_TBL_SIZE_MAX);
1170 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1172 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1176 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1177 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1179 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1181 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1183 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1187 hns3vf_parse_dev_specifications(hw, desc);
1189 return hns3vf_check_dev_specifications(hw);
1193 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
1195 uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
1196 HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1197 uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1198 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1200 if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1201 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1202 __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1206 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
1208 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS 500
1210 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1211 int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
1212 uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1213 uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1214 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1216 __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
1219 (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1222 while (remain_ms > 0) {
1223 rte_delay_ms(HNS3_POLL_RESPONE_MS);
1224 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
1225 HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1231 * When exit above loop, the pf_push_lsc_cap could be one of the three
1232 * state: unknown (means pf not ack), not_supported, supported.
1233 * Here config it as 'not_supported' when it's 'unknown' state.
1235 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1236 __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1238 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
1239 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
1240 hns3_info(hw, "detect PF support push link status change!");
1243 * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
1244 * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
1245 * the RTE_ETH_DEV_INTR_LSC capability.
1247 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
1252 hns3vf_get_capability(struct hns3_hw *hw)
1254 struct rte_pci_device *pci_dev;
1255 struct rte_eth_dev *eth_dev;
1259 eth_dev = &rte_eth_devices[hw->data->port_id];
1260 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1262 /* Get PCI revision id */
1263 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1264 HNS3_PCI_REVISION_ID);
1265 if (ret != HNS3_PCI_REVISION_ID_LEN) {
1266 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1270 hw->revision = revision;
1272 if (revision < PCI_REVISION_ID_HIP09_A) {
1273 hns3vf_set_default_dev_specifications(hw);
1274 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1275 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1276 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1277 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
1278 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1279 hw->rss_info.ipv6_sctp_offload_supported = false;
1280 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1284 ret = hns3vf_query_dev_specifications(hw);
1287 "failed to query dev specifications, ret = %d",
1292 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1293 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1294 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1295 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1296 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1297 hw->rss_info.ipv6_sctp_offload_supported = true;
1298 hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1304 hns3vf_check_tqp_info(struct hns3_hw *hw)
1306 if (hw->tqps_num == 0) {
1307 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1311 if (hw->rss_size_max == 0) {
1312 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1316 hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1322 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1327 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1328 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1329 true, &resp_msg, sizeof(resp_msg));
1331 if (ret == -ETIME) {
1333 * Getting current port based VLAN state from PF driver
1334 * will not affect VF driver's basic function. Because
1335 * the VF driver relies on hns3 PF kernel ether driver,
1336 * to avoid introducing compatibility issues with older
1337 * version of PF driver, no failure will be returned
1338 * when the return value is ETIME. This return value has
1339 * the following scenarios:
1340 * 1) Firmware didn't return the results in time
1341 * 2) the result return by firmware is timeout
1342 * 3) the older version of kernel side PF driver does
1343 * not support this mailbox message.
1344 * For scenarios 1 and 2, it is most likely that a
1345 * hardware error has occurred, or a hardware reset has
1346 * occurred. In this case, these errors will be caught
1347 * by other functions.
1349 PMD_INIT_LOG(WARNING,
1350 "failed to get PVID state for timeout, maybe "
1351 "kernel side PF driver doesn't support this "
1352 "mailbox message, or firmware didn't respond.");
1353 resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1355 PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1360 hw->port_base_vlan_cfg.state = resp_msg ?
1361 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1366 hns3vf_get_queue_info(struct hns3_hw *hw)
1368 #define HNS3VF_TQPS_RSS_INFO_LEN 6
1369 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1372 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1373 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1375 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1379 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1380 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1382 return hns3vf_check_tqp_info(hw);
1386 hns3vf_get_queue_depth(struct hns3_hw *hw)
1388 #define HNS3VF_TQPS_DEPTH_INFO_LEN 4
1389 uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1392 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1393 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1395 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1400 memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1401 memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1407 hns3vf_get_tc_info(struct hns3_hw *hw)
1413 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1414 true, &resp_msg, sizeof(resp_msg));
1416 hns3_err(hw, "VF request to get TC info from PF failed %d",
1421 hw->hw_tc_map = resp_msg;
1423 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1424 if (hw->hw_tc_map & BIT(i))
1432 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1434 uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1437 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1438 true, host_mac, RTE_ETHER_ADDR_LEN);
1440 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1444 memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1450 hns3vf_get_configuration(struct hns3_hw *hw)
1454 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1455 hw->rss_dis_flag = false;
1457 /* Get device capability */
1458 ret = hns3vf_get_capability(hw);
1460 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1464 hns3vf_get_push_lsc_cap(hw);
1466 /* Get queue configuration from PF */
1467 ret = hns3vf_get_queue_info(hw);
1471 /* Get queue depth info from PF */
1472 ret = hns3vf_get_queue_depth(hw);
1476 /* Get user defined VF MAC addr from PF */
1477 ret = hns3vf_get_host_mac_addr(hw);
1481 ret = hns3vf_get_port_base_vlan_filter_state(hw);
1485 /* Get tc configuration from PF */
1486 return hns3vf_get_tc_info(hw);
1490 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1493 struct hns3_hw *hw = &hns->hw;
1495 if (nb_rx_q < hw->num_tc) {
1496 hns3_err(hw, "number of Rx queues(%u) is less than tcs(%u).",
1497 nb_rx_q, hw->num_tc);
1501 if (nb_tx_q < hw->num_tc) {
1502 hns3_err(hw, "number of Tx queues(%u) is less than tcs(%u).",
1503 nb_tx_q, hw->num_tc);
1507 return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1511 hns3vf_request_link_info(struct hns3_hw *hw)
1513 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1518 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1521 send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1522 vf->req_link_info_cnt > 0;
1526 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1527 &resp_msg, sizeof(resp_msg));
1529 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1533 if (vf->req_link_info_cnt > 0)
1534 vf->req_link_info_cnt--;
1538 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1539 uint32_t link_speed, uint8_t link_duplex)
1541 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1542 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1543 struct hns3_mac *mac = &hw->mac;
1547 * PF kernel driver may push link status when VF driver is in resetting,
1548 * driver will stop polling job in this case, after resetting done
1549 * driver will start polling job again.
1550 * When polling job started, driver will get initial link status by
1551 * sending request to PF kernel driver, then could update link status by
1552 * process PF kernel driver's link status mailbox message.
1554 if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1557 if (hw->adapter_state != HNS3_NIC_STARTED)
1560 mac->link_status = link_status;
1561 mac->link_speed = link_speed;
1562 mac->link_duplex = link_duplex;
1563 ret = hns3vf_dev_link_update(dev, 0);
1564 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1565 hns3_start_report_lse(dev);
1569 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1571 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1572 struct hns3_hw *hw = &hns->hw;
1573 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1574 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1575 uint8_t is_kill = on ? 0 : 1;
1577 msg_data[0] = is_kill;
1578 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1579 memcpy(&msg_data[3], &proto, sizeof(proto));
1581 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1582 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1587 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1589 struct hns3_adapter *hns = dev->data->dev_private;
1590 struct hns3_hw *hw = &hns->hw;
1593 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1595 "vf set vlan id failed during resetting, vlan_id =%u",
1599 rte_spinlock_lock(&hw->lock);
1600 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1601 rte_spinlock_unlock(&hw->lock);
1603 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1610 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1615 msg_data = enable ? 1 : 0;
1616 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1617 &msg_data, sizeof(msg_data), false, NULL, 0);
1619 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1625 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1627 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1628 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1629 unsigned int tmp_mask;
1632 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1633 hns3_err(hw, "vf set vlan offload failed during resetting, "
1634 "mask = 0x%x", mask);
1638 tmp_mask = (unsigned int)mask;
1639 /* Vlan stripping setting */
1640 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1641 rte_spinlock_lock(&hw->lock);
1642 /* Enable or disable VLAN stripping */
1643 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1644 ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1646 ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1647 rte_spinlock_unlock(&hw->lock);
1654 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1656 struct rte_vlan_filter_conf *vfc;
1657 struct hns3_hw *hw = &hns->hw;
1664 vfc = &hw->data->vlan_filter_conf;
1665 for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1666 if (vfc->ids[i] == 0)
1671 * 64 means the num bits of ids, one bit corresponds to
1675 /* count trailing zeroes */
1676 vbit = ~ids & (ids - 1);
1677 /* clear least significant bit set */
1678 ids ^= (ids ^ (ids - 1)) ^ vbit;
1683 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1686 "VF handle vlan table failed, ret =%d, on = %d",
1697 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1699 return hns3vf_handle_all_vlan_table(hns, 0);
1703 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1705 struct hns3_hw *hw = &hns->hw;
1706 struct rte_eth_conf *dev_conf;
1710 dev_conf = &hw->data->dev_conf;
1711 en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1713 ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1715 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1721 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1723 struct hns3_adapter *hns = dev->data->dev_private;
1724 struct rte_eth_dev_data *data = dev->data;
1725 struct hns3_hw *hw = &hns->hw;
1728 if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1729 data->dev_conf.txmode.hw_vlan_reject_untagged ||
1730 data->dev_conf.txmode.hw_vlan_insert_pvid) {
1731 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1732 "or hw_vlan_insert_pvid is not support!");
1735 /* Apply vlan offload setting */
1736 ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1738 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1744 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1748 msg_data = alive ? 1 : 0;
1749 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1750 sizeof(msg_data), false, NULL, 0);
1754 hns3vf_keep_alive_handler(void *param)
1756 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1757 struct hns3_adapter *hns = eth_dev->data->dev_private;
1758 struct hns3_hw *hw = &hns->hw;
1762 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1763 false, &respmsg, sizeof(uint8_t));
1765 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1768 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1773 hns3vf_service_handler(void *param)
1775 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1776 struct hns3_adapter *hns = eth_dev->data->dev_private;
1777 struct hns3_hw *hw = &hns->hw;
1780 * The query link status and reset processing are executed in the
1781 * interrupt thread. When the IMP reset occurs, IMP will not respond,
1782 * and the query operation will timeout after 30ms. In the case of
1783 * multiple PF/VFs, each query failure timeout causes the IMP reset
1784 * interrupt to fail to respond within 100ms.
1785 * Before querying the link status, check whether there is a reset
1786 * pending, and if so, abandon the query.
1788 if (!hns3vf_is_reset_pending(hns))
1789 hns3vf_request_link_info(hw);
1791 hns3_warn(hw, "Cancel the query when reset is pending");
1793 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1798 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1800 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT 3
1802 struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1804 if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1805 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1807 __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1809 hns3vf_service_handler(dev);
1813 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1815 struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1817 rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1819 __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1823 hns3_query_vf_resource(struct hns3_hw *hw)
1825 struct hns3_vf_res_cmd *req;
1826 struct hns3_cmd_desc desc;
1830 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1831 ret = hns3_cmd_send(hw, &desc, 1);
1833 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1837 req = (struct hns3_vf_res_cmd *)desc.data;
1838 num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1839 HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1840 if (num_msi < HNS3_MIN_VECTOR_NUM) {
1841 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1842 num_msi, HNS3_MIN_VECTOR_NUM);
1846 hw->num_msi = num_msi;
1852 hns3vf_init_hardware(struct hns3_adapter *hns)
1854 struct hns3_hw *hw = &hns->hw;
1855 uint16_t mtu = hw->data->mtu;
1858 ret = hns3vf_set_promisc_mode(hw, true, false, false);
1862 ret = hns3vf_config_mtu(hw, mtu);
1864 goto err_init_hardware;
1866 ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1868 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1869 goto err_init_hardware;
1872 ret = hns3_config_gro(hw, false);
1874 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1875 goto err_init_hardware;
1879 * In the initialization clearing the all hardware mapping relationship
1880 * configurations between queues and interrupt vectors is needed, so
1881 * some error caused by the residual configurations, such as the
1882 * unexpected interrupt, can be avoid.
1884 ret = hns3vf_init_ring_with_vector(hw);
1886 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1887 goto err_init_hardware;
1890 ret = hns3vf_set_alive(hw, true);
1892 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1893 goto err_init_hardware;
1899 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1904 hns3vf_clear_vport_list(struct hns3_hw *hw)
1906 return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1907 HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1912 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1914 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1915 struct hns3_adapter *hns = eth_dev->data->dev_private;
1916 struct hns3_hw *hw = &hns->hw;
1919 PMD_INIT_FUNC_TRACE();
1921 /* Get hardware io base address from pcie BAR2 IO space */
1922 hw->io_base = pci_dev->mem_resource[2].addr;
1924 /* Firmware command queue initialize */
1925 ret = hns3_cmd_init_queue(hw);
1927 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1928 goto err_cmd_init_queue;
1931 /* Firmware command initialize */
1932 ret = hns3_cmd_init(hw);
1934 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1938 /* Get VF resource */
1939 ret = hns3_query_vf_resource(hw);
1943 rte_spinlock_init(&hw->mbx_resp.lock);
1945 hns3vf_clear_event_cause(hw, 0);
1947 ret = rte_intr_callback_register(&pci_dev->intr_handle,
1948 hns3vf_interrupt_handler, eth_dev);
1950 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1951 goto err_intr_callback_register;
1954 /* Enable interrupt */
1955 rte_intr_enable(&pci_dev->intr_handle);
1956 hns3vf_enable_irq0(hw);
1958 /* Get configuration from PF */
1959 ret = hns3vf_get_configuration(hw);
1961 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1962 goto err_get_config;
1965 ret = hns3_tqp_stats_init(hw);
1967 goto err_get_config;
1969 /* Hardware statistics of imissed registers cleared. */
1970 ret = hns3_update_imissed_stats(hw, true);
1972 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1973 goto err_set_tc_queue;
1976 ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1978 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1979 goto err_set_tc_queue;
1982 ret = hns3vf_clear_vport_list(hw);
1984 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1985 goto err_set_tc_queue;
1988 ret = hns3vf_init_hardware(hns);
1990 goto err_set_tc_queue;
1992 hns3_rss_set_default_args(hw);
1997 hns3_tqp_stats_uninit(hw);
2000 hns3vf_disable_irq0(hw);
2001 rte_intr_disable(&pci_dev->intr_handle);
2002 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
2004 err_intr_callback_register:
2006 hns3_cmd_uninit(hw);
2007 hns3_cmd_destroy_queue(hw);
2015 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
2017 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2018 struct hns3_adapter *hns = eth_dev->data->dev_private;
2019 struct hns3_hw *hw = &hns->hw;
2021 PMD_INIT_FUNC_TRACE();
2023 hns3_rss_uninit(hns);
2024 (void)hns3_config_gro(hw, false);
2025 (void)hns3vf_set_alive(hw, false);
2026 (void)hns3vf_set_promisc_mode(hw, false, false, false);
2027 hns3_tqp_stats_uninit(hw);
2028 hns3vf_disable_irq0(hw);
2029 rte_intr_disable(&pci_dev->intr_handle);
2030 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
2032 hns3_cmd_uninit(hw);
2033 hns3_cmd_destroy_queue(hw);
2038 hns3vf_do_stop(struct hns3_adapter *hns)
2040 struct hns3_hw *hw = &hns->hw;
2043 hw->mac.link_status = ETH_LINK_DOWN;
2046 * The "hns3vf_do_stop" function will also be called by .stop_service to
2047 * prepare reset. At the time of global or IMP reset, the command cannot
2048 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
2049 * accessed during the reset process. So the mbuf can not be released
2050 * during reset and is required to be released after the reset is
2053 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)
2054 hns3_dev_release_mbufs(hns);
2056 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
2057 hns3vf_configure_mac_addr(hns, true);
2058 ret = hns3_reset_all_tqps(hns);
2060 hns3_err(hw, "failed to reset all queues ret = %d",
2069 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
2071 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2072 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2073 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2074 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2075 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2078 if (dev->data->dev_conf.intr_conf.rxq == 0)
2081 /* unmap the ring with vector */
2082 if (rte_intr_allow_others(intr_handle)) {
2083 vec = RTE_INTR_VEC_RXTX_OFFSET;
2084 base = RTE_INTR_VEC_RXTX_OFFSET;
2086 if (rte_intr_dp_is_en(intr_handle)) {
2087 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2088 (void)hns3vf_bind_ring_with_vector(hw, vec, false,
2091 if (vec < base + intr_handle->nb_efd - 1)
2095 /* Clean datapath event and queue/vec mapping */
2096 rte_intr_efd_disable(intr_handle);
2097 if (intr_handle->intr_vec) {
2098 rte_free(intr_handle->intr_vec);
2099 intr_handle->intr_vec = NULL;
2104 hns3vf_dev_stop(struct rte_eth_dev *dev)
2106 struct hns3_adapter *hns = dev->data->dev_private;
2107 struct hns3_hw *hw = &hns->hw;
2109 PMD_INIT_FUNC_TRACE();
2110 dev->data->dev_started = 0;
2112 hw->adapter_state = HNS3_NIC_STOPPING;
2113 hns3_set_rxtx_function(dev);
2115 /* Disable datapath on secondary process. */
2116 hns3_mp_req_stop_rxtx(dev);
2117 /* Prevent crashes when queues are still in use. */
2118 rte_delay_ms(hw->tqps_num);
2120 rte_spinlock_lock(&hw->lock);
2121 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
2123 hns3vf_do_stop(hns);
2124 hns3vf_unmap_rx_interrupt(dev);
2125 hw->adapter_state = HNS3_NIC_CONFIGURED;
2127 hns3_rx_scattered_reset(dev);
2128 hns3vf_stop_poll_job(dev);
2129 hns3_stop_report_lse(dev);
2130 rte_spinlock_unlock(&hw->lock);
2136 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
2138 struct hns3_adapter *hns = eth_dev->data->dev_private;
2139 struct hns3_hw *hw = &hns->hw;
2142 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2143 rte_free(eth_dev->process_private);
2144 eth_dev->process_private = NULL;
2148 if (hw->adapter_state == HNS3_NIC_STARTED)
2149 ret = hns3vf_dev_stop(eth_dev);
2151 hw->adapter_state = HNS3_NIC_CLOSING;
2152 hns3_reset_abort(hns);
2153 hw->adapter_state = HNS3_NIC_CLOSED;
2154 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
2155 hns3vf_configure_all_mc_mac_addr(hns, true);
2156 hns3vf_remove_all_vlan_table(hns);
2157 hns3vf_uninit_vf(eth_dev);
2158 hns3_free_all_queues(eth_dev);
2159 rte_free(hw->reset.wait_data);
2160 rte_free(eth_dev->process_private);
2161 eth_dev->process_private = NULL;
2162 hns3_mp_uninit_primary();
2163 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
2169 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2172 struct hns3_adapter *hns = eth_dev->data->dev_private;
2173 struct hns3_hw *hw = &hns->hw;
2174 uint32_t version = hw->fw_version;
2177 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2178 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2179 HNS3_FW_VERSION_BYTE3_S),
2180 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2181 HNS3_FW_VERSION_BYTE2_S),
2182 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2183 HNS3_FW_VERSION_BYTE1_S),
2184 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2185 HNS3_FW_VERSION_BYTE0_S));
2186 ret += 1; /* add the size of '\0' */
2187 if (fw_size < (uint32_t)ret)
2194 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2195 __rte_unused int wait_to_complete)
2197 struct hns3_adapter *hns = eth_dev->data->dev_private;
2198 struct hns3_hw *hw = &hns->hw;
2199 struct hns3_mac *mac = &hw->mac;
2200 struct rte_eth_link new_link;
2202 memset(&new_link, 0, sizeof(new_link));
2203 switch (mac->link_speed) {
2204 case ETH_SPEED_NUM_10M:
2205 case ETH_SPEED_NUM_100M:
2206 case ETH_SPEED_NUM_1G:
2207 case ETH_SPEED_NUM_10G:
2208 case ETH_SPEED_NUM_25G:
2209 case ETH_SPEED_NUM_40G:
2210 case ETH_SPEED_NUM_50G:
2211 case ETH_SPEED_NUM_100G:
2212 case ETH_SPEED_NUM_200G:
2213 new_link.link_speed = mac->link_speed;
2216 if (mac->link_status)
2217 new_link.link_speed = ETH_SPEED_NUM_UNKNOWN;
2219 new_link.link_speed = ETH_SPEED_NUM_NONE;
2223 new_link.link_duplex = mac->link_duplex;
2224 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2225 new_link.link_autoneg =
2226 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2228 return rte_eth_linkstatus_set(eth_dev, &new_link);
2232 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2234 struct hns3_hw *hw = &hns->hw;
2235 uint16_t nb_rx_q = hw->data->nb_rx_queues;
2236 uint16_t nb_tx_q = hw->data->nb_tx_queues;
2239 ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2243 hns3_enable_rxd_adv_layout(hw);
2245 ret = hns3_init_queues(hns, reset_queue);
2247 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2253 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2255 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2256 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2257 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2258 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2259 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2260 uint32_t intr_vector;
2265 * hns3 needs a separate interrupt to be used as event interrupt which
2266 * could not be shared with task queue pair, so KERNEL drivers need
2267 * support multiple interrupt vectors.
2269 if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2270 !rte_intr_cap_multiple(intr_handle))
2273 rte_intr_disable(intr_handle);
2274 intr_vector = hw->used_rx_queues;
2275 /* It creates event fd for each intr vector when MSIX is used */
2276 if (rte_intr_efd_enable(intr_handle, intr_vector))
2279 if (intr_handle->intr_vec == NULL) {
2280 intr_handle->intr_vec =
2281 rte_zmalloc("intr_vec",
2282 hw->used_rx_queues * sizeof(int), 0);
2283 if (intr_handle->intr_vec == NULL) {
2284 hns3_err(hw, "Failed to allocate %u rx_queues"
2285 " intr_vec", hw->used_rx_queues);
2287 goto vf_alloc_intr_vec_error;
2291 if (rte_intr_allow_others(intr_handle)) {
2292 vec = RTE_INTR_VEC_RXTX_OFFSET;
2293 base = RTE_INTR_VEC_RXTX_OFFSET;
2296 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2297 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2298 HNS3_RING_TYPE_RX, q_id);
2300 goto vf_bind_vector_error;
2301 intr_handle->intr_vec[q_id] = vec;
2303 * If there are not enough efds (e.g. not enough interrupt),
2304 * remaining queues will be bond to the last interrupt.
2306 if (vec < base + intr_handle->nb_efd - 1)
2309 rte_intr_enable(intr_handle);
2312 vf_bind_vector_error:
2313 free(intr_handle->intr_vec);
2314 intr_handle->intr_vec = NULL;
2315 vf_alloc_intr_vec_error:
2316 rte_intr_efd_disable(intr_handle);
2321 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2323 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2324 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2325 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2329 if (dev->data->dev_conf.intr_conf.rxq == 0)
2332 if (rte_intr_dp_is_en(intr_handle)) {
2333 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2334 ret = hns3vf_bind_ring_with_vector(hw,
2335 intr_handle->intr_vec[q_id], true,
2336 HNS3_RING_TYPE_RX, q_id);
2346 hns3vf_restore_filter(struct rte_eth_dev *dev)
2348 hns3_restore_rss_filter(dev);
2352 hns3vf_dev_start(struct rte_eth_dev *dev)
2354 struct hns3_adapter *hns = dev->data->dev_private;
2355 struct hns3_hw *hw = &hns->hw;
2358 PMD_INIT_FUNC_TRACE();
2359 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2362 rte_spinlock_lock(&hw->lock);
2363 hw->adapter_state = HNS3_NIC_STARTING;
2364 ret = hns3vf_do_start(hns, true);
2366 hw->adapter_state = HNS3_NIC_CONFIGURED;
2367 rte_spinlock_unlock(&hw->lock);
2370 ret = hns3vf_map_rx_interrupt(dev);
2372 goto map_rx_inter_err;
2375 * There are three register used to control the status of a TQP
2376 * (contains a pair of Tx queue and Rx queue) in the new version network
2377 * engine. One is used to control the enabling of Tx queue, the other is
2378 * used to control the enabling of Rx queue, and the last is the master
2379 * switch used to control the enabling of the tqp. The Tx register and
2380 * TQP register must be enabled at the same time to enable a Tx queue.
2381 * The same applies to the Rx queue. For the older network enginem, this
2382 * function only refresh the enabled flag, and it is used to update the
2383 * status of queue in the dpdk framework.
2385 ret = hns3_start_all_txqs(dev);
2387 goto map_rx_inter_err;
2389 ret = hns3_start_all_rxqs(dev);
2391 goto start_all_rxqs_fail;
2393 hw->adapter_state = HNS3_NIC_STARTED;
2394 rte_spinlock_unlock(&hw->lock);
2396 hns3_rx_scattered_calc(dev);
2397 hns3_set_rxtx_function(dev);
2398 hns3_mp_req_start_rxtx(dev);
2400 hns3vf_restore_filter(dev);
2402 /* Enable interrupt of all rx queues before enabling queues */
2403 hns3_dev_all_rx_queue_intr_enable(hw, true);
2404 hns3_start_tqps(hw);
2406 if (dev->data->dev_conf.intr_conf.lsc != 0)
2407 hns3vf_dev_link_update(dev, 0);
2408 hns3vf_start_poll_job(dev);
2412 start_all_rxqs_fail:
2413 hns3_stop_all_txqs(dev);
2415 (void)hns3vf_do_stop(hns);
2416 hw->adapter_state = HNS3_NIC_CONFIGURED;
2417 rte_spinlock_unlock(&hw->lock);
2423 is_vf_reset_done(struct hns3_hw *hw)
2425 #define HNS3_FUN_RST_ING_BITS \
2426 (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2427 BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2428 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2429 BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2433 if (hw->reset.level == HNS3_VF_RESET) {
2434 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2435 if (val & HNS3_VF_RST_ING_BIT)
2438 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2439 if (val & HNS3_FUN_RST_ING_BITS)
2446 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2448 struct hns3_hw *hw = &hns->hw;
2449 enum hns3_reset_level reset;
2452 * According to the protocol of PCIe, FLR to a PF device resets the PF
2453 * state as well as the SR-IOV extended capability including VF Enable
2454 * which means that VFs no longer exist.
2456 * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2457 * is in FLR stage, the register state of VF device is not reliable,
2458 * so register states detection can not be carried out. In this case,
2459 * we just ignore the register states and return false to indicate that
2460 * there are no other reset states that need to be processed by driver.
2462 if (hw->reset.level == HNS3_VF_FULL_RESET)
2465 /* Check the registers to confirm whether there is reset pending */
2466 hns3vf_check_event_cause(hns, NULL);
2467 reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2468 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2469 hns3_warn(hw, "High level reset %d is pending", reset);
2476 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2478 struct hns3_hw *hw = &hns->hw;
2479 struct hns3_wait_data *wait_data = hw->reset.wait_data;
2482 if (wait_data->result == HNS3_WAIT_SUCCESS) {
2484 * After vf reset is ready, the PF may not have completed
2485 * the reset processing. The vf sending mbox to PF may fail
2486 * during the pf reset, so it is better to add extra delay.
2488 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2489 hw->reset.level == HNS3_FLR_RESET)
2491 /* Reset retry process, no need to add extra delay. */
2492 if (hw->reset.attempts)
2494 if (wait_data->check_completion == NULL)
2497 wait_data->check_completion = NULL;
2498 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2499 wait_data->count = 1;
2500 wait_data->result = HNS3_WAIT_REQUEST;
2501 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2503 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2505 } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2506 gettimeofday(&tv, NULL);
2507 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2508 tv.tv_sec, tv.tv_usec);
2510 } else if (wait_data->result == HNS3_WAIT_REQUEST)
2513 wait_data->hns = hns;
2514 wait_data->check_completion = is_vf_reset_done;
2515 wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2516 HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2517 wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2518 wait_data->count = HNS3VF_RESET_WAIT_CNT;
2519 wait_data->result = HNS3_WAIT_REQUEST;
2520 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2525 hns3vf_prepare_reset(struct hns3_adapter *hns)
2527 struct hns3_hw *hw = &hns->hw;
2530 if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2531 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2536 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2542 hns3vf_stop_service(struct hns3_adapter *hns)
2544 struct hns3_hw *hw = &hns->hw;
2545 struct rte_eth_dev *eth_dev;
2547 eth_dev = &rte_eth_devices[hw->data->port_id];
2548 if (hw->adapter_state == HNS3_NIC_STARTED) {
2550 * Make sure call update link status before hns3vf_stop_poll_job
2551 * because update link status depend on polling job exist.
2553 hns3vf_update_link_status(hw, ETH_LINK_DOWN, hw->mac.link_speed,
2554 hw->mac.link_duplex);
2555 hns3vf_stop_poll_job(eth_dev);
2557 hw->mac.link_status = ETH_LINK_DOWN;
2559 hns3_set_rxtx_function(eth_dev);
2561 /* Disable datapath on secondary process. */
2562 hns3_mp_req_stop_rxtx(eth_dev);
2563 rte_delay_ms(hw->tqps_num);
2565 rte_spinlock_lock(&hw->lock);
2566 if (hw->adapter_state == HNS3_NIC_STARTED ||
2567 hw->adapter_state == HNS3_NIC_STOPPING) {
2568 hns3_enable_all_queues(hw, false);
2569 hns3vf_do_stop(hns);
2570 hw->reset.mbuf_deferred_free = true;
2572 hw->reset.mbuf_deferred_free = false;
2575 * It is cumbersome for hardware to pick-and-choose entries for deletion
2576 * from table space. Hence, for function reset software intervention is
2577 * required to delete the entries.
2579 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2580 hns3vf_configure_all_mc_mac_addr(hns, true);
2581 rte_spinlock_unlock(&hw->lock);
2587 hns3vf_start_service(struct hns3_adapter *hns)
2589 struct hns3_hw *hw = &hns->hw;
2590 struct rte_eth_dev *eth_dev;
2592 eth_dev = &rte_eth_devices[hw->data->port_id];
2593 hns3_set_rxtx_function(eth_dev);
2594 hns3_mp_req_start_rxtx(eth_dev);
2595 if (hw->adapter_state == HNS3_NIC_STARTED) {
2596 hns3vf_start_poll_job(eth_dev);
2598 /* Enable interrupt of all rx queues before enabling queues */
2599 hns3_dev_all_rx_queue_intr_enable(hw, true);
2601 * Enable state of each rxq and txq will be recovered after
2602 * reset, so we need to restore them before enable all tqps;
2604 hns3_restore_tqp_enable_state(hw);
2606 * When finished the initialization, enable queues to receive
2607 * and transmit packets.
2609 hns3_enable_all_queues(hw, true);
2616 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2618 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2619 struct rte_ether_addr *hw_mac;
2623 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2624 * on the host by "ip link set ..." command. If the hns3 PF kernel
2625 * ethdev driver sets the MAC address for VF device after the
2626 * initialization of the related VF device, the PF driver will notify
2627 * VF driver to reset VF device to make the new MAC address effective
2628 * immediately. The hns3 VF PMD driver should check whether the MAC
2629 * address has been changed by the PF kernel ethdev driver, if changed
2630 * VF driver should configure hardware using the new MAC address in the
2631 * recovering hardware configuration stage of the reset process.
2633 ret = hns3vf_get_host_mac_addr(hw);
2637 hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2638 ret = rte_is_zero_ether_addr(hw_mac);
2640 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2642 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2644 rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2645 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2646 &hw->data->mac_addrs[0]);
2647 hns3_warn(hw, "Default MAC address has been changed to:"
2648 " %s by the host PF kernel ethdev driver",
2657 hns3vf_restore_conf(struct hns3_adapter *hns)
2659 struct hns3_hw *hw = &hns->hw;
2662 ret = hns3vf_check_default_mac_change(hw);
2666 ret = hns3vf_configure_mac_addr(hns, false);
2670 ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2674 ret = hns3vf_restore_promisc(hns);
2676 goto err_vlan_table;
2678 ret = hns3vf_restore_vlan_conf(hns);
2680 goto err_vlan_table;
2682 ret = hns3vf_get_port_base_vlan_filter_state(hw);
2684 goto err_vlan_table;
2686 ret = hns3vf_restore_rx_interrupt(hw);
2688 goto err_vlan_table;
2690 ret = hns3_restore_gro_conf(hw);
2692 goto err_vlan_table;
2694 if (hw->adapter_state == HNS3_NIC_STARTED) {
2695 ret = hns3vf_do_start(hns, false);
2697 goto err_vlan_table;
2698 hns3_info(hw, "hns3vf dev restart successful!");
2699 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2700 hw->adapter_state = HNS3_NIC_CONFIGURED;
2704 hns3vf_configure_all_mc_mac_addr(hns, true);
2706 hns3vf_configure_mac_addr(hns, true);
2710 static enum hns3_reset_level
2711 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2713 enum hns3_reset_level reset_level;
2715 /* return the highest priority reset level amongst all */
2716 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2717 reset_level = HNS3_VF_RESET;
2718 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2719 reset_level = HNS3_VF_FULL_RESET;
2720 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2721 reset_level = HNS3_VF_PF_FUNC_RESET;
2722 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2723 reset_level = HNS3_VF_FUNC_RESET;
2724 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2725 reset_level = HNS3_FLR_RESET;
2727 reset_level = HNS3_NONE_RESET;
2729 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2730 return HNS3_NONE_RESET;
2736 hns3vf_reset_service(void *param)
2738 struct hns3_adapter *hns = (struct hns3_adapter *)param;
2739 struct hns3_hw *hw = &hns->hw;
2740 enum hns3_reset_level reset_level;
2741 struct timeval tv_delta;
2742 struct timeval tv_start;
2747 * The interrupt is not triggered within the delay time.
2748 * The interrupt may have been lost. It is necessary to handle
2749 * the interrupt to recover from the error.
2751 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2752 SCHEDULE_DEFERRED) {
2753 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2755 hns3_err(hw, "Handling interrupts in delayed tasks");
2756 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2757 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2758 if (reset_level == HNS3_NONE_RESET) {
2759 hns3_err(hw, "No reset level is set, try global reset");
2760 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2763 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2766 * Hardware reset has been notified, we now have to poll & check if
2767 * hardware has actually completed the reset sequence.
2769 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2770 if (reset_level != HNS3_NONE_RESET) {
2771 gettimeofday(&tv_start, NULL);
2772 hns3_reset_process(hns, reset_level);
2773 gettimeofday(&tv, NULL);
2774 timersub(&tv, &tv_start, &tv_delta);
2775 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2776 tv_delta.tv_usec / USEC_PER_MSEC;
2777 if (msec > HNS3_RESET_PROCESS_MS)
2778 hns3_err(hw, "%d handle long time delta %" PRIx64
2779 " ms time=%ld.%.6ld",
2780 hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2785 hns3vf_reinit_dev(struct hns3_adapter *hns)
2787 struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2788 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2789 struct hns3_hw *hw = &hns->hw;
2792 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2793 rte_intr_disable(&pci_dev->intr_handle);
2794 ret = hns3vf_set_bus_master(pci_dev, true);
2796 hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2801 /* Firmware command initialize */
2802 ret = hns3_cmd_init(hw);
2804 hns3_err(hw, "Failed to init cmd: %d", ret);
2808 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2810 * UIO enables msix by writing the pcie configuration space
2811 * vfio_pci enables msix in rte_intr_enable.
2813 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2814 pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2815 if (hns3vf_enable_msix(pci_dev, true))
2816 hns3_err(hw, "Failed to enable msix");
2819 rte_intr_enable(&pci_dev->intr_handle);
2822 ret = hns3_reset_all_tqps(hns);
2824 hns3_err(hw, "Failed to reset all queues: %d", ret);
2828 ret = hns3vf_init_hardware(hns);
2830 hns3_err(hw, "Failed to init hardware: %d", ret);
2837 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2838 .dev_configure = hns3vf_dev_configure,
2839 .dev_start = hns3vf_dev_start,
2840 .dev_stop = hns3vf_dev_stop,
2841 .dev_close = hns3vf_dev_close,
2842 .mtu_set = hns3vf_dev_mtu_set,
2843 .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2844 .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2845 .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2846 .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2847 .stats_get = hns3_stats_get,
2848 .stats_reset = hns3_stats_reset,
2849 .xstats_get = hns3_dev_xstats_get,
2850 .xstats_get_names = hns3_dev_xstats_get_names,
2851 .xstats_reset = hns3_dev_xstats_reset,
2852 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
2853 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2854 .dev_infos_get = hns3vf_dev_infos_get,
2855 .fw_version_get = hns3vf_fw_version_get,
2856 .rx_queue_setup = hns3_rx_queue_setup,
2857 .tx_queue_setup = hns3_tx_queue_setup,
2858 .rx_queue_release = hns3_dev_rx_queue_release,
2859 .tx_queue_release = hns3_dev_tx_queue_release,
2860 .rx_queue_start = hns3_dev_rx_queue_start,
2861 .rx_queue_stop = hns3_dev_rx_queue_stop,
2862 .tx_queue_start = hns3_dev_tx_queue_start,
2863 .tx_queue_stop = hns3_dev_tx_queue_stop,
2864 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
2865 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
2866 .rxq_info_get = hns3_rxq_info_get,
2867 .txq_info_get = hns3_txq_info_get,
2868 .rx_burst_mode_get = hns3_rx_burst_mode_get,
2869 .tx_burst_mode_get = hns3_tx_burst_mode_get,
2870 .mac_addr_add = hns3vf_add_mac_addr,
2871 .mac_addr_remove = hns3vf_remove_mac_addr,
2872 .mac_addr_set = hns3vf_set_default_mac_addr,
2873 .set_mc_addr_list = hns3vf_set_mc_mac_addr_list,
2874 .link_update = hns3vf_dev_link_update,
2875 .rss_hash_update = hns3_dev_rss_hash_update,
2876 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
2877 .reta_update = hns3_dev_rss_reta_update,
2878 .reta_query = hns3_dev_rss_reta_query,
2879 .flow_ops_get = hns3_dev_flow_ops_get,
2880 .vlan_filter_set = hns3vf_vlan_filter_set,
2881 .vlan_offload_set = hns3vf_vlan_offload_set,
2882 .get_reg = hns3_get_regs,
2883 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2884 .tx_done_cleanup = hns3_tx_done_cleanup,
2887 static const struct hns3_reset_ops hns3vf_reset_ops = {
2888 .reset_service = hns3vf_reset_service,
2889 .stop_service = hns3vf_stop_service,
2890 .prepare_reset = hns3vf_prepare_reset,
2891 .wait_hardware_ready = hns3vf_wait_hardware_ready,
2892 .reinit_dev = hns3vf_reinit_dev,
2893 .restore_conf = hns3vf_restore_conf,
2894 .start_service = hns3vf_start_service,
2898 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2900 struct hns3_adapter *hns = eth_dev->data->dev_private;
2901 struct hns3_hw *hw = &hns->hw;
2904 PMD_INIT_FUNC_TRACE();
2906 eth_dev->process_private = (struct hns3_process_private *)
2907 rte_zmalloc_socket("hns3_filter_list",
2908 sizeof(struct hns3_process_private),
2909 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2910 if (eth_dev->process_private == NULL) {
2911 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2915 /* initialize flow filter lists */
2916 hns3_filterlist_init(eth_dev);
2918 hns3_set_rxtx_function(eth_dev);
2919 eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2920 eth_dev->rx_queue_count = hns3_rx_queue_count;
2921 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2922 ret = hns3_mp_init_secondary();
2924 PMD_INIT_LOG(ERR, "Failed to init for secondary "
2925 "process, ret = %d", ret);
2926 goto err_mp_init_secondary;
2929 hw->secondary_cnt++;
2933 ret = hns3_mp_init_primary();
2936 "Failed to init for primary process, ret = %d",
2938 goto err_mp_init_primary;
2941 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2943 hw->data = eth_dev->data;
2944 hns3_parse_devargs(eth_dev);
2946 ret = hns3_reset_init(hw);
2948 goto err_init_reset;
2949 hw->reset.ops = &hns3vf_reset_ops;
2951 ret = hns3vf_init_vf(eth_dev);
2953 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2957 /* Allocate memory for storing MAC addresses */
2958 eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2959 sizeof(struct rte_ether_addr) *
2960 HNS3_VF_UC_MACADDR_NUM, 0);
2961 if (eth_dev->data->mac_addrs == NULL) {
2962 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2963 "to store MAC addresses",
2964 sizeof(struct rte_ether_addr) *
2965 HNS3_VF_UC_MACADDR_NUM);
2967 goto err_rte_zmalloc;
2971 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2972 * on the host by "ip link set ..." command. To avoid some incorrect
2973 * scenes, for example, hns3 VF PMD driver fails to receive and send
2974 * packets after user configure the MAC address by using the
2975 * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2976 * address strategy as the hns3 kernel ethdev driver in the
2977 * initialization. If user configure a MAC address by the ip command
2978 * for VF device, then hns3 VF PMD driver will start with it, otherwise
2979 * start with a random MAC address in the initialization.
2981 if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2982 rte_eth_random_addr(hw->mac.mac_addr);
2983 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2984 ð_dev->data->mac_addrs[0]);
2986 hw->adapter_state = HNS3_NIC_INITIALIZED;
2988 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2990 hns3_err(hw, "Reschedule reset service after dev_init");
2991 hns3_schedule_reset(hns);
2993 /* IMP will wait ready flag before reset */
2994 hns3_notify_reset_ready(hw, false);
2996 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
3001 hns3vf_uninit_vf(eth_dev);
3004 rte_free(hw->reset.wait_data);
3007 hns3_mp_uninit_primary();
3009 err_mp_init_primary:
3010 err_mp_init_secondary:
3011 eth_dev->dev_ops = NULL;
3012 eth_dev->rx_pkt_burst = NULL;
3013 eth_dev->rx_descriptor_status = NULL;
3014 eth_dev->tx_pkt_burst = NULL;
3015 eth_dev->tx_pkt_prepare = NULL;
3016 eth_dev->tx_descriptor_status = NULL;
3017 rte_free(eth_dev->process_private);
3018 eth_dev->process_private = NULL;
3024 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
3026 struct hns3_adapter *hns = eth_dev->data->dev_private;
3027 struct hns3_hw *hw = &hns->hw;
3029 PMD_INIT_FUNC_TRACE();
3031 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3032 rte_free(eth_dev->process_private);
3033 eth_dev->process_private = NULL;
3037 if (hw->adapter_state < HNS3_NIC_CLOSING)
3038 hns3vf_dev_close(eth_dev);
3040 hw->adapter_state = HNS3_NIC_REMOVED;
3045 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3046 struct rte_pci_device *pci_dev)
3048 return rte_eth_dev_pci_generic_probe(pci_dev,
3049 sizeof(struct hns3_adapter),
3054 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
3056 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
3059 static const struct rte_pci_id pci_id_hns3vf_map[] = {
3060 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
3061 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
3062 { .vendor_id = 0, }, /* sentinel */
3065 static struct rte_pci_driver rte_hns3vf_pmd = {
3066 .id_table = pci_id_hns3vf_map,
3067 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3068 .probe = eth_hns3vf_pci_probe,
3069 .remove = eth_hns3vf_pci_remove,
3072 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
3073 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
3074 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
3075 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
3076 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
3077 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common ");