1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
5 #include <linux/pci_regs.h>
7 #include <ethdev_pci.h>
12 #include "hns3_ethdev.h"
13 #include "hns3_logs.h"
14 #include "hns3_rxtx.h"
15 #include "hns3_regs.h"
16 #include "hns3_intr.h"
20 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */
21 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */
23 #define HNS3VF_RESET_WAIT_MS 20
24 #define HNS3VF_RESET_WAIT_CNT 2000
26 /* Reset related Registers */
27 #define HNS3_GLOBAL_RESET_BIT 0
28 #define HNS3_CORE_RESET_BIT 1
29 #define HNS3_IMP_RESET_BIT 2
30 #define HNS3_FUN_RST_ING_B 0
32 enum hns3vf_evt_cause {
33 HNS3VF_VECTOR0_EVENT_RST,
34 HNS3VF_VECTOR0_EVENT_MBX,
35 HNS3VF_VECTOR0_EVENT_OTHER,
38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
44 struct rte_ether_addr *mac_addr);
45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
46 struct rte_ether_addr *mac_addr);
47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
48 __rte_unused int wait_to_complete);
50 /* set PCI bus mastering */
52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
57 ret = rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND);
59 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
65 /* set the master bit */
66 reg |= PCI_COMMAND_MASTER;
68 reg &= ~(PCI_COMMAND_MASTER);
70 return rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND);
74 * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
75 * @cap: the capability
77 * Return the address of the given capability within the PCI capability list.
80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
82 #define MAX_PCIE_CAPABILITY 48
89 ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
91 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
95 if (!(status & PCI_STATUS_CAP_LIST))
98 ttl = MAX_PCIE_CAPABILITY;
99 ret = rte_pci_read_config(device, &pos, sizeof(pos),
100 PCI_CAPABILITY_LIST);
102 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
103 PCI_CAPABILITY_LIST);
107 while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
108 ret = rte_pci_read_config(device, &id, sizeof(id),
109 (pos + PCI_CAP_LIST_ID));
111 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
112 (pos + PCI_CAP_LIST_ID));
122 ret = rte_pci_read_config(device, &pos, sizeof(pos),
123 (pos + PCI_CAP_LIST_NEXT));
125 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
126 (pos + PCI_CAP_LIST_NEXT));
134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
140 pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
142 ret = rte_pci_read_config(device, &control, sizeof(control),
143 (pos + PCI_MSIX_FLAGS));
145 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
146 (pos + PCI_MSIX_FLAGS));
151 control |= PCI_MSIX_FLAGS_ENABLE;
153 control &= ~PCI_MSIX_FLAGS_ENABLE;
154 ret = rte_pci_write_config(device, &control, sizeof(control),
155 (pos + PCI_MSIX_FLAGS));
157 PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
158 (pos + PCI_MSIX_FLAGS));
169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
171 /* mac address was checked by upper level interface */
172 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
175 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
176 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
177 RTE_ETHER_ADDR_LEN, false, NULL, 0);
179 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
181 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
190 /* mac address was checked by upper level interface */
191 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
194 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
195 HNS3_MBX_MAC_VLAN_UC_REMOVE,
196 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
199 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
201 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
208 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
209 struct rte_ether_addr *mac_addr)
211 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
212 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
213 struct rte_ether_addr *old_addr;
214 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
215 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
219 * It has been guaranteed that input parameter named mac_addr is valid
220 * address in the rte layer of DPDK framework.
222 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
223 rte_spinlock_lock(&hw->lock);
224 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
225 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
228 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
229 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
230 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
233 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
234 * driver. When user has configured a MAC address for VF device
235 * by "ip link set ..." command based on the PF device, the hns3
236 * PF kernel ethdev driver does not allow VF driver to request
237 * reconfiguring a different default MAC address, and return
238 * -EPREM to VF driver through mailbox.
241 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
243 hns3_warn(hw, "Has permanet mac addr(%s) for vf",
246 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
248 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
253 rte_ether_addr_copy(mac_addr,
254 (struct rte_ether_addr *)hw->mac.mac_addr);
255 rte_spinlock_unlock(&hw->lock);
261 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
262 struct rte_ether_addr *mac_addr)
264 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
267 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
268 HNS3_MBX_MAC_VLAN_MC_ADD,
269 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
272 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
274 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
282 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
283 struct rte_ether_addr *mac_addr)
285 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
288 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
289 HNS3_MBX_MAC_VLAN_MC_REMOVE,
290 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
293 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
295 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
303 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
304 bool en_uc_pmc, bool en_mc_pmc)
306 struct hns3_mbx_vf_to_pf_cmd *req;
307 struct hns3_cmd_desc desc;
310 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
313 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
314 * so there are some features for promiscuous/allmulticast mode in hns3
315 * VF PMD driver as below:
316 * 1. The promiscuous/allmulticast mode can be configured successfully
317 * only based on the trusted VF device. If based on the non trusted
318 * VF device, configuring promiscuous/allmulticast mode will fail.
319 * The hns3 VF device can be confiruged as trusted device by hns3 PF
320 * kernel ethdev driver on the host by the following command:
321 * "ip link set <eth num> vf <vf id> turst on"
322 * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
323 * driver can receive the ingress and outgoing traffic. In the words,
324 * all the ingress packets, all the packets sent from the PF and
325 * other VFs on the same physical port.
326 * 3. Note: Because of the hardware constraints, By default vlan filter
327 * is enabled and couldn't be turned off based on VF device, so vlan
328 * filter is still effective even in promiscuous mode. If upper
329 * applications don't call rte_eth_dev_vlan_filter API function to
330 * set vlan based on VF device, hns3 VF PMD driver will can't receive
331 * the packets with vlan tag in promiscuoue mode.
333 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
334 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
335 req->msg[1] = en_bc_pmc ? 1 : 0;
336 req->msg[2] = en_uc_pmc ? 1 : 0;
337 req->msg[3] = en_mc_pmc ? 1 : 0;
338 req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
340 ret = hns3_cmd_send(hw, &desc, 1);
342 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
348 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
350 struct hns3_adapter *hns = dev->data->dev_private;
351 struct hns3_hw *hw = &hns->hw;
354 ret = hns3vf_set_promisc_mode(hw, true, true, true);
356 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
362 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
364 bool allmulti = dev->data->all_multicast ? true : false;
365 struct hns3_adapter *hns = dev->data->dev_private;
366 struct hns3_hw *hw = &hns->hw;
369 ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
371 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
377 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
379 struct hns3_adapter *hns = dev->data->dev_private;
380 struct hns3_hw *hw = &hns->hw;
383 if (dev->data->promiscuous)
386 ret = hns3vf_set_promisc_mode(hw, true, false, true);
388 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
394 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
396 struct hns3_adapter *hns = dev->data->dev_private;
397 struct hns3_hw *hw = &hns->hw;
400 if (dev->data->promiscuous)
403 ret = hns3vf_set_promisc_mode(hw, true, false, false);
405 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
411 hns3vf_restore_promisc(struct hns3_adapter *hns)
413 struct hns3_hw *hw = &hns->hw;
414 bool allmulti = hw->data->all_multicast ? true : false;
416 if (hw->data->promiscuous)
417 return hns3vf_set_promisc_mode(hw, true, true, true);
419 return hns3vf_set_promisc_mode(hw, true, false, allmulti);
423 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
424 bool mmap, enum hns3_ring_type queue_type,
427 struct hns3_vf_bind_vector_msg bind_msg;
432 memset(&bind_msg, 0, sizeof(bind_msg));
433 code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
434 HNS3_MBX_UNMAP_RING_TO_VECTOR;
435 bind_msg.vector_id = vector_id;
437 if (queue_type == HNS3_RING_TYPE_RX)
438 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
440 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
442 bind_msg.param[0].ring_type = queue_type;
443 bind_msg.ring_num = 1;
444 bind_msg.param[0].tqp_index = queue_id;
445 op_str = mmap ? "Map" : "Unmap";
446 ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
447 sizeof(bind_msg), false, NULL, 0);
449 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
450 op_str, queue_id, bind_msg.vector_id, ret);
456 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
463 * In hns3 network engine, vector 0 is always the misc interrupt of this
464 * function, vector 1~N can be used respectively for the queues of the
465 * function. Tx and Rx queues with the same number share the interrupt
466 * vector. In the initialization clearing the all hardware mapping
467 * relationship configurations between queues and interrupt vectors is
468 * needed, so some error caused by the residual configurations, such as
469 * the unexpected Tx interrupt, can be avoid.
471 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
472 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
473 vec = vec - 1; /* the last interrupt is reserved */
474 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
475 for (i = 0; i < hw->intr_tqps_num; i++) {
477 * Set gap limiter/rate limiter/quanity limiter algorithm
478 * configuration for interrupt coalesce of queue's interrupt.
480 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
481 HNS3_TQP_INTR_GL_DEFAULT);
482 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
483 HNS3_TQP_INTR_GL_DEFAULT);
484 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
486 * QL(quantity limiter) is not used currently, just set 0 to
489 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
491 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
492 HNS3_RING_TYPE_TX, i);
494 PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
495 "vector: %u, ret=%d", i, vec, ret);
499 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
500 HNS3_RING_TYPE_RX, i);
502 PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
503 "vector: %u, ret=%d", i, vec, ret);
512 hns3vf_dev_configure(struct rte_eth_dev *dev)
514 struct hns3_adapter *hns = dev->data->dev_private;
515 struct hns3_hw *hw = &hns->hw;
516 struct rte_eth_conf *conf = &dev->data->dev_conf;
517 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
518 uint16_t nb_rx_q = dev->data->nb_rx_queues;
519 uint16_t nb_tx_q = dev->data->nb_tx_queues;
520 struct rte_eth_rss_conf rss_conf;
524 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
527 * Some versions of hardware network engine does not support
528 * individually enable/disable/reset the Tx or Rx queue. These devices
529 * must enable/disable/reset Tx and Rx queues at the same time. When the
530 * numbers of Tx queues allocated by upper applications are not equal to
531 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
532 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
533 * work as usual. But these fake queues are imperceptible, and can not
534 * be used by upper applications.
536 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
538 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
539 hw->cfg_max_queues = 0;
543 hw->adapter_state = HNS3_NIC_CONFIGURING;
544 if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
545 hns3_err(hw, "setting link speed/duplex not supported");
550 /* When RSS is not configured, redirect the packet queue 0 */
551 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
552 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
553 hw->rss_dis_flag = false;
554 rss_conf = conf->rx_adv_conf.rss_conf;
555 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
560 ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
564 ret = hns3vf_dev_configure_vlan(dev);
568 /* config hardware GRO */
569 gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
570 ret = hns3_config_gro(hw, gro_en);
574 hns3_init_rx_ptype_tble(dev);
576 hw->adapter_state = HNS3_NIC_CONFIGURED;
580 hw->cfg_max_queues = 0;
581 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
582 hw->adapter_state = HNS3_NIC_INITIALIZED;
588 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
592 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
593 sizeof(mtu), true, NULL, 0);
595 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
601 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
603 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
604 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
608 * The hns3 PF/VF devices on the same port share the hardware MTU
609 * configuration. Currently, we send mailbox to inform hns3 PF kernel
610 * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
611 * driver, there is no need to stop the port for hns3 VF device, and the
612 * MTU value issued by hns3 VF PMD driver must be less than or equal to
615 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
616 hns3_err(hw, "Failed to set mtu during resetting");
621 * when Rx of scattered packets is off, we have some possibility of
622 * using vector Rx process function or simple Rx functions in hns3 PMD
623 * driver. If the input MTU is increased and the maximum length of
624 * received packets is greater than the length of a buffer for Rx
625 * packet, the hardware network engine needs to use multiple BDs and
626 * buffers to store these packets. This will cause problems when still
627 * using vector Rx process function or simple Rx function to receiving
628 * packets. So, when Rx of scattered packets is off and device is
629 * started, it is not permitted to increase MTU so that the maximum
630 * length of Rx packets is greater than Rx buffer length.
632 if (dev->data->dev_started && !dev->data->scattered_rx &&
633 frame_size > hw->rx_buf_len) {
634 hns3_err(hw, "failed to set mtu because current is "
635 "not scattered rx mode");
639 rte_spinlock_lock(&hw->lock);
640 ret = hns3vf_config_mtu(hw, mtu);
642 rte_spinlock_unlock(&hw->lock);
645 rte_spinlock_unlock(&hw->lock);
651 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
653 struct hns3_adapter *hns = eth_dev->data->dev_private;
654 struct hns3_hw *hw = &hns->hw;
655 uint16_t q_num = hw->tqps_num;
658 * In interrupt mode, 'max_rx_queues' is set based on the number of
659 * MSI-X interrupt resources of the hardware.
661 if (hw->data->dev_conf.intr_conf.rxq == 1)
662 q_num = hw->intr_tqps_num;
664 info->max_rx_queues = q_num;
665 info->max_tx_queues = hw->tqps_num;
666 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
667 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
668 info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
669 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
670 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
672 info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
673 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
674 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
675 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
676 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
677 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
678 RTE_ETH_RX_OFFLOAD_SCATTER |
679 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
680 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
681 RTE_ETH_RX_OFFLOAD_RSS_HASH |
682 RTE_ETH_RX_OFFLOAD_TCP_LRO);
683 info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
684 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
685 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
686 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
687 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
688 RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
689 RTE_ETH_TX_OFFLOAD_TCP_TSO |
690 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
691 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
692 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
693 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
694 hns3_txvlan_cap_get(hw));
696 if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
697 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
699 if (hns3_dev_get_support(hw, INDEP_TXRX))
700 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
701 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
703 info->rx_desc_lim = (struct rte_eth_desc_lim) {
704 .nb_max = HNS3_MAX_RING_DESC,
705 .nb_min = HNS3_MIN_RING_DESC,
706 .nb_align = HNS3_ALIGN_RING_DESC,
709 info->tx_desc_lim = (struct rte_eth_desc_lim) {
710 .nb_max = HNS3_MAX_RING_DESC,
711 .nb_min = HNS3_MIN_RING_DESC,
712 .nb_align = HNS3_ALIGN_RING_DESC,
713 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
714 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
717 info->default_rxconf = (struct rte_eth_rxconf) {
718 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
720 * If there are no available Rx buffer descriptors, incoming
721 * packets are always dropped by hardware based on hns3 network
727 info->default_txconf = (struct rte_eth_txconf) {
728 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
732 info->reta_size = hw->rss_ind_tbl_size;
733 info->hash_key_size = HNS3_RSS_KEY_SIZE;
734 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
736 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
737 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
738 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
739 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
740 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
741 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
747 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
749 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
753 hns3vf_disable_irq0(struct hns3_hw *hw)
755 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
759 hns3vf_enable_irq0(struct hns3_hw *hw)
761 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
764 static enum hns3vf_evt_cause
765 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
767 struct hns3_hw *hw = &hns->hw;
768 enum hns3vf_evt_cause ret;
769 uint32_t cmdq_stat_reg;
770 uint32_t rst_ing_reg;
773 /* Fetch the events from their corresponding regs */
774 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
775 if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
776 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
777 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
778 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
779 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
780 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
781 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
782 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
784 hw->reset.stats.global_cnt++;
785 hns3_warn(hw, "Global reset detected, clear reset status");
787 hns3_schedule_delayed_reset(hns);
788 hns3_warn(hw, "Global reset detected, don't clear reset status");
791 ret = HNS3VF_VECTOR0_EVENT_RST;
795 /* Check for vector0 mailbox(=CMDQ RX) event source */
796 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
797 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
798 ret = HNS3VF_VECTOR0_EVENT_MBX;
803 ret = HNS3VF_VECTOR0_EVENT_OTHER;
811 hns3vf_interrupt_handler(void *param)
813 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
814 struct hns3_adapter *hns = dev->data->dev_private;
815 struct hns3_hw *hw = &hns->hw;
816 enum hns3vf_evt_cause event_cause;
819 /* Disable interrupt */
820 hns3vf_disable_irq0(hw);
822 /* Read out interrupt causes */
823 event_cause = hns3vf_check_event_cause(hns, &clearval);
824 /* Clear interrupt causes */
825 hns3vf_clear_event_cause(hw, clearval);
827 switch (event_cause) {
828 case HNS3VF_VECTOR0_EVENT_RST:
829 hns3_schedule_reset(hns);
831 case HNS3VF_VECTOR0_EVENT_MBX:
832 hns3_dev_handle_mbx_msg(hw);
838 /* Enable interrupt */
839 hns3vf_enable_irq0(hw);
843 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
845 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
846 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
847 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
848 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
852 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
854 struct hns3_dev_specs_0_cmd *req0;
856 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
858 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
859 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
860 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
861 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
865 hns3vf_check_dev_specifications(struct hns3_hw *hw)
867 if (hw->rss_ind_tbl_size == 0 ||
868 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
869 hns3_warn(hw, "the size of hash lookup table configured (%u)"
870 " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
871 HNS3_RSS_IND_TBL_SIZE_MAX);
879 hns3vf_query_dev_specifications(struct hns3_hw *hw)
881 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
885 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
886 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
888 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
890 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
892 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
896 hns3vf_parse_dev_specifications(hw, desc);
898 return hns3vf_check_dev_specifications(hw);
902 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
904 uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
905 HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
906 uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
907 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
909 if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
910 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
911 __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
915 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
917 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS 500
919 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
920 int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
921 uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
922 uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
923 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
925 __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
928 (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
931 while (remain_ms > 0) {
932 rte_delay_ms(HNS3_POLL_RESPONE_MS);
933 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
934 HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
940 * When exit above loop, the pf_push_lsc_cap could be one of the three
941 * state: unknown (means pf not ack), not_supported, supported.
942 * Here config it as 'not_supported' when it's 'unknown' state.
944 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
945 __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
947 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
948 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
949 hns3_info(hw, "detect PF support push link status change!");
952 * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
953 * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
954 * the RTE_ETH_DEV_INTR_LSC capability.
956 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
961 hns3vf_get_capability(struct hns3_hw *hw)
963 struct rte_pci_device *pci_dev;
964 struct rte_eth_dev *eth_dev;
968 eth_dev = &rte_eth_devices[hw->data->port_id];
969 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
971 /* Get PCI revision id */
972 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
973 HNS3_PCI_REVISION_ID);
974 if (ret != HNS3_PCI_REVISION_ID_LEN) {
975 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
979 hw->revision = revision;
981 if (revision < PCI_REVISION_ID_HIP09_A) {
982 hns3vf_set_default_dev_specifications(hw);
983 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
984 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
985 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
986 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
987 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
988 hw->rss_info.ipv6_sctp_offload_supported = false;
989 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
993 ret = hns3vf_query_dev_specifications(hw);
996 "failed to query dev specifications, ret = %d",
1001 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1002 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1003 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1004 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1005 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1006 hw->rss_info.ipv6_sctp_offload_supported = true;
1007 hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1013 hns3vf_check_tqp_info(struct hns3_hw *hw)
1015 if (hw->tqps_num == 0) {
1016 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1020 if (hw->rss_size_max == 0) {
1021 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1025 hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1031 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1036 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1037 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1038 true, &resp_msg, sizeof(resp_msg));
1040 if (ret == -ETIME) {
1042 * Getting current port based VLAN state from PF driver
1043 * will not affect VF driver's basic function. Because
1044 * the VF driver relies on hns3 PF kernel ether driver,
1045 * to avoid introducing compatibility issues with older
1046 * version of PF driver, no failure will be returned
1047 * when the return value is ETIME. This return value has
1048 * the following scenarios:
1049 * 1) Firmware didn't return the results in time
1050 * 2) the result return by firmware is timeout
1051 * 3) the older version of kernel side PF driver does
1052 * not support this mailbox message.
1053 * For scenarios 1 and 2, it is most likely that a
1054 * hardware error has occurred, or a hardware reset has
1055 * occurred. In this case, these errors will be caught
1056 * by other functions.
1058 PMD_INIT_LOG(WARNING,
1059 "failed to get PVID state for timeout, maybe "
1060 "kernel side PF driver doesn't support this "
1061 "mailbox message, or firmware didn't respond.");
1062 resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1064 PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1069 hw->port_base_vlan_cfg.state = resp_msg ?
1070 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1075 hns3vf_get_queue_info(struct hns3_hw *hw)
1077 #define HNS3VF_TQPS_RSS_INFO_LEN 6
1078 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1081 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1082 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1084 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1088 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1089 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1091 return hns3vf_check_tqp_info(hw);
1095 hns3vf_get_queue_depth(struct hns3_hw *hw)
1097 #define HNS3VF_TQPS_DEPTH_INFO_LEN 4
1098 uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1101 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1102 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1104 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1109 memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1110 memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1116 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
1118 if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
1119 hns3_set_bit(hw->capability,
1120 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
1124 hns3vf_get_num_tc(struct hns3_hw *hw)
1129 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1130 if (hw->hw_tc_map & BIT(i))
1137 hns3vf_get_basic_info(struct hns3_hw *hw)
1139 uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
1140 struct hns3_basic_info *basic_info;
1143 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
1144 true, resp_msg, sizeof(resp_msg));
1146 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
1151 basic_info = (struct hns3_basic_info *)resp_msg;
1152 hw->hw_tc_map = basic_info->hw_tc_map;
1153 hw->num_tc = hns3vf_get_num_tc(hw);
1154 hw->pf_vf_if_version = basic_info->pf_vf_if_version;
1155 hns3vf_update_caps(hw, basic_info->caps);
1161 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1163 uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1166 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1167 true, host_mac, RTE_ETHER_ADDR_LEN);
1169 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1173 memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1179 hns3vf_get_configuration(struct hns3_hw *hw)
1183 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1184 hw->rss_dis_flag = false;
1186 /* Get device capability */
1187 ret = hns3vf_get_capability(hw);
1189 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1193 hns3vf_get_push_lsc_cap(hw);
1195 /* Get basic info from PF */
1196 ret = hns3vf_get_basic_info(hw);
1200 /* Get queue configuration from PF */
1201 ret = hns3vf_get_queue_info(hw);
1205 /* Get queue depth info from PF */
1206 ret = hns3vf_get_queue_depth(hw);
1210 /* Get user defined VF MAC addr from PF */
1211 ret = hns3vf_get_host_mac_addr(hw);
1215 return hns3vf_get_port_base_vlan_filter_state(hw);
1219 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1222 struct hns3_hw *hw = &hns->hw;
1224 return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1228 hns3vf_request_link_info(struct hns3_hw *hw)
1230 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1234 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1237 send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1238 vf->req_link_info_cnt > 0;
1242 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1245 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1249 if (vf->req_link_info_cnt > 0)
1250 vf->req_link_info_cnt--;
1254 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1255 uint32_t link_speed, uint8_t link_duplex)
1257 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1258 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1259 struct hns3_mac *mac = &hw->mac;
1263 * PF kernel driver may push link status when VF driver is in resetting,
1264 * driver will stop polling job in this case, after resetting done
1265 * driver will start polling job again.
1266 * When polling job started, driver will get initial link status by
1267 * sending request to PF kernel driver, then could update link status by
1268 * process PF kernel driver's link status mailbox message.
1270 if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1273 if (hw->adapter_state != HNS3_NIC_STARTED)
1276 mac->link_status = link_status;
1277 mac->link_speed = link_speed;
1278 mac->link_duplex = link_duplex;
1279 ret = hns3vf_dev_link_update(dev, 0);
1280 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1281 hns3_start_report_lse(dev);
1285 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1287 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1288 struct hns3_hw *hw = &hns->hw;
1289 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1290 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1291 uint8_t is_kill = on ? 0 : 1;
1293 msg_data[0] = is_kill;
1294 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1295 memcpy(&msg_data[3], &proto, sizeof(proto));
1297 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1298 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1303 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1305 struct hns3_adapter *hns = dev->data->dev_private;
1306 struct hns3_hw *hw = &hns->hw;
1309 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1311 "vf set vlan id failed during resetting, vlan_id =%u",
1315 rte_spinlock_lock(&hw->lock);
1316 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1317 rte_spinlock_unlock(&hw->lock);
1319 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1326 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1331 if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1334 msg_data = enable ? 1 : 0;
1335 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1336 HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1337 sizeof(msg_data), true, NULL, 0);
1339 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1340 enable ? "enable" : "disable", ret);
1346 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1351 msg_data = enable ? 1 : 0;
1352 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1353 &msg_data, sizeof(msg_data), false, NULL, 0);
1355 hns3_err(hw, "vf %s strip failed, ret = %d.",
1356 enable ? "enable" : "disable", ret);
1362 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1364 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1365 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1366 unsigned int tmp_mask;
1369 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1370 hns3_err(hw, "vf set vlan offload failed during resetting, "
1371 "mask = 0x%x", mask);
1375 tmp_mask = (unsigned int)mask;
1377 if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
1378 rte_spinlock_lock(&hw->lock);
1379 /* Enable or disable VLAN filter */
1380 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1381 ret = hns3vf_en_vlan_filter(hw, true);
1383 ret = hns3vf_en_vlan_filter(hw, false);
1384 rte_spinlock_unlock(&hw->lock);
1389 /* Vlan stripping setting */
1390 if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
1391 rte_spinlock_lock(&hw->lock);
1392 /* Enable or disable VLAN stripping */
1393 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1394 ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1396 ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1397 rte_spinlock_unlock(&hw->lock);
1404 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1406 struct rte_vlan_filter_conf *vfc;
1407 struct hns3_hw *hw = &hns->hw;
1414 vfc = &hw->data->vlan_filter_conf;
1415 for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1416 if (vfc->ids[i] == 0)
1421 * 64 means the num bits of ids, one bit corresponds to
1425 /* count trailing zeroes */
1426 vbit = ~ids & (ids - 1);
1427 /* clear least significant bit set */
1428 ids ^= (ids ^ (ids - 1)) ^ vbit;
1433 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1436 "VF handle vlan table failed, ret =%d, on = %d",
1447 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1449 return hns3vf_handle_all_vlan_table(hns, 0);
1453 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1455 struct hns3_hw *hw = &hns->hw;
1456 struct rte_eth_conf *dev_conf;
1460 dev_conf = &hw->data->dev_conf;
1461 en = dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? true
1463 ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1465 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1471 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1473 struct hns3_adapter *hns = dev->data->dev_private;
1474 struct rte_eth_dev_data *data = dev->data;
1475 struct hns3_hw *hw = &hns->hw;
1478 if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1479 data->dev_conf.txmode.hw_vlan_reject_untagged ||
1480 data->dev_conf.txmode.hw_vlan_insert_pvid) {
1481 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1482 "or hw_vlan_insert_pvid is not support!");
1485 /* Apply vlan offload setting */
1486 ret = hns3vf_vlan_offload_set(dev, RTE_ETH_VLAN_STRIP_MASK |
1487 RTE_ETH_VLAN_FILTER_MASK);
1489 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1495 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1499 msg_data = alive ? 1 : 0;
1500 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1501 sizeof(msg_data), false, NULL, 0);
1505 hns3vf_keep_alive_handler(void *param)
1507 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1508 struct hns3_adapter *hns = eth_dev->data->dev_private;
1509 struct hns3_hw *hw = &hns->hw;
1512 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1515 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1518 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1523 hns3vf_service_handler(void *param)
1525 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1526 struct hns3_adapter *hns = eth_dev->data->dev_private;
1527 struct hns3_hw *hw = &hns->hw;
1530 * The query link status and reset processing are executed in the
1531 * interrupt thread. When the IMP reset occurs, IMP will not respond,
1532 * and the query operation will timeout after 30ms. In the case of
1533 * multiple PF/VFs, each query failure timeout causes the IMP reset
1534 * interrupt to fail to respond within 100ms.
1535 * Before querying the link status, check whether there is a reset
1536 * pending, and if so, abandon the query.
1538 if (!hns3vf_is_reset_pending(hns))
1539 hns3vf_request_link_info(hw);
1541 hns3_warn(hw, "Cancel the query when reset is pending");
1543 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1548 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1550 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT 3
1552 struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1554 if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1555 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1557 __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1559 hns3vf_service_handler(dev);
1563 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1565 struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1567 rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1569 __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1573 hns3_query_vf_resource(struct hns3_hw *hw)
1575 struct hns3_vf_res_cmd *req;
1576 struct hns3_cmd_desc desc;
1580 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1581 ret = hns3_cmd_send(hw, &desc, 1);
1583 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1587 req = (struct hns3_vf_res_cmd *)desc.data;
1588 num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1589 HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1590 if (num_msi < HNS3_MIN_VECTOR_NUM) {
1591 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1592 num_msi, HNS3_MIN_VECTOR_NUM);
1596 hw->num_msi = num_msi;
1602 hns3vf_init_hardware(struct hns3_adapter *hns)
1604 struct hns3_hw *hw = &hns->hw;
1605 uint16_t mtu = hw->data->mtu;
1608 ret = hns3vf_set_promisc_mode(hw, true, false, false);
1612 ret = hns3vf_config_mtu(hw, mtu);
1614 goto err_init_hardware;
1616 ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1618 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1619 goto err_init_hardware;
1622 ret = hns3_config_gro(hw, false);
1624 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1625 goto err_init_hardware;
1629 * In the initialization clearing the all hardware mapping relationship
1630 * configurations between queues and interrupt vectors is needed, so
1631 * some error caused by the residual configurations, such as the
1632 * unexpected interrupt, can be avoid.
1634 ret = hns3vf_init_ring_with_vector(hw);
1636 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1637 goto err_init_hardware;
1643 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1648 hns3vf_clear_vport_list(struct hns3_hw *hw)
1650 return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1651 HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1656 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1658 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1659 struct hns3_adapter *hns = eth_dev->data->dev_private;
1660 struct hns3_hw *hw = &hns->hw;
1663 PMD_INIT_FUNC_TRACE();
1665 /* Get hardware io base address from pcie BAR2 IO space */
1666 hw->io_base = pci_dev->mem_resource[2].addr;
1668 /* Firmware command queue initialize */
1669 ret = hns3_cmd_init_queue(hw);
1671 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1672 goto err_cmd_init_queue;
1675 /* Firmware command initialize */
1676 ret = hns3_cmd_init(hw);
1678 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1682 hns3_tx_push_init(eth_dev);
1684 /* Get VF resource */
1685 ret = hns3_query_vf_resource(hw);
1689 rte_spinlock_init(&hw->mbx_resp.lock);
1691 hns3vf_clear_event_cause(hw, 0);
1693 ret = rte_intr_callback_register(pci_dev->intr_handle,
1694 hns3vf_interrupt_handler, eth_dev);
1696 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1697 goto err_intr_callback_register;
1700 /* Enable interrupt */
1701 rte_intr_enable(pci_dev->intr_handle);
1702 hns3vf_enable_irq0(hw);
1704 /* Get configuration from PF */
1705 ret = hns3vf_get_configuration(hw);
1707 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1708 goto err_get_config;
1711 ret = hns3_tqp_stats_init(hw);
1713 goto err_get_config;
1715 /* Hardware statistics of imissed registers cleared. */
1716 ret = hns3_update_imissed_stats(hw, true);
1718 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1719 goto err_set_tc_queue;
1722 ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1724 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1725 goto err_set_tc_queue;
1728 ret = hns3vf_clear_vport_list(hw);
1730 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1731 goto err_set_tc_queue;
1734 ret = hns3vf_init_hardware(hns);
1736 goto err_set_tc_queue;
1738 hns3_rss_set_default_args(hw);
1740 ret = hns3vf_set_alive(hw, true);
1742 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1743 goto err_set_tc_queue;
1749 hns3_tqp_stats_uninit(hw);
1752 hns3vf_disable_irq0(hw);
1753 rte_intr_disable(pci_dev->intr_handle);
1754 hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1756 err_intr_callback_register:
1758 hns3_cmd_uninit(hw);
1759 hns3_cmd_destroy_queue(hw);
1767 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1769 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1770 struct hns3_adapter *hns = eth_dev->data->dev_private;
1771 struct hns3_hw *hw = &hns->hw;
1773 PMD_INIT_FUNC_TRACE();
1775 hns3_rss_uninit(hns);
1776 (void)hns3_config_gro(hw, false);
1777 (void)hns3vf_set_alive(hw, false);
1778 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1779 hns3_flow_uninit(eth_dev);
1780 hns3_tqp_stats_uninit(hw);
1781 hns3vf_disable_irq0(hw);
1782 rte_intr_disable(pci_dev->intr_handle);
1783 hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1785 hns3_cmd_uninit(hw);
1786 hns3_cmd_destroy_queue(hw);
1791 hns3vf_do_stop(struct hns3_adapter *hns)
1793 struct hns3_hw *hw = &hns->hw;
1796 hw->mac.link_status = RTE_ETH_LINK_DOWN;
1799 * The "hns3vf_do_stop" function will also be called by .stop_service to
1800 * prepare reset. At the time of global or IMP reset, the command cannot
1801 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
1802 * accessed during the reset process. So the mbuf can not be released
1803 * during reset and is required to be released after the reset is
1806 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)
1807 hns3_dev_release_mbufs(hns);
1809 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
1810 hns3_configure_all_mac_addr(hns, true);
1811 ret = hns3_reset_all_tqps(hns);
1813 hns3_err(hw, "failed to reset all queues ret = %d",
1822 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1824 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1825 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1826 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1827 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1828 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1831 if (dev->data->dev_conf.intr_conf.rxq == 0)
1834 /* unmap the ring with vector */
1835 if (rte_intr_allow_others(intr_handle)) {
1836 vec = RTE_INTR_VEC_RXTX_OFFSET;
1837 base = RTE_INTR_VEC_RXTX_OFFSET;
1839 if (rte_intr_dp_is_en(intr_handle)) {
1840 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1841 (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1844 if (vec < base + rte_intr_nb_efd_get(intr_handle)
1849 /* Clean datapath event and queue/vec mapping */
1850 rte_intr_efd_disable(intr_handle);
1852 /* Cleanup vector list */
1853 rte_intr_vec_list_free(intr_handle);
1857 hns3vf_dev_stop(struct rte_eth_dev *dev)
1859 struct hns3_adapter *hns = dev->data->dev_private;
1860 struct hns3_hw *hw = &hns->hw;
1862 PMD_INIT_FUNC_TRACE();
1863 dev->data->dev_started = 0;
1865 hw->adapter_state = HNS3_NIC_STOPPING;
1866 hns3_set_rxtx_function(dev);
1868 /* Disable datapath on secondary process. */
1869 hns3_mp_req_stop_rxtx(dev);
1870 /* Prevent crashes when queues are still in use. */
1871 rte_delay_ms(hw->cfg_max_queues);
1873 rte_spinlock_lock(&hw->lock);
1874 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1876 hns3vf_do_stop(hns);
1877 hns3vf_unmap_rx_interrupt(dev);
1878 hw->adapter_state = HNS3_NIC_CONFIGURED;
1880 hns3_rx_scattered_reset(dev);
1881 hns3vf_stop_poll_job(dev);
1882 hns3_stop_report_lse(dev);
1883 rte_spinlock_unlock(&hw->lock);
1889 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1891 struct hns3_adapter *hns = eth_dev->data->dev_private;
1892 struct hns3_hw *hw = &hns->hw;
1895 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1898 if (hw->adapter_state == HNS3_NIC_STARTED)
1899 ret = hns3vf_dev_stop(eth_dev);
1901 hw->adapter_state = HNS3_NIC_CLOSING;
1902 hns3_reset_abort(hns);
1903 hw->adapter_state = HNS3_NIC_CLOSED;
1904 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1905 hns3_configure_all_mc_mac_addr(hns, true);
1906 hns3vf_remove_all_vlan_table(hns);
1907 hns3vf_uninit_vf(eth_dev);
1908 hns3_free_all_queues(eth_dev);
1909 rte_free(hw->reset.wait_data);
1910 hns3_mp_uninit_primary();
1911 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
1917 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1920 struct hns3_adapter *hns = eth_dev->data->dev_private;
1921 struct hns3_hw *hw = &hns->hw;
1922 uint32_t version = hw->fw_version;
1925 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1926 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1927 HNS3_FW_VERSION_BYTE3_S),
1928 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1929 HNS3_FW_VERSION_BYTE2_S),
1930 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1931 HNS3_FW_VERSION_BYTE1_S),
1932 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1933 HNS3_FW_VERSION_BYTE0_S));
1937 ret += 1; /* add the size of '\0' */
1938 if (fw_size < (size_t)ret)
1945 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1946 __rte_unused int wait_to_complete)
1948 struct hns3_adapter *hns = eth_dev->data->dev_private;
1949 struct hns3_hw *hw = &hns->hw;
1950 struct hns3_mac *mac = &hw->mac;
1951 struct rte_eth_link new_link;
1953 memset(&new_link, 0, sizeof(new_link));
1954 switch (mac->link_speed) {
1955 case RTE_ETH_SPEED_NUM_10M:
1956 case RTE_ETH_SPEED_NUM_100M:
1957 case RTE_ETH_SPEED_NUM_1G:
1958 case RTE_ETH_SPEED_NUM_10G:
1959 case RTE_ETH_SPEED_NUM_25G:
1960 case RTE_ETH_SPEED_NUM_40G:
1961 case RTE_ETH_SPEED_NUM_50G:
1962 case RTE_ETH_SPEED_NUM_100G:
1963 case RTE_ETH_SPEED_NUM_200G:
1964 if (mac->link_status)
1965 new_link.link_speed = mac->link_speed;
1968 if (mac->link_status)
1969 new_link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
1973 if (!mac->link_status)
1974 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
1976 new_link.link_duplex = mac->link_duplex;
1977 new_link.link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
1978 new_link.link_autoneg =
1979 !(eth_dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED);
1981 return rte_eth_linkstatus_set(eth_dev, &new_link);
1985 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1987 struct hns3_hw *hw = &hns->hw;
1988 uint16_t nb_rx_q = hw->data->nb_rx_queues;
1989 uint16_t nb_tx_q = hw->data->nb_tx_queues;
1992 ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
1996 hns3_enable_rxd_adv_layout(hw);
1998 ret = hns3_init_queues(hns, reset_queue);
2000 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2006 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2008 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2009 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2010 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2011 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2012 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2013 uint32_t intr_vector;
2018 * hns3 needs a separate interrupt to be used as event interrupt which
2019 * could not be shared with task queue pair, so KERNEL drivers need
2020 * support multiple interrupt vectors.
2022 if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2023 !rte_intr_cap_multiple(intr_handle))
2026 rte_intr_disable(intr_handle);
2027 intr_vector = hw->used_rx_queues;
2028 /* It creates event fd for each intr vector when MSIX is used */
2029 if (rte_intr_efd_enable(intr_handle, intr_vector))
2032 /* Allocate vector list */
2033 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
2034 hw->used_rx_queues)) {
2035 hns3_err(hw, "Failed to allocate %u rx_queues"
2036 " intr_vec", hw->used_rx_queues);
2038 goto vf_alloc_intr_vec_error;
2041 if (rte_intr_allow_others(intr_handle)) {
2042 vec = RTE_INTR_VEC_RXTX_OFFSET;
2043 base = RTE_INTR_VEC_RXTX_OFFSET;
2046 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2047 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2048 HNS3_RING_TYPE_RX, q_id);
2050 goto vf_bind_vector_error;
2052 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
2053 goto vf_bind_vector_error;
2056 * If there are not enough efds (e.g. not enough interrupt),
2057 * remaining queues will be bond to the last interrupt.
2059 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
2062 rte_intr_enable(intr_handle);
2065 vf_bind_vector_error:
2066 rte_intr_vec_list_free(intr_handle);
2067 vf_alloc_intr_vec_error:
2068 rte_intr_efd_disable(intr_handle);
2073 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2075 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2076 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2077 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2081 if (dev->data->dev_conf.intr_conf.rxq == 0)
2084 if (rte_intr_dp_is_en(intr_handle)) {
2085 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2086 ret = hns3vf_bind_ring_with_vector(hw,
2087 rte_intr_vec_list_index_get(intr_handle,
2089 true, HNS3_RING_TYPE_RX, q_id);
2099 hns3vf_restore_filter(struct rte_eth_dev *dev)
2101 hns3_restore_rss_filter(dev);
2105 hns3vf_dev_start(struct rte_eth_dev *dev)
2107 struct hns3_adapter *hns = dev->data->dev_private;
2108 struct hns3_hw *hw = &hns->hw;
2111 PMD_INIT_FUNC_TRACE();
2112 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2115 rte_spinlock_lock(&hw->lock);
2116 hw->adapter_state = HNS3_NIC_STARTING;
2117 ret = hns3vf_do_start(hns, true);
2119 hw->adapter_state = HNS3_NIC_CONFIGURED;
2120 rte_spinlock_unlock(&hw->lock);
2123 ret = hns3vf_map_rx_interrupt(dev);
2125 goto map_rx_inter_err;
2128 * There are three register used to control the status of a TQP
2129 * (contains a pair of Tx queue and Rx queue) in the new version network
2130 * engine. One is used to control the enabling of Tx queue, the other is
2131 * used to control the enabling of Rx queue, and the last is the master
2132 * switch used to control the enabling of the tqp. The Tx register and
2133 * TQP register must be enabled at the same time to enable a Tx queue.
2134 * The same applies to the Rx queue. For the older network enginem, this
2135 * function only refresh the enabled flag, and it is used to update the
2136 * status of queue in the dpdk framework.
2138 ret = hns3_start_all_txqs(dev);
2140 goto map_rx_inter_err;
2142 ret = hns3_start_all_rxqs(dev);
2144 goto start_all_rxqs_fail;
2146 hw->adapter_state = HNS3_NIC_STARTED;
2147 rte_spinlock_unlock(&hw->lock);
2149 hns3_rx_scattered_calc(dev);
2150 hns3_set_rxtx_function(dev);
2151 hns3_mp_req_start_rxtx(dev);
2153 hns3vf_restore_filter(dev);
2155 /* Enable interrupt of all rx queues before enabling queues */
2156 hns3_dev_all_rx_queue_intr_enable(hw, true);
2157 hns3_start_tqps(hw);
2159 if (dev->data->dev_conf.intr_conf.lsc != 0)
2160 hns3vf_dev_link_update(dev, 0);
2161 hns3vf_start_poll_job(dev);
2165 start_all_rxqs_fail:
2166 hns3_stop_all_txqs(dev);
2168 (void)hns3vf_do_stop(hns);
2169 hw->adapter_state = HNS3_NIC_CONFIGURED;
2170 rte_spinlock_unlock(&hw->lock);
2176 is_vf_reset_done(struct hns3_hw *hw)
2178 #define HNS3_FUN_RST_ING_BITS \
2179 (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2180 BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2181 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2182 BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2186 if (hw->reset.level == HNS3_VF_RESET) {
2187 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2188 if (val & HNS3_VF_RST_ING_BIT)
2191 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2192 if (val & HNS3_FUN_RST_ING_BITS)
2199 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2201 struct hns3_hw *hw = &hns->hw;
2202 enum hns3_reset_level reset;
2205 * According to the protocol of PCIe, FLR to a PF device resets the PF
2206 * state as well as the SR-IOV extended capability including VF Enable
2207 * which means that VFs no longer exist.
2209 * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2210 * is in FLR stage, the register state of VF device is not reliable,
2211 * so register states detection can not be carried out. In this case,
2212 * we just ignore the register states and return false to indicate that
2213 * there are no other reset states that need to be processed by driver.
2215 if (hw->reset.level == HNS3_VF_FULL_RESET)
2218 /* Check the registers to confirm whether there is reset pending */
2219 hns3vf_check_event_cause(hns, NULL);
2220 reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2221 if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2222 hw->reset.level < reset) {
2223 hns3_warn(hw, "High level reset %d is pending", reset);
2230 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2232 struct hns3_hw *hw = &hns->hw;
2233 struct hns3_wait_data *wait_data = hw->reset.wait_data;
2236 if (wait_data->result == HNS3_WAIT_SUCCESS) {
2238 * After vf reset is ready, the PF may not have completed
2239 * the reset processing. The vf sending mbox to PF may fail
2240 * during the pf reset, so it is better to add extra delay.
2242 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2243 hw->reset.level == HNS3_FLR_RESET)
2245 /* Reset retry process, no need to add extra delay. */
2246 if (hw->reset.attempts)
2248 if (wait_data->check_completion == NULL)
2251 wait_data->check_completion = NULL;
2252 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2253 wait_data->count = 1;
2254 wait_data->result = HNS3_WAIT_REQUEST;
2255 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2257 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2259 } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2260 hns3_clock_gettime(&tv);
2261 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2262 tv.tv_sec, tv.tv_usec);
2264 } else if (wait_data->result == HNS3_WAIT_REQUEST)
2267 wait_data->hns = hns;
2268 wait_data->check_completion = is_vf_reset_done;
2269 wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2270 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2271 wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2272 wait_data->count = HNS3VF_RESET_WAIT_CNT;
2273 wait_data->result = HNS3_WAIT_REQUEST;
2274 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2279 hns3vf_prepare_reset(struct hns3_adapter *hns)
2281 struct hns3_hw *hw = &hns->hw;
2284 if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2285 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2290 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2296 hns3vf_stop_service(struct hns3_adapter *hns)
2298 struct hns3_hw *hw = &hns->hw;
2299 struct rte_eth_dev *eth_dev;
2301 eth_dev = &rte_eth_devices[hw->data->port_id];
2302 if (hw->adapter_state == HNS3_NIC_STARTED) {
2304 * Make sure call update link status before hns3vf_stop_poll_job
2305 * because update link status depend on polling job exist.
2307 hns3vf_update_link_status(hw, RTE_ETH_LINK_DOWN, hw->mac.link_speed,
2308 hw->mac.link_duplex);
2309 hns3vf_stop_poll_job(eth_dev);
2311 hw->mac.link_status = RTE_ETH_LINK_DOWN;
2313 hns3_set_rxtx_function(eth_dev);
2315 /* Disable datapath on secondary process. */
2316 hns3_mp_req_stop_rxtx(eth_dev);
2317 rte_delay_ms(hw->cfg_max_queues);
2319 rte_spinlock_lock(&hw->lock);
2320 if (hw->adapter_state == HNS3_NIC_STARTED ||
2321 hw->adapter_state == HNS3_NIC_STOPPING) {
2322 hns3_enable_all_queues(hw, false);
2323 hns3vf_do_stop(hns);
2324 hw->reset.mbuf_deferred_free = true;
2326 hw->reset.mbuf_deferred_free = false;
2329 * It is cumbersome for hardware to pick-and-choose entries for deletion
2330 * from table space. Hence, for function reset software intervention is
2331 * required to delete the entries.
2333 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2334 hns3_configure_all_mc_mac_addr(hns, true);
2335 rte_spinlock_unlock(&hw->lock);
2341 hns3vf_start_service(struct hns3_adapter *hns)
2343 struct hns3_hw *hw = &hns->hw;
2344 struct rte_eth_dev *eth_dev;
2346 eth_dev = &rte_eth_devices[hw->data->port_id];
2347 hns3_set_rxtx_function(eth_dev);
2348 hns3_mp_req_start_rxtx(eth_dev);
2349 if (hw->adapter_state == HNS3_NIC_STARTED) {
2350 hns3vf_start_poll_job(eth_dev);
2352 /* Enable interrupt of all rx queues before enabling queues */
2353 hns3_dev_all_rx_queue_intr_enable(hw, true);
2355 * Enable state of each rxq and txq will be recovered after
2356 * reset, so we need to restore them before enable all tqps;
2358 hns3_restore_tqp_enable_state(hw);
2360 * When finished the initialization, enable queues to receive
2361 * and transmit packets.
2363 hns3_enable_all_queues(hw, true);
2370 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2372 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2373 struct rte_ether_addr *hw_mac;
2377 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2378 * on the host by "ip link set ..." command. If the hns3 PF kernel
2379 * ethdev driver sets the MAC address for VF device after the
2380 * initialization of the related VF device, the PF driver will notify
2381 * VF driver to reset VF device to make the new MAC address effective
2382 * immediately. The hns3 VF PMD driver should check whether the MAC
2383 * address has been changed by the PF kernel ethdev driver, if changed
2384 * VF driver should configure hardware using the new MAC address in the
2385 * recovering hardware configuration stage of the reset process.
2387 ret = hns3vf_get_host_mac_addr(hw);
2391 hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2392 ret = rte_is_zero_ether_addr(hw_mac);
2394 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2396 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2398 rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2399 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2400 &hw->data->mac_addrs[0]);
2401 hns3_warn(hw, "Default MAC address has been changed to:"
2402 " %s by the host PF kernel ethdev driver",
2411 hns3vf_restore_conf(struct hns3_adapter *hns)
2413 struct hns3_hw *hw = &hns->hw;
2416 ret = hns3vf_check_default_mac_change(hw);
2420 ret = hns3_configure_all_mac_addr(hns, false);
2424 ret = hns3_configure_all_mc_mac_addr(hns, false);
2428 ret = hns3vf_restore_promisc(hns);
2430 goto err_vlan_table;
2432 ret = hns3vf_restore_vlan_conf(hns);
2434 goto err_vlan_table;
2436 ret = hns3vf_get_port_base_vlan_filter_state(hw);
2438 goto err_vlan_table;
2440 ret = hns3vf_restore_rx_interrupt(hw);
2442 goto err_vlan_table;
2444 ret = hns3_restore_gro_conf(hw);
2446 goto err_vlan_table;
2448 if (hw->adapter_state == HNS3_NIC_STARTED) {
2449 ret = hns3vf_do_start(hns, false);
2451 goto err_vlan_table;
2452 hns3_info(hw, "hns3vf dev restart successful!");
2453 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2454 hw->adapter_state = HNS3_NIC_CONFIGURED;
2456 ret = hns3vf_set_alive(hw, true);
2458 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2459 goto err_vlan_table;
2465 hns3_configure_all_mc_mac_addr(hns, true);
2467 hns3_configure_all_mac_addr(hns, true);
2471 static enum hns3_reset_level
2472 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2474 enum hns3_reset_level reset_level;
2476 /* return the highest priority reset level amongst all */
2477 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2478 reset_level = HNS3_VF_RESET;
2479 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2480 reset_level = HNS3_VF_FULL_RESET;
2481 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2482 reset_level = HNS3_VF_PF_FUNC_RESET;
2483 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2484 reset_level = HNS3_VF_FUNC_RESET;
2485 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2486 reset_level = HNS3_FLR_RESET;
2488 reset_level = HNS3_NONE_RESET;
2490 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2491 return HNS3_NONE_RESET;
2497 hns3vf_reset_service(void *param)
2499 struct hns3_adapter *hns = (struct hns3_adapter *)param;
2500 struct hns3_hw *hw = &hns->hw;
2501 enum hns3_reset_level reset_level;
2502 struct timeval tv_delta;
2503 struct timeval tv_start;
2508 * The interrupt is not triggered within the delay time.
2509 * The interrupt may have been lost. It is necessary to handle
2510 * the interrupt to recover from the error.
2512 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2513 SCHEDULE_DEFERRED) {
2514 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2516 hns3_err(hw, "Handling interrupts in delayed tasks");
2517 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2518 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2519 if (reset_level == HNS3_NONE_RESET) {
2520 hns3_err(hw, "No reset level is set, try global reset");
2521 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2524 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2527 * Hardware reset has been notified, we now have to poll & check if
2528 * hardware has actually completed the reset sequence.
2530 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2531 if (reset_level != HNS3_NONE_RESET) {
2532 hns3_clock_gettime(&tv_start);
2533 hns3_reset_process(hns, reset_level);
2534 hns3_clock_gettime(&tv);
2535 timersub(&tv, &tv_start, &tv_delta);
2536 msec = hns3_clock_calctime_ms(&tv_delta);
2537 if (msec > HNS3_RESET_PROCESS_MS)
2538 hns3_err(hw, "%d handle long time delta %" PRIu64
2539 " ms time=%ld.%.6ld",
2540 hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2545 hns3vf_reinit_dev(struct hns3_adapter *hns)
2547 struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2548 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2549 struct hns3_hw *hw = &hns->hw;
2552 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2553 rte_intr_disable(pci_dev->intr_handle);
2554 ret = hns3vf_set_bus_master(pci_dev, true);
2556 hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2561 /* Firmware command initialize */
2562 ret = hns3_cmd_init(hw);
2564 hns3_err(hw, "Failed to init cmd: %d", ret);
2568 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2570 * UIO enables msix by writing the pcie configuration space
2571 * vfio_pci enables msix in rte_intr_enable.
2573 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2574 pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2575 if (hns3vf_enable_msix(pci_dev, true))
2576 hns3_err(hw, "Failed to enable msix");
2579 rte_intr_enable(pci_dev->intr_handle);
2582 ret = hns3_reset_all_tqps(hns);
2584 hns3_err(hw, "Failed to reset all queues: %d", ret);
2588 ret = hns3vf_init_hardware(hns);
2590 hns3_err(hw, "Failed to init hardware: %d", ret);
2597 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2598 .dev_configure = hns3vf_dev_configure,
2599 .dev_start = hns3vf_dev_start,
2600 .dev_stop = hns3vf_dev_stop,
2601 .dev_close = hns3vf_dev_close,
2602 .mtu_set = hns3vf_dev_mtu_set,
2603 .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2604 .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2605 .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2606 .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2607 .stats_get = hns3_stats_get,
2608 .stats_reset = hns3_stats_reset,
2609 .xstats_get = hns3_dev_xstats_get,
2610 .xstats_get_names = hns3_dev_xstats_get_names,
2611 .xstats_reset = hns3_dev_xstats_reset,
2612 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
2613 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2614 .dev_infos_get = hns3vf_dev_infos_get,
2615 .fw_version_get = hns3vf_fw_version_get,
2616 .rx_queue_setup = hns3_rx_queue_setup,
2617 .tx_queue_setup = hns3_tx_queue_setup,
2618 .rx_queue_release = hns3_dev_rx_queue_release,
2619 .tx_queue_release = hns3_dev_tx_queue_release,
2620 .rx_queue_start = hns3_dev_rx_queue_start,
2621 .rx_queue_stop = hns3_dev_rx_queue_stop,
2622 .tx_queue_start = hns3_dev_tx_queue_start,
2623 .tx_queue_stop = hns3_dev_tx_queue_stop,
2624 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
2625 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
2626 .rxq_info_get = hns3_rxq_info_get,
2627 .txq_info_get = hns3_txq_info_get,
2628 .rx_burst_mode_get = hns3_rx_burst_mode_get,
2629 .tx_burst_mode_get = hns3_tx_burst_mode_get,
2630 .mac_addr_add = hns3_add_mac_addr,
2631 .mac_addr_remove = hns3_remove_mac_addr,
2632 .mac_addr_set = hns3vf_set_default_mac_addr,
2633 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
2634 .link_update = hns3vf_dev_link_update,
2635 .rss_hash_update = hns3_dev_rss_hash_update,
2636 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
2637 .reta_update = hns3_dev_rss_reta_update,
2638 .reta_query = hns3_dev_rss_reta_query,
2639 .flow_ops_get = hns3_dev_flow_ops_get,
2640 .vlan_filter_set = hns3vf_vlan_filter_set,
2641 .vlan_offload_set = hns3vf_vlan_offload_set,
2642 .get_reg = hns3_get_regs,
2643 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2644 .tx_done_cleanup = hns3_tx_done_cleanup,
2647 static const struct hns3_reset_ops hns3vf_reset_ops = {
2648 .reset_service = hns3vf_reset_service,
2649 .stop_service = hns3vf_stop_service,
2650 .prepare_reset = hns3vf_prepare_reset,
2651 .wait_hardware_ready = hns3vf_wait_hardware_ready,
2652 .reinit_dev = hns3vf_reinit_dev,
2653 .restore_conf = hns3vf_restore_conf,
2654 .start_service = hns3vf_start_service,
2658 hns3vf_init_hw_ops(struct hns3_hw *hw)
2660 hw->ops.add_mc_mac_addr = hns3vf_add_mc_mac_addr;
2661 hw->ops.del_mc_mac_addr = hns3vf_remove_mc_mac_addr;
2662 hw->ops.add_uc_mac_addr = hns3vf_add_uc_mac_addr;
2663 hw->ops.del_uc_mac_addr = hns3vf_remove_uc_mac_addr;
2667 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2669 struct hns3_adapter *hns = eth_dev->data->dev_private;
2670 struct hns3_hw *hw = &hns->hw;
2673 PMD_INIT_FUNC_TRACE();
2675 hns3_flow_init(eth_dev);
2677 hns3_set_rxtx_function(eth_dev);
2678 eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2679 eth_dev->rx_queue_count = hns3_rx_queue_count;
2680 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2681 ret = hns3_mp_init_secondary();
2683 PMD_INIT_LOG(ERR, "Failed to init for secondary "
2684 "process, ret = %d", ret);
2685 goto err_mp_init_secondary;
2687 hw->secondary_cnt++;
2688 hns3_tx_push_init(eth_dev);
2692 ret = hns3_mp_init_primary();
2695 "Failed to init for primary process, ret = %d",
2697 goto err_mp_init_primary;
2700 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2702 hw->data = eth_dev->data;
2703 hns3_parse_devargs(eth_dev);
2705 ret = hns3_reset_init(hw);
2707 goto err_init_reset;
2708 hw->reset.ops = &hns3vf_reset_ops;
2710 hns3vf_init_hw_ops(hw);
2711 ret = hns3vf_init_vf(eth_dev);
2713 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2717 /* Allocate memory for storing MAC addresses */
2718 eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2719 sizeof(struct rte_ether_addr) *
2720 HNS3_VF_UC_MACADDR_NUM, 0);
2721 if (eth_dev->data->mac_addrs == NULL) {
2722 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2723 "to store MAC addresses",
2724 sizeof(struct rte_ether_addr) *
2725 HNS3_VF_UC_MACADDR_NUM);
2727 goto err_rte_zmalloc;
2731 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2732 * on the host by "ip link set ..." command. To avoid some incorrect
2733 * scenes, for example, hns3 VF PMD driver fails to receive and send
2734 * packets after user configure the MAC address by using the
2735 * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2736 * address strategy as the hns3 kernel ethdev driver in the
2737 * initialization. If user configure a MAC address by the ip command
2738 * for VF device, then hns3 VF PMD driver will start with it, otherwise
2739 * start with a random MAC address in the initialization.
2741 if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2742 rte_eth_random_addr(hw->mac.mac_addr);
2743 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2744 ð_dev->data->mac_addrs[0]);
2746 hw->adapter_state = HNS3_NIC_INITIALIZED;
2748 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2750 hns3_err(hw, "Reschedule reset service after dev_init");
2751 hns3_schedule_reset(hns);
2753 /* IMP will wait ready flag before reset */
2754 hns3_notify_reset_ready(hw, false);
2756 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2761 hns3vf_uninit_vf(eth_dev);
2764 rte_free(hw->reset.wait_data);
2767 hns3_mp_uninit_primary();
2769 err_mp_init_primary:
2770 err_mp_init_secondary:
2771 eth_dev->dev_ops = NULL;
2772 eth_dev->rx_pkt_burst = NULL;
2773 eth_dev->rx_descriptor_status = NULL;
2774 eth_dev->tx_pkt_burst = NULL;
2775 eth_dev->tx_pkt_prepare = NULL;
2776 eth_dev->tx_descriptor_status = NULL;
2782 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2784 struct hns3_adapter *hns = eth_dev->data->dev_private;
2785 struct hns3_hw *hw = &hns->hw;
2787 PMD_INIT_FUNC_TRACE();
2789 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2792 if (hw->adapter_state < HNS3_NIC_CLOSING)
2793 hns3vf_dev_close(eth_dev);
2795 hw->adapter_state = HNS3_NIC_REMOVED;
2800 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2801 struct rte_pci_device *pci_dev)
2803 return rte_eth_dev_pci_generic_probe(pci_dev,
2804 sizeof(struct hns3_adapter),
2809 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2811 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2814 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2815 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2816 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2817 { .vendor_id = 0, }, /* sentinel */
2820 static struct rte_pci_driver rte_hns3vf_pmd = {
2821 .id_table = pci_id_hns3vf_map,
2822 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2823 .probe = eth_hns3vf_pci_probe,
2824 .remove = eth_hns3vf_pci_remove,
2827 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2828 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2829 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
2830 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
2831 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
2832 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
2833 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
2834 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16_t> ");