1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #include <linux/pci_regs.h>
7 #include <rte_ethdev_pci.h>
12 #include "hns3_ethdev.h"
13 #include "hns3_logs.h"
14 #include "hns3_rxtx.h"
15 #include "hns3_regs.h"
16 #include "hns3_intr.h"
20 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */
21 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */
23 #define HNS3VF_RESET_WAIT_MS 20
24 #define HNS3VF_RESET_WAIT_CNT 2000
26 /* Reset related Registers */
27 #define HNS3_GLOBAL_RESET_BIT 0
28 #define HNS3_CORE_RESET_BIT 1
29 #define HNS3_IMP_RESET_BIT 2
30 #define HNS3_FUN_RST_ING_B 0
32 enum hns3vf_evt_cause {
33 HNS3VF_VECTOR0_EVENT_RST,
34 HNS3VF_VECTOR0_EVENT_MBX,
35 HNS3VF_VECTOR0_EVENT_OTHER,
38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
44 struct rte_ether_addr *mac_addr);
45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
46 struct rte_ether_addr *mac_addr);
47 /* set PCI bus mastering */
49 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
54 ret = rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND);
56 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
62 /* set the master bit */
63 reg |= PCI_COMMAND_MASTER;
65 reg &= ~(PCI_COMMAND_MASTER);
67 return rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND);
71 * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
72 * @cap: the capability
74 * Return the address of the given capability within the PCI capability list.
77 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
79 #define MAX_PCIE_CAPABILITY 48
86 ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
88 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
92 if (!(status & PCI_STATUS_CAP_LIST))
95 ttl = MAX_PCIE_CAPABILITY;
96 ret = rte_pci_read_config(device, &pos, sizeof(pos),
99 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
100 PCI_CAPABILITY_LIST);
104 while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
105 ret = rte_pci_read_config(device, &id, sizeof(id),
106 (pos + PCI_CAP_LIST_ID));
108 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
109 (pos + PCI_CAP_LIST_ID));
119 ret = rte_pci_read_config(device, &pos, sizeof(pos),
120 (pos + PCI_CAP_LIST_NEXT));
122 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
123 (pos + PCI_CAP_LIST_NEXT));
131 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
137 pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
139 ret = rte_pci_read_config(device, &control, sizeof(control),
140 (pos + PCI_MSIX_FLAGS));
142 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
143 (pos + PCI_MSIX_FLAGS));
148 control |= PCI_MSIX_FLAGS_ENABLE;
150 control &= ~PCI_MSIX_FLAGS_ENABLE;
151 rte_pci_write_config(device, &control, sizeof(control),
152 (pos + PCI_MSIX_FLAGS));
159 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
161 /* mac address was checked by upper level interface */
162 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
165 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
166 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
167 RTE_ETHER_ADDR_LEN, false, NULL, 0);
169 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
171 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
178 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
180 /* mac address was checked by upper level interface */
181 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
184 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
185 HNS3_MBX_MAC_VLAN_UC_REMOVE,
186 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
189 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
191 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
198 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
200 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
201 struct rte_ether_addr *addr;
205 for (i = 0; i < hw->mc_addrs_num; i++) {
206 addr = &hw->mc_addrs[i];
207 /* Check if there are duplicate addresses */
208 if (rte_is_same_ether_addr(addr, mac_addr)) {
209 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
211 hns3_err(hw, "failed to add mc mac addr, same addrs"
212 "(%s) is added by the set_mc_mac_addr_list "
218 ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
220 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
222 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
229 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
230 __rte_unused uint32_t idx,
231 __rte_unused uint32_t pool)
233 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
234 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
237 rte_spinlock_lock(&hw->lock);
240 * In hns3 network engine adding UC and MC mac address with different
241 * commands with firmware. We need to determine whether the input
242 * address is a UC or a MC address to call different commands.
243 * By the way, it is recommended calling the API function named
244 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
245 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
246 * may affect the specifications of UC mac addresses.
248 if (rte_is_multicast_ether_addr(mac_addr))
249 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
251 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
253 rte_spinlock_unlock(&hw->lock);
255 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
257 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
265 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
267 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
268 /* index will be checked by upper level rte interface */
269 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
270 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
273 rte_spinlock_lock(&hw->lock);
275 if (rte_is_multicast_ether_addr(mac_addr))
276 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
278 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
280 rte_spinlock_unlock(&hw->lock);
282 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
284 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
290 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
291 struct rte_ether_addr *mac_addr)
293 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
294 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
295 struct rte_ether_addr *old_addr;
296 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
297 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
301 * It has been guaranteed that input parameter named mac_addr is valid
302 * address in the rte layer of DPDK framework.
304 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
305 rte_spinlock_lock(&hw->lock);
306 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
307 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
310 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
311 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
312 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
315 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
316 * driver. When user has configured a MAC address for VF device
317 * by "ip link set ..." command based on the PF device, the hns3
318 * PF kernel ethdev driver does not allow VF driver to request
319 * reconfiguring a different default MAC address, and return
320 * -EPREM to VF driver through mailbox.
323 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
325 hns3_warn(hw, "Has permanet mac addr(%s) for vf",
328 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
330 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
335 rte_ether_addr_copy(mac_addr,
336 (struct rte_ether_addr *)hw->mac.mac_addr);
337 rte_spinlock_unlock(&hw->lock);
343 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
345 struct hns3_hw *hw = &hns->hw;
346 struct rte_ether_addr *addr;
347 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
352 for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
353 addr = &hw->data->mac_addrs[i];
354 if (rte_is_zero_ether_addr(addr))
356 if (rte_is_multicast_ether_addr(addr))
357 ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
358 hns3vf_add_mc_mac_addr(hw, addr);
360 ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
361 hns3vf_add_uc_mac_addr(hw, addr);
365 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
367 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
368 "ret = %d.", del ? "remove" : "restore",
376 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
377 struct rte_ether_addr *mac_addr)
379 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
382 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
383 HNS3_MBX_MAC_VLAN_MC_ADD,
384 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
387 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
389 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
397 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
398 struct rte_ether_addr *mac_addr)
400 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
403 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
404 HNS3_MBX_MAC_VLAN_MC_REMOVE,
405 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
408 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
410 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
418 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
419 struct rte_ether_addr *mc_addr_set,
422 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
423 struct rte_ether_addr *addr;
427 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
428 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
429 "invalid. valid range: 0~%d",
430 nb_mc_addr, HNS3_MC_MACADDR_NUM);
434 /* Check if input mac addresses are valid */
435 for (i = 0; i < nb_mc_addr; i++) {
436 addr = &mc_addr_set[i];
437 if (!rte_is_multicast_ether_addr(addr)) {
438 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
441 "failed to set mc mac addr, addr(%s) invalid.",
446 /* Check if there are duplicate addresses */
447 for (j = i + 1; j < nb_mc_addr; j++) {
448 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
449 rte_ether_format_addr(mac_str,
450 RTE_ETHER_ADDR_FMT_SIZE,
452 hns3_err(hw, "failed to set mc mac addr, "
453 "addrs invalid. two same addrs(%s).",
460 * Check if there are duplicate addresses between mac_addrs
463 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
464 if (rte_is_same_ether_addr(addr,
465 &hw->data->mac_addrs[j])) {
466 rte_ether_format_addr(mac_str,
467 RTE_ETHER_ADDR_FMT_SIZE,
469 hns3_err(hw, "failed to set mc mac addr, "
470 "addrs invalid. addrs(%s) has already "
471 "configured in mac_addr add API",
482 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
483 struct rte_ether_addr *mc_addr_set,
486 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
487 struct rte_ether_addr *addr;
494 ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
498 rte_spinlock_lock(&hw->lock);
499 cur_addr_num = hw->mc_addrs_num;
500 for (i = 0; i < cur_addr_num; i++) {
501 num = cur_addr_num - i - 1;
502 addr = &hw->mc_addrs[num];
503 ret = hns3vf_remove_mc_mac_addr(hw, addr);
505 rte_spinlock_unlock(&hw->lock);
512 set_addr_num = (int)nb_mc_addr;
513 for (i = 0; i < set_addr_num; i++) {
514 addr = &mc_addr_set[i];
515 ret = hns3vf_add_mc_mac_addr(hw, addr);
517 rte_spinlock_unlock(&hw->lock);
521 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
524 rte_spinlock_unlock(&hw->lock);
530 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
532 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
533 struct hns3_hw *hw = &hns->hw;
534 struct rte_ether_addr *addr;
539 for (i = 0; i < hw->mc_addrs_num; i++) {
540 addr = &hw->mc_addrs[i];
541 if (!rte_is_multicast_ether_addr(addr))
544 ret = hns3vf_remove_mc_mac_addr(hw, addr);
546 ret = hns3vf_add_mc_mac_addr(hw, addr);
549 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
551 hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
552 del ? "Remove" : "Restore", mac_str, ret);
559 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
560 bool en_uc_pmc, bool en_mc_pmc)
562 struct hns3_mbx_vf_to_pf_cmd *req;
563 struct hns3_cmd_desc desc;
566 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
569 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
570 * so there are some features for promiscuous/allmulticast mode in hns3
571 * VF PMD driver as below:
572 * 1. The promiscuous/allmulticast mode can be configured successfully
573 * only based on the trusted VF device. If based on the non trusted
574 * VF device, configuring promiscuous/allmulticast mode will fail.
575 * The hns3 VF device can be confiruged as trusted device by hns3 PF
576 * kernel ethdev driver on the host by the following command:
577 * "ip link set <eth num> vf <vf id> turst on"
578 * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
579 * driver can receive the ingress and outgoing traffic. In the words,
580 * all the ingress packets, all the packets sent from the PF and
581 * other VFs on the same physical port.
582 * 3. Note: Because of the hardware constraints, By default vlan filter
583 * is enabled and couldn't be turned off based on VF device, so vlan
584 * filter is still effective even in promiscuous mode. If upper
585 * applications don't call rte_eth_dev_vlan_filter API function to
586 * set vlan based on VF device, hns3 VF PMD driver will can't receive
587 * the packets with vlan tag in promiscuoue mode.
589 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
590 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
591 req->msg[1] = en_bc_pmc ? 1 : 0;
592 req->msg[2] = en_uc_pmc ? 1 : 0;
593 req->msg[3] = en_mc_pmc ? 1 : 0;
594 req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
596 ret = hns3_cmd_send(hw, &desc, 1);
598 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
604 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
606 struct hns3_adapter *hns = dev->data->dev_private;
607 struct hns3_hw *hw = &hns->hw;
610 ret = hns3vf_set_promisc_mode(hw, true, true, true);
612 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
618 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
620 bool allmulti = dev->data->all_multicast ? true : false;
621 struct hns3_adapter *hns = dev->data->dev_private;
622 struct hns3_hw *hw = &hns->hw;
625 ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
627 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
633 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
635 struct hns3_adapter *hns = dev->data->dev_private;
636 struct hns3_hw *hw = &hns->hw;
639 if (dev->data->promiscuous)
642 ret = hns3vf_set_promisc_mode(hw, true, false, true);
644 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
650 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
652 struct hns3_adapter *hns = dev->data->dev_private;
653 struct hns3_hw *hw = &hns->hw;
656 if (dev->data->promiscuous)
659 ret = hns3vf_set_promisc_mode(hw, true, false, false);
661 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
667 hns3vf_restore_promisc(struct hns3_adapter *hns)
669 struct hns3_hw *hw = &hns->hw;
670 bool allmulti = hw->data->all_multicast ? true : false;
672 if (hw->data->promiscuous)
673 return hns3vf_set_promisc_mode(hw, true, true, true);
675 return hns3vf_set_promisc_mode(hw, true, false, allmulti);
679 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
680 bool mmap, enum hns3_ring_type queue_type,
683 struct hns3_vf_bind_vector_msg bind_msg;
688 memset(&bind_msg, 0, sizeof(bind_msg));
689 code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
690 HNS3_MBX_UNMAP_RING_TO_VECTOR;
691 bind_msg.vector_id = vector_id;
693 if (queue_type == HNS3_RING_TYPE_RX)
694 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
696 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
698 bind_msg.param[0].ring_type = queue_type;
699 bind_msg.ring_num = 1;
700 bind_msg.param[0].tqp_index = queue_id;
701 op_str = mmap ? "Map" : "Unmap";
702 ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
703 sizeof(bind_msg), false, NULL, 0);
705 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
706 op_str, queue_id, bind_msg.vector_id, ret);
712 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
719 * In hns3 network engine, vector 0 is always the misc interrupt of this
720 * function, vector 1~N can be used respectively for the queues of the
721 * function. Tx and Rx queues with the same number share the interrupt
722 * vector. In the initialization clearing the all hardware mapping
723 * relationship configurations between queues and interrupt vectors is
724 * needed, so some error caused by the residual configurations, such as
725 * the unexpected Tx interrupt, can be avoid.
727 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
728 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
729 vec = vec - 1; /* the last interrupt is reserved */
730 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
731 for (i = 0; i < hw->intr_tqps_num; i++) {
733 * Set gap limiter/rate limiter/quanity limiter algorithm
734 * configuration for interrupt coalesce of queue's interrupt.
736 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
737 HNS3_TQP_INTR_GL_DEFAULT);
738 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
739 HNS3_TQP_INTR_GL_DEFAULT);
740 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
742 * QL(quantity limiter) is not used currently, just set 0 to
745 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
747 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
748 HNS3_RING_TYPE_TX, i);
750 PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
751 "vector: %u, ret=%d", i, vec, ret);
755 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
756 HNS3_RING_TYPE_RX, i);
758 PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
759 "vector: %u, ret=%d", i, vec, ret);
768 hns3vf_dev_configure(struct rte_eth_dev *dev)
770 struct hns3_adapter *hns = dev->data->dev_private;
771 struct hns3_hw *hw = &hns->hw;
772 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
773 struct rte_eth_conf *conf = &dev->data->dev_conf;
774 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
775 uint16_t nb_rx_q = dev->data->nb_rx_queues;
776 uint16_t nb_tx_q = dev->data->nb_tx_queues;
777 struct rte_eth_rss_conf rss_conf;
782 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
785 * Some versions of hardware network engine does not support
786 * individually enable/disable/reset the Tx or Rx queue. These devices
787 * must enable/disable/reset Tx and Rx queues at the same time. When the
788 * numbers of Tx queues allocated by upper applications are not equal to
789 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
790 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
791 * work as usual. But these fake queues are imperceptible, and can not
792 * be used by upper applications.
794 if (!hns3_dev_indep_txrx_supported(hw)) {
795 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
797 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
803 hw->adapter_state = HNS3_NIC_CONFIGURING;
804 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
805 hns3_err(hw, "setting link speed/duplex not supported");
810 /* When RSS is not configured, redirect the packet queue 0 */
811 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
812 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
813 hw->rss_dis_flag = false;
814 rss_conf = conf->rx_adv_conf.rss_conf;
815 if (rss_conf.rss_key == NULL) {
816 rss_conf.rss_key = rss_cfg->key;
817 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
820 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
826 * If jumbo frames are enabled, MTU needs to be refreshed
827 * according to the maximum RX packet length.
829 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
831 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
832 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
833 * can safely assign to "uint16_t" type variable.
835 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
836 ret = hns3vf_dev_mtu_set(dev, mtu);
839 dev->data->mtu = mtu;
842 ret = hns3vf_dev_configure_vlan(dev);
846 /* config hardware GRO */
847 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
848 ret = hns3_config_gro(hw, gro_en);
852 hns->rx_simple_allowed = true;
853 hns->rx_vec_allowed = true;
854 hns->tx_simple_allowed = true;
855 hns->tx_vec_allowed = true;
857 hns3_init_rx_ptype_tble(dev);
859 hw->adapter_state = HNS3_NIC_CONFIGURED;
863 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
864 hw->adapter_state = HNS3_NIC_INITIALIZED;
870 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
874 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
875 sizeof(mtu), true, NULL, 0);
877 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
883 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
885 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
886 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
890 * The hns3 PF/VF devices on the same port share the hardware MTU
891 * configuration. Currently, we send mailbox to inform hns3 PF kernel
892 * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
893 * driver, there is no need to stop the port for hns3 VF device, and the
894 * MTU value issued by hns3 VF PMD driver must be less than or equal to
897 if (rte_atomic16_read(&hw->reset.resetting)) {
898 hns3_err(hw, "Failed to set mtu during resetting");
903 * when Rx of scattered packets is off, we have some possibility of
904 * using vector Rx process function or simple Rx functions in hns3 PMD
905 * driver. If the input MTU is increased and the maximum length of
906 * received packets is greater than the length of a buffer for Rx
907 * packet, the hardware network engine needs to use multiple BDs and
908 * buffers to store these packets. This will cause problems when still
909 * using vector Rx process function or simple Rx function to receiving
910 * packets. So, when Rx of scattered packets is off and device is
911 * started, it is not permitted to increase MTU so that the maximum
912 * length of Rx packets is greater than Rx buffer length.
914 if (dev->data->dev_started && !dev->data->scattered_rx &&
915 frame_size > hw->rx_buf_len) {
916 hns3_err(hw, "failed to set mtu because current is "
917 "not scattered rx mode");
921 rte_spinlock_lock(&hw->lock);
922 ret = hns3vf_config_mtu(hw, mtu);
924 rte_spinlock_unlock(&hw->lock);
927 if (frame_size > RTE_ETHER_MAX_LEN)
928 dev->data->dev_conf.rxmode.offloads |=
929 DEV_RX_OFFLOAD_JUMBO_FRAME;
931 dev->data->dev_conf.rxmode.offloads &=
932 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
933 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
934 rte_spinlock_unlock(&hw->lock);
940 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
942 struct hns3_adapter *hns = eth_dev->data->dev_private;
943 struct hns3_hw *hw = &hns->hw;
944 uint16_t q_num = hw->tqps_num;
947 * In interrupt mode, 'max_rx_queues' is set based on the number of
948 * MSI-X interrupt resources of the hardware.
950 if (hw->data->dev_conf.intr_conf.rxq == 1)
951 q_num = hw->intr_tqps_num;
953 info->max_rx_queues = q_num;
954 info->max_tx_queues = hw->tqps_num;
955 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
956 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
957 info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
958 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
959 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
961 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
962 DEV_RX_OFFLOAD_UDP_CKSUM |
963 DEV_RX_OFFLOAD_TCP_CKSUM |
964 DEV_RX_OFFLOAD_SCTP_CKSUM |
965 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
966 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
967 DEV_RX_OFFLOAD_SCATTER |
968 DEV_RX_OFFLOAD_VLAN_STRIP |
969 DEV_RX_OFFLOAD_VLAN_FILTER |
970 DEV_RX_OFFLOAD_JUMBO_FRAME |
971 DEV_RX_OFFLOAD_RSS_HASH |
972 DEV_RX_OFFLOAD_TCP_LRO);
973 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
974 DEV_TX_OFFLOAD_IPV4_CKSUM |
975 DEV_TX_OFFLOAD_TCP_CKSUM |
976 DEV_TX_OFFLOAD_UDP_CKSUM |
977 DEV_TX_OFFLOAD_SCTP_CKSUM |
978 DEV_TX_OFFLOAD_MULTI_SEGS |
979 DEV_TX_OFFLOAD_TCP_TSO |
980 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
981 DEV_TX_OFFLOAD_GRE_TNL_TSO |
982 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
983 DEV_TX_OFFLOAD_MBUF_FAST_FREE |
984 hns3_txvlan_cap_get(hw));
986 if (hns3_dev_indep_txrx_supported(hw))
987 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
988 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
990 info->rx_desc_lim = (struct rte_eth_desc_lim) {
991 .nb_max = HNS3_MAX_RING_DESC,
992 .nb_min = HNS3_MIN_RING_DESC,
993 .nb_align = HNS3_ALIGN_RING_DESC,
996 info->tx_desc_lim = (struct rte_eth_desc_lim) {
997 .nb_max = HNS3_MAX_RING_DESC,
998 .nb_min = HNS3_MIN_RING_DESC,
999 .nb_align = HNS3_ALIGN_RING_DESC,
1000 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
1001 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
1004 info->default_rxconf = (struct rte_eth_rxconf) {
1005 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
1007 * If there are no available Rx buffer descriptors, incoming
1008 * packets are always dropped by hardware based on hns3 network
1014 info->default_txconf = (struct rte_eth_txconf) {
1015 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
1019 info->vmdq_queue_num = 0;
1021 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
1022 info->hash_key_size = HNS3_RSS_KEY_SIZE;
1023 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1024 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1025 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1031 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1033 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1037 hns3vf_disable_irq0(struct hns3_hw *hw)
1039 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1043 hns3vf_enable_irq0(struct hns3_hw *hw)
1045 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1048 static enum hns3vf_evt_cause
1049 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1051 struct hns3_hw *hw = &hns->hw;
1052 enum hns3vf_evt_cause ret;
1053 uint32_t cmdq_stat_reg;
1054 uint32_t rst_ing_reg;
1057 /* Fetch the events from their corresponding regs */
1058 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1060 if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1061 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1062 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1063 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1064 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1065 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1066 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1067 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1069 hw->reset.stats.global_cnt++;
1070 hns3_warn(hw, "Global reset detected, clear reset status");
1072 hns3_schedule_delayed_reset(hns);
1073 hns3_warn(hw, "Global reset detected, don't clear reset status");
1076 ret = HNS3VF_VECTOR0_EVENT_RST;
1080 /* Check for vector0 mailbox(=CMDQ RX) event source */
1081 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1082 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1083 ret = HNS3VF_VECTOR0_EVENT_MBX;
1088 ret = HNS3VF_VECTOR0_EVENT_OTHER;
1096 hns3vf_interrupt_handler(void *param)
1098 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1099 struct hns3_adapter *hns = dev->data->dev_private;
1100 struct hns3_hw *hw = &hns->hw;
1101 enum hns3vf_evt_cause event_cause;
1104 if (hw->irq_thread_id == 0)
1105 hw->irq_thread_id = pthread_self();
1107 /* Disable interrupt */
1108 hns3vf_disable_irq0(hw);
1110 /* Read out interrupt causes */
1111 event_cause = hns3vf_check_event_cause(hns, &clearval);
1113 switch (event_cause) {
1114 case HNS3VF_VECTOR0_EVENT_RST:
1115 hns3_schedule_reset(hns);
1117 case HNS3VF_VECTOR0_EVENT_MBX:
1118 hns3_dev_handle_mbx_msg(hw);
1124 /* Clear interrupt causes */
1125 hns3vf_clear_event_cause(hw, clearval);
1127 /* Enable interrupt */
1128 hns3vf_enable_irq0(hw);
1132 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1134 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1135 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1136 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1137 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
1141 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1143 struct hns3_dev_specs_0_cmd *req0;
1145 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1147 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1148 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1149 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1150 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
1154 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1156 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1160 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1161 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1163 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1165 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1167 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1171 hns3vf_parse_dev_specifications(hw, desc);
1177 hns3vf_get_capability(struct hns3_hw *hw)
1179 struct rte_pci_device *pci_dev;
1180 struct rte_eth_dev *eth_dev;
1184 eth_dev = &rte_eth_devices[hw->data->port_id];
1185 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1187 /* Get PCI revision id */
1188 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1189 HNS3_PCI_REVISION_ID);
1190 if (ret != HNS3_PCI_REVISION_ID_LEN) {
1191 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1195 hw->revision = revision;
1197 if (revision < PCI_REVISION_ID_HIP09_A) {
1198 hns3vf_set_default_dev_specifications(hw);
1199 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1200 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1201 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1202 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1203 hw->rss_info.ipv6_sctp_offload_supported = false;
1204 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1208 ret = hns3vf_query_dev_specifications(hw);
1211 "failed to query dev specifications, ret = %d",
1216 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1217 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1218 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1219 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1220 hw->rss_info.ipv6_sctp_offload_supported = true;
1221 hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1227 hns3vf_check_tqp_info(struct hns3_hw *hw)
1229 if (hw->tqps_num == 0) {
1230 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1234 if (hw->rss_size_max == 0) {
1235 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1239 hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1245 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1250 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1251 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1252 true, &resp_msg, sizeof(resp_msg));
1254 if (ret == -ETIME) {
1256 * Getting current port based VLAN state from PF driver
1257 * will not affect VF driver's basic function. Because
1258 * the VF driver relies on hns3 PF kernel ether driver,
1259 * to avoid introducing compatibility issues with older
1260 * version of PF driver, no failure will be returned
1261 * when the return value is ETIME. This return value has
1262 * the following scenarios:
1263 * 1) Firmware didn't return the results in time
1264 * 2) the result return by firmware is timeout
1265 * 3) the older version of kernel side PF driver does
1266 * not support this mailbox message.
1267 * For scenarios 1 and 2, it is most likely that a
1268 * hardware error has occurred, or a hardware reset has
1269 * occurred. In this case, these errors will be caught
1270 * by other functions.
1272 PMD_INIT_LOG(WARNING,
1273 "failed to get PVID state for timeout, maybe "
1274 "kernel side PF driver doesn't support this "
1275 "mailbox message, or firmware didn't respond.");
1276 resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1278 PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1283 hw->port_base_vlan_cfg.state = resp_msg ?
1284 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1289 hns3vf_get_queue_info(struct hns3_hw *hw)
1291 #define HNS3VF_TQPS_RSS_INFO_LEN 6
1292 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1295 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1296 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1298 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1302 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1303 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1305 return hns3vf_check_tqp_info(hw);
1309 hns3vf_get_queue_depth(struct hns3_hw *hw)
1311 #define HNS3VF_TQPS_DEPTH_INFO_LEN 4
1312 uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1315 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1316 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1318 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1323 memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1324 memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1330 hns3vf_get_tc_info(struct hns3_hw *hw)
1336 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1337 true, &resp_msg, sizeof(resp_msg));
1339 hns3_err(hw, "VF request to get TC info from PF failed %d",
1344 hw->hw_tc_map = resp_msg;
1346 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1347 if (hw->hw_tc_map & BIT(i))
1355 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1357 uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1360 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1361 true, host_mac, RTE_ETHER_ADDR_LEN);
1363 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1367 memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1373 hns3vf_get_configuration(struct hns3_hw *hw)
1377 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1378 hw->rss_dis_flag = false;
1380 /* Get device capability */
1381 ret = hns3vf_get_capability(hw);
1383 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1387 /* Get queue configuration from PF */
1388 ret = hns3vf_get_queue_info(hw);
1392 /* Get queue depth info from PF */
1393 ret = hns3vf_get_queue_depth(hw);
1397 /* Get user defined VF MAC addr from PF */
1398 ret = hns3vf_get_host_mac_addr(hw);
1402 ret = hns3vf_get_port_base_vlan_filter_state(hw);
1406 /* Get tc configuration from PF */
1407 return hns3vf_get_tc_info(hw);
1411 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1414 struct hns3_hw *hw = &hns->hw;
1416 if (nb_rx_q < hw->num_tc) {
1417 hns3_err(hw, "number of Rx queues(%u) is less than tcs(%u).",
1418 nb_rx_q, hw->num_tc);
1422 if (nb_tx_q < hw->num_tc) {
1423 hns3_err(hw, "number of Tx queues(%u) is less than tcs(%u).",
1424 nb_tx_q, hw->num_tc);
1428 return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1432 hns3vf_request_link_info(struct hns3_hw *hw)
1437 if (rte_atomic16_read(&hw->reset.resetting))
1439 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1440 &resp_msg, sizeof(resp_msg));
1442 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1446 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1448 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1449 struct hns3_hw *hw = &hns->hw;
1450 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1451 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1452 uint8_t is_kill = on ? 0 : 1;
1454 msg_data[0] = is_kill;
1455 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1456 memcpy(&msg_data[3], &proto, sizeof(proto));
1458 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1459 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1464 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1466 struct hns3_adapter *hns = dev->data->dev_private;
1467 struct hns3_hw *hw = &hns->hw;
1470 if (rte_atomic16_read(&hw->reset.resetting)) {
1472 "vf set vlan id failed during resetting, vlan_id =%u",
1476 rte_spinlock_lock(&hw->lock);
1477 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1478 rte_spinlock_unlock(&hw->lock);
1480 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1487 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1492 msg_data = enable ? 1 : 0;
1493 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1494 &msg_data, sizeof(msg_data), false, NULL, 0);
1496 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1502 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1504 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1505 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1506 unsigned int tmp_mask;
1509 if (rte_atomic16_read(&hw->reset.resetting)) {
1510 hns3_err(hw, "vf set vlan offload failed during resetting, "
1511 "mask = 0x%x", mask);
1515 tmp_mask = (unsigned int)mask;
1516 /* Vlan stripping setting */
1517 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1518 rte_spinlock_lock(&hw->lock);
1519 /* Enable or disable VLAN stripping */
1520 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1521 ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1523 ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1524 rte_spinlock_unlock(&hw->lock);
1531 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1533 struct rte_vlan_filter_conf *vfc;
1534 struct hns3_hw *hw = &hns->hw;
1541 vfc = &hw->data->vlan_filter_conf;
1542 for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1543 if (vfc->ids[i] == 0)
1548 * 64 means the num bits of ids, one bit corresponds to
1552 /* count trailing zeroes */
1553 vbit = ~ids & (ids - 1);
1554 /* clear least significant bit set */
1555 ids ^= (ids ^ (ids - 1)) ^ vbit;
1560 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1563 "VF handle vlan table failed, ret =%d, on = %d",
1574 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1576 return hns3vf_handle_all_vlan_table(hns, 0);
1580 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1582 struct hns3_hw *hw = &hns->hw;
1583 struct rte_eth_conf *dev_conf;
1587 dev_conf = &hw->data->dev_conf;
1588 en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1590 ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1592 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1598 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1600 struct hns3_adapter *hns = dev->data->dev_private;
1601 struct rte_eth_dev_data *data = dev->data;
1602 struct hns3_hw *hw = &hns->hw;
1605 if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1606 data->dev_conf.txmode.hw_vlan_reject_untagged ||
1607 data->dev_conf.txmode.hw_vlan_insert_pvid) {
1608 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1609 "or hw_vlan_insert_pvid is not support!");
1612 /* Apply vlan offload setting */
1613 ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1615 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1621 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1625 msg_data = alive ? 1 : 0;
1626 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1627 sizeof(msg_data), false, NULL, 0);
1631 hns3vf_keep_alive_handler(void *param)
1633 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1634 struct hns3_adapter *hns = eth_dev->data->dev_private;
1635 struct hns3_hw *hw = &hns->hw;
1639 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1640 false, &respmsg, sizeof(uint8_t));
1642 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1645 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1650 hns3vf_service_handler(void *param)
1652 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1653 struct hns3_adapter *hns = eth_dev->data->dev_private;
1654 struct hns3_hw *hw = &hns->hw;
1657 * The query link status and reset processing are executed in the
1658 * interrupt thread.When the IMP reset occurs, IMP will not respond,
1659 * and the query operation will time out after 30ms. In the case of
1660 * multiple PF/VFs, each query failure timeout causes the IMP reset
1661 * interrupt to fail to respond within 100ms.
1662 * Before querying the link status, check whether there is a reset
1663 * pending, and if so, abandon the query.
1665 if (!hns3vf_is_reset_pending(hns))
1666 hns3vf_request_link_info(hw);
1668 hns3_warn(hw, "Cancel the query when reset is pending");
1670 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1675 hns3_query_vf_resource(struct hns3_hw *hw)
1677 struct hns3_vf_res_cmd *req;
1678 struct hns3_cmd_desc desc;
1682 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1683 ret = hns3_cmd_send(hw, &desc, 1);
1685 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1689 req = (struct hns3_vf_res_cmd *)desc.data;
1690 num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1691 HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1692 if (num_msi < HNS3_MIN_VECTOR_NUM) {
1693 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1694 num_msi, HNS3_MIN_VECTOR_NUM);
1698 hw->num_msi = num_msi;
1704 hns3vf_init_hardware(struct hns3_adapter *hns)
1706 struct hns3_hw *hw = &hns->hw;
1707 uint16_t mtu = hw->data->mtu;
1710 ret = hns3vf_set_promisc_mode(hw, true, false, false);
1714 ret = hns3vf_config_mtu(hw, mtu);
1716 goto err_init_hardware;
1718 ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1720 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1721 goto err_init_hardware;
1724 ret = hns3_config_gro(hw, false);
1726 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1727 goto err_init_hardware;
1731 * In the initialization clearing the all hardware mapping relationship
1732 * configurations between queues and interrupt vectors is needed, so
1733 * some error caused by the residual configurations, such as the
1734 * unexpected interrupt, can be avoid.
1736 ret = hns3vf_init_ring_with_vector(hw);
1738 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1739 goto err_init_hardware;
1742 ret = hns3vf_set_alive(hw, true);
1744 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1745 goto err_init_hardware;
1748 hns3vf_request_link_info(hw);
1752 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1757 hns3vf_clear_vport_list(struct hns3_hw *hw)
1759 return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1760 HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1765 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1767 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1768 struct hns3_adapter *hns = eth_dev->data->dev_private;
1769 struct hns3_hw *hw = &hns->hw;
1772 PMD_INIT_FUNC_TRACE();
1774 /* Get hardware io base address from pcie BAR2 IO space */
1775 hw->io_base = pci_dev->mem_resource[2].addr;
1777 /* Firmware command queue initialize */
1778 ret = hns3_cmd_init_queue(hw);
1780 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1781 goto err_cmd_init_queue;
1784 /* Firmware command initialize */
1785 ret = hns3_cmd_init(hw);
1787 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1791 /* Get VF resource */
1792 ret = hns3_query_vf_resource(hw);
1796 rte_spinlock_init(&hw->mbx_resp.lock);
1798 hns3vf_clear_event_cause(hw, 0);
1800 ret = rte_intr_callback_register(&pci_dev->intr_handle,
1801 hns3vf_interrupt_handler, eth_dev);
1803 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1804 goto err_intr_callback_register;
1807 /* Enable interrupt */
1808 rte_intr_enable(&pci_dev->intr_handle);
1809 hns3vf_enable_irq0(hw);
1811 /* Get configuration from PF */
1812 ret = hns3vf_get_configuration(hw);
1814 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1815 goto err_get_config;
1818 ret = hns3_tqp_stats_init(hw);
1820 goto err_get_config;
1822 ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1824 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1825 goto err_set_tc_queue;
1828 ret = hns3vf_clear_vport_list(hw);
1830 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1831 goto err_set_tc_queue;
1834 ret = hns3vf_init_hardware(hns);
1836 goto err_set_tc_queue;
1838 hns3_set_default_rss_args(hw);
1843 hns3_tqp_stats_uninit(hw);
1846 hns3vf_disable_irq0(hw);
1847 rte_intr_disable(&pci_dev->intr_handle);
1848 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1850 err_intr_callback_register:
1852 hns3_cmd_uninit(hw);
1853 hns3_cmd_destroy_queue(hw);
1861 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1863 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1864 struct hns3_adapter *hns = eth_dev->data->dev_private;
1865 struct hns3_hw *hw = &hns->hw;
1867 PMD_INIT_FUNC_TRACE();
1869 hns3_rss_uninit(hns);
1870 (void)hns3_config_gro(hw, false);
1871 (void)hns3vf_set_alive(hw, false);
1872 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1873 hns3_tqp_stats_uninit(hw);
1874 hns3vf_disable_irq0(hw);
1875 rte_intr_disable(&pci_dev->intr_handle);
1876 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1878 hns3_cmd_uninit(hw);
1879 hns3_cmd_destroy_queue(hw);
1884 hns3vf_do_stop(struct hns3_adapter *hns)
1886 struct hns3_hw *hw = &hns->hw;
1889 hw->mac.link_status = ETH_LINK_DOWN;
1891 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1892 hns3vf_configure_mac_addr(hns, true);
1893 ret = hns3_reset_all_tqps(hns);
1895 hns3_err(hw, "failed to reset all queues ret = %d",
1904 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1906 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1907 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1908 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1909 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1910 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1913 if (dev->data->dev_conf.intr_conf.rxq == 0)
1916 /* unmap the ring with vector */
1917 if (rte_intr_allow_others(intr_handle)) {
1918 vec = RTE_INTR_VEC_RXTX_OFFSET;
1919 base = RTE_INTR_VEC_RXTX_OFFSET;
1921 if (rte_intr_dp_is_en(intr_handle)) {
1922 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1923 (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1926 if (vec < base + intr_handle->nb_efd - 1)
1930 /* Clean datapath event and queue/vec mapping */
1931 rte_intr_efd_disable(intr_handle);
1932 if (intr_handle->intr_vec) {
1933 rte_free(intr_handle->intr_vec);
1934 intr_handle->intr_vec = NULL;
1939 hns3vf_dev_stop(struct rte_eth_dev *dev)
1941 struct hns3_adapter *hns = dev->data->dev_private;
1942 struct hns3_hw *hw = &hns->hw;
1944 PMD_INIT_FUNC_TRACE();
1945 dev->data->dev_started = 0;
1947 hw->adapter_state = HNS3_NIC_STOPPING;
1948 hns3_set_rxtx_function(dev);
1950 /* Disable datapath on secondary process. */
1951 hns3_mp_req_stop_rxtx(dev);
1952 /* Prevent crashes when queues are still in use. */
1953 rte_delay_ms(hw->tqps_num);
1955 rte_spinlock_lock(&hw->lock);
1956 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1958 hns3vf_do_stop(hns);
1959 hns3vf_unmap_rx_interrupt(dev);
1960 hns3_dev_release_mbufs(hns);
1961 hw->adapter_state = HNS3_NIC_CONFIGURED;
1963 hns3_rx_scattered_reset(dev);
1964 rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1965 rte_spinlock_unlock(&hw->lock);
1971 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1973 struct hns3_adapter *hns = eth_dev->data->dev_private;
1974 struct hns3_hw *hw = &hns->hw;
1977 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1980 if (hw->adapter_state == HNS3_NIC_STARTED)
1981 ret = hns3vf_dev_stop(eth_dev);
1983 hw->adapter_state = HNS3_NIC_CLOSING;
1984 hns3_reset_abort(hns);
1985 hw->adapter_state = HNS3_NIC_CLOSED;
1986 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1987 hns3vf_configure_all_mc_mac_addr(hns, true);
1988 hns3vf_remove_all_vlan_table(hns);
1989 hns3vf_uninit_vf(eth_dev);
1990 hns3_free_all_queues(eth_dev);
1991 rte_free(hw->reset.wait_data);
1992 rte_free(eth_dev->process_private);
1993 eth_dev->process_private = NULL;
1994 hns3_mp_uninit_primary();
1995 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
2001 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2004 struct hns3_adapter *hns = eth_dev->data->dev_private;
2005 struct hns3_hw *hw = &hns->hw;
2006 uint32_t version = hw->fw_version;
2009 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2010 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2011 HNS3_FW_VERSION_BYTE3_S),
2012 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2013 HNS3_FW_VERSION_BYTE2_S),
2014 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2015 HNS3_FW_VERSION_BYTE1_S),
2016 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2017 HNS3_FW_VERSION_BYTE0_S));
2018 ret += 1; /* add the size of '\0' */
2019 if (fw_size < (uint32_t)ret)
2026 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2027 __rte_unused int wait_to_complete)
2029 struct hns3_adapter *hns = eth_dev->data->dev_private;
2030 struct hns3_hw *hw = &hns->hw;
2031 struct hns3_mac *mac = &hw->mac;
2032 struct rte_eth_link new_link;
2034 memset(&new_link, 0, sizeof(new_link));
2035 switch (mac->link_speed) {
2036 case ETH_SPEED_NUM_10M:
2037 case ETH_SPEED_NUM_100M:
2038 case ETH_SPEED_NUM_1G:
2039 case ETH_SPEED_NUM_10G:
2040 case ETH_SPEED_NUM_25G:
2041 case ETH_SPEED_NUM_40G:
2042 case ETH_SPEED_NUM_50G:
2043 case ETH_SPEED_NUM_100G:
2044 case ETH_SPEED_NUM_200G:
2045 new_link.link_speed = mac->link_speed;
2048 new_link.link_speed = ETH_SPEED_NUM_100M;
2052 new_link.link_duplex = mac->link_duplex;
2053 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2054 new_link.link_autoneg =
2055 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2057 return rte_eth_linkstatus_set(eth_dev, &new_link);
2061 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2063 struct hns3_hw *hw = &hns->hw;
2064 uint16_t nb_rx_q = hw->data->nb_rx_queues;
2065 uint16_t nb_tx_q = hw->data->nb_tx_queues;
2068 ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2072 ret = hns3_init_queues(hns, reset_queue);
2074 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2080 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2082 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2083 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2084 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2086 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2087 uint32_t intr_vector;
2091 if (dev->data->dev_conf.intr_conf.rxq == 0)
2094 /* disable uio/vfio intr/eventfd mapping */
2095 rte_intr_disable(intr_handle);
2097 /* check and configure queue intr-vector mapping */
2098 if (rte_intr_cap_multiple(intr_handle) ||
2099 !RTE_ETH_DEV_SRIOV(dev).active) {
2100 intr_vector = hw->used_rx_queues;
2101 /* It creates event fd for each intr vector when MSIX is used */
2102 if (rte_intr_efd_enable(intr_handle, intr_vector))
2105 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2106 intr_handle->intr_vec =
2107 rte_zmalloc("intr_vec",
2108 hw->used_rx_queues * sizeof(int), 0);
2109 if (intr_handle->intr_vec == NULL) {
2110 hns3_err(hw, "Failed to allocate %u rx_queues"
2111 " intr_vec", hw->used_rx_queues);
2113 goto vf_alloc_intr_vec_error;
2117 if (rte_intr_allow_others(intr_handle)) {
2118 vec = RTE_INTR_VEC_RXTX_OFFSET;
2119 base = RTE_INTR_VEC_RXTX_OFFSET;
2121 if (rte_intr_dp_is_en(intr_handle)) {
2122 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2123 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2127 goto vf_bind_vector_error;
2128 intr_handle->intr_vec[q_id] = vec;
2129 if (vec < base + intr_handle->nb_efd - 1)
2133 rte_intr_enable(intr_handle);
2136 vf_bind_vector_error:
2137 rte_intr_efd_disable(intr_handle);
2138 if (intr_handle->intr_vec) {
2139 free(intr_handle->intr_vec);
2140 intr_handle->intr_vec = NULL;
2143 vf_alloc_intr_vec_error:
2144 rte_intr_efd_disable(intr_handle);
2149 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2151 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2152 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2153 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2157 if (dev->data->dev_conf.intr_conf.rxq == 0)
2160 if (rte_intr_dp_is_en(intr_handle)) {
2161 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2162 ret = hns3vf_bind_ring_with_vector(hw,
2163 intr_handle->intr_vec[q_id], true,
2164 HNS3_RING_TYPE_RX, q_id);
2174 hns3vf_restore_filter(struct rte_eth_dev *dev)
2176 hns3_restore_rss_filter(dev);
2180 hns3vf_dev_start(struct rte_eth_dev *dev)
2182 struct hns3_adapter *hns = dev->data->dev_private;
2183 struct hns3_hw *hw = &hns->hw;
2186 PMD_INIT_FUNC_TRACE();
2187 if (rte_atomic16_read(&hw->reset.resetting))
2190 rte_spinlock_lock(&hw->lock);
2191 hw->adapter_state = HNS3_NIC_STARTING;
2192 ret = hns3vf_do_start(hns, true);
2194 hw->adapter_state = HNS3_NIC_CONFIGURED;
2195 rte_spinlock_unlock(&hw->lock);
2198 ret = hns3vf_map_rx_interrupt(dev);
2200 hw->adapter_state = HNS3_NIC_CONFIGURED;
2201 rte_spinlock_unlock(&hw->lock);
2206 * There are three register used to control the status of a TQP
2207 * (contains a pair of Tx queue and Rx queue) in the new version network
2208 * engine. One is used to control the enabling of Tx queue, the other is
2209 * used to control the enabling of Rx queue, and the last is the master
2210 * switch used to control the enabling of the tqp. The Tx register and
2211 * TQP register must be enabled at the same time to enable a Tx queue.
2212 * The same applies to the Rx queue. For the older network enginem, this
2213 * function only refresh the enabled flag, and it is used to update the
2214 * status of queue in the dpdk framework.
2216 ret = hns3_start_all_txqs(dev);
2218 hw->adapter_state = HNS3_NIC_CONFIGURED;
2219 rte_spinlock_unlock(&hw->lock);
2223 ret = hns3_start_all_rxqs(dev);
2225 hns3_stop_all_txqs(dev);
2226 hw->adapter_state = HNS3_NIC_CONFIGURED;
2227 rte_spinlock_unlock(&hw->lock);
2231 hw->adapter_state = HNS3_NIC_STARTED;
2232 rte_spinlock_unlock(&hw->lock);
2234 hns3_rx_scattered_calc(dev);
2235 hns3_set_rxtx_function(dev);
2236 hns3_mp_req_start_rxtx(dev);
2237 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2239 hns3vf_restore_filter(dev);
2241 /* Enable interrupt of all rx queues before enabling queues */
2242 hns3_dev_all_rx_queue_intr_enable(hw, true);
2245 * After finished the initialization, start all tqps to receive/transmit
2246 * packets and refresh all queue status.
2248 hns3_start_tqps(hw);
2254 is_vf_reset_done(struct hns3_hw *hw)
2256 #define HNS3_FUN_RST_ING_BITS \
2257 (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2258 BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2259 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2260 BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2264 if (hw->reset.level == HNS3_VF_RESET) {
2265 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2266 if (val & HNS3_VF_RST_ING_BIT)
2269 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2270 if (val & HNS3_FUN_RST_ING_BITS)
2277 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2279 struct hns3_hw *hw = &hns->hw;
2280 enum hns3_reset_level reset;
2283 * According to the protocol of PCIe, FLR to a PF device resets the PF
2284 * state as well as the SR-IOV extended capability including VF Enable
2285 * which means that VFs no longer exist.
2287 * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2288 * is in FLR stage, the register state of VF device is not reliable,
2289 * so register states detection can not be carried out. In this case,
2290 * we just ignore the register states and return false to indicate that
2291 * there are no other reset states that need to be processed by driver.
2293 if (hw->reset.level == HNS3_VF_FULL_RESET)
2296 /* Check the registers to confirm whether there is reset pending */
2297 hns3vf_check_event_cause(hns, NULL);
2298 reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2299 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2300 hns3_warn(hw, "High level reset %d is pending", reset);
2307 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2309 struct hns3_hw *hw = &hns->hw;
2310 struct hns3_wait_data *wait_data = hw->reset.wait_data;
2313 if (wait_data->result == HNS3_WAIT_SUCCESS) {
2315 * After vf reset is ready, the PF may not have completed
2316 * the reset processing. The vf sending mbox to PF may fail
2317 * during the pf reset, so it is better to add extra delay.
2319 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2320 hw->reset.level == HNS3_FLR_RESET)
2322 /* Reset retry process, no need to add extra delay. */
2323 if (hw->reset.attempts)
2325 if (wait_data->check_completion == NULL)
2328 wait_data->check_completion = NULL;
2329 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2330 wait_data->count = 1;
2331 wait_data->result = HNS3_WAIT_REQUEST;
2332 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2334 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2336 } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2337 gettimeofday(&tv, NULL);
2338 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2339 tv.tv_sec, tv.tv_usec);
2341 } else if (wait_data->result == HNS3_WAIT_REQUEST)
2344 wait_data->hns = hns;
2345 wait_data->check_completion = is_vf_reset_done;
2346 wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2347 HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2348 wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2349 wait_data->count = HNS3VF_RESET_WAIT_CNT;
2350 wait_data->result = HNS3_WAIT_REQUEST;
2351 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2356 hns3vf_prepare_reset(struct hns3_adapter *hns)
2358 struct hns3_hw *hw = &hns->hw;
2361 if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2362 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2365 rte_atomic16_set(&hw->reset.disable_cmd, 1);
2371 hns3vf_stop_service(struct hns3_adapter *hns)
2373 struct hns3_hw *hw = &hns->hw;
2374 struct rte_eth_dev *eth_dev;
2376 eth_dev = &rte_eth_devices[hw->data->port_id];
2377 if (hw->adapter_state == HNS3_NIC_STARTED)
2378 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2379 hw->mac.link_status = ETH_LINK_DOWN;
2381 hns3_set_rxtx_function(eth_dev);
2383 /* Disable datapath on secondary process. */
2384 hns3_mp_req_stop_rxtx(eth_dev);
2385 rte_delay_ms(hw->tqps_num);
2387 rte_spinlock_lock(&hw->lock);
2388 if (hw->adapter_state == HNS3_NIC_STARTED ||
2389 hw->adapter_state == HNS3_NIC_STOPPING) {
2390 hns3_enable_all_queues(hw, false);
2391 hns3vf_do_stop(hns);
2392 hw->reset.mbuf_deferred_free = true;
2394 hw->reset.mbuf_deferred_free = false;
2397 * It is cumbersome for hardware to pick-and-choose entries for deletion
2398 * from table space. Hence, for function reset software intervention is
2399 * required to delete the entries.
2401 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2402 hns3vf_configure_all_mc_mac_addr(hns, true);
2403 rte_spinlock_unlock(&hw->lock);
2409 hns3vf_start_service(struct hns3_adapter *hns)
2411 struct hns3_hw *hw = &hns->hw;
2412 struct rte_eth_dev *eth_dev;
2414 eth_dev = &rte_eth_devices[hw->data->port_id];
2415 hns3_set_rxtx_function(eth_dev);
2416 hns3_mp_req_start_rxtx(eth_dev);
2417 if (hw->adapter_state == HNS3_NIC_STARTED) {
2418 hns3vf_service_handler(eth_dev);
2420 /* Enable interrupt of all rx queues before enabling queues */
2421 hns3_dev_all_rx_queue_intr_enable(hw, true);
2423 * When finished the initialization, enable queues to receive
2424 * and transmit packets.
2426 hns3_enable_all_queues(hw, true);
2433 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2435 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2436 struct rte_ether_addr *hw_mac;
2440 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2441 * on the host by "ip link set ..." command. If the hns3 PF kernel
2442 * ethdev driver sets the MAC address for VF device after the
2443 * initialization of the related VF device, the PF driver will notify
2444 * VF driver to reset VF device to make the new MAC address effective
2445 * immediately. The hns3 VF PMD driver should check whether the MAC
2446 * address has been changed by the PF kernel ethdev driver, if changed
2447 * VF driver should configure hardware using the new MAC address in the
2448 * recovering hardware configuration stage of the reset process.
2450 ret = hns3vf_get_host_mac_addr(hw);
2454 hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2455 ret = rte_is_zero_ether_addr(hw_mac);
2457 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2459 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2461 rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2462 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2463 &hw->data->mac_addrs[0]);
2464 hns3_warn(hw, "Default MAC address has been changed to:"
2465 " %s by the host PF kernel ethdev driver",
2474 hns3vf_restore_conf(struct hns3_adapter *hns)
2476 struct hns3_hw *hw = &hns->hw;
2479 ret = hns3vf_check_default_mac_change(hw);
2483 ret = hns3vf_configure_mac_addr(hns, false);
2487 ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2491 ret = hns3vf_restore_promisc(hns);
2493 goto err_vlan_table;
2495 ret = hns3vf_restore_vlan_conf(hns);
2497 goto err_vlan_table;
2499 ret = hns3vf_get_port_base_vlan_filter_state(hw);
2501 goto err_vlan_table;
2503 ret = hns3vf_restore_rx_interrupt(hw);
2505 goto err_vlan_table;
2507 ret = hns3_restore_gro_conf(hw);
2509 goto err_vlan_table;
2511 if (hw->adapter_state == HNS3_NIC_STARTED) {
2512 ret = hns3vf_do_start(hns, false);
2514 goto err_vlan_table;
2515 hns3_info(hw, "hns3vf dev restart successful!");
2516 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2517 hw->adapter_state = HNS3_NIC_CONFIGURED;
2521 hns3vf_configure_all_mc_mac_addr(hns, true);
2523 hns3vf_configure_mac_addr(hns, true);
2527 static enum hns3_reset_level
2528 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2530 enum hns3_reset_level reset_level;
2532 /* return the highest priority reset level amongst all */
2533 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2534 reset_level = HNS3_VF_RESET;
2535 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2536 reset_level = HNS3_VF_FULL_RESET;
2537 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2538 reset_level = HNS3_VF_PF_FUNC_RESET;
2539 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2540 reset_level = HNS3_VF_FUNC_RESET;
2541 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2542 reset_level = HNS3_FLR_RESET;
2544 reset_level = HNS3_NONE_RESET;
2546 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2547 return HNS3_NONE_RESET;
2553 hns3vf_reset_service(void *param)
2555 struct hns3_adapter *hns = (struct hns3_adapter *)param;
2556 struct hns3_hw *hw = &hns->hw;
2557 enum hns3_reset_level reset_level;
2558 struct timeval tv_delta;
2559 struct timeval tv_start;
2564 * The interrupt is not triggered within the delay time.
2565 * The interrupt may have been lost. It is necessary to handle
2566 * the interrupt to recover from the error.
2568 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2569 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2570 hns3_err(hw, "Handling interrupts in delayed tasks");
2571 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2572 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2573 if (reset_level == HNS3_NONE_RESET) {
2574 hns3_err(hw, "No reset level is set, try global reset");
2575 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2578 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2581 * Hardware reset has been notified, we now have to poll & check if
2582 * hardware has actually completed the reset sequence.
2584 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2585 if (reset_level != HNS3_NONE_RESET) {
2586 gettimeofday(&tv_start, NULL);
2587 hns3_reset_process(hns, reset_level);
2588 gettimeofday(&tv, NULL);
2589 timersub(&tv, &tv_start, &tv_delta);
2590 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2591 tv_delta.tv_usec / USEC_PER_MSEC;
2592 if (msec > HNS3_RESET_PROCESS_MS)
2593 hns3_err(hw, "%d handle long time delta %" PRIx64
2594 " ms time=%ld.%.6ld",
2595 hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2600 hns3vf_reinit_dev(struct hns3_adapter *hns)
2602 struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2603 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2604 struct hns3_hw *hw = &hns->hw;
2607 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2608 rte_intr_disable(&pci_dev->intr_handle);
2609 ret = hns3vf_set_bus_master(pci_dev, true);
2611 hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2616 /* Firmware command initialize */
2617 ret = hns3_cmd_init(hw);
2619 hns3_err(hw, "Failed to init cmd: %d", ret);
2623 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2625 * UIO enables msix by writing the pcie configuration space
2626 * vfio_pci enables msix in rte_intr_enable.
2628 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2629 pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2630 if (hns3vf_enable_msix(pci_dev, true))
2631 hns3_err(hw, "Failed to enable msix");
2634 rte_intr_enable(&pci_dev->intr_handle);
2637 ret = hns3_reset_all_tqps(hns);
2639 hns3_err(hw, "Failed to reset all queues: %d", ret);
2643 ret = hns3vf_init_hardware(hns);
2645 hns3_err(hw, "Failed to init hardware: %d", ret);
2652 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2653 .dev_configure = hns3vf_dev_configure,
2654 .dev_start = hns3vf_dev_start,
2655 .dev_stop = hns3vf_dev_stop,
2656 .dev_close = hns3vf_dev_close,
2657 .mtu_set = hns3vf_dev_mtu_set,
2658 .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2659 .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2660 .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2661 .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2662 .stats_get = hns3_stats_get,
2663 .stats_reset = hns3_stats_reset,
2664 .xstats_get = hns3_dev_xstats_get,
2665 .xstats_get_names = hns3_dev_xstats_get_names,
2666 .xstats_reset = hns3_dev_xstats_reset,
2667 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
2668 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2669 .dev_infos_get = hns3vf_dev_infos_get,
2670 .fw_version_get = hns3vf_fw_version_get,
2671 .rx_queue_setup = hns3_rx_queue_setup,
2672 .tx_queue_setup = hns3_tx_queue_setup,
2673 .rx_queue_release = hns3_dev_rx_queue_release,
2674 .tx_queue_release = hns3_dev_tx_queue_release,
2675 .rx_queue_start = hns3_dev_rx_queue_start,
2676 .rx_queue_stop = hns3_dev_rx_queue_stop,
2677 .tx_queue_start = hns3_dev_tx_queue_start,
2678 .tx_queue_stop = hns3_dev_tx_queue_stop,
2679 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
2680 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
2681 .rxq_info_get = hns3_rxq_info_get,
2682 .txq_info_get = hns3_txq_info_get,
2683 .rx_burst_mode_get = hns3_rx_burst_mode_get,
2684 .tx_burst_mode_get = hns3_tx_burst_mode_get,
2685 .mac_addr_add = hns3vf_add_mac_addr,
2686 .mac_addr_remove = hns3vf_remove_mac_addr,
2687 .mac_addr_set = hns3vf_set_default_mac_addr,
2688 .set_mc_addr_list = hns3vf_set_mc_mac_addr_list,
2689 .link_update = hns3vf_dev_link_update,
2690 .rss_hash_update = hns3_dev_rss_hash_update,
2691 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
2692 .reta_update = hns3_dev_rss_reta_update,
2693 .reta_query = hns3_dev_rss_reta_query,
2694 .filter_ctrl = hns3_dev_filter_ctrl,
2695 .vlan_filter_set = hns3vf_vlan_filter_set,
2696 .vlan_offload_set = hns3vf_vlan_offload_set,
2697 .get_reg = hns3_get_regs,
2698 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2701 static const struct hns3_reset_ops hns3vf_reset_ops = {
2702 .reset_service = hns3vf_reset_service,
2703 .stop_service = hns3vf_stop_service,
2704 .prepare_reset = hns3vf_prepare_reset,
2705 .wait_hardware_ready = hns3vf_wait_hardware_ready,
2706 .reinit_dev = hns3vf_reinit_dev,
2707 .restore_conf = hns3vf_restore_conf,
2708 .start_service = hns3vf_start_service,
2712 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2714 struct hns3_adapter *hns = eth_dev->data->dev_private;
2715 struct hns3_hw *hw = &hns->hw;
2718 PMD_INIT_FUNC_TRACE();
2720 eth_dev->process_private = (struct hns3_process_private *)
2721 rte_zmalloc_socket("hns3_filter_list",
2722 sizeof(struct hns3_process_private),
2723 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2724 if (eth_dev->process_private == NULL) {
2725 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2729 /* initialize flow filter lists */
2730 hns3_filterlist_init(eth_dev);
2732 hns3_set_rxtx_function(eth_dev);
2733 eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2734 eth_dev->rx_queue_count = hns3_rx_queue_count;
2735 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2736 ret = hns3_mp_init_secondary();
2738 PMD_INIT_LOG(ERR, "Failed to init for secondary "
2739 "process, ret = %d", ret);
2740 goto err_mp_init_secondary;
2743 hw->secondary_cnt++;
2747 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2749 ret = hns3_mp_init_primary();
2752 "Failed to init for primary process, ret = %d",
2754 goto err_mp_init_primary;
2757 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2759 hw->data = eth_dev->data;
2761 ret = hns3_reset_init(hw);
2763 goto err_init_reset;
2764 hw->reset.ops = &hns3vf_reset_ops;
2766 ret = hns3vf_init_vf(eth_dev);
2768 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2772 /* Allocate memory for storing MAC addresses */
2773 eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2774 sizeof(struct rte_ether_addr) *
2775 HNS3_VF_UC_MACADDR_NUM, 0);
2776 if (eth_dev->data->mac_addrs == NULL) {
2777 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2778 "to store MAC addresses",
2779 sizeof(struct rte_ether_addr) *
2780 HNS3_VF_UC_MACADDR_NUM);
2782 goto err_rte_zmalloc;
2786 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2787 * on the host by "ip link set ..." command. To avoid some incorrect
2788 * scenes, for example, hns3 VF PMD driver fails to receive and send
2789 * packets after user configure the MAC address by using the
2790 * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2791 * address strategy as the hns3 kernel ethdev driver in the
2792 * initialization. If user configure a MAC address by the ip command
2793 * for VF device, then hns3 VF PMD driver will start with it, otherwise
2794 * start with a random MAC address in the initialization.
2796 if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2797 rte_eth_random_addr(hw->mac.mac_addr);
2798 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2799 ð_dev->data->mac_addrs[0]);
2801 hw->adapter_state = HNS3_NIC_INITIALIZED;
2803 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2804 hns3_err(hw, "Reschedule reset service after dev_init");
2805 hns3_schedule_reset(hns);
2807 /* IMP will wait ready flag before reset */
2808 hns3_notify_reset_ready(hw, false);
2810 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2815 hns3vf_uninit_vf(eth_dev);
2818 rte_free(hw->reset.wait_data);
2821 hns3_mp_uninit_primary();
2823 err_mp_init_primary:
2824 err_mp_init_secondary:
2825 eth_dev->dev_ops = NULL;
2826 eth_dev->rx_pkt_burst = NULL;
2827 eth_dev->tx_pkt_burst = NULL;
2828 eth_dev->tx_pkt_prepare = NULL;
2829 rte_free(eth_dev->process_private);
2830 eth_dev->process_private = NULL;
2836 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2838 struct hns3_adapter *hns = eth_dev->data->dev_private;
2839 struct hns3_hw *hw = &hns->hw;
2841 PMD_INIT_FUNC_TRACE();
2843 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2846 if (hw->adapter_state < HNS3_NIC_CLOSING)
2847 hns3vf_dev_close(eth_dev);
2849 hw->adapter_state = HNS3_NIC_REMOVED;
2854 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2855 struct rte_pci_device *pci_dev)
2857 return rte_eth_dev_pci_generic_probe(pci_dev,
2858 sizeof(struct hns3_adapter),
2863 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2865 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2868 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2869 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2870 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2871 { .vendor_id = 0, }, /* sentinel */
2874 static struct rte_pci_driver rte_hns3vf_pmd = {
2875 .id_table = pci_id_hns3vf_map,
2876 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2877 .probe = eth_hns3vf_pci_probe,
2878 .remove = eth_hns3vf_pci_remove,
2881 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2882 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2883 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");