1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
11 #include <arpa/inet.h>
12 #include <rte_alarm.h>
13 #include <rte_atomic.h>
14 #include <rte_bus_pci.h>
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
20 #include <rte_ether.h>
21 #include <rte_ethdev_driver.h>
22 #include <rte_ethdev_pci.h>
23 #include <rte_interrupts.h>
28 #include "hns3_ethdev.h"
29 #include "hns3_logs.h"
30 #include "hns3_rxtx.h"
31 #include "hns3_regs.h"
34 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */
35 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */
37 #define HNS3VF_RESET_WAIT_MS 20
38 #define HNS3VF_RESET_WAIT_CNT 2000
40 enum hns3vf_evt_cause {
41 HNS3VF_VECTOR0_EVENT_RST,
42 HNS3VF_VECTOR0_EVENT_MBX,
43 HNS3VF_VECTOR0_EVENT_OTHER,
46 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
47 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
50 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
51 __attribute__ ((unused)) uint32_t idx,
52 __attribute__ ((unused)) uint32_t pool)
54 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
55 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
58 rte_spinlock_lock(&hw->lock);
59 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
60 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
61 RTE_ETHER_ADDR_LEN, false, NULL, 0);
62 rte_spinlock_unlock(&hw->lock);
64 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
66 hns3_err(hw, "Failed to add mac addr(%s) for vf: %d", mac_str,
74 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
76 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
77 /* index will be checked by upper level rte interface */
78 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
79 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
82 rte_spinlock_lock(&hw->lock);
83 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
84 HNS3_MBX_MAC_VLAN_UC_REMOVE,
85 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
87 rte_spinlock_unlock(&hw->lock);
89 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
91 hns3_err(hw, "Failed to remove mac addr(%s) for vf: %d",
97 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
98 struct rte_ether_addr *mac_addr)
100 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
101 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
102 struct rte_ether_addr *old_addr;
103 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
104 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
107 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
108 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
110 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid.",
115 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
116 rte_spinlock_lock(&hw->lock);
117 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
118 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
121 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
122 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
123 HNS3_TWO_ETHER_ADDR_LEN, false, NULL, 0);
125 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
127 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d", mac_str,
131 rte_ether_addr_copy(mac_addr,
132 (struct rte_ether_addr *)hw->mac.mac_addr);
133 rte_spinlock_unlock(&hw->lock);
139 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
141 struct hns3_hw *hw = &hns->hw;
142 struct rte_ether_addr *addr;
143 enum hns3_mbx_mac_vlan_subcode opcode;
144 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
149 opcode = HNS3_MBX_MAC_VLAN_UC_REMOVE;
151 opcode = HNS3_MBX_MAC_VLAN_UC_ADD;
152 for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
153 addr = &hw->data->mac_addrs[i];
154 if (!rte_is_valid_assigned_ether_addr(addr))
156 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr);
157 hns3_dbg(hw, "rm mac addr: %s", mac_str);
158 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, opcode,
159 addr->addr_bytes, RTE_ETHER_ADDR_LEN,
162 hns3_err(hw, "Failed to remove mac addr for vf: %d",
171 hns3vf_add_mc_mac_addr(struct hns3_adapter *hns,
172 struct rte_ether_addr *mac_addr)
174 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
175 struct hns3_hw *hw = &hns->hw;
178 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
179 HNS3_MBX_MAC_VLAN_MC_ADD,
180 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
183 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
185 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
194 hns3vf_remove_mc_mac_addr(struct hns3_adapter *hns,
195 struct rte_ether_addr *mac_addr)
197 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
198 struct hns3_hw *hw = &hns->hw;
201 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
202 HNS3_MBX_MAC_VLAN_MC_REMOVE,
203 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
206 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
208 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
217 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
218 struct rte_ether_addr *mc_addr_set,
221 struct hns3_adapter *hns = dev->data->dev_private;
222 struct hns3_hw *hw = &hns->hw;
223 struct rte_ether_addr *addr;
224 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
231 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
232 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
233 "invalid. valid range: 0~%d",
234 nb_mc_addr, HNS3_MC_MACADDR_NUM);
238 set_addr_num = (int)nb_mc_addr;
239 for (i = 0; i < set_addr_num; i++) {
240 addr = &mc_addr_set[i];
241 if (!rte_is_multicast_ether_addr(addr)) {
242 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
245 "Failed to set mc mac addr, addr(%s) invalid.",
250 rte_spinlock_lock(&hw->lock);
251 cur_addr_num = hw->mc_addrs_num;
252 for (i = 0; i < cur_addr_num; i++) {
253 num = cur_addr_num - i - 1;
254 addr = &hw->mc_addrs[num];
255 ret = hns3vf_remove_mc_mac_addr(hns, addr);
257 rte_spinlock_unlock(&hw->lock);
264 for (i = 0; i < set_addr_num; i++) {
265 addr = &mc_addr_set[i];
266 ret = hns3vf_add_mc_mac_addr(hns, addr);
268 rte_spinlock_unlock(&hw->lock);
272 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
275 rte_spinlock_unlock(&hw->lock);
281 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
283 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
284 struct hns3_hw *hw = &hns->hw;
285 struct rte_ether_addr *addr;
290 for (i = 0; i < hw->mc_addrs_num; i++) {
291 addr = &hw->mc_addrs[i];
292 if (!rte_is_multicast_ether_addr(addr))
295 ret = hns3vf_remove_mc_mac_addr(hns, addr);
297 ret = hns3vf_add_mc_mac_addr(hns, addr);
300 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
302 hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
303 del ? "Remove" : "Restore", mac_str, ret);
310 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc)
312 struct hns3_mbx_vf_to_pf_cmd *req;
313 struct hns3_cmd_desc desc;
316 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
318 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
319 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
320 req->msg[1] = en_bc_pmc ? 1 : 0;
322 ret = hns3_cmd_send(hw, &desc, 1);
324 hns3_err(hw, "Set promisc mode fail, status is %d", ret);
330 hns3vf_dev_configure(struct rte_eth_dev *dev)
332 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
333 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
334 struct rte_eth_conf *conf = &dev->data->dev_conf;
335 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
336 uint16_t nb_rx_q = dev->data->nb_rx_queues;
337 uint16_t nb_tx_q = dev->data->nb_tx_queues;
338 struct rte_eth_rss_conf rss_conf;
343 * Hardware does not support where the number of rx and tx queues is
344 * not equal in hip08.
346 if (nb_rx_q != nb_tx_q) {
348 "nb_rx_queues(%u) not equal with nb_tx_queues(%u)! "
349 "Hardware does not support this configuration!",
354 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
355 hns3_err(hw, "setting link speed/duplex not supported");
359 hw->adapter_state = HNS3_NIC_CONFIGURING;
361 /* When RSS is not configured, redirect the packet queue 0 */
362 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
363 rss_conf = conf->rx_adv_conf.rss_conf;
364 if (rss_conf.rss_key == NULL) {
365 rss_conf.rss_key = rss_cfg->key;
366 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
369 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
375 * If jumbo frames are enabled, MTU needs to be refreshed
376 * according to the maximum RX packet length.
378 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
380 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
381 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
382 * can safely assign to "uint16_t" type variable.
384 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
385 ret = hns3vf_dev_mtu_set(dev, mtu);
388 dev->data->mtu = mtu;
391 ret = hns3vf_dev_configure_vlan(dev);
395 hw->adapter_state = HNS3_NIC_CONFIGURED;
399 hw->adapter_state = HNS3_NIC_INITIALIZED;
404 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
408 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
409 sizeof(mtu), true, NULL, 0);
411 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
417 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
419 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
420 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
423 if (dev->data->dev_started) {
424 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
425 "before configuration", dev->data->port_id);
429 rte_spinlock_lock(&hw->lock);
430 ret = hns3vf_config_mtu(hw, mtu);
432 rte_spinlock_unlock(&hw->lock);
435 if (frame_size > RTE_ETHER_MAX_LEN)
436 dev->data->dev_conf.rxmode.offloads |=
437 DEV_RX_OFFLOAD_JUMBO_FRAME;
439 dev->data->dev_conf.rxmode.offloads &=
440 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
441 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
442 rte_spinlock_unlock(&hw->lock);
448 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
450 struct hns3_adapter *hns = eth_dev->data->dev_private;
451 struct hns3_hw *hw = &hns->hw;
453 info->max_rx_queues = hw->tqps_num;
454 info->max_tx_queues = hw->tqps_num;
455 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
456 info->min_rx_bufsize = hw->rx_buf_len;
457 info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
458 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
460 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
461 DEV_RX_OFFLOAD_UDP_CKSUM |
462 DEV_RX_OFFLOAD_TCP_CKSUM |
463 DEV_RX_OFFLOAD_SCTP_CKSUM |
464 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
465 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
466 DEV_RX_OFFLOAD_KEEP_CRC |
467 DEV_RX_OFFLOAD_SCATTER |
468 DEV_RX_OFFLOAD_VLAN_STRIP |
469 DEV_RX_OFFLOAD_QINQ_STRIP |
470 DEV_RX_OFFLOAD_VLAN_FILTER |
471 DEV_RX_OFFLOAD_JUMBO_FRAME);
472 info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
473 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
474 DEV_TX_OFFLOAD_IPV4_CKSUM |
475 DEV_TX_OFFLOAD_TCP_CKSUM |
476 DEV_TX_OFFLOAD_UDP_CKSUM |
477 DEV_TX_OFFLOAD_SCTP_CKSUM |
478 DEV_TX_OFFLOAD_VLAN_INSERT |
479 DEV_TX_OFFLOAD_QINQ_INSERT |
480 DEV_TX_OFFLOAD_MULTI_SEGS |
481 info->tx_queue_offload_capa);
483 info->rx_desc_lim = (struct rte_eth_desc_lim) {
484 .nb_max = HNS3_MAX_RING_DESC,
485 .nb_min = HNS3_MIN_RING_DESC,
486 .nb_align = HNS3_ALIGN_RING_DESC,
489 info->tx_desc_lim = (struct rte_eth_desc_lim) {
490 .nb_max = HNS3_MAX_RING_DESC,
491 .nb_min = HNS3_MIN_RING_DESC,
492 .nb_align = HNS3_ALIGN_RING_DESC,
495 info->vmdq_queue_num = 0;
497 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
498 info->hash_key_size = HNS3_RSS_KEY_SIZE;
499 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
500 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
501 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
507 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
509 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
513 hns3vf_disable_irq0(struct hns3_hw *hw)
515 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
519 hns3vf_enable_irq0(struct hns3_hw *hw)
521 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
524 static enum hns3vf_evt_cause
525 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
527 struct hns3_hw *hw = &hns->hw;
528 enum hns3vf_evt_cause ret;
529 uint32_t cmdq_stat_reg;
532 /* Fetch the events from their corresponding regs */
533 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
535 /* Check for vector0 mailbox(=CMDQ RX) event source */
536 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
537 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
538 ret = HNS3VF_VECTOR0_EVENT_MBX;
543 ret = HNS3VF_VECTOR0_EVENT_OTHER;
551 hns3vf_interrupt_handler(void *param)
553 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
554 struct hns3_adapter *hns = dev->data->dev_private;
555 struct hns3_hw *hw = &hns->hw;
556 enum hns3vf_evt_cause event_cause;
559 /* Disable interrupt */
560 hns3vf_disable_irq0(hw);
562 /* Read out interrupt causes */
563 event_cause = hns3vf_check_event_cause(hns, &clearval);
565 switch (event_cause) {
566 case HNS3VF_VECTOR0_EVENT_MBX:
567 hns3_dev_handle_mbx_msg(hw);
573 /* Clear interrupt causes */
574 hns3vf_clear_event_cause(hw, clearval);
576 /* Enable interrupt */
577 hns3vf_enable_irq0(hw);
581 hns3vf_check_tqp_info(struct hns3_hw *hw)
585 tqps_num = hw->tqps_num;
586 if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
587 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
589 tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
593 if (hw->rx_buf_len == 0)
594 hw->rx_buf_len = HNS3_DEFAULT_RX_BUF_LEN;
595 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
601 hns3vf_get_queue_info(struct hns3_hw *hw)
603 #define HNS3VF_TQPS_RSS_INFO_LEN 6
604 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
607 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
608 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
610 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
614 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
615 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
616 memcpy(&hw->rx_buf_len, &resp_msg[4], sizeof(uint16_t));
618 return hns3vf_check_tqp_info(hw);
622 hns3vf_get_queue_depth(struct hns3_hw *hw)
624 #define HNS3VF_TQPS_DEPTH_INFO_LEN 4
625 uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
628 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
629 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
631 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
636 memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
637 memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
643 hns3vf_get_tc_info(struct hns3_hw *hw)
648 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
649 true, &resp_msg, sizeof(resp_msg));
651 hns3_err(hw, "VF request to get TC info from PF failed %d",
656 hw->hw_tc_map = resp_msg;
662 hns3vf_get_configuration(struct hns3_hw *hw)
666 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
668 /* Get queue configuration from PF */
669 ret = hns3vf_get_queue_info(hw);
673 /* Get queue depth info from PF */
674 ret = hns3vf_get_queue_depth(hw);
678 /* Get tc configuration from PF */
679 return hns3vf_get_tc_info(hw);
683 hns3vf_set_tc_info(struct hns3_adapter *hns)
685 struct hns3_hw *hw = &hns->hw;
686 uint16_t nb_rx_q = hw->data->nb_rx_queues;
691 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
692 if (hw->hw_tc_map & BIT(i))
695 new_tqps = RTE_MIN(hw->tqps_num, nb_rx_q);
696 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, new_tqps / hw->num_tc);
697 hw->alloc_tqps = hw->alloc_rss_size * hw->num_tc;
699 hns3_tc_queue_mapping_cfg(hw);
703 hns3vf_request_link_info(struct hns3_hw *hw)
708 if (rte_atomic16_read(&hw->reset.resetting))
710 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
711 &resp_msg, sizeof(resp_msg));
713 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
717 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
719 #define HNS3VF_VLAN_MBX_MSG_LEN 5
720 struct hns3_hw *hw = &hns->hw;
721 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
722 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
723 uint8_t is_kill = on ? 0 : 1;
725 msg_data[0] = is_kill;
726 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
727 memcpy(&msg_data[3], &proto, sizeof(proto));
729 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
730 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
735 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
737 struct hns3_adapter *hns = dev->data->dev_private;
738 struct hns3_hw *hw = &hns->hw;
741 rte_spinlock_lock(&hw->lock);
742 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
743 rte_spinlock_unlock(&hw->lock);
745 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
752 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
757 msg_data = enable ? 1 : 0;
758 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
759 &msg_data, sizeof(msg_data), false, NULL, 0);
761 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
767 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
769 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
770 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
771 unsigned int tmp_mask;
773 tmp_mask = (unsigned int)mask;
774 /* Vlan stripping setting */
775 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
776 rte_spinlock_lock(&hw->lock);
777 /* Enable or disable VLAN stripping */
778 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
779 hns3vf_en_hw_strip_rxvtag(hw, true);
781 hns3vf_en_hw_strip_rxvtag(hw, false);
782 rte_spinlock_unlock(&hw->lock);
789 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
791 struct hns3_adapter *hns = dev->data->dev_private;
792 struct rte_eth_dev_data *data = dev->data;
793 struct hns3_hw *hw = &hns->hw;
796 if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
797 data->dev_conf.txmode.hw_vlan_reject_untagged ||
798 data->dev_conf.txmode.hw_vlan_insert_pvid) {
799 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
800 "or hw_vlan_insert_pvid is not support!");
803 /* Apply vlan offload setting */
804 ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
806 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
812 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
816 msg_data = alive ? 1 : 0;
817 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
818 sizeof(msg_data), false, NULL, 0);
822 hns3vf_keep_alive_handler(void *param)
824 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
825 struct hns3_adapter *hns = eth_dev->data->dev_private;
826 struct hns3_hw *hw = &hns->hw;
830 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
831 false, &respmsg, sizeof(uint8_t));
833 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
836 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
841 hns3vf_service_handler(void *param)
843 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
844 struct hns3_adapter *hns = eth_dev->data->dev_private;
845 struct hns3_hw *hw = &hns->hw;
847 hns3vf_request_link_info(hw);
849 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
854 hns3vf_init_hardware(struct hns3_adapter *hns)
856 struct hns3_hw *hw = &hns->hw;
857 uint16_t mtu = hw->data->mtu;
860 ret = hns3vf_set_promisc_mode(hw, true);
864 ret = hns3vf_config_mtu(hw, mtu);
866 goto err_init_hardware;
868 ret = hns3vf_vlan_filter_configure(hns, 0, 1);
870 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
871 goto err_init_hardware;
874 ret = hns3_config_gro(hw, false);
876 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
877 goto err_init_hardware;
880 ret = hns3vf_set_alive(hw, true);
882 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
883 goto err_init_hardware;
886 hns3vf_request_link_info(hw);
890 (void)hns3vf_set_promisc_mode(hw, false);
895 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
897 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
898 struct hns3_adapter *hns = eth_dev->data->dev_private;
899 struct hns3_hw *hw = &hns->hw;
902 PMD_INIT_FUNC_TRACE();
904 /* Get hardware io base address from pcie BAR2 IO space */
905 hw->io_base = pci_dev->mem_resource[2].addr;
907 /* Firmware command queue initialize */
908 ret = hns3_cmd_init_queue(hw);
910 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
911 goto err_cmd_init_queue;
914 /* Firmware command initialize */
915 ret = hns3_cmd_init(hw);
917 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
921 rte_spinlock_init(&hw->mbx_resp.lock);
923 hns3vf_clear_event_cause(hw, 0);
925 ret = rte_intr_callback_register(&pci_dev->intr_handle,
926 hns3vf_interrupt_handler, eth_dev);
928 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
929 goto err_intr_callback_register;
932 /* Enable interrupt */
933 rte_intr_enable(&pci_dev->intr_handle);
934 hns3vf_enable_irq0(hw);
936 /* Get configuration from PF */
937 ret = hns3vf_get_configuration(hw);
939 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
943 rte_eth_random_addr(hw->mac.mac_addr); /* Generate a random mac addr */
945 ret = hns3vf_init_hardware(hns);
949 hns3_set_default_rss_args(hw);
954 hns3vf_disable_irq0(hw);
955 rte_intr_disable(&pci_dev->intr_handle);
957 err_intr_callback_register:
961 hns3_cmd_destroy_queue(hw);
970 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
972 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
973 struct hns3_adapter *hns = eth_dev->data->dev_private;
974 struct hns3_hw *hw = &hns->hw;
976 PMD_INIT_FUNC_TRACE();
978 hns3_rss_uninit(hns);
979 (void)hns3vf_set_alive(hw, false);
980 (void)hns3vf_set_promisc_mode(hw, false);
981 hns3vf_disable_irq0(hw);
982 rte_intr_disable(&pci_dev->intr_handle);
984 hns3_cmd_destroy_queue(hw);
989 hns3vf_do_stop(struct hns3_adapter *hns)
991 struct hns3_hw *hw = &hns->hw;
993 hw->mac.link_status = ETH_LINK_DOWN;
995 hns3vf_configure_mac_addr(hns, true);
1001 hns3vf_dev_stop(struct rte_eth_dev *eth_dev)
1003 struct hns3_adapter *hns = eth_dev->data->dev_private;
1004 struct hns3_hw *hw = &hns->hw;
1006 PMD_INIT_FUNC_TRACE();
1008 hw->adapter_state = HNS3_NIC_STOPPING;
1009 hns3_set_rxtx_function(eth_dev);
1011 rte_spinlock_lock(&hw->lock);
1012 hns3vf_do_stop(hns);
1013 hns3_dev_release_mbufs(hns);
1014 hw->adapter_state = HNS3_NIC_CONFIGURED;
1015 rte_spinlock_unlock(&hw->lock);
1019 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1021 struct hns3_adapter *hns = eth_dev->data->dev_private;
1022 struct hns3_hw *hw = &hns->hw;
1024 if (hw->adapter_state == HNS3_NIC_STARTED)
1025 hns3vf_dev_stop(eth_dev);
1027 hw->adapter_state = HNS3_NIC_CLOSING;
1028 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1029 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
1030 hns3vf_configure_all_mc_mac_addr(hns, true);
1031 hns3vf_uninit_vf(eth_dev);
1032 hns3_free_all_queues(eth_dev);
1033 rte_free(eth_dev->process_private);
1034 eth_dev->process_private = NULL;
1035 hw->adapter_state = HNS3_NIC_CLOSED;
1036 hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1040 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1041 __rte_unused int wait_to_complete)
1043 struct hns3_adapter *hns = eth_dev->data->dev_private;
1044 struct hns3_hw *hw = &hns->hw;
1045 struct hns3_mac *mac = &hw->mac;
1046 struct rte_eth_link new_link;
1048 hns3vf_request_link_info(hw);
1050 memset(&new_link, 0, sizeof(new_link));
1051 switch (mac->link_speed) {
1052 case ETH_SPEED_NUM_10M:
1053 case ETH_SPEED_NUM_100M:
1054 case ETH_SPEED_NUM_1G:
1055 case ETH_SPEED_NUM_10G:
1056 case ETH_SPEED_NUM_25G:
1057 case ETH_SPEED_NUM_40G:
1058 case ETH_SPEED_NUM_50G:
1059 case ETH_SPEED_NUM_100G:
1060 new_link.link_speed = mac->link_speed;
1063 new_link.link_speed = ETH_SPEED_NUM_100M;
1067 new_link.link_duplex = mac->link_duplex;
1068 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1069 new_link.link_autoneg =
1070 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1072 return rte_eth_linkstatus_set(eth_dev, &new_link);
1076 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1078 struct hns3_hw *hw = &hns->hw;
1081 hns3vf_set_tc_info(hns);
1083 ret = hns3_start_queues(hns, reset_queue);
1085 hns3_err(hw, "Failed to start queues: %d", ret);
1093 hns3vf_dev_start(struct rte_eth_dev *eth_dev)
1095 struct hns3_adapter *hns = eth_dev->data->dev_private;
1096 struct hns3_hw *hw = &hns->hw;
1099 PMD_INIT_FUNC_TRACE();
1100 rte_spinlock_lock(&hw->lock);
1101 hw->adapter_state = HNS3_NIC_STARTING;
1102 ret = hns3vf_do_start(hns, true);
1104 hw->adapter_state = HNS3_NIC_CONFIGURED;
1105 rte_spinlock_unlock(&hw->lock);
1108 hw->adapter_state = HNS3_NIC_STARTED;
1109 rte_spinlock_unlock(&hw->lock);
1110 hns3_set_rxtx_function(eth_dev);
1114 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
1115 .dev_start = hns3vf_dev_start,
1116 .dev_stop = hns3vf_dev_stop,
1117 .dev_close = hns3vf_dev_close,
1118 .mtu_set = hns3vf_dev_mtu_set,
1119 .dev_infos_get = hns3vf_dev_infos_get,
1120 .rx_queue_setup = hns3_rx_queue_setup,
1121 .tx_queue_setup = hns3_tx_queue_setup,
1122 .rx_queue_release = hns3_dev_rx_queue_release,
1123 .tx_queue_release = hns3_dev_tx_queue_release,
1124 .dev_configure = hns3vf_dev_configure,
1125 .mac_addr_add = hns3vf_add_mac_addr,
1126 .mac_addr_remove = hns3vf_remove_mac_addr,
1127 .mac_addr_set = hns3vf_set_default_mac_addr,
1128 .set_mc_addr_list = hns3vf_set_mc_mac_addr_list,
1129 .link_update = hns3vf_dev_link_update,
1130 .rss_hash_update = hns3_dev_rss_hash_update,
1131 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
1132 .reta_update = hns3_dev_rss_reta_update,
1133 .reta_query = hns3_dev_rss_reta_query,
1134 .filter_ctrl = hns3_dev_filter_ctrl,
1135 .vlan_filter_set = hns3vf_vlan_filter_set,
1136 .vlan_offload_set = hns3vf_vlan_offload_set,
1137 .get_reg = hns3_get_regs,
1138 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
1142 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
1144 struct hns3_adapter *hns = eth_dev->data->dev_private;
1145 struct hns3_hw *hw = &hns->hw;
1148 PMD_INIT_FUNC_TRACE();
1150 eth_dev->process_private = (struct hns3_process_private *)
1151 rte_zmalloc_socket("hns3_filter_list",
1152 sizeof(struct hns3_process_private),
1153 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
1154 if (eth_dev->process_private == NULL) {
1155 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
1159 /* initialize flow filter lists */
1160 hns3_filterlist_init(eth_dev);
1162 hns3_set_rxtx_function(eth_dev);
1163 eth_dev->dev_ops = &hns3vf_eth_dev_ops;
1164 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1167 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
1169 hw->data = eth_dev->data;
1171 ret = hns3vf_init_vf(eth_dev);
1173 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
1177 /* Allocate memory for storing MAC addresses */
1178 eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
1179 sizeof(struct rte_ether_addr) *
1180 HNS3_VF_UC_MACADDR_NUM, 0);
1181 if (eth_dev->data->mac_addrs == NULL) {
1182 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
1183 "to store MAC addresses",
1184 sizeof(struct rte_ether_addr) *
1185 HNS3_VF_UC_MACADDR_NUM);
1187 goto err_rte_zmalloc;
1190 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
1191 ð_dev->data->mac_addrs[0]);
1192 hw->adapter_state = HNS3_NIC_INITIALIZED;
1194 * Pass the information to the rte_eth_dev_close() that it should also
1195 * release the private port resources.
1197 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1199 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1201 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1206 hns3vf_uninit_vf(eth_dev);
1209 eth_dev->dev_ops = NULL;
1210 eth_dev->rx_pkt_burst = NULL;
1211 eth_dev->tx_pkt_burst = NULL;
1212 eth_dev->tx_pkt_prepare = NULL;
1213 rte_free(eth_dev->process_private);
1214 eth_dev->process_private = NULL;
1220 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
1222 struct hns3_adapter *hns = eth_dev->data->dev_private;
1223 struct hns3_hw *hw = &hns->hw;
1225 PMD_INIT_FUNC_TRACE();
1227 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1230 eth_dev->dev_ops = NULL;
1231 eth_dev->rx_pkt_burst = NULL;
1232 eth_dev->tx_pkt_burst = NULL;
1233 eth_dev->tx_pkt_prepare = NULL;
1235 if (hw->adapter_state < HNS3_NIC_CLOSING)
1236 hns3vf_dev_close(eth_dev);
1238 hw->adapter_state = HNS3_NIC_REMOVED;
1243 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1244 struct rte_pci_device *pci_dev)
1246 return rte_eth_dev_pci_generic_probe(pci_dev,
1247 sizeof(struct hns3_adapter),
1252 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
1254 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
1257 static const struct rte_pci_id pci_id_hns3vf_map[] = {
1258 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
1259 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
1260 { .vendor_id = 0, /* sentinel */ },
1263 static struct rte_pci_driver rte_hns3vf_pmd = {
1264 .id_table = pci_id_hns3vf_map,
1265 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1266 .probe = eth_hns3vf_pci_probe,
1267 .remove = eth_hns3vf_pci_remove,
1270 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
1271 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
1272 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");