drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
  48                                    __rte_unused int wait_to_complete);
  49
  50 /* set PCI bus mastering */
  51 static int
  52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  53 {
  54         uint16_t reg;
  55         int ret;
  56
  57         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  58         if (ret < 0) {
  59                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  60                              PCI_COMMAND);
  61                 return ret;
  62         }
  63
  64         if (op)
  65                 /* set the master bit */
  66                 reg |= PCI_COMMAND_MASTER;
  67         else
  68                 reg &= ~(PCI_COMMAND_MASTER);
  69
  70         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  71 }
  72
  73 /**
  74  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  75  * @cap: the capability
  76  *
  77  * Return the address of the given capability within the PCI capability list.
  78  */
  79 static int
  80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  81 {
  82 #define MAX_PCIE_CAPABILITY 48
  83         uint16_t status;
  84         uint8_t pos;
  85         uint8_t id;
  86         int ttl;
  87         int ret;
  88
  89         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  90         if (ret < 0) {
  91                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  92                 return 0;
  93         }
  94
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 100                                   PCI_CAPABILITY_LIST);
 101         if (ret < 0) {
 102                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 103                              PCI_CAPABILITY_LIST);
 104                 return 0;
 105         }
 106
 107         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 108                 ret = rte_pci_read_config(device, &id, sizeof(id),
 109                                           (pos + PCI_CAP_LIST_ID));
 110                 if (ret < 0) {
 111                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 112                                      (pos + PCI_CAP_LIST_ID));
 113                         break;
 114                 }
 115
 116                 if (id == 0xFF)
 117                         break;
 118
 119                 if (id == cap)
 120                         return (int)pos;
 121
 122                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 123                                           (pos + PCI_CAP_LIST_NEXT));
 124                 if (ret < 0) {
 125                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 126                                      (pos + PCI_CAP_LIST_NEXT));
 127                         break;
 128                 }
 129         }
 130         return 0;
 131 }
 132
 133 static int
 134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 135 {
 136         uint16_t control;
 137         int pos;
 138         int ret;
 139
 140         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 141         if (pos) {
 142                 ret = rte_pci_read_config(device, &control, sizeof(control),
 143                                     (pos + PCI_MSIX_FLAGS));
 144                 if (ret < 0) {
 145                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 146                                      (pos + PCI_MSIX_FLAGS));
 147                         return -ENXIO;
 148                 }
 149
 150                 if (op)
 151                         control |= PCI_MSIX_FLAGS_ENABLE;
 152                 else
 153                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 154                 ret = rte_pci_write_config(device, &control, sizeof(control),
 155                                           (pos + PCI_MSIX_FLAGS));
 156                 if (ret < 0) {
 157                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 158                                     (pos + PCI_MSIX_FLAGS));
 159                         return -ENXIO;
 160                 }
 161
 162                 return 0;
 163         }
 164
 165         return -ENXIO;
 166 }
 167
 168 static int
 169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 170 {
 171         /* mac address was checked by upper level interface */
 172         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 173         int ret;
 174
 175         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 176                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 177                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 178         if (ret) {
 179                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 180                                       mac_addr);
 181                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 182                          mac_str, ret);
 183         }
 184         return ret;
 185 }
 186
 187 static int
 188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 189 {
 190         /* mac address was checked by upper level interface */
 191         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 192         int ret;
 193
 194         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 195                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 196                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 197                                 false, NULL, 0);
 198         if (ret) {
 199                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 200                                       mac_addr);
 201                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 202                          mac_str, ret);
 203         }
 204         return ret;
 205 }
 206
 207 static int
 208 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 209 {
 210         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 211         struct rte_ether_addr *addr;
 212         int ret;
 213         int i;
 214
 215         for (i = 0; i < hw->mc_addrs_num; i++) {
 216                 addr = &hw->mc_addrs[i];
 217                 /* Check if there are duplicate addresses */
 218                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 219                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 220                                               addr);
 221                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 222                                  "(%s) is added by the set_mc_mac_addr_list "
 223                                  "API", mac_str);
 224                         return -EINVAL;
 225                 }
 226         }
 227
 228         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 229         if (ret) {
 230                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 231                                       mac_addr);
 232                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 233                          mac_str, ret);
 234         }
 235         return ret;
 236 }
 237
 238 static int
 239 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 240                     __rte_unused uint32_t idx,
 241                     __rte_unused uint32_t pool)
 242 {
 243         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 244         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 245         int ret;
 246
 247         rte_spinlock_lock(&hw->lock);
 248
 249         /*
 250          * In hns3 network engine adding UC and MC mac address with different
 251          * commands with firmware. We need to determine whether the input
 252          * address is a UC or a MC address to call different commands.
 253          * By the way, it is recommended calling the API function named
 254          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 255          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 256          * may affect the specifications of UC mac addresses.
 257          */
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 260         else
 261                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 268                          ret);
 269         }
 270
 271         return ret;
 272 }
 273
 274 static void
 275 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 276 {
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         /* index will be checked by upper level rte interface */
 279         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         rte_spinlock_lock(&hw->lock);
 284
 285         if (rte_is_multicast_ether_addr(mac_addr))
 286                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 287         else
 288                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 289
 290         rte_spinlock_unlock(&hw->lock);
 291         if (ret) {
 292                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 293                                       mac_addr);
 294                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 295                          mac_str, ret);
 296         }
 297 }
 298
 299 static int
 300 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 301                             struct rte_ether_addr *mac_addr)
 302 {
 303 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 304         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 305         struct rte_ether_addr *old_addr;
 306         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 307         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 308         int ret;
 309
 310         /*
 311          * It has been guaranteed that input parameter named mac_addr is valid
 312          * address in the rte layer of DPDK framework.
 313          */
 314         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 315         rte_spinlock_lock(&hw->lock);
 316         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 317         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 318                RTE_ETHER_ADDR_LEN);
 319
 320         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 321                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 322                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 323         if (ret) {
 324                 /*
 325                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 326                  * driver. When user has configured a MAC address for VF device
 327                  * by "ip link set ..." command based on the PF device, the hns3
 328                  * PF kernel ethdev driver does not allow VF driver to request
 329                  * reconfiguring a different default MAC address, and return
 330                  * -EPREM to VF driver through mailbox.
 331                  */
 332                 if (ret == -EPERM) {
 333                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 334                                               old_addr);
 335                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 336                                   mac_str);
 337                 } else {
 338                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 339                                               mac_addr);
 340                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 341                                  mac_str, ret);
 342                 }
 343         }
 344
 345         rte_ether_addr_copy(mac_addr,
 346                             (struct rte_ether_addr *)hw->mac.mac_addr);
 347         rte_spinlock_unlock(&hw->lock);
 348
 349         return ret;
 350 }
 351
 352 static int
 353 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 354 {
 355         struct hns3_hw *hw = &hns->hw;
 356         struct rte_ether_addr *addr;
 357         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 358         int err = 0;
 359         int ret;
 360         int i;
 361
 362         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 363                 addr = &hw->data->mac_addrs[i];
 364                 if (rte_is_zero_ether_addr(addr))
 365                         continue;
 366                 if (rte_is_multicast_ether_addr(addr))
 367                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 368                               hns3vf_add_mc_mac_addr(hw, addr);
 369                 else
 370                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 371                               hns3vf_add_uc_mac_addr(hw, addr);
 372
 373                 if (ret) {
 374                         err = ret;
 375                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 376                                               addr);
 377                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 378                                  "ret = %d.", del ? "remove" : "restore",
 379                                  mac_str, i, ret);
 380                 }
 381         }
 382         return err;
 383 }
 384
 385 static int
 386 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 387                        struct rte_ether_addr *mac_addr)
 388 {
 389         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 390         int ret;
 391
 392         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 393                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 394                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 395                                 NULL, 0);
 396         if (ret) {
 397                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 398                                       mac_addr);
 399                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 400                          mac_str, ret);
 401         }
 402
 403         return ret;
 404 }
 405
 406 static int
 407 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 408                           struct rte_ether_addr *mac_addr)
 409 {
 410         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 411         int ret;
 412
 413         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 414                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 415                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 416                                 NULL, 0);
 417         if (ret) {
 418                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 419                                       mac_addr);
 420                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 421                          mac_str, ret);
 422         }
 423
 424         return ret;
 425 }
 426
 427 static int
 428 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 429                              struct rte_ether_addr *mc_addr_set,
 430                              uint32_t nb_mc_addr)
 431 {
 432         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 433         struct rte_ether_addr *addr;
 434         uint32_t i;
 435         uint32_t j;
 436
 437         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 438                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
 439                          "invalid. valid range: 0~%d",
 440                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 441                 return -EINVAL;
 442         }
 443
 444         /* Check if input mac addresses are valid */
 445         for (i = 0; i < nb_mc_addr; i++) {
 446                 addr = &mc_addr_set[i];
 447                 if (!rte_is_multicast_ether_addr(addr)) {
 448                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 449                                               addr);
 450                         hns3_err(hw,
 451                                  "failed to set mc mac addr, addr(%s) invalid.",
 452                                  mac_str);
 453                         return -EINVAL;
 454                 }
 455
 456                 /* Check if there are duplicate addresses */
 457                 for (j = i + 1; j < nb_mc_addr; j++) {
 458                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 459                                 hns3_ether_format_addr(mac_str,
 460                                                       RTE_ETHER_ADDR_FMT_SIZE,
 461                                                       addr);
 462                                 hns3_err(hw, "failed to set mc mac addr, "
 463                                          "addrs invalid. two same addrs(%s).",
 464                                          mac_str);
 465                                 return -EINVAL;
 466                         }
 467                 }
 468
 469                 /*
 470                  * Check if there are duplicate addresses between mac_addrs
 471                  * and mc_addr_set
 472                  */
 473                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 474                         if (rte_is_same_ether_addr(addr,
 475                                                    &hw->data->mac_addrs[j])) {
 476                                 hns3_ether_format_addr(mac_str,
 477                                                       RTE_ETHER_ADDR_FMT_SIZE,
 478                                                       addr);
 479                                 hns3_err(hw, "failed to set mc mac addr, "
 480                                          "addrs invalid. addrs(%s) has already "
 481                                          "configured in mac_addr add API",
 482                                          mac_str);
 483                                 return -EINVAL;
 484                         }
 485                 }
 486         }
 487
 488         return 0;
 489 }
 490
 491 static int
 492 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 493                             struct rte_ether_addr *mc_addr_set,
 494                             uint32_t nb_mc_addr)
 495 {
 496         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 497         struct rte_ether_addr *addr;
 498         int cur_addr_num;
 499         int set_addr_num;
 500         int num;
 501         int ret;
 502         int i;
 503
 504         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 505         if (ret)
 506                 return ret;
 507
 508         rte_spinlock_lock(&hw->lock);
 509         cur_addr_num = hw->mc_addrs_num;
 510         for (i = 0; i < cur_addr_num; i++) {
 511                 num = cur_addr_num - i - 1;
 512                 addr = &hw->mc_addrs[num];
 513                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 514                 if (ret) {
 515                         rte_spinlock_unlock(&hw->lock);
 516                         return ret;
 517                 }
 518
 519                 hw->mc_addrs_num--;
 520         }
 521
 522         set_addr_num = (int)nb_mc_addr;
 523         for (i = 0; i < set_addr_num; i++) {
 524                 addr = &mc_addr_set[i];
 525                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 526                 if (ret) {
 527                         rte_spinlock_unlock(&hw->lock);
 528                         return ret;
 529                 }
 530
 531                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 532                 hw->mc_addrs_num++;
 533         }
 534         rte_spinlock_unlock(&hw->lock);
 535
 536         return 0;
 537 }
 538
 539 static int
 540 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 541 {
 542         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 543         struct hns3_hw *hw = &hns->hw;
 544         struct rte_ether_addr *addr;
 545         int err = 0;
 546         int ret;
 547         int i;
 548
 549         for (i = 0; i < hw->mc_addrs_num; i++) {
 550                 addr = &hw->mc_addrs[i];
 551                 if (!rte_is_multicast_ether_addr(addr))
 552                         continue;
 553                 if (del)
 554                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 555                 else
 556                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 557                 if (ret) {
 558                         err = ret;
 559                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 560                                               addr);
 561                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 562                                  del ? "Remove" : "Restore", mac_str, ret);
 563                 }
 564         }
 565         return err;
 566 }
 567
 568 static int
 569 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 570                         bool en_uc_pmc, bool en_mc_pmc)
 571 {
 572         struct hns3_mbx_vf_to_pf_cmd *req;
 573         struct hns3_cmd_desc desc;
 574         int ret;
 575
 576         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 577
 578         /*
 579          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 580          * so there are some features for promiscuous/allmulticast mode in hns3
 581          * VF PMD driver as below:
 582          * 1. The promiscuous/allmulticast mode can be configured successfully
 583          *    only based on the trusted VF device. If based on the non trusted
 584          *    VF device, configuring promiscuous/allmulticast mode will fail.
 585          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 586          *    kernel ethdev driver on the host by the following command:
 587          *      "ip link set <eth num> vf <vf id> turst on"
 588          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 589          *    driver can receive the ingress and outgoing traffic. In the words,
 590          *    all the ingress packets, all the packets sent from the PF and
 591          *    other VFs on the same physical port.
 592          * 3. Note: Because of the hardware constraints, By default vlan filter
 593          *    is enabled and couldn't be turned off based on VF device, so vlan
 594          *    filter is still effective even in promiscuous mode. If upper
 595          *    applications don't call rte_eth_dev_vlan_filter API function to
 596          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 597          *    the packets with vlan tag in promiscuoue mode.
 598          */
 599         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 600         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 601         req->msg[1] = en_bc_pmc ? 1 : 0;
 602         req->msg[2] = en_uc_pmc ? 1 : 0;
 603         req->msg[3] = en_mc_pmc ? 1 : 0;
 604         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 605
 606         ret = hns3_cmd_send(hw, &desc, 1);
 607         if (ret)
 608                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 609
 610         return ret;
 611 }
 612
 613 static int
 614 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 615 {
 616         struct hns3_adapter *hns = dev->data->dev_private;
 617         struct hns3_hw *hw = &hns->hw;
 618         int ret;
 619
 620         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 621         if (ret)
 622                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 623                         ret);
 624         return ret;
 625 }
 626
 627 static int
 628 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 629 {
 630         bool allmulti = dev->data->all_multicast ? true : false;
 631         struct hns3_adapter *hns = dev->data->dev_private;
 632         struct hns3_hw *hw = &hns->hw;
 633         int ret;
 634
 635         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 636         if (ret)
 637                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 638                         ret);
 639         return ret;
 640 }
 641
 642 static int
 643 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 644 {
 645         struct hns3_adapter *hns = dev->data->dev_private;
 646         struct hns3_hw *hw = &hns->hw;
 647         int ret;
 648
 649         if (dev->data->promiscuous)
 650                 return 0;
 651
 652         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 653         if (ret)
 654                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 655                         ret);
 656         return ret;
 657 }
 658
 659 static int
 660 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 661 {
 662         struct hns3_adapter *hns = dev->data->dev_private;
 663         struct hns3_hw *hw = &hns->hw;
 664         int ret;
 665
 666         if (dev->data->promiscuous)
 667                 return 0;
 668
 669         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 670         if (ret)
 671                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 672                         ret);
 673         return ret;
 674 }
 675
 676 static int
 677 hns3vf_restore_promisc(struct hns3_adapter *hns)
 678 {
 679         struct hns3_hw *hw = &hns->hw;
 680         bool allmulti = hw->data->all_multicast ? true : false;
 681
 682         if (hw->data->promiscuous)
 683                 return hns3vf_set_promisc_mode(hw, true, true, true);
 684
 685         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 686 }
 687
 688 static int
 689 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 690                              bool mmap, enum hns3_ring_type queue_type,
 691                              uint16_t queue_id)
 692 {
 693         struct hns3_vf_bind_vector_msg bind_msg;
 694         const char *op_str;
 695         uint16_t code;
 696         int ret;
 697
 698         memset(&bind_msg, 0, sizeof(bind_msg));
 699         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 700                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 701         bind_msg.vector_id = vector_id;
 702
 703         if (queue_type == HNS3_RING_TYPE_RX)
 704                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 705         else
 706                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 707
 708         bind_msg.param[0].ring_type = queue_type;
 709         bind_msg.ring_num = 1;
 710         bind_msg.param[0].tqp_index = queue_id;
 711         op_str = mmap ? "Map" : "Unmap";
 712         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 713                                 sizeof(bind_msg), false, NULL, 0);
 714         if (ret)
 715                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 716                          op_str, queue_id, bind_msg.vector_id, ret);
 717
 718         return ret;
 719 }
 720
 721 static int
 722 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 723 {
 724         uint16_t vec;
 725         int ret;
 726         int i;
 727
 728         /*
 729          * In hns3 network engine, vector 0 is always the misc interrupt of this
 730          * function, vector 1~N can be used respectively for the queues of the
 731          * function. Tx and Rx queues with the same number share the interrupt
 732          * vector. In the initialization clearing the all hardware mapping
 733          * relationship configurations between queues and interrupt vectors is
 734          * needed, so some error caused by the residual configurations, such as
 735          * the unexpected Tx interrupt, can be avoid.
 736          */
 737         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 738         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 739                 vec = vec - 1; /* the last interrupt is reserved */
 740         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 741         for (i = 0; i < hw->intr_tqps_num; i++) {
 742                 /*
 743                  * Set gap limiter/rate limiter/quanity limiter algorithm
 744                  * configuration for interrupt coalesce of queue's interrupt.
 745                  */
 746                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 747                                        HNS3_TQP_INTR_GL_DEFAULT);
 748                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 749                                        HNS3_TQP_INTR_GL_DEFAULT);
 750                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 751                 /*
 752                  * QL(quantity limiter) is not used currently, just set 0 to
 753                  * close it.
 754                  */
 755                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 756
 757                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 758                                                    HNS3_RING_TYPE_TX, i);
 759                 if (ret) {
 760                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 761                                           "vector: %u, ret=%d", i, vec, ret);
 762                         return ret;
 763                 }
 764
 765                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 766                                                    HNS3_RING_TYPE_RX, i);
 767                 if (ret) {
 768                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 769                                           "vector: %u, ret=%d", i, vec, ret);
 770                         return ret;
 771                 }
 772         }
 773
 774         return 0;
 775 }
 776
 777 static int
 778 hns3vf_dev_configure(struct rte_eth_dev *dev)
 779 {
 780         struct hns3_adapter *hns = dev->data->dev_private;
 781         struct hns3_hw *hw = &hns->hw;
 782         struct rte_eth_conf *conf = &dev->data->dev_conf;
 783         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 784         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 785         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 786         struct rte_eth_rss_conf rss_conf;
 787         bool gro_en;
 788         int ret;
 789
 790         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 791
 792         /*
 793          * Some versions of hardware network engine does not support
 794          * individually enable/disable/reset the Tx or Rx queue. These devices
 795          * must enable/disable/reset Tx and Rx queues at the same time. When the
 796          * numbers of Tx queues allocated by upper applications are not equal to
 797          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 798          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 799          * work as usual. But these fake queues are imperceptible, and can not
 800          * be used by upper applications.
 801          */
 802         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 803         if (ret) {
 804                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
 805                 hw->cfg_max_queues = 0;
 806                 return ret;
 807         }
 808
 809         hw->adapter_state = HNS3_NIC_CONFIGURING;
 810         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 811                 hns3_err(hw, "setting link speed/duplex not supported");
 812                 ret = -EINVAL;
 813                 goto cfg_err;
 814         }
 815
 816         /* When RSS is not configured, redirect the packet queue 0 */
 817         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 818                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 819                 hw->rss_dis_flag = false;
 820                 rss_conf = conf->rx_adv_conf.rss_conf;
 821                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 822                 if (ret)
 823                         goto cfg_err;
 824         }
 825
 826         ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
 827         if (ret != 0)
 828                 goto cfg_err;
 829
 830         ret = hns3vf_dev_configure_vlan(dev);
 831         if (ret)
 832                 goto cfg_err;
 833
 834         /* config hardware GRO */
 835         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 836         ret = hns3_config_gro(hw, gro_en);
 837         if (ret)
 838                 goto cfg_err;
 839
 840         hns3_init_rx_ptype_tble(dev);
 841
 842         hw->adapter_state = HNS3_NIC_CONFIGURED;
 843         return 0;
 844
 845 cfg_err:
 846         hw->cfg_max_queues = 0;
 847         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 848         hw->adapter_state = HNS3_NIC_INITIALIZED;
 849
 850         return ret;
 851 }
 852
 853 static int
 854 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 855 {
 856         int ret;
 857
 858         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 859                                 sizeof(mtu), true, NULL, 0);
 860         if (ret)
 861                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 862
 863         return ret;
 864 }
 865
 866 static int
 867 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 868 {
 869         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 870         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 871         int ret;
 872
 873         /*
 874          * The hns3 PF/VF devices on the same port share the hardware MTU
 875          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 876          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 877          * driver, there is no need to stop the port for hns3 VF device, and the
 878          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 879          * PF's MTU.
 880          */
 881         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 882                 hns3_err(hw, "Failed to set mtu during resetting");
 883                 return -EIO;
 884         }
 885
 886         /*
 887          * when Rx of scattered packets is off, we have some possibility of
 888          * using vector Rx process function or simple Rx functions in hns3 PMD
 889          * driver. If the input MTU is increased and the maximum length of
 890          * received packets is greater than the length of a buffer for Rx
 891          * packet, the hardware network engine needs to use multiple BDs and
 892          * buffers to store these packets. This will cause problems when still
 893          * using vector Rx process function or simple Rx function to receiving
 894          * packets. So, when Rx of scattered packets is off and device is
 895          * started, it is not permitted to increase MTU so that the maximum
 896          * length of Rx packets is greater than Rx buffer length.
 897          */
 898         if (dev->data->dev_started && !dev->data->scattered_rx &&
 899             frame_size > hw->rx_buf_len) {
 900                 hns3_err(hw, "failed to set mtu because current is "
 901                         "not scattered rx mode");
 902                 return -EOPNOTSUPP;
 903         }
 904
 905         rte_spinlock_lock(&hw->lock);
 906         ret = hns3vf_config_mtu(hw, mtu);
 907         if (ret) {
 908                 rte_spinlock_unlock(&hw->lock);
 909                 return ret;
 910         }
 911         rte_spinlock_unlock(&hw->lock);
 912
 913         return 0;
 914 }
 915
 916 static int
 917 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 918 {
 919         struct hns3_adapter *hns = eth_dev->data->dev_private;
 920         struct hns3_hw *hw = &hns->hw;
 921         uint16_t q_num = hw->tqps_num;
 922
 923         /*
 924          * In interrupt mode, 'max_rx_queues' is set based on the number of
 925          * MSI-X interrupt resources of the hardware.
 926          */
 927         if (hw->data->dev_conf.intr_conf.rxq == 1)
 928                 q_num = hw->intr_tqps_num;
 929
 930         info->max_rx_queues = q_num;
 931         info->max_tx_queues = hw->tqps_num;
 932         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 933         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 934         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 935         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 936         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 937
 938         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 939                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 940                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 941                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 942                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 943                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 944                                  DEV_RX_OFFLOAD_SCATTER |
 945                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 946                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 947                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 948                                  DEV_RX_OFFLOAD_RSS_HASH |
 949                                  DEV_RX_OFFLOAD_TCP_LRO);
 950         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 951                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 952                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 953                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 954                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 955                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 956                                  DEV_TX_OFFLOAD_TCP_TSO |
 957                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 958                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 959                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 960                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 961                                  hns3_txvlan_cap_get(hw));
 962
 963         if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
 964                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
 965
 966         if (hns3_dev_get_support(hw, INDEP_TXRX))
 967                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 968                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 969
 970         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 971                 .nb_max = HNS3_MAX_RING_DESC,
 972                 .nb_min = HNS3_MIN_RING_DESC,
 973                 .nb_align = HNS3_ALIGN_RING_DESC,
 974         };
 975
 976         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 977                 .nb_max = HNS3_MAX_RING_DESC,
 978                 .nb_min = HNS3_MIN_RING_DESC,
 979                 .nb_align = HNS3_ALIGN_RING_DESC,
 980                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 981                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
 982         };
 983
 984         info->default_rxconf = (struct rte_eth_rxconf) {
 985                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 986                 /*
 987                  * If there are no available Rx buffer descriptors, incoming
 988                  * packets are always dropped by hardware based on hns3 network
 989                  * engine.
 990                  */
 991                 .rx_drop_en = 1,
 992                 .offloads = 0,
 993         };
 994         info->default_txconf = (struct rte_eth_txconf) {
 995                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 996                 .offloads = 0,
 997         };
 998
 999         info->reta_size = hw->rss_ind_tbl_size;
1000         info->hash_key_size = HNS3_RSS_KEY_SIZE;
1001         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1002
1003         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1004         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1005         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1006         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1007         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1008         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1009
1010         return 0;
1011 }
1012
1013 static void
1014 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1015 {
1016         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1017 }
1018
1019 static void
1020 hns3vf_disable_irq0(struct hns3_hw *hw)
1021 {
1022         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1023 }
1024
1025 static void
1026 hns3vf_enable_irq0(struct hns3_hw *hw)
1027 {
1028         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1029 }
1030
1031 static enum hns3vf_evt_cause
1032 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1033 {
1034         struct hns3_hw *hw = &hns->hw;
1035         enum hns3vf_evt_cause ret;
1036         uint32_t cmdq_stat_reg;
1037         uint32_t rst_ing_reg;
1038         uint32_t val;
1039
1040         /* Fetch the events from their corresponding regs */
1041         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1042         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1043                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1044                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1045                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1046                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
1047                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1048                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1049                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1050                 if (clearval) {
1051                         hw->reset.stats.global_cnt++;
1052                         hns3_warn(hw, "Global reset detected, clear reset status");
1053                 } else {
1054                         hns3_schedule_delayed_reset(hns);
1055                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1056                 }
1057
1058                 ret = HNS3VF_VECTOR0_EVENT_RST;
1059                 goto out;
1060         }
1061
1062         /* Check for vector0 mailbox(=CMDQ RX) event source */
1063         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1064                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1065                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1066                 goto out;
1067         }
1068
1069         val = 0;
1070         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1071 out:
1072         if (clearval)
1073                 *clearval = val;
1074         return ret;
1075 }
1076
1077 static void
1078 hns3vf_interrupt_handler(void *param)
1079 {
1080         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1081         struct hns3_adapter *hns = dev->data->dev_private;
1082         struct hns3_hw *hw = &hns->hw;
1083         enum hns3vf_evt_cause event_cause;
1084         uint32_t clearval;
1085
1086         /* Disable interrupt */
1087         hns3vf_disable_irq0(hw);
1088
1089         /* Read out interrupt causes */
1090         event_cause = hns3vf_check_event_cause(hns, &clearval);
1091         /* Clear interrupt causes */
1092         hns3vf_clear_event_cause(hw, clearval);
1093
1094         switch (event_cause) {
1095         case HNS3VF_VECTOR0_EVENT_RST:
1096                 hns3_schedule_reset(hns);
1097                 break;
1098         case HNS3VF_VECTOR0_EVENT_MBX:
1099                 hns3_dev_handle_mbx_msg(hw);
1100                 break;
1101         default:
1102                 break;
1103         }
1104
1105         /* Enable interrupt */
1106         hns3vf_enable_irq0(hw);
1107 }
1108
1109 static void
1110 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1111 {
1112         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1113         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1114         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1115         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
1116 }
1117
1118 static void
1119 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1120 {
1121         struct hns3_dev_specs_0_cmd *req0;
1122
1123         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1124
1125         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1126         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1127         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1128         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
1129 }
1130
1131 static int
1132 hns3vf_check_dev_specifications(struct hns3_hw *hw)
1133 {
1134         if (hw->rss_ind_tbl_size == 0 ||
1135             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
1136                 hns3_warn(hw, "the size of hash lookup table configured (%u)"
1137                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
1138                               HNS3_RSS_IND_TBL_SIZE_MAX);
1139                 return -EINVAL;
1140         }
1141
1142         return 0;
1143 }
1144
1145 static int
1146 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1147 {
1148         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1149         int ret;
1150         int i;
1151
1152         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1153                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1154                                           true);
1155                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1156         }
1157         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1158
1159         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1160         if (ret)
1161                 return ret;
1162
1163         hns3vf_parse_dev_specifications(hw, desc);
1164
1165         return hns3vf_check_dev_specifications(hw);
1166 }
1167
1168 void
1169 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
1170 {
1171         uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
1172                                    HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1173         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1174         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1175
1176         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1177                 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1178                                           __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1179 }
1180
1181 static void
1182 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
1183 {
1184 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS      500
1185
1186         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1187         int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
1188         uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1189         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1190         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1191
1192         __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
1193                          __ATOMIC_RELEASE);
1194
1195         (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1196                                 NULL, 0);
1197
1198         while (remain_ms > 0) {
1199                 rte_delay_ms(HNS3_POLL_RESPONE_MS);
1200                 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
1201                         HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1202                         break;
1203                 remain_ms--;
1204         }
1205
1206         /*
1207          * When exit above loop, the pf_push_lsc_cap could be one of the three
1208          * state: unknown (means pf not ack), not_supported, supported.
1209          * Here config it as 'not_supported' when it's 'unknown' state.
1210          */
1211         __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1212                                   __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1213
1214         if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
1215                 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
1216                 hns3_info(hw, "detect PF support push link status change!");
1217         } else {
1218                 /*
1219                  * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
1220                  * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
1221                  * the RTE_ETH_DEV_INTR_LSC capability.
1222                  */
1223                 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
1224         }
1225 }
1226
1227 static int
1228 hns3vf_get_capability(struct hns3_hw *hw)
1229 {
1230         struct rte_pci_device *pci_dev;
1231         struct rte_eth_dev *eth_dev;
1232         uint8_t revision;
1233         int ret;
1234
1235         eth_dev = &rte_eth_devices[hw->data->port_id];
1236         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1237
1238         /* Get PCI revision id */
1239         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1240                                   HNS3_PCI_REVISION_ID);
1241         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1242                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1243                              ret);
1244                 return -EIO;
1245         }
1246         hw->revision = revision;
1247
1248         if (revision < PCI_REVISION_ID_HIP09_A) {
1249                 hns3vf_set_default_dev_specifications(hw);
1250                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1251                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1252                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1253                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
1254                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1255                 hw->rss_info.ipv6_sctp_offload_supported = false;
1256                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1257                 return 0;
1258         }
1259
1260         ret = hns3vf_query_dev_specifications(hw);
1261         if (ret) {
1262                 PMD_INIT_LOG(ERR,
1263                              "failed to query dev specifications, ret = %d",
1264                              ret);
1265                 return ret;
1266         }
1267
1268         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1269         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1270         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1271         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1272         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1273         hw->rss_info.ipv6_sctp_offload_supported = true;
1274         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1275
1276         return 0;
1277 }
1278
1279 static int
1280 hns3vf_check_tqp_info(struct hns3_hw *hw)
1281 {
1282         if (hw->tqps_num == 0) {
1283                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1284                 return -EINVAL;
1285         }
1286
1287         if (hw->rss_size_max == 0) {
1288                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1289                 return -EINVAL;
1290         }
1291
1292         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1293
1294         return 0;
1295 }
1296
1297 static int
1298 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1299 {
1300         uint8_t resp_msg;
1301         int ret;
1302
1303         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1304                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1305                                 true, &resp_msg, sizeof(resp_msg));
1306         if (ret) {
1307                 if (ret == -ETIME) {
1308                         /*
1309                          * Getting current port based VLAN state from PF driver
1310                          * will not affect VF driver's basic function. Because
1311                          * the VF driver relies on hns3 PF kernel ether driver,
1312                          * to avoid introducing compatibility issues with older
1313                          * version of PF driver, no failure will be returned
1314                          * when the return value is ETIME. This return value has
1315                          * the following scenarios:
1316                          * 1) Firmware didn't return the results in time
1317                          * 2) the result return by firmware is timeout
1318                          * 3) the older version of kernel side PF driver does
1319                          *    not support this mailbox message.
1320                          * For scenarios 1 and 2, it is most likely that a
1321                          * hardware error has occurred, or a hardware reset has
1322                          * occurred. In this case, these errors will be caught
1323                          * by other functions.
1324                          */
1325                         PMD_INIT_LOG(WARNING,
1326                                 "failed to get PVID state for timeout, maybe "
1327                                 "kernel side PF driver doesn't support this "
1328                                 "mailbox message, or firmware didn't respond.");
1329                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1330                 } else {
1331                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1332                                 " ret = %d", ret);
1333                         return ret;
1334                 }
1335         }
1336         hw->port_base_vlan_cfg.state = resp_msg ?
1337                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1338         return 0;
1339 }
1340
1341 static int
1342 hns3vf_get_queue_info(struct hns3_hw *hw)
1343 {
1344 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1345         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1346         int ret;
1347
1348         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1349                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1350         if (ret) {
1351                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1352                 return ret;
1353         }
1354
1355         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1356         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1357
1358         return hns3vf_check_tqp_info(hw);
1359 }
1360
1361 static int
1362 hns3vf_get_queue_depth(struct hns3_hw *hw)
1363 {
1364 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1365         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1366         int ret;
1367
1368         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1369                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1370         if (ret) {
1371                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1372                              ret);
1373                 return ret;
1374         }
1375
1376         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1377         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1378
1379         return 0;
1380 }
1381
1382 static void
1383 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
1384 {
1385         if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
1386                 hns3_set_bit(hw->capability,
1387                                 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
1388 }
1389
1390 static int
1391 hns3vf_get_num_tc(struct hns3_hw *hw)
1392 {
1393         uint8_t num_tc = 0;
1394         uint32_t i;
1395
1396         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1397                 if (hw->hw_tc_map & BIT(i))
1398                         num_tc++;
1399         }
1400         return num_tc;
1401 }
1402
1403 static int
1404 hns3vf_get_basic_info(struct hns3_hw *hw)
1405 {
1406         uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
1407         struct hns3_basic_info *basic_info;
1408         int ret;
1409
1410         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
1411                                 true, resp_msg, sizeof(resp_msg));
1412         if (ret) {
1413                 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
1414                                 ret);
1415                 return ret;
1416         }
1417
1418         basic_info = (struct hns3_basic_info *)resp_msg;
1419         hw->hw_tc_map = basic_info->hw_tc_map;
1420         hw->num_tc = hns3vf_get_num_tc(hw);
1421         hw->pf_vf_if_version = basic_info->pf_vf_if_version;
1422         hns3vf_update_caps(hw, basic_info->caps);
1423
1424         return 0;
1425 }
1426
1427 static int
1428 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1429 {
1430         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1431         int ret;
1432
1433         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1434                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1435         if (ret) {
1436                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1437                 return ret;
1438         }
1439
1440         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1441
1442         return 0;
1443 }
1444
1445 static int
1446 hns3vf_get_configuration(struct hns3_hw *hw)
1447 {
1448         int ret;
1449
1450         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1451         hw->rss_dis_flag = false;
1452
1453         /* Get device capability */
1454         ret = hns3vf_get_capability(hw);
1455         if (ret) {
1456                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1457                 return ret;
1458         }
1459
1460         hns3vf_get_push_lsc_cap(hw);
1461
1462         /* Get basic info from PF */
1463         ret = hns3vf_get_basic_info(hw);
1464         if (ret)
1465                 return ret;
1466
1467         /* Get queue configuration from PF */
1468         ret = hns3vf_get_queue_info(hw);
1469         if (ret)
1470                 return ret;
1471
1472         /* Get queue depth info from PF */
1473         ret = hns3vf_get_queue_depth(hw);
1474         if (ret)
1475                 return ret;
1476
1477         /* Get user defined VF MAC addr from PF */
1478         ret = hns3vf_get_host_mac_addr(hw);
1479         if (ret)
1480                 return ret;
1481
1482         return hns3vf_get_port_base_vlan_filter_state(hw);
1483 }
1484
1485 static int
1486 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1487                             uint16_t nb_tx_q)
1488 {
1489         struct hns3_hw *hw = &hns->hw;
1490
1491         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1492 }
1493
1494 static void
1495 hns3vf_request_link_info(struct hns3_hw *hw)
1496 {
1497         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1498         bool send_req;
1499         int ret;
1500
1501         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1502                 return;
1503
1504         send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1505                    vf->req_link_info_cnt > 0;
1506         if (!send_req)
1507                 return;
1508
1509         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1510                                 NULL, 0);
1511         if (ret) {
1512                 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1513                 return;
1514         }
1515
1516         if (vf->req_link_info_cnt > 0)
1517                 vf->req_link_info_cnt--;
1518 }
1519
1520 void
1521 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1522                           uint32_t link_speed, uint8_t link_duplex)
1523 {
1524         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1525         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1526         struct hns3_mac *mac = &hw->mac;
1527         int ret;
1528
1529         /*
1530          * PF kernel driver may push link status when VF driver is in resetting,
1531          * driver will stop polling job in this case, after resetting done
1532          * driver will start polling job again.
1533          * When polling job started, driver will get initial link status by
1534          * sending request to PF kernel driver, then could update link status by
1535          * process PF kernel driver's link status mailbox message.
1536          */
1537         if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1538                 return;
1539
1540         if (hw->adapter_state != HNS3_NIC_STARTED)
1541                 return;
1542
1543         mac->link_status = link_status;
1544         mac->link_speed = link_speed;
1545         mac->link_duplex = link_duplex;
1546         ret = hns3vf_dev_link_update(dev, 0);
1547         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1548                 hns3_start_report_lse(dev);
1549 }
1550
1551 static int
1552 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1553 {
1554 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1555         struct hns3_hw *hw = &hns->hw;
1556         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1557         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1558         uint8_t is_kill = on ? 0 : 1;
1559
1560         msg_data[0] = is_kill;
1561         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1562         memcpy(&msg_data[3], &proto, sizeof(proto));
1563
1564         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1565                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1566                                  0);
1567 }
1568
1569 static int
1570 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1571 {
1572         struct hns3_adapter *hns = dev->data->dev_private;
1573         struct hns3_hw *hw = &hns->hw;
1574         int ret;
1575
1576         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1577                 hns3_err(hw,
1578                          "vf set vlan id failed during resetting, vlan_id =%u",
1579                          vlan_id);
1580                 return -EIO;
1581         }
1582         rte_spinlock_lock(&hw->lock);
1583         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1584         rte_spinlock_unlock(&hw->lock);
1585         if (ret)
1586                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1587                          vlan_id, ret);
1588
1589         return ret;
1590 }
1591
1592 static int
1593 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1594 {
1595         uint8_t msg_data;
1596         int ret;
1597
1598         if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1599                 return 0;
1600
1601         msg_data = enable ? 1 : 0;
1602         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1603                         HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1604                         sizeof(msg_data), true, NULL, 0);
1605         if (ret)
1606                 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1607                                 enable ? "enable" : "disable", ret);
1608
1609         return ret;
1610 }
1611
1612 static int
1613 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1614 {
1615         uint8_t msg_data;
1616         int ret;
1617
1618         msg_data = enable ? 1 : 0;
1619         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1620                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1621         if (ret)
1622                 hns3_err(hw, "vf %s strip failed, ret = %d.",
1623                                 enable ? "enable" : "disable", ret);
1624
1625         return ret;
1626 }
1627
1628 static int
1629 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1630 {
1631         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1632         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1633         unsigned int tmp_mask;
1634         int ret = 0;
1635
1636         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1637                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1638                              "mask = 0x%x", mask);
1639                 return -EIO;
1640         }
1641
1642         tmp_mask = (unsigned int)mask;
1643
1644         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
1645                 rte_spinlock_lock(&hw->lock);
1646                 /* Enable or disable VLAN filter */
1647                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1648                         ret = hns3vf_en_vlan_filter(hw, true);
1649                 else
1650                         ret = hns3vf_en_vlan_filter(hw, false);
1651                 rte_spinlock_unlock(&hw->lock);
1652                 if (ret)
1653                         return ret;
1654         }
1655
1656         /* Vlan stripping setting */
1657         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1658                 rte_spinlock_lock(&hw->lock);
1659                 /* Enable or disable VLAN stripping */
1660                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1661                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1662                 else
1663                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1664                 rte_spinlock_unlock(&hw->lock);
1665         }
1666
1667         return ret;
1668 }
1669
1670 static int
1671 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1672 {
1673         struct rte_vlan_filter_conf *vfc;
1674         struct hns3_hw *hw = &hns->hw;
1675         uint16_t vlan_id;
1676         uint64_t vbit;
1677         uint64_t ids;
1678         int ret = 0;
1679         uint32_t i;
1680
1681         vfc = &hw->data->vlan_filter_conf;
1682         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1683                 if (vfc->ids[i] == 0)
1684                         continue;
1685                 ids = vfc->ids[i];
1686                 while (ids) {
1687                         /*
1688                          * 64 means the num bits of ids, one bit corresponds to
1689                          * one vlan id
1690                          */
1691                         vlan_id = 64 * i;
1692                         /* count trailing zeroes */
1693                         vbit = ~ids & (ids - 1);
1694                         /* clear least significant bit set */
1695                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1696                         for (; vbit;) {
1697                                 vbit >>= 1;
1698                                 vlan_id++;
1699                         }
1700                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1701                         if (ret) {
1702                                 hns3_err(hw,
1703                                          "VF handle vlan table failed, ret =%d, on = %d",
1704                                          ret, on);
1705                                 return ret;
1706                         }
1707                 }
1708         }
1709
1710         return ret;
1711 }
1712
1713 static int
1714 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1715 {
1716         return hns3vf_handle_all_vlan_table(hns, 0);
1717 }
1718
1719 static int
1720 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1721 {
1722         struct hns3_hw *hw = &hns->hw;
1723         struct rte_eth_conf *dev_conf;
1724         bool en;
1725         int ret;
1726
1727         dev_conf = &hw->data->dev_conf;
1728         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1729                                                                    : false;
1730         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1731         if (ret)
1732                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1733                          ret);
1734         return ret;
1735 }
1736
1737 static int
1738 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1739 {
1740         struct hns3_adapter *hns = dev->data->dev_private;
1741         struct rte_eth_dev_data *data = dev->data;
1742         struct hns3_hw *hw = &hns->hw;
1743         int ret;
1744
1745         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1746             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1747             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1748                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1749                               "or hw_vlan_insert_pvid is not support!");
1750         }
1751
1752         /* Apply vlan offload setting */
1753         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK |
1754                                         ETH_VLAN_FILTER_MASK);
1755         if (ret)
1756                 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1757
1758         return ret;
1759 }
1760
1761 static int
1762 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1763 {
1764         uint8_t msg_data;
1765
1766         msg_data = alive ? 1 : 0;
1767         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1768                                  sizeof(msg_data), false, NULL, 0);
1769 }
1770
1771 static void
1772 hns3vf_keep_alive_handler(void *param)
1773 {
1774         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1775         struct hns3_adapter *hns = eth_dev->data->dev_private;
1776         struct hns3_hw *hw = &hns->hw;
1777         int ret;
1778
1779         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1780                                 false, NULL, 0);
1781         if (ret)
1782                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1783                          ret);
1784
1785         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1786                           eth_dev);
1787 }
1788
1789 static void
1790 hns3vf_service_handler(void *param)
1791 {
1792         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1793         struct hns3_adapter *hns = eth_dev->data->dev_private;
1794         struct hns3_hw *hw = &hns->hw;
1795
1796         /*
1797          * The query link status and reset processing are executed in the
1798          * interrupt thread. When the IMP reset occurs, IMP will not respond,
1799          * and the query operation will timeout after 30ms. In the case of
1800          * multiple PF/VFs, each query failure timeout causes the IMP reset
1801          * interrupt to fail to respond within 100ms.
1802          * Before querying the link status, check whether there is a reset
1803          * pending, and if so, abandon the query.
1804          */
1805         if (!hns3vf_is_reset_pending(hns))
1806                 hns3vf_request_link_info(hw);
1807         else
1808                 hns3_warn(hw, "Cancel the query when reset is pending");
1809
1810         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1811                           eth_dev);
1812 }
1813
1814 static void
1815 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1816 {
1817 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT      3
1818
1819         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1820
1821         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1822                 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1823
1824         __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1825
1826         hns3vf_service_handler(dev);
1827 }
1828
1829 static void
1830 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1831 {
1832         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1833
1834         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1835
1836         __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1837 }
1838
1839 static int
1840 hns3_query_vf_resource(struct hns3_hw *hw)
1841 {
1842         struct hns3_vf_res_cmd *req;
1843         struct hns3_cmd_desc desc;
1844         uint16_t num_msi;
1845         int ret;
1846
1847         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1848         ret = hns3_cmd_send(hw, &desc, 1);
1849         if (ret) {
1850                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1851                 return ret;
1852         }
1853
1854         req = (struct hns3_vf_res_cmd *)desc.data;
1855         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1856                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1857         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1858                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1859                          num_msi, HNS3_MIN_VECTOR_NUM);
1860                 return -EINVAL;
1861         }
1862
1863         hw->num_msi = num_msi;
1864
1865         return 0;
1866 }
1867
1868 static int
1869 hns3vf_init_hardware(struct hns3_adapter *hns)
1870 {
1871         struct hns3_hw *hw = &hns->hw;
1872         uint16_t mtu = hw->data->mtu;
1873         int ret;
1874
1875         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1876         if (ret)
1877                 return ret;
1878
1879         ret = hns3vf_config_mtu(hw, mtu);
1880         if (ret)
1881                 goto err_init_hardware;
1882
1883         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1884         if (ret) {
1885                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1886                 goto err_init_hardware;
1887         }
1888
1889         ret = hns3_config_gro(hw, false);
1890         if (ret) {
1891                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1892                 goto err_init_hardware;
1893         }
1894
1895         /*
1896          * In the initialization clearing the all hardware mapping relationship
1897          * configurations between queues and interrupt vectors is needed, so
1898          * some error caused by the residual configurations, such as the
1899          * unexpected interrupt, can be avoid.
1900          */
1901         ret = hns3vf_init_ring_with_vector(hw);
1902         if (ret) {
1903                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1904                 goto err_init_hardware;
1905         }
1906
1907         return 0;
1908
1909 err_init_hardware:
1910         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1911         return ret;
1912 }
1913
1914 static int
1915 hns3vf_clear_vport_list(struct hns3_hw *hw)
1916 {
1917         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1918                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1919                                  NULL, 0);
1920 }
1921
1922 static int
1923 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1924 {
1925         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1926         struct hns3_adapter *hns = eth_dev->data->dev_private;
1927         struct hns3_hw *hw = &hns->hw;
1928         int ret;
1929
1930         PMD_INIT_FUNC_TRACE();
1931
1932         /* Get hardware io base address from pcie BAR2 IO space */
1933         hw->io_base = pci_dev->mem_resource[2].addr;
1934
1935         /* Firmware command queue initialize */
1936         ret = hns3_cmd_init_queue(hw);
1937         if (ret) {
1938                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1939                 goto err_cmd_init_queue;
1940         }
1941
1942         /* Firmware command initialize */
1943         ret = hns3_cmd_init(hw);
1944         if (ret) {
1945                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1946                 goto err_cmd_init;
1947         }
1948
1949         hns3_tx_push_init(eth_dev);
1950
1951         /* Get VF resource */
1952         ret = hns3_query_vf_resource(hw);
1953         if (ret)
1954                 goto err_cmd_init;
1955
1956         rte_spinlock_init(&hw->mbx_resp.lock);
1957
1958         hns3vf_clear_event_cause(hw, 0);
1959
1960         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1961                                          hns3vf_interrupt_handler, eth_dev);
1962         if (ret) {
1963                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1964                 goto err_intr_callback_register;
1965         }
1966
1967         /* Enable interrupt */
1968         rte_intr_enable(&pci_dev->intr_handle);
1969         hns3vf_enable_irq0(hw);
1970
1971         /* Get configuration from PF */
1972         ret = hns3vf_get_configuration(hw);
1973         if (ret) {
1974                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1975                 goto err_get_config;
1976         }
1977
1978         ret = hns3_tqp_stats_init(hw);
1979         if (ret)
1980                 goto err_get_config;
1981
1982         /* Hardware statistics of imissed registers cleared. */
1983         ret = hns3_update_imissed_stats(hw, true);
1984         if (ret) {
1985                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1986                 goto err_set_tc_queue;
1987         }
1988
1989         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1990         if (ret) {
1991                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1992                 goto err_set_tc_queue;
1993         }
1994
1995         ret = hns3vf_clear_vport_list(hw);
1996         if (ret) {
1997                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1998                 goto err_set_tc_queue;
1999         }
2000
2001         ret = hns3vf_init_hardware(hns);
2002         if (ret)
2003                 goto err_set_tc_queue;
2004
2005         hns3_rss_set_default_args(hw);
2006
2007         ret = hns3vf_set_alive(hw, true);
2008         if (ret) {
2009                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
2010                 goto err_set_tc_queue;
2011         }
2012
2013         return 0;
2014
2015 err_set_tc_queue:
2016         hns3_tqp_stats_uninit(hw);
2017
2018 err_get_config:
2019         hns3vf_disable_irq0(hw);
2020         rte_intr_disable(&pci_dev->intr_handle);
2021         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
2022                              eth_dev);
2023 err_intr_callback_register:
2024 err_cmd_init:
2025         hns3_cmd_uninit(hw);
2026         hns3_cmd_destroy_queue(hw);
2027 err_cmd_init_queue:
2028         hw->io_base = NULL;
2029
2030         return ret;
2031 }
2032
2033 static void
2034 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
2035 {
2036         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2037         struct hns3_adapter *hns = eth_dev->data->dev_private;
2038         struct hns3_hw *hw = &hns->hw;
2039
2040         PMD_INIT_FUNC_TRACE();
2041
2042         hns3_rss_uninit(hns);
2043         (void)hns3_config_gro(hw, false);
2044         (void)hns3vf_set_alive(hw, false);
2045         (void)hns3vf_set_promisc_mode(hw, false, false, false);
2046         hns3_flow_uninit(eth_dev);
2047         hns3_tqp_stats_uninit(hw);
2048         hns3vf_disable_irq0(hw);
2049         rte_intr_disable(&pci_dev->intr_handle);
2050         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
2051                              eth_dev);
2052         hns3_cmd_uninit(hw);
2053         hns3_cmd_destroy_queue(hw);
2054         hw->io_base = NULL;
2055 }
2056
2057 static int
2058 hns3vf_do_stop(struct hns3_adapter *hns)
2059 {
2060         struct hns3_hw *hw = &hns->hw;
2061         int ret;
2062
2063         hw->mac.link_status = ETH_LINK_DOWN;
2064
2065         /*
2066          * The "hns3vf_do_stop" function will also be called by .stop_service to
2067          * prepare reset. At the time of global or IMP reset, the command cannot
2068          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
2069          * accessed during the reset process. So the mbuf can not be released
2070          * during reset and is required to be released after the reset is
2071          * completed.
2072          */
2073         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
2074                 hns3_dev_release_mbufs(hns);
2075
2076         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
2077                 hns3vf_configure_mac_addr(hns, true);
2078                 ret = hns3_reset_all_tqps(hns);
2079                 if (ret) {
2080                         hns3_err(hw, "failed to reset all queues ret = %d",
2081                                  ret);
2082                         return ret;
2083                 }
2084         }
2085         return 0;
2086 }
2087
2088 static void
2089 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
2090 {
2091         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2092         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2093         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2094         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2095         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2096         uint16_t q_id;
2097
2098         if (dev->data->dev_conf.intr_conf.rxq == 0)
2099                 return;
2100
2101         /* unmap the ring with vector */
2102         if (rte_intr_allow_others(intr_handle)) {
2103                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2104                 base = RTE_INTR_VEC_RXTX_OFFSET;
2105         }
2106         if (rte_intr_dp_is_en(intr_handle)) {
2107                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2108                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
2109                                                            HNS3_RING_TYPE_RX,
2110                                                            q_id);
2111                         if (vec < base + intr_handle->nb_efd - 1)
2112                                 vec++;
2113                 }
2114         }
2115         /* Clean datapath event and queue/vec mapping */
2116         rte_intr_efd_disable(intr_handle);
2117         if (intr_handle->intr_vec) {
2118                 rte_free(intr_handle->intr_vec);
2119                 intr_handle->intr_vec = NULL;
2120         }
2121 }
2122
2123 static int
2124 hns3vf_dev_stop(struct rte_eth_dev *dev)
2125 {
2126         struct hns3_adapter *hns = dev->data->dev_private;
2127         struct hns3_hw *hw = &hns->hw;
2128
2129         PMD_INIT_FUNC_TRACE();
2130         dev->data->dev_started = 0;
2131
2132         hw->adapter_state = HNS3_NIC_STOPPING;
2133         hns3_set_rxtx_function(dev);
2134         rte_wmb();
2135         /* Disable datapath on secondary process. */
2136         hns3_mp_req_stop_rxtx(dev);
2137         /* Prevent crashes when queues are still in use. */
2138         rte_delay_ms(hw->cfg_max_queues);
2139
2140         rte_spinlock_lock(&hw->lock);
2141         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
2142                 hns3_stop_tqps(hw);
2143                 hns3vf_do_stop(hns);
2144                 hns3vf_unmap_rx_interrupt(dev);
2145                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2146         }
2147         hns3_rx_scattered_reset(dev);
2148         hns3vf_stop_poll_job(dev);
2149         hns3_stop_report_lse(dev);
2150         rte_spinlock_unlock(&hw->lock);
2151
2152         return 0;
2153 }
2154
2155 static int
2156 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
2157 {
2158         struct hns3_adapter *hns = eth_dev->data->dev_private;
2159         struct hns3_hw *hw = &hns->hw;
2160         int ret = 0;
2161
2162         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2163                 return 0;
2164
2165         if (hw->adapter_state == HNS3_NIC_STARTED)
2166                 ret = hns3vf_dev_stop(eth_dev);
2167
2168         hw->adapter_state = HNS3_NIC_CLOSING;
2169         hns3_reset_abort(hns);
2170         hw->adapter_state = HNS3_NIC_CLOSED;
2171         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
2172         hns3vf_configure_all_mc_mac_addr(hns, true);
2173         hns3vf_remove_all_vlan_table(hns);
2174         hns3vf_uninit_vf(eth_dev);
2175         hns3_free_all_queues(eth_dev);
2176         rte_free(hw->reset.wait_data);
2177         hns3_mp_uninit_primary();
2178         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
2179
2180         return ret;
2181 }
2182
2183 static int
2184 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2185                       size_t fw_size)
2186 {
2187         struct hns3_adapter *hns = eth_dev->data->dev_private;
2188         struct hns3_hw *hw = &hns->hw;
2189         uint32_t version = hw->fw_version;
2190         int ret;
2191
2192         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2193                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2194                                       HNS3_FW_VERSION_BYTE3_S),
2195                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2196                                       HNS3_FW_VERSION_BYTE2_S),
2197                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2198                                       HNS3_FW_VERSION_BYTE1_S),
2199                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2200                                       HNS3_FW_VERSION_BYTE0_S));
2201         if (ret < 0)
2202                 return -EINVAL;
2203
2204         ret += 1; /* add the size of '\0' */
2205         if (fw_size < (size_t)ret)
2206                 return ret;
2207         else
2208                 return 0;
2209 }
2210
2211 static int
2212 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2213                        __rte_unused int wait_to_complete)
2214 {
2215         struct hns3_adapter *hns = eth_dev->data->dev_private;
2216         struct hns3_hw *hw = &hns->hw;
2217         struct hns3_mac *mac = &hw->mac;
2218         struct rte_eth_link new_link;
2219
2220         memset(&new_link, 0, sizeof(new_link));
2221         switch (mac->link_speed) {
2222         case ETH_SPEED_NUM_10M:
2223         case ETH_SPEED_NUM_100M:
2224         case ETH_SPEED_NUM_1G:
2225         case ETH_SPEED_NUM_10G:
2226         case ETH_SPEED_NUM_25G:
2227         case ETH_SPEED_NUM_40G:
2228         case ETH_SPEED_NUM_50G:
2229         case ETH_SPEED_NUM_100G:
2230         case ETH_SPEED_NUM_200G:
2231                 if (mac->link_status)
2232                         new_link.link_speed = mac->link_speed;
2233                 break;
2234         default:
2235                 if (mac->link_status)
2236                         new_link.link_speed = ETH_SPEED_NUM_UNKNOWN;
2237                 break;
2238         }
2239
2240         if (!mac->link_status)
2241                 new_link.link_speed = ETH_SPEED_NUM_NONE;
2242
2243         new_link.link_duplex = mac->link_duplex;
2244         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2245         new_link.link_autoneg =
2246             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2247
2248         return rte_eth_linkstatus_set(eth_dev, &new_link);
2249 }
2250
2251 static int
2252 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2253 {
2254         struct hns3_hw *hw = &hns->hw;
2255         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2256         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2257         int ret;
2258
2259         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2260         if (ret)
2261                 return ret;
2262
2263         hns3_enable_rxd_adv_layout(hw);
2264
2265         ret = hns3_init_queues(hns, reset_queue);
2266         if (ret)
2267                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2268
2269         return ret;
2270 }
2271
2272 static int
2273 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2274 {
2275         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2276         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2278         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2279         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2280         uint32_t intr_vector;
2281         uint16_t q_id;
2282         int ret;
2283
2284         /*
2285          * hns3 needs a separate interrupt to be used as event interrupt which
2286          * could not be shared with task queue pair, so KERNEL drivers need
2287          * support multiple interrupt vectors.
2288          */
2289         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2290             !rte_intr_cap_multiple(intr_handle))
2291                 return 0;
2292
2293         rte_intr_disable(intr_handle);
2294         intr_vector = hw->used_rx_queues;
2295         /* It creates event fd for each intr vector when MSIX is used */
2296         if (rte_intr_efd_enable(intr_handle, intr_vector))
2297                 return -EINVAL;
2298
2299         if (intr_handle->intr_vec == NULL) {
2300                 intr_handle->intr_vec =
2301                         rte_zmalloc("intr_vec",
2302                                     hw->used_rx_queues * sizeof(int), 0);
2303                 if (intr_handle->intr_vec == NULL) {
2304                         hns3_err(hw, "Failed to allocate %u rx_queues"
2305                                      " intr_vec", hw->used_rx_queues);
2306                         ret = -ENOMEM;
2307                         goto vf_alloc_intr_vec_error;
2308                 }
2309         }
2310
2311         if (rte_intr_allow_others(intr_handle)) {
2312                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2313                 base = RTE_INTR_VEC_RXTX_OFFSET;
2314         }
2315
2316         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2317                 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2318                                                    HNS3_RING_TYPE_RX, q_id);
2319                 if (ret)
2320                         goto vf_bind_vector_error;
2321                 intr_handle->intr_vec[q_id] = vec;
2322                 /*
2323                  * If there are not enough efds (e.g. not enough interrupt),
2324                  * remaining queues will be bond to the last interrupt.
2325                  */
2326                 if (vec < base + intr_handle->nb_efd - 1)
2327                         vec++;
2328         }
2329         rte_intr_enable(intr_handle);
2330         return 0;
2331
2332 vf_bind_vector_error:
2333         rte_free(intr_handle->intr_vec);
2334         intr_handle->intr_vec = NULL;
2335 vf_alloc_intr_vec_error:
2336         rte_intr_efd_disable(intr_handle);
2337         return ret;
2338 }
2339
2340 static int
2341 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2342 {
2343         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2344         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2345         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2346         uint16_t q_id;
2347         int ret;
2348
2349         if (dev->data->dev_conf.intr_conf.rxq == 0)
2350                 return 0;
2351
2352         if (rte_intr_dp_is_en(intr_handle)) {
2353                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2354                         ret = hns3vf_bind_ring_with_vector(hw,
2355                                         intr_handle->intr_vec[q_id], true,
2356                                         HNS3_RING_TYPE_RX, q_id);
2357                         if (ret)
2358                                 return ret;
2359                 }
2360         }
2361
2362         return 0;
2363 }
2364
2365 static void
2366 hns3vf_restore_filter(struct rte_eth_dev *dev)
2367 {
2368         hns3_restore_rss_filter(dev);
2369 }
2370
2371 static int
2372 hns3vf_dev_start(struct rte_eth_dev *dev)
2373 {
2374         struct hns3_adapter *hns = dev->data->dev_private;
2375         struct hns3_hw *hw = &hns->hw;
2376         int ret;
2377
2378         PMD_INIT_FUNC_TRACE();
2379         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2380                 return -EBUSY;
2381
2382         rte_spinlock_lock(&hw->lock);
2383         hw->adapter_state = HNS3_NIC_STARTING;
2384         ret = hns3vf_do_start(hns, true);
2385         if (ret) {
2386                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2387                 rte_spinlock_unlock(&hw->lock);
2388                 return ret;
2389         }
2390         ret = hns3vf_map_rx_interrupt(dev);
2391         if (ret)
2392                 goto map_rx_inter_err;
2393
2394         /*
2395          * There are three register used to control the status of a TQP
2396          * (contains a pair of Tx queue and Rx queue) in the new version network
2397          * engine. One is used to control the enabling of Tx queue, the other is
2398          * used to control the enabling of Rx queue, and the last is the master
2399          * switch used to control the enabling of the tqp. The Tx register and
2400          * TQP register must be enabled at the same time to enable a Tx queue.
2401          * The same applies to the Rx queue. For the older network enginem, this
2402          * function only refresh the enabled flag, and it is used to update the
2403          * status of queue in the dpdk framework.
2404          */
2405         ret = hns3_start_all_txqs(dev);
2406         if (ret)
2407                 goto map_rx_inter_err;
2408
2409         ret = hns3_start_all_rxqs(dev);
2410         if (ret)
2411                 goto start_all_rxqs_fail;
2412
2413         hw->adapter_state = HNS3_NIC_STARTED;
2414         rte_spinlock_unlock(&hw->lock);
2415
2416         hns3_rx_scattered_calc(dev);
2417         hns3_set_rxtx_function(dev);
2418         hns3_mp_req_start_rxtx(dev);
2419
2420         hns3vf_restore_filter(dev);
2421
2422         /* Enable interrupt of all rx queues before enabling queues */
2423         hns3_dev_all_rx_queue_intr_enable(hw, true);
2424         hns3_start_tqps(hw);
2425
2426         if (dev->data->dev_conf.intr_conf.lsc != 0)
2427                 hns3vf_dev_link_update(dev, 0);
2428         hns3vf_start_poll_job(dev);
2429
2430         return ret;
2431
2432 start_all_rxqs_fail:
2433         hns3_stop_all_txqs(dev);
2434 map_rx_inter_err:
2435         (void)hns3vf_do_stop(hns);
2436         hw->adapter_state = HNS3_NIC_CONFIGURED;
2437         rte_spinlock_unlock(&hw->lock);
2438
2439         return ret;
2440 }
2441
2442 static bool
2443 is_vf_reset_done(struct hns3_hw *hw)
2444 {
2445 #define HNS3_FUN_RST_ING_BITS \
2446         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2447          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2448          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2449          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2450
2451         uint32_t val;
2452
2453         if (hw->reset.level == HNS3_VF_RESET) {
2454                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2455                 if (val & HNS3_VF_RST_ING_BIT)
2456                         return false;
2457         } else {
2458                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2459                 if (val & HNS3_FUN_RST_ING_BITS)
2460                         return false;
2461         }
2462         return true;
2463 }
2464
2465 bool
2466 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2467 {
2468         struct hns3_hw *hw = &hns->hw;
2469         enum hns3_reset_level reset;
2470
2471         /*
2472          * According to the protocol of PCIe, FLR to a PF device resets the PF
2473          * state as well as the SR-IOV extended capability including VF Enable
2474          * which means that VFs no longer exist.
2475          *
2476          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2477          * is in FLR stage, the register state of VF device is not reliable,
2478          * so register states detection can not be carried out. In this case,
2479          * we just ignore the register states and return false to indicate that
2480          * there are no other reset states that need to be processed by driver.
2481          */
2482         if (hw->reset.level == HNS3_VF_FULL_RESET)
2483                 return false;
2484
2485         /* Check the registers to confirm whether there is reset pending */
2486         hns3vf_check_event_cause(hns, NULL);
2487         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2488         if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2489             hw->reset.level < reset) {
2490                 hns3_warn(hw, "High level reset %d is pending", reset);
2491                 return true;
2492         }
2493         return false;
2494 }
2495
2496 static int
2497 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2498 {
2499         struct hns3_hw *hw = &hns->hw;
2500         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2501         struct timeval tv;
2502
2503         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2504                 /*
2505                  * After vf reset is ready, the PF may not have completed
2506                  * the reset processing. The vf sending mbox to PF may fail
2507                  * during the pf reset, so it is better to add extra delay.
2508                  */
2509                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2510                     hw->reset.level == HNS3_FLR_RESET)
2511                         return 0;
2512                 /* Reset retry process, no need to add extra delay. */
2513                 if (hw->reset.attempts)
2514                         return 0;
2515                 if (wait_data->check_completion == NULL)
2516                         return 0;
2517
2518                 wait_data->check_completion = NULL;
2519                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2520                 wait_data->count = 1;
2521                 wait_data->result = HNS3_WAIT_REQUEST;
2522                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2523                                   wait_data);
2524                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2525                 return -EAGAIN;
2526         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2527                 hns3_clock_gettime(&tv);
2528                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2529                           tv.tv_sec, tv.tv_usec);
2530                 return -ETIME;
2531         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2532                 return -EAGAIN;
2533
2534         wait_data->hns = hns;
2535         wait_data->check_completion = is_vf_reset_done;
2536         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2537                                 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2538         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2539         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2540         wait_data->result = HNS3_WAIT_REQUEST;
2541         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2542         return -EAGAIN;
2543 }
2544
2545 static int
2546 hns3vf_prepare_reset(struct hns3_adapter *hns)
2547 {
2548         struct hns3_hw *hw = &hns->hw;
2549         int ret;
2550
2551         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2552                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2553                                         0, true, NULL, 0);
2554                 if (ret)
2555                         return ret;
2556         }
2557         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2558
2559         return 0;
2560 }
2561
2562 static int
2563 hns3vf_stop_service(struct hns3_adapter *hns)
2564 {
2565         struct hns3_hw *hw = &hns->hw;
2566         struct rte_eth_dev *eth_dev;
2567
2568         eth_dev = &rte_eth_devices[hw->data->port_id];
2569         if (hw->adapter_state == HNS3_NIC_STARTED) {
2570                 /*
2571                  * Make sure call update link status before hns3vf_stop_poll_job
2572                  * because update link status depend on polling job exist.
2573                  */
2574                 hns3vf_update_link_status(hw, ETH_LINK_DOWN, hw->mac.link_speed,
2575                                           hw->mac.link_duplex);
2576                 hns3vf_stop_poll_job(eth_dev);
2577         }
2578         hw->mac.link_status = ETH_LINK_DOWN;
2579
2580         hns3_set_rxtx_function(eth_dev);
2581         rte_wmb();
2582         /* Disable datapath on secondary process. */
2583         hns3_mp_req_stop_rxtx(eth_dev);
2584         rte_delay_ms(hw->cfg_max_queues);
2585
2586         rte_spinlock_lock(&hw->lock);
2587         if (hw->adapter_state == HNS3_NIC_STARTED ||
2588             hw->adapter_state == HNS3_NIC_STOPPING) {
2589                 hns3_enable_all_queues(hw, false);
2590                 hns3vf_do_stop(hns);
2591                 hw->reset.mbuf_deferred_free = true;
2592         } else
2593                 hw->reset.mbuf_deferred_free = false;
2594
2595         /*
2596          * It is cumbersome for hardware to pick-and-choose entries for deletion
2597          * from table space. Hence, for function reset software intervention is
2598          * required to delete the entries.
2599          */
2600         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2601                 hns3vf_configure_all_mc_mac_addr(hns, true);
2602         rte_spinlock_unlock(&hw->lock);
2603
2604         return 0;
2605 }
2606
2607 static int
2608 hns3vf_start_service(struct hns3_adapter *hns)
2609 {
2610         struct hns3_hw *hw = &hns->hw;
2611         struct rte_eth_dev *eth_dev;
2612
2613         eth_dev = &rte_eth_devices[hw->data->port_id];
2614         hns3_set_rxtx_function(eth_dev);
2615         hns3_mp_req_start_rxtx(eth_dev);
2616         if (hw->adapter_state == HNS3_NIC_STARTED) {
2617                 hns3vf_start_poll_job(eth_dev);
2618
2619                 /* Enable interrupt of all rx queues before enabling queues */
2620                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2621                 /*
2622                  * Enable state of each rxq and txq will be recovered after
2623                  * reset, so we need to restore them before enable all tqps;
2624                  */
2625                 hns3_restore_tqp_enable_state(hw);
2626                 /*
2627                  * When finished the initialization, enable queues to receive
2628                  * and transmit packets.
2629                  */
2630                 hns3_enable_all_queues(hw, true);
2631         }
2632
2633         return 0;
2634 }
2635
2636 static int
2637 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2638 {
2639         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2640         struct rte_ether_addr *hw_mac;
2641         int ret;
2642
2643         /*
2644          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2645          * on the host by "ip link set ..." command. If the hns3 PF kernel
2646          * ethdev driver sets the MAC address for VF device after the
2647          * initialization of the related VF device, the PF driver will notify
2648          * VF driver to reset VF device to make the new MAC address effective
2649          * immediately. The hns3 VF PMD driver should check whether the MAC
2650          * address has been changed by the PF kernel ethdev driver, if changed
2651          * VF driver should configure hardware using the new MAC address in the
2652          * recovering hardware configuration stage of the reset process.
2653          */
2654         ret = hns3vf_get_host_mac_addr(hw);
2655         if (ret)
2656                 return ret;
2657
2658         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2659         ret = rte_is_zero_ether_addr(hw_mac);
2660         if (ret) {
2661                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2662         } else {
2663                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2664                 if (!ret) {
2665                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2666                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2667                                               &hw->data->mac_addrs[0]);
2668                         hns3_warn(hw, "Default MAC address has been changed to:"
2669                                   " %s by the host PF kernel ethdev driver",
2670                                   mac_str);
2671                 }
2672         }
2673
2674         return 0;
2675 }
2676
2677 static int
2678 hns3vf_restore_conf(struct hns3_adapter *hns)
2679 {
2680         struct hns3_hw *hw = &hns->hw;
2681         int ret;
2682
2683         ret = hns3vf_check_default_mac_change(hw);
2684         if (ret)
2685                 return ret;
2686
2687         ret = hns3vf_configure_mac_addr(hns, false);
2688         if (ret)
2689                 return ret;
2690
2691         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2692         if (ret)
2693                 goto err_mc_mac;
2694
2695         ret = hns3vf_restore_promisc(hns);
2696         if (ret)
2697                 goto err_vlan_table;
2698
2699         ret = hns3vf_restore_vlan_conf(hns);
2700         if (ret)
2701                 goto err_vlan_table;
2702
2703         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2704         if (ret)
2705                 goto err_vlan_table;
2706
2707         ret = hns3vf_restore_rx_interrupt(hw);
2708         if (ret)
2709                 goto err_vlan_table;
2710
2711         ret = hns3_restore_gro_conf(hw);
2712         if (ret)
2713                 goto err_vlan_table;
2714
2715         if (hw->adapter_state == HNS3_NIC_STARTED) {
2716                 ret = hns3vf_do_start(hns, false);
2717                 if (ret)
2718                         goto err_vlan_table;
2719                 hns3_info(hw, "hns3vf dev restart successful!");
2720         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2721                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2722
2723         ret = hns3vf_set_alive(hw, true);
2724         if (ret) {
2725                 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2726                 goto err_vlan_table;
2727         }
2728
2729         return 0;
2730
2731 err_vlan_table:
2732         hns3vf_configure_all_mc_mac_addr(hns, true);
2733 err_mc_mac:
2734         hns3vf_configure_mac_addr(hns, true);
2735         return ret;
2736 }
2737
2738 static enum hns3_reset_level
2739 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2740 {
2741         enum hns3_reset_level reset_level;
2742
2743         /* return the highest priority reset level amongst all */
2744         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2745                 reset_level = HNS3_VF_RESET;
2746         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2747                 reset_level = HNS3_VF_FULL_RESET;
2748         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2749                 reset_level = HNS3_VF_PF_FUNC_RESET;
2750         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2751                 reset_level = HNS3_VF_FUNC_RESET;
2752         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2753                 reset_level = HNS3_FLR_RESET;
2754         else
2755                 reset_level = HNS3_NONE_RESET;
2756
2757         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2758                 return HNS3_NONE_RESET;
2759
2760         return reset_level;
2761 }
2762
2763 static void
2764 hns3vf_reset_service(void *param)
2765 {
2766         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2767         struct hns3_hw *hw = &hns->hw;
2768         enum hns3_reset_level reset_level;
2769         struct timeval tv_delta;
2770         struct timeval tv_start;
2771         struct timeval tv;
2772         uint64_t msec;
2773
2774         /*
2775          * The interrupt is not triggered within the delay time.
2776          * The interrupt may have been lost. It is necessary to handle
2777          * the interrupt to recover from the error.
2778          */
2779         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2780                             SCHEDULE_DEFERRED) {
2781                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2782                                  __ATOMIC_RELAXED);
2783                 hns3_err(hw, "Handling interrupts in delayed tasks");
2784                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2785                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2786                 if (reset_level == HNS3_NONE_RESET) {
2787                         hns3_err(hw, "No reset level is set, try global reset");
2788                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2789                 }
2790         }
2791         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2792
2793         /*
2794          * Hardware reset has been notified, we now have to poll & check if
2795          * hardware has actually completed the reset sequence.
2796          */
2797         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2798         if (reset_level != HNS3_NONE_RESET) {
2799                 hns3_clock_gettime(&tv_start);
2800                 hns3_reset_process(hns, reset_level);
2801                 hns3_clock_gettime(&tv);
2802                 timersub(&tv, &tv_start, &tv_delta);
2803                 msec = hns3_clock_calctime_ms(&tv_delta);
2804                 if (msec > HNS3_RESET_PROCESS_MS)
2805                         hns3_err(hw, "%d handle long time delta %" PRIu64
2806                                  " ms time=%ld.%.6ld",
2807                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2808         }
2809 }
2810
2811 static int
2812 hns3vf_reinit_dev(struct hns3_adapter *hns)
2813 {
2814         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2815         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2816         struct hns3_hw *hw = &hns->hw;
2817         int ret;
2818
2819         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2820                 rte_intr_disable(&pci_dev->intr_handle);
2821                 ret = hns3vf_set_bus_master(pci_dev, true);
2822                 if (ret < 0) {
2823                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2824                         return ret;
2825                 }
2826         }
2827
2828         /* Firmware command initialize */
2829         ret = hns3_cmd_init(hw);
2830         if (ret) {
2831                 hns3_err(hw, "Failed to init cmd: %d", ret);
2832                 return ret;
2833         }
2834
2835         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2836                 /*
2837                  * UIO enables msix by writing the pcie configuration space
2838                  * vfio_pci enables msix in rte_intr_enable.
2839                  */
2840                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2841                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2842                         if (hns3vf_enable_msix(pci_dev, true))
2843                                 hns3_err(hw, "Failed to enable msix");
2844                 }
2845
2846                 rte_intr_enable(&pci_dev->intr_handle);
2847         }
2848
2849         ret = hns3_reset_all_tqps(hns);
2850         if (ret) {
2851                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2852                 return ret;
2853         }
2854
2855         ret = hns3vf_init_hardware(hns);
2856         if (ret) {
2857                 hns3_err(hw, "Failed to init hardware: %d", ret);
2858                 return ret;
2859         }
2860
2861         return 0;
2862 }
2863
2864 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2865         .dev_configure      = hns3vf_dev_configure,
2866         .dev_start          = hns3vf_dev_start,
2867         .dev_stop           = hns3vf_dev_stop,
2868         .dev_close          = hns3vf_dev_close,
2869         .mtu_set            = hns3vf_dev_mtu_set,
2870         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2871         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2872         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2873         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2874         .stats_get          = hns3_stats_get,
2875         .stats_reset        = hns3_stats_reset,
2876         .xstats_get         = hns3_dev_xstats_get,
2877         .xstats_get_names   = hns3_dev_xstats_get_names,
2878         .xstats_reset       = hns3_dev_xstats_reset,
2879         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2880         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2881         .dev_infos_get      = hns3vf_dev_infos_get,
2882         .fw_version_get     = hns3vf_fw_version_get,
2883         .rx_queue_setup     = hns3_rx_queue_setup,
2884         .tx_queue_setup     = hns3_tx_queue_setup,
2885         .rx_queue_release   = hns3_dev_rx_queue_release,
2886         .tx_queue_release   = hns3_dev_tx_queue_release,
2887         .rx_queue_start     = hns3_dev_rx_queue_start,
2888         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2889         .tx_queue_start     = hns3_dev_tx_queue_start,
2890         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2891         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2892         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2893         .rxq_info_get       = hns3_rxq_info_get,
2894         .txq_info_get       = hns3_txq_info_get,
2895         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2896         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2897         .mac_addr_add       = hns3vf_add_mac_addr,
2898         .mac_addr_remove    = hns3vf_remove_mac_addr,
2899         .mac_addr_set       = hns3vf_set_default_mac_addr,
2900         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2901         .link_update        = hns3vf_dev_link_update,
2902         .rss_hash_update    = hns3_dev_rss_hash_update,
2903         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2904         .reta_update        = hns3_dev_rss_reta_update,
2905         .reta_query         = hns3_dev_rss_reta_query,
2906         .flow_ops_get       = hns3_dev_flow_ops_get,
2907         .vlan_filter_set    = hns3vf_vlan_filter_set,
2908         .vlan_offload_set   = hns3vf_vlan_offload_set,
2909         .get_reg            = hns3_get_regs,
2910         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2911         .tx_done_cleanup    = hns3_tx_done_cleanup,
2912 };
2913
2914 static const struct hns3_reset_ops hns3vf_reset_ops = {
2915         .reset_service       = hns3vf_reset_service,
2916         .stop_service        = hns3vf_stop_service,
2917         .prepare_reset       = hns3vf_prepare_reset,
2918         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2919         .reinit_dev          = hns3vf_reinit_dev,
2920         .restore_conf        = hns3vf_restore_conf,
2921         .start_service       = hns3vf_start_service,
2922 };
2923
2924 static int
2925 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2926 {
2927         struct hns3_adapter *hns = eth_dev->data->dev_private;
2928         struct hns3_hw *hw = &hns->hw;
2929         int ret;
2930
2931         PMD_INIT_FUNC_TRACE();
2932
2933         hns3_flow_init(eth_dev);
2934
2935         hns3_set_rxtx_function(eth_dev);
2936         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2937         eth_dev->rx_queue_count = hns3_rx_queue_count;
2938         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2939                 ret = hns3_mp_init_secondary();
2940                 if (ret) {
2941                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2942                                           "process, ret = %d", ret);
2943                         goto err_mp_init_secondary;
2944                 }
2945                 hw->secondary_cnt++;
2946                 hns3_tx_push_init(eth_dev);
2947                 return 0;
2948         }
2949
2950         ret = hns3_mp_init_primary();
2951         if (ret) {
2952                 PMD_INIT_LOG(ERR,
2953                              "Failed to init for primary process, ret = %d",
2954                              ret);
2955                 goto err_mp_init_primary;
2956         }
2957
2958         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2959         hns->is_vf = true;
2960         hw->data = eth_dev->data;
2961         hns3_parse_devargs(eth_dev);
2962
2963         ret = hns3_reset_init(hw);
2964         if (ret)
2965                 goto err_init_reset;
2966         hw->reset.ops = &hns3vf_reset_ops;
2967
2968         ret = hns3vf_init_vf(eth_dev);
2969         if (ret) {
2970                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2971                 goto err_init_vf;
2972         }
2973
2974         /* Allocate memory for storing MAC addresses */
2975         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2976                                                sizeof(struct rte_ether_addr) *
2977                                                HNS3_VF_UC_MACADDR_NUM, 0);
2978         if (eth_dev->data->mac_addrs == NULL) {
2979                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2980                              "to store MAC addresses",
2981                              sizeof(struct rte_ether_addr) *
2982                              HNS3_VF_UC_MACADDR_NUM);
2983                 ret = -ENOMEM;
2984                 goto err_rte_zmalloc;
2985         }
2986
2987         /*
2988          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2989          * on the host by "ip link set ..." command. To avoid some incorrect
2990          * scenes, for example, hns3 VF PMD driver fails to receive and send
2991          * packets after user configure the MAC address by using the
2992          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2993          * address strategy as the hns3 kernel ethdev driver in the
2994          * initialization. If user configure a MAC address by the ip command
2995          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2996          * start with a random MAC address in the initialization.
2997          */
2998         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2999                 rte_eth_random_addr(hw->mac.mac_addr);
3000         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
3001                             &eth_dev->data->mac_addrs[0]);
3002
3003         hw->adapter_state = HNS3_NIC_INITIALIZED;
3004
3005         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
3006                             SCHEDULE_PENDING) {
3007                 hns3_err(hw, "Reschedule reset service after dev_init");
3008                 hns3_schedule_reset(hns);
3009         } else {
3010                 /* IMP will wait ready flag before reset */
3011                 hns3_notify_reset_ready(hw, false);
3012         }
3013         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
3014                           eth_dev);
3015         return 0;
3016
3017 err_rte_zmalloc:
3018         hns3vf_uninit_vf(eth_dev);
3019
3020 err_init_vf:
3021         rte_free(hw->reset.wait_data);
3022
3023 err_init_reset:
3024         hns3_mp_uninit_primary();
3025
3026 err_mp_init_primary:
3027 err_mp_init_secondary:
3028         eth_dev->dev_ops = NULL;
3029         eth_dev->rx_pkt_burst = NULL;
3030         eth_dev->rx_descriptor_status = NULL;
3031         eth_dev->tx_pkt_burst = NULL;
3032         eth_dev->tx_pkt_prepare = NULL;
3033         eth_dev->tx_descriptor_status = NULL;
3034
3035         return ret;
3036 }
3037
3038 static int
3039 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
3040 {
3041         struct hns3_adapter *hns = eth_dev->data->dev_private;
3042         struct hns3_hw *hw = &hns->hw;
3043
3044         PMD_INIT_FUNC_TRACE();
3045
3046         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3047                 return 0;
3048
3049         if (hw->adapter_state < HNS3_NIC_CLOSING)
3050                 hns3vf_dev_close(eth_dev);
3051
3052         hw->adapter_state = HNS3_NIC_REMOVED;
3053         return 0;
3054 }
3055
3056 static int
3057 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3058                      struct rte_pci_device *pci_dev)
3059 {
3060         return rte_eth_dev_pci_generic_probe(pci_dev,
3061                                              sizeof(struct hns3_adapter),
3062                                              hns3vf_dev_init);
3063 }
3064
3065 static int
3066 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
3067 {
3068         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
3069 }
3070
3071 static const struct rte_pci_id pci_id_hns3vf_map[] = {
3072         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
3073         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
3074         { .vendor_id = 0, }, /* sentinel */
3075 };
3076
3077 static struct rte_pci_driver rte_hns3vf_pmd = {
3078         .id_table = pci_id_hns3vf_map,
3079         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3080         .probe = eth_hns3vf_pci_probe,
3081         .remove = eth_hns3vf_pci_remove,
3082 };
3083
3084 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
3085 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
3086 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
3087 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
3088                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
3089                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
3090                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");