drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
  48                                    __rte_unused int wait_to_complete);
  49
  50 /* set PCI bus mastering */
  51 static int
  52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  53 {
  54         uint16_t reg;
  55         int ret;
  56
  57         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  58         if (ret < 0) {
  59                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  60                              PCI_COMMAND);
  61                 return ret;
  62         }
  63
  64         if (op)
  65                 /* set the master bit */
  66                 reg |= PCI_COMMAND_MASTER;
  67         else
  68                 reg &= ~(PCI_COMMAND_MASTER);
  69
  70         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  71 }
  72
  73 /**
  74  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  75  * @cap: the capability
  76  *
  77  * Return the address of the given capability within the PCI capability list.
  78  */
  79 static int
  80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  81 {
  82 #define MAX_PCIE_CAPABILITY 48
  83         uint16_t status;
  84         uint8_t pos;
  85         uint8_t id;
  86         int ttl;
  87         int ret;
  88
  89         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  90         if (ret < 0) {
  91                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  92                 return 0;
  93         }
  94
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 100                                   PCI_CAPABILITY_LIST);
 101         if (ret < 0) {
 102                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 103                              PCI_CAPABILITY_LIST);
 104                 return 0;
 105         }
 106
 107         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 108                 ret = rte_pci_read_config(device, &id, sizeof(id),
 109                                           (pos + PCI_CAP_LIST_ID));
 110                 if (ret < 0) {
 111                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 112                                      (pos + PCI_CAP_LIST_ID));
 113                         break;
 114                 }
 115
 116                 if (id == 0xFF)
 117                         break;
 118
 119                 if (id == cap)
 120                         return (int)pos;
 121
 122                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 123                                           (pos + PCI_CAP_LIST_NEXT));
 124                 if (ret < 0) {
 125                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 126                                      (pos + PCI_CAP_LIST_NEXT));
 127                         break;
 128                 }
 129         }
 130         return 0;
 131 }
 132
 133 static int
 134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 135 {
 136         uint16_t control;
 137         int pos;
 138         int ret;
 139
 140         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 141         if (pos) {
 142                 ret = rte_pci_read_config(device, &control, sizeof(control),
 143                                     (pos + PCI_MSIX_FLAGS));
 144                 if (ret < 0) {
 145                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 146                                      (pos + PCI_MSIX_FLAGS));
 147                         return -ENXIO;
 148                 }
 149
 150                 if (op)
 151                         control |= PCI_MSIX_FLAGS_ENABLE;
 152                 else
 153                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 154                 ret = rte_pci_write_config(device, &control, sizeof(control),
 155                                           (pos + PCI_MSIX_FLAGS));
 156                 if (ret < 0) {
 157                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 158                                     (pos + PCI_MSIX_FLAGS));
 159                         return -ENXIO;
 160                 }
 161
 162                 return 0;
 163         }
 164
 165         return -ENXIO;
 166 }
 167
 168 static int
 169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 170 {
 171         /* mac address was checked by upper level interface */
 172         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 173         int ret;
 174
 175         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 176                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 177                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 178         if (ret) {
 179                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 180                                       mac_addr);
 181                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 182                          mac_str, ret);
 183         }
 184         return ret;
 185 }
 186
 187 static int
 188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 189 {
 190         /* mac address was checked by upper level interface */
 191         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 192         int ret;
 193
 194         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 195                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 196                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 197                                 false, NULL, 0);
 198         if (ret) {
 199                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 200                                       mac_addr);
 201                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 202                          mac_str, ret);
 203         }
 204         return ret;
 205 }
 206
 207 static int
 208 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 209 {
 210         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 211         struct rte_ether_addr *addr;
 212         int ret;
 213         int i;
 214
 215         for (i = 0; i < hw->mc_addrs_num; i++) {
 216                 addr = &hw->mc_addrs[i];
 217                 /* Check if there are duplicate addresses */
 218                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 219                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 220                                               addr);
 221                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 222                                  "(%s) is added by the set_mc_mac_addr_list "
 223                                  "API", mac_str);
 224                         return -EINVAL;
 225                 }
 226         }
 227
 228         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 229         if (ret) {
 230                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 231                                       mac_addr);
 232                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 233                          mac_str, ret);
 234         }
 235         return ret;
 236 }
 237
 238 static int
 239 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 240                     __rte_unused uint32_t idx,
 241                     __rte_unused uint32_t pool)
 242 {
 243         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 244         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 245         int ret;
 246
 247         rte_spinlock_lock(&hw->lock);
 248
 249         /*
 250          * In hns3 network engine adding UC and MC mac address with different
 251          * commands with firmware. We need to determine whether the input
 252          * address is a UC or a MC address to call different commands.
 253          * By the way, it is recommended calling the API function named
 254          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 255          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 256          * may affect the specifications of UC mac addresses.
 257          */
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 260         else
 261                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 268                          ret);
 269         }
 270
 271         return ret;
 272 }
 273
 274 static void
 275 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 276 {
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         /* index will be checked by upper level rte interface */
 279         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         rte_spinlock_lock(&hw->lock);
 284
 285         if (rte_is_multicast_ether_addr(mac_addr))
 286                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 287         else
 288                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 289
 290         rte_spinlock_unlock(&hw->lock);
 291         if (ret) {
 292                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 293                                       mac_addr);
 294                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 295                          mac_str, ret);
 296         }
 297 }
 298
 299 static int
 300 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 301                             struct rte_ether_addr *mac_addr)
 302 {
 303 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 304         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 305         struct rte_ether_addr *old_addr;
 306         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 307         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 308         int ret;
 309
 310         /*
 311          * It has been guaranteed that input parameter named mac_addr is valid
 312          * address in the rte layer of DPDK framework.
 313          */
 314         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 315         rte_spinlock_lock(&hw->lock);
 316         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 317         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 318                RTE_ETHER_ADDR_LEN);
 319
 320         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 321                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 322                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 323         if (ret) {
 324                 /*
 325                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 326                  * driver. When user has configured a MAC address for VF device
 327                  * by "ip link set ..." command based on the PF device, the hns3
 328                  * PF kernel ethdev driver does not allow VF driver to request
 329                  * reconfiguring a different default MAC address, and return
 330                  * -EPREM to VF driver through mailbox.
 331                  */
 332                 if (ret == -EPERM) {
 333                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 334                                               old_addr);
 335                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 336                                   mac_str);
 337                 } else {
 338                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 339                                               mac_addr);
 340                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 341                                  mac_str, ret);
 342                 }
 343         }
 344
 345         rte_ether_addr_copy(mac_addr,
 346                             (struct rte_ether_addr *)hw->mac.mac_addr);
 347         rte_spinlock_unlock(&hw->lock);
 348
 349         return ret;
 350 }
 351
 352 static int
 353 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 354 {
 355         struct hns3_hw *hw = &hns->hw;
 356         struct rte_ether_addr *addr;
 357         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 358         int err = 0;
 359         int ret;
 360         int i;
 361
 362         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 363                 addr = &hw->data->mac_addrs[i];
 364                 if (rte_is_zero_ether_addr(addr))
 365                         continue;
 366                 if (rte_is_multicast_ether_addr(addr))
 367                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 368                               hns3vf_add_mc_mac_addr(hw, addr);
 369                 else
 370                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 371                               hns3vf_add_uc_mac_addr(hw, addr);
 372
 373                 if (ret) {
 374                         err = ret;
 375                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 376                                               addr);
 377                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 378                                  "ret = %d.", del ? "remove" : "restore",
 379                                  mac_str, i, ret);
 380                 }
 381         }
 382         return err;
 383 }
 384
 385 static int
 386 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 387                        struct rte_ether_addr *mac_addr)
 388 {
 389         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 390         int ret;
 391
 392         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 393                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 394                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 395                                 NULL, 0);
 396         if (ret) {
 397                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 398                                       mac_addr);
 399                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 400                          mac_str, ret);
 401         }
 402
 403         return ret;
 404 }
 405
 406 static int
 407 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 408                           struct rte_ether_addr *mac_addr)
 409 {
 410         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 411         int ret;
 412
 413         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 414                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 415                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 416                                 NULL, 0);
 417         if (ret) {
 418                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 419                                       mac_addr);
 420                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 421                          mac_str, ret);
 422         }
 423
 424         return ret;
 425 }
 426
 427 static int
 428 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 429                              struct rte_ether_addr *mc_addr_set,
 430                              uint32_t nb_mc_addr)
 431 {
 432         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 433         struct rte_ether_addr *addr;
 434         uint32_t i;
 435         uint32_t j;
 436
 437         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 438                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
 439                          "invalid. valid range: 0~%d",
 440                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 441                 return -EINVAL;
 442         }
 443
 444         /* Check if input mac addresses are valid */
 445         for (i = 0; i < nb_mc_addr; i++) {
 446                 addr = &mc_addr_set[i];
 447                 if (!rte_is_multicast_ether_addr(addr)) {
 448                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 449                                               addr);
 450                         hns3_err(hw,
 451                                  "failed to set mc mac addr, addr(%s) invalid.",
 452                                  mac_str);
 453                         return -EINVAL;
 454                 }
 455
 456                 /* Check if there are duplicate addresses */
 457                 for (j = i + 1; j < nb_mc_addr; j++) {
 458                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 459                                 hns3_ether_format_addr(mac_str,
 460                                                       RTE_ETHER_ADDR_FMT_SIZE,
 461                                                       addr);
 462                                 hns3_err(hw, "failed to set mc mac addr, "
 463                                          "addrs invalid. two same addrs(%s).",
 464                                          mac_str);
 465                                 return -EINVAL;
 466                         }
 467                 }
 468
 469                 /*
 470                  * Check if there are duplicate addresses between mac_addrs
 471                  * and mc_addr_set
 472                  */
 473                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 474                         if (rte_is_same_ether_addr(addr,
 475                                                    &hw->data->mac_addrs[j])) {
 476                                 hns3_ether_format_addr(mac_str,
 477                                                       RTE_ETHER_ADDR_FMT_SIZE,
 478                                                       addr);
 479                                 hns3_err(hw, "failed to set mc mac addr, "
 480                                          "addrs invalid. addrs(%s) has already "
 481                                          "configured in mac_addr add API",
 482                                          mac_str);
 483                                 return -EINVAL;
 484                         }
 485                 }
 486         }
 487
 488         return 0;
 489 }
 490
 491 static int
 492 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 493                             struct rte_ether_addr *mc_addr_set,
 494                             uint32_t nb_mc_addr)
 495 {
 496         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 497         struct rte_ether_addr *addr;
 498         int cur_addr_num;
 499         int set_addr_num;
 500         int num;
 501         int ret;
 502         int i;
 503
 504         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 505         if (ret)
 506                 return ret;
 507
 508         rte_spinlock_lock(&hw->lock);
 509         cur_addr_num = hw->mc_addrs_num;
 510         for (i = 0; i < cur_addr_num; i++) {
 511                 num = cur_addr_num - i - 1;
 512                 addr = &hw->mc_addrs[num];
 513                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 514                 if (ret) {
 515                         rte_spinlock_unlock(&hw->lock);
 516                         return ret;
 517                 }
 518
 519                 hw->mc_addrs_num--;
 520         }
 521
 522         set_addr_num = (int)nb_mc_addr;
 523         for (i = 0; i < set_addr_num; i++) {
 524                 addr = &mc_addr_set[i];
 525                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 526                 if (ret) {
 527                         rte_spinlock_unlock(&hw->lock);
 528                         return ret;
 529                 }
 530
 531                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 532                 hw->mc_addrs_num++;
 533         }
 534         rte_spinlock_unlock(&hw->lock);
 535
 536         return 0;
 537 }
 538
 539 static int
 540 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 541 {
 542         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 543         struct hns3_hw *hw = &hns->hw;
 544         struct rte_ether_addr *addr;
 545         int err = 0;
 546         int ret;
 547         int i;
 548
 549         for (i = 0; i < hw->mc_addrs_num; i++) {
 550                 addr = &hw->mc_addrs[i];
 551                 if (!rte_is_multicast_ether_addr(addr))
 552                         continue;
 553                 if (del)
 554                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 555                 else
 556                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 557                 if (ret) {
 558                         err = ret;
 559                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 560                                               addr);
 561                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 562                                  del ? "Remove" : "Restore", mac_str, ret);
 563                 }
 564         }
 565         return err;
 566 }
 567
 568 static int
 569 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 570                         bool en_uc_pmc, bool en_mc_pmc)
 571 {
 572         struct hns3_mbx_vf_to_pf_cmd *req;
 573         struct hns3_cmd_desc desc;
 574         int ret;
 575
 576         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 577
 578         /*
 579          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 580          * so there are some features for promiscuous/allmulticast mode in hns3
 581          * VF PMD driver as below:
 582          * 1. The promiscuous/allmulticast mode can be configured successfully
 583          *    only based on the trusted VF device. If based on the non trusted
 584          *    VF device, configuring promiscuous/allmulticast mode will fail.
 585          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 586          *    kernel ethdev driver on the host by the following command:
 587          *      "ip link set <eth num> vf <vf id> turst on"
 588          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 589          *    driver can receive the ingress and outgoing traffic. In the words,
 590          *    all the ingress packets, all the packets sent from the PF and
 591          *    other VFs on the same physical port.
 592          * 3. Note: Because of the hardware constraints, By default vlan filter
 593          *    is enabled and couldn't be turned off based on VF device, so vlan
 594          *    filter is still effective even in promiscuous mode. If upper
 595          *    applications don't call rte_eth_dev_vlan_filter API function to
 596          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 597          *    the packets with vlan tag in promiscuoue mode.
 598          */
 599         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 600         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 601         req->msg[1] = en_bc_pmc ? 1 : 0;
 602         req->msg[2] = en_uc_pmc ? 1 : 0;
 603         req->msg[3] = en_mc_pmc ? 1 : 0;
 604         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 605
 606         ret = hns3_cmd_send(hw, &desc, 1);
 607         if (ret)
 608                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 609
 610         return ret;
 611 }
 612
 613 static int
 614 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 615 {
 616         struct hns3_adapter *hns = dev->data->dev_private;
 617         struct hns3_hw *hw = &hns->hw;
 618         int ret;
 619
 620         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 621         if (ret)
 622                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 623                         ret);
 624         return ret;
 625 }
 626
 627 static int
 628 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 629 {
 630         bool allmulti = dev->data->all_multicast ? true : false;
 631         struct hns3_adapter *hns = dev->data->dev_private;
 632         struct hns3_hw *hw = &hns->hw;
 633         int ret;
 634
 635         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 636         if (ret)
 637                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 638                         ret);
 639         return ret;
 640 }
 641
 642 static int
 643 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 644 {
 645         struct hns3_adapter *hns = dev->data->dev_private;
 646         struct hns3_hw *hw = &hns->hw;
 647         int ret;
 648
 649         if (dev->data->promiscuous)
 650                 return 0;
 651
 652         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 653         if (ret)
 654                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 655                         ret);
 656         return ret;
 657 }
 658
 659 static int
 660 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 661 {
 662         struct hns3_adapter *hns = dev->data->dev_private;
 663         struct hns3_hw *hw = &hns->hw;
 664         int ret;
 665
 666         if (dev->data->promiscuous)
 667                 return 0;
 668
 669         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 670         if (ret)
 671                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 672                         ret);
 673         return ret;
 674 }
 675
 676 static int
 677 hns3vf_restore_promisc(struct hns3_adapter *hns)
 678 {
 679         struct hns3_hw *hw = &hns->hw;
 680         bool allmulti = hw->data->all_multicast ? true : false;
 681
 682         if (hw->data->promiscuous)
 683                 return hns3vf_set_promisc_mode(hw, true, true, true);
 684
 685         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 686 }
 687
 688 static int
 689 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 690                              bool mmap, enum hns3_ring_type queue_type,
 691                              uint16_t queue_id)
 692 {
 693         struct hns3_vf_bind_vector_msg bind_msg;
 694         const char *op_str;
 695         uint16_t code;
 696         int ret;
 697
 698         memset(&bind_msg, 0, sizeof(bind_msg));
 699         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 700                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 701         bind_msg.vector_id = vector_id;
 702
 703         if (queue_type == HNS3_RING_TYPE_RX)
 704                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 705         else
 706                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 707
 708         bind_msg.param[0].ring_type = queue_type;
 709         bind_msg.ring_num = 1;
 710         bind_msg.param[0].tqp_index = queue_id;
 711         op_str = mmap ? "Map" : "Unmap";
 712         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 713                                 sizeof(bind_msg), false, NULL, 0);
 714         if (ret)
 715                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 716                          op_str, queue_id, bind_msg.vector_id, ret);
 717
 718         return ret;
 719 }
 720
 721 static int
 722 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 723 {
 724         uint16_t vec;
 725         int ret;
 726         int i;
 727
 728         /*
 729          * In hns3 network engine, vector 0 is always the misc interrupt of this
 730          * function, vector 1~N can be used respectively for the queues of the
 731          * function. Tx and Rx queues with the same number share the interrupt
 732          * vector. In the initialization clearing the all hardware mapping
 733          * relationship configurations between queues and interrupt vectors is
 734          * needed, so some error caused by the residual configurations, such as
 735          * the unexpected Tx interrupt, can be avoid.
 736          */
 737         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 738         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 739                 vec = vec - 1; /* the last interrupt is reserved */
 740         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 741         for (i = 0; i < hw->intr_tqps_num; i++) {
 742                 /*
 743                  * Set gap limiter/rate limiter/quanity limiter algorithm
 744                  * configuration for interrupt coalesce of queue's interrupt.
 745                  */
 746                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 747                                        HNS3_TQP_INTR_GL_DEFAULT);
 748                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 749                                        HNS3_TQP_INTR_GL_DEFAULT);
 750                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 751                 /*
 752                  * QL(quantity limiter) is not used currently, just set 0 to
 753                  * close it.
 754                  */
 755                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 756
 757                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 758                                                    HNS3_RING_TYPE_TX, i);
 759                 if (ret) {
 760                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 761                                           "vector: %u, ret=%d", i, vec, ret);
 762                         return ret;
 763                 }
 764
 765                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 766                                                    HNS3_RING_TYPE_RX, i);
 767                 if (ret) {
 768                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 769                                           "vector: %u, ret=%d", i, vec, ret);
 770                         return ret;
 771                 }
 772         }
 773
 774         return 0;
 775 }
 776
 777 static int
 778 hns3vf_dev_configure(struct rte_eth_dev *dev)
 779 {
 780         struct hns3_adapter *hns = dev->data->dev_private;
 781         struct hns3_hw *hw = &hns->hw;
 782         struct rte_eth_conf *conf = &dev->data->dev_conf;
 783         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 784         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 785         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 786         struct rte_eth_rss_conf rss_conf;
 787         uint32_t max_rx_pkt_len;
 788         uint16_t mtu;
 789         bool gro_en;
 790         int ret;
 791
 792         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 793
 794         /*
 795          * Some versions of hardware network engine does not support
 796          * individually enable/disable/reset the Tx or Rx queue. These devices
 797          * must enable/disable/reset Tx and Rx queues at the same time. When the
 798          * numbers of Tx queues allocated by upper applications are not equal to
 799          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 800          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 801          * work as usual. But these fake queues are imperceptible, and can not
 802          * be used by upper applications.
 803          */
 804         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 805         if (ret) {
 806                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
 807                 hw->cfg_max_queues = 0;
 808                 return ret;
 809         }
 810
 811         hw->adapter_state = HNS3_NIC_CONFIGURING;
 812         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 813                 hns3_err(hw, "setting link speed/duplex not supported");
 814                 ret = -EINVAL;
 815                 goto cfg_err;
 816         }
 817
 818         /* When RSS is not configured, redirect the packet queue 0 */
 819         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 820                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 821                 hw->rss_dis_flag = false;
 822                 rss_conf = conf->rx_adv_conf.rss_conf;
 823                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 824                 if (ret)
 825                         goto cfg_err;
 826         }
 827
 828         /*
 829          * If jumbo frames are enabled, MTU needs to be refreshed
 830          * according to the maximum RX packet length.
 831          */
 832         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 833                 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
 834                 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
 835                     max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
 836                         hns3_err(hw, "maximum Rx packet length must be greater "
 837                                  "than %u and less than %u when jumbo frame enabled.",
 838                                  (uint16_t)HNS3_DEFAULT_FRAME_LEN,
 839                                  (uint16_t)HNS3_MAX_FRAME_LEN);
 840                         ret = -EINVAL;
 841                         goto cfg_err;
 842                 }
 843
 844                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
 845                 ret = hns3vf_dev_mtu_set(dev, mtu);
 846                 if (ret)
 847                         goto cfg_err;
 848                 dev->data->mtu = mtu;
 849         }
 850
 851         ret = hns3vf_dev_configure_vlan(dev);
 852         if (ret)
 853                 goto cfg_err;
 854
 855         /* config hardware GRO */
 856         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 857         ret = hns3_config_gro(hw, gro_en);
 858         if (ret)
 859                 goto cfg_err;
 860
 861         hns3_init_rx_ptype_tble(dev);
 862
 863         hw->adapter_state = HNS3_NIC_CONFIGURED;
 864         return 0;
 865
 866 cfg_err:
 867         hw->cfg_max_queues = 0;
 868         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 869         hw->adapter_state = HNS3_NIC_INITIALIZED;
 870
 871         return ret;
 872 }
 873
 874 static int
 875 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 876 {
 877         int ret;
 878
 879         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 880                                 sizeof(mtu), true, NULL, 0);
 881         if (ret)
 882                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 883
 884         return ret;
 885 }
 886
 887 static int
 888 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 889 {
 890         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 891         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 892         int ret;
 893
 894         /*
 895          * The hns3 PF/VF devices on the same port share the hardware MTU
 896          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 897          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 898          * driver, there is no need to stop the port for hns3 VF device, and the
 899          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 900          * PF's MTU.
 901          */
 902         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 903                 hns3_err(hw, "Failed to set mtu during resetting");
 904                 return -EIO;
 905         }
 906
 907         /*
 908          * when Rx of scattered packets is off, we have some possibility of
 909          * using vector Rx process function or simple Rx functions in hns3 PMD
 910          * driver. If the input MTU is increased and the maximum length of
 911          * received packets is greater than the length of a buffer for Rx
 912          * packet, the hardware network engine needs to use multiple BDs and
 913          * buffers to store these packets. This will cause problems when still
 914          * using vector Rx process function or simple Rx function to receiving
 915          * packets. So, when Rx of scattered packets is off and device is
 916          * started, it is not permitted to increase MTU so that the maximum
 917          * length of Rx packets is greater than Rx buffer length.
 918          */
 919         if (dev->data->dev_started && !dev->data->scattered_rx &&
 920             frame_size > hw->rx_buf_len) {
 921                 hns3_err(hw, "failed to set mtu because current is "
 922                         "not scattered rx mode");
 923                 return -EOPNOTSUPP;
 924         }
 925
 926         rte_spinlock_lock(&hw->lock);
 927         ret = hns3vf_config_mtu(hw, mtu);
 928         if (ret) {
 929                 rte_spinlock_unlock(&hw->lock);
 930                 return ret;
 931         }
 932         if (mtu > RTE_ETHER_MTU)
 933                 dev->data->dev_conf.rxmode.offloads |=
 934                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 935         else
 936                 dev->data->dev_conf.rxmode.offloads &=
 937                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 938         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 939         rte_spinlock_unlock(&hw->lock);
 940
 941         return 0;
 942 }
 943
 944 static int
 945 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 946 {
 947         struct hns3_adapter *hns = eth_dev->data->dev_private;
 948         struct hns3_hw *hw = &hns->hw;
 949         uint16_t q_num = hw->tqps_num;
 950
 951         /*
 952          * In interrupt mode, 'max_rx_queues' is set based on the number of
 953          * MSI-X interrupt resources of the hardware.
 954          */
 955         if (hw->data->dev_conf.intr_conf.rxq == 1)
 956                 q_num = hw->intr_tqps_num;
 957
 958         info->max_rx_queues = q_num;
 959         info->max_tx_queues = hw->tqps_num;
 960         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 961         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 962         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 963         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 964         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 965
 966         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 967                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 968                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 969                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 970                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 971                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 972                                  DEV_RX_OFFLOAD_SCATTER |
 973                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 974                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 975                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 976                                  DEV_RX_OFFLOAD_RSS_HASH |
 977                                  DEV_RX_OFFLOAD_TCP_LRO);
 978         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 979                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 980                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 981                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 982                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 983                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 984                                  DEV_TX_OFFLOAD_TCP_TSO |
 985                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 986                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 987                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 988                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 989                                  hns3_txvlan_cap_get(hw));
 990
 991         if (hns3_dev_outer_udp_cksum_supported(hw))
 992                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
 993
 994         if (hns3_dev_indep_txrx_supported(hw))
 995                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 996                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 997
 998         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 999                 .nb_max = HNS3_MAX_RING_DESC,
1000                 .nb_min = HNS3_MIN_RING_DESC,
1001                 .nb_align = HNS3_ALIGN_RING_DESC,
1002         };
1003
1004         info->tx_desc_lim = (struct rte_eth_desc_lim) {
1005                 .nb_max = HNS3_MAX_RING_DESC,
1006                 .nb_min = HNS3_MIN_RING_DESC,
1007                 .nb_align = HNS3_ALIGN_RING_DESC,
1008                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
1009                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
1010         };
1011
1012         info->default_rxconf = (struct rte_eth_rxconf) {
1013                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
1014                 /*
1015                  * If there are no available Rx buffer descriptors, incoming
1016                  * packets are always dropped by hardware based on hns3 network
1017                  * engine.
1018                  */
1019                 .rx_drop_en = 1,
1020                 .offloads = 0,
1021         };
1022         info->default_txconf = (struct rte_eth_txconf) {
1023                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
1024                 .offloads = 0,
1025         };
1026
1027         info->reta_size = hw->rss_ind_tbl_size;
1028         info->hash_key_size = HNS3_RSS_KEY_SIZE;
1029         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1030
1031         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1032         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1033         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1034         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1035         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1036         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1037
1038         return 0;
1039 }
1040
1041 static void
1042 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1043 {
1044         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1045 }
1046
1047 static void
1048 hns3vf_disable_irq0(struct hns3_hw *hw)
1049 {
1050         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1051 }
1052
1053 static void
1054 hns3vf_enable_irq0(struct hns3_hw *hw)
1055 {
1056         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1057 }
1058
1059 static enum hns3vf_evt_cause
1060 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1061 {
1062         struct hns3_hw *hw = &hns->hw;
1063         enum hns3vf_evt_cause ret;
1064         uint32_t cmdq_stat_reg;
1065         uint32_t rst_ing_reg;
1066         uint32_t val;
1067
1068         /* Fetch the events from their corresponding regs */
1069         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1070         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1071                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1072                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1073                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1074                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
1075                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1076                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1077                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1078                 if (clearval) {
1079                         hw->reset.stats.global_cnt++;
1080                         hns3_warn(hw, "Global reset detected, clear reset status");
1081                 } else {
1082                         hns3_schedule_delayed_reset(hns);
1083                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1084                 }
1085
1086                 ret = HNS3VF_VECTOR0_EVENT_RST;
1087                 goto out;
1088         }
1089
1090         /* Check for vector0 mailbox(=CMDQ RX) event source */
1091         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1092                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1093                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1094                 goto out;
1095         }
1096
1097         val = 0;
1098         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1099 out:
1100         if (clearval)
1101                 *clearval = val;
1102         return ret;
1103 }
1104
1105 static void
1106 hns3vf_interrupt_handler(void *param)
1107 {
1108         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1109         struct hns3_adapter *hns = dev->data->dev_private;
1110         struct hns3_hw *hw = &hns->hw;
1111         enum hns3vf_evt_cause event_cause;
1112         uint32_t clearval;
1113
1114         /* Disable interrupt */
1115         hns3vf_disable_irq0(hw);
1116
1117         /* Read out interrupt causes */
1118         event_cause = hns3vf_check_event_cause(hns, &clearval);
1119
1120         switch (event_cause) {
1121         case HNS3VF_VECTOR0_EVENT_RST:
1122                 hns3_schedule_reset(hns);
1123                 break;
1124         case HNS3VF_VECTOR0_EVENT_MBX:
1125                 hns3_dev_handle_mbx_msg(hw);
1126                 break;
1127         default:
1128                 break;
1129         }
1130
1131         /* Clear interrupt causes */
1132         hns3vf_clear_event_cause(hw, clearval);
1133
1134         /* Enable interrupt */
1135         hns3vf_enable_irq0(hw);
1136 }
1137
1138 static void
1139 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1140 {
1141         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1142         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1143         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1144         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
1145 }
1146
1147 static void
1148 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1149 {
1150         struct hns3_dev_specs_0_cmd *req0;
1151
1152         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1153
1154         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1155         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1156         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1157         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
1158 }
1159
1160 static int
1161 hns3vf_check_dev_specifications(struct hns3_hw *hw)
1162 {
1163         if (hw->rss_ind_tbl_size == 0 ||
1164             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
1165                 hns3_warn(hw, "the size of hash lookup table configured (%u)"
1166                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
1167                               HNS3_RSS_IND_TBL_SIZE_MAX);
1168                 return -EINVAL;
1169         }
1170
1171         return 0;
1172 }
1173
1174 static int
1175 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1176 {
1177         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1178         int ret;
1179         int i;
1180
1181         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1182                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1183                                           true);
1184                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1185         }
1186         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1187
1188         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1189         if (ret)
1190                 return ret;
1191
1192         hns3vf_parse_dev_specifications(hw, desc);
1193
1194         return hns3vf_check_dev_specifications(hw);
1195 }
1196
1197 void
1198 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
1199 {
1200         uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
1201                                    HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1202         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1203         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1204
1205         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1206                 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1207                                           __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1208 }
1209
1210 static void
1211 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
1212 {
1213 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS      500
1214
1215         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1216         int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
1217         uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1218         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1219         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1220
1221         __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
1222                          __ATOMIC_RELEASE);
1223
1224         (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1225                                 NULL, 0);
1226
1227         while (remain_ms > 0) {
1228                 rte_delay_ms(HNS3_POLL_RESPONE_MS);
1229                 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
1230                         HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1231                         break;
1232                 remain_ms--;
1233         }
1234
1235         /*
1236          * When exit above loop, the pf_push_lsc_cap could be one of the three
1237          * state: unknown (means pf not ack), not_supported, supported.
1238          * Here config it as 'not_supported' when it's 'unknown' state.
1239          */
1240         __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1241                                   __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1242
1243         if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
1244                 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
1245                 hns3_info(hw, "detect PF support push link status change!");
1246         } else {
1247                 /*
1248                  * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
1249                  * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
1250                  * the RTE_ETH_DEV_INTR_LSC capability.
1251                  */
1252                 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
1253         }
1254 }
1255
1256 static int
1257 hns3vf_get_capability(struct hns3_hw *hw)
1258 {
1259         struct rte_pci_device *pci_dev;
1260         struct rte_eth_dev *eth_dev;
1261         uint8_t revision;
1262         int ret;
1263
1264         eth_dev = &rte_eth_devices[hw->data->port_id];
1265         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1266
1267         /* Get PCI revision id */
1268         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1269                                   HNS3_PCI_REVISION_ID);
1270         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1271                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1272                              ret);
1273                 return -EIO;
1274         }
1275         hw->revision = revision;
1276
1277         if (revision < PCI_REVISION_ID_HIP09_A) {
1278                 hns3vf_set_default_dev_specifications(hw);
1279                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1280                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1281                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1282                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
1283                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1284                 hw->rss_info.ipv6_sctp_offload_supported = false;
1285                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1286                 return 0;
1287         }
1288
1289         ret = hns3vf_query_dev_specifications(hw);
1290         if (ret) {
1291                 PMD_INIT_LOG(ERR,
1292                              "failed to query dev specifications, ret = %d",
1293                              ret);
1294                 return ret;
1295         }
1296
1297         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1298         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1299         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1300         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1301         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1302         hw->rss_info.ipv6_sctp_offload_supported = true;
1303         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1304
1305         return 0;
1306 }
1307
1308 static int
1309 hns3vf_check_tqp_info(struct hns3_hw *hw)
1310 {
1311         if (hw->tqps_num == 0) {
1312                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1313                 return -EINVAL;
1314         }
1315
1316         if (hw->rss_size_max == 0) {
1317                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1318                 return -EINVAL;
1319         }
1320
1321         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1322
1323         return 0;
1324 }
1325
1326 static int
1327 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1328 {
1329         uint8_t resp_msg;
1330         int ret;
1331
1332         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1333                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1334                                 true, &resp_msg, sizeof(resp_msg));
1335         if (ret) {
1336                 if (ret == -ETIME) {
1337                         /*
1338                          * Getting current port based VLAN state from PF driver
1339                          * will not affect VF driver's basic function. Because
1340                          * the VF driver relies on hns3 PF kernel ether driver,
1341                          * to avoid introducing compatibility issues with older
1342                          * version of PF driver, no failure will be returned
1343                          * when the return value is ETIME. This return value has
1344                          * the following scenarios:
1345                          * 1) Firmware didn't return the results in time
1346                          * 2) the result return by firmware is timeout
1347                          * 3) the older version of kernel side PF driver does
1348                          *    not support this mailbox message.
1349                          * For scenarios 1 and 2, it is most likely that a
1350                          * hardware error has occurred, or a hardware reset has
1351                          * occurred. In this case, these errors will be caught
1352                          * by other functions.
1353                          */
1354                         PMD_INIT_LOG(WARNING,
1355                                 "failed to get PVID state for timeout, maybe "
1356                                 "kernel side PF driver doesn't support this "
1357                                 "mailbox message, or firmware didn't respond.");
1358                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1359                 } else {
1360                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1361                                 " ret = %d", ret);
1362                         return ret;
1363                 }
1364         }
1365         hw->port_base_vlan_cfg.state = resp_msg ?
1366                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1367         return 0;
1368 }
1369
1370 static int
1371 hns3vf_get_queue_info(struct hns3_hw *hw)
1372 {
1373 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1374         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1375         int ret;
1376
1377         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1378                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1379         if (ret) {
1380                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1381                 return ret;
1382         }
1383
1384         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1385         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1386
1387         return hns3vf_check_tqp_info(hw);
1388 }
1389
1390 static int
1391 hns3vf_get_queue_depth(struct hns3_hw *hw)
1392 {
1393 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1394         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1395         int ret;
1396
1397         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1398                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1399         if (ret) {
1400                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1401                              ret);
1402                 return ret;
1403         }
1404
1405         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1406         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1407
1408         return 0;
1409 }
1410
1411 static void
1412 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
1413 {
1414         if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
1415                 hns3_set_bit(hw->capability,
1416                                 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
1417 }
1418
1419 static int
1420 hns3vf_get_num_tc(struct hns3_hw *hw)
1421 {
1422         uint8_t num_tc = 0;
1423         uint32_t i;
1424
1425         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1426                 if (hw->hw_tc_map & BIT(i))
1427                         num_tc++;
1428         }
1429         return num_tc;
1430 }
1431
1432 static int
1433 hns3vf_get_basic_info(struct hns3_hw *hw)
1434 {
1435         uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
1436         struct hns3_basic_info *basic_info;
1437         int ret;
1438
1439         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
1440                                 true, resp_msg, sizeof(resp_msg));
1441         if (ret) {
1442                 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
1443                                 ret);
1444                 return ret;
1445         }
1446
1447         basic_info = (struct hns3_basic_info *)resp_msg;
1448         hw->hw_tc_map = basic_info->hw_tc_map;
1449         hw->num_tc = hns3vf_get_num_tc(hw);
1450         hw->pf_vf_if_version = basic_info->pf_vf_if_version;
1451         hns3vf_update_caps(hw, basic_info->caps);
1452
1453         return 0;
1454 }
1455
1456 static int
1457 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1458 {
1459         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1460         int ret;
1461
1462         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1463                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1464         if (ret) {
1465                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1466                 return ret;
1467         }
1468
1469         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1470
1471         return 0;
1472 }
1473
1474 static int
1475 hns3vf_get_configuration(struct hns3_hw *hw)
1476 {
1477         int ret;
1478
1479         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1480         hw->rss_dis_flag = false;
1481
1482         /* Get device capability */
1483         ret = hns3vf_get_capability(hw);
1484         if (ret) {
1485                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1486                 return ret;
1487         }
1488
1489         hns3vf_get_push_lsc_cap(hw);
1490
1491         /* Get basic info from PF */
1492         ret = hns3vf_get_basic_info(hw);
1493         if (ret)
1494                 return ret;
1495
1496         /* Get queue configuration from PF */
1497         ret = hns3vf_get_queue_info(hw);
1498         if (ret)
1499                 return ret;
1500
1501         /* Get queue depth info from PF */
1502         ret = hns3vf_get_queue_depth(hw);
1503         if (ret)
1504                 return ret;
1505
1506         /* Get user defined VF MAC addr from PF */
1507         ret = hns3vf_get_host_mac_addr(hw);
1508         if (ret)
1509                 return ret;
1510
1511         return hns3vf_get_port_base_vlan_filter_state(hw);
1512 }
1513
1514 static int
1515 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1516                             uint16_t nb_tx_q)
1517 {
1518         struct hns3_hw *hw = &hns->hw;
1519
1520         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1521 }
1522
1523 static void
1524 hns3vf_request_link_info(struct hns3_hw *hw)
1525 {
1526         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1527         bool send_req;
1528         int ret;
1529
1530         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1531                 return;
1532
1533         send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1534                    vf->req_link_info_cnt > 0;
1535         if (!send_req)
1536                 return;
1537
1538         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1539                                 NULL, 0);
1540         if (ret) {
1541                 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1542                 return;
1543         }
1544
1545         if (vf->req_link_info_cnt > 0)
1546                 vf->req_link_info_cnt--;
1547 }
1548
1549 void
1550 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1551                           uint32_t link_speed, uint8_t link_duplex)
1552 {
1553         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1554         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1555         struct hns3_mac *mac = &hw->mac;
1556         int ret;
1557
1558         /*
1559          * PF kernel driver may push link status when VF driver is in resetting,
1560          * driver will stop polling job in this case, after resetting done
1561          * driver will start polling job again.
1562          * When polling job started, driver will get initial link status by
1563          * sending request to PF kernel driver, then could update link status by
1564          * process PF kernel driver's link status mailbox message.
1565          */
1566         if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1567                 return;
1568
1569         if (hw->adapter_state != HNS3_NIC_STARTED)
1570                 return;
1571
1572         mac->link_status = link_status;
1573         mac->link_speed = link_speed;
1574         mac->link_duplex = link_duplex;
1575         ret = hns3vf_dev_link_update(dev, 0);
1576         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1577                 hns3_start_report_lse(dev);
1578 }
1579
1580 static int
1581 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1582 {
1583 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1584         struct hns3_hw *hw = &hns->hw;
1585         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1586         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1587         uint8_t is_kill = on ? 0 : 1;
1588
1589         msg_data[0] = is_kill;
1590         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1591         memcpy(&msg_data[3], &proto, sizeof(proto));
1592
1593         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1594                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1595                                  0);
1596 }
1597
1598 static int
1599 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1600 {
1601         struct hns3_adapter *hns = dev->data->dev_private;
1602         struct hns3_hw *hw = &hns->hw;
1603         int ret;
1604
1605         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1606                 hns3_err(hw,
1607                          "vf set vlan id failed during resetting, vlan_id =%u",
1608                          vlan_id);
1609                 return -EIO;
1610         }
1611         rte_spinlock_lock(&hw->lock);
1612         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1613         rte_spinlock_unlock(&hw->lock);
1614         if (ret)
1615                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1616                          vlan_id, ret);
1617
1618         return ret;
1619 }
1620
1621 static int
1622 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1623 {
1624         uint8_t msg_data;
1625         int ret;
1626
1627         if (!hns3_dev_vf_vlan_flt_supported(hw))
1628                 return 0;
1629
1630         msg_data = enable ? 1 : 0;
1631         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1632                         HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1633                         sizeof(msg_data), true, NULL, 0);
1634         if (ret)
1635                 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1636                                 enable ? "enable" : "disable", ret);
1637
1638         return ret;
1639 }
1640
1641 static int
1642 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1643 {
1644         uint8_t msg_data;
1645         int ret;
1646
1647         msg_data = enable ? 1 : 0;
1648         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1649                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1650         if (ret)
1651                 hns3_err(hw, "vf %s strip failed, ret = %d.",
1652                                 enable ? "enable" : "disable", ret);
1653
1654         return ret;
1655 }
1656
1657 static int
1658 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1659 {
1660         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1661         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1662         unsigned int tmp_mask;
1663         int ret = 0;
1664
1665         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1666                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1667                              "mask = 0x%x", mask);
1668                 return -EIO;
1669         }
1670
1671         tmp_mask = (unsigned int)mask;
1672
1673         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
1674                 rte_spinlock_lock(&hw->lock);
1675                 /* Enable or disable VLAN filter */
1676                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1677                         ret = hns3vf_en_vlan_filter(hw, true);
1678                 else
1679                         ret = hns3vf_en_vlan_filter(hw, false);
1680                 rte_spinlock_unlock(&hw->lock);
1681                 if (ret)
1682                         return ret;
1683         }
1684
1685         /* Vlan stripping setting */
1686         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1687                 rte_spinlock_lock(&hw->lock);
1688                 /* Enable or disable VLAN stripping */
1689                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1690                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1691                 else
1692                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1693                 rte_spinlock_unlock(&hw->lock);
1694         }
1695
1696         return ret;
1697 }
1698
1699 static int
1700 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1701 {
1702         struct rte_vlan_filter_conf *vfc;
1703         struct hns3_hw *hw = &hns->hw;
1704         uint16_t vlan_id;
1705         uint64_t vbit;
1706         uint64_t ids;
1707         int ret = 0;
1708         uint32_t i;
1709
1710         vfc = &hw->data->vlan_filter_conf;
1711         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1712                 if (vfc->ids[i] == 0)
1713                         continue;
1714                 ids = vfc->ids[i];
1715                 while (ids) {
1716                         /*
1717                          * 64 means the num bits of ids, one bit corresponds to
1718                          * one vlan id
1719                          */
1720                         vlan_id = 64 * i;
1721                         /* count trailing zeroes */
1722                         vbit = ~ids & (ids - 1);
1723                         /* clear least significant bit set */
1724                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1725                         for (; vbit;) {
1726                                 vbit >>= 1;
1727                                 vlan_id++;
1728                         }
1729                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1730                         if (ret) {
1731                                 hns3_err(hw,
1732                                          "VF handle vlan table failed, ret =%d, on = %d",
1733                                          ret, on);
1734                                 return ret;
1735                         }
1736                 }
1737         }
1738
1739         return ret;
1740 }
1741
1742 static int
1743 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1744 {
1745         return hns3vf_handle_all_vlan_table(hns, 0);
1746 }
1747
1748 static int
1749 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1750 {
1751         struct hns3_hw *hw = &hns->hw;
1752         struct rte_eth_conf *dev_conf;
1753         bool en;
1754         int ret;
1755
1756         dev_conf = &hw->data->dev_conf;
1757         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1758                                                                    : false;
1759         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1760         if (ret)
1761                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1762                          ret);
1763         return ret;
1764 }
1765
1766 static int
1767 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1768 {
1769         struct hns3_adapter *hns = dev->data->dev_private;
1770         struct rte_eth_dev_data *data = dev->data;
1771         struct hns3_hw *hw = &hns->hw;
1772         int ret;
1773
1774         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1775             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1776             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1777                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1778                               "or hw_vlan_insert_pvid is not support!");
1779         }
1780
1781         /* Apply vlan offload setting */
1782         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK |
1783                                         ETH_VLAN_FILTER_MASK);
1784         if (ret)
1785                 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1786
1787         return ret;
1788 }
1789
1790 static int
1791 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1792 {
1793         uint8_t msg_data;
1794
1795         msg_data = alive ? 1 : 0;
1796         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1797                                  sizeof(msg_data), false, NULL, 0);
1798 }
1799
1800 static void
1801 hns3vf_keep_alive_handler(void *param)
1802 {
1803         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1804         struct hns3_adapter *hns = eth_dev->data->dev_private;
1805         struct hns3_hw *hw = &hns->hw;
1806         int ret;
1807
1808         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1809                                 false, NULL, 0);
1810         if (ret)
1811                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1812                          ret);
1813
1814         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1815                           eth_dev);
1816 }
1817
1818 static void
1819 hns3vf_service_handler(void *param)
1820 {
1821         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1822         struct hns3_adapter *hns = eth_dev->data->dev_private;
1823         struct hns3_hw *hw = &hns->hw;
1824
1825         /*
1826          * The query link status and reset processing are executed in the
1827          * interrupt thread. When the IMP reset occurs, IMP will not respond,
1828          * and the query operation will timeout after 30ms. In the case of
1829          * multiple PF/VFs, each query failure timeout causes the IMP reset
1830          * interrupt to fail to respond within 100ms.
1831          * Before querying the link status, check whether there is a reset
1832          * pending, and if so, abandon the query.
1833          */
1834         if (!hns3vf_is_reset_pending(hns))
1835                 hns3vf_request_link_info(hw);
1836         else
1837                 hns3_warn(hw, "Cancel the query when reset is pending");
1838
1839         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1840                           eth_dev);
1841 }
1842
1843 static void
1844 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1845 {
1846 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT      3
1847
1848         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1849
1850         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1851                 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1852
1853         __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1854
1855         hns3vf_service_handler(dev);
1856 }
1857
1858 static void
1859 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1860 {
1861         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1862
1863         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1864
1865         __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1866 }
1867
1868 static int
1869 hns3_query_vf_resource(struct hns3_hw *hw)
1870 {
1871         struct hns3_vf_res_cmd *req;
1872         struct hns3_cmd_desc desc;
1873         uint16_t num_msi;
1874         int ret;
1875
1876         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1877         ret = hns3_cmd_send(hw, &desc, 1);
1878         if (ret) {
1879                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1880                 return ret;
1881         }
1882
1883         req = (struct hns3_vf_res_cmd *)desc.data;
1884         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1885                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1886         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1887                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1888                          num_msi, HNS3_MIN_VECTOR_NUM);
1889                 return -EINVAL;
1890         }
1891
1892         hw->num_msi = num_msi;
1893
1894         return 0;
1895 }
1896
1897 static int
1898 hns3vf_init_hardware(struct hns3_adapter *hns)
1899 {
1900         struct hns3_hw *hw = &hns->hw;
1901         uint16_t mtu = hw->data->mtu;
1902         int ret;
1903
1904         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1905         if (ret)
1906                 return ret;
1907
1908         ret = hns3vf_config_mtu(hw, mtu);
1909         if (ret)
1910                 goto err_init_hardware;
1911
1912         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1913         if (ret) {
1914                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1915                 goto err_init_hardware;
1916         }
1917
1918         ret = hns3_config_gro(hw, false);
1919         if (ret) {
1920                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1921                 goto err_init_hardware;
1922         }
1923
1924         /*
1925          * In the initialization clearing the all hardware mapping relationship
1926          * configurations between queues and interrupt vectors is needed, so
1927          * some error caused by the residual configurations, such as the
1928          * unexpected interrupt, can be avoid.
1929          */
1930         ret = hns3vf_init_ring_with_vector(hw);
1931         if (ret) {
1932                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1933                 goto err_init_hardware;
1934         }
1935
1936         return 0;
1937
1938 err_init_hardware:
1939         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1940         return ret;
1941 }
1942
1943 static int
1944 hns3vf_clear_vport_list(struct hns3_hw *hw)
1945 {
1946         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1947                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1948                                  NULL, 0);
1949 }
1950
1951 static int
1952 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1953 {
1954         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1955         struct hns3_adapter *hns = eth_dev->data->dev_private;
1956         struct hns3_hw *hw = &hns->hw;
1957         int ret;
1958
1959         PMD_INIT_FUNC_TRACE();
1960
1961         /* Get hardware io base address from pcie BAR2 IO space */
1962         hw->io_base = pci_dev->mem_resource[2].addr;
1963
1964         /* Firmware command queue initialize */
1965         ret = hns3_cmd_init_queue(hw);
1966         if (ret) {
1967                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1968                 goto err_cmd_init_queue;
1969         }
1970
1971         /* Firmware command initialize */
1972         ret = hns3_cmd_init(hw);
1973         if (ret) {
1974                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1975                 goto err_cmd_init;
1976         }
1977
1978         hns3_tx_push_init(eth_dev);
1979
1980         /* Get VF resource */
1981         ret = hns3_query_vf_resource(hw);
1982         if (ret)
1983                 goto err_cmd_init;
1984
1985         rte_spinlock_init(&hw->mbx_resp.lock);
1986
1987         hns3vf_clear_event_cause(hw, 0);
1988
1989         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1990                                          hns3vf_interrupt_handler, eth_dev);
1991         if (ret) {
1992                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1993                 goto err_intr_callback_register;
1994         }
1995
1996         /* Enable interrupt */
1997         rte_intr_enable(&pci_dev->intr_handle);
1998         hns3vf_enable_irq0(hw);
1999
2000         /* Get configuration from PF */
2001         ret = hns3vf_get_configuration(hw);
2002         if (ret) {
2003                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
2004                 goto err_get_config;
2005         }
2006
2007         ret = hns3_tqp_stats_init(hw);
2008         if (ret)
2009                 goto err_get_config;
2010
2011         /* Hardware statistics of imissed registers cleared. */
2012         ret = hns3_update_imissed_stats(hw, true);
2013         if (ret) {
2014                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
2015                 goto err_set_tc_queue;
2016         }
2017
2018         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
2019         if (ret) {
2020                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
2021                 goto err_set_tc_queue;
2022         }
2023
2024         ret = hns3vf_clear_vport_list(hw);
2025         if (ret) {
2026                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
2027                 goto err_set_tc_queue;
2028         }
2029
2030         ret = hns3vf_init_hardware(hns);
2031         if (ret)
2032                 goto err_set_tc_queue;
2033
2034         hns3_rss_set_default_args(hw);
2035
2036         ret = hns3vf_set_alive(hw, true);
2037         if (ret) {
2038                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
2039                 goto err_set_tc_queue;
2040         }
2041
2042         return 0;
2043
2044 err_set_tc_queue:
2045         hns3_tqp_stats_uninit(hw);
2046
2047 err_get_config:
2048         hns3vf_disable_irq0(hw);
2049         rte_intr_disable(&pci_dev->intr_handle);
2050         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
2051                              eth_dev);
2052 err_intr_callback_register:
2053 err_cmd_init:
2054         hns3_cmd_uninit(hw);
2055         hns3_cmd_destroy_queue(hw);
2056 err_cmd_init_queue:
2057         hw->io_base = NULL;
2058
2059         return ret;
2060 }
2061
2062 static void
2063 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
2064 {
2065         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2066         struct hns3_adapter *hns = eth_dev->data->dev_private;
2067         struct hns3_hw *hw = &hns->hw;
2068
2069         PMD_INIT_FUNC_TRACE();
2070
2071         hns3_rss_uninit(hns);
2072         (void)hns3_config_gro(hw, false);
2073         (void)hns3vf_set_alive(hw, false);
2074         (void)hns3vf_set_promisc_mode(hw, false, false, false);
2075         hns3_tqp_stats_uninit(hw);
2076         hns3vf_disable_irq0(hw);
2077         rte_intr_disable(&pci_dev->intr_handle);
2078         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
2079                              eth_dev);
2080         hns3_cmd_uninit(hw);
2081         hns3_cmd_destroy_queue(hw);
2082         hw->io_base = NULL;
2083 }
2084
2085 static int
2086 hns3vf_do_stop(struct hns3_adapter *hns)
2087 {
2088         struct hns3_hw *hw = &hns->hw;
2089         int ret;
2090
2091         hw->mac.link_status = ETH_LINK_DOWN;
2092
2093         /*
2094          * The "hns3vf_do_stop" function will also be called by .stop_service to
2095          * prepare reset. At the time of global or IMP reset, the command cannot
2096          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
2097          * accessed during the reset process. So the mbuf can not be released
2098          * during reset and is required to be released after the reset is
2099          * completed.
2100          */
2101         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
2102                 hns3_dev_release_mbufs(hns);
2103
2104         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
2105                 hns3vf_configure_mac_addr(hns, true);
2106                 ret = hns3_reset_all_tqps(hns);
2107                 if (ret) {
2108                         hns3_err(hw, "failed to reset all queues ret = %d",
2109                                  ret);
2110                         return ret;
2111                 }
2112         }
2113         return 0;
2114 }
2115
2116 static void
2117 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
2118 {
2119         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2121         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2122         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2123         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2124         uint16_t q_id;
2125
2126         if (dev->data->dev_conf.intr_conf.rxq == 0)
2127                 return;
2128
2129         /* unmap the ring with vector */
2130         if (rte_intr_allow_others(intr_handle)) {
2131                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2132                 base = RTE_INTR_VEC_RXTX_OFFSET;
2133         }
2134         if (rte_intr_dp_is_en(intr_handle)) {
2135                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2136                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
2137                                                            HNS3_RING_TYPE_RX,
2138                                                            q_id);
2139                         if (vec < base + intr_handle->nb_efd - 1)
2140                                 vec++;
2141                 }
2142         }
2143         /* Clean datapath event and queue/vec mapping */
2144         rte_intr_efd_disable(intr_handle);
2145         if (intr_handle->intr_vec) {
2146                 rte_free(intr_handle->intr_vec);
2147                 intr_handle->intr_vec = NULL;
2148         }
2149 }
2150
2151 static int
2152 hns3vf_dev_stop(struct rte_eth_dev *dev)
2153 {
2154         struct hns3_adapter *hns = dev->data->dev_private;
2155         struct hns3_hw *hw = &hns->hw;
2156
2157         PMD_INIT_FUNC_TRACE();
2158         dev->data->dev_started = 0;
2159
2160         hw->adapter_state = HNS3_NIC_STOPPING;
2161         hns3_set_rxtx_function(dev);
2162         rte_wmb();
2163         /* Disable datapath on secondary process. */
2164         hns3_mp_req_stop_rxtx(dev);
2165         /* Prevent crashes when queues are still in use. */
2166         rte_delay_ms(hw->cfg_max_queues);
2167
2168         rte_spinlock_lock(&hw->lock);
2169         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
2170                 hns3_stop_tqps(hw);
2171                 hns3vf_do_stop(hns);
2172                 hns3vf_unmap_rx_interrupt(dev);
2173                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2174         }
2175         hns3_rx_scattered_reset(dev);
2176         hns3vf_stop_poll_job(dev);
2177         hns3_stop_report_lse(dev);
2178         rte_spinlock_unlock(&hw->lock);
2179
2180         return 0;
2181 }
2182
2183 static int
2184 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
2185 {
2186         struct hns3_adapter *hns = eth_dev->data->dev_private;
2187         struct hns3_hw *hw = &hns->hw;
2188         int ret = 0;
2189
2190         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2191                 rte_free(eth_dev->process_private);
2192                 eth_dev->process_private = NULL;
2193                 return 0;
2194         }
2195
2196         if (hw->adapter_state == HNS3_NIC_STARTED)
2197                 ret = hns3vf_dev_stop(eth_dev);
2198
2199         hw->adapter_state = HNS3_NIC_CLOSING;
2200         hns3_reset_abort(hns);
2201         hw->adapter_state = HNS3_NIC_CLOSED;
2202         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
2203         hns3vf_configure_all_mc_mac_addr(hns, true);
2204         hns3vf_remove_all_vlan_table(hns);
2205         hns3vf_uninit_vf(eth_dev);
2206         hns3_free_all_queues(eth_dev);
2207         rte_free(hw->reset.wait_data);
2208         rte_free(eth_dev->process_private);
2209         eth_dev->process_private = NULL;
2210         hns3_mp_uninit_primary();
2211         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
2212
2213         return ret;
2214 }
2215
2216 static int
2217 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2218                       size_t fw_size)
2219 {
2220         struct hns3_adapter *hns = eth_dev->data->dev_private;
2221         struct hns3_hw *hw = &hns->hw;
2222         uint32_t version = hw->fw_version;
2223         int ret;
2224
2225         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2226                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2227                                       HNS3_FW_VERSION_BYTE3_S),
2228                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2229                                       HNS3_FW_VERSION_BYTE2_S),
2230                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2231                                       HNS3_FW_VERSION_BYTE1_S),
2232                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2233                                       HNS3_FW_VERSION_BYTE0_S));
2234         if (ret < 0)
2235                 return -EINVAL;
2236
2237         ret += 1; /* add the size of '\0' */
2238         if (fw_size < (size_t)ret)
2239                 return ret;
2240         else
2241                 return 0;
2242 }
2243
2244 static int
2245 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2246                        __rte_unused int wait_to_complete)
2247 {
2248         struct hns3_adapter *hns = eth_dev->data->dev_private;
2249         struct hns3_hw *hw = &hns->hw;
2250         struct hns3_mac *mac = &hw->mac;
2251         struct rte_eth_link new_link;
2252
2253         memset(&new_link, 0, sizeof(new_link));
2254         switch (mac->link_speed) {
2255         case ETH_SPEED_NUM_10M:
2256         case ETH_SPEED_NUM_100M:
2257         case ETH_SPEED_NUM_1G:
2258         case ETH_SPEED_NUM_10G:
2259         case ETH_SPEED_NUM_25G:
2260         case ETH_SPEED_NUM_40G:
2261         case ETH_SPEED_NUM_50G:
2262         case ETH_SPEED_NUM_100G:
2263         case ETH_SPEED_NUM_200G:
2264                 if (mac->link_status)
2265                         new_link.link_speed = mac->link_speed;
2266                 break;
2267         default:
2268                 if (mac->link_status)
2269                         new_link.link_speed = ETH_SPEED_NUM_UNKNOWN;
2270                 break;
2271         }
2272
2273         if (!mac->link_status)
2274                 new_link.link_speed = ETH_SPEED_NUM_NONE;
2275
2276         new_link.link_duplex = mac->link_duplex;
2277         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2278         new_link.link_autoneg =
2279             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2280
2281         return rte_eth_linkstatus_set(eth_dev, &new_link);
2282 }
2283
2284 static int
2285 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2286 {
2287         struct hns3_hw *hw = &hns->hw;
2288         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2289         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2290         int ret;
2291
2292         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2293         if (ret)
2294                 return ret;
2295
2296         hns3_enable_rxd_adv_layout(hw);
2297
2298         ret = hns3_init_queues(hns, reset_queue);
2299         if (ret)
2300                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2301
2302         return ret;
2303 }
2304
2305 static int
2306 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2307 {
2308         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2309         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2310         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2311         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2312         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2313         uint32_t intr_vector;
2314         uint16_t q_id;
2315         int ret;
2316
2317         /*
2318          * hns3 needs a separate interrupt to be used as event interrupt which
2319          * could not be shared with task queue pair, so KERNEL drivers need
2320          * support multiple interrupt vectors.
2321          */
2322         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2323             !rte_intr_cap_multiple(intr_handle))
2324                 return 0;
2325
2326         rte_intr_disable(intr_handle);
2327         intr_vector = hw->used_rx_queues;
2328         /* It creates event fd for each intr vector when MSIX is used */
2329         if (rte_intr_efd_enable(intr_handle, intr_vector))
2330                 return -EINVAL;
2331
2332         if (intr_handle->intr_vec == NULL) {
2333                 intr_handle->intr_vec =
2334                         rte_zmalloc("intr_vec",
2335                                     hw->used_rx_queues * sizeof(int), 0);
2336                 if (intr_handle->intr_vec == NULL) {
2337                         hns3_err(hw, "Failed to allocate %u rx_queues"
2338                                      " intr_vec", hw->used_rx_queues);
2339                         ret = -ENOMEM;
2340                         goto vf_alloc_intr_vec_error;
2341                 }
2342         }
2343
2344         if (rte_intr_allow_others(intr_handle)) {
2345                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2346                 base = RTE_INTR_VEC_RXTX_OFFSET;
2347         }
2348
2349         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2350                 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2351                                                    HNS3_RING_TYPE_RX, q_id);
2352                 if (ret)
2353                         goto vf_bind_vector_error;
2354                 intr_handle->intr_vec[q_id] = vec;
2355                 /*
2356                  * If there are not enough efds (e.g. not enough interrupt),
2357                  * remaining queues will be bond to the last interrupt.
2358                  */
2359                 if (vec < base + intr_handle->nb_efd - 1)
2360                         vec++;
2361         }
2362         rte_intr_enable(intr_handle);
2363         return 0;
2364
2365 vf_bind_vector_error:
2366         free(intr_handle->intr_vec);
2367         intr_handle->intr_vec = NULL;
2368 vf_alloc_intr_vec_error:
2369         rte_intr_efd_disable(intr_handle);
2370         return ret;
2371 }
2372
2373 static int
2374 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2375 {
2376         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2377         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2378         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2379         uint16_t q_id;
2380         int ret;
2381
2382         if (dev->data->dev_conf.intr_conf.rxq == 0)
2383                 return 0;
2384
2385         if (rte_intr_dp_is_en(intr_handle)) {
2386                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2387                         ret = hns3vf_bind_ring_with_vector(hw,
2388                                         intr_handle->intr_vec[q_id], true,
2389                                         HNS3_RING_TYPE_RX, q_id);
2390                         if (ret)
2391                                 return ret;
2392                 }
2393         }
2394
2395         return 0;
2396 }
2397
2398 static void
2399 hns3vf_restore_filter(struct rte_eth_dev *dev)
2400 {
2401         hns3_restore_rss_filter(dev);
2402 }
2403
2404 static int
2405 hns3vf_dev_start(struct rte_eth_dev *dev)
2406 {
2407         struct hns3_adapter *hns = dev->data->dev_private;
2408         struct hns3_hw *hw = &hns->hw;
2409         int ret;
2410
2411         PMD_INIT_FUNC_TRACE();
2412         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2413                 return -EBUSY;
2414
2415         rte_spinlock_lock(&hw->lock);
2416         hw->adapter_state = HNS3_NIC_STARTING;
2417         ret = hns3vf_do_start(hns, true);
2418         if (ret) {
2419                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2420                 rte_spinlock_unlock(&hw->lock);
2421                 return ret;
2422         }
2423         ret = hns3vf_map_rx_interrupt(dev);
2424         if (ret)
2425                 goto map_rx_inter_err;
2426
2427         /*
2428          * There are three register used to control the status of a TQP
2429          * (contains a pair of Tx queue and Rx queue) in the new version network
2430          * engine. One is used to control the enabling of Tx queue, the other is
2431          * used to control the enabling of Rx queue, and the last is the master
2432          * switch used to control the enabling of the tqp. The Tx register and
2433          * TQP register must be enabled at the same time to enable a Tx queue.
2434          * The same applies to the Rx queue. For the older network enginem, this
2435          * function only refresh the enabled flag, and it is used to update the
2436          * status of queue in the dpdk framework.
2437          */
2438         ret = hns3_start_all_txqs(dev);
2439         if (ret)
2440                 goto map_rx_inter_err;
2441
2442         ret = hns3_start_all_rxqs(dev);
2443         if (ret)
2444                 goto start_all_rxqs_fail;
2445
2446         hw->adapter_state = HNS3_NIC_STARTED;
2447         rte_spinlock_unlock(&hw->lock);
2448
2449         hns3_rx_scattered_calc(dev);
2450         hns3_set_rxtx_function(dev);
2451         hns3_mp_req_start_rxtx(dev);
2452
2453         hns3vf_restore_filter(dev);
2454
2455         /* Enable interrupt of all rx queues before enabling queues */
2456         hns3_dev_all_rx_queue_intr_enable(hw, true);
2457         hns3_start_tqps(hw);
2458
2459         if (dev->data->dev_conf.intr_conf.lsc != 0)
2460                 hns3vf_dev_link_update(dev, 0);
2461         hns3vf_start_poll_job(dev);
2462
2463         return ret;
2464
2465 start_all_rxqs_fail:
2466         hns3_stop_all_txqs(dev);
2467 map_rx_inter_err:
2468         (void)hns3vf_do_stop(hns);
2469         hw->adapter_state = HNS3_NIC_CONFIGURED;
2470         rte_spinlock_unlock(&hw->lock);
2471
2472         return ret;
2473 }
2474
2475 static bool
2476 is_vf_reset_done(struct hns3_hw *hw)
2477 {
2478 #define HNS3_FUN_RST_ING_BITS \
2479         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2480          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2481          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2482          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2483
2484         uint32_t val;
2485
2486         if (hw->reset.level == HNS3_VF_RESET) {
2487                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2488                 if (val & HNS3_VF_RST_ING_BIT)
2489                         return false;
2490         } else {
2491                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2492                 if (val & HNS3_FUN_RST_ING_BITS)
2493                         return false;
2494         }
2495         return true;
2496 }
2497
2498 bool
2499 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2500 {
2501         struct hns3_hw *hw = &hns->hw;
2502         enum hns3_reset_level reset;
2503
2504         /*
2505          * According to the protocol of PCIe, FLR to a PF device resets the PF
2506          * state as well as the SR-IOV extended capability including VF Enable
2507          * which means that VFs no longer exist.
2508          *
2509          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2510          * is in FLR stage, the register state of VF device is not reliable,
2511          * so register states detection can not be carried out. In this case,
2512          * we just ignore the register states and return false to indicate that
2513          * there are no other reset states that need to be processed by driver.
2514          */
2515         if (hw->reset.level == HNS3_VF_FULL_RESET)
2516                 return false;
2517
2518         /* Check the registers to confirm whether there is reset pending */
2519         hns3vf_check_event_cause(hns, NULL);
2520         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2521         if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2522             hw->reset.level < reset) {
2523                 hns3_warn(hw, "High level reset %d is pending", reset);
2524                 return true;
2525         }
2526         return false;
2527 }
2528
2529 static int
2530 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2531 {
2532         struct hns3_hw *hw = &hns->hw;
2533         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2534         struct timeval tv;
2535
2536         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2537                 /*
2538                  * After vf reset is ready, the PF may not have completed
2539                  * the reset processing. The vf sending mbox to PF may fail
2540                  * during the pf reset, so it is better to add extra delay.
2541                  */
2542                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2543                     hw->reset.level == HNS3_FLR_RESET)
2544                         return 0;
2545                 /* Reset retry process, no need to add extra delay. */
2546                 if (hw->reset.attempts)
2547                         return 0;
2548                 if (wait_data->check_completion == NULL)
2549                         return 0;
2550
2551                 wait_data->check_completion = NULL;
2552                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2553                 wait_data->count = 1;
2554                 wait_data->result = HNS3_WAIT_REQUEST;
2555                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2556                                   wait_data);
2557                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2558                 return -EAGAIN;
2559         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2560                 hns3_clock_gettime(&tv);
2561                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2562                           tv.tv_sec, tv.tv_usec);
2563                 return -ETIME;
2564         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2565                 return -EAGAIN;
2566
2567         wait_data->hns = hns;
2568         wait_data->check_completion = is_vf_reset_done;
2569         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2570                                 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2571         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2572         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2573         wait_data->result = HNS3_WAIT_REQUEST;
2574         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2575         return -EAGAIN;
2576 }
2577
2578 static int
2579 hns3vf_prepare_reset(struct hns3_adapter *hns)
2580 {
2581         struct hns3_hw *hw = &hns->hw;
2582         int ret;
2583
2584         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2585                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2586                                         0, true, NULL, 0);
2587                 if (ret)
2588                         return ret;
2589         }
2590         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2591
2592         return 0;
2593 }
2594
2595 static int
2596 hns3vf_stop_service(struct hns3_adapter *hns)
2597 {
2598         struct hns3_hw *hw = &hns->hw;
2599         struct rte_eth_dev *eth_dev;
2600
2601         eth_dev = &rte_eth_devices[hw->data->port_id];
2602         if (hw->adapter_state == HNS3_NIC_STARTED) {
2603                 /*
2604                  * Make sure call update link status before hns3vf_stop_poll_job
2605                  * because update link status depend on polling job exist.
2606                  */
2607                 hns3vf_update_link_status(hw, ETH_LINK_DOWN, hw->mac.link_speed,
2608                                           hw->mac.link_duplex);
2609                 hns3vf_stop_poll_job(eth_dev);
2610         }
2611         hw->mac.link_status = ETH_LINK_DOWN;
2612
2613         hns3_set_rxtx_function(eth_dev);
2614         rte_wmb();
2615         /* Disable datapath on secondary process. */
2616         hns3_mp_req_stop_rxtx(eth_dev);
2617         rte_delay_ms(hw->cfg_max_queues);
2618
2619         rte_spinlock_lock(&hw->lock);
2620         if (hw->adapter_state == HNS3_NIC_STARTED ||
2621             hw->adapter_state == HNS3_NIC_STOPPING) {
2622                 hns3_enable_all_queues(hw, false);
2623                 hns3vf_do_stop(hns);
2624                 hw->reset.mbuf_deferred_free = true;
2625         } else
2626                 hw->reset.mbuf_deferred_free = false;
2627
2628         /*
2629          * It is cumbersome for hardware to pick-and-choose entries for deletion
2630          * from table space. Hence, for function reset software intervention is
2631          * required to delete the entries.
2632          */
2633         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2634                 hns3vf_configure_all_mc_mac_addr(hns, true);
2635         rte_spinlock_unlock(&hw->lock);
2636
2637         return 0;
2638 }
2639
2640 static int
2641 hns3vf_start_service(struct hns3_adapter *hns)
2642 {
2643         struct hns3_hw *hw = &hns->hw;
2644         struct rte_eth_dev *eth_dev;
2645
2646         eth_dev = &rte_eth_devices[hw->data->port_id];
2647         hns3_set_rxtx_function(eth_dev);
2648         hns3_mp_req_start_rxtx(eth_dev);
2649         if (hw->adapter_state == HNS3_NIC_STARTED) {
2650                 hns3vf_start_poll_job(eth_dev);
2651
2652                 /* Enable interrupt of all rx queues before enabling queues */
2653                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2654                 /*
2655                  * Enable state of each rxq and txq will be recovered after
2656                  * reset, so we need to restore them before enable all tqps;
2657                  */
2658                 hns3_restore_tqp_enable_state(hw);
2659                 /*
2660                  * When finished the initialization, enable queues to receive
2661                  * and transmit packets.
2662                  */
2663                 hns3_enable_all_queues(hw, true);
2664         }
2665
2666         return 0;
2667 }
2668
2669 static int
2670 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2671 {
2672         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2673         struct rte_ether_addr *hw_mac;
2674         int ret;
2675
2676         /*
2677          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2678          * on the host by "ip link set ..." command. If the hns3 PF kernel
2679          * ethdev driver sets the MAC address for VF device after the
2680          * initialization of the related VF device, the PF driver will notify
2681          * VF driver to reset VF device to make the new MAC address effective
2682          * immediately. The hns3 VF PMD driver should check whether the MAC
2683          * address has been changed by the PF kernel ethdev driver, if changed
2684          * VF driver should configure hardware using the new MAC address in the
2685          * recovering hardware configuration stage of the reset process.
2686          */
2687         ret = hns3vf_get_host_mac_addr(hw);
2688         if (ret)
2689                 return ret;
2690
2691         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2692         ret = rte_is_zero_ether_addr(hw_mac);
2693         if (ret) {
2694                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2695         } else {
2696                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2697                 if (!ret) {
2698                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2699                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2700                                               &hw->data->mac_addrs[0]);
2701                         hns3_warn(hw, "Default MAC address has been changed to:"
2702                                   " %s by the host PF kernel ethdev driver",
2703                                   mac_str);
2704                 }
2705         }
2706
2707         return 0;
2708 }
2709
2710 static int
2711 hns3vf_restore_conf(struct hns3_adapter *hns)
2712 {
2713         struct hns3_hw *hw = &hns->hw;
2714         int ret;
2715
2716         ret = hns3vf_check_default_mac_change(hw);
2717         if (ret)
2718                 return ret;
2719
2720         ret = hns3vf_configure_mac_addr(hns, false);
2721         if (ret)
2722                 return ret;
2723
2724         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2725         if (ret)
2726                 goto err_mc_mac;
2727
2728         ret = hns3vf_restore_promisc(hns);
2729         if (ret)
2730                 goto err_vlan_table;
2731
2732         ret = hns3vf_restore_vlan_conf(hns);
2733         if (ret)
2734                 goto err_vlan_table;
2735
2736         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2737         if (ret)
2738                 goto err_vlan_table;
2739
2740         ret = hns3vf_restore_rx_interrupt(hw);
2741         if (ret)
2742                 goto err_vlan_table;
2743
2744         ret = hns3_restore_gro_conf(hw);
2745         if (ret)
2746                 goto err_vlan_table;
2747
2748         if (hw->adapter_state == HNS3_NIC_STARTED) {
2749                 ret = hns3vf_do_start(hns, false);
2750                 if (ret)
2751                         goto err_vlan_table;
2752                 hns3_info(hw, "hns3vf dev restart successful!");
2753         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2754                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2755
2756         ret = hns3vf_set_alive(hw, true);
2757         if (ret) {
2758                 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2759                 goto err_vlan_table;
2760         }
2761
2762         return 0;
2763
2764 err_vlan_table:
2765         hns3vf_configure_all_mc_mac_addr(hns, true);
2766 err_mc_mac:
2767         hns3vf_configure_mac_addr(hns, true);
2768         return ret;
2769 }
2770
2771 static enum hns3_reset_level
2772 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2773 {
2774         enum hns3_reset_level reset_level;
2775
2776         /* return the highest priority reset level amongst all */
2777         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2778                 reset_level = HNS3_VF_RESET;
2779         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2780                 reset_level = HNS3_VF_FULL_RESET;
2781         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2782                 reset_level = HNS3_VF_PF_FUNC_RESET;
2783         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2784                 reset_level = HNS3_VF_FUNC_RESET;
2785         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2786                 reset_level = HNS3_FLR_RESET;
2787         else
2788                 reset_level = HNS3_NONE_RESET;
2789
2790         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2791                 return HNS3_NONE_RESET;
2792
2793         return reset_level;
2794 }
2795
2796 static void
2797 hns3vf_reset_service(void *param)
2798 {
2799         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2800         struct hns3_hw *hw = &hns->hw;
2801         enum hns3_reset_level reset_level;
2802         struct timeval tv_delta;
2803         struct timeval tv_start;
2804         struct timeval tv;
2805         uint64_t msec;
2806
2807         /*
2808          * The interrupt is not triggered within the delay time.
2809          * The interrupt may have been lost. It is necessary to handle
2810          * the interrupt to recover from the error.
2811          */
2812         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2813                             SCHEDULE_DEFERRED) {
2814                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2815                                  __ATOMIC_RELAXED);
2816                 hns3_err(hw, "Handling interrupts in delayed tasks");
2817                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2818                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2819                 if (reset_level == HNS3_NONE_RESET) {
2820                         hns3_err(hw, "No reset level is set, try global reset");
2821                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2822                 }
2823         }
2824         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2825
2826         /*
2827          * Hardware reset has been notified, we now have to poll & check if
2828          * hardware has actually completed the reset sequence.
2829          */
2830         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2831         if (reset_level != HNS3_NONE_RESET) {
2832                 hns3_clock_gettime(&tv_start);
2833                 hns3_reset_process(hns, reset_level);
2834                 hns3_clock_gettime(&tv);
2835                 timersub(&tv, &tv_start, &tv_delta);
2836                 msec = hns3_clock_calctime_ms(&tv_delta);
2837                 if (msec > HNS3_RESET_PROCESS_MS)
2838                         hns3_err(hw, "%d handle long time delta %" PRIu64
2839                                  " ms time=%ld.%.6ld",
2840                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2841         }
2842 }
2843
2844 static int
2845 hns3vf_reinit_dev(struct hns3_adapter *hns)
2846 {
2847         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2848         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2849         struct hns3_hw *hw = &hns->hw;
2850         int ret;
2851
2852         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2853                 rte_intr_disable(&pci_dev->intr_handle);
2854                 ret = hns3vf_set_bus_master(pci_dev, true);
2855                 if (ret < 0) {
2856                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2857                         return ret;
2858                 }
2859         }
2860
2861         /* Firmware command initialize */
2862         ret = hns3_cmd_init(hw);
2863         if (ret) {
2864                 hns3_err(hw, "Failed to init cmd: %d", ret);
2865                 return ret;
2866         }
2867
2868         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2869                 /*
2870                  * UIO enables msix by writing the pcie configuration space
2871                  * vfio_pci enables msix in rte_intr_enable.
2872                  */
2873                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2874                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2875                         if (hns3vf_enable_msix(pci_dev, true))
2876                                 hns3_err(hw, "Failed to enable msix");
2877                 }
2878
2879                 rte_intr_enable(&pci_dev->intr_handle);
2880         }
2881
2882         ret = hns3_reset_all_tqps(hns);
2883         if (ret) {
2884                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2885                 return ret;
2886         }
2887
2888         ret = hns3vf_init_hardware(hns);
2889         if (ret) {
2890                 hns3_err(hw, "Failed to init hardware: %d", ret);
2891                 return ret;
2892         }
2893
2894         return 0;
2895 }
2896
2897 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2898         .dev_configure      = hns3vf_dev_configure,
2899         .dev_start          = hns3vf_dev_start,
2900         .dev_stop           = hns3vf_dev_stop,
2901         .dev_close          = hns3vf_dev_close,
2902         .mtu_set            = hns3vf_dev_mtu_set,
2903         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2904         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2905         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2906         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2907         .stats_get          = hns3_stats_get,
2908         .stats_reset        = hns3_stats_reset,
2909         .xstats_get         = hns3_dev_xstats_get,
2910         .xstats_get_names   = hns3_dev_xstats_get_names,
2911         .xstats_reset       = hns3_dev_xstats_reset,
2912         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2913         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2914         .dev_infos_get      = hns3vf_dev_infos_get,
2915         .fw_version_get     = hns3vf_fw_version_get,
2916         .rx_queue_setup     = hns3_rx_queue_setup,
2917         .tx_queue_setup     = hns3_tx_queue_setup,
2918         .rx_queue_release   = hns3_dev_rx_queue_release,
2919         .tx_queue_release   = hns3_dev_tx_queue_release,
2920         .rx_queue_start     = hns3_dev_rx_queue_start,
2921         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2922         .tx_queue_start     = hns3_dev_tx_queue_start,
2923         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2924         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2925         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2926         .rxq_info_get       = hns3_rxq_info_get,
2927         .txq_info_get       = hns3_txq_info_get,
2928         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2929         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2930         .mac_addr_add       = hns3vf_add_mac_addr,
2931         .mac_addr_remove    = hns3vf_remove_mac_addr,
2932         .mac_addr_set       = hns3vf_set_default_mac_addr,
2933         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2934         .link_update        = hns3vf_dev_link_update,
2935         .rss_hash_update    = hns3_dev_rss_hash_update,
2936         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2937         .reta_update        = hns3_dev_rss_reta_update,
2938         .reta_query         = hns3_dev_rss_reta_query,
2939         .flow_ops_get       = hns3_dev_flow_ops_get,
2940         .vlan_filter_set    = hns3vf_vlan_filter_set,
2941         .vlan_offload_set   = hns3vf_vlan_offload_set,
2942         .get_reg            = hns3_get_regs,
2943         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2944         .tx_done_cleanup    = hns3_tx_done_cleanup,
2945 };
2946
2947 static const struct hns3_reset_ops hns3vf_reset_ops = {
2948         .reset_service       = hns3vf_reset_service,
2949         .stop_service        = hns3vf_stop_service,
2950         .prepare_reset       = hns3vf_prepare_reset,
2951         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2952         .reinit_dev          = hns3vf_reinit_dev,
2953         .restore_conf        = hns3vf_restore_conf,
2954         .start_service       = hns3vf_start_service,
2955 };
2956
2957 static int
2958 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2959 {
2960         struct hns3_adapter *hns = eth_dev->data->dev_private;
2961         struct hns3_hw *hw = &hns->hw;
2962         int ret;
2963
2964         PMD_INIT_FUNC_TRACE();
2965
2966         eth_dev->process_private = (struct hns3_process_private *)
2967             rte_zmalloc_socket("hns3_filter_list",
2968                                sizeof(struct hns3_process_private),
2969                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2970         if (eth_dev->process_private == NULL) {
2971                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2972                 return -ENOMEM;
2973         }
2974
2975         hns3_flow_init(eth_dev);
2976
2977         hns3_set_rxtx_function(eth_dev);
2978         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2979         eth_dev->rx_queue_count = hns3_rx_queue_count;
2980         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2981                 ret = hns3_mp_init_secondary();
2982                 if (ret) {
2983                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2984                                           "process, ret = %d", ret);
2985                         goto err_mp_init_secondary;
2986                 }
2987                 hw->secondary_cnt++;
2988                 hns3_tx_push_init(eth_dev);
2989                 return 0;
2990         }
2991
2992         ret = hns3_mp_init_primary();
2993         if (ret) {
2994                 PMD_INIT_LOG(ERR,
2995                              "Failed to init for primary process, ret = %d",
2996                              ret);
2997                 goto err_mp_init_primary;
2998         }
2999
3000         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
3001         hns->is_vf = true;
3002         hw->data = eth_dev->data;
3003         hns3_parse_devargs(eth_dev);
3004
3005         ret = hns3_reset_init(hw);
3006         if (ret)
3007                 goto err_init_reset;
3008         hw->reset.ops = &hns3vf_reset_ops;
3009
3010         ret = hns3vf_init_vf(eth_dev);
3011         if (ret) {
3012                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
3013                 goto err_init_vf;
3014         }
3015
3016         /* Allocate memory for storing MAC addresses */
3017         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
3018                                                sizeof(struct rte_ether_addr) *
3019                                                HNS3_VF_UC_MACADDR_NUM, 0);
3020         if (eth_dev->data->mac_addrs == NULL) {
3021                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
3022                              "to store MAC addresses",
3023                              sizeof(struct rte_ether_addr) *
3024                              HNS3_VF_UC_MACADDR_NUM);
3025                 ret = -ENOMEM;
3026                 goto err_rte_zmalloc;
3027         }
3028
3029         /*
3030          * The hns3 PF ethdev driver in kernel support setting VF MAC address
3031          * on the host by "ip link set ..." command. To avoid some incorrect
3032          * scenes, for example, hns3 VF PMD driver fails to receive and send
3033          * packets after user configure the MAC address by using the
3034          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
3035          * address strategy as the hns3 kernel ethdev driver in the
3036          * initialization. If user configure a MAC address by the ip command
3037          * for VF device, then hns3 VF PMD driver will start with it, otherwise
3038          * start with a random MAC address in the initialization.
3039          */
3040         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
3041                 rte_eth_random_addr(hw->mac.mac_addr);
3042         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
3043                             &eth_dev->data->mac_addrs[0]);
3044
3045         hw->adapter_state = HNS3_NIC_INITIALIZED;
3046
3047         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
3048                             SCHEDULE_PENDING) {
3049                 hns3_err(hw, "Reschedule reset service after dev_init");
3050                 hns3_schedule_reset(hns);
3051         } else {
3052                 /* IMP will wait ready flag before reset */
3053                 hns3_notify_reset_ready(hw, false);
3054         }
3055         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
3056                           eth_dev);
3057         return 0;
3058
3059 err_rte_zmalloc:
3060         hns3vf_uninit_vf(eth_dev);
3061
3062 err_init_vf:
3063         rte_free(hw->reset.wait_data);
3064
3065 err_init_reset:
3066         hns3_mp_uninit_primary();
3067
3068 err_mp_init_primary:
3069 err_mp_init_secondary:
3070         eth_dev->dev_ops = NULL;
3071         eth_dev->rx_pkt_burst = NULL;
3072         eth_dev->rx_descriptor_status = NULL;
3073         eth_dev->tx_pkt_burst = NULL;
3074         eth_dev->tx_pkt_prepare = NULL;
3075         eth_dev->tx_descriptor_status = NULL;
3076         rte_free(eth_dev->process_private);
3077         eth_dev->process_private = NULL;
3078
3079         return ret;
3080 }
3081
3082 static int
3083 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
3084 {
3085         struct hns3_adapter *hns = eth_dev->data->dev_private;
3086         struct hns3_hw *hw = &hns->hw;
3087
3088         PMD_INIT_FUNC_TRACE();
3089
3090         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3091                 rte_free(eth_dev->process_private);
3092                 eth_dev->process_private = NULL;
3093                 return 0;
3094         }
3095
3096         if (hw->adapter_state < HNS3_NIC_CLOSING)
3097                 hns3vf_dev_close(eth_dev);
3098
3099         hw->adapter_state = HNS3_NIC_REMOVED;
3100         return 0;
3101 }
3102
3103 static int
3104 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3105                      struct rte_pci_device *pci_dev)
3106 {
3107         return rte_eth_dev_pci_generic_probe(pci_dev,
3108                                              sizeof(struct hns3_adapter),
3109                                              hns3vf_dev_init);
3110 }
3111
3112 static int
3113 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
3114 {
3115         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
3116 }
3117
3118 static const struct rte_pci_id pci_id_hns3vf_map[] = {
3119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
3120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
3121         { .vendor_id = 0, }, /* sentinel */
3122 };
3123
3124 static struct rte_pci_driver rte_hns3vf_pmd = {
3125         .id_table = pci_id_hns3vf_map,
3126         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3127         .probe = eth_hns3vf_pci_probe,
3128         .remove = eth_hns3vf_pci_remove,
3129 };
3130
3131 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
3132 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
3133 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
3134 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
3135                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
3136                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
3137                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");