1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
5 #include <linux/pci_regs.h>
7 #include <ethdev_pci.h>
12 #include "hns3_ethdev.h"
13 #include "hns3_logs.h"
14 #include "hns3_rxtx.h"
15 #include "hns3_regs.h"
16 #include "hns3_intr.h"
20 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */
21 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */
23 #define HNS3VF_RESET_WAIT_MS 20
24 #define HNS3VF_RESET_WAIT_CNT 2000
26 /* Reset related Registers */
27 #define HNS3_GLOBAL_RESET_BIT 0
28 #define HNS3_CORE_RESET_BIT 1
29 #define HNS3_IMP_RESET_BIT 2
30 #define HNS3_FUN_RST_ING_B 0
32 enum hns3vf_evt_cause {
33 HNS3VF_VECTOR0_EVENT_RST,
34 HNS3VF_VECTOR0_EVENT_MBX,
35 HNS3VF_VECTOR0_EVENT_OTHER,
38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
44 struct rte_ether_addr *mac_addr);
45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
46 struct rte_ether_addr *mac_addr);
47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
48 __rte_unused int wait_to_complete);
50 /* set PCI bus mastering */
52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
57 ret = rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND);
59 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
65 /* set the master bit */
66 reg |= PCI_COMMAND_MASTER;
68 reg &= ~(PCI_COMMAND_MASTER);
70 return rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND);
74 * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
75 * @cap: the capability
77 * Return the address of the given capability within the PCI capability list.
80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
82 #define MAX_PCIE_CAPABILITY 48
89 ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
91 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
95 if (!(status & PCI_STATUS_CAP_LIST))
98 ttl = MAX_PCIE_CAPABILITY;
99 ret = rte_pci_read_config(device, &pos, sizeof(pos),
100 PCI_CAPABILITY_LIST);
102 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
103 PCI_CAPABILITY_LIST);
107 while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
108 ret = rte_pci_read_config(device, &id, sizeof(id),
109 (pos + PCI_CAP_LIST_ID));
111 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
112 (pos + PCI_CAP_LIST_ID));
122 ret = rte_pci_read_config(device, &pos, sizeof(pos),
123 (pos + PCI_CAP_LIST_NEXT));
125 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
126 (pos + PCI_CAP_LIST_NEXT));
134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
140 pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
142 ret = rte_pci_read_config(device, &control, sizeof(control),
143 (pos + PCI_MSIX_FLAGS));
145 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
146 (pos + PCI_MSIX_FLAGS));
151 control |= PCI_MSIX_FLAGS_ENABLE;
153 control &= ~PCI_MSIX_FLAGS_ENABLE;
154 ret = rte_pci_write_config(device, &control, sizeof(control),
155 (pos + PCI_MSIX_FLAGS));
157 PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
158 (pos + PCI_MSIX_FLAGS));
169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
171 /* mac address was checked by upper level interface */
172 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
175 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
176 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
177 RTE_ETHER_ADDR_LEN, false, NULL, 0);
179 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
181 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
190 /* mac address was checked by upper level interface */
191 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
194 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
195 HNS3_MBX_MAC_VLAN_UC_REMOVE,
196 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
199 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
201 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
208 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
209 struct rte_ether_addr *mac_addr)
211 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
212 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
213 struct rte_ether_addr *old_addr;
214 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
215 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
219 * It has been guaranteed that input parameter named mac_addr is valid
220 * address in the rte layer of DPDK framework.
222 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
223 rte_spinlock_lock(&hw->lock);
224 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
225 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
228 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
229 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
230 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
233 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
234 * driver. When user has configured a MAC address for VF device
235 * by "ip link set ..." command based on the PF device, the hns3
236 * PF kernel ethdev driver does not allow VF driver to request
237 * reconfiguring a different default MAC address, and return
238 * -EPREM to VF driver through mailbox.
241 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
243 hns3_warn(hw, "Has permanet mac addr(%s) for vf",
246 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
248 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
253 rte_ether_addr_copy(mac_addr,
254 (struct rte_ether_addr *)hw->mac.mac_addr);
255 rte_spinlock_unlock(&hw->lock);
261 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
262 struct rte_ether_addr *mac_addr)
264 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
267 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
268 HNS3_MBX_MAC_VLAN_MC_ADD,
269 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
272 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
274 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
282 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
283 struct rte_ether_addr *mac_addr)
285 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
288 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
289 HNS3_MBX_MAC_VLAN_MC_REMOVE,
290 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
293 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
295 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
303 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
304 bool en_uc_pmc, bool en_mc_pmc)
306 struct hns3_mbx_vf_to_pf_cmd *req;
307 struct hns3_cmd_desc desc;
310 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
313 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
314 * so there are some features for promiscuous/allmulticast mode in hns3
315 * VF PMD driver as below:
316 * 1. The promiscuous/allmulticast mode can be configured successfully
317 * only based on the trusted VF device. If based on the non trusted
318 * VF device, configuring promiscuous/allmulticast mode will fail.
319 * The hns3 VF device can be confiruged as trusted device by hns3 PF
320 * kernel ethdev driver on the host by the following command:
321 * "ip link set <eth num> vf <vf id> turst on"
322 * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
323 * driver can receive the ingress and outgoing traffic. In the words,
324 * all the ingress packets, all the packets sent from the PF and
325 * other VFs on the same physical port.
326 * 3. Note: Because of the hardware constraints, By default vlan filter
327 * is enabled and couldn't be turned off based on VF device, so vlan
328 * filter is still effective even in promiscuous mode. If upper
329 * applications don't call rte_eth_dev_vlan_filter API function to
330 * set vlan based on VF device, hns3 VF PMD driver will can't receive
331 * the packets with vlan tag in promiscuoue mode.
333 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
334 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
335 req->msg[1] = en_bc_pmc ? 1 : 0;
336 req->msg[2] = en_uc_pmc ? 1 : 0;
337 req->msg[3] = en_mc_pmc ? 1 : 0;
338 req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
340 ret = hns3_cmd_send(hw, &desc, 1);
342 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
348 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
350 struct hns3_adapter *hns = dev->data->dev_private;
351 struct hns3_hw *hw = &hns->hw;
354 ret = hns3vf_set_promisc_mode(hw, true, true, true);
356 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
362 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
364 bool allmulti = dev->data->all_multicast ? true : false;
365 struct hns3_adapter *hns = dev->data->dev_private;
366 struct hns3_hw *hw = &hns->hw;
369 ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
371 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
377 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
379 struct hns3_adapter *hns = dev->data->dev_private;
380 struct hns3_hw *hw = &hns->hw;
383 if (dev->data->promiscuous)
386 ret = hns3vf_set_promisc_mode(hw, true, false, true);
388 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
394 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
396 struct hns3_adapter *hns = dev->data->dev_private;
397 struct hns3_hw *hw = &hns->hw;
400 if (dev->data->promiscuous)
403 ret = hns3vf_set_promisc_mode(hw, true, false, false);
405 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
411 hns3vf_restore_promisc(struct hns3_adapter *hns)
413 struct hns3_hw *hw = &hns->hw;
414 bool allmulti = hw->data->all_multicast ? true : false;
416 if (hw->data->promiscuous)
417 return hns3vf_set_promisc_mode(hw, true, true, true);
419 return hns3vf_set_promisc_mode(hw, true, false, allmulti);
423 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
424 bool mmap, enum hns3_ring_type queue_type,
427 struct hns3_vf_bind_vector_msg bind_msg;
432 memset(&bind_msg, 0, sizeof(bind_msg));
433 code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
434 HNS3_MBX_UNMAP_RING_TO_VECTOR;
435 bind_msg.vector_id = vector_id;
437 if (queue_type == HNS3_RING_TYPE_RX)
438 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
440 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
442 bind_msg.param[0].ring_type = queue_type;
443 bind_msg.ring_num = 1;
444 bind_msg.param[0].tqp_index = queue_id;
445 op_str = mmap ? "Map" : "Unmap";
446 ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
447 sizeof(bind_msg), false, NULL, 0);
449 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
450 op_str, queue_id, bind_msg.vector_id, ret);
456 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
463 * In hns3 network engine, vector 0 is always the misc interrupt of this
464 * function, vector 1~N can be used respectively for the queues of the
465 * function. Tx and Rx queues with the same number share the interrupt
466 * vector. In the initialization clearing the all hardware mapping
467 * relationship configurations between queues and interrupt vectors is
468 * needed, so some error caused by the residual configurations, such as
469 * the unexpected Tx interrupt, can be avoid.
471 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
472 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
473 vec = vec - 1; /* the last interrupt is reserved */
474 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
475 for (i = 0; i < hw->intr_tqps_num; i++) {
477 * Set gap limiter/rate limiter/quanity limiter algorithm
478 * configuration for interrupt coalesce of queue's interrupt.
480 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
481 HNS3_TQP_INTR_GL_DEFAULT);
482 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
483 HNS3_TQP_INTR_GL_DEFAULT);
484 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
486 * QL(quantity limiter) is not used currently, just set 0 to
489 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
491 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
492 HNS3_RING_TYPE_TX, i);
494 PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
495 "vector: %u, ret=%d", i, vec, ret);
499 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
500 HNS3_RING_TYPE_RX, i);
502 PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
503 "vector: %u, ret=%d", i, vec, ret);
512 hns3vf_dev_configure(struct rte_eth_dev *dev)
514 struct hns3_adapter *hns = dev->data->dev_private;
515 struct hns3_hw *hw = &hns->hw;
516 struct rte_eth_conf *conf = &dev->data->dev_conf;
517 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
518 uint16_t nb_rx_q = dev->data->nb_rx_queues;
519 uint16_t nb_tx_q = dev->data->nb_tx_queues;
520 struct rte_eth_rss_conf rss_conf;
524 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
527 * Some versions of hardware network engine does not support
528 * individually enable/disable/reset the Tx or Rx queue. These devices
529 * must enable/disable/reset Tx and Rx queues at the same time. When the
530 * numbers of Tx queues allocated by upper applications are not equal to
531 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
532 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
533 * work as usual. But these fake queues are imperceptible, and can not
534 * be used by upper applications.
536 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
538 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
539 hw->cfg_max_queues = 0;
543 hw->adapter_state = HNS3_NIC_CONFIGURING;
544 if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
545 hns3_err(hw, "setting link speed/duplex not supported");
550 /* When RSS is not configured, redirect the packet queue 0 */
551 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
552 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
553 hw->rss_dis_flag = false;
554 rss_conf = conf->rx_adv_conf.rss_conf;
555 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
560 ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
564 ret = hns3vf_dev_configure_vlan(dev);
568 /* config hardware GRO */
569 gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
570 ret = hns3_config_gro(hw, gro_en);
574 hns3_init_rx_ptype_tble(dev);
576 hw->adapter_state = HNS3_NIC_CONFIGURED;
580 hw->cfg_max_queues = 0;
581 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
582 hw->adapter_state = HNS3_NIC_INITIALIZED;
588 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
592 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
593 sizeof(mtu), true, NULL, 0);
595 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
601 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
603 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
604 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
608 * The hns3 PF/VF devices on the same port share the hardware MTU
609 * configuration. Currently, we send mailbox to inform hns3 PF kernel
610 * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
611 * driver, there is no need to stop the port for hns3 VF device, and the
612 * MTU value issued by hns3 VF PMD driver must be less than or equal to
615 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
616 hns3_err(hw, "Failed to set mtu during resetting");
621 * when Rx of scattered packets is off, we have some possibility of
622 * using vector Rx process function or simple Rx functions in hns3 PMD
623 * driver. If the input MTU is increased and the maximum length of
624 * received packets is greater than the length of a buffer for Rx
625 * packet, the hardware network engine needs to use multiple BDs and
626 * buffers to store these packets. This will cause problems when still
627 * using vector Rx process function or simple Rx function to receiving
628 * packets. So, when Rx of scattered packets is off and device is
629 * started, it is not permitted to increase MTU so that the maximum
630 * length of Rx packets is greater than Rx buffer length.
632 if (dev->data->dev_started && !dev->data->scattered_rx &&
633 frame_size > hw->rx_buf_len) {
634 hns3_err(hw, "failed to set mtu because current is "
635 "not scattered rx mode");
639 rte_spinlock_lock(&hw->lock);
640 ret = hns3vf_config_mtu(hw, mtu);
642 rte_spinlock_unlock(&hw->lock);
645 rte_spinlock_unlock(&hw->lock);
651 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
653 struct hns3_adapter *hns = eth_dev->data->dev_private;
654 struct hns3_hw *hw = &hns->hw;
655 uint16_t q_num = hw->tqps_num;
658 * In interrupt mode, 'max_rx_queues' is set based on the number of
659 * MSI-X interrupt resources of the hardware.
661 if (hw->data->dev_conf.intr_conf.rxq == 1)
662 q_num = hw->intr_tqps_num;
664 info->max_rx_queues = q_num;
665 info->max_tx_queues = hw->tqps_num;
666 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
667 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
668 info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
669 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
670 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
672 info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
673 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
674 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
675 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
676 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
677 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
678 RTE_ETH_RX_OFFLOAD_SCATTER |
679 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
680 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
681 RTE_ETH_RX_OFFLOAD_RSS_HASH |
682 RTE_ETH_RX_OFFLOAD_TCP_LRO);
683 info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
684 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
685 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
686 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
687 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
688 RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
689 RTE_ETH_TX_OFFLOAD_TCP_TSO |
690 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
691 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
692 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
693 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
694 hns3_txvlan_cap_get(hw));
696 if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
697 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
699 if (hns3_dev_get_support(hw, INDEP_TXRX))
700 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
701 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
702 info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
704 info->rx_desc_lim = (struct rte_eth_desc_lim) {
705 .nb_max = HNS3_MAX_RING_DESC,
706 .nb_min = HNS3_MIN_RING_DESC,
707 .nb_align = HNS3_ALIGN_RING_DESC,
710 info->tx_desc_lim = (struct rte_eth_desc_lim) {
711 .nb_max = HNS3_MAX_RING_DESC,
712 .nb_min = HNS3_MIN_RING_DESC,
713 .nb_align = HNS3_ALIGN_RING_DESC,
714 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
715 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
718 info->default_rxconf = (struct rte_eth_rxconf) {
719 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
721 * If there are no available Rx buffer descriptors, incoming
722 * packets are always dropped by hardware based on hns3 network
728 info->default_txconf = (struct rte_eth_txconf) {
729 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
733 info->reta_size = hw->rss_ind_tbl_size;
734 info->hash_key_size = HNS3_RSS_KEY_SIZE;
735 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
737 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
738 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
739 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
740 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
741 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
742 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
748 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
750 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
754 hns3vf_disable_irq0(struct hns3_hw *hw)
756 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
760 hns3vf_enable_irq0(struct hns3_hw *hw)
762 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
765 static enum hns3vf_evt_cause
766 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
768 struct hns3_hw *hw = &hns->hw;
769 enum hns3vf_evt_cause ret;
770 uint32_t cmdq_stat_reg;
771 uint32_t rst_ing_reg;
774 /* Fetch the events from their corresponding regs */
775 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
776 if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
777 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
778 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
779 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
780 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
781 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
782 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
783 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
785 hw->reset.stats.global_cnt++;
786 hns3_warn(hw, "Global reset detected, clear reset status");
788 hns3_schedule_delayed_reset(hns);
789 hns3_warn(hw, "Global reset detected, don't clear reset status");
792 ret = HNS3VF_VECTOR0_EVENT_RST;
796 /* Check for vector0 mailbox(=CMDQ RX) event source */
797 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
798 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
799 ret = HNS3VF_VECTOR0_EVENT_MBX;
804 ret = HNS3VF_VECTOR0_EVENT_OTHER;
812 hns3vf_interrupt_handler(void *param)
814 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
815 struct hns3_adapter *hns = dev->data->dev_private;
816 struct hns3_hw *hw = &hns->hw;
817 enum hns3vf_evt_cause event_cause;
820 /* Disable interrupt */
821 hns3vf_disable_irq0(hw);
823 /* Read out interrupt causes */
824 event_cause = hns3vf_check_event_cause(hns, &clearval);
825 /* Clear interrupt causes */
826 hns3vf_clear_event_cause(hw, clearval);
828 switch (event_cause) {
829 case HNS3VF_VECTOR0_EVENT_RST:
830 hns3_schedule_reset(hns);
832 case HNS3VF_VECTOR0_EVENT_MBX:
833 hns3_dev_handle_mbx_msg(hw);
839 /* Enable interrupt */
840 hns3vf_enable_irq0(hw);
844 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
846 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
847 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
848 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
849 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
853 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
855 struct hns3_dev_specs_0_cmd *req0;
857 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
859 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
860 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
861 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
862 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
866 hns3vf_check_dev_specifications(struct hns3_hw *hw)
868 if (hw->rss_ind_tbl_size == 0 ||
869 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
870 hns3_warn(hw, "the size of hash lookup table configured (%u)"
871 " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
872 HNS3_RSS_IND_TBL_SIZE_MAX);
880 hns3vf_query_dev_specifications(struct hns3_hw *hw)
882 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
886 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
887 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
889 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
891 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
893 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
897 hns3vf_parse_dev_specifications(hw, desc);
899 return hns3vf_check_dev_specifications(hw);
903 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
905 uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
906 HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
907 uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
908 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
910 if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
911 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
912 __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
916 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
918 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS 500
920 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
921 int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
922 uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
923 uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
924 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
926 __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
929 (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
932 while (remain_ms > 0) {
933 rte_delay_ms(HNS3_POLL_RESPONE_MS);
934 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
935 HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
941 * When exit above loop, the pf_push_lsc_cap could be one of the three
942 * state: unknown (means pf not ack), not_supported, supported.
943 * Here config it as 'not_supported' when it's 'unknown' state.
945 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
946 __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
948 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
949 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
950 hns3_info(hw, "detect PF support push link status change!");
953 * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
954 * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
955 * the RTE_ETH_DEV_INTR_LSC capability.
957 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
962 hns3vf_get_capability(struct hns3_hw *hw)
964 struct rte_pci_device *pci_dev;
965 struct rte_eth_dev *eth_dev;
969 eth_dev = &rte_eth_devices[hw->data->port_id];
970 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
972 /* Get PCI revision id */
973 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
974 HNS3_PCI_REVISION_ID);
975 if (ret != HNS3_PCI_REVISION_ID_LEN) {
976 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
980 hw->revision = revision;
982 if (revision < PCI_REVISION_ID_HIP09_A) {
983 hns3vf_set_default_dev_specifications(hw);
984 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
985 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
986 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
987 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
988 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
989 hw->rss_info.ipv6_sctp_offload_supported = false;
990 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
994 ret = hns3vf_query_dev_specifications(hw);
997 "failed to query dev specifications, ret = %d",
1002 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1003 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1004 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1005 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1006 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1007 hw->rss_info.ipv6_sctp_offload_supported = true;
1008 hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1014 hns3vf_check_tqp_info(struct hns3_hw *hw)
1016 if (hw->tqps_num == 0) {
1017 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1021 if (hw->rss_size_max == 0) {
1022 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1026 hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1032 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1037 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1038 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1039 true, &resp_msg, sizeof(resp_msg));
1041 if (ret == -ETIME) {
1043 * Getting current port based VLAN state from PF driver
1044 * will not affect VF driver's basic function. Because
1045 * the VF driver relies on hns3 PF kernel ether driver,
1046 * to avoid introducing compatibility issues with older
1047 * version of PF driver, no failure will be returned
1048 * when the return value is ETIME. This return value has
1049 * the following scenarios:
1050 * 1) Firmware didn't return the results in time
1051 * 2) the result return by firmware is timeout
1052 * 3) the older version of kernel side PF driver does
1053 * not support this mailbox message.
1054 * For scenarios 1 and 2, it is most likely that a
1055 * hardware error has occurred, or a hardware reset has
1056 * occurred. In this case, these errors will be caught
1057 * by other functions.
1059 PMD_INIT_LOG(WARNING,
1060 "failed to get PVID state for timeout, maybe "
1061 "kernel side PF driver doesn't support this "
1062 "mailbox message, or firmware didn't respond.");
1063 resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1065 PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1070 hw->port_base_vlan_cfg.state = resp_msg ?
1071 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1076 hns3vf_get_queue_info(struct hns3_hw *hw)
1078 #define HNS3VF_TQPS_RSS_INFO_LEN 6
1079 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1082 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1083 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1085 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1089 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1090 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1092 return hns3vf_check_tqp_info(hw);
1096 hns3vf_get_queue_depth(struct hns3_hw *hw)
1098 #define HNS3VF_TQPS_DEPTH_INFO_LEN 4
1099 uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1102 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1103 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1105 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1110 memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1111 memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1117 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
1119 if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
1120 hns3_set_bit(hw->capability,
1121 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
1125 hns3vf_get_num_tc(struct hns3_hw *hw)
1130 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1131 if (hw->hw_tc_map & BIT(i))
1138 hns3vf_get_basic_info(struct hns3_hw *hw)
1140 uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
1141 struct hns3_basic_info *basic_info;
1144 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
1145 true, resp_msg, sizeof(resp_msg));
1147 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
1152 basic_info = (struct hns3_basic_info *)resp_msg;
1153 hw->hw_tc_map = basic_info->hw_tc_map;
1154 hw->num_tc = hns3vf_get_num_tc(hw);
1155 hw->pf_vf_if_version = basic_info->pf_vf_if_version;
1156 hns3vf_update_caps(hw, basic_info->caps);
1162 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1164 uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1167 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1168 true, host_mac, RTE_ETHER_ADDR_LEN);
1170 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1174 memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1180 hns3vf_get_configuration(struct hns3_hw *hw)
1184 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1185 hw->rss_dis_flag = false;
1187 /* Get device capability */
1188 ret = hns3vf_get_capability(hw);
1190 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1194 hns3vf_get_push_lsc_cap(hw);
1196 /* Get basic info from PF */
1197 ret = hns3vf_get_basic_info(hw);
1201 /* Get queue configuration from PF */
1202 ret = hns3vf_get_queue_info(hw);
1206 /* Get queue depth info from PF */
1207 ret = hns3vf_get_queue_depth(hw);
1211 /* Get user defined VF MAC addr from PF */
1212 ret = hns3vf_get_host_mac_addr(hw);
1216 return hns3vf_get_port_base_vlan_filter_state(hw);
1220 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1223 struct hns3_hw *hw = &hns->hw;
1225 return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1229 hns3vf_request_link_info(struct hns3_hw *hw)
1231 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1235 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1238 send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1239 vf->req_link_info_cnt > 0;
1243 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1246 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1250 if (vf->req_link_info_cnt > 0)
1251 vf->req_link_info_cnt--;
1255 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1256 uint32_t link_speed, uint8_t link_duplex)
1258 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1259 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1260 struct hns3_mac *mac = &hw->mac;
1264 * PF kernel driver may push link status when VF driver is in resetting,
1265 * driver will stop polling job in this case, after resetting done
1266 * driver will start polling job again.
1267 * When polling job started, driver will get initial link status by
1268 * sending request to PF kernel driver, then could update link status by
1269 * process PF kernel driver's link status mailbox message.
1271 if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1274 if (hw->adapter_state != HNS3_NIC_STARTED)
1277 mac->link_status = link_status;
1278 mac->link_speed = link_speed;
1279 mac->link_duplex = link_duplex;
1280 ret = hns3vf_dev_link_update(dev, 0);
1281 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1282 hns3_start_report_lse(dev);
1286 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1288 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1289 struct hns3_hw *hw = &hns->hw;
1290 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1291 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1292 uint8_t is_kill = on ? 0 : 1;
1294 msg_data[0] = is_kill;
1295 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1296 memcpy(&msg_data[3], &proto, sizeof(proto));
1298 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1299 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1304 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1306 struct hns3_adapter *hns = dev->data->dev_private;
1307 struct hns3_hw *hw = &hns->hw;
1310 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1312 "vf set vlan id failed during resetting, vlan_id =%u",
1316 rte_spinlock_lock(&hw->lock);
1317 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1318 rte_spinlock_unlock(&hw->lock);
1320 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1327 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1332 if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1335 msg_data = enable ? 1 : 0;
1336 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1337 HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1338 sizeof(msg_data), true, NULL, 0);
1340 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1341 enable ? "enable" : "disable", ret);
1347 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1352 msg_data = enable ? 1 : 0;
1353 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1354 &msg_data, sizeof(msg_data), false, NULL, 0);
1356 hns3_err(hw, "vf %s strip failed, ret = %d.",
1357 enable ? "enable" : "disable", ret);
1363 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1365 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1366 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1367 unsigned int tmp_mask;
1370 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1371 hns3_err(hw, "vf set vlan offload failed during resetting, "
1372 "mask = 0x%x", mask);
1376 tmp_mask = (unsigned int)mask;
1378 if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
1379 rte_spinlock_lock(&hw->lock);
1380 /* Enable or disable VLAN filter */
1381 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1382 ret = hns3vf_en_vlan_filter(hw, true);
1384 ret = hns3vf_en_vlan_filter(hw, false);
1385 rte_spinlock_unlock(&hw->lock);
1390 /* Vlan stripping setting */
1391 if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
1392 rte_spinlock_lock(&hw->lock);
1393 /* Enable or disable VLAN stripping */
1394 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1395 ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1397 ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1398 rte_spinlock_unlock(&hw->lock);
1405 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1407 struct rte_vlan_filter_conf *vfc;
1408 struct hns3_hw *hw = &hns->hw;
1415 vfc = &hw->data->vlan_filter_conf;
1416 for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1417 if (vfc->ids[i] == 0)
1422 * 64 means the num bits of ids, one bit corresponds to
1426 /* count trailing zeroes */
1427 vbit = ~ids & (ids - 1);
1428 /* clear least significant bit set */
1429 ids ^= (ids ^ (ids - 1)) ^ vbit;
1434 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1437 "VF handle vlan table failed, ret =%d, on = %d",
1448 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1450 return hns3vf_handle_all_vlan_table(hns, 0);
1454 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1456 struct hns3_hw *hw = &hns->hw;
1457 struct rte_eth_conf *dev_conf;
1461 dev_conf = &hw->data->dev_conf;
1462 en = dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? true
1464 ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1466 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1472 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1474 struct hns3_adapter *hns = dev->data->dev_private;
1475 struct rte_eth_dev_data *data = dev->data;
1476 struct hns3_hw *hw = &hns->hw;
1479 if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1480 data->dev_conf.txmode.hw_vlan_reject_untagged ||
1481 data->dev_conf.txmode.hw_vlan_insert_pvid) {
1482 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1483 "or hw_vlan_insert_pvid is not support!");
1486 /* Apply vlan offload setting */
1487 ret = hns3vf_vlan_offload_set(dev, RTE_ETH_VLAN_STRIP_MASK |
1488 RTE_ETH_VLAN_FILTER_MASK);
1490 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1496 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1500 msg_data = alive ? 1 : 0;
1501 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1502 sizeof(msg_data), false, NULL, 0);
1506 hns3vf_keep_alive_handler(void *param)
1508 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1509 struct hns3_adapter *hns = eth_dev->data->dev_private;
1510 struct hns3_hw *hw = &hns->hw;
1513 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1516 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1519 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1524 hns3vf_service_handler(void *param)
1526 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1527 struct hns3_adapter *hns = eth_dev->data->dev_private;
1528 struct hns3_hw *hw = &hns->hw;
1531 * The query link status and reset processing are executed in the
1532 * interrupt thread. When the IMP reset occurs, IMP will not respond,
1533 * and the query operation will timeout after 30ms. In the case of
1534 * multiple PF/VFs, each query failure timeout causes the IMP reset
1535 * interrupt to fail to respond within 100ms.
1536 * Before querying the link status, check whether there is a reset
1537 * pending, and if so, abandon the query.
1539 if (!hns3vf_is_reset_pending(hns))
1540 hns3vf_request_link_info(hw);
1542 hns3_warn(hw, "Cancel the query when reset is pending");
1544 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1549 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1551 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT 3
1553 struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1555 if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1556 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1558 __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1560 hns3vf_service_handler(dev);
1564 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1566 struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1568 rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1570 __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1574 hns3_query_vf_resource(struct hns3_hw *hw)
1576 struct hns3_vf_res_cmd *req;
1577 struct hns3_cmd_desc desc;
1581 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1582 ret = hns3_cmd_send(hw, &desc, 1);
1584 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1588 req = (struct hns3_vf_res_cmd *)desc.data;
1589 num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1590 HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1591 if (num_msi < HNS3_MIN_VECTOR_NUM) {
1592 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1593 num_msi, HNS3_MIN_VECTOR_NUM);
1597 hw->num_msi = num_msi;
1603 hns3vf_init_hardware(struct hns3_adapter *hns)
1605 struct hns3_hw *hw = &hns->hw;
1606 uint16_t mtu = hw->data->mtu;
1609 ret = hns3vf_set_promisc_mode(hw, true, false, false);
1613 ret = hns3vf_config_mtu(hw, mtu);
1615 goto err_init_hardware;
1617 ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1619 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1620 goto err_init_hardware;
1623 ret = hns3_config_gro(hw, false);
1625 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1626 goto err_init_hardware;
1630 * In the initialization clearing the all hardware mapping relationship
1631 * configurations between queues and interrupt vectors is needed, so
1632 * some error caused by the residual configurations, such as the
1633 * unexpected interrupt, can be avoid.
1635 ret = hns3vf_init_ring_with_vector(hw);
1637 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1638 goto err_init_hardware;
1644 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1649 hns3vf_clear_vport_list(struct hns3_hw *hw)
1651 return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1652 HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1657 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1659 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1660 struct hns3_adapter *hns = eth_dev->data->dev_private;
1661 struct hns3_hw *hw = &hns->hw;
1664 PMD_INIT_FUNC_TRACE();
1666 /* Get hardware io base address from pcie BAR2 IO space */
1667 hw->io_base = pci_dev->mem_resource[2].addr;
1669 /* Firmware command queue initialize */
1670 ret = hns3_cmd_init_queue(hw);
1672 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1673 goto err_cmd_init_queue;
1676 /* Firmware command initialize */
1677 ret = hns3_cmd_init(hw);
1679 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1683 hns3_tx_push_init(eth_dev);
1685 /* Get VF resource */
1686 ret = hns3_query_vf_resource(hw);
1690 rte_spinlock_init(&hw->mbx_resp.lock);
1692 hns3vf_clear_event_cause(hw, 0);
1694 ret = rte_intr_callback_register(pci_dev->intr_handle,
1695 hns3vf_interrupt_handler, eth_dev);
1697 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1698 goto err_intr_callback_register;
1701 /* Enable interrupt */
1702 rte_intr_enable(pci_dev->intr_handle);
1703 hns3vf_enable_irq0(hw);
1705 /* Get configuration from PF */
1706 ret = hns3vf_get_configuration(hw);
1708 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1709 goto err_get_config;
1712 ret = hns3_tqp_stats_init(hw);
1714 goto err_get_config;
1716 /* Hardware statistics of imissed registers cleared. */
1717 ret = hns3_update_imissed_stats(hw, true);
1719 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1720 goto err_set_tc_queue;
1723 ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1725 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1726 goto err_set_tc_queue;
1729 ret = hns3vf_clear_vport_list(hw);
1731 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1732 goto err_set_tc_queue;
1735 ret = hns3vf_init_hardware(hns);
1737 goto err_set_tc_queue;
1739 hns3_rss_set_default_args(hw);
1741 ret = hns3vf_set_alive(hw, true);
1743 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1744 goto err_set_tc_queue;
1750 hns3_tqp_stats_uninit(hw);
1753 hns3vf_disable_irq0(hw);
1754 rte_intr_disable(pci_dev->intr_handle);
1755 hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1757 err_intr_callback_register:
1759 hns3_cmd_uninit(hw);
1760 hns3_cmd_destroy_queue(hw);
1768 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1770 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1771 struct hns3_adapter *hns = eth_dev->data->dev_private;
1772 struct hns3_hw *hw = &hns->hw;
1774 PMD_INIT_FUNC_TRACE();
1776 hns3_rss_uninit(hns);
1777 (void)hns3_config_gro(hw, false);
1778 (void)hns3vf_set_alive(hw, false);
1779 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1780 hns3_flow_uninit(eth_dev);
1781 hns3_tqp_stats_uninit(hw);
1782 hns3vf_disable_irq0(hw);
1783 rte_intr_disable(pci_dev->intr_handle);
1784 hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1786 hns3_cmd_uninit(hw);
1787 hns3_cmd_destroy_queue(hw);
1792 hns3vf_do_stop(struct hns3_adapter *hns)
1794 struct hns3_hw *hw = &hns->hw;
1797 hw->mac.link_status = RTE_ETH_LINK_DOWN;
1800 * The "hns3vf_do_stop" function will also be called by .stop_service to
1801 * prepare reset. At the time of global or IMP reset, the command cannot
1802 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
1803 * accessed during the reset process. So the mbuf can not be released
1804 * during reset and is required to be released after the reset is
1807 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)
1808 hns3_dev_release_mbufs(hns);
1810 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
1811 hns3_configure_all_mac_addr(hns, true);
1812 ret = hns3_reset_all_tqps(hns);
1814 hns3_err(hw, "failed to reset all queues ret = %d",
1823 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1825 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1826 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1827 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1828 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1829 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1832 if (dev->data->dev_conf.intr_conf.rxq == 0)
1835 /* unmap the ring with vector */
1836 if (rte_intr_allow_others(intr_handle)) {
1837 vec = RTE_INTR_VEC_RXTX_OFFSET;
1838 base = RTE_INTR_VEC_RXTX_OFFSET;
1840 if (rte_intr_dp_is_en(intr_handle)) {
1841 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1842 (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1845 if (vec < base + rte_intr_nb_efd_get(intr_handle)
1850 /* Clean datapath event and queue/vec mapping */
1851 rte_intr_efd_disable(intr_handle);
1853 /* Cleanup vector list */
1854 rte_intr_vec_list_free(intr_handle);
1858 hns3vf_dev_stop(struct rte_eth_dev *dev)
1860 struct hns3_adapter *hns = dev->data->dev_private;
1861 struct hns3_hw *hw = &hns->hw;
1863 PMD_INIT_FUNC_TRACE();
1864 dev->data->dev_started = 0;
1866 hw->adapter_state = HNS3_NIC_STOPPING;
1867 hns3_set_rxtx_function(dev);
1869 /* Disable datapath on secondary process. */
1870 hns3_mp_req_stop_rxtx(dev);
1871 /* Prevent crashes when queues are still in use. */
1872 rte_delay_ms(hw->cfg_max_queues);
1874 rte_spinlock_lock(&hw->lock);
1875 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1877 hns3vf_do_stop(hns);
1878 hns3vf_unmap_rx_interrupt(dev);
1879 hw->adapter_state = HNS3_NIC_CONFIGURED;
1881 hns3_rx_scattered_reset(dev);
1882 hns3vf_stop_poll_job(dev);
1883 hns3_stop_report_lse(dev);
1884 rte_spinlock_unlock(&hw->lock);
1890 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1892 struct hns3_adapter *hns = eth_dev->data->dev_private;
1893 struct hns3_hw *hw = &hns->hw;
1896 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1897 __atomic_fetch_sub(&hw->secondary_cnt, 1, __ATOMIC_RELAXED);
1901 if (hw->adapter_state == HNS3_NIC_STARTED)
1902 ret = hns3vf_dev_stop(eth_dev);
1904 hw->adapter_state = HNS3_NIC_CLOSING;
1905 hns3_reset_abort(hns);
1906 hw->adapter_state = HNS3_NIC_CLOSED;
1907 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1908 hns3_configure_all_mc_mac_addr(hns, true);
1909 hns3vf_remove_all_vlan_table(hns);
1910 hns3vf_uninit_vf(eth_dev);
1911 hns3_free_all_queues(eth_dev);
1912 rte_free(hw->reset.wait_data);
1913 hns3_mp_uninit_primary();
1914 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
1920 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1923 struct hns3_adapter *hns = eth_dev->data->dev_private;
1924 struct hns3_hw *hw = &hns->hw;
1925 uint32_t version = hw->fw_version;
1928 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1929 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1930 HNS3_FW_VERSION_BYTE3_S),
1931 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1932 HNS3_FW_VERSION_BYTE2_S),
1933 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1934 HNS3_FW_VERSION_BYTE1_S),
1935 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1936 HNS3_FW_VERSION_BYTE0_S));
1940 ret += 1; /* add the size of '\0' */
1941 if (fw_size < (size_t)ret)
1948 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1949 __rte_unused int wait_to_complete)
1951 struct hns3_adapter *hns = eth_dev->data->dev_private;
1952 struct hns3_hw *hw = &hns->hw;
1953 struct hns3_mac *mac = &hw->mac;
1954 struct rte_eth_link new_link;
1956 memset(&new_link, 0, sizeof(new_link));
1957 switch (mac->link_speed) {
1958 case RTE_ETH_SPEED_NUM_10M:
1959 case RTE_ETH_SPEED_NUM_100M:
1960 case RTE_ETH_SPEED_NUM_1G:
1961 case RTE_ETH_SPEED_NUM_10G:
1962 case RTE_ETH_SPEED_NUM_25G:
1963 case RTE_ETH_SPEED_NUM_40G:
1964 case RTE_ETH_SPEED_NUM_50G:
1965 case RTE_ETH_SPEED_NUM_100G:
1966 case RTE_ETH_SPEED_NUM_200G:
1967 if (mac->link_status)
1968 new_link.link_speed = mac->link_speed;
1971 if (mac->link_status)
1972 new_link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
1976 if (!mac->link_status)
1977 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
1979 new_link.link_duplex = mac->link_duplex;
1980 new_link.link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
1981 new_link.link_autoneg =
1982 !(eth_dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED);
1984 return rte_eth_linkstatus_set(eth_dev, &new_link);
1988 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1990 struct hns3_hw *hw = &hns->hw;
1991 uint16_t nb_rx_q = hw->data->nb_rx_queues;
1992 uint16_t nb_tx_q = hw->data->nb_tx_queues;
1995 ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
1999 hns3_enable_rxd_adv_layout(hw);
2001 ret = hns3_init_queues(hns, reset_queue);
2003 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2009 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2011 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2012 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2013 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2014 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2015 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2016 uint32_t intr_vector;
2021 * hns3 needs a separate interrupt to be used as event interrupt which
2022 * could not be shared with task queue pair, so KERNEL drivers need
2023 * support multiple interrupt vectors.
2025 if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2026 !rte_intr_cap_multiple(intr_handle))
2029 rte_intr_disable(intr_handle);
2030 intr_vector = hw->used_rx_queues;
2031 /* It creates event fd for each intr vector when MSIX is used */
2032 if (rte_intr_efd_enable(intr_handle, intr_vector))
2035 /* Allocate vector list */
2036 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
2037 hw->used_rx_queues)) {
2038 hns3_err(hw, "Failed to allocate %u rx_queues"
2039 " intr_vec", hw->used_rx_queues);
2041 goto vf_alloc_intr_vec_error;
2044 if (rte_intr_allow_others(intr_handle)) {
2045 vec = RTE_INTR_VEC_RXTX_OFFSET;
2046 base = RTE_INTR_VEC_RXTX_OFFSET;
2049 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2050 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2051 HNS3_RING_TYPE_RX, q_id);
2053 goto vf_bind_vector_error;
2055 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
2056 goto vf_bind_vector_error;
2059 * If there are not enough efds (e.g. not enough interrupt),
2060 * remaining queues will be bond to the last interrupt.
2062 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
2065 rte_intr_enable(intr_handle);
2068 vf_bind_vector_error:
2069 rte_intr_vec_list_free(intr_handle);
2070 vf_alloc_intr_vec_error:
2071 rte_intr_efd_disable(intr_handle);
2076 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2078 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2079 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2080 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2084 if (dev->data->dev_conf.intr_conf.rxq == 0)
2087 if (rte_intr_dp_is_en(intr_handle)) {
2088 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2089 ret = hns3vf_bind_ring_with_vector(hw,
2090 rte_intr_vec_list_index_get(intr_handle,
2092 true, HNS3_RING_TYPE_RX, q_id);
2102 hns3vf_restore_filter(struct rte_eth_dev *dev)
2104 hns3_restore_rss_filter(dev);
2108 hns3vf_dev_start(struct rte_eth_dev *dev)
2110 struct hns3_adapter *hns = dev->data->dev_private;
2111 struct hns3_hw *hw = &hns->hw;
2114 PMD_INIT_FUNC_TRACE();
2115 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2118 rte_spinlock_lock(&hw->lock);
2119 hw->adapter_state = HNS3_NIC_STARTING;
2120 ret = hns3vf_do_start(hns, true);
2122 hw->adapter_state = HNS3_NIC_CONFIGURED;
2123 rte_spinlock_unlock(&hw->lock);
2126 ret = hns3vf_map_rx_interrupt(dev);
2128 goto map_rx_inter_err;
2131 * There are three register used to control the status of a TQP
2132 * (contains a pair of Tx queue and Rx queue) in the new version network
2133 * engine. One is used to control the enabling of Tx queue, the other is
2134 * used to control the enabling of Rx queue, and the last is the master
2135 * switch used to control the enabling of the tqp. The Tx register and
2136 * TQP register must be enabled at the same time to enable a Tx queue.
2137 * The same applies to the Rx queue. For the older network enginem, this
2138 * function only refresh the enabled flag, and it is used to update the
2139 * status of queue in the dpdk framework.
2141 ret = hns3_start_all_txqs(dev);
2143 goto map_rx_inter_err;
2145 ret = hns3_start_all_rxqs(dev);
2147 goto start_all_rxqs_fail;
2149 hw->adapter_state = HNS3_NIC_STARTED;
2150 rte_spinlock_unlock(&hw->lock);
2152 hns3_rx_scattered_calc(dev);
2153 hns3_set_rxtx_function(dev);
2154 hns3_mp_req_start_rxtx(dev);
2156 hns3vf_restore_filter(dev);
2158 /* Enable interrupt of all rx queues before enabling queues */
2159 hns3_dev_all_rx_queue_intr_enable(hw, true);
2160 hns3_start_tqps(hw);
2162 if (dev->data->dev_conf.intr_conf.lsc != 0)
2163 hns3vf_dev_link_update(dev, 0);
2164 hns3vf_start_poll_job(dev);
2168 start_all_rxqs_fail:
2169 hns3_stop_all_txqs(dev);
2171 (void)hns3vf_do_stop(hns);
2172 hw->adapter_state = HNS3_NIC_CONFIGURED;
2173 rte_spinlock_unlock(&hw->lock);
2179 is_vf_reset_done(struct hns3_hw *hw)
2181 #define HNS3_FUN_RST_ING_BITS \
2182 (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2183 BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2184 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2185 BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2189 if (hw->reset.level == HNS3_VF_RESET) {
2190 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2191 if (val & HNS3_VF_RST_ING_BIT)
2194 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2195 if (val & HNS3_FUN_RST_ING_BITS)
2202 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2204 struct hns3_hw *hw = &hns->hw;
2205 enum hns3_reset_level reset;
2208 * According to the protocol of PCIe, FLR to a PF device resets the PF
2209 * state as well as the SR-IOV extended capability including VF Enable
2210 * which means that VFs no longer exist.
2212 * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2213 * is in FLR stage, the register state of VF device is not reliable,
2214 * so register states detection can not be carried out. In this case,
2215 * we just ignore the register states and return false to indicate that
2216 * there are no other reset states that need to be processed by driver.
2218 if (hw->reset.level == HNS3_VF_FULL_RESET)
2221 /* Check the registers to confirm whether there is reset pending */
2222 hns3vf_check_event_cause(hns, NULL);
2223 reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2224 if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2225 hw->reset.level < reset) {
2226 hns3_warn(hw, "High level reset %d is pending", reset);
2233 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2235 struct hns3_hw *hw = &hns->hw;
2236 struct hns3_wait_data *wait_data = hw->reset.wait_data;
2239 if (wait_data->result == HNS3_WAIT_SUCCESS) {
2241 * After vf reset is ready, the PF may not have completed
2242 * the reset processing. The vf sending mbox to PF may fail
2243 * during the pf reset, so it is better to add extra delay.
2245 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2246 hw->reset.level == HNS3_FLR_RESET)
2248 /* Reset retry process, no need to add extra delay. */
2249 if (hw->reset.attempts)
2251 if (wait_data->check_completion == NULL)
2254 wait_data->check_completion = NULL;
2255 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2256 wait_data->count = 1;
2257 wait_data->result = HNS3_WAIT_REQUEST;
2258 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2260 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2262 } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2263 hns3_clock_gettime(&tv);
2264 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2265 tv.tv_sec, tv.tv_usec);
2267 } else if (wait_data->result == HNS3_WAIT_REQUEST)
2270 wait_data->hns = hns;
2271 wait_data->check_completion = is_vf_reset_done;
2272 wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2273 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2274 wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2275 wait_data->count = HNS3VF_RESET_WAIT_CNT;
2276 wait_data->result = HNS3_WAIT_REQUEST;
2277 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2282 hns3vf_prepare_reset(struct hns3_adapter *hns)
2284 struct hns3_hw *hw = &hns->hw;
2287 if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2288 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2293 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2299 hns3vf_stop_service(struct hns3_adapter *hns)
2301 struct hns3_hw *hw = &hns->hw;
2302 struct rte_eth_dev *eth_dev;
2304 eth_dev = &rte_eth_devices[hw->data->port_id];
2305 if (hw->adapter_state == HNS3_NIC_STARTED) {
2307 * Make sure call update link status before hns3vf_stop_poll_job
2308 * because update link status depend on polling job exist.
2310 hns3vf_update_link_status(hw, RTE_ETH_LINK_DOWN, hw->mac.link_speed,
2311 hw->mac.link_duplex);
2312 hns3vf_stop_poll_job(eth_dev);
2314 hw->mac.link_status = RTE_ETH_LINK_DOWN;
2316 hns3_set_rxtx_function(eth_dev);
2318 /* Disable datapath on secondary process. */
2319 hns3_mp_req_stop_rxtx(eth_dev);
2320 rte_delay_ms(hw->cfg_max_queues);
2322 rte_spinlock_lock(&hw->lock);
2323 if (hw->adapter_state == HNS3_NIC_STARTED ||
2324 hw->adapter_state == HNS3_NIC_STOPPING) {
2325 hns3_enable_all_queues(hw, false);
2326 hns3vf_do_stop(hns);
2327 hw->reset.mbuf_deferred_free = true;
2329 hw->reset.mbuf_deferred_free = false;
2332 * It is cumbersome for hardware to pick-and-choose entries for deletion
2333 * from table space. Hence, for function reset software intervention is
2334 * required to delete the entries.
2336 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2337 hns3_configure_all_mc_mac_addr(hns, true);
2338 rte_spinlock_unlock(&hw->lock);
2344 hns3vf_start_service(struct hns3_adapter *hns)
2346 struct hns3_hw *hw = &hns->hw;
2347 struct rte_eth_dev *eth_dev;
2349 eth_dev = &rte_eth_devices[hw->data->port_id];
2350 hns3_set_rxtx_function(eth_dev);
2351 hns3_mp_req_start_rxtx(eth_dev);
2352 if (hw->adapter_state == HNS3_NIC_STARTED) {
2353 hns3vf_start_poll_job(eth_dev);
2355 /* Enable interrupt of all rx queues before enabling queues */
2356 hns3_dev_all_rx_queue_intr_enable(hw, true);
2358 * Enable state of each rxq and txq will be recovered after
2359 * reset, so we need to restore them before enable all tqps;
2361 hns3_restore_tqp_enable_state(hw);
2363 * When finished the initialization, enable queues to receive
2364 * and transmit packets.
2366 hns3_enable_all_queues(hw, true);
2373 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2375 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2376 struct rte_ether_addr *hw_mac;
2380 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2381 * on the host by "ip link set ..." command. If the hns3 PF kernel
2382 * ethdev driver sets the MAC address for VF device after the
2383 * initialization of the related VF device, the PF driver will notify
2384 * VF driver to reset VF device to make the new MAC address effective
2385 * immediately. The hns3 VF PMD driver should check whether the MAC
2386 * address has been changed by the PF kernel ethdev driver, if changed
2387 * VF driver should configure hardware using the new MAC address in the
2388 * recovering hardware configuration stage of the reset process.
2390 ret = hns3vf_get_host_mac_addr(hw);
2394 hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2395 ret = rte_is_zero_ether_addr(hw_mac);
2397 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2399 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2401 rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2402 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2403 &hw->data->mac_addrs[0]);
2404 hns3_warn(hw, "Default MAC address has been changed to:"
2405 " %s by the host PF kernel ethdev driver",
2414 hns3vf_restore_conf(struct hns3_adapter *hns)
2416 struct hns3_hw *hw = &hns->hw;
2419 ret = hns3vf_check_default_mac_change(hw);
2423 ret = hns3_configure_all_mac_addr(hns, false);
2427 ret = hns3_configure_all_mc_mac_addr(hns, false);
2431 ret = hns3vf_restore_promisc(hns);
2433 goto err_vlan_table;
2435 ret = hns3vf_restore_vlan_conf(hns);
2437 goto err_vlan_table;
2439 ret = hns3vf_get_port_base_vlan_filter_state(hw);
2441 goto err_vlan_table;
2443 ret = hns3vf_restore_rx_interrupt(hw);
2445 goto err_vlan_table;
2447 ret = hns3_restore_gro_conf(hw);
2449 goto err_vlan_table;
2451 if (hw->adapter_state == HNS3_NIC_STARTED) {
2452 ret = hns3vf_do_start(hns, false);
2454 goto err_vlan_table;
2455 hns3_info(hw, "hns3vf dev restart successful!");
2456 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2457 hw->adapter_state = HNS3_NIC_CONFIGURED;
2459 ret = hns3vf_set_alive(hw, true);
2461 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2462 goto err_vlan_table;
2468 hns3_configure_all_mc_mac_addr(hns, true);
2470 hns3_configure_all_mac_addr(hns, true);
2474 static enum hns3_reset_level
2475 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2477 enum hns3_reset_level reset_level;
2479 /* return the highest priority reset level amongst all */
2480 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2481 reset_level = HNS3_VF_RESET;
2482 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2483 reset_level = HNS3_VF_FULL_RESET;
2484 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2485 reset_level = HNS3_VF_PF_FUNC_RESET;
2486 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2487 reset_level = HNS3_VF_FUNC_RESET;
2488 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2489 reset_level = HNS3_FLR_RESET;
2491 reset_level = HNS3_NONE_RESET;
2493 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2494 return HNS3_NONE_RESET;
2500 hns3vf_reset_service(void *param)
2502 struct hns3_adapter *hns = (struct hns3_adapter *)param;
2503 struct hns3_hw *hw = &hns->hw;
2504 enum hns3_reset_level reset_level;
2505 struct timeval tv_delta;
2506 struct timeval tv_start;
2511 * The interrupt is not triggered within the delay time.
2512 * The interrupt may have been lost. It is necessary to handle
2513 * the interrupt to recover from the error.
2515 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2516 SCHEDULE_DEFERRED) {
2517 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2519 hns3_err(hw, "Handling interrupts in delayed tasks");
2520 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2521 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2522 if (reset_level == HNS3_NONE_RESET) {
2523 hns3_err(hw, "No reset level is set, try global reset");
2524 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2527 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2530 * Hardware reset has been notified, we now have to poll & check if
2531 * hardware has actually completed the reset sequence.
2533 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2534 if (reset_level != HNS3_NONE_RESET) {
2535 hns3_clock_gettime(&tv_start);
2536 hns3_reset_process(hns, reset_level);
2537 hns3_clock_gettime(&tv);
2538 timersub(&tv, &tv_start, &tv_delta);
2539 msec = hns3_clock_calctime_ms(&tv_delta);
2540 if (msec > HNS3_RESET_PROCESS_MS)
2541 hns3_err(hw, "%d handle long time delta %" PRIu64
2542 " ms time=%ld.%.6ld",
2543 hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2548 hns3vf_reinit_dev(struct hns3_adapter *hns)
2550 struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2551 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2552 struct hns3_hw *hw = &hns->hw;
2555 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2556 rte_intr_disable(pci_dev->intr_handle);
2557 ret = hns3vf_set_bus_master(pci_dev, true);
2559 hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2564 /* Firmware command initialize */
2565 ret = hns3_cmd_init(hw);
2567 hns3_err(hw, "Failed to init cmd: %d", ret);
2571 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2573 * UIO enables msix by writing the pcie configuration space
2574 * vfio_pci enables msix in rte_intr_enable.
2576 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2577 pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2578 if (hns3vf_enable_msix(pci_dev, true))
2579 hns3_err(hw, "Failed to enable msix");
2582 rte_intr_enable(pci_dev->intr_handle);
2585 ret = hns3_reset_all_tqps(hns);
2587 hns3_err(hw, "Failed to reset all queues: %d", ret);
2591 ret = hns3vf_init_hardware(hns);
2593 hns3_err(hw, "Failed to init hardware: %d", ret);
2600 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2601 .dev_configure = hns3vf_dev_configure,
2602 .dev_start = hns3vf_dev_start,
2603 .dev_stop = hns3vf_dev_stop,
2604 .dev_close = hns3vf_dev_close,
2605 .mtu_set = hns3vf_dev_mtu_set,
2606 .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2607 .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2608 .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2609 .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2610 .stats_get = hns3_stats_get,
2611 .stats_reset = hns3_stats_reset,
2612 .xstats_get = hns3_dev_xstats_get,
2613 .xstats_get_names = hns3_dev_xstats_get_names,
2614 .xstats_reset = hns3_dev_xstats_reset,
2615 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
2616 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2617 .dev_infos_get = hns3vf_dev_infos_get,
2618 .fw_version_get = hns3vf_fw_version_get,
2619 .rx_queue_setup = hns3_rx_queue_setup,
2620 .tx_queue_setup = hns3_tx_queue_setup,
2621 .rx_queue_release = hns3_dev_rx_queue_release,
2622 .tx_queue_release = hns3_dev_tx_queue_release,
2623 .rx_queue_start = hns3_dev_rx_queue_start,
2624 .rx_queue_stop = hns3_dev_rx_queue_stop,
2625 .tx_queue_start = hns3_dev_tx_queue_start,
2626 .tx_queue_stop = hns3_dev_tx_queue_stop,
2627 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
2628 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
2629 .rxq_info_get = hns3_rxq_info_get,
2630 .txq_info_get = hns3_txq_info_get,
2631 .rx_burst_mode_get = hns3_rx_burst_mode_get,
2632 .tx_burst_mode_get = hns3_tx_burst_mode_get,
2633 .mac_addr_add = hns3_add_mac_addr,
2634 .mac_addr_remove = hns3_remove_mac_addr,
2635 .mac_addr_set = hns3vf_set_default_mac_addr,
2636 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
2637 .link_update = hns3vf_dev_link_update,
2638 .rss_hash_update = hns3_dev_rss_hash_update,
2639 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
2640 .reta_update = hns3_dev_rss_reta_update,
2641 .reta_query = hns3_dev_rss_reta_query,
2642 .flow_ops_get = hns3_dev_flow_ops_get,
2643 .vlan_filter_set = hns3vf_vlan_filter_set,
2644 .vlan_offload_set = hns3vf_vlan_offload_set,
2645 .get_reg = hns3_get_regs,
2646 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2647 .tx_done_cleanup = hns3_tx_done_cleanup,
2650 static const struct hns3_reset_ops hns3vf_reset_ops = {
2651 .reset_service = hns3vf_reset_service,
2652 .stop_service = hns3vf_stop_service,
2653 .prepare_reset = hns3vf_prepare_reset,
2654 .wait_hardware_ready = hns3vf_wait_hardware_ready,
2655 .reinit_dev = hns3vf_reinit_dev,
2656 .restore_conf = hns3vf_restore_conf,
2657 .start_service = hns3vf_start_service,
2661 hns3vf_init_hw_ops(struct hns3_hw *hw)
2663 hw->ops.add_mc_mac_addr = hns3vf_add_mc_mac_addr;
2664 hw->ops.del_mc_mac_addr = hns3vf_remove_mc_mac_addr;
2665 hw->ops.add_uc_mac_addr = hns3vf_add_uc_mac_addr;
2666 hw->ops.del_uc_mac_addr = hns3vf_remove_uc_mac_addr;
2670 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2672 struct hns3_adapter *hns = eth_dev->data->dev_private;
2673 struct hns3_hw *hw = &hns->hw;
2676 PMD_INIT_FUNC_TRACE();
2678 hns3_flow_init(eth_dev);
2680 hns3_set_rxtx_function(eth_dev);
2681 eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2682 eth_dev->rx_queue_count = hns3_rx_queue_count;
2683 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2684 ret = hns3_mp_init_secondary();
2686 PMD_INIT_LOG(ERR, "Failed to init for secondary "
2687 "process, ret = %d", ret);
2688 goto err_mp_init_secondary;
2690 __atomic_fetch_add(&hw->secondary_cnt, 1, __ATOMIC_RELAXED);
2691 process_data.eth_dev_cnt++;
2692 hns3_tx_push_init(eth_dev);
2696 ret = hns3_mp_init_primary();
2699 "Failed to init for primary process, ret = %d",
2701 goto err_mp_init_primary;
2703 process_data.eth_dev_cnt++;
2705 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2707 hw->data = eth_dev->data;
2708 hns3_parse_devargs(eth_dev);
2710 ret = hns3_reset_init(hw);
2712 goto err_init_reset;
2713 hw->reset.ops = &hns3vf_reset_ops;
2715 hns3vf_init_hw_ops(hw);
2716 ret = hns3vf_init_vf(eth_dev);
2718 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2722 /* Allocate memory for storing MAC addresses */
2723 eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2724 sizeof(struct rte_ether_addr) *
2725 HNS3_VF_UC_MACADDR_NUM, 0);
2726 if (eth_dev->data->mac_addrs == NULL) {
2727 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2728 "to store MAC addresses",
2729 sizeof(struct rte_ether_addr) *
2730 HNS3_VF_UC_MACADDR_NUM);
2732 goto err_rte_zmalloc;
2736 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2737 * on the host by "ip link set ..." command. To avoid some incorrect
2738 * scenes, for example, hns3 VF PMD driver fails to receive and send
2739 * packets after user configure the MAC address by using the
2740 * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2741 * address strategy as the hns3 kernel ethdev driver in the
2742 * initialization. If user configure a MAC address by the ip command
2743 * for VF device, then hns3 VF PMD driver will start with it, otherwise
2744 * start with a random MAC address in the initialization.
2746 if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2747 rte_eth_random_addr(hw->mac.mac_addr);
2748 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2749 ð_dev->data->mac_addrs[0]);
2751 hw->adapter_state = HNS3_NIC_INITIALIZED;
2753 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2755 hns3_err(hw, "Reschedule reset service after dev_init");
2756 hns3_schedule_reset(hns);
2758 /* IMP will wait ready flag before reset */
2759 hns3_notify_reset_ready(hw, false);
2761 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2766 hns3vf_uninit_vf(eth_dev);
2769 rte_free(hw->reset.wait_data);
2772 hns3_mp_uninit_primary();
2774 err_mp_init_primary:
2775 err_mp_init_secondary:
2776 eth_dev->dev_ops = NULL;
2777 eth_dev->rx_pkt_burst = NULL;
2778 eth_dev->rx_descriptor_status = NULL;
2779 eth_dev->tx_pkt_burst = NULL;
2780 eth_dev->tx_pkt_prepare = NULL;
2781 eth_dev->tx_descriptor_status = NULL;
2787 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2789 struct hns3_adapter *hns = eth_dev->data->dev_private;
2790 struct hns3_hw *hw = &hns->hw;
2792 PMD_INIT_FUNC_TRACE();
2794 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2795 __atomic_fetch_sub(&hw->secondary_cnt, 1, __ATOMIC_RELAXED);
2799 if (hw->adapter_state < HNS3_NIC_CLOSING)
2800 hns3vf_dev_close(eth_dev);
2802 hw->adapter_state = HNS3_NIC_REMOVED;
2807 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2808 struct rte_pci_device *pci_dev)
2810 return rte_eth_dev_pci_generic_probe(pci_dev,
2811 sizeof(struct hns3_adapter),
2816 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2818 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2821 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2822 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2823 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2824 { .vendor_id = 0, }, /* sentinel */
2827 static struct rte_pci_driver rte_hns3vf_pmd = {
2828 .id_table = pci_id_hns3vf_map,
2829 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2830 .probe = eth_hns3vf_pci_probe,
2831 .remove = eth_hns3vf_pci_remove,
2834 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2835 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2836 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
2837 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
2838 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
2839 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
2840 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
2841 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16_t> ");