drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static void
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71
  72         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  73
  74         if (op)
  75                 /* set the master bit */
  76                 reg |= PCI_COMMAND_MASTER;
  77         else
  78                 reg &= ~(PCI_COMMAND_MASTER);
  79
  80         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  81 }
  82
  83 /**
  84  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  85  * @cap: the capability
  86  *
  87  * Return the address of the given capability within the PCI capability list.
  88  */
  89 static int
  90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  91 {
  92 #define MAX_PCIE_CAPABILITY 48
  93         uint16_t status;
  94         uint8_t pos;
  95         uint8_t id;
  96         int ttl;
  97
  98         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  99         if (!(status & PCI_STATUS_CAP_LIST))
 100                 return 0;
 101
 102         ttl = MAX_PCIE_CAPABILITY;
 103         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 rte_pci_read_config(device, &id, sizeof(id),
 106                                     (pos + PCI_CAP_LIST_ID));
 107
 108                 if (id == 0xFF)
 109                         break;
 110
 111                 if (id == cap)
 112                         return (int)pos;
 113
 114                 rte_pci_read_config(device, &pos, sizeof(pos),
 115                                     (pos + PCI_CAP_LIST_NEXT));
 116         }
 117         return 0;
 118 }
 119
 120 static int
 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 122 {
 123         uint16_t control;
 124         int pos;
 125
 126         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 127         if (pos) {
 128                 rte_pci_read_config(device, &control, sizeof(control),
 129                                     (pos + PCI_MSIX_FLAGS));
 130                 if (op)
 131                         control |= PCI_MSIX_FLAGS_ENABLE;
 132                 else
 133                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 134                 rte_pci_write_config(device, &control, sizeof(control),
 135                                      (pos + PCI_MSIX_FLAGS));
 136                 return 0;
 137         }
 138         return -ENXIO;
 139 }
 140
 141 static int
 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 143 {
 144         /* mac address was checked by upper level interface */
 145         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 146         int ret;
 147
 148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 149                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 150                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 155                          mac_str, ret);
 156         }
 157         return ret;
 158 }
 159
 160 static int
 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 162 {
 163         /* mac address was checked by upper level interface */
 164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 165         int ret;
 166
 167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 168                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 169                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 170                                 false, NULL, 0);
 171         if (ret) {
 172                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 173                                       mac_addr);
 174                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 175                          mac_str, ret);
 176         }
 177         return ret;
 178 }
 179
 180 static int
 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 182 {
 183         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 184         struct rte_ether_addr *addr;
 185         int ret;
 186         int i;
 187
 188         for (i = 0; i < hw->mc_addrs_num; i++) {
 189                 addr = &hw->mc_addrs[i];
 190                 /* Check if there are duplicate addresses */
 191                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 192                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 193                                               addr);
 194                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 195                                  "(%s) is added by the set_mc_mac_addr_list "
 196                                  "API", mac_str);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 202         if (ret) {
 203                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 204                                       mac_addr);
 205                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 206                          mac_str, ret);
 207         }
 208         return ret;
 209 }
 210
 211 static int
 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 213                     __rte_unused uint32_t idx,
 214                     __rte_unused uint32_t pool)
 215 {
 216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 218         int ret;
 219
 220         rte_spinlock_lock(&hw->lock);
 221
 222         /*
 223          * In hns3 network engine adding UC and MC mac address with different
 224          * commands with firmware. We need to determine whether the input
 225          * address is a UC or a MC address to call different commands.
 226          * By the way, it is recommended calling the API function named
 227          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 228          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 229          * may affect the specifications of UC mac addresses.
 230          */
 231         if (rte_is_multicast_ether_addr(mac_addr))
 232                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 233         else
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235
 236         rte_spinlock_unlock(&hw->lock);
 237         if (ret) {
 238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 239                                       mac_addr);
 240                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 241                          ret);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 249 {
 250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 251         /* index will be checked by upper level rte interface */
 252         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 260         else
 261                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 268                          mac_str, ret);
 269         }
 270 }
 271
 272 static int
 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                             struct rte_ether_addr *mac_addr)
 275 {
 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         struct rte_ether_addr *old_addr;
 279         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         /*
 284          * It has been guaranteed that input parameter named mac_addr is valid
 285          * address in the rte layer of DPDK framework.
 286          */
 287         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 288         rte_spinlock_lock(&hw->lock);
 289         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 290         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 291                RTE_ETHER_ADDR_LEN);
 292
 293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 294                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 295                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 296         if (ret) {
 297                 /*
 298                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 299                  * driver. When user has configured a MAC address for VF device
 300                  * by "ip link set ..." command based on the PF device, the hns3
 301                  * PF kernel ethdev driver does not allow VF driver to request
 302                  * reconfiguring a different default MAC address, and return
 303                  * -EPREM to VF driver through mailbox.
 304                  */
 305                 if (ret == -EPERM) {
 306                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 307                                               old_addr);
 308                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 309                                   mac_str);
 310                 } else {
 311                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 312                                               mac_addr);
 313                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 314                                  mac_str, ret);
 315                 }
 316         }
 317
 318         rte_ether_addr_copy(mac_addr,
 319                             (struct rte_ether_addr *)hw->mac.mac_addr);
 320         rte_spinlock_unlock(&hw->lock);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 327 {
 328         struct hns3_hw *hw = &hns->hw;
 329         struct rte_ether_addr *addr;
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int err = 0;
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 336                 addr = &hw->data->mac_addrs[i];
 337                 if (rte_is_zero_ether_addr(addr))
 338                         continue;
 339                 if (rte_is_multicast_ether_addr(addr))
 340                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 341                               hns3vf_add_mc_mac_addr(hw, addr);
 342                 else
 343                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 344                               hns3vf_add_uc_mac_addr(hw, addr);
 345
 346                 if (ret) {
 347                         err = ret;
 348                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 349                                               addr);
 350                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 351                                  "ret = %d.", del ? "remove" : "restore",
 352                                  mac_str, i, ret);
 353                 }
 354         }
 355         return err;
 356 }
 357
 358 static int
 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 360                        struct rte_ether_addr *mac_addr)
 361 {
 362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 363         int ret;
 364
 365         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 366                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 367                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 368                                 NULL, 0);
 369         if (ret) {
 370                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 371                                       mac_addr);
 372                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 373                          mac_str, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int
 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 381                           struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 402                              struct rte_ether_addr *mc_addr_set,
 403                              uint32_t nb_mc_addr)
 404 {
 405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 406         struct rte_ether_addr *addr;
 407         uint32_t i;
 408         uint32_t j;
 409
 410         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 411                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 412                          "invalid. valid range: 0~%d",
 413                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 414                 return -EINVAL;
 415         }
 416
 417         /* Check if input mac addresses are valid */
 418         for (i = 0; i < nb_mc_addr; i++) {
 419                 addr = &mc_addr_set[i];
 420                 if (!rte_is_multicast_ether_addr(addr)) {
 421                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 422                                               addr);
 423                         hns3_err(hw,
 424                                  "failed to set mc mac addr, addr(%s) invalid.",
 425                                  mac_str);
 426                         return -EINVAL;
 427                 }
 428
 429                 /* Check if there are duplicate addresses */
 430                 for (j = i + 1; j < nb_mc_addr; j++) {
 431                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 432                                 rte_ether_format_addr(mac_str,
 433                                                       RTE_ETHER_ADDR_FMT_SIZE,
 434                                                       addr);
 435                                 hns3_err(hw, "failed to set mc mac addr, "
 436                                          "addrs invalid. two same addrs(%s).",
 437                                          mac_str);
 438                                 return -EINVAL;
 439                         }
 440                 }
 441
 442                 /*
 443                  * Check if there are duplicate addresses between mac_addrs
 444                  * and mc_addr_set
 445                  */
 446                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 447                         if (rte_is_same_ether_addr(addr,
 448                                                    &hw->data->mac_addrs[j])) {
 449                                 rte_ether_format_addr(mac_str,
 450                                                       RTE_ETHER_ADDR_FMT_SIZE,
 451                                                       addr);
 452                                 hns3_err(hw, "failed to set mc mac addr, "
 453                                          "addrs invalid. addrs(%s) has already "
 454                                          "configured in mac_addr add API",
 455                                          mac_str);
 456                                 return -EINVAL;
 457                         }
 458                 }
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int
 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 466                             struct rte_ether_addr *mc_addr_set,
 467                             uint32_t nb_mc_addr)
 468 {
 469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 470         struct rte_ether_addr *addr;
 471         int cur_addr_num;
 472         int set_addr_num;
 473         int num;
 474         int ret;
 475         int i;
 476
 477         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 478         if (ret)
 479                 return ret;
 480
 481         rte_spinlock_lock(&hw->lock);
 482         cur_addr_num = hw->mc_addrs_num;
 483         for (i = 0; i < cur_addr_num; i++) {
 484                 num = cur_addr_num - i - 1;
 485                 addr = &hw->mc_addrs[num];
 486                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 487                 if (ret) {
 488                         rte_spinlock_unlock(&hw->lock);
 489                         return ret;
 490                 }
 491
 492                 hw->mc_addrs_num--;
 493         }
 494
 495         set_addr_num = (int)nb_mc_addr;
 496         for (i = 0; i < set_addr_num; i++) {
 497                 addr = &mc_addr_set[i];
 498                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 499                 if (ret) {
 500                         rte_spinlock_unlock(&hw->lock);
 501                         return ret;
 502                 }
 503
 504                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 505                 hw->mc_addrs_num++;
 506         }
 507         rte_spinlock_unlock(&hw->lock);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 514 {
 515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 516         struct hns3_hw *hw = &hns->hw;
 517         struct rte_ether_addr *addr;
 518         int err = 0;
 519         int ret;
 520         int i;
 521
 522         for (i = 0; i < hw->mc_addrs_num; i++) {
 523                 addr = &hw->mc_addrs[i];
 524                 if (!rte_is_multicast_ether_addr(addr))
 525                         continue;
 526                 if (del)
 527                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 528                 else
 529                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 530                 if (ret) {
 531                         err = ret;
 532                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 533                                               addr);
 534                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 535                                  del ? "Remove" : "Restore", mac_str, ret);
 536                 }
 537         }
 538         return err;
 539 }
 540
 541 static int
 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 543                         bool en_uc_pmc, bool en_mc_pmc)
 544 {
 545         struct hns3_mbx_vf_to_pf_cmd *req;
 546         struct hns3_cmd_desc desc;
 547         int ret;
 548
 549         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 550
 551         /*
 552          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 553          * so there are some features for promiscuous/allmulticast mode in hns3
 554          * VF PMD driver as below:
 555          * 1. The promiscuous/allmulticast mode can be configured successfully
 556          *    only based on the trusted VF device. If based on the non trusted
 557          *    VF device, configuring promiscuous/allmulticast mode will fail.
 558          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 559          *    kernel ethdev driver on the host by the following command:
 560          *      "ip link set <eth num> vf <vf id> turst on"
 561          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 562          *    driver can receive the ingress and outgoing traffic. In the words,
 563          *    all the ingress packets, all the packets sent from the PF and
 564          *    other VFs on the same physical port.
 565          * 3. Note: Because of the hardware constraints, By default vlan filter
 566          *    is enabled and couldn't be turned off based on VF device, so vlan
 567          *    filter is still effective even in promiscuous mode. If upper
 568          *    applications don't call rte_eth_dev_vlan_filter API function to
 569          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 570          *    the packets with vlan tag in promiscuoue mode.
 571          */
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 573         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 574         req->msg[1] = en_bc_pmc ? 1 : 0;
 575         req->msg[2] = en_uc_pmc ? 1 : 0;
 576         req->msg[3] = en_mc_pmc ? 1 : 0;
 577
 578         ret = hns3_cmd_send(hw, &desc, 1);
 579         if (ret)
 580                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 587 {
 588         struct hns3_adapter *hns = dev->data->dev_private;
 589         struct hns3_hw *hw = &hns->hw;
 590         int ret;
 591
 592         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 593         if (ret)
 594                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 595                         ret);
 596         return ret;
 597 }
 598
 599 static int
 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         bool allmulti = dev->data->all_multicast ? true : false;
 603         struct hns3_adapter *hns = dev->data->dev_private;
 604         struct hns3_hw *hw = &hns->hw;
 605         int ret;
 606
 607         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 608         if (ret)
 609                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 610                         ret);
 611         return ret;
 612 }
 613
 614 static int
 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 616 {
 617         struct hns3_adapter *hns = dev->data->dev_private;
 618         struct hns3_hw *hw = &hns->hw;
 619         int ret;
 620
 621         if (dev->data->promiscuous)
 622                 return 0;
 623
 624         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 625         if (ret)
 626                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 627                         ret);
 628         return ret;
 629 }
 630
 631 static int
 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 633 {
 634         struct hns3_adapter *hns = dev->data->dev_private;
 635         struct hns3_hw *hw = &hns->hw;
 636         int ret;
 637
 638         if (dev->data->promiscuous)
 639                 return 0;
 640
 641         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 642         if (ret)
 643                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 644                         ret);
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_restore_promisc(struct hns3_adapter *hns)
 650 {
 651         struct hns3_hw *hw = &hns->hw;
 652         bool allmulti = hw->data->all_multicast ? true : false;
 653
 654         if (hw->data->promiscuous)
 655                 return hns3vf_set_promisc_mode(hw, true, true, true);
 656
 657         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 658 }
 659
 660 static int
 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 662                              bool mmap, enum hns3_ring_type queue_type,
 663                              uint16_t queue_id)
 664 {
 665         struct hns3_vf_bind_vector_msg bind_msg;
 666         const char *op_str;
 667         uint16_t code;
 668         int ret;
 669
 670         memset(&bind_msg, 0, sizeof(bind_msg));
 671         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 672                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 673         bind_msg.vector_id = vector_id;
 674
 675         if (queue_type == HNS3_RING_TYPE_RX)
 676                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 677         else
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 679
 680         bind_msg.param[0].ring_type = queue_type;
 681         bind_msg.ring_num = 1;
 682         bind_msg.param[0].tqp_index = queue_id;
 683         op_str = mmap ? "Map" : "Unmap";
 684         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 685                                 sizeof(bind_msg), false, NULL, 0);
 686         if (ret)
 687                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 688                          op_str, queue_id, bind_msg.vector_id, ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 695 {
 696         uint8_t vec;
 697         int ret;
 698         int i;
 699
 700         /*
 701          * In hns3 network engine, vector 0 is always the misc interrupt of this
 702          * function, vector 1~N can be used respectively for the queues of the
 703          * function. Tx and Rx queues with the same number share the interrupt
 704          * vector. In the initialization clearing the all hardware mapping
 705          * relationship configurations between queues and interrupt vectors is
 706          * needed, so some error caused by the residual configurations, such as
 707          * the unexpected Tx interrupt, can be avoid. Because of the hardware
 708          * constraints in hns3 hardware engine, we have to implement clearing
 709          * the mapping relationship configurations by binding all queues to the
 710          * last interrupt vector and reserving the last interrupt vector. This
 711          * method results in a decrease of the maximum queues when upper
 712          * applications call the rte_eth_dev_configure API function to enable
 713          * Rx interrupt.
 714          */
 715         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 716         /* vec - 1: the last interrupt is reserved */
 717         hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;
 718         for (i = 0; i < hw->intr_tqps_num; i++) {
 719                 /*
 720                  * Set gap limiter and rate limiter configuration of queue's
 721                  * interrupt.
 722                  */
 723                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 724                                        HNS3_TQP_INTR_GL_DEFAULT);
 725                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 726                                        HNS3_TQP_INTR_GL_DEFAULT);
 727                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 728
 729                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 730                                                    HNS3_RING_TYPE_TX, i);
 731                 if (ret) {
 732                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 733                                           "vector: %d, ret=%d", i, vec, ret);
 734                         return ret;
 735                 }
 736
 737                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 738                                                    HNS3_RING_TYPE_RX, i);
 739                 if (ret) {
 740                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 741                                           "vector: %d, ret=%d", i, vec, ret);
 742                         return ret;
 743                 }
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int
 750 hns3vf_dev_configure(struct rte_eth_dev *dev)
 751 {
 752         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 753         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 754         struct rte_eth_conf *conf = &dev->data->dev_conf;
 755         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 756         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 757         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 758         struct rte_eth_rss_conf rss_conf;
 759         uint16_t mtu;
 760         bool gro_en;
 761         int ret;
 762
 763         /*
 764          * Hardware does not support individually enable/disable/reset the Tx or
 765          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 766          * and Rx queues at the same time. When the numbers of Tx queues
 767          * allocated by upper applications are not equal to the numbers of Rx
 768          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 769          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 770          * these fake queues are imperceptible, and can not be used by upper
 771          * applications.
 772          */
 773         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 774         if (ret) {
 775                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 776                 return ret;
 777         }
 778
 779         hw->adapter_state = HNS3_NIC_CONFIGURING;
 780         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 781                 hns3_err(hw, "setting link speed/duplex not supported");
 782                 ret = -EINVAL;
 783                 goto cfg_err;
 784         }
 785
 786         /* When RSS is not configured, redirect the packet queue 0 */
 787         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 788                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 789                 rss_conf = conf->rx_adv_conf.rss_conf;
 790                 if (rss_conf.rss_key == NULL) {
 791                         rss_conf.rss_key = rss_cfg->key;
 792                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 793                 }
 794
 795                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 796                 if (ret)
 797                         goto cfg_err;
 798         }
 799
 800         /*
 801          * If jumbo frames are enabled, MTU needs to be refreshed
 802          * according to the maximum RX packet length.
 803          */
 804         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 805                 /*
 806                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 807                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 808                  * can safely assign to "uint16_t" type variable.
 809                  */
 810                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 811                 ret = hns3vf_dev_mtu_set(dev, mtu);
 812                 if (ret)
 813                         goto cfg_err;
 814                 dev->data->mtu = mtu;
 815         }
 816
 817         ret = hns3vf_dev_configure_vlan(dev);
 818         if (ret)
 819                 goto cfg_err;
 820
 821         /* config hardware GRO */
 822         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 823         ret = hns3_config_gro(hw, gro_en);
 824         if (ret)
 825                 goto cfg_err;
 826
 827         hw->adapter_state = HNS3_NIC_CONFIGURED;
 828         return 0;
 829
 830 cfg_err:
 831         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 832         hw->adapter_state = HNS3_NIC_INITIALIZED;
 833
 834         return ret;
 835 }
 836
 837 static int
 838 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 839 {
 840         int ret;
 841
 842         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 843                                 sizeof(mtu), true, NULL, 0);
 844         if (ret)
 845                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 846
 847         return ret;
 848 }
 849
 850 static int
 851 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 852 {
 853         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 854         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 855         int ret;
 856
 857         /*
 858          * The hns3 PF/VF devices on the same port share the hardware MTU
 859          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 860          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 861          * driver, there is no need to stop the port for hns3 VF device, and the
 862          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 863          * PF's MTU.
 864          */
 865         if (rte_atomic16_read(&hw->reset.resetting)) {
 866                 hns3_err(hw, "Failed to set mtu during resetting");
 867                 return -EIO;
 868         }
 869
 870         rte_spinlock_lock(&hw->lock);
 871         ret = hns3vf_config_mtu(hw, mtu);
 872         if (ret) {
 873                 rte_spinlock_unlock(&hw->lock);
 874                 return ret;
 875         }
 876         if (frame_size > RTE_ETHER_MAX_LEN)
 877                 dev->data->dev_conf.rxmode.offloads |=
 878                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 879         else
 880                 dev->data->dev_conf.rxmode.offloads &=
 881                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 882         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 883         rte_spinlock_unlock(&hw->lock);
 884
 885         return 0;
 886 }
 887
 888 static int
 889 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 890 {
 891         struct hns3_adapter *hns = eth_dev->data->dev_private;
 892         struct hns3_hw *hw = &hns->hw;
 893         uint16_t q_num = hw->tqps_num;
 894
 895         /*
 896          * In interrupt mode, 'max_rx_queues' is set based on the number of
 897          * MSI-X interrupt resources of the hardware.
 898          */
 899         if (hw->data->dev_conf.intr_conf.rxq == 1)
 900                 q_num = hw->intr_tqps_num;
 901
 902         info->max_rx_queues = q_num;
 903         info->max_tx_queues = hw->tqps_num;
 904         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 905         info->min_rx_bufsize = hw->rx_buf_len;
 906         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 907         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 908         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 909
 910         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 911                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 912                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 913                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 914                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 915                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 916                                  DEV_RX_OFFLOAD_KEEP_CRC |
 917                                  DEV_RX_OFFLOAD_SCATTER |
 918                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 919                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 920                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 921                                  DEV_RX_OFFLOAD_RSS_HASH |
 922                                  DEV_RX_OFFLOAD_TCP_LRO);
 923         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 924         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 925                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 926                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 927                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 928                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 929                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 930                                  DEV_TX_OFFLOAD_TCP_TSO |
 931                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 932                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 933                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 934                                  info->tx_queue_offload_capa |
 935                                  hns3_txvlan_cap_get(hw));
 936
 937         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 938                 .nb_max = HNS3_MAX_RING_DESC,
 939                 .nb_min = HNS3_MIN_RING_DESC,
 940                 .nb_align = HNS3_ALIGN_RING_DESC,
 941         };
 942
 943         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 944                 .nb_max = HNS3_MAX_RING_DESC,
 945                 .nb_min = HNS3_MIN_RING_DESC,
 946                 .nb_align = HNS3_ALIGN_RING_DESC,
 947                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 948                 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT,
 949         };
 950
 951         info->vmdq_queue_num = 0;
 952
 953         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 954         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 955         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 956         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 957         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 958
 959         return 0;
 960 }
 961
 962 static void
 963 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 964 {
 965         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 966 }
 967
 968 static void
 969 hns3vf_disable_irq0(struct hns3_hw *hw)
 970 {
 971         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 972 }
 973
 974 static void
 975 hns3vf_enable_irq0(struct hns3_hw *hw)
 976 {
 977         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 978 }
 979
 980 static enum hns3vf_evt_cause
 981 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 982 {
 983         struct hns3_hw *hw = &hns->hw;
 984         enum hns3vf_evt_cause ret;
 985         uint32_t cmdq_stat_reg;
 986         uint32_t rst_ing_reg;
 987         uint32_t val;
 988
 989         /* Fetch the events from their corresponding regs */
 990         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 991
 992         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 993                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 994                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 995                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 996                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 997                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 998                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 999                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1000                 if (clearval) {
1001                         hw->reset.stats.global_cnt++;
1002                         hns3_warn(hw, "Global reset detected, clear reset status");
1003                 } else {
1004                         hns3_schedule_delayed_reset(hns);
1005                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1006                 }
1007
1008                 ret = HNS3VF_VECTOR0_EVENT_RST;
1009                 goto out;
1010         }
1011
1012         /* Check for vector0 mailbox(=CMDQ RX) event source */
1013         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1014                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1015                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1016                 goto out;
1017         }
1018
1019         val = 0;
1020         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1021 out:
1022         if (clearval)
1023                 *clearval = val;
1024         return ret;
1025 }
1026
1027 static void
1028 hns3vf_interrupt_handler(void *param)
1029 {
1030         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1031         struct hns3_adapter *hns = dev->data->dev_private;
1032         struct hns3_hw *hw = &hns->hw;
1033         enum hns3vf_evt_cause event_cause;
1034         uint32_t clearval;
1035
1036         if (hw->irq_thread_id == 0)
1037                 hw->irq_thread_id = pthread_self();
1038
1039         /* Disable interrupt */
1040         hns3vf_disable_irq0(hw);
1041
1042         /* Read out interrupt causes */
1043         event_cause = hns3vf_check_event_cause(hns, &clearval);
1044
1045         switch (event_cause) {
1046         case HNS3VF_VECTOR0_EVENT_RST:
1047                 hns3_schedule_reset(hns);
1048                 break;
1049         case HNS3VF_VECTOR0_EVENT_MBX:
1050                 hns3_dev_handle_mbx_msg(hw);
1051                 break;
1052         default:
1053                 break;
1054         }
1055
1056         /* Clear interrupt causes */
1057         hns3vf_clear_event_cause(hw, clearval);
1058
1059         /* Enable interrupt */
1060         hns3vf_enable_irq0(hw);
1061 }
1062
1063 static int
1064 hns3vf_get_capability(struct hns3_hw *hw)
1065 {
1066         struct rte_pci_device *pci_dev;
1067         struct rte_eth_dev *eth_dev;
1068         uint8_t revision;
1069         int ret;
1070
1071         eth_dev = &rte_eth_devices[hw->data->port_id];
1072         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1073
1074         /* Get PCI revision id */
1075         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1076                                   HNS3_PCI_REVISION_ID);
1077         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1078                 PMD_INIT_LOG(ERR, "failed to read pci revision id: %d", ret);
1079                 return -EIO;
1080         }
1081         hw->revision = revision;
1082
1083         return 0;
1084 }
1085
1086 static int
1087 hns3vf_check_tqp_info(struct hns3_hw *hw)
1088 {
1089         uint16_t tqps_num;
1090
1091         tqps_num = hw->tqps_num;
1092         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1093                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1094                                   "range: 1~%d",
1095                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1096                 return -EINVAL;
1097         }
1098
1099         if (hw->rx_buf_len == 0)
1100                 hw->rx_buf_len = HNS3_DEFAULT_RX_BUF_LEN;
1101         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1102
1103         return 0;
1104 }
1105 static int
1106 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1107 {
1108         uint8_t resp_msg;
1109         int ret;
1110
1111         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1112                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1113                                 true, &resp_msg, sizeof(resp_msg));
1114         if (ret) {
1115                 if (ret == -ETIME) {
1116                         /*
1117                          * Getting current port based VLAN state from PF driver
1118                          * will not affect VF driver's basic function. Because
1119                          * the VF driver relies on hns3 PF kernel ether driver,
1120                          * to avoid introducing compatibility issues with older
1121                          * version of PF driver, no failure will be returned
1122                          * when the return value is ETIME. This return value has
1123                          * the following scenarios:
1124                          * 1) Firmware didn't return the results in time
1125                          * 2) the result return by firmware is timeout
1126                          * 3) the older version of kernel side PF driver does
1127                          *    not support this mailbox message.
1128                          * For scenarios 1 and 2, it is most likely that a
1129                          * hardware error has occurred, or a hardware reset has
1130                          * occurred. In this case, these errors will be caught
1131                          * by other functions.
1132                          */
1133                         PMD_INIT_LOG(WARNING,
1134                                 "failed to get PVID state for timeout, maybe "
1135                                 "kernel side PF driver doesn't support this "
1136                                 "mailbox message, or firmware didn't respond.");
1137                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1138                 } else {
1139                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1140                                 " ret = %d", ret);
1141                         return ret;
1142                 }
1143         }
1144         hw->port_base_vlan_cfg.state = resp_msg ?
1145                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1146         return 0;
1147 }
1148
1149 static int
1150 hns3vf_get_queue_info(struct hns3_hw *hw)
1151 {
1152 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1153         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1154         int ret;
1155
1156         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1157                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1158         if (ret) {
1159                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1160                 return ret;
1161         }
1162
1163         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1164         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1165         memcpy(&hw->rx_buf_len, &resp_msg[4], sizeof(uint16_t));
1166
1167         return hns3vf_check_tqp_info(hw);
1168 }
1169
1170 static int
1171 hns3vf_get_queue_depth(struct hns3_hw *hw)
1172 {
1173 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1174         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1175         int ret;
1176
1177         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1178                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1179         if (ret) {
1180                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1181                              ret);
1182                 return ret;
1183         }
1184
1185         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1186         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1187
1188         return 0;
1189 }
1190
1191 static int
1192 hns3vf_get_tc_info(struct hns3_hw *hw)
1193 {
1194         uint8_t resp_msg;
1195         int ret;
1196
1197         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1198                                 true, &resp_msg, sizeof(resp_msg));
1199         if (ret) {
1200                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1201                          ret);
1202                 return ret;
1203         }
1204
1205         hw->hw_tc_map = resp_msg;
1206
1207         return 0;
1208 }
1209
1210 static int
1211 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1212 {
1213         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1214         int ret;
1215
1216         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1217                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1218         if (ret) {
1219                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1220                 return ret;
1221         }
1222
1223         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1224
1225         return 0;
1226 }
1227
1228 static int
1229 hns3vf_get_configuration(struct hns3_hw *hw)
1230 {
1231         int ret;
1232
1233         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1234         hw->rss_dis_flag = false;
1235
1236         /* Get device capability */
1237         ret = hns3vf_get_capability(hw);
1238         if (ret) {
1239                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1240                 return ret;
1241         }
1242
1243         /* Get queue configuration from PF */
1244         ret = hns3vf_get_queue_info(hw);
1245         if (ret)
1246                 return ret;
1247
1248         /* Get queue depth info from PF */
1249         ret = hns3vf_get_queue_depth(hw);
1250         if (ret)
1251                 return ret;
1252
1253         /* Get user defined VF MAC addr from PF */
1254         ret = hns3vf_get_host_mac_addr(hw);
1255         if (ret)
1256                 return ret;
1257
1258         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1259         if (ret)
1260                 return ret;
1261
1262         /* Get tc configuration from PF */
1263         return hns3vf_get_tc_info(hw);
1264 }
1265
1266 static int
1267 hns3vf_set_tc_info(struct hns3_adapter *hns)
1268 {
1269         struct hns3_hw *hw = &hns->hw;
1270         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1271         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1272         uint8_t i;
1273
1274         hw->num_tc = 0;
1275         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1276                 if (hw->hw_tc_map & BIT(i))
1277                         hw->num_tc++;
1278
1279         if (nb_rx_q < hw->num_tc) {
1280                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1281                          nb_rx_q, hw->num_tc);
1282                 return -EINVAL;
1283         }
1284
1285         if (nb_tx_q < hw->num_tc) {
1286                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1287                          nb_tx_q, hw->num_tc);
1288                 return -EINVAL;
1289         }
1290
1291         hns3_set_rss_size(hw, nb_rx_q);
1292         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1293
1294         return 0;
1295 }
1296
1297 static void
1298 hns3vf_request_link_info(struct hns3_hw *hw)
1299 {
1300         uint8_t resp_msg;
1301         int ret;
1302
1303         if (rte_atomic16_read(&hw->reset.resetting))
1304                 return;
1305         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1306                                 &resp_msg, sizeof(resp_msg));
1307         if (ret)
1308                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1309 }
1310
1311 static int
1312 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1313 {
1314 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1315         struct hns3_hw *hw = &hns->hw;
1316         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1317         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1318         uint8_t is_kill = on ? 0 : 1;
1319
1320         msg_data[0] = is_kill;
1321         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1322         memcpy(&msg_data[3], &proto, sizeof(proto));
1323
1324         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1325                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1326                                  0);
1327 }
1328
1329 static int
1330 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1331 {
1332         struct hns3_adapter *hns = dev->data->dev_private;
1333         struct hns3_hw *hw = &hns->hw;
1334         int ret;
1335
1336         if (rte_atomic16_read(&hw->reset.resetting)) {
1337                 hns3_err(hw,
1338                          "vf set vlan id failed during resetting, vlan_id =%u",
1339                          vlan_id);
1340                 return -EIO;
1341         }
1342         rte_spinlock_lock(&hw->lock);
1343         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1344         rte_spinlock_unlock(&hw->lock);
1345         if (ret)
1346                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1347                          vlan_id, ret);
1348
1349         return ret;
1350 }
1351
1352 static int
1353 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1354 {
1355         uint8_t msg_data;
1356         int ret;
1357
1358         msg_data = enable ? 1 : 0;
1359         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1360                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1361         if (ret)
1362                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1363
1364         return ret;
1365 }
1366
1367 static int
1368 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1369 {
1370         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1371         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1372         unsigned int tmp_mask;
1373         int ret = 0;
1374
1375         if (rte_atomic16_read(&hw->reset.resetting)) {
1376                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1377                              "mask = 0x%x", mask);
1378                 return -EIO;
1379         }
1380
1381         tmp_mask = (unsigned int)mask;
1382         /* Vlan stripping setting */
1383         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1384                 rte_spinlock_lock(&hw->lock);
1385                 /* Enable or disable VLAN stripping */
1386                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1387                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1388                 else
1389                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1390                 rte_spinlock_unlock(&hw->lock);
1391         }
1392
1393         return ret;
1394 }
1395
1396 static int
1397 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1398 {
1399         struct rte_vlan_filter_conf *vfc;
1400         struct hns3_hw *hw = &hns->hw;
1401         uint16_t vlan_id;
1402         uint64_t vbit;
1403         uint64_t ids;
1404         int ret = 0;
1405         uint32_t i;
1406
1407         vfc = &hw->data->vlan_filter_conf;
1408         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1409                 if (vfc->ids[i] == 0)
1410                         continue;
1411                 ids = vfc->ids[i];
1412                 while (ids) {
1413                         /*
1414                          * 64 means the num bits of ids, one bit corresponds to
1415                          * one vlan id
1416                          */
1417                         vlan_id = 64 * i;
1418                         /* count trailing zeroes */
1419                         vbit = ~ids & (ids - 1);
1420                         /* clear least significant bit set */
1421                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1422                         for (; vbit;) {
1423                                 vbit >>= 1;
1424                                 vlan_id++;
1425                         }
1426                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1427                         if (ret) {
1428                                 hns3_err(hw,
1429                                          "VF handle vlan table failed, ret =%d, on = %d",
1430                                          ret, on);
1431                                 return ret;
1432                         }
1433                 }
1434         }
1435
1436         return ret;
1437 }
1438
1439 static int
1440 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1441 {
1442         return hns3vf_handle_all_vlan_table(hns, 0);
1443 }
1444
1445 static int
1446 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1447 {
1448         struct hns3_hw *hw = &hns->hw;
1449         struct rte_eth_conf *dev_conf;
1450         bool en;
1451         int ret;
1452
1453         dev_conf = &hw->data->dev_conf;
1454         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1455                                                                    : false;
1456         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1457         if (ret)
1458                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1459                          ret);
1460         return ret;
1461 }
1462
1463 static int
1464 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1465 {
1466         struct hns3_adapter *hns = dev->data->dev_private;
1467         struct rte_eth_dev_data *data = dev->data;
1468         struct hns3_hw *hw = &hns->hw;
1469         int ret;
1470
1471         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1472             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1473             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1474                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1475                               "or hw_vlan_insert_pvid is not support!");
1476         }
1477
1478         /* Apply vlan offload setting */
1479         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1480         if (ret)
1481                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1482
1483         return ret;
1484 }
1485
1486 static int
1487 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1488 {
1489         uint8_t msg_data;
1490
1491         msg_data = alive ? 1 : 0;
1492         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1493                                  sizeof(msg_data), false, NULL, 0);
1494 }
1495
1496 static void
1497 hns3vf_keep_alive_handler(void *param)
1498 {
1499         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1500         struct hns3_adapter *hns = eth_dev->data->dev_private;
1501         struct hns3_hw *hw = &hns->hw;
1502         uint8_t respmsg;
1503         int ret;
1504
1505         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1506                                 false, &respmsg, sizeof(uint8_t));
1507         if (ret)
1508                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1509                          ret);
1510
1511         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1512                           eth_dev);
1513 }
1514
1515 static void
1516 hns3vf_service_handler(void *param)
1517 {
1518         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1519         struct hns3_adapter *hns = eth_dev->data->dev_private;
1520         struct hns3_hw *hw = &hns->hw;
1521
1522         /*
1523          * The query link status and reset processing are executed in the
1524          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1525          * and the query operation will time out after 30ms. In the case of
1526          * multiple PF/VFs, each query failure timeout causes the IMP reset
1527          * interrupt to fail to respond within 100ms.
1528          * Before querying the link status, check whether there is a reset
1529          * pending, and if so, abandon the query.
1530          */
1531         if (!hns3vf_is_reset_pending(hns))
1532                 hns3vf_request_link_info(hw);
1533         else
1534                 hns3_warn(hw, "Cancel the query when reset is pending");
1535
1536         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1537                           eth_dev);
1538 }
1539
1540 static int
1541 hns3_query_vf_resource(struct hns3_hw *hw)
1542 {
1543         struct hns3_vf_res_cmd *req;
1544         struct hns3_cmd_desc desc;
1545         uint16_t num_msi;
1546         int ret;
1547
1548         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1549         ret = hns3_cmd_send(hw, &desc, 1);
1550         if (ret) {
1551                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1552                 return ret;
1553         }
1554
1555         req = (struct hns3_vf_res_cmd *)desc.data;
1556         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1557                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
1558         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1559                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1560                          num_msi, HNS3_MIN_VECTOR_NUM);
1561                 return -EINVAL;
1562         }
1563
1564         hw->num_msi = num_msi;
1565
1566         return 0;
1567 }
1568
1569 static int
1570 hns3vf_init_hardware(struct hns3_adapter *hns)
1571 {
1572         struct hns3_hw *hw = &hns->hw;
1573         uint16_t mtu = hw->data->mtu;
1574         int ret;
1575
1576         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1577         if (ret)
1578                 return ret;
1579
1580         ret = hns3vf_config_mtu(hw, mtu);
1581         if (ret)
1582                 goto err_init_hardware;
1583
1584         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1585         if (ret) {
1586                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1587                 goto err_init_hardware;
1588         }
1589
1590         ret = hns3_config_gro(hw, false);
1591         if (ret) {
1592                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1593                 goto err_init_hardware;
1594         }
1595
1596         /*
1597          * In the initialization clearing the all hardware mapping relationship
1598          * configurations between queues and interrupt vectors is needed, so
1599          * some error caused by the residual configurations, such as the
1600          * unexpected interrupt, can be avoid.
1601          */
1602         ret = hns3vf_init_ring_with_vector(hw);
1603         if (ret) {
1604                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1605                 goto err_init_hardware;
1606         }
1607
1608         ret = hns3vf_set_alive(hw, true);
1609         if (ret) {
1610                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1611                 goto err_init_hardware;
1612         }
1613
1614         hns3vf_request_link_info(hw);
1615         return 0;
1616
1617 err_init_hardware:
1618         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1619         return ret;
1620 }
1621
1622 static int
1623 hns3vf_clear_vport_list(struct hns3_hw *hw)
1624 {
1625         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1626                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1627                                  NULL, 0);
1628 }
1629
1630 static int
1631 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1632 {
1633         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1634         struct hns3_adapter *hns = eth_dev->data->dev_private;
1635         struct hns3_hw *hw = &hns->hw;
1636         int ret;
1637
1638         PMD_INIT_FUNC_TRACE();
1639
1640         /* Get hardware io base address from pcie BAR2 IO space */
1641         hw->io_base = pci_dev->mem_resource[2].addr;
1642
1643         /* Firmware command queue initialize */
1644         ret = hns3_cmd_init_queue(hw);
1645         if (ret) {
1646                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1647                 goto err_cmd_init_queue;
1648         }
1649
1650         /* Firmware command initialize */
1651         ret = hns3_cmd_init(hw);
1652         if (ret) {
1653                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1654                 goto err_cmd_init;
1655         }
1656
1657         /* Get VF resource */
1658         ret = hns3_query_vf_resource(hw);
1659         if (ret)
1660                 goto err_cmd_init;
1661
1662         rte_spinlock_init(&hw->mbx_resp.lock);
1663
1664         hns3vf_clear_event_cause(hw, 0);
1665
1666         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1667                                          hns3vf_interrupt_handler, eth_dev);
1668         if (ret) {
1669                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1670                 goto err_intr_callback_register;
1671         }
1672
1673         /* Enable interrupt */
1674         rte_intr_enable(&pci_dev->intr_handle);
1675         hns3vf_enable_irq0(hw);
1676
1677         /* Get configuration from PF */
1678         ret = hns3vf_get_configuration(hw);
1679         if (ret) {
1680                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1681                 goto err_get_config;
1682         }
1683
1684         /*
1685          * The hns3 PF ethdev driver in kernel support setting VF MAC address
1686          * on the host by "ip link set ..." command. To avoid some incorrect
1687          * scenes, for example, hns3 VF PMD driver fails to receive and send
1688          * packets after user configure the MAC address by using the
1689          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
1690          * address strategy as the hns3 kernel ethdev driver in the
1691          * initialization. If user configure a MAC address by the ip command
1692          * for VF device, then hns3 VF PMD driver will start with it, otherwise
1693          * start with a random MAC address in the initialization.
1694          */
1695         ret = rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr);
1696         if (ret)
1697                 rte_eth_random_addr(hw->mac.mac_addr);
1698
1699         ret = hns3vf_clear_vport_list(hw);
1700         if (ret) {
1701                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1702                 goto err_get_config;
1703         }
1704
1705         ret = hns3vf_init_hardware(hns);
1706         if (ret)
1707                 goto err_get_config;
1708
1709         hns3_set_default_rss_args(hw);
1710
1711         return 0;
1712
1713 err_get_config:
1714         hns3vf_disable_irq0(hw);
1715         rte_intr_disable(&pci_dev->intr_handle);
1716         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1717                              eth_dev);
1718 err_intr_callback_register:
1719 err_cmd_init:
1720         hns3_cmd_uninit(hw);
1721         hns3_cmd_destroy_queue(hw);
1722 err_cmd_init_queue:
1723         hw->io_base = NULL;
1724
1725         return ret;
1726 }
1727
1728 static void
1729 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1730 {
1731         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1732         struct hns3_adapter *hns = eth_dev->data->dev_private;
1733         struct hns3_hw *hw = &hns->hw;
1734
1735         PMD_INIT_FUNC_TRACE();
1736
1737         hns3_rss_uninit(hns);
1738         (void)hns3_config_gro(hw, false);
1739         (void)hns3vf_set_alive(hw, false);
1740         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1741         hns3vf_disable_irq0(hw);
1742         rte_intr_disable(&pci_dev->intr_handle);
1743         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1744                              eth_dev);
1745         hns3_cmd_uninit(hw);
1746         hns3_cmd_destroy_queue(hw);
1747         hw->io_base = NULL;
1748 }
1749
1750 static int
1751 hns3vf_do_stop(struct hns3_adapter *hns)
1752 {
1753         struct hns3_hw *hw = &hns->hw;
1754         bool reset_queue;
1755
1756         hw->mac.link_status = ETH_LINK_DOWN;
1757
1758         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1759                 hns3vf_configure_mac_addr(hns, true);
1760                 reset_queue = true;
1761         } else
1762                 reset_queue = false;
1763         return hns3_stop_queues(hns, reset_queue);
1764 }
1765
1766 static void
1767 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1768 {
1769         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1771         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1772         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1773         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1774         uint16_t q_id;
1775
1776         if (dev->data->dev_conf.intr_conf.rxq == 0)
1777                 return;
1778
1779         /* unmap the ring with vector */
1780         if (rte_intr_allow_others(intr_handle)) {
1781                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1782                 base = RTE_INTR_VEC_RXTX_OFFSET;
1783         }
1784         if (rte_intr_dp_is_en(intr_handle)) {
1785                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1786                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1787                                                            HNS3_RING_TYPE_RX,
1788                                                            q_id);
1789                         if (vec < base + intr_handle->nb_efd - 1)
1790                                 vec++;
1791                 }
1792         }
1793         /* Clean datapath event and queue/vec mapping */
1794         rte_intr_efd_disable(intr_handle);
1795         if (intr_handle->intr_vec) {
1796                 rte_free(intr_handle->intr_vec);
1797                 intr_handle->intr_vec = NULL;
1798         }
1799 }
1800
1801 static void
1802 hns3vf_dev_stop(struct rte_eth_dev *dev)
1803 {
1804         struct hns3_adapter *hns = dev->data->dev_private;
1805         struct hns3_hw *hw = &hns->hw;
1806
1807         PMD_INIT_FUNC_TRACE();
1808
1809         hw->adapter_state = HNS3_NIC_STOPPING;
1810         hns3_set_rxtx_function(dev);
1811         rte_wmb();
1812         /* Disable datapath on secondary process. */
1813         hns3_mp_req_stop_rxtx(dev);
1814         /* Prevent crashes when queues are still in use. */
1815         rte_delay_ms(hw->tqps_num);
1816
1817         rte_spinlock_lock(&hw->lock);
1818         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1819                 hns3vf_do_stop(hns);
1820                 hns3vf_unmap_rx_interrupt(dev);
1821                 hns3_dev_release_mbufs(hns);
1822                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1823         }
1824         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1825         rte_spinlock_unlock(&hw->lock);
1826 }
1827
1828 static void
1829 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1830 {
1831         struct hns3_adapter *hns = eth_dev->data->dev_private;
1832         struct hns3_hw *hw = &hns->hw;
1833
1834         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1835                 return;
1836
1837         if (hw->adapter_state == HNS3_NIC_STARTED)
1838                 hns3vf_dev_stop(eth_dev);
1839
1840         hw->adapter_state = HNS3_NIC_CLOSING;
1841         hns3_reset_abort(hns);
1842         hw->adapter_state = HNS3_NIC_CLOSED;
1843         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1844         hns3vf_configure_all_mc_mac_addr(hns, true);
1845         hns3vf_remove_all_vlan_table(hns);
1846         hns3vf_uninit_vf(eth_dev);
1847         hns3_free_all_queues(eth_dev);
1848         rte_free(hw->reset.wait_data);
1849         rte_free(eth_dev->process_private);
1850         eth_dev->process_private = NULL;
1851         hns3_mp_uninit_primary();
1852         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1853 }
1854
1855 static int
1856 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1857                       size_t fw_size)
1858 {
1859         struct hns3_adapter *hns = eth_dev->data->dev_private;
1860         struct hns3_hw *hw = &hns->hw;
1861         uint32_t version = hw->fw_version;
1862         int ret;
1863
1864         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1865                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1866                                       HNS3_FW_VERSION_BYTE3_S),
1867                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1868                                       HNS3_FW_VERSION_BYTE2_S),
1869                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1870                                       HNS3_FW_VERSION_BYTE1_S),
1871                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1872                                       HNS3_FW_VERSION_BYTE0_S));
1873         ret += 1; /* add the size of '\0' */
1874         if (fw_size < (uint32_t)ret)
1875                 return ret;
1876         else
1877                 return 0;
1878 }
1879
1880 static int
1881 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1882                        __rte_unused int wait_to_complete)
1883 {
1884         struct hns3_adapter *hns = eth_dev->data->dev_private;
1885         struct hns3_hw *hw = &hns->hw;
1886         struct hns3_mac *mac = &hw->mac;
1887         struct rte_eth_link new_link;
1888
1889         memset(&new_link, 0, sizeof(new_link));
1890         switch (mac->link_speed) {
1891         case ETH_SPEED_NUM_10M:
1892         case ETH_SPEED_NUM_100M:
1893         case ETH_SPEED_NUM_1G:
1894         case ETH_SPEED_NUM_10G:
1895         case ETH_SPEED_NUM_25G:
1896         case ETH_SPEED_NUM_40G:
1897         case ETH_SPEED_NUM_50G:
1898         case ETH_SPEED_NUM_100G:
1899                 new_link.link_speed = mac->link_speed;
1900                 break;
1901         default:
1902                 new_link.link_speed = ETH_SPEED_NUM_100M;
1903                 break;
1904         }
1905
1906         new_link.link_duplex = mac->link_duplex;
1907         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1908         new_link.link_autoneg =
1909             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1910
1911         return rte_eth_linkstatus_set(eth_dev, &new_link);
1912 }
1913
1914 static int
1915 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1916 {
1917         struct hns3_hw *hw = &hns->hw;
1918         int ret;
1919
1920         ret = hns3vf_set_tc_info(hns);
1921         if (ret)
1922                 return ret;
1923
1924         ret = hns3_start_queues(hns, reset_queue);
1925         if (ret)
1926                 hns3_err(hw, "Failed to start queues: %d", ret);
1927
1928         return ret;
1929 }
1930
1931 static int
1932 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1933 {
1934         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1935         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1936         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1937         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1938         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1939         uint32_t intr_vector;
1940         uint16_t q_id;
1941         int ret;
1942
1943         if (dev->data->dev_conf.intr_conf.rxq == 0)
1944                 return 0;
1945
1946         /* disable uio/vfio intr/eventfd mapping */
1947         rte_intr_disable(intr_handle);
1948
1949         /* check and configure queue intr-vector mapping */
1950         if (rte_intr_cap_multiple(intr_handle) ||
1951             !RTE_ETH_DEV_SRIOV(dev).active) {
1952                 intr_vector = hw->used_rx_queues;
1953                 /* It creates event fd for each intr vector when MSIX is used */
1954                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1955                         return -EINVAL;
1956         }
1957         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1958                 intr_handle->intr_vec =
1959                         rte_zmalloc("intr_vec",
1960                                     hw->used_rx_queues * sizeof(int), 0);
1961                 if (intr_handle->intr_vec == NULL) {
1962                         hns3_err(hw, "Failed to allocate %d rx_queues"
1963                                      " intr_vec", hw->used_rx_queues);
1964                         ret = -ENOMEM;
1965                         goto vf_alloc_intr_vec_error;
1966                 }
1967         }
1968
1969         if (rte_intr_allow_others(intr_handle)) {
1970                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1971                 base = RTE_INTR_VEC_RXTX_OFFSET;
1972         }
1973         if (rte_intr_dp_is_en(intr_handle)) {
1974                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1975                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
1976                                                            HNS3_RING_TYPE_RX,
1977                                                            q_id);
1978                         if (ret)
1979                                 goto vf_bind_vector_error;
1980                         intr_handle->intr_vec[q_id] = vec;
1981                         if (vec < base + intr_handle->nb_efd - 1)
1982                                 vec++;
1983                 }
1984         }
1985         rte_intr_enable(intr_handle);
1986         return 0;
1987
1988 vf_bind_vector_error:
1989         rte_intr_efd_disable(intr_handle);
1990         if (intr_handle->intr_vec) {
1991                 free(intr_handle->intr_vec);
1992                 intr_handle->intr_vec = NULL;
1993         }
1994         return ret;
1995 vf_alloc_intr_vec_error:
1996         rte_intr_efd_disable(intr_handle);
1997         return ret;
1998 }
1999
2000 static int
2001 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2002 {
2003         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2004         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2005         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2006         uint16_t q_id;
2007         int ret;
2008
2009         if (dev->data->dev_conf.intr_conf.rxq == 0)
2010                 return 0;
2011
2012         if (rte_intr_dp_is_en(intr_handle)) {
2013                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2014                         ret = hns3vf_bind_ring_with_vector(hw,
2015                                         intr_handle->intr_vec[q_id], true,
2016                                         HNS3_RING_TYPE_RX, q_id);
2017                         if (ret)
2018                                 return ret;
2019                 }
2020         }
2021
2022         return 0;
2023 }
2024
2025 static void
2026 hns3vf_restore_filter(struct rte_eth_dev *dev)
2027 {
2028         hns3_restore_rss_filter(dev);
2029 }
2030
2031 static int
2032 hns3vf_dev_start(struct rte_eth_dev *dev)
2033 {
2034         struct hns3_adapter *hns = dev->data->dev_private;
2035         struct hns3_hw *hw = &hns->hw;
2036         int ret;
2037
2038         PMD_INIT_FUNC_TRACE();
2039         if (rte_atomic16_read(&hw->reset.resetting))
2040                 return -EBUSY;
2041
2042         rte_spinlock_lock(&hw->lock);
2043         hw->adapter_state = HNS3_NIC_STARTING;
2044         ret = hns3vf_do_start(hns, true);
2045         if (ret) {
2046                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2047                 rte_spinlock_unlock(&hw->lock);
2048                 return ret;
2049         }
2050         ret = hns3vf_map_rx_interrupt(dev);
2051         if (ret) {
2052                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2053                 rte_spinlock_unlock(&hw->lock);
2054                 return ret;
2055         }
2056         hw->adapter_state = HNS3_NIC_STARTED;
2057         rte_spinlock_unlock(&hw->lock);
2058
2059         hns3_set_rxtx_function(dev);
2060         hns3_mp_req_start_rxtx(dev);
2061         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2062
2063         hns3vf_restore_filter(dev);
2064
2065         /* Enable interrupt of all rx queues before enabling queues */
2066         hns3_dev_all_rx_queue_intr_enable(hw, true);
2067         /*
2068          * When finished the initialization, enable queues to receive/transmit
2069          * packets.
2070          */
2071         hns3_enable_all_queues(hw, true);
2072
2073         return ret;
2074 }
2075
2076 static bool
2077 is_vf_reset_done(struct hns3_hw *hw)
2078 {
2079 #define HNS3_FUN_RST_ING_BITS \
2080         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2081          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2082          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2083          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2084
2085         uint32_t val;
2086
2087         if (hw->reset.level == HNS3_VF_RESET) {
2088                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2089                 if (val & HNS3_VF_RST_ING_BIT)
2090                         return false;
2091         } else {
2092                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2093                 if (val & HNS3_FUN_RST_ING_BITS)
2094                         return false;
2095         }
2096         return true;
2097 }
2098
2099 bool
2100 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2101 {
2102         struct hns3_hw *hw = &hns->hw;
2103         enum hns3_reset_level reset;
2104
2105         hns3vf_check_event_cause(hns, NULL);
2106         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2107         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2108                 hns3_warn(hw, "High level reset %d is pending", reset);
2109                 return true;
2110         }
2111         return false;
2112 }
2113
2114 static int
2115 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2116 {
2117         struct hns3_hw *hw = &hns->hw;
2118         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2119         struct timeval tv;
2120
2121         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2122                 /*
2123                  * After vf reset is ready, the PF may not have completed
2124                  * the reset processing. The vf sending mbox to PF may fail
2125                  * during the pf reset, so it is better to add extra delay.
2126                  */
2127                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2128                     hw->reset.level == HNS3_FLR_RESET)
2129                         return 0;
2130                 /* Reset retry process, no need to add extra delay. */
2131                 if (hw->reset.attempts)
2132                         return 0;
2133                 if (wait_data->check_completion == NULL)
2134                         return 0;
2135
2136                 wait_data->check_completion = NULL;
2137                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2138                 wait_data->count = 1;
2139                 wait_data->result = HNS3_WAIT_REQUEST;
2140                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2141                                   wait_data);
2142                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2143                 return -EAGAIN;
2144         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2145                 gettimeofday(&tv, NULL);
2146                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2147                           tv.tv_sec, tv.tv_usec);
2148                 return -ETIME;
2149         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2150                 return -EAGAIN;
2151
2152         wait_data->hns = hns;
2153         wait_data->check_completion = is_vf_reset_done;
2154         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2155                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2156         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2157         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2158         wait_data->result = HNS3_WAIT_REQUEST;
2159         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2160         return -EAGAIN;
2161 }
2162
2163 static int
2164 hns3vf_prepare_reset(struct hns3_adapter *hns)
2165 {
2166         struct hns3_hw *hw = &hns->hw;
2167         int ret = 0;
2168
2169         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2170                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2171                                         0, true, NULL, 0);
2172         }
2173         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2174
2175         return ret;
2176 }
2177
2178 static int
2179 hns3vf_stop_service(struct hns3_adapter *hns)
2180 {
2181         struct hns3_hw *hw = &hns->hw;
2182         struct rte_eth_dev *eth_dev;
2183
2184         eth_dev = &rte_eth_devices[hw->data->port_id];
2185         if (hw->adapter_state == HNS3_NIC_STARTED)
2186                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2187         hw->mac.link_status = ETH_LINK_DOWN;
2188
2189         hns3_set_rxtx_function(eth_dev);
2190         rte_wmb();
2191         /* Disable datapath on secondary process. */
2192         hns3_mp_req_stop_rxtx(eth_dev);
2193         rte_delay_ms(hw->tqps_num);
2194
2195         rte_spinlock_lock(&hw->lock);
2196         if (hw->adapter_state == HNS3_NIC_STARTED ||
2197             hw->adapter_state == HNS3_NIC_STOPPING) {
2198                 hns3vf_do_stop(hns);
2199                 hw->reset.mbuf_deferred_free = true;
2200         } else
2201                 hw->reset.mbuf_deferred_free = false;
2202
2203         /*
2204          * It is cumbersome for hardware to pick-and-choose entries for deletion
2205          * from table space. Hence, for function reset software intervention is
2206          * required to delete the entries.
2207          */
2208         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2209                 hns3vf_configure_all_mc_mac_addr(hns, true);
2210         rte_spinlock_unlock(&hw->lock);
2211
2212         return 0;
2213 }
2214
2215 static int
2216 hns3vf_start_service(struct hns3_adapter *hns)
2217 {
2218         struct hns3_hw *hw = &hns->hw;
2219         struct rte_eth_dev *eth_dev;
2220
2221         eth_dev = &rte_eth_devices[hw->data->port_id];
2222         hns3_set_rxtx_function(eth_dev);
2223         hns3_mp_req_start_rxtx(eth_dev);
2224         if (hw->adapter_state == HNS3_NIC_STARTED) {
2225                 hns3vf_service_handler(eth_dev);
2226
2227                 /* Enable interrupt of all rx queues before enabling queues */
2228                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2229                 /*
2230                  * When finished the initialization, enable queues to receive
2231                  * and transmit packets.
2232                  */
2233                 hns3_enable_all_queues(hw, true);
2234         }
2235
2236         return 0;
2237 }
2238
2239 static int
2240 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2241 {
2242         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2243         struct rte_ether_addr *hw_mac;
2244         int ret;
2245
2246         /*
2247          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2248          * on the host by "ip link set ..." command. If the hns3 PF kernel
2249          * ethdev driver sets the MAC address for VF device after the
2250          * initialization of the related VF device, the PF driver will notify
2251          * VF driver to reset VF device to make the new MAC address effective
2252          * immediately. The hns3 VF PMD driver should check whether the MAC
2253          * address has been changed by the PF kernel ethdev driver, if changed
2254          * VF driver should configure hardware using the new MAC address in the
2255          * recovering hardware configuration stage of the reset process.
2256          */
2257         ret = hns3vf_get_host_mac_addr(hw);
2258         if (ret)
2259                 return ret;
2260
2261         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2262         ret = rte_is_zero_ether_addr(hw_mac);
2263         if (ret) {
2264                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2265         } else {
2266                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2267                 if (!ret) {
2268                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2269                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2270                                               &hw->data->mac_addrs[0]);
2271                         hns3_warn(hw, "Default MAC address has been changed to:"
2272                                   " %s by the host PF kernel ethdev driver",
2273                                   mac_str);
2274                 }
2275         }
2276
2277         return 0;
2278 }
2279
2280 static int
2281 hns3vf_restore_conf(struct hns3_adapter *hns)
2282 {
2283         struct hns3_hw *hw = &hns->hw;
2284         int ret;
2285
2286         ret = hns3vf_check_default_mac_change(hw);
2287         if (ret)
2288                 return ret;
2289
2290         ret = hns3vf_configure_mac_addr(hns, false);
2291         if (ret)
2292                 return ret;
2293
2294         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2295         if (ret)
2296                 goto err_mc_mac;
2297
2298         ret = hns3vf_restore_promisc(hns);
2299         if (ret)
2300                 goto err_vlan_table;
2301
2302         ret = hns3vf_restore_vlan_conf(hns);
2303         if (ret)
2304                 goto err_vlan_table;
2305
2306         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2307         if (ret)
2308                 goto err_vlan_table;
2309
2310         ret = hns3vf_restore_rx_interrupt(hw);
2311         if (ret)
2312                 goto err_vlan_table;
2313
2314         ret = hns3_restore_gro_conf(hw);
2315         if (ret)
2316                 goto err_vlan_table;
2317
2318         if (hw->adapter_state == HNS3_NIC_STARTED) {
2319                 ret = hns3vf_do_start(hns, false);
2320                 if (ret)
2321                         goto err_vlan_table;
2322                 hns3_info(hw, "hns3vf dev restart successful!");
2323         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2324                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2325         return 0;
2326
2327 err_vlan_table:
2328         hns3vf_configure_all_mc_mac_addr(hns, true);
2329 err_mc_mac:
2330         hns3vf_configure_mac_addr(hns, true);
2331         return ret;
2332 }
2333
2334 static enum hns3_reset_level
2335 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2336 {
2337         enum hns3_reset_level reset_level;
2338
2339         /* return the highest priority reset level amongst all */
2340         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2341                 reset_level = HNS3_VF_RESET;
2342         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2343                 reset_level = HNS3_VF_FULL_RESET;
2344         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2345                 reset_level = HNS3_VF_PF_FUNC_RESET;
2346         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2347                 reset_level = HNS3_VF_FUNC_RESET;
2348         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2349                 reset_level = HNS3_FLR_RESET;
2350         else
2351                 reset_level = HNS3_NONE_RESET;
2352
2353         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2354                 return HNS3_NONE_RESET;
2355
2356         return reset_level;
2357 }
2358
2359 static void
2360 hns3vf_reset_service(void *param)
2361 {
2362         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2363         struct hns3_hw *hw = &hns->hw;
2364         enum hns3_reset_level reset_level;
2365         struct timeval tv_delta;
2366         struct timeval tv_start;
2367         struct timeval tv;
2368         uint64_t msec;
2369
2370         /*
2371          * The interrupt is not triggered within the delay time.
2372          * The interrupt may have been lost. It is necessary to handle
2373          * the interrupt to recover from the error.
2374          */
2375         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2376                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2377                 hns3_err(hw, "Handling interrupts in delayed tasks");
2378                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2379                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2380                 if (reset_level == HNS3_NONE_RESET) {
2381                         hns3_err(hw, "No reset level is set, try global reset");
2382                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2383                 }
2384         }
2385         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2386
2387         /*
2388          * Hardware reset has been notified, we now have to poll & check if
2389          * hardware has actually completed the reset sequence.
2390          */
2391         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2392         if (reset_level != HNS3_NONE_RESET) {
2393                 gettimeofday(&tv_start, NULL);
2394                 hns3_reset_process(hns, reset_level);
2395                 gettimeofday(&tv, NULL);
2396                 timersub(&tv, &tv_start, &tv_delta);
2397                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2398                        tv_delta.tv_usec / USEC_PER_MSEC;
2399                 if (msec > HNS3_RESET_PROCESS_MS)
2400                         hns3_err(hw, "%d handle long time delta %" PRIx64
2401                                  " ms time=%ld.%.6ld",
2402                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2403         }
2404 }
2405
2406 static int
2407 hns3vf_reinit_dev(struct hns3_adapter *hns)
2408 {
2409         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2410         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2411         struct hns3_hw *hw = &hns->hw;
2412         int ret;
2413
2414         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2415                 rte_intr_disable(&pci_dev->intr_handle);
2416                 hns3vf_set_bus_master(pci_dev, true);
2417         }
2418
2419         /* Firmware command initialize */
2420         ret = hns3_cmd_init(hw);
2421         if (ret) {
2422                 hns3_err(hw, "Failed to init cmd: %d", ret);
2423                 return ret;
2424         }
2425
2426         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2427                 /*
2428                  * UIO enables msix by writing the pcie configuration space
2429                  * vfio_pci enables msix in rte_intr_enable.
2430                  */
2431                 if (pci_dev->kdrv == RTE_KDRV_IGB_UIO ||
2432                     pci_dev->kdrv == RTE_KDRV_UIO_GENERIC) {
2433                         if (hns3vf_enable_msix(pci_dev, true))
2434                                 hns3_err(hw, "Failed to enable msix");
2435                 }
2436
2437                 rte_intr_enable(&pci_dev->intr_handle);
2438         }
2439
2440         ret = hns3_reset_all_queues(hns);
2441         if (ret) {
2442                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2443                 return ret;
2444         }
2445
2446         ret = hns3vf_init_hardware(hns);
2447         if (ret) {
2448                 hns3_err(hw, "Failed to init hardware: %d", ret);
2449                 return ret;
2450         }
2451
2452         return 0;
2453 }
2454
2455 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2456         .dev_start          = hns3vf_dev_start,
2457         .dev_stop           = hns3vf_dev_stop,
2458         .dev_close          = hns3vf_dev_close,
2459         .mtu_set            = hns3vf_dev_mtu_set,
2460         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2461         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2462         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2463         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2464         .stats_get          = hns3_stats_get,
2465         .stats_reset        = hns3_stats_reset,
2466         .xstats_get         = hns3_dev_xstats_get,
2467         .xstats_get_names   = hns3_dev_xstats_get_names,
2468         .xstats_reset       = hns3_dev_xstats_reset,
2469         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2470         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2471         .dev_infos_get      = hns3vf_dev_infos_get,
2472         .fw_version_get     = hns3vf_fw_version_get,
2473         .rx_queue_setup     = hns3_rx_queue_setup,
2474         .tx_queue_setup     = hns3_tx_queue_setup,
2475         .rx_queue_release   = hns3_dev_rx_queue_release,
2476         .tx_queue_release   = hns3_dev_tx_queue_release,
2477         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2478         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2479         .dev_configure      = hns3vf_dev_configure,
2480         .mac_addr_add       = hns3vf_add_mac_addr,
2481         .mac_addr_remove    = hns3vf_remove_mac_addr,
2482         .mac_addr_set       = hns3vf_set_default_mac_addr,
2483         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2484         .link_update        = hns3vf_dev_link_update,
2485         .rss_hash_update    = hns3_dev_rss_hash_update,
2486         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2487         .reta_update        = hns3_dev_rss_reta_update,
2488         .reta_query         = hns3_dev_rss_reta_query,
2489         .filter_ctrl        = hns3_dev_filter_ctrl,
2490         .vlan_filter_set    = hns3vf_vlan_filter_set,
2491         .vlan_offload_set   = hns3vf_vlan_offload_set,
2492         .get_reg            = hns3_get_regs,
2493         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2494 };
2495
2496 static const struct hns3_reset_ops hns3vf_reset_ops = {
2497         .reset_service       = hns3vf_reset_service,
2498         .stop_service        = hns3vf_stop_service,
2499         .prepare_reset       = hns3vf_prepare_reset,
2500         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2501         .reinit_dev          = hns3vf_reinit_dev,
2502         .restore_conf        = hns3vf_restore_conf,
2503         .start_service       = hns3vf_start_service,
2504 };
2505
2506 static int
2507 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2508 {
2509         struct hns3_adapter *hns = eth_dev->data->dev_private;
2510         struct hns3_hw *hw = &hns->hw;
2511         int ret;
2512
2513         PMD_INIT_FUNC_TRACE();
2514
2515         eth_dev->process_private = (struct hns3_process_private *)
2516             rte_zmalloc_socket("hns3_filter_list",
2517                                sizeof(struct hns3_process_private),
2518                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2519         if (eth_dev->process_private == NULL) {
2520                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2521                 return -ENOMEM;
2522         }
2523
2524         /* initialize flow filter lists */
2525         hns3_filterlist_init(eth_dev);
2526
2527         hns3_set_rxtx_function(eth_dev);
2528         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2529         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2530                 hns3_mp_init_secondary();
2531                 hw->secondary_cnt++;
2532                 return 0;
2533         }
2534
2535         hns3_mp_init_primary();
2536
2537         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2538         hns->is_vf = true;
2539         hw->data = eth_dev->data;
2540
2541         ret = hns3_reset_init(hw);
2542         if (ret)
2543                 goto err_init_reset;
2544         hw->reset.ops = &hns3vf_reset_ops;
2545
2546         ret = hns3vf_init_vf(eth_dev);
2547         if (ret) {
2548                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2549                 goto err_init_vf;
2550         }
2551
2552         /* Allocate memory for storing MAC addresses */
2553         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2554                                                sizeof(struct rte_ether_addr) *
2555                                                HNS3_VF_UC_MACADDR_NUM, 0);
2556         if (eth_dev->data->mac_addrs == NULL) {
2557                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2558                              "to store MAC addresses",
2559                              sizeof(struct rte_ether_addr) *
2560                              HNS3_VF_UC_MACADDR_NUM);
2561                 ret = -ENOMEM;
2562                 goto err_rte_zmalloc;
2563         }
2564
2565         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2566                             &eth_dev->data->mac_addrs[0]);
2567         hw->adapter_state = HNS3_NIC_INITIALIZED;
2568         /*
2569          * Pass the information to the rte_eth_dev_close() that it should also
2570          * release the private port resources.
2571          */
2572         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2573
2574         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2575                 hns3_err(hw, "Reschedule reset service after dev_init");
2576                 hns3_schedule_reset(hns);
2577         } else {
2578                 /* IMP will wait ready flag before reset */
2579                 hns3_notify_reset_ready(hw, false);
2580         }
2581         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2582                           eth_dev);
2583         return 0;
2584
2585 err_rte_zmalloc:
2586         hns3vf_uninit_vf(eth_dev);
2587
2588 err_init_vf:
2589         rte_free(hw->reset.wait_data);
2590
2591 err_init_reset:
2592         eth_dev->dev_ops = NULL;
2593         eth_dev->rx_pkt_burst = NULL;
2594         eth_dev->tx_pkt_burst = NULL;
2595         eth_dev->tx_pkt_prepare = NULL;
2596         rte_free(eth_dev->process_private);
2597         eth_dev->process_private = NULL;
2598
2599         return ret;
2600 }
2601
2602 static int
2603 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2604 {
2605         struct hns3_adapter *hns = eth_dev->data->dev_private;
2606         struct hns3_hw *hw = &hns->hw;
2607
2608         PMD_INIT_FUNC_TRACE();
2609
2610         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2611                 return -EPERM;
2612
2613         eth_dev->dev_ops = NULL;
2614         eth_dev->rx_pkt_burst = NULL;
2615         eth_dev->tx_pkt_burst = NULL;
2616         eth_dev->tx_pkt_prepare = NULL;
2617
2618         if (hw->adapter_state < HNS3_NIC_CLOSING)
2619                 hns3vf_dev_close(eth_dev);
2620
2621         hw->adapter_state = HNS3_NIC_REMOVED;
2622         return 0;
2623 }
2624
2625 static int
2626 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2627                      struct rte_pci_device *pci_dev)
2628 {
2629         return rte_eth_dev_pci_generic_probe(pci_dev,
2630                                              sizeof(struct hns3_adapter),
2631                                              hns3vf_dev_init);
2632 }
2633
2634 static int
2635 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2636 {
2637         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2638 }
2639
2640 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2641         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2642         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2643         { .vendor_id = 0, /* sentinel */ },
2644 };
2645
2646 static struct rte_pci_driver rte_hns3vf_pmd = {
2647         .id_table = pci_id_hns3vf_map,
2648         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2649         .probe = eth_hns3vf_pci_probe,
2650         .remove = eth_hns3vf_pci_remove,
2651 };
2652
2653 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2654 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2655 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");