drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static void
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71
  72         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  73
  74         if (op)
  75                 /* set the master bit */
  76                 reg |= PCI_COMMAND_MASTER;
  77         else
  78                 reg &= ~(PCI_COMMAND_MASTER);
  79
  80         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  81 }
  82
  83 /**
  84  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  85  * @cap: the capability
  86  *
  87  * Return the address of the given capability within the PCI capability list.
  88  */
  89 static int
  90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  91 {
  92 #define MAX_PCIE_CAPABILITY 48
  93         uint16_t status;
  94         uint8_t pos;
  95         uint8_t id;
  96         int ttl;
  97
  98         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  99         if (!(status & PCI_STATUS_CAP_LIST))
 100                 return 0;
 101
 102         ttl = MAX_PCIE_CAPABILITY;
 103         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 rte_pci_read_config(device, &id, sizeof(id),
 106                                     (pos + PCI_CAP_LIST_ID));
 107
 108                 if (id == 0xFF)
 109                         break;
 110
 111                 if (id == cap)
 112                         return (int)pos;
 113
 114                 rte_pci_read_config(device, &pos, sizeof(pos),
 115                                     (pos + PCI_CAP_LIST_NEXT));
 116         }
 117         return 0;
 118 }
 119
 120 static int
 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 122 {
 123         uint16_t control;
 124         int pos;
 125
 126         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 127         if (pos) {
 128                 rte_pci_read_config(device, &control, sizeof(control),
 129                                     (pos + PCI_MSIX_FLAGS));
 130                 if (op)
 131                         control |= PCI_MSIX_FLAGS_ENABLE;
 132                 else
 133                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 134                 rte_pci_write_config(device, &control, sizeof(control),
 135                                      (pos + PCI_MSIX_FLAGS));
 136                 return 0;
 137         }
 138         return -ENXIO;
 139 }
 140
 141 static int
 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 143 {
 144         /* mac address was checked by upper level interface */
 145         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 146         int ret;
 147
 148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 149                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 150                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 155                          mac_str, ret);
 156         }
 157         return ret;
 158 }
 159
 160 static int
 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 162 {
 163         /* mac address was checked by upper level interface */
 164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 165         int ret;
 166
 167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 168                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 169                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 170                                 false, NULL, 0);
 171         if (ret) {
 172                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 173                                       mac_addr);
 174                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 175                          mac_str, ret);
 176         }
 177         return ret;
 178 }
 179
 180 static int
 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 182 {
 183         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 184         struct rte_ether_addr *addr;
 185         int ret;
 186         int i;
 187
 188         for (i = 0; i < hw->mc_addrs_num; i++) {
 189                 addr = &hw->mc_addrs[i];
 190                 /* Check if there are duplicate addresses */
 191                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 192                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 193                                               addr);
 194                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 195                                  "(%s) is added by the set_mc_mac_addr_list "
 196                                  "API", mac_str);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 202         if (ret) {
 203                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 204                                       mac_addr);
 205                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 206                          mac_str, ret);
 207         }
 208         return ret;
 209 }
 210
 211 static int
 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 213                     __rte_unused uint32_t idx,
 214                     __rte_unused uint32_t pool)
 215 {
 216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 218         int ret;
 219
 220         rte_spinlock_lock(&hw->lock);
 221
 222         /*
 223          * In hns3 network engine adding UC and MC mac address with different
 224          * commands with firmware. We need to determine whether the input
 225          * address is a UC or a MC address to call different commands.
 226          * By the way, it is recommended calling the API function named
 227          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 228          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 229          * may affect the specifications of UC mac addresses.
 230          */
 231         if (rte_is_multicast_ether_addr(mac_addr))
 232                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 233         else
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235
 236         rte_spinlock_unlock(&hw->lock);
 237         if (ret) {
 238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 239                                       mac_addr);
 240                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 241                          ret);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 249 {
 250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 251         /* index will be checked by upper level rte interface */
 252         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 260         else
 261                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 268                          mac_str, ret);
 269         }
 270 }
 271
 272 static int
 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                             struct rte_ether_addr *mac_addr)
 275 {
 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         struct rte_ether_addr *old_addr;
 279         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         /*
 284          * It has been guaranteed that input parameter named mac_addr is valid
 285          * address in the rte layer of DPDK framework.
 286          */
 287         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 288         rte_spinlock_lock(&hw->lock);
 289         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 290         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 291                RTE_ETHER_ADDR_LEN);
 292
 293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 294                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 295                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 296         if (ret) {
 297                 /*
 298                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 299                  * driver. When user has configured a MAC address for VF device
 300                  * by "ip link set ..." command based on the PF device, the hns3
 301                  * PF kernel ethdev driver does not allow VF driver to request
 302                  * reconfiguring a different default MAC address, and return
 303                  * -EPREM to VF driver through mailbox.
 304                  */
 305                 if (ret == -EPERM) {
 306                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 307                                               old_addr);
 308                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 309                                   mac_str);
 310                 } else {
 311                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 312                                               mac_addr);
 313                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 314                                  mac_str, ret);
 315                 }
 316         }
 317
 318         rte_ether_addr_copy(mac_addr,
 319                             (struct rte_ether_addr *)hw->mac.mac_addr);
 320         rte_spinlock_unlock(&hw->lock);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 327 {
 328         struct hns3_hw *hw = &hns->hw;
 329         struct rte_ether_addr *addr;
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int err = 0;
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 336                 addr = &hw->data->mac_addrs[i];
 337                 if (rte_is_zero_ether_addr(addr))
 338                         continue;
 339                 if (rte_is_multicast_ether_addr(addr))
 340                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 341                               hns3vf_add_mc_mac_addr(hw, addr);
 342                 else
 343                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 344                               hns3vf_add_uc_mac_addr(hw, addr);
 345
 346                 if (ret) {
 347                         err = ret;
 348                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 349                                               addr);
 350                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 351                                  "ret = %d.", del ? "remove" : "restore",
 352                                  mac_str, i, ret);
 353                 }
 354         }
 355         return err;
 356 }
 357
 358 static int
 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 360                        struct rte_ether_addr *mac_addr)
 361 {
 362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 363         int ret;
 364
 365         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 366                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 367                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 368                                 NULL, 0);
 369         if (ret) {
 370                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 371                                       mac_addr);
 372                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 373                          mac_str, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int
 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 381                           struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 402                              struct rte_ether_addr *mc_addr_set,
 403                              uint32_t nb_mc_addr)
 404 {
 405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 406         struct rte_ether_addr *addr;
 407         uint32_t i;
 408         uint32_t j;
 409
 410         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 411                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 412                          "invalid. valid range: 0~%d",
 413                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 414                 return -EINVAL;
 415         }
 416
 417         /* Check if input mac addresses are valid */
 418         for (i = 0; i < nb_mc_addr; i++) {
 419                 addr = &mc_addr_set[i];
 420                 if (!rte_is_multicast_ether_addr(addr)) {
 421                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 422                                               addr);
 423                         hns3_err(hw,
 424                                  "failed to set mc mac addr, addr(%s) invalid.",
 425                                  mac_str);
 426                         return -EINVAL;
 427                 }
 428
 429                 /* Check if there are duplicate addresses */
 430                 for (j = i + 1; j < nb_mc_addr; j++) {
 431                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 432                                 rte_ether_format_addr(mac_str,
 433                                                       RTE_ETHER_ADDR_FMT_SIZE,
 434                                                       addr);
 435                                 hns3_err(hw, "failed to set mc mac addr, "
 436                                          "addrs invalid. two same addrs(%s).",
 437                                          mac_str);
 438                                 return -EINVAL;
 439                         }
 440                 }
 441
 442                 /*
 443                  * Check if there are duplicate addresses between mac_addrs
 444                  * and mc_addr_set
 445                  */
 446                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 447                         if (rte_is_same_ether_addr(addr,
 448                                                    &hw->data->mac_addrs[j])) {
 449                                 rte_ether_format_addr(mac_str,
 450                                                       RTE_ETHER_ADDR_FMT_SIZE,
 451                                                       addr);
 452                                 hns3_err(hw, "failed to set mc mac addr, "
 453                                          "addrs invalid. addrs(%s) has already "
 454                                          "configured in mac_addr add API",
 455                                          mac_str);
 456                                 return -EINVAL;
 457                         }
 458                 }
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int
 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 466                             struct rte_ether_addr *mc_addr_set,
 467                             uint32_t nb_mc_addr)
 468 {
 469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 470         struct rte_ether_addr *addr;
 471         int cur_addr_num;
 472         int set_addr_num;
 473         int num;
 474         int ret;
 475         int i;
 476
 477         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 478         if (ret)
 479                 return ret;
 480
 481         rte_spinlock_lock(&hw->lock);
 482         cur_addr_num = hw->mc_addrs_num;
 483         for (i = 0; i < cur_addr_num; i++) {
 484                 num = cur_addr_num - i - 1;
 485                 addr = &hw->mc_addrs[num];
 486                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 487                 if (ret) {
 488                         rte_spinlock_unlock(&hw->lock);
 489                         return ret;
 490                 }
 491
 492                 hw->mc_addrs_num--;
 493         }
 494
 495         set_addr_num = (int)nb_mc_addr;
 496         for (i = 0; i < set_addr_num; i++) {
 497                 addr = &mc_addr_set[i];
 498                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 499                 if (ret) {
 500                         rte_spinlock_unlock(&hw->lock);
 501                         return ret;
 502                 }
 503
 504                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 505                 hw->mc_addrs_num++;
 506         }
 507         rte_spinlock_unlock(&hw->lock);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 514 {
 515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 516         struct hns3_hw *hw = &hns->hw;
 517         struct rte_ether_addr *addr;
 518         int err = 0;
 519         int ret;
 520         int i;
 521
 522         for (i = 0; i < hw->mc_addrs_num; i++) {
 523                 addr = &hw->mc_addrs[i];
 524                 if (!rte_is_multicast_ether_addr(addr))
 525                         continue;
 526                 if (del)
 527                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 528                 else
 529                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 530                 if (ret) {
 531                         err = ret;
 532                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 533                                               addr);
 534                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 535                                  del ? "Remove" : "Restore", mac_str, ret);
 536                 }
 537         }
 538         return err;
 539 }
 540
 541 static int
 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 543                         bool en_uc_pmc, bool en_mc_pmc)
 544 {
 545         struct hns3_mbx_vf_to_pf_cmd *req;
 546         struct hns3_cmd_desc desc;
 547         int ret;
 548
 549         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 550
 551         /*
 552          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 553          * so there are some features for promiscuous/allmulticast mode in hns3
 554          * VF PMD driver as below:
 555          * 1. The promiscuous/allmulticast mode can be configured successfully
 556          *    only based on the trusted VF device. If based on the non trusted
 557          *    VF device, configuring promiscuous/allmulticast mode will fail.
 558          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 559          *    kernel ethdev driver on the host by the following command:
 560          *      "ip link set <eth num> vf <vf id> turst on"
 561          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 562          *    driver can receive the ingress and outgoing traffic. In the words,
 563          *    all the ingress packets, all the packets sent from the PF and
 564          *    other VFs on the same physical port.
 565          * 3. Note: Because of the hardware constraints, By default vlan filter
 566          *    is enabled and couldn't be turned off based on VF device, so vlan
 567          *    filter is still effective even in promiscuous mode. If upper
 568          *    applications don't call rte_eth_dev_vlan_filter API function to
 569          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 570          *    the packets with vlan tag in promiscuoue mode.
 571          */
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 573         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 574         req->msg[1] = en_bc_pmc ? 1 : 0;
 575         req->msg[2] = en_uc_pmc ? 1 : 0;
 576         req->msg[3] = en_mc_pmc ? 1 : 0;
 577
 578         ret = hns3_cmd_send(hw, &desc, 1);
 579         if (ret)
 580                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 587 {
 588         struct hns3_adapter *hns = dev->data->dev_private;
 589         struct hns3_hw *hw = &hns->hw;
 590         int ret;
 591
 592         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 593         if (ret)
 594                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 595                         ret);
 596         return ret;
 597 }
 598
 599 static int
 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         bool allmulti = dev->data->all_multicast ? true : false;
 603         struct hns3_adapter *hns = dev->data->dev_private;
 604         struct hns3_hw *hw = &hns->hw;
 605         int ret;
 606
 607         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 608         if (ret)
 609                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 610                         ret);
 611         return ret;
 612 }
 613
 614 static int
 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 616 {
 617         struct hns3_adapter *hns = dev->data->dev_private;
 618         struct hns3_hw *hw = &hns->hw;
 619         int ret;
 620
 621         if (dev->data->promiscuous)
 622                 return 0;
 623
 624         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 625         if (ret)
 626                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 627                         ret);
 628         return ret;
 629 }
 630
 631 static int
 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 633 {
 634         struct hns3_adapter *hns = dev->data->dev_private;
 635         struct hns3_hw *hw = &hns->hw;
 636         int ret;
 637
 638         if (dev->data->promiscuous)
 639                 return 0;
 640
 641         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 642         if (ret)
 643                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 644                         ret);
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_restore_promisc(struct hns3_adapter *hns)
 650 {
 651         struct hns3_hw *hw = &hns->hw;
 652         bool allmulti = hw->data->all_multicast ? true : false;
 653
 654         if (hw->data->promiscuous)
 655                 return hns3vf_set_promisc_mode(hw, true, true, true);
 656
 657         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 658 }
 659
 660 static int
 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 662                              bool mmap, enum hns3_ring_type queue_type,
 663                              uint16_t queue_id)
 664 {
 665         struct hns3_vf_bind_vector_msg bind_msg;
 666         const char *op_str;
 667         uint16_t code;
 668         int ret;
 669
 670         memset(&bind_msg, 0, sizeof(bind_msg));
 671         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 672                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 673         bind_msg.vector_id = vector_id;
 674
 675         if (queue_type == HNS3_RING_TYPE_RX)
 676                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 677         else
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 679
 680         bind_msg.param[0].ring_type = queue_type;
 681         bind_msg.ring_num = 1;
 682         bind_msg.param[0].tqp_index = queue_id;
 683         op_str = mmap ? "Map" : "Unmap";
 684         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 685                                 sizeof(bind_msg), false, NULL, 0);
 686         if (ret)
 687                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 688                          op_str, queue_id, bind_msg.vector_id, ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 695 {
 696         uint8_t vec;
 697         int ret;
 698         int i;
 699
 700         /*
 701          * In hns3 network engine, vector 0 is always the misc interrupt of this
 702          * function, vector 1~N can be used respectively for the queues of the
 703          * function. Tx and Rx queues with the same number share the interrupt
 704          * vector. In the initialization clearing the all hardware mapping
 705          * relationship configurations between queues and interrupt vectors is
 706          * needed, so some error caused by the residual configurations, such as
 707          * the unexpected Tx interrupt, can be avoid. Because of the hardware
 708          * constraints in hns3 hardware engine, we have to implement clearing
 709          * the mapping relationship configurations by binding all queues to the
 710          * last interrupt vector and reserving the last interrupt vector. This
 711          * method results in a decrease of the maximum queues when upper
 712          * applications call the rte_eth_dev_configure API function to enable
 713          * Rx interrupt.
 714          */
 715         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 716         /* vec - 1: the last interrupt is reserved */
 717         hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;
 718         for (i = 0; i < hw->intr_tqps_num; i++) {
 719                 /*
 720                  * Set gap limiter and rate limiter configuration of queue's
 721                  * interrupt.
 722                  */
 723                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 724                                        HNS3_TQP_INTR_GL_DEFAULT);
 725                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 726                                        HNS3_TQP_INTR_GL_DEFAULT);
 727                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 728
 729                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 730                                                    HNS3_RING_TYPE_TX, i);
 731                 if (ret) {
 732                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 733                                           "vector: %d, ret=%d", i, vec, ret);
 734                         return ret;
 735                 }
 736
 737                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 738                                                    HNS3_RING_TYPE_RX, i);
 739                 if (ret) {
 740                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 741                                           "vector: %d, ret=%d", i, vec, ret);
 742                         return ret;
 743                 }
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int
 750 hns3vf_dev_configure(struct rte_eth_dev *dev)
 751 {
 752         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 753         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 754         struct rte_eth_conf *conf = &dev->data->dev_conf;
 755         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 756         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 757         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 758         struct rte_eth_rss_conf rss_conf;
 759         uint16_t mtu;
 760         bool gro_en;
 761         int ret;
 762
 763         /*
 764          * Hardware does not support individually enable/disable/reset the Tx or
 765          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 766          * and Rx queues at the same time. When the numbers of Tx queues
 767          * allocated by upper applications are not equal to the numbers of Rx
 768          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 769          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 770          * these fake queues are imperceptible, and can not be used by upper
 771          * applications.
 772          */
 773         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 774         if (ret) {
 775                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 776                 return ret;
 777         }
 778
 779         hw->adapter_state = HNS3_NIC_CONFIGURING;
 780         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 781                 hns3_err(hw, "setting link speed/duplex not supported");
 782                 ret = -EINVAL;
 783                 goto cfg_err;
 784         }
 785
 786         /* When RSS is not configured, redirect the packet queue 0 */
 787         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 788                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 789                 rss_conf = conf->rx_adv_conf.rss_conf;
 790                 if (rss_conf.rss_key == NULL) {
 791                         rss_conf.rss_key = rss_cfg->key;
 792                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 793                 }
 794
 795                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 796                 if (ret)
 797                         goto cfg_err;
 798         }
 799
 800         /*
 801          * If jumbo frames are enabled, MTU needs to be refreshed
 802          * according to the maximum RX packet length.
 803          */
 804         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 805                 /*
 806                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 807                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 808                  * can safely assign to "uint16_t" type variable.
 809                  */
 810                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 811                 ret = hns3vf_dev_mtu_set(dev, mtu);
 812                 if (ret)
 813                         goto cfg_err;
 814                 dev->data->mtu = mtu;
 815         }
 816
 817         ret = hns3vf_dev_configure_vlan(dev);
 818         if (ret)
 819                 goto cfg_err;
 820
 821         /* config hardware GRO */
 822         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 823         ret = hns3_config_gro(hw, gro_en);
 824         if (ret)
 825                 goto cfg_err;
 826
 827         hw->adapter_state = HNS3_NIC_CONFIGURED;
 828         return 0;
 829
 830 cfg_err:
 831         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 832         hw->adapter_state = HNS3_NIC_INITIALIZED;
 833
 834         return ret;
 835 }
 836
 837 static int
 838 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 839 {
 840         int ret;
 841
 842         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 843                                 sizeof(mtu), true, NULL, 0);
 844         if (ret)
 845                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 846
 847         return ret;
 848 }
 849
 850 static int
 851 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 852 {
 853         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 854         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 855         int ret;
 856
 857         /*
 858          * The hns3 PF/VF devices on the same port share the hardware MTU
 859          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 860          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 861          * driver, there is no need to stop the port for hns3 VF device, and the
 862          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 863          * PF's MTU.
 864          */
 865         if (rte_atomic16_read(&hw->reset.resetting)) {
 866                 hns3_err(hw, "Failed to set mtu during resetting");
 867                 return -EIO;
 868         }
 869
 870         rte_spinlock_lock(&hw->lock);
 871         ret = hns3vf_config_mtu(hw, mtu);
 872         if (ret) {
 873                 rte_spinlock_unlock(&hw->lock);
 874                 return ret;
 875         }
 876         if (frame_size > RTE_ETHER_MAX_LEN)
 877                 dev->data->dev_conf.rxmode.offloads |=
 878                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 879         else
 880                 dev->data->dev_conf.rxmode.offloads &=
 881                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 882         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 883         rte_spinlock_unlock(&hw->lock);
 884
 885         return 0;
 886 }
 887
 888 static int
 889 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 890 {
 891         struct hns3_adapter *hns = eth_dev->data->dev_private;
 892         struct hns3_hw *hw = &hns->hw;
 893         uint16_t q_num = hw->tqps_num;
 894
 895         /*
 896          * In interrupt mode, 'max_rx_queues' is set based on the number of
 897          * MSI-X interrupt resources of the hardware.
 898          */
 899         if (hw->data->dev_conf.intr_conf.rxq == 1)
 900                 q_num = hw->intr_tqps_num;
 901
 902         info->max_rx_queues = q_num;
 903         info->max_tx_queues = hw->tqps_num;
 904         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 905         info->min_rx_bufsize = hw->rx_buf_len;
 906         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 907         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 908         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 909
 910         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 911                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 912                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 913                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 914                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 915                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 916                                  DEV_RX_OFFLOAD_KEEP_CRC |
 917                                  DEV_RX_OFFLOAD_SCATTER |
 918                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 919                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 920                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 921                                  DEV_RX_OFFLOAD_RSS_HASH |
 922                                  DEV_RX_OFFLOAD_TCP_LRO);
 923         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 924         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 925                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 926                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 927                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 928                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 929                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 930                                  DEV_TX_OFFLOAD_TCP_TSO |
 931                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 932                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 933                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 934                                  info->tx_queue_offload_capa |
 935                                  hns3_txvlan_cap_get(hw));
 936
 937         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 938                 .nb_max = HNS3_MAX_RING_DESC,
 939                 .nb_min = HNS3_MIN_RING_DESC,
 940                 .nb_align = HNS3_ALIGN_RING_DESC,
 941         };
 942
 943         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 944                 .nb_max = HNS3_MAX_RING_DESC,
 945                 .nb_min = HNS3_MIN_RING_DESC,
 946                 .nb_align = HNS3_ALIGN_RING_DESC,
 947         };
 948
 949         info->vmdq_queue_num = 0;
 950
 951         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 952         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 953         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 954         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 955         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 956
 957         return 0;
 958 }
 959
 960 static void
 961 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 962 {
 963         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 964 }
 965
 966 static void
 967 hns3vf_disable_irq0(struct hns3_hw *hw)
 968 {
 969         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 970 }
 971
 972 static void
 973 hns3vf_enable_irq0(struct hns3_hw *hw)
 974 {
 975         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 976 }
 977
 978 static enum hns3vf_evt_cause
 979 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 980 {
 981         struct hns3_hw *hw = &hns->hw;
 982         enum hns3vf_evt_cause ret;
 983         uint32_t cmdq_stat_reg;
 984         uint32_t rst_ing_reg;
 985         uint32_t val;
 986
 987         /* Fetch the events from their corresponding regs */
 988         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 989
 990         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 991                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 992                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 993                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 994                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 995                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 996                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 997                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
 998                 if (clearval) {
 999                         hw->reset.stats.global_cnt++;
1000                         hns3_warn(hw, "Global reset detected, clear reset status");
1001                 } else {
1002                         hns3_schedule_delayed_reset(hns);
1003                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1004                 }
1005
1006                 ret = HNS3VF_VECTOR0_EVENT_RST;
1007                 goto out;
1008         }
1009
1010         /* Check for vector0 mailbox(=CMDQ RX) event source */
1011         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1012                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1013                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1014                 goto out;
1015         }
1016
1017         val = 0;
1018         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1019 out:
1020         if (clearval)
1021                 *clearval = val;
1022         return ret;
1023 }
1024
1025 static void
1026 hns3vf_interrupt_handler(void *param)
1027 {
1028         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1029         struct hns3_adapter *hns = dev->data->dev_private;
1030         struct hns3_hw *hw = &hns->hw;
1031         enum hns3vf_evt_cause event_cause;
1032         uint32_t clearval;
1033
1034         if (hw->irq_thread_id == 0)
1035                 hw->irq_thread_id = pthread_self();
1036
1037         /* Disable interrupt */
1038         hns3vf_disable_irq0(hw);
1039
1040         /* Read out interrupt causes */
1041         event_cause = hns3vf_check_event_cause(hns, &clearval);
1042
1043         switch (event_cause) {
1044         case HNS3VF_VECTOR0_EVENT_RST:
1045                 hns3_schedule_reset(hns);
1046                 break;
1047         case HNS3VF_VECTOR0_EVENT_MBX:
1048                 hns3_dev_handle_mbx_msg(hw);
1049                 break;
1050         default:
1051                 break;
1052         }
1053
1054         /* Clear interrupt causes */
1055         hns3vf_clear_event_cause(hw, clearval);
1056
1057         /* Enable interrupt */
1058         hns3vf_enable_irq0(hw);
1059 }
1060
1061 static int
1062 hns3vf_check_tqp_info(struct hns3_hw *hw)
1063 {
1064         uint16_t tqps_num;
1065
1066         tqps_num = hw->tqps_num;
1067         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1068                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1069                                   "range: 1~%d",
1070                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1071                 return -EINVAL;
1072         }
1073
1074         if (hw->rx_buf_len == 0)
1075                 hw->rx_buf_len = HNS3_DEFAULT_RX_BUF_LEN;
1076         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1077
1078         return 0;
1079 }
1080 static int
1081 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1082 {
1083         uint8_t resp_msg;
1084         int ret;
1085
1086         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1087                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1088                                 true, &resp_msg, sizeof(resp_msg));
1089         if (ret) {
1090                 if (ret == -ETIME) {
1091                         /*
1092                          * Getting current port based VLAN state from PF driver
1093                          * will not affect VF driver's basic function. Because
1094                          * the VF driver relies on hns3 PF kernel ether driver,
1095                          * to avoid introducing compatibility issues with older
1096                          * version of PF driver, no failure will be returned
1097                          * when the return value is ETIME. This return value has
1098                          * the following scenarios:
1099                          * 1) Firmware didn't return the results in time
1100                          * 2) the result return by firmware is timeout
1101                          * 3) the older version of kernel side PF driver does
1102                          *    not support this mailbox message.
1103                          * For scenarios 1 and 2, it is most likely that a
1104                          * hardware error has occurred, or a hardware reset has
1105                          * occurred. In this case, these errors will be caught
1106                          * by other functions.
1107                          */
1108                         PMD_INIT_LOG(WARNING,
1109                                 "failed to get PVID state for timeout, maybe "
1110                                 "kernel side PF driver doesn't support this "
1111                                 "mailbox message, or firmware didn't respond.");
1112                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1113                 } else {
1114                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1115                                 " ret = %d", ret);
1116                         return ret;
1117                 }
1118         }
1119         hw->port_base_vlan_cfg.state = resp_msg ?
1120                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1121         return 0;
1122 }
1123
1124 static int
1125 hns3vf_get_queue_info(struct hns3_hw *hw)
1126 {
1127 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1128         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1129         int ret;
1130
1131         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1132                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1133         if (ret) {
1134                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1135                 return ret;
1136         }
1137
1138         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1139         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1140         memcpy(&hw->rx_buf_len, &resp_msg[4], sizeof(uint16_t));
1141
1142         return hns3vf_check_tqp_info(hw);
1143 }
1144
1145 static int
1146 hns3vf_get_queue_depth(struct hns3_hw *hw)
1147 {
1148 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1149         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1150         int ret;
1151
1152         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1153                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1154         if (ret) {
1155                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1156                              ret);
1157                 return ret;
1158         }
1159
1160         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1161         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1162
1163         return 0;
1164 }
1165
1166 static int
1167 hns3vf_get_tc_info(struct hns3_hw *hw)
1168 {
1169         uint8_t resp_msg;
1170         int ret;
1171
1172         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1173                                 true, &resp_msg, sizeof(resp_msg));
1174         if (ret) {
1175                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1176                          ret);
1177                 return ret;
1178         }
1179
1180         hw->hw_tc_map = resp_msg;
1181
1182         return 0;
1183 }
1184
1185 static int
1186 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1187 {
1188         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1189         int ret;
1190
1191         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1192                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1193         if (ret) {
1194                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1195                 return ret;
1196         }
1197
1198         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1199
1200         return 0;
1201 }
1202
1203 static int
1204 hns3vf_get_configuration(struct hns3_hw *hw)
1205 {
1206         int ret;
1207
1208         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1209         hw->rss_dis_flag = false;
1210
1211         /* Get queue configuration from PF */
1212         ret = hns3vf_get_queue_info(hw);
1213         if (ret)
1214                 return ret;
1215
1216         /* Get queue depth info from PF */
1217         ret = hns3vf_get_queue_depth(hw);
1218         if (ret)
1219                 return ret;
1220
1221         /* Get user defined VF MAC addr from PF */
1222         ret = hns3vf_get_host_mac_addr(hw);
1223         if (ret)
1224                 return ret;
1225
1226         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1227         if (ret)
1228                 return ret;
1229
1230         /* Get tc configuration from PF */
1231         return hns3vf_get_tc_info(hw);
1232 }
1233
1234 static int
1235 hns3vf_set_tc_info(struct hns3_adapter *hns)
1236 {
1237         struct hns3_hw *hw = &hns->hw;
1238         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1239         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1240         uint8_t i;
1241
1242         hw->num_tc = 0;
1243         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1244                 if (hw->hw_tc_map & BIT(i))
1245                         hw->num_tc++;
1246
1247         if (nb_rx_q < hw->num_tc) {
1248                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1249                          nb_rx_q, hw->num_tc);
1250                 return -EINVAL;
1251         }
1252
1253         if (nb_tx_q < hw->num_tc) {
1254                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1255                          nb_tx_q, hw->num_tc);
1256                 return -EINVAL;
1257         }
1258
1259         hns3_set_rss_size(hw, nb_rx_q);
1260         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1261
1262         return 0;
1263 }
1264
1265 static void
1266 hns3vf_request_link_info(struct hns3_hw *hw)
1267 {
1268         uint8_t resp_msg;
1269         int ret;
1270
1271         if (rte_atomic16_read(&hw->reset.resetting))
1272                 return;
1273         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1274                                 &resp_msg, sizeof(resp_msg));
1275         if (ret)
1276                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1277 }
1278
1279 static int
1280 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1281 {
1282 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1283         struct hns3_hw *hw = &hns->hw;
1284         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1285         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1286         uint8_t is_kill = on ? 0 : 1;
1287
1288         msg_data[0] = is_kill;
1289         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1290         memcpy(&msg_data[3], &proto, sizeof(proto));
1291
1292         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1293                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1294                                  0);
1295 }
1296
1297 static int
1298 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1299 {
1300         struct hns3_adapter *hns = dev->data->dev_private;
1301         struct hns3_hw *hw = &hns->hw;
1302         int ret;
1303
1304         if (rte_atomic16_read(&hw->reset.resetting)) {
1305                 hns3_err(hw,
1306                          "vf set vlan id failed during resetting, vlan_id =%u",
1307                          vlan_id);
1308                 return -EIO;
1309         }
1310         rte_spinlock_lock(&hw->lock);
1311         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1312         rte_spinlock_unlock(&hw->lock);
1313         if (ret)
1314                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1315                          vlan_id, ret);
1316
1317         return ret;
1318 }
1319
1320 static int
1321 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1322 {
1323         uint8_t msg_data;
1324         int ret;
1325
1326         msg_data = enable ? 1 : 0;
1327         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1328                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1329         if (ret)
1330                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1331
1332         return ret;
1333 }
1334
1335 static int
1336 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1337 {
1338         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1339         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1340         unsigned int tmp_mask;
1341         int ret = 0;
1342
1343         if (rte_atomic16_read(&hw->reset.resetting)) {
1344                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1345                              "mask = 0x%x", mask);
1346                 return -EIO;
1347         }
1348
1349         tmp_mask = (unsigned int)mask;
1350         /* Vlan stripping setting */
1351         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1352                 rte_spinlock_lock(&hw->lock);
1353                 /* Enable or disable VLAN stripping */
1354                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1355                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1356                 else
1357                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1358                 rte_spinlock_unlock(&hw->lock);
1359         }
1360
1361         return ret;
1362 }
1363
1364 static int
1365 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1366 {
1367         struct rte_vlan_filter_conf *vfc;
1368         struct hns3_hw *hw = &hns->hw;
1369         uint16_t vlan_id;
1370         uint64_t vbit;
1371         uint64_t ids;
1372         int ret = 0;
1373         uint32_t i;
1374
1375         vfc = &hw->data->vlan_filter_conf;
1376         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1377                 if (vfc->ids[i] == 0)
1378                         continue;
1379                 ids = vfc->ids[i];
1380                 while (ids) {
1381                         /*
1382                          * 64 means the num bits of ids, one bit corresponds to
1383                          * one vlan id
1384                          */
1385                         vlan_id = 64 * i;
1386                         /* count trailing zeroes */
1387                         vbit = ~ids & (ids - 1);
1388                         /* clear least significant bit set */
1389                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1390                         for (; vbit;) {
1391                                 vbit >>= 1;
1392                                 vlan_id++;
1393                         }
1394                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1395                         if (ret) {
1396                                 hns3_err(hw,
1397                                          "VF handle vlan table failed, ret =%d, on = %d",
1398                                          ret, on);
1399                                 return ret;
1400                         }
1401                 }
1402         }
1403
1404         return ret;
1405 }
1406
1407 static int
1408 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1409 {
1410         return hns3vf_handle_all_vlan_table(hns, 0);
1411 }
1412
1413 static int
1414 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1415 {
1416         struct hns3_hw *hw = &hns->hw;
1417         struct rte_eth_conf *dev_conf;
1418         bool en;
1419         int ret;
1420
1421         dev_conf = &hw->data->dev_conf;
1422         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1423                                                                    : false;
1424         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1425         if (ret)
1426                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1427                          ret);
1428         return ret;
1429 }
1430
1431 static int
1432 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1433 {
1434         struct hns3_adapter *hns = dev->data->dev_private;
1435         struct rte_eth_dev_data *data = dev->data;
1436         struct hns3_hw *hw = &hns->hw;
1437         int ret;
1438
1439         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1440             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1441             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1442                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1443                               "or hw_vlan_insert_pvid is not support!");
1444         }
1445
1446         /* Apply vlan offload setting */
1447         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1448         if (ret)
1449                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1450
1451         return ret;
1452 }
1453
1454 static int
1455 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1456 {
1457         uint8_t msg_data;
1458
1459         msg_data = alive ? 1 : 0;
1460         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1461                                  sizeof(msg_data), false, NULL, 0);
1462 }
1463
1464 static void
1465 hns3vf_keep_alive_handler(void *param)
1466 {
1467         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1468         struct hns3_adapter *hns = eth_dev->data->dev_private;
1469         struct hns3_hw *hw = &hns->hw;
1470         uint8_t respmsg;
1471         int ret;
1472
1473         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1474                                 false, &respmsg, sizeof(uint8_t));
1475         if (ret)
1476                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1477                          ret);
1478
1479         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1480                           eth_dev);
1481 }
1482
1483 static void
1484 hns3vf_service_handler(void *param)
1485 {
1486         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1487         struct hns3_adapter *hns = eth_dev->data->dev_private;
1488         struct hns3_hw *hw = &hns->hw;
1489
1490         /*
1491          * The query link status and reset processing are executed in the
1492          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1493          * and the query operation will time out after 30ms. In the case of
1494          * multiple PF/VFs, each query failure timeout causes the IMP reset
1495          * interrupt to fail to respond within 100ms.
1496          * Before querying the link status, check whether there is a reset
1497          * pending, and if so, abandon the query.
1498          */
1499         if (!hns3vf_is_reset_pending(hns))
1500                 hns3vf_request_link_info(hw);
1501         else
1502                 hns3_warn(hw, "Cancel the query when reset is pending");
1503
1504         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1505                           eth_dev);
1506 }
1507
1508 static int
1509 hns3_query_vf_resource(struct hns3_hw *hw)
1510 {
1511         struct hns3_vf_res_cmd *req;
1512         struct hns3_cmd_desc desc;
1513         uint16_t num_msi;
1514         int ret;
1515
1516         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1517         ret = hns3_cmd_send(hw, &desc, 1);
1518         if (ret) {
1519                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1520                 return ret;
1521         }
1522
1523         req = (struct hns3_vf_res_cmd *)desc.data;
1524         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1525                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
1526         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1527                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1528                          num_msi, HNS3_MIN_VECTOR_NUM);
1529                 return -EINVAL;
1530         }
1531
1532         hw->num_msi = num_msi;
1533
1534         return 0;
1535 }
1536
1537 static int
1538 hns3vf_init_hardware(struct hns3_adapter *hns)
1539 {
1540         struct hns3_hw *hw = &hns->hw;
1541         uint16_t mtu = hw->data->mtu;
1542         int ret;
1543
1544         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1545         if (ret)
1546                 return ret;
1547
1548         ret = hns3vf_config_mtu(hw, mtu);
1549         if (ret)
1550                 goto err_init_hardware;
1551
1552         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1553         if (ret) {
1554                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1555                 goto err_init_hardware;
1556         }
1557
1558         ret = hns3_config_gro(hw, false);
1559         if (ret) {
1560                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1561                 goto err_init_hardware;
1562         }
1563
1564         /*
1565          * In the initialization clearing the all hardware mapping relationship
1566          * configurations between queues and interrupt vectors is needed, so
1567          * some error caused by the residual configurations, such as the
1568          * unexpected interrupt, can be avoid.
1569          */
1570         ret = hns3vf_init_ring_with_vector(hw);
1571         if (ret) {
1572                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1573                 goto err_init_hardware;
1574         }
1575
1576         ret = hns3vf_set_alive(hw, true);
1577         if (ret) {
1578                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1579                 goto err_init_hardware;
1580         }
1581
1582         hns3vf_request_link_info(hw);
1583         return 0;
1584
1585 err_init_hardware:
1586         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1587         return ret;
1588 }
1589
1590 static int
1591 hns3vf_clear_vport_list(struct hns3_hw *hw)
1592 {
1593         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1594                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1595                                  NULL, 0);
1596 }
1597
1598 static int
1599 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1600 {
1601         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1602         struct hns3_adapter *hns = eth_dev->data->dev_private;
1603         struct hns3_hw *hw = &hns->hw;
1604         int ret;
1605
1606         PMD_INIT_FUNC_TRACE();
1607
1608         /* Get hardware io base address from pcie BAR2 IO space */
1609         hw->io_base = pci_dev->mem_resource[2].addr;
1610
1611         /* Firmware command queue initialize */
1612         ret = hns3_cmd_init_queue(hw);
1613         if (ret) {
1614                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1615                 goto err_cmd_init_queue;
1616         }
1617
1618         /* Firmware command initialize */
1619         ret = hns3_cmd_init(hw);
1620         if (ret) {
1621                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1622                 goto err_cmd_init;
1623         }
1624
1625         /* Get VF resource */
1626         ret = hns3_query_vf_resource(hw);
1627         if (ret)
1628                 goto err_cmd_init;
1629
1630         rte_spinlock_init(&hw->mbx_resp.lock);
1631
1632         hns3vf_clear_event_cause(hw, 0);
1633
1634         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1635                                          hns3vf_interrupt_handler, eth_dev);
1636         if (ret) {
1637                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1638                 goto err_intr_callback_register;
1639         }
1640
1641         /* Enable interrupt */
1642         rte_intr_enable(&pci_dev->intr_handle);
1643         hns3vf_enable_irq0(hw);
1644
1645         /* Get configuration from PF */
1646         ret = hns3vf_get_configuration(hw);
1647         if (ret) {
1648                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1649                 goto err_get_config;
1650         }
1651
1652         /*
1653          * The hns3 PF ethdev driver in kernel support setting VF MAC address
1654          * on the host by "ip link set ..." command. To avoid some incorrect
1655          * scenes, for example, hns3 VF PMD driver fails to receive and send
1656          * packets after user configure the MAC address by using the
1657          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
1658          * address strategy as the hns3 kernel ethdev driver in the
1659          * initialization. If user configure a MAC address by the ip command
1660          * for VF device, then hns3 VF PMD driver will start with it, otherwise
1661          * start with a random MAC address in the initialization.
1662          */
1663         ret = rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr);
1664         if (ret)
1665                 rte_eth_random_addr(hw->mac.mac_addr);
1666
1667         ret = hns3vf_clear_vport_list(hw);
1668         if (ret) {
1669                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1670                 goto err_get_config;
1671         }
1672
1673         ret = hns3vf_init_hardware(hns);
1674         if (ret)
1675                 goto err_get_config;
1676
1677         hns3_set_default_rss_args(hw);
1678
1679         return 0;
1680
1681 err_get_config:
1682         hns3vf_disable_irq0(hw);
1683         rte_intr_disable(&pci_dev->intr_handle);
1684         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1685                              eth_dev);
1686 err_intr_callback_register:
1687 err_cmd_init:
1688         hns3_cmd_uninit(hw);
1689         hns3_cmd_destroy_queue(hw);
1690 err_cmd_init_queue:
1691         hw->io_base = NULL;
1692
1693         return ret;
1694 }
1695
1696 static void
1697 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1698 {
1699         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1700         struct hns3_adapter *hns = eth_dev->data->dev_private;
1701         struct hns3_hw *hw = &hns->hw;
1702
1703         PMD_INIT_FUNC_TRACE();
1704
1705         hns3_rss_uninit(hns);
1706         (void)hns3_config_gro(hw, false);
1707         (void)hns3vf_set_alive(hw, false);
1708         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1709         hns3vf_disable_irq0(hw);
1710         rte_intr_disable(&pci_dev->intr_handle);
1711         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1712                              eth_dev);
1713         hns3_cmd_uninit(hw);
1714         hns3_cmd_destroy_queue(hw);
1715         hw->io_base = NULL;
1716 }
1717
1718 static int
1719 hns3vf_do_stop(struct hns3_adapter *hns)
1720 {
1721         struct hns3_hw *hw = &hns->hw;
1722         bool reset_queue;
1723
1724         hw->mac.link_status = ETH_LINK_DOWN;
1725
1726         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1727                 hns3vf_configure_mac_addr(hns, true);
1728                 reset_queue = true;
1729         } else
1730                 reset_queue = false;
1731         return hns3_stop_queues(hns, reset_queue);
1732 }
1733
1734 static void
1735 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1736 {
1737         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1738         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1739         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1740         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1741         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1742         uint16_t q_id;
1743
1744         if (dev->data->dev_conf.intr_conf.rxq == 0)
1745                 return;
1746
1747         /* unmap the ring with vector */
1748         if (rte_intr_allow_others(intr_handle)) {
1749                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1750                 base = RTE_INTR_VEC_RXTX_OFFSET;
1751         }
1752         if (rte_intr_dp_is_en(intr_handle)) {
1753                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1754                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1755                                                            HNS3_RING_TYPE_RX,
1756                                                            q_id);
1757                         if (vec < base + intr_handle->nb_efd - 1)
1758                                 vec++;
1759                 }
1760         }
1761         /* Clean datapath event and queue/vec mapping */
1762         rte_intr_efd_disable(intr_handle);
1763         if (intr_handle->intr_vec) {
1764                 rte_free(intr_handle->intr_vec);
1765                 intr_handle->intr_vec = NULL;
1766         }
1767 }
1768
1769 static void
1770 hns3vf_dev_stop(struct rte_eth_dev *dev)
1771 {
1772         struct hns3_adapter *hns = dev->data->dev_private;
1773         struct hns3_hw *hw = &hns->hw;
1774
1775         PMD_INIT_FUNC_TRACE();
1776
1777         hw->adapter_state = HNS3_NIC_STOPPING;
1778         hns3_set_rxtx_function(dev);
1779         rte_wmb();
1780         /* Disable datapath on secondary process. */
1781         hns3_mp_req_stop_rxtx(dev);
1782         /* Prevent crashes when queues are still in use. */
1783         rte_delay_ms(hw->tqps_num);
1784
1785         rte_spinlock_lock(&hw->lock);
1786         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1787                 hns3vf_do_stop(hns);
1788                 hns3vf_unmap_rx_interrupt(dev);
1789                 hns3_dev_release_mbufs(hns);
1790                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1791         }
1792         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1793         rte_spinlock_unlock(&hw->lock);
1794 }
1795
1796 static void
1797 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1798 {
1799         struct hns3_adapter *hns = eth_dev->data->dev_private;
1800         struct hns3_hw *hw = &hns->hw;
1801
1802         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1803                 return;
1804
1805         if (hw->adapter_state == HNS3_NIC_STARTED)
1806                 hns3vf_dev_stop(eth_dev);
1807
1808         hw->adapter_state = HNS3_NIC_CLOSING;
1809         hns3_reset_abort(hns);
1810         hw->adapter_state = HNS3_NIC_CLOSED;
1811         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1812         hns3vf_configure_all_mc_mac_addr(hns, true);
1813         hns3vf_remove_all_vlan_table(hns);
1814         hns3vf_uninit_vf(eth_dev);
1815         hns3_free_all_queues(eth_dev);
1816         rte_free(hw->reset.wait_data);
1817         rte_free(eth_dev->process_private);
1818         eth_dev->process_private = NULL;
1819         hns3_mp_uninit_primary();
1820         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1821 }
1822
1823 static int
1824 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1825                       size_t fw_size)
1826 {
1827         struct hns3_adapter *hns = eth_dev->data->dev_private;
1828         struct hns3_hw *hw = &hns->hw;
1829         uint32_t version = hw->fw_version;
1830         int ret;
1831
1832         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1833                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1834                                       HNS3_FW_VERSION_BYTE3_S),
1835                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1836                                       HNS3_FW_VERSION_BYTE2_S),
1837                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1838                                       HNS3_FW_VERSION_BYTE1_S),
1839                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1840                                       HNS3_FW_VERSION_BYTE0_S));
1841         ret += 1; /* add the size of '\0' */
1842         if (fw_size < (uint32_t)ret)
1843                 return ret;
1844         else
1845                 return 0;
1846 }
1847
1848 static int
1849 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1850                        __rte_unused int wait_to_complete)
1851 {
1852         struct hns3_adapter *hns = eth_dev->data->dev_private;
1853         struct hns3_hw *hw = &hns->hw;
1854         struct hns3_mac *mac = &hw->mac;
1855         struct rte_eth_link new_link;
1856
1857         memset(&new_link, 0, sizeof(new_link));
1858         switch (mac->link_speed) {
1859         case ETH_SPEED_NUM_10M:
1860         case ETH_SPEED_NUM_100M:
1861         case ETH_SPEED_NUM_1G:
1862         case ETH_SPEED_NUM_10G:
1863         case ETH_SPEED_NUM_25G:
1864         case ETH_SPEED_NUM_40G:
1865         case ETH_SPEED_NUM_50G:
1866         case ETH_SPEED_NUM_100G:
1867                 new_link.link_speed = mac->link_speed;
1868                 break;
1869         default:
1870                 new_link.link_speed = ETH_SPEED_NUM_100M;
1871                 break;
1872         }
1873
1874         new_link.link_duplex = mac->link_duplex;
1875         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1876         new_link.link_autoneg =
1877             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1878
1879         return rte_eth_linkstatus_set(eth_dev, &new_link);
1880 }
1881
1882 static int
1883 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1884 {
1885         struct hns3_hw *hw = &hns->hw;
1886         int ret;
1887
1888         ret = hns3vf_set_tc_info(hns);
1889         if (ret)
1890                 return ret;
1891
1892         ret = hns3_start_queues(hns, reset_queue);
1893         if (ret)
1894                 hns3_err(hw, "Failed to start queues: %d", ret);
1895
1896         return ret;
1897 }
1898
1899 static int
1900 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1901 {
1902         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1903         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1904         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1905         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1906         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1907         uint32_t intr_vector;
1908         uint16_t q_id;
1909         int ret;
1910
1911         if (dev->data->dev_conf.intr_conf.rxq == 0)
1912                 return 0;
1913
1914         /* disable uio/vfio intr/eventfd mapping */
1915         rte_intr_disable(intr_handle);
1916
1917         /* check and configure queue intr-vector mapping */
1918         if (rte_intr_cap_multiple(intr_handle) ||
1919             !RTE_ETH_DEV_SRIOV(dev).active) {
1920                 intr_vector = hw->used_rx_queues;
1921                 /* It creates event fd for each intr vector when MSIX is used */
1922                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1923                         return -EINVAL;
1924         }
1925         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1926                 intr_handle->intr_vec =
1927                         rte_zmalloc("intr_vec",
1928                                     hw->used_rx_queues * sizeof(int), 0);
1929                 if (intr_handle->intr_vec == NULL) {
1930                         hns3_err(hw, "Failed to allocate %d rx_queues"
1931                                      " intr_vec", hw->used_rx_queues);
1932                         ret = -ENOMEM;
1933                         goto vf_alloc_intr_vec_error;
1934                 }
1935         }
1936
1937         if (rte_intr_allow_others(intr_handle)) {
1938                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1939                 base = RTE_INTR_VEC_RXTX_OFFSET;
1940         }
1941         if (rte_intr_dp_is_en(intr_handle)) {
1942                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1943                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
1944                                                            HNS3_RING_TYPE_RX,
1945                                                            q_id);
1946                         if (ret)
1947                                 goto vf_bind_vector_error;
1948                         intr_handle->intr_vec[q_id] = vec;
1949                         if (vec < base + intr_handle->nb_efd - 1)
1950                                 vec++;
1951                 }
1952         }
1953         rte_intr_enable(intr_handle);
1954         return 0;
1955
1956 vf_bind_vector_error:
1957         rte_intr_efd_disable(intr_handle);
1958         if (intr_handle->intr_vec) {
1959                 free(intr_handle->intr_vec);
1960                 intr_handle->intr_vec = NULL;
1961         }
1962         return ret;
1963 vf_alloc_intr_vec_error:
1964         rte_intr_efd_disable(intr_handle);
1965         return ret;
1966 }
1967
1968 static int
1969 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
1970 {
1971         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1972         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1973         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1974         uint16_t q_id;
1975         int ret;
1976
1977         if (dev->data->dev_conf.intr_conf.rxq == 0)
1978                 return 0;
1979
1980         if (rte_intr_dp_is_en(intr_handle)) {
1981                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1982                         ret = hns3vf_bind_ring_with_vector(hw,
1983                                         intr_handle->intr_vec[q_id], true,
1984                                         HNS3_RING_TYPE_RX, q_id);
1985                         if (ret)
1986                                 return ret;
1987                 }
1988         }
1989
1990         return 0;
1991 }
1992
1993 static void
1994 hns3vf_restore_filter(struct rte_eth_dev *dev)
1995 {
1996         hns3_restore_rss_filter(dev);
1997 }
1998
1999 static int
2000 hns3vf_dev_start(struct rte_eth_dev *dev)
2001 {
2002         struct hns3_adapter *hns = dev->data->dev_private;
2003         struct hns3_hw *hw = &hns->hw;
2004         int ret;
2005
2006         PMD_INIT_FUNC_TRACE();
2007         if (rte_atomic16_read(&hw->reset.resetting))
2008                 return -EBUSY;
2009
2010         rte_spinlock_lock(&hw->lock);
2011         hw->adapter_state = HNS3_NIC_STARTING;
2012         ret = hns3vf_do_start(hns, true);
2013         if (ret) {
2014                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2015                 rte_spinlock_unlock(&hw->lock);
2016                 return ret;
2017         }
2018         ret = hns3vf_map_rx_interrupt(dev);
2019         if (ret) {
2020                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2021                 rte_spinlock_unlock(&hw->lock);
2022                 return ret;
2023         }
2024         hw->adapter_state = HNS3_NIC_STARTED;
2025         rte_spinlock_unlock(&hw->lock);
2026
2027         hns3_set_rxtx_function(dev);
2028         hns3_mp_req_start_rxtx(dev);
2029         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2030
2031         hns3vf_restore_filter(dev);
2032
2033         /* Enable interrupt of all rx queues before enabling queues */
2034         hns3_dev_all_rx_queue_intr_enable(hw, true);
2035         /*
2036          * When finished the initialization, enable queues to receive/transmit
2037          * packets.
2038          */
2039         hns3_enable_all_queues(hw, true);
2040
2041         return ret;
2042 }
2043
2044 static bool
2045 is_vf_reset_done(struct hns3_hw *hw)
2046 {
2047 #define HNS3_FUN_RST_ING_BITS \
2048         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2049          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2050          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2051          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2052
2053         uint32_t val;
2054
2055         if (hw->reset.level == HNS3_VF_RESET) {
2056                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2057                 if (val & HNS3_VF_RST_ING_BIT)
2058                         return false;
2059         } else {
2060                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2061                 if (val & HNS3_FUN_RST_ING_BITS)
2062                         return false;
2063         }
2064         return true;
2065 }
2066
2067 bool
2068 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2069 {
2070         struct hns3_hw *hw = &hns->hw;
2071         enum hns3_reset_level reset;
2072
2073         hns3vf_check_event_cause(hns, NULL);
2074         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2075         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2076                 hns3_warn(hw, "High level reset %d is pending", reset);
2077                 return true;
2078         }
2079         return false;
2080 }
2081
2082 static int
2083 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2084 {
2085         struct hns3_hw *hw = &hns->hw;
2086         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2087         struct timeval tv;
2088
2089         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2090                 /*
2091                  * After vf reset is ready, the PF may not have completed
2092                  * the reset processing. The vf sending mbox to PF may fail
2093                  * during the pf reset, so it is better to add extra delay.
2094                  */
2095                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2096                     hw->reset.level == HNS3_FLR_RESET)
2097                         return 0;
2098                 /* Reset retry process, no need to add extra delay. */
2099                 if (hw->reset.attempts)
2100                         return 0;
2101                 if (wait_data->check_completion == NULL)
2102                         return 0;
2103
2104                 wait_data->check_completion = NULL;
2105                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2106                 wait_data->count = 1;
2107                 wait_data->result = HNS3_WAIT_REQUEST;
2108                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2109                                   wait_data);
2110                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2111                 return -EAGAIN;
2112         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2113                 gettimeofday(&tv, NULL);
2114                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2115                           tv.tv_sec, tv.tv_usec);
2116                 return -ETIME;
2117         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2118                 return -EAGAIN;
2119
2120         wait_data->hns = hns;
2121         wait_data->check_completion = is_vf_reset_done;
2122         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2123                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2124         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2125         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2126         wait_data->result = HNS3_WAIT_REQUEST;
2127         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2128         return -EAGAIN;
2129 }
2130
2131 static int
2132 hns3vf_prepare_reset(struct hns3_adapter *hns)
2133 {
2134         struct hns3_hw *hw = &hns->hw;
2135         int ret = 0;
2136
2137         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2138                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2139                                         0, true, NULL, 0);
2140         }
2141         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2142
2143         return ret;
2144 }
2145
2146 static int
2147 hns3vf_stop_service(struct hns3_adapter *hns)
2148 {
2149         struct hns3_hw *hw = &hns->hw;
2150         struct rte_eth_dev *eth_dev;
2151
2152         eth_dev = &rte_eth_devices[hw->data->port_id];
2153         if (hw->adapter_state == HNS3_NIC_STARTED)
2154                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2155         hw->mac.link_status = ETH_LINK_DOWN;
2156
2157         hns3_set_rxtx_function(eth_dev);
2158         rte_wmb();
2159         /* Disable datapath on secondary process. */
2160         hns3_mp_req_stop_rxtx(eth_dev);
2161         rte_delay_ms(hw->tqps_num);
2162
2163         rte_spinlock_lock(&hw->lock);
2164         if (hw->adapter_state == HNS3_NIC_STARTED ||
2165             hw->adapter_state == HNS3_NIC_STOPPING) {
2166                 hns3vf_do_stop(hns);
2167                 hw->reset.mbuf_deferred_free = true;
2168         } else
2169                 hw->reset.mbuf_deferred_free = false;
2170
2171         /*
2172          * It is cumbersome for hardware to pick-and-choose entries for deletion
2173          * from table space. Hence, for function reset software intervention is
2174          * required to delete the entries.
2175          */
2176         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2177                 hns3vf_configure_all_mc_mac_addr(hns, true);
2178         rte_spinlock_unlock(&hw->lock);
2179
2180         return 0;
2181 }
2182
2183 static int
2184 hns3vf_start_service(struct hns3_adapter *hns)
2185 {
2186         struct hns3_hw *hw = &hns->hw;
2187         struct rte_eth_dev *eth_dev;
2188
2189         eth_dev = &rte_eth_devices[hw->data->port_id];
2190         hns3_set_rxtx_function(eth_dev);
2191         hns3_mp_req_start_rxtx(eth_dev);
2192         if (hw->adapter_state == HNS3_NIC_STARTED) {
2193                 hns3vf_service_handler(eth_dev);
2194
2195                 /* Enable interrupt of all rx queues before enabling queues */
2196                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2197                 /*
2198                  * When finished the initialization, enable queues to receive
2199                  * and transmit packets.
2200                  */
2201                 hns3_enable_all_queues(hw, true);
2202         }
2203
2204         return 0;
2205 }
2206
2207 static int
2208 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2209 {
2210         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2211         struct rte_ether_addr *hw_mac;
2212         int ret;
2213
2214         /*
2215          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2216          * on the host by "ip link set ..." command. If the hns3 PF kernel
2217          * ethdev driver sets the MAC address for VF device after the
2218          * initialization of the related VF device, the PF driver will notify
2219          * VF driver to reset VF device to make the new MAC address effective
2220          * immediately. The hns3 VF PMD driver should check whether the MAC
2221          * address has been changed by the PF kernel ethdev driver, if changed
2222          * VF driver should configure hardware using the new MAC address in the
2223          * recovering hardware configuration stage of the reset process.
2224          */
2225         ret = hns3vf_get_host_mac_addr(hw);
2226         if (ret)
2227                 return ret;
2228
2229         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2230         ret = rte_is_zero_ether_addr(hw_mac);
2231         if (ret) {
2232                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2233         } else {
2234                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2235                 if (!ret) {
2236                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2237                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2238                                               &hw->data->mac_addrs[0]);
2239                         hns3_warn(hw, "Default MAC address has been changed to:"
2240                                   " %s by the host PF kernel ethdev driver",
2241                                   mac_str);
2242                 }
2243         }
2244
2245         return 0;
2246 }
2247
2248 static int
2249 hns3vf_restore_conf(struct hns3_adapter *hns)
2250 {
2251         struct hns3_hw *hw = &hns->hw;
2252         int ret;
2253
2254         ret = hns3vf_check_default_mac_change(hw);
2255         if (ret)
2256                 return ret;
2257
2258         ret = hns3vf_configure_mac_addr(hns, false);
2259         if (ret)
2260                 return ret;
2261
2262         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2263         if (ret)
2264                 goto err_mc_mac;
2265
2266         ret = hns3vf_restore_promisc(hns);
2267         if (ret)
2268                 goto err_vlan_table;
2269
2270         ret = hns3vf_restore_vlan_conf(hns);
2271         if (ret)
2272                 goto err_vlan_table;
2273
2274         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2275         if (ret)
2276                 goto err_vlan_table;
2277
2278         ret = hns3vf_restore_rx_interrupt(hw);
2279         if (ret)
2280                 goto err_vlan_table;
2281
2282         ret = hns3_restore_gro_conf(hw);
2283         if (ret)
2284                 goto err_vlan_table;
2285
2286         if (hw->adapter_state == HNS3_NIC_STARTED) {
2287                 ret = hns3vf_do_start(hns, false);
2288                 if (ret)
2289                         goto err_vlan_table;
2290                 hns3_info(hw, "hns3vf dev restart successful!");
2291         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2292                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2293         return 0;
2294
2295 err_vlan_table:
2296         hns3vf_configure_all_mc_mac_addr(hns, true);
2297 err_mc_mac:
2298         hns3vf_configure_mac_addr(hns, true);
2299         return ret;
2300 }
2301
2302 static enum hns3_reset_level
2303 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2304 {
2305         enum hns3_reset_level reset_level;
2306
2307         /* return the highest priority reset level amongst all */
2308         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2309                 reset_level = HNS3_VF_RESET;
2310         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2311                 reset_level = HNS3_VF_FULL_RESET;
2312         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2313                 reset_level = HNS3_VF_PF_FUNC_RESET;
2314         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2315                 reset_level = HNS3_VF_FUNC_RESET;
2316         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2317                 reset_level = HNS3_FLR_RESET;
2318         else
2319                 reset_level = HNS3_NONE_RESET;
2320
2321         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2322                 return HNS3_NONE_RESET;
2323
2324         return reset_level;
2325 }
2326
2327 static void
2328 hns3vf_reset_service(void *param)
2329 {
2330         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2331         struct hns3_hw *hw = &hns->hw;
2332         enum hns3_reset_level reset_level;
2333         struct timeval tv_delta;
2334         struct timeval tv_start;
2335         struct timeval tv;
2336         uint64_t msec;
2337
2338         /*
2339          * The interrupt is not triggered within the delay time.
2340          * The interrupt may have been lost. It is necessary to handle
2341          * the interrupt to recover from the error.
2342          */
2343         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2344                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2345                 hns3_err(hw, "Handling interrupts in delayed tasks");
2346                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2347                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2348                 if (reset_level == HNS3_NONE_RESET) {
2349                         hns3_err(hw, "No reset level is set, try global reset");
2350                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2351                 }
2352         }
2353         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2354
2355         /*
2356          * Hardware reset has been notified, we now have to poll & check if
2357          * hardware has actually completed the reset sequence.
2358          */
2359         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2360         if (reset_level != HNS3_NONE_RESET) {
2361                 gettimeofday(&tv_start, NULL);
2362                 hns3_reset_process(hns, reset_level);
2363                 gettimeofday(&tv, NULL);
2364                 timersub(&tv, &tv_start, &tv_delta);
2365                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2366                        tv_delta.tv_usec / USEC_PER_MSEC;
2367                 if (msec > HNS3_RESET_PROCESS_MS)
2368                         hns3_err(hw, "%d handle long time delta %" PRIx64
2369                                  " ms time=%ld.%.6ld",
2370                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2371         }
2372 }
2373
2374 static int
2375 hns3vf_reinit_dev(struct hns3_adapter *hns)
2376 {
2377         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2378         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2379         struct hns3_hw *hw = &hns->hw;
2380         int ret;
2381
2382         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2383                 rte_intr_disable(&pci_dev->intr_handle);
2384                 hns3vf_set_bus_master(pci_dev, true);
2385         }
2386
2387         /* Firmware command initialize */
2388         ret = hns3_cmd_init(hw);
2389         if (ret) {
2390                 hns3_err(hw, "Failed to init cmd: %d", ret);
2391                 return ret;
2392         }
2393
2394         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2395                 /*
2396                  * UIO enables msix by writing the pcie configuration space
2397                  * vfio_pci enables msix in rte_intr_enable.
2398                  */
2399                 if (pci_dev->kdrv == RTE_KDRV_IGB_UIO ||
2400                     pci_dev->kdrv == RTE_KDRV_UIO_GENERIC) {
2401                         if (hns3vf_enable_msix(pci_dev, true))
2402                                 hns3_err(hw, "Failed to enable msix");
2403                 }
2404
2405                 rte_intr_enable(&pci_dev->intr_handle);
2406         }
2407
2408         ret = hns3_reset_all_queues(hns);
2409         if (ret) {
2410                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2411                 return ret;
2412         }
2413
2414         ret = hns3vf_init_hardware(hns);
2415         if (ret) {
2416                 hns3_err(hw, "Failed to init hardware: %d", ret);
2417                 return ret;
2418         }
2419
2420         return 0;
2421 }
2422
2423 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2424         .dev_start          = hns3vf_dev_start,
2425         .dev_stop           = hns3vf_dev_stop,
2426         .dev_close          = hns3vf_dev_close,
2427         .mtu_set            = hns3vf_dev_mtu_set,
2428         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2429         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2430         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2431         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2432         .stats_get          = hns3_stats_get,
2433         .stats_reset        = hns3_stats_reset,
2434         .xstats_get         = hns3_dev_xstats_get,
2435         .xstats_get_names   = hns3_dev_xstats_get_names,
2436         .xstats_reset       = hns3_dev_xstats_reset,
2437         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2438         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2439         .dev_infos_get      = hns3vf_dev_infos_get,
2440         .fw_version_get     = hns3vf_fw_version_get,
2441         .rx_queue_setup     = hns3_rx_queue_setup,
2442         .tx_queue_setup     = hns3_tx_queue_setup,
2443         .rx_queue_release   = hns3_dev_rx_queue_release,
2444         .tx_queue_release   = hns3_dev_tx_queue_release,
2445         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2446         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2447         .dev_configure      = hns3vf_dev_configure,
2448         .mac_addr_add       = hns3vf_add_mac_addr,
2449         .mac_addr_remove    = hns3vf_remove_mac_addr,
2450         .mac_addr_set       = hns3vf_set_default_mac_addr,
2451         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2452         .link_update        = hns3vf_dev_link_update,
2453         .rss_hash_update    = hns3_dev_rss_hash_update,
2454         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2455         .reta_update        = hns3_dev_rss_reta_update,
2456         .reta_query         = hns3_dev_rss_reta_query,
2457         .filter_ctrl        = hns3_dev_filter_ctrl,
2458         .vlan_filter_set    = hns3vf_vlan_filter_set,
2459         .vlan_offload_set   = hns3vf_vlan_offload_set,
2460         .get_reg            = hns3_get_regs,
2461         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2462 };
2463
2464 static const struct hns3_reset_ops hns3vf_reset_ops = {
2465         .reset_service       = hns3vf_reset_service,
2466         .stop_service        = hns3vf_stop_service,
2467         .prepare_reset       = hns3vf_prepare_reset,
2468         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2469         .reinit_dev          = hns3vf_reinit_dev,
2470         .restore_conf        = hns3vf_restore_conf,
2471         .start_service       = hns3vf_start_service,
2472 };
2473
2474 static int
2475 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2476 {
2477         struct rte_device *dev = eth_dev->device;
2478         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
2479         struct hns3_adapter *hns = eth_dev->data->dev_private;
2480         struct hns3_hw *hw = &hns->hw;
2481         uint8_t revision;
2482         int ret;
2483
2484         PMD_INIT_FUNC_TRACE();
2485
2486         /* Get PCI revision id */
2487         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
2488                                   HNS3_PCI_REVISION_ID);
2489         if (ret != HNS3_PCI_REVISION_ID_LEN) {
2490                 PMD_INIT_LOG(ERR, "Failed to read pci revision id, ret = %d",
2491                              ret);
2492                 return -EIO;
2493         }
2494         hw->revision = revision;
2495
2496         eth_dev->process_private = (struct hns3_process_private *)
2497             rte_zmalloc_socket("hns3_filter_list",
2498                                sizeof(struct hns3_process_private),
2499                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2500         if (eth_dev->process_private == NULL) {
2501                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2502                 return -ENOMEM;
2503         }
2504
2505         /* initialize flow filter lists */
2506         hns3_filterlist_init(eth_dev);
2507
2508         hns3_set_rxtx_function(eth_dev);
2509         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2510         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2511                 hns3_mp_init_secondary();
2512                 hw->secondary_cnt++;
2513                 return 0;
2514         }
2515
2516         hns3_mp_init_primary();
2517
2518         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2519         hns->is_vf = true;
2520         hw->data = eth_dev->data;
2521
2522         ret = hns3_reset_init(hw);
2523         if (ret)
2524                 goto err_init_reset;
2525         hw->reset.ops = &hns3vf_reset_ops;
2526
2527         ret = hns3vf_init_vf(eth_dev);
2528         if (ret) {
2529                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2530                 goto err_init_vf;
2531         }
2532
2533         /* Allocate memory for storing MAC addresses */
2534         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2535                                                sizeof(struct rte_ether_addr) *
2536                                                HNS3_VF_UC_MACADDR_NUM, 0);
2537         if (eth_dev->data->mac_addrs == NULL) {
2538                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2539                              "to store MAC addresses",
2540                              sizeof(struct rte_ether_addr) *
2541                              HNS3_VF_UC_MACADDR_NUM);
2542                 ret = -ENOMEM;
2543                 goto err_rte_zmalloc;
2544         }
2545
2546         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2547                             &eth_dev->data->mac_addrs[0]);
2548         hw->adapter_state = HNS3_NIC_INITIALIZED;
2549         /*
2550          * Pass the information to the rte_eth_dev_close() that it should also
2551          * release the private port resources.
2552          */
2553         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2554
2555         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2556                 hns3_err(hw, "Reschedule reset service after dev_init");
2557                 hns3_schedule_reset(hns);
2558         } else {
2559                 /* IMP will wait ready flag before reset */
2560                 hns3_notify_reset_ready(hw, false);
2561         }
2562         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2563                           eth_dev);
2564         return 0;
2565
2566 err_rte_zmalloc:
2567         hns3vf_uninit_vf(eth_dev);
2568
2569 err_init_vf:
2570         rte_free(hw->reset.wait_data);
2571
2572 err_init_reset:
2573         eth_dev->dev_ops = NULL;
2574         eth_dev->rx_pkt_burst = NULL;
2575         eth_dev->tx_pkt_burst = NULL;
2576         eth_dev->tx_pkt_prepare = NULL;
2577         rte_free(eth_dev->process_private);
2578         eth_dev->process_private = NULL;
2579
2580         return ret;
2581 }
2582
2583 static int
2584 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2585 {
2586         struct hns3_adapter *hns = eth_dev->data->dev_private;
2587         struct hns3_hw *hw = &hns->hw;
2588
2589         PMD_INIT_FUNC_TRACE();
2590
2591         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2592                 return -EPERM;
2593
2594         eth_dev->dev_ops = NULL;
2595         eth_dev->rx_pkt_burst = NULL;
2596         eth_dev->tx_pkt_burst = NULL;
2597         eth_dev->tx_pkt_prepare = NULL;
2598
2599         if (hw->adapter_state < HNS3_NIC_CLOSING)
2600                 hns3vf_dev_close(eth_dev);
2601
2602         hw->adapter_state = HNS3_NIC_REMOVED;
2603         return 0;
2604 }
2605
2606 static int
2607 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2608                      struct rte_pci_device *pci_dev)
2609 {
2610         return rte_eth_dev_pci_generic_probe(pci_dev,
2611                                              sizeof(struct hns3_adapter),
2612                                              hns3vf_dev_init);
2613 }
2614
2615 static int
2616 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2617 {
2618         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2619 }
2620
2621 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2622         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2623         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2624         { .vendor_id = 0, /* sentinel */ },
2625 };
2626
2627 static struct rte_pci_driver rte_hns3vf_pmd = {
2628         .id_table = pci_id_hns3vf_map,
2629         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2630         .probe = eth_hns3vf_pci_probe,
2631         .remove = eth_hns3vf_pci_remove,
2632 };
2633
2634 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2635 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2636 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");