1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
5 #include <linux/pci_regs.h>
7 #include <ethdev_pci.h>
12 #include "hns3_ethdev.h"
13 #include "hns3_logs.h"
14 #include "hns3_rxtx.h"
15 #include "hns3_regs.h"
16 #include "hns3_intr.h"
20 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */
21 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */
23 #define HNS3VF_RESET_WAIT_MS 20
24 #define HNS3VF_RESET_WAIT_CNT 2000
26 /* Reset related Registers */
27 #define HNS3_GLOBAL_RESET_BIT 0
28 #define HNS3_CORE_RESET_BIT 1
29 #define HNS3_IMP_RESET_BIT 2
30 #define HNS3_FUN_RST_ING_B 0
32 enum hns3vf_evt_cause {
33 HNS3VF_VECTOR0_EVENT_RST,
34 HNS3VF_VECTOR0_EVENT_MBX,
35 HNS3VF_VECTOR0_EVENT_OTHER,
38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
44 struct rte_ether_addr *mac_addr);
45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
46 struct rte_ether_addr *mac_addr);
47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
48 __rte_unused int wait_to_complete);
50 /* set PCI bus mastering */
52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
57 ret = rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND);
59 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
65 /* set the master bit */
66 reg |= PCI_COMMAND_MASTER;
68 reg &= ~(PCI_COMMAND_MASTER);
70 return rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND);
74 * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
75 * @cap: the capability
77 * Return the address of the given capability within the PCI capability list.
80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
82 #define MAX_PCIE_CAPABILITY 48
89 ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
91 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
95 if (!(status & PCI_STATUS_CAP_LIST))
98 ttl = MAX_PCIE_CAPABILITY;
99 ret = rte_pci_read_config(device, &pos, sizeof(pos),
100 PCI_CAPABILITY_LIST);
102 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
103 PCI_CAPABILITY_LIST);
107 while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
108 ret = rte_pci_read_config(device, &id, sizeof(id),
109 (pos + PCI_CAP_LIST_ID));
111 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
112 (pos + PCI_CAP_LIST_ID));
122 ret = rte_pci_read_config(device, &pos, sizeof(pos),
123 (pos + PCI_CAP_LIST_NEXT));
125 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
126 (pos + PCI_CAP_LIST_NEXT));
134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
140 pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
142 ret = rte_pci_read_config(device, &control, sizeof(control),
143 (pos + PCI_MSIX_FLAGS));
145 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
146 (pos + PCI_MSIX_FLAGS));
151 control |= PCI_MSIX_FLAGS_ENABLE;
153 control &= ~PCI_MSIX_FLAGS_ENABLE;
154 ret = rte_pci_write_config(device, &control, sizeof(control),
155 (pos + PCI_MSIX_FLAGS));
157 PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
158 (pos + PCI_MSIX_FLAGS));
169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
171 /* mac address was checked by upper level interface */
172 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
175 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
176 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
177 RTE_ETHER_ADDR_LEN, false, NULL, 0);
179 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
181 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
190 /* mac address was checked by upper level interface */
191 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
194 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
195 HNS3_MBX_MAC_VLAN_UC_REMOVE,
196 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
199 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
201 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
208 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
209 struct rte_ether_addr *mac_addr)
211 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
212 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
213 struct rte_ether_addr *old_addr;
214 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
215 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
219 * It has been guaranteed that input parameter named mac_addr is valid
220 * address in the rte layer of DPDK framework.
222 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
223 rte_spinlock_lock(&hw->lock);
224 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
225 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
228 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
229 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
230 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
233 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
234 * driver. When user has configured a MAC address for VF device
235 * by "ip link set ..." command based on the PF device, the hns3
236 * PF kernel ethdev driver does not allow VF driver to request
237 * reconfiguring a different default MAC address, and return
238 * -EPREM to VF driver through mailbox.
241 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
243 hns3_warn(hw, "Has permanet mac addr(%s) for vf",
246 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
248 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
253 rte_ether_addr_copy(mac_addr,
254 (struct rte_ether_addr *)hw->mac.mac_addr);
255 rte_spinlock_unlock(&hw->lock);
261 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
262 struct rte_ether_addr *mac_addr)
264 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
267 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
268 HNS3_MBX_MAC_VLAN_MC_ADD,
269 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
272 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
274 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
282 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
283 struct rte_ether_addr *mac_addr)
285 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
288 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
289 HNS3_MBX_MAC_VLAN_MC_REMOVE,
290 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
293 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
295 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
303 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
304 struct rte_ether_addr *mc_addr_set,
307 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
308 struct rte_ether_addr *addr;
315 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
319 rte_spinlock_lock(&hw->lock);
320 cur_addr_num = hw->mc_addrs_num;
321 for (i = 0; i < cur_addr_num; i++) {
322 num = cur_addr_num - i - 1;
323 addr = &hw->mc_addrs[num];
324 ret = hw->ops.del_mc_mac_addr(hw, addr);
326 rte_spinlock_unlock(&hw->lock);
333 set_addr_num = (int)nb_mc_addr;
334 for (i = 0; i < set_addr_num; i++) {
335 addr = &mc_addr_set[i];
336 ret = hw->ops.add_mc_mac_addr(hw, addr);
338 rte_spinlock_unlock(&hw->lock);
342 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
345 rte_spinlock_unlock(&hw->lock);
351 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
352 bool en_uc_pmc, bool en_mc_pmc)
354 struct hns3_mbx_vf_to_pf_cmd *req;
355 struct hns3_cmd_desc desc;
358 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
361 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
362 * so there are some features for promiscuous/allmulticast mode in hns3
363 * VF PMD driver as below:
364 * 1. The promiscuous/allmulticast mode can be configured successfully
365 * only based on the trusted VF device. If based on the non trusted
366 * VF device, configuring promiscuous/allmulticast mode will fail.
367 * The hns3 VF device can be confiruged as trusted device by hns3 PF
368 * kernel ethdev driver on the host by the following command:
369 * "ip link set <eth num> vf <vf id> turst on"
370 * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
371 * driver can receive the ingress and outgoing traffic. In the words,
372 * all the ingress packets, all the packets sent from the PF and
373 * other VFs on the same physical port.
374 * 3. Note: Because of the hardware constraints, By default vlan filter
375 * is enabled and couldn't be turned off based on VF device, so vlan
376 * filter is still effective even in promiscuous mode. If upper
377 * applications don't call rte_eth_dev_vlan_filter API function to
378 * set vlan based on VF device, hns3 VF PMD driver will can't receive
379 * the packets with vlan tag in promiscuoue mode.
381 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
382 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
383 req->msg[1] = en_bc_pmc ? 1 : 0;
384 req->msg[2] = en_uc_pmc ? 1 : 0;
385 req->msg[3] = en_mc_pmc ? 1 : 0;
386 req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
388 ret = hns3_cmd_send(hw, &desc, 1);
390 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
396 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
398 struct hns3_adapter *hns = dev->data->dev_private;
399 struct hns3_hw *hw = &hns->hw;
402 ret = hns3vf_set_promisc_mode(hw, true, true, true);
404 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
410 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
412 bool allmulti = dev->data->all_multicast ? true : false;
413 struct hns3_adapter *hns = dev->data->dev_private;
414 struct hns3_hw *hw = &hns->hw;
417 ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
419 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
425 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
427 struct hns3_adapter *hns = dev->data->dev_private;
428 struct hns3_hw *hw = &hns->hw;
431 if (dev->data->promiscuous)
434 ret = hns3vf_set_promisc_mode(hw, true, false, true);
436 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
442 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
444 struct hns3_adapter *hns = dev->data->dev_private;
445 struct hns3_hw *hw = &hns->hw;
448 if (dev->data->promiscuous)
451 ret = hns3vf_set_promisc_mode(hw, true, false, false);
453 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
459 hns3vf_restore_promisc(struct hns3_adapter *hns)
461 struct hns3_hw *hw = &hns->hw;
462 bool allmulti = hw->data->all_multicast ? true : false;
464 if (hw->data->promiscuous)
465 return hns3vf_set_promisc_mode(hw, true, true, true);
467 return hns3vf_set_promisc_mode(hw, true, false, allmulti);
471 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
472 bool mmap, enum hns3_ring_type queue_type,
475 struct hns3_vf_bind_vector_msg bind_msg;
480 memset(&bind_msg, 0, sizeof(bind_msg));
481 code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
482 HNS3_MBX_UNMAP_RING_TO_VECTOR;
483 bind_msg.vector_id = vector_id;
485 if (queue_type == HNS3_RING_TYPE_RX)
486 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
488 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
490 bind_msg.param[0].ring_type = queue_type;
491 bind_msg.ring_num = 1;
492 bind_msg.param[0].tqp_index = queue_id;
493 op_str = mmap ? "Map" : "Unmap";
494 ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
495 sizeof(bind_msg), false, NULL, 0);
497 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
498 op_str, queue_id, bind_msg.vector_id, ret);
504 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
511 * In hns3 network engine, vector 0 is always the misc interrupt of this
512 * function, vector 1~N can be used respectively for the queues of the
513 * function. Tx and Rx queues with the same number share the interrupt
514 * vector. In the initialization clearing the all hardware mapping
515 * relationship configurations between queues and interrupt vectors is
516 * needed, so some error caused by the residual configurations, such as
517 * the unexpected Tx interrupt, can be avoid.
519 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
520 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
521 vec = vec - 1; /* the last interrupt is reserved */
522 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
523 for (i = 0; i < hw->intr_tqps_num; i++) {
525 * Set gap limiter/rate limiter/quanity limiter algorithm
526 * configuration for interrupt coalesce of queue's interrupt.
528 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
529 HNS3_TQP_INTR_GL_DEFAULT);
530 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
531 HNS3_TQP_INTR_GL_DEFAULT);
532 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
534 * QL(quantity limiter) is not used currently, just set 0 to
537 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
539 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
540 HNS3_RING_TYPE_TX, i);
542 PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
543 "vector: %u, ret=%d", i, vec, ret);
547 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
548 HNS3_RING_TYPE_RX, i);
550 PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
551 "vector: %u, ret=%d", i, vec, ret);
560 hns3vf_dev_configure(struct rte_eth_dev *dev)
562 struct hns3_adapter *hns = dev->data->dev_private;
563 struct hns3_hw *hw = &hns->hw;
564 struct rte_eth_conf *conf = &dev->data->dev_conf;
565 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
566 uint16_t nb_rx_q = dev->data->nb_rx_queues;
567 uint16_t nb_tx_q = dev->data->nb_tx_queues;
568 struct rte_eth_rss_conf rss_conf;
572 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
575 * Some versions of hardware network engine does not support
576 * individually enable/disable/reset the Tx or Rx queue. These devices
577 * must enable/disable/reset Tx and Rx queues at the same time. When the
578 * numbers of Tx queues allocated by upper applications are not equal to
579 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
580 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
581 * work as usual. But these fake queues are imperceptible, and can not
582 * be used by upper applications.
584 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
586 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
587 hw->cfg_max_queues = 0;
591 hw->adapter_state = HNS3_NIC_CONFIGURING;
592 if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
593 hns3_err(hw, "setting link speed/duplex not supported");
598 /* When RSS is not configured, redirect the packet queue 0 */
599 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
600 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
601 hw->rss_dis_flag = false;
602 rss_conf = conf->rx_adv_conf.rss_conf;
603 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
608 ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
612 ret = hns3vf_dev_configure_vlan(dev);
616 /* config hardware GRO */
617 gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
618 ret = hns3_config_gro(hw, gro_en);
622 hns3_init_rx_ptype_tble(dev);
624 hw->adapter_state = HNS3_NIC_CONFIGURED;
628 hw->cfg_max_queues = 0;
629 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
630 hw->adapter_state = HNS3_NIC_INITIALIZED;
636 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
640 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
641 sizeof(mtu), true, NULL, 0);
643 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
649 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
651 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
652 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
656 * The hns3 PF/VF devices on the same port share the hardware MTU
657 * configuration. Currently, we send mailbox to inform hns3 PF kernel
658 * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
659 * driver, there is no need to stop the port for hns3 VF device, and the
660 * MTU value issued by hns3 VF PMD driver must be less than or equal to
663 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
664 hns3_err(hw, "Failed to set mtu during resetting");
669 * when Rx of scattered packets is off, we have some possibility of
670 * using vector Rx process function or simple Rx functions in hns3 PMD
671 * driver. If the input MTU is increased and the maximum length of
672 * received packets is greater than the length of a buffer for Rx
673 * packet, the hardware network engine needs to use multiple BDs and
674 * buffers to store these packets. This will cause problems when still
675 * using vector Rx process function or simple Rx function to receiving
676 * packets. So, when Rx of scattered packets is off and device is
677 * started, it is not permitted to increase MTU so that the maximum
678 * length of Rx packets is greater than Rx buffer length.
680 if (dev->data->dev_started && !dev->data->scattered_rx &&
681 frame_size > hw->rx_buf_len) {
682 hns3_err(hw, "failed to set mtu because current is "
683 "not scattered rx mode");
687 rte_spinlock_lock(&hw->lock);
688 ret = hns3vf_config_mtu(hw, mtu);
690 rte_spinlock_unlock(&hw->lock);
693 rte_spinlock_unlock(&hw->lock);
699 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
701 struct hns3_adapter *hns = eth_dev->data->dev_private;
702 struct hns3_hw *hw = &hns->hw;
703 uint16_t q_num = hw->tqps_num;
706 * In interrupt mode, 'max_rx_queues' is set based on the number of
707 * MSI-X interrupt resources of the hardware.
709 if (hw->data->dev_conf.intr_conf.rxq == 1)
710 q_num = hw->intr_tqps_num;
712 info->max_rx_queues = q_num;
713 info->max_tx_queues = hw->tqps_num;
714 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
715 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
716 info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
717 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
718 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
720 info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
721 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
722 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
723 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
724 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
725 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
726 RTE_ETH_RX_OFFLOAD_SCATTER |
727 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
728 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
729 RTE_ETH_RX_OFFLOAD_RSS_HASH |
730 RTE_ETH_RX_OFFLOAD_TCP_LRO);
731 info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
732 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
733 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
734 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
735 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
736 RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
737 RTE_ETH_TX_OFFLOAD_TCP_TSO |
738 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
739 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
740 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
741 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
742 hns3_txvlan_cap_get(hw));
744 if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
745 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
747 if (hns3_dev_get_support(hw, INDEP_TXRX))
748 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
749 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
751 info->rx_desc_lim = (struct rte_eth_desc_lim) {
752 .nb_max = HNS3_MAX_RING_DESC,
753 .nb_min = HNS3_MIN_RING_DESC,
754 .nb_align = HNS3_ALIGN_RING_DESC,
757 info->tx_desc_lim = (struct rte_eth_desc_lim) {
758 .nb_max = HNS3_MAX_RING_DESC,
759 .nb_min = HNS3_MIN_RING_DESC,
760 .nb_align = HNS3_ALIGN_RING_DESC,
761 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
762 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
765 info->default_rxconf = (struct rte_eth_rxconf) {
766 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
768 * If there are no available Rx buffer descriptors, incoming
769 * packets are always dropped by hardware based on hns3 network
775 info->default_txconf = (struct rte_eth_txconf) {
776 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
780 info->reta_size = hw->rss_ind_tbl_size;
781 info->hash_key_size = HNS3_RSS_KEY_SIZE;
782 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
784 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
785 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
786 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
787 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
788 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
789 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
795 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
797 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
801 hns3vf_disable_irq0(struct hns3_hw *hw)
803 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
807 hns3vf_enable_irq0(struct hns3_hw *hw)
809 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
812 static enum hns3vf_evt_cause
813 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
815 struct hns3_hw *hw = &hns->hw;
816 enum hns3vf_evt_cause ret;
817 uint32_t cmdq_stat_reg;
818 uint32_t rst_ing_reg;
821 /* Fetch the events from their corresponding regs */
822 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
823 if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
824 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
825 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
826 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
827 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
828 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
829 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
830 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
832 hw->reset.stats.global_cnt++;
833 hns3_warn(hw, "Global reset detected, clear reset status");
835 hns3_schedule_delayed_reset(hns);
836 hns3_warn(hw, "Global reset detected, don't clear reset status");
839 ret = HNS3VF_VECTOR0_EVENT_RST;
843 /* Check for vector0 mailbox(=CMDQ RX) event source */
844 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
845 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
846 ret = HNS3VF_VECTOR0_EVENT_MBX;
851 ret = HNS3VF_VECTOR0_EVENT_OTHER;
859 hns3vf_interrupt_handler(void *param)
861 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
862 struct hns3_adapter *hns = dev->data->dev_private;
863 struct hns3_hw *hw = &hns->hw;
864 enum hns3vf_evt_cause event_cause;
867 /* Disable interrupt */
868 hns3vf_disable_irq0(hw);
870 /* Read out interrupt causes */
871 event_cause = hns3vf_check_event_cause(hns, &clearval);
872 /* Clear interrupt causes */
873 hns3vf_clear_event_cause(hw, clearval);
875 switch (event_cause) {
876 case HNS3VF_VECTOR0_EVENT_RST:
877 hns3_schedule_reset(hns);
879 case HNS3VF_VECTOR0_EVENT_MBX:
880 hns3_dev_handle_mbx_msg(hw);
886 /* Enable interrupt */
887 hns3vf_enable_irq0(hw);
891 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
893 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
894 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
895 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
896 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
900 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
902 struct hns3_dev_specs_0_cmd *req0;
904 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
906 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
907 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
908 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
909 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
913 hns3vf_check_dev_specifications(struct hns3_hw *hw)
915 if (hw->rss_ind_tbl_size == 0 ||
916 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
917 hns3_warn(hw, "the size of hash lookup table configured (%u)"
918 " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
919 HNS3_RSS_IND_TBL_SIZE_MAX);
927 hns3vf_query_dev_specifications(struct hns3_hw *hw)
929 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
933 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
934 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
936 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
938 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
940 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
944 hns3vf_parse_dev_specifications(hw, desc);
946 return hns3vf_check_dev_specifications(hw);
950 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
952 uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
953 HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
954 uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
955 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
957 if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
958 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
959 __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
963 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
965 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS 500
967 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
968 int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
969 uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
970 uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
971 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
973 __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
976 (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
979 while (remain_ms > 0) {
980 rte_delay_ms(HNS3_POLL_RESPONE_MS);
981 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
982 HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
988 * When exit above loop, the pf_push_lsc_cap could be one of the three
989 * state: unknown (means pf not ack), not_supported, supported.
990 * Here config it as 'not_supported' when it's 'unknown' state.
992 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
993 __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
995 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
996 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
997 hns3_info(hw, "detect PF support push link status change!");
1000 * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
1001 * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
1002 * the RTE_ETH_DEV_INTR_LSC capability.
1004 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
1009 hns3vf_get_capability(struct hns3_hw *hw)
1011 struct rte_pci_device *pci_dev;
1012 struct rte_eth_dev *eth_dev;
1016 eth_dev = &rte_eth_devices[hw->data->port_id];
1017 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1019 /* Get PCI revision id */
1020 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1021 HNS3_PCI_REVISION_ID);
1022 if (ret != HNS3_PCI_REVISION_ID_LEN) {
1023 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1027 hw->revision = revision;
1029 if (revision < PCI_REVISION_ID_HIP09_A) {
1030 hns3vf_set_default_dev_specifications(hw);
1031 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1032 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1033 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1034 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
1035 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1036 hw->rss_info.ipv6_sctp_offload_supported = false;
1037 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1041 ret = hns3vf_query_dev_specifications(hw);
1044 "failed to query dev specifications, ret = %d",
1049 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1050 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1051 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1052 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1053 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1054 hw->rss_info.ipv6_sctp_offload_supported = true;
1055 hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1061 hns3vf_check_tqp_info(struct hns3_hw *hw)
1063 if (hw->tqps_num == 0) {
1064 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1068 if (hw->rss_size_max == 0) {
1069 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1073 hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1079 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1084 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1085 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1086 true, &resp_msg, sizeof(resp_msg));
1088 if (ret == -ETIME) {
1090 * Getting current port based VLAN state from PF driver
1091 * will not affect VF driver's basic function. Because
1092 * the VF driver relies on hns3 PF kernel ether driver,
1093 * to avoid introducing compatibility issues with older
1094 * version of PF driver, no failure will be returned
1095 * when the return value is ETIME. This return value has
1096 * the following scenarios:
1097 * 1) Firmware didn't return the results in time
1098 * 2) the result return by firmware is timeout
1099 * 3) the older version of kernel side PF driver does
1100 * not support this mailbox message.
1101 * For scenarios 1 and 2, it is most likely that a
1102 * hardware error has occurred, or a hardware reset has
1103 * occurred. In this case, these errors will be caught
1104 * by other functions.
1106 PMD_INIT_LOG(WARNING,
1107 "failed to get PVID state for timeout, maybe "
1108 "kernel side PF driver doesn't support this "
1109 "mailbox message, or firmware didn't respond.");
1110 resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1112 PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1117 hw->port_base_vlan_cfg.state = resp_msg ?
1118 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1123 hns3vf_get_queue_info(struct hns3_hw *hw)
1125 #define HNS3VF_TQPS_RSS_INFO_LEN 6
1126 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1129 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1130 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1132 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1136 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1137 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1139 return hns3vf_check_tqp_info(hw);
1143 hns3vf_get_queue_depth(struct hns3_hw *hw)
1145 #define HNS3VF_TQPS_DEPTH_INFO_LEN 4
1146 uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1149 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1150 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1152 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1157 memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1158 memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1164 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
1166 if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
1167 hns3_set_bit(hw->capability,
1168 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
1172 hns3vf_get_num_tc(struct hns3_hw *hw)
1177 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1178 if (hw->hw_tc_map & BIT(i))
1185 hns3vf_get_basic_info(struct hns3_hw *hw)
1187 uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
1188 struct hns3_basic_info *basic_info;
1191 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
1192 true, resp_msg, sizeof(resp_msg));
1194 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
1199 basic_info = (struct hns3_basic_info *)resp_msg;
1200 hw->hw_tc_map = basic_info->hw_tc_map;
1201 hw->num_tc = hns3vf_get_num_tc(hw);
1202 hw->pf_vf_if_version = basic_info->pf_vf_if_version;
1203 hns3vf_update_caps(hw, basic_info->caps);
1209 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1211 uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1214 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1215 true, host_mac, RTE_ETHER_ADDR_LEN);
1217 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1221 memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1227 hns3vf_get_configuration(struct hns3_hw *hw)
1231 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1232 hw->rss_dis_flag = false;
1234 /* Get device capability */
1235 ret = hns3vf_get_capability(hw);
1237 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1241 hns3vf_get_push_lsc_cap(hw);
1243 /* Get basic info from PF */
1244 ret = hns3vf_get_basic_info(hw);
1248 /* Get queue configuration from PF */
1249 ret = hns3vf_get_queue_info(hw);
1253 /* Get queue depth info from PF */
1254 ret = hns3vf_get_queue_depth(hw);
1258 /* Get user defined VF MAC addr from PF */
1259 ret = hns3vf_get_host_mac_addr(hw);
1263 return hns3vf_get_port_base_vlan_filter_state(hw);
1267 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1270 struct hns3_hw *hw = &hns->hw;
1272 return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1276 hns3vf_request_link_info(struct hns3_hw *hw)
1278 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1282 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1285 send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1286 vf->req_link_info_cnt > 0;
1290 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1293 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1297 if (vf->req_link_info_cnt > 0)
1298 vf->req_link_info_cnt--;
1302 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1303 uint32_t link_speed, uint8_t link_duplex)
1305 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1306 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1307 struct hns3_mac *mac = &hw->mac;
1311 * PF kernel driver may push link status when VF driver is in resetting,
1312 * driver will stop polling job in this case, after resetting done
1313 * driver will start polling job again.
1314 * When polling job started, driver will get initial link status by
1315 * sending request to PF kernel driver, then could update link status by
1316 * process PF kernel driver's link status mailbox message.
1318 if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1321 if (hw->adapter_state != HNS3_NIC_STARTED)
1324 mac->link_status = link_status;
1325 mac->link_speed = link_speed;
1326 mac->link_duplex = link_duplex;
1327 ret = hns3vf_dev_link_update(dev, 0);
1328 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1329 hns3_start_report_lse(dev);
1333 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1335 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1336 struct hns3_hw *hw = &hns->hw;
1337 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1338 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1339 uint8_t is_kill = on ? 0 : 1;
1341 msg_data[0] = is_kill;
1342 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1343 memcpy(&msg_data[3], &proto, sizeof(proto));
1345 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1346 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1351 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1353 struct hns3_adapter *hns = dev->data->dev_private;
1354 struct hns3_hw *hw = &hns->hw;
1357 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1359 "vf set vlan id failed during resetting, vlan_id =%u",
1363 rte_spinlock_lock(&hw->lock);
1364 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1365 rte_spinlock_unlock(&hw->lock);
1367 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1374 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1379 if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1382 msg_data = enable ? 1 : 0;
1383 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1384 HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1385 sizeof(msg_data), true, NULL, 0);
1387 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1388 enable ? "enable" : "disable", ret);
1394 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1399 msg_data = enable ? 1 : 0;
1400 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1401 &msg_data, sizeof(msg_data), false, NULL, 0);
1403 hns3_err(hw, "vf %s strip failed, ret = %d.",
1404 enable ? "enable" : "disable", ret);
1410 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1412 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1413 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1414 unsigned int tmp_mask;
1417 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1418 hns3_err(hw, "vf set vlan offload failed during resetting, "
1419 "mask = 0x%x", mask);
1423 tmp_mask = (unsigned int)mask;
1425 if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
1426 rte_spinlock_lock(&hw->lock);
1427 /* Enable or disable VLAN filter */
1428 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1429 ret = hns3vf_en_vlan_filter(hw, true);
1431 ret = hns3vf_en_vlan_filter(hw, false);
1432 rte_spinlock_unlock(&hw->lock);
1437 /* Vlan stripping setting */
1438 if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
1439 rte_spinlock_lock(&hw->lock);
1440 /* Enable or disable VLAN stripping */
1441 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1442 ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1444 ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1445 rte_spinlock_unlock(&hw->lock);
1452 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1454 struct rte_vlan_filter_conf *vfc;
1455 struct hns3_hw *hw = &hns->hw;
1462 vfc = &hw->data->vlan_filter_conf;
1463 for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1464 if (vfc->ids[i] == 0)
1469 * 64 means the num bits of ids, one bit corresponds to
1473 /* count trailing zeroes */
1474 vbit = ~ids & (ids - 1);
1475 /* clear least significant bit set */
1476 ids ^= (ids ^ (ids - 1)) ^ vbit;
1481 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1484 "VF handle vlan table failed, ret =%d, on = %d",
1495 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1497 return hns3vf_handle_all_vlan_table(hns, 0);
1501 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1503 struct hns3_hw *hw = &hns->hw;
1504 struct rte_eth_conf *dev_conf;
1508 dev_conf = &hw->data->dev_conf;
1509 en = dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? true
1511 ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1513 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1519 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1521 struct hns3_adapter *hns = dev->data->dev_private;
1522 struct rte_eth_dev_data *data = dev->data;
1523 struct hns3_hw *hw = &hns->hw;
1526 if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1527 data->dev_conf.txmode.hw_vlan_reject_untagged ||
1528 data->dev_conf.txmode.hw_vlan_insert_pvid) {
1529 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1530 "or hw_vlan_insert_pvid is not support!");
1533 /* Apply vlan offload setting */
1534 ret = hns3vf_vlan_offload_set(dev, RTE_ETH_VLAN_STRIP_MASK |
1535 RTE_ETH_VLAN_FILTER_MASK);
1537 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1543 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1547 msg_data = alive ? 1 : 0;
1548 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1549 sizeof(msg_data), false, NULL, 0);
1553 hns3vf_keep_alive_handler(void *param)
1555 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1556 struct hns3_adapter *hns = eth_dev->data->dev_private;
1557 struct hns3_hw *hw = &hns->hw;
1560 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1563 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1566 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1571 hns3vf_service_handler(void *param)
1573 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1574 struct hns3_adapter *hns = eth_dev->data->dev_private;
1575 struct hns3_hw *hw = &hns->hw;
1578 * The query link status and reset processing are executed in the
1579 * interrupt thread. When the IMP reset occurs, IMP will not respond,
1580 * and the query operation will timeout after 30ms. In the case of
1581 * multiple PF/VFs, each query failure timeout causes the IMP reset
1582 * interrupt to fail to respond within 100ms.
1583 * Before querying the link status, check whether there is a reset
1584 * pending, and if so, abandon the query.
1586 if (!hns3vf_is_reset_pending(hns))
1587 hns3vf_request_link_info(hw);
1589 hns3_warn(hw, "Cancel the query when reset is pending");
1591 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1596 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1598 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT 3
1600 struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1602 if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1603 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1605 __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1607 hns3vf_service_handler(dev);
1611 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1613 struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1615 rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1617 __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1621 hns3_query_vf_resource(struct hns3_hw *hw)
1623 struct hns3_vf_res_cmd *req;
1624 struct hns3_cmd_desc desc;
1628 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1629 ret = hns3_cmd_send(hw, &desc, 1);
1631 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1635 req = (struct hns3_vf_res_cmd *)desc.data;
1636 num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1637 HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1638 if (num_msi < HNS3_MIN_VECTOR_NUM) {
1639 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1640 num_msi, HNS3_MIN_VECTOR_NUM);
1644 hw->num_msi = num_msi;
1650 hns3vf_init_hardware(struct hns3_adapter *hns)
1652 struct hns3_hw *hw = &hns->hw;
1653 uint16_t mtu = hw->data->mtu;
1656 ret = hns3vf_set_promisc_mode(hw, true, false, false);
1660 ret = hns3vf_config_mtu(hw, mtu);
1662 goto err_init_hardware;
1664 ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1666 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1667 goto err_init_hardware;
1670 ret = hns3_config_gro(hw, false);
1672 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1673 goto err_init_hardware;
1677 * In the initialization clearing the all hardware mapping relationship
1678 * configurations between queues and interrupt vectors is needed, so
1679 * some error caused by the residual configurations, such as the
1680 * unexpected interrupt, can be avoid.
1682 ret = hns3vf_init_ring_with_vector(hw);
1684 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1685 goto err_init_hardware;
1691 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1696 hns3vf_clear_vport_list(struct hns3_hw *hw)
1698 return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1699 HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1704 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1706 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1707 struct hns3_adapter *hns = eth_dev->data->dev_private;
1708 struct hns3_hw *hw = &hns->hw;
1711 PMD_INIT_FUNC_TRACE();
1713 /* Get hardware io base address from pcie BAR2 IO space */
1714 hw->io_base = pci_dev->mem_resource[2].addr;
1716 /* Firmware command queue initialize */
1717 ret = hns3_cmd_init_queue(hw);
1719 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1720 goto err_cmd_init_queue;
1723 /* Firmware command initialize */
1724 ret = hns3_cmd_init(hw);
1726 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1730 hns3_tx_push_init(eth_dev);
1732 /* Get VF resource */
1733 ret = hns3_query_vf_resource(hw);
1737 rte_spinlock_init(&hw->mbx_resp.lock);
1739 hns3vf_clear_event_cause(hw, 0);
1741 ret = rte_intr_callback_register(pci_dev->intr_handle,
1742 hns3vf_interrupt_handler, eth_dev);
1744 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1745 goto err_intr_callback_register;
1748 /* Enable interrupt */
1749 rte_intr_enable(pci_dev->intr_handle);
1750 hns3vf_enable_irq0(hw);
1752 /* Get configuration from PF */
1753 ret = hns3vf_get_configuration(hw);
1755 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1756 goto err_get_config;
1759 ret = hns3_tqp_stats_init(hw);
1761 goto err_get_config;
1763 /* Hardware statistics of imissed registers cleared. */
1764 ret = hns3_update_imissed_stats(hw, true);
1766 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1767 goto err_set_tc_queue;
1770 ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1772 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1773 goto err_set_tc_queue;
1776 ret = hns3vf_clear_vport_list(hw);
1778 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1779 goto err_set_tc_queue;
1782 ret = hns3vf_init_hardware(hns);
1784 goto err_set_tc_queue;
1786 hns3_rss_set_default_args(hw);
1788 ret = hns3vf_set_alive(hw, true);
1790 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1791 goto err_set_tc_queue;
1797 hns3_tqp_stats_uninit(hw);
1800 hns3vf_disable_irq0(hw);
1801 rte_intr_disable(pci_dev->intr_handle);
1802 hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1804 err_intr_callback_register:
1806 hns3_cmd_uninit(hw);
1807 hns3_cmd_destroy_queue(hw);
1815 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1817 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1818 struct hns3_adapter *hns = eth_dev->data->dev_private;
1819 struct hns3_hw *hw = &hns->hw;
1821 PMD_INIT_FUNC_TRACE();
1823 hns3_rss_uninit(hns);
1824 (void)hns3_config_gro(hw, false);
1825 (void)hns3vf_set_alive(hw, false);
1826 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1827 hns3_flow_uninit(eth_dev);
1828 hns3_tqp_stats_uninit(hw);
1829 hns3vf_disable_irq0(hw);
1830 rte_intr_disable(pci_dev->intr_handle);
1831 hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1833 hns3_cmd_uninit(hw);
1834 hns3_cmd_destroy_queue(hw);
1839 hns3vf_do_stop(struct hns3_adapter *hns)
1841 struct hns3_hw *hw = &hns->hw;
1844 hw->mac.link_status = RTE_ETH_LINK_DOWN;
1847 * The "hns3vf_do_stop" function will also be called by .stop_service to
1848 * prepare reset. At the time of global or IMP reset, the command cannot
1849 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
1850 * accessed during the reset process. So the mbuf can not be released
1851 * during reset and is required to be released after the reset is
1854 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)
1855 hns3_dev_release_mbufs(hns);
1857 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
1858 hns3_configure_all_mac_addr(hns, true);
1859 ret = hns3_reset_all_tqps(hns);
1861 hns3_err(hw, "failed to reset all queues ret = %d",
1870 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1872 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1873 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1874 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1875 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1876 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1879 if (dev->data->dev_conf.intr_conf.rxq == 0)
1882 /* unmap the ring with vector */
1883 if (rte_intr_allow_others(intr_handle)) {
1884 vec = RTE_INTR_VEC_RXTX_OFFSET;
1885 base = RTE_INTR_VEC_RXTX_OFFSET;
1887 if (rte_intr_dp_is_en(intr_handle)) {
1888 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1889 (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1892 if (vec < base + rte_intr_nb_efd_get(intr_handle)
1897 /* Clean datapath event and queue/vec mapping */
1898 rte_intr_efd_disable(intr_handle);
1900 /* Cleanup vector list */
1901 rte_intr_vec_list_free(intr_handle);
1905 hns3vf_dev_stop(struct rte_eth_dev *dev)
1907 struct hns3_adapter *hns = dev->data->dev_private;
1908 struct hns3_hw *hw = &hns->hw;
1910 PMD_INIT_FUNC_TRACE();
1911 dev->data->dev_started = 0;
1913 hw->adapter_state = HNS3_NIC_STOPPING;
1914 hns3_set_rxtx_function(dev);
1916 /* Disable datapath on secondary process. */
1917 hns3_mp_req_stop_rxtx(dev);
1918 /* Prevent crashes when queues are still in use. */
1919 rte_delay_ms(hw->cfg_max_queues);
1921 rte_spinlock_lock(&hw->lock);
1922 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1924 hns3vf_do_stop(hns);
1925 hns3vf_unmap_rx_interrupt(dev);
1926 hw->adapter_state = HNS3_NIC_CONFIGURED;
1928 hns3_rx_scattered_reset(dev);
1929 hns3vf_stop_poll_job(dev);
1930 hns3_stop_report_lse(dev);
1931 rte_spinlock_unlock(&hw->lock);
1937 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1939 struct hns3_adapter *hns = eth_dev->data->dev_private;
1940 struct hns3_hw *hw = &hns->hw;
1943 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1946 if (hw->adapter_state == HNS3_NIC_STARTED)
1947 ret = hns3vf_dev_stop(eth_dev);
1949 hw->adapter_state = HNS3_NIC_CLOSING;
1950 hns3_reset_abort(hns);
1951 hw->adapter_state = HNS3_NIC_CLOSED;
1952 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1953 hns3_configure_all_mc_mac_addr(hns, true);
1954 hns3vf_remove_all_vlan_table(hns);
1955 hns3vf_uninit_vf(eth_dev);
1956 hns3_free_all_queues(eth_dev);
1957 rte_free(hw->reset.wait_data);
1958 hns3_mp_uninit_primary();
1959 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
1965 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1968 struct hns3_adapter *hns = eth_dev->data->dev_private;
1969 struct hns3_hw *hw = &hns->hw;
1970 uint32_t version = hw->fw_version;
1973 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1974 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1975 HNS3_FW_VERSION_BYTE3_S),
1976 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1977 HNS3_FW_VERSION_BYTE2_S),
1978 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1979 HNS3_FW_VERSION_BYTE1_S),
1980 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1981 HNS3_FW_VERSION_BYTE0_S));
1985 ret += 1; /* add the size of '\0' */
1986 if (fw_size < (size_t)ret)
1993 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1994 __rte_unused int wait_to_complete)
1996 struct hns3_adapter *hns = eth_dev->data->dev_private;
1997 struct hns3_hw *hw = &hns->hw;
1998 struct hns3_mac *mac = &hw->mac;
1999 struct rte_eth_link new_link;
2001 memset(&new_link, 0, sizeof(new_link));
2002 switch (mac->link_speed) {
2003 case RTE_ETH_SPEED_NUM_10M:
2004 case RTE_ETH_SPEED_NUM_100M:
2005 case RTE_ETH_SPEED_NUM_1G:
2006 case RTE_ETH_SPEED_NUM_10G:
2007 case RTE_ETH_SPEED_NUM_25G:
2008 case RTE_ETH_SPEED_NUM_40G:
2009 case RTE_ETH_SPEED_NUM_50G:
2010 case RTE_ETH_SPEED_NUM_100G:
2011 case RTE_ETH_SPEED_NUM_200G:
2012 if (mac->link_status)
2013 new_link.link_speed = mac->link_speed;
2016 if (mac->link_status)
2017 new_link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2021 if (!mac->link_status)
2022 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2024 new_link.link_duplex = mac->link_duplex;
2025 new_link.link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2026 new_link.link_autoneg =
2027 !(eth_dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED);
2029 return rte_eth_linkstatus_set(eth_dev, &new_link);
2033 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2035 struct hns3_hw *hw = &hns->hw;
2036 uint16_t nb_rx_q = hw->data->nb_rx_queues;
2037 uint16_t nb_tx_q = hw->data->nb_tx_queues;
2040 ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2044 hns3_enable_rxd_adv_layout(hw);
2046 ret = hns3_init_queues(hns, reset_queue);
2048 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2054 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2056 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2057 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2058 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2059 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2060 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2061 uint32_t intr_vector;
2066 * hns3 needs a separate interrupt to be used as event interrupt which
2067 * could not be shared with task queue pair, so KERNEL drivers need
2068 * support multiple interrupt vectors.
2070 if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2071 !rte_intr_cap_multiple(intr_handle))
2074 rte_intr_disable(intr_handle);
2075 intr_vector = hw->used_rx_queues;
2076 /* It creates event fd for each intr vector when MSIX is used */
2077 if (rte_intr_efd_enable(intr_handle, intr_vector))
2080 /* Allocate vector list */
2081 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
2082 hw->used_rx_queues)) {
2083 hns3_err(hw, "Failed to allocate %u rx_queues"
2084 " intr_vec", hw->used_rx_queues);
2086 goto vf_alloc_intr_vec_error;
2089 if (rte_intr_allow_others(intr_handle)) {
2090 vec = RTE_INTR_VEC_RXTX_OFFSET;
2091 base = RTE_INTR_VEC_RXTX_OFFSET;
2094 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2095 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2096 HNS3_RING_TYPE_RX, q_id);
2098 goto vf_bind_vector_error;
2100 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
2101 goto vf_bind_vector_error;
2104 * If there are not enough efds (e.g. not enough interrupt),
2105 * remaining queues will be bond to the last interrupt.
2107 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
2110 rte_intr_enable(intr_handle);
2113 vf_bind_vector_error:
2114 rte_intr_vec_list_free(intr_handle);
2115 vf_alloc_intr_vec_error:
2116 rte_intr_efd_disable(intr_handle);
2121 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2123 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2124 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2125 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2129 if (dev->data->dev_conf.intr_conf.rxq == 0)
2132 if (rte_intr_dp_is_en(intr_handle)) {
2133 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2134 ret = hns3vf_bind_ring_with_vector(hw,
2135 rte_intr_vec_list_index_get(intr_handle,
2137 true, HNS3_RING_TYPE_RX, q_id);
2147 hns3vf_restore_filter(struct rte_eth_dev *dev)
2149 hns3_restore_rss_filter(dev);
2153 hns3vf_dev_start(struct rte_eth_dev *dev)
2155 struct hns3_adapter *hns = dev->data->dev_private;
2156 struct hns3_hw *hw = &hns->hw;
2159 PMD_INIT_FUNC_TRACE();
2160 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2163 rte_spinlock_lock(&hw->lock);
2164 hw->adapter_state = HNS3_NIC_STARTING;
2165 ret = hns3vf_do_start(hns, true);
2167 hw->adapter_state = HNS3_NIC_CONFIGURED;
2168 rte_spinlock_unlock(&hw->lock);
2171 ret = hns3vf_map_rx_interrupt(dev);
2173 goto map_rx_inter_err;
2176 * There are three register used to control the status of a TQP
2177 * (contains a pair of Tx queue and Rx queue) in the new version network
2178 * engine. One is used to control the enabling of Tx queue, the other is
2179 * used to control the enabling of Rx queue, and the last is the master
2180 * switch used to control the enabling of the tqp. The Tx register and
2181 * TQP register must be enabled at the same time to enable a Tx queue.
2182 * The same applies to the Rx queue. For the older network enginem, this
2183 * function only refresh the enabled flag, and it is used to update the
2184 * status of queue in the dpdk framework.
2186 ret = hns3_start_all_txqs(dev);
2188 goto map_rx_inter_err;
2190 ret = hns3_start_all_rxqs(dev);
2192 goto start_all_rxqs_fail;
2194 hw->adapter_state = HNS3_NIC_STARTED;
2195 rte_spinlock_unlock(&hw->lock);
2197 hns3_rx_scattered_calc(dev);
2198 hns3_set_rxtx_function(dev);
2199 hns3_mp_req_start_rxtx(dev);
2201 hns3vf_restore_filter(dev);
2203 /* Enable interrupt of all rx queues before enabling queues */
2204 hns3_dev_all_rx_queue_intr_enable(hw, true);
2205 hns3_start_tqps(hw);
2207 if (dev->data->dev_conf.intr_conf.lsc != 0)
2208 hns3vf_dev_link_update(dev, 0);
2209 hns3vf_start_poll_job(dev);
2213 start_all_rxqs_fail:
2214 hns3_stop_all_txqs(dev);
2216 (void)hns3vf_do_stop(hns);
2217 hw->adapter_state = HNS3_NIC_CONFIGURED;
2218 rte_spinlock_unlock(&hw->lock);
2224 is_vf_reset_done(struct hns3_hw *hw)
2226 #define HNS3_FUN_RST_ING_BITS \
2227 (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2228 BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2229 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2230 BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2234 if (hw->reset.level == HNS3_VF_RESET) {
2235 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2236 if (val & HNS3_VF_RST_ING_BIT)
2239 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2240 if (val & HNS3_FUN_RST_ING_BITS)
2247 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2249 struct hns3_hw *hw = &hns->hw;
2250 enum hns3_reset_level reset;
2253 * According to the protocol of PCIe, FLR to a PF device resets the PF
2254 * state as well as the SR-IOV extended capability including VF Enable
2255 * which means that VFs no longer exist.
2257 * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2258 * is in FLR stage, the register state of VF device is not reliable,
2259 * so register states detection can not be carried out. In this case,
2260 * we just ignore the register states and return false to indicate that
2261 * there are no other reset states that need to be processed by driver.
2263 if (hw->reset.level == HNS3_VF_FULL_RESET)
2266 /* Check the registers to confirm whether there is reset pending */
2267 hns3vf_check_event_cause(hns, NULL);
2268 reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2269 if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2270 hw->reset.level < reset) {
2271 hns3_warn(hw, "High level reset %d is pending", reset);
2278 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2280 struct hns3_hw *hw = &hns->hw;
2281 struct hns3_wait_data *wait_data = hw->reset.wait_data;
2284 if (wait_data->result == HNS3_WAIT_SUCCESS) {
2286 * After vf reset is ready, the PF may not have completed
2287 * the reset processing. The vf sending mbox to PF may fail
2288 * during the pf reset, so it is better to add extra delay.
2290 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2291 hw->reset.level == HNS3_FLR_RESET)
2293 /* Reset retry process, no need to add extra delay. */
2294 if (hw->reset.attempts)
2296 if (wait_data->check_completion == NULL)
2299 wait_data->check_completion = NULL;
2300 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2301 wait_data->count = 1;
2302 wait_data->result = HNS3_WAIT_REQUEST;
2303 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2305 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2307 } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2308 hns3_clock_gettime(&tv);
2309 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2310 tv.tv_sec, tv.tv_usec);
2312 } else if (wait_data->result == HNS3_WAIT_REQUEST)
2315 wait_data->hns = hns;
2316 wait_data->check_completion = is_vf_reset_done;
2317 wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2318 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2319 wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2320 wait_data->count = HNS3VF_RESET_WAIT_CNT;
2321 wait_data->result = HNS3_WAIT_REQUEST;
2322 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2327 hns3vf_prepare_reset(struct hns3_adapter *hns)
2329 struct hns3_hw *hw = &hns->hw;
2332 if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2333 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2338 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2344 hns3vf_stop_service(struct hns3_adapter *hns)
2346 struct hns3_hw *hw = &hns->hw;
2347 struct rte_eth_dev *eth_dev;
2349 eth_dev = &rte_eth_devices[hw->data->port_id];
2350 if (hw->adapter_state == HNS3_NIC_STARTED) {
2352 * Make sure call update link status before hns3vf_stop_poll_job
2353 * because update link status depend on polling job exist.
2355 hns3vf_update_link_status(hw, RTE_ETH_LINK_DOWN, hw->mac.link_speed,
2356 hw->mac.link_duplex);
2357 hns3vf_stop_poll_job(eth_dev);
2359 hw->mac.link_status = RTE_ETH_LINK_DOWN;
2361 hns3_set_rxtx_function(eth_dev);
2363 /* Disable datapath on secondary process. */
2364 hns3_mp_req_stop_rxtx(eth_dev);
2365 rte_delay_ms(hw->cfg_max_queues);
2367 rte_spinlock_lock(&hw->lock);
2368 if (hw->adapter_state == HNS3_NIC_STARTED ||
2369 hw->adapter_state == HNS3_NIC_STOPPING) {
2370 hns3_enable_all_queues(hw, false);
2371 hns3vf_do_stop(hns);
2372 hw->reset.mbuf_deferred_free = true;
2374 hw->reset.mbuf_deferred_free = false;
2377 * It is cumbersome for hardware to pick-and-choose entries for deletion
2378 * from table space. Hence, for function reset software intervention is
2379 * required to delete the entries.
2381 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2382 hns3_configure_all_mc_mac_addr(hns, true);
2383 rte_spinlock_unlock(&hw->lock);
2389 hns3vf_start_service(struct hns3_adapter *hns)
2391 struct hns3_hw *hw = &hns->hw;
2392 struct rte_eth_dev *eth_dev;
2394 eth_dev = &rte_eth_devices[hw->data->port_id];
2395 hns3_set_rxtx_function(eth_dev);
2396 hns3_mp_req_start_rxtx(eth_dev);
2397 if (hw->adapter_state == HNS3_NIC_STARTED) {
2398 hns3vf_start_poll_job(eth_dev);
2400 /* Enable interrupt of all rx queues before enabling queues */
2401 hns3_dev_all_rx_queue_intr_enable(hw, true);
2403 * Enable state of each rxq and txq will be recovered after
2404 * reset, so we need to restore them before enable all tqps;
2406 hns3_restore_tqp_enable_state(hw);
2408 * When finished the initialization, enable queues to receive
2409 * and transmit packets.
2411 hns3_enable_all_queues(hw, true);
2418 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2420 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2421 struct rte_ether_addr *hw_mac;
2425 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2426 * on the host by "ip link set ..." command. If the hns3 PF kernel
2427 * ethdev driver sets the MAC address for VF device after the
2428 * initialization of the related VF device, the PF driver will notify
2429 * VF driver to reset VF device to make the new MAC address effective
2430 * immediately. The hns3 VF PMD driver should check whether the MAC
2431 * address has been changed by the PF kernel ethdev driver, if changed
2432 * VF driver should configure hardware using the new MAC address in the
2433 * recovering hardware configuration stage of the reset process.
2435 ret = hns3vf_get_host_mac_addr(hw);
2439 hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2440 ret = rte_is_zero_ether_addr(hw_mac);
2442 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2444 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2446 rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2447 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2448 &hw->data->mac_addrs[0]);
2449 hns3_warn(hw, "Default MAC address has been changed to:"
2450 " %s by the host PF kernel ethdev driver",
2459 hns3vf_restore_conf(struct hns3_adapter *hns)
2461 struct hns3_hw *hw = &hns->hw;
2464 ret = hns3vf_check_default_mac_change(hw);
2468 ret = hns3_configure_all_mac_addr(hns, false);
2472 ret = hns3_configure_all_mc_mac_addr(hns, false);
2476 ret = hns3vf_restore_promisc(hns);
2478 goto err_vlan_table;
2480 ret = hns3vf_restore_vlan_conf(hns);
2482 goto err_vlan_table;
2484 ret = hns3vf_get_port_base_vlan_filter_state(hw);
2486 goto err_vlan_table;
2488 ret = hns3vf_restore_rx_interrupt(hw);
2490 goto err_vlan_table;
2492 ret = hns3_restore_gro_conf(hw);
2494 goto err_vlan_table;
2496 if (hw->adapter_state == HNS3_NIC_STARTED) {
2497 ret = hns3vf_do_start(hns, false);
2499 goto err_vlan_table;
2500 hns3_info(hw, "hns3vf dev restart successful!");
2501 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2502 hw->adapter_state = HNS3_NIC_CONFIGURED;
2504 ret = hns3vf_set_alive(hw, true);
2506 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2507 goto err_vlan_table;
2513 hns3_configure_all_mc_mac_addr(hns, true);
2515 hns3_configure_all_mac_addr(hns, true);
2519 static enum hns3_reset_level
2520 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2522 enum hns3_reset_level reset_level;
2524 /* return the highest priority reset level amongst all */
2525 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2526 reset_level = HNS3_VF_RESET;
2527 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2528 reset_level = HNS3_VF_FULL_RESET;
2529 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2530 reset_level = HNS3_VF_PF_FUNC_RESET;
2531 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2532 reset_level = HNS3_VF_FUNC_RESET;
2533 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2534 reset_level = HNS3_FLR_RESET;
2536 reset_level = HNS3_NONE_RESET;
2538 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2539 return HNS3_NONE_RESET;
2545 hns3vf_reset_service(void *param)
2547 struct hns3_adapter *hns = (struct hns3_adapter *)param;
2548 struct hns3_hw *hw = &hns->hw;
2549 enum hns3_reset_level reset_level;
2550 struct timeval tv_delta;
2551 struct timeval tv_start;
2556 * The interrupt is not triggered within the delay time.
2557 * The interrupt may have been lost. It is necessary to handle
2558 * the interrupt to recover from the error.
2560 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2561 SCHEDULE_DEFERRED) {
2562 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2564 hns3_err(hw, "Handling interrupts in delayed tasks");
2565 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2566 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2567 if (reset_level == HNS3_NONE_RESET) {
2568 hns3_err(hw, "No reset level is set, try global reset");
2569 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2572 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2575 * Hardware reset has been notified, we now have to poll & check if
2576 * hardware has actually completed the reset sequence.
2578 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2579 if (reset_level != HNS3_NONE_RESET) {
2580 hns3_clock_gettime(&tv_start);
2581 hns3_reset_process(hns, reset_level);
2582 hns3_clock_gettime(&tv);
2583 timersub(&tv, &tv_start, &tv_delta);
2584 msec = hns3_clock_calctime_ms(&tv_delta);
2585 if (msec > HNS3_RESET_PROCESS_MS)
2586 hns3_err(hw, "%d handle long time delta %" PRIu64
2587 " ms time=%ld.%.6ld",
2588 hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2593 hns3vf_reinit_dev(struct hns3_adapter *hns)
2595 struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2596 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2597 struct hns3_hw *hw = &hns->hw;
2600 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2601 rte_intr_disable(pci_dev->intr_handle);
2602 ret = hns3vf_set_bus_master(pci_dev, true);
2604 hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2609 /* Firmware command initialize */
2610 ret = hns3_cmd_init(hw);
2612 hns3_err(hw, "Failed to init cmd: %d", ret);
2616 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2618 * UIO enables msix by writing the pcie configuration space
2619 * vfio_pci enables msix in rte_intr_enable.
2621 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2622 pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2623 if (hns3vf_enable_msix(pci_dev, true))
2624 hns3_err(hw, "Failed to enable msix");
2627 rte_intr_enable(pci_dev->intr_handle);
2630 ret = hns3_reset_all_tqps(hns);
2632 hns3_err(hw, "Failed to reset all queues: %d", ret);
2636 ret = hns3vf_init_hardware(hns);
2638 hns3_err(hw, "Failed to init hardware: %d", ret);
2645 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2646 .dev_configure = hns3vf_dev_configure,
2647 .dev_start = hns3vf_dev_start,
2648 .dev_stop = hns3vf_dev_stop,
2649 .dev_close = hns3vf_dev_close,
2650 .mtu_set = hns3vf_dev_mtu_set,
2651 .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2652 .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2653 .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2654 .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2655 .stats_get = hns3_stats_get,
2656 .stats_reset = hns3_stats_reset,
2657 .xstats_get = hns3_dev_xstats_get,
2658 .xstats_get_names = hns3_dev_xstats_get_names,
2659 .xstats_reset = hns3_dev_xstats_reset,
2660 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
2661 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2662 .dev_infos_get = hns3vf_dev_infos_get,
2663 .fw_version_get = hns3vf_fw_version_get,
2664 .rx_queue_setup = hns3_rx_queue_setup,
2665 .tx_queue_setup = hns3_tx_queue_setup,
2666 .rx_queue_release = hns3_dev_rx_queue_release,
2667 .tx_queue_release = hns3_dev_tx_queue_release,
2668 .rx_queue_start = hns3_dev_rx_queue_start,
2669 .rx_queue_stop = hns3_dev_rx_queue_stop,
2670 .tx_queue_start = hns3_dev_tx_queue_start,
2671 .tx_queue_stop = hns3_dev_tx_queue_stop,
2672 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
2673 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
2674 .rxq_info_get = hns3_rxq_info_get,
2675 .txq_info_get = hns3_txq_info_get,
2676 .rx_burst_mode_get = hns3_rx_burst_mode_get,
2677 .tx_burst_mode_get = hns3_tx_burst_mode_get,
2678 .mac_addr_add = hns3_add_mac_addr,
2679 .mac_addr_remove = hns3_remove_mac_addr,
2680 .mac_addr_set = hns3vf_set_default_mac_addr,
2681 .set_mc_addr_list = hns3vf_set_mc_mac_addr_list,
2682 .link_update = hns3vf_dev_link_update,
2683 .rss_hash_update = hns3_dev_rss_hash_update,
2684 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
2685 .reta_update = hns3_dev_rss_reta_update,
2686 .reta_query = hns3_dev_rss_reta_query,
2687 .flow_ops_get = hns3_dev_flow_ops_get,
2688 .vlan_filter_set = hns3vf_vlan_filter_set,
2689 .vlan_offload_set = hns3vf_vlan_offload_set,
2690 .get_reg = hns3_get_regs,
2691 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2692 .tx_done_cleanup = hns3_tx_done_cleanup,
2695 static const struct hns3_reset_ops hns3vf_reset_ops = {
2696 .reset_service = hns3vf_reset_service,
2697 .stop_service = hns3vf_stop_service,
2698 .prepare_reset = hns3vf_prepare_reset,
2699 .wait_hardware_ready = hns3vf_wait_hardware_ready,
2700 .reinit_dev = hns3vf_reinit_dev,
2701 .restore_conf = hns3vf_restore_conf,
2702 .start_service = hns3vf_start_service,
2706 hns3vf_init_hw_ops(struct hns3_hw *hw)
2708 hw->ops.add_mc_mac_addr = hns3vf_add_mc_mac_addr;
2709 hw->ops.del_mc_mac_addr = hns3vf_remove_mc_mac_addr;
2710 hw->ops.add_uc_mac_addr = hns3vf_add_uc_mac_addr;
2711 hw->ops.del_uc_mac_addr = hns3vf_remove_uc_mac_addr;
2715 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2717 struct hns3_adapter *hns = eth_dev->data->dev_private;
2718 struct hns3_hw *hw = &hns->hw;
2721 PMD_INIT_FUNC_TRACE();
2723 hns3_flow_init(eth_dev);
2725 hns3_set_rxtx_function(eth_dev);
2726 eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2727 eth_dev->rx_queue_count = hns3_rx_queue_count;
2728 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2729 ret = hns3_mp_init_secondary();
2731 PMD_INIT_LOG(ERR, "Failed to init for secondary "
2732 "process, ret = %d", ret);
2733 goto err_mp_init_secondary;
2735 hw->secondary_cnt++;
2736 hns3_tx_push_init(eth_dev);
2740 ret = hns3_mp_init_primary();
2743 "Failed to init for primary process, ret = %d",
2745 goto err_mp_init_primary;
2748 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2750 hw->data = eth_dev->data;
2751 hns3_parse_devargs(eth_dev);
2753 ret = hns3_reset_init(hw);
2755 goto err_init_reset;
2756 hw->reset.ops = &hns3vf_reset_ops;
2758 hns3vf_init_hw_ops(hw);
2759 ret = hns3vf_init_vf(eth_dev);
2761 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2765 /* Allocate memory for storing MAC addresses */
2766 eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2767 sizeof(struct rte_ether_addr) *
2768 HNS3_VF_UC_MACADDR_NUM, 0);
2769 if (eth_dev->data->mac_addrs == NULL) {
2770 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2771 "to store MAC addresses",
2772 sizeof(struct rte_ether_addr) *
2773 HNS3_VF_UC_MACADDR_NUM);
2775 goto err_rte_zmalloc;
2779 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2780 * on the host by "ip link set ..." command. To avoid some incorrect
2781 * scenes, for example, hns3 VF PMD driver fails to receive and send
2782 * packets after user configure the MAC address by using the
2783 * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2784 * address strategy as the hns3 kernel ethdev driver in the
2785 * initialization. If user configure a MAC address by the ip command
2786 * for VF device, then hns3 VF PMD driver will start with it, otherwise
2787 * start with a random MAC address in the initialization.
2789 if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2790 rte_eth_random_addr(hw->mac.mac_addr);
2791 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2792 ð_dev->data->mac_addrs[0]);
2794 hw->adapter_state = HNS3_NIC_INITIALIZED;
2796 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2798 hns3_err(hw, "Reschedule reset service after dev_init");
2799 hns3_schedule_reset(hns);
2801 /* IMP will wait ready flag before reset */
2802 hns3_notify_reset_ready(hw, false);
2804 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2809 hns3vf_uninit_vf(eth_dev);
2812 rte_free(hw->reset.wait_data);
2815 hns3_mp_uninit_primary();
2817 err_mp_init_primary:
2818 err_mp_init_secondary:
2819 eth_dev->dev_ops = NULL;
2820 eth_dev->rx_pkt_burst = NULL;
2821 eth_dev->rx_descriptor_status = NULL;
2822 eth_dev->tx_pkt_burst = NULL;
2823 eth_dev->tx_pkt_prepare = NULL;
2824 eth_dev->tx_descriptor_status = NULL;
2830 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2832 struct hns3_adapter *hns = eth_dev->data->dev_private;
2833 struct hns3_hw *hw = &hns->hw;
2835 PMD_INIT_FUNC_TRACE();
2837 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2840 if (hw->adapter_state < HNS3_NIC_CLOSING)
2841 hns3vf_dev_close(eth_dev);
2843 hw->adapter_state = HNS3_NIC_REMOVED;
2848 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2849 struct rte_pci_device *pci_dev)
2851 return rte_eth_dev_pci_generic_probe(pci_dev,
2852 sizeof(struct hns3_adapter),
2857 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2859 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2862 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2863 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2864 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2865 { .vendor_id = 0, }, /* sentinel */
2868 static struct rte_pci_driver rte_hns3vf_pmd = {
2869 .id_table = pci_id_hns3vf_map,
2870 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2871 .probe = eth_hns3vf_pci_probe,
2872 .remove = eth_hns3vf_pci_remove,
2875 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2876 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2877 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
2878 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
2879 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
2880 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
2881 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
2882 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16_t> ");