drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static void
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71
  72         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  73
  74         if (op)
  75                 /* set the master bit */
  76                 reg |= PCI_COMMAND_MASTER;
  77         else
  78                 reg &= ~(PCI_COMMAND_MASTER);
  79
  80         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  81 }
  82
  83 /**
  84  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  85  * @cap: the capability
  86  *
  87  * Return the address of the given capability within the PCI capability list.
  88  */
  89 static int
  90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  91 {
  92 #define MAX_PCIE_CAPABILITY 48
  93         uint16_t status;
  94         uint8_t pos;
  95         uint8_t id;
  96         int ttl;
  97
  98         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  99         if (!(status & PCI_STATUS_CAP_LIST))
 100                 return 0;
 101
 102         ttl = MAX_PCIE_CAPABILITY;
 103         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 rte_pci_read_config(device, &id, sizeof(id),
 106                                     (pos + PCI_CAP_LIST_ID));
 107
 108                 if (id == 0xFF)
 109                         break;
 110
 111                 if (id == cap)
 112                         return (int)pos;
 113
 114                 rte_pci_read_config(device, &pos, sizeof(pos),
 115                                     (pos + PCI_CAP_LIST_NEXT));
 116         }
 117         return 0;
 118 }
 119
 120 static int
 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 122 {
 123         uint16_t control;
 124         int pos;
 125
 126         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 127         if (pos) {
 128                 rte_pci_read_config(device, &control, sizeof(control),
 129                                     (pos + PCI_MSIX_FLAGS));
 130                 if (op)
 131                         control |= PCI_MSIX_FLAGS_ENABLE;
 132                 else
 133                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 134                 rte_pci_write_config(device, &control, sizeof(control),
 135                                      (pos + PCI_MSIX_FLAGS));
 136                 return 0;
 137         }
 138         return -ENXIO;
 139 }
 140
 141 static int
 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 143 {
 144         /* mac address was checked by upper level interface */
 145         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 146         int ret;
 147
 148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 149                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 150                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 155                          mac_str, ret);
 156         }
 157         return ret;
 158 }
 159
 160 static int
 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 162 {
 163         /* mac address was checked by upper level interface */
 164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 165         int ret;
 166
 167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 168                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 169                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 170                                 false, NULL, 0);
 171         if (ret) {
 172                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 173                                       mac_addr);
 174                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 175                          mac_str, ret);
 176         }
 177         return ret;
 178 }
 179
 180 static int
 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 182 {
 183         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 184         struct rte_ether_addr *addr;
 185         int ret;
 186         int i;
 187
 188         for (i = 0; i < hw->mc_addrs_num; i++) {
 189                 addr = &hw->mc_addrs[i];
 190                 /* Check if there are duplicate addresses */
 191                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 192                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 193                                               addr);
 194                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 195                                  "(%s) is added by the set_mc_mac_addr_list "
 196                                  "API", mac_str);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 202         if (ret) {
 203                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 204                                       mac_addr);
 205                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 206                          mac_str, ret);
 207         }
 208         return ret;
 209 }
 210
 211 static int
 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 213                     __rte_unused uint32_t idx,
 214                     __rte_unused uint32_t pool)
 215 {
 216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 218         int ret;
 219
 220         rte_spinlock_lock(&hw->lock);
 221
 222         /*
 223          * In hns3 network engine adding UC and MC mac address with different
 224          * commands with firmware. We need to determine whether the input
 225          * address is a UC or a MC address to call different commands.
 226          * By the way, it is recommended calling the API function named
 227          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 228          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 229          * may affect the specifications of UC mac addresses.
 230          */
 231         if (rte_is_multicast_ether_addr(mac_addr))
 232                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 233         else
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235
 236         rte_spinlock_unlock(&hw->lock);
 237         if (ret) {
 238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 239                                       mac_addr);
 240                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 241                          ret);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 249 {
 250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 251         /* index will be checked by upper level rte interface */
 252         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 260         else
 261                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 268                          mac_str, ret);
 269         }
 270 }
 271
 272 static int
 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                             struct rte_ether_addr *mac_addr)
 275 {
 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         struct rte_ether_addr *old_addr;
 279         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         /*
 284          * It has been guaranteed that input parameter named mac_addr is valid
 285          * address in the rte layer of DPDK framework.
 286          */
 287         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 288         rte_spinlock_lock(&hw->lock);
 289         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 290         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 291                RTE_ETHER_ADDR_LEN);
 292
 293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 294                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 295                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 296         if (ret) {
 297                 /*
 298                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 299                  * driver. When user has configured a MAC address for VF device
 300                  * by "ip link set ..." command based on the PF device, the hns3
 301                  * PF kernel ethdev driver does not allow VF driver to request
 302                  * reconfiguring a different default MAC address, and return
 303                  * -EPREM to VF driver through mailbox.
 304                  */
 305                 if (ret == -EPERM) {
 306                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 307                                               old_addr);
 308                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 309                                   mac_str);
 310                 } else {
 311                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 312                                               mac_addr);
 313                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 314                                  mac_str, ret);
 315                 }
 316         }
 317
 318         rte_ether_addr_copy(mac_addr,
 319                             (struct rte_ether_addr *)hw->mac.mac_addr);
 320         rte_spinlock_unlock(&hw->lock);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 327 {
 328         struct hns3_hw *hw = &hns->hw;
 329         struct rte_ether_addr *addr;
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int err = 0;
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 336                 addr = &hw->data->mac_addrs[i];
 337                 if (rte_is_zero_ether_addr(addr))
 338                         continue;
 339                 if (rte_is_multicast_ether_addr(addr))
 340                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 341                               hns3vf_add_mc_mac_addr(hw, addr);
 342                 else
 343                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 344                               hns3vf_add_uc_mac_addr(hw, addr);
 345
 346                 if (ret) {
 347                         err = ret;
 348                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 349                                               addr);
 350                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 351                                  "ret = %d.", del ? "remove" : "restore",
 352                                  mac_str, i, ret);
 353                 }
 354         }
 355         return err;
 356 }
 357
 358 static int
 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 360                        struct rte_ether_addr *mac_addr)
 361 {
 362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 363         int ret;
 364
 365         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 366                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 367                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 368                                 NULL, 0);
 369         if (ret) {
 370                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 371                                       mac_addr);
 372                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 373                          mac_str, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int
 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 381                           struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 402                              struct rte_ether_addr *mc_addr_set,
 403                              uint32_t nb_mc_addr)
 404 {
 405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 406         struct rte_ether_addr *addr;
 407         uint32_t i;
 408         uint32_t j;
 409
 410         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 411                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 412                          "invalid. valid range: 0~%d",
 413                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 414                 return -EINVAL;
 415         }
 416
 417         /* Check if input mac addresses are valid */
 418         for (i = 0; i < nb_mc_addr; i++) {
 419                 addr = &mc_addr_set[i];
 420                 if (!rte_is_multicast_ether_addr(addr)) {
 421                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 422                                               addr);
 423                         hns3_err(hw,
 424                                  "failed to set mc mac addr, addr(%s) invalid.",
 425                                  mac_str);
 426                         return -EINVAL;
 427                 }
 428
 429                 /* Check if there are duplicate addresses */
 430                 for (j = i + 1; j < nb_mc_addr; j++) {
 431                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 432                                 rte_ether_format_addr(mac_str,
 433                                                       RTE_ETHER_ADDR_FMT_SIZE,
 434                                                       addr);
 435                                 hns3_err(hw, "failed to set mc mac addr, "
 436                                          "addrs invalid. two same addrs(%s).",
 437                                          mac_str);
 438                                 return -EINVAL;
 439                         }
 440                 }
 441
 442                 /*
 443                  * Check if there are duplicate addresses between mac_addrs
 444                  * and mc_addr_set
 445                  */
 446                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 447                         if (rte_is_same_ether_addr(addr,
 448                                                    &hw->data->mac_addrs[j])) {
 449                                 rte_ether_format_addr(mac_str,
 450                                                       RTE_ETHER_ADDR_FMT_SIZE,
 451                                                       addr);
 452                                 hns3_err(hw, "failed to set mc mac addr, "
 453                                          "addrs invalid. addrs(%s) has already "
 454                                          "configured in mac_addr add API",
 455                                          mac_str);
 456                                 return -EINVAL;
 457                         }
 458                 }
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int
 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 466                             struct rte_ether_addr *mc_addr_set,
 467                             uint32_t nb_mc_addr)
 468 {
 469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 470         struct rte_ether_addr *addr;
 471         int cur_addr_num;
 472         int set_addr_num;
 473         int num;
 474         int ret;
 475         int i;
 476
 477         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 478         if (ret)
 479                 return ret;
 480
 481         rte_spinlock_lock(&hw->lock);
 482         cur_addr_num = hw->mc_addrs_num;
 483         for (i = 0; i < cur_addr_num; i++) {
 484                 num = cur_addr_num - i - 1;
 485                 addr = &hw->mc_addrs[num];
 486                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 487                 if (ret) {
 488                         rte_spinlock_unlock(&hw->lock);
 489                         return ret;
 490                 }
 491
 492                 hw->mc_addrs_num--;
 493         }
 494
 495         set_addr_num = (int)nb_mc_addr;
 496         for (i = 0; i < set_addr_num; i++) {
 497                 addr = &mc_addr_set[i];
 498                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 499                 if (ret) {
 500                         rte_spinlock_unlock(&hw->lock);
 501                         return ret;
 502                 }
 503
 504                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 505                 hw->mc_addrs_num++;
 506         }
 507         rte_spinlock_unlock(&hw->lock);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 514 {
 515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 516         struct hns3_hw *hw = &hns->hw;
 517         struct rte_ether_addr *addr;
 518         int err = 0;
 519         int ret;
 520         int i;
 521
 522         for (i = 0; i < hw->mc_addrs_num; i++) {
 523                 addr = &hw->mc_addrs[i];
 524                 if (!rte_is_multicast_ether_addr(addr))
 525                         continue;
 526                 if (del)
 527                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 528                 else
 529                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 530                 if (ret) {
 531                         err = ret;
 532                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 533                                               addr);
 534                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 535                                  del ? "Remove" : "Restore", mac_str, ret);
 536                 }
 537         }
 538         return err;
 539 }
 540
 541 static int
 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 543                         bool en_uc_pmc, bool en_mc_pmc)
 544 {
 545         struct hns3_mbx_vf_to_pf_cmd *req;
 546         struct hns3_cmd_desc desc;
 547         int ret;
 548
 549         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 550
 551         /*
 552          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 553          * so there are some features for promiscuous/allmulticast mode in hns3
 554          * VF PMD driver as below:
 555          * 1. The promiscuous/allmulticast mode can be configured successfully
 556          *    only based on the trusted VF device. If based on the non trusted
 557          *    VF device, configuring promiscuous/allmulticast mode will fail.
 558          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 559          *    kernel ethdev driver on the host by the following command:
 560          *      "ip link set <eth num> vf <vf id> turst on"
 561          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 562          *    driver can receive the ingress and outgoing traffic. In the words,
 563          *    all the ingress packets, all the packets sent from the PF and
 564          *    other VFs on the same physical port.
 565          * 3. Note: Because of the hardware constraints, By default vlan filter
 566          *    is enabled and couldn't be turned off based on VF device, so vlan
 567          *    filter is still effective even in promiscuous mode. If upper
 568          *    applications don't call rte_eth_dev_vlan_filter API function to
 569          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 570          *    the packets with vlan tag in promiscuoue mode.
 571          */
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 573         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 574         req->msg[1] = en_bc_pmc ? 1 : 0;
 575         req->msg[2] = en_uc_pmc ? 1 : 0;
 576         req->msg[3] = en_mc_pmc ? 1 : 0;
 577
 578         ret = hns3_cmd_send(hw, &desc, 1);
 579         if (ret)
 580                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 587 {
 588         struct hns3_adapter *hns = dev->data->dev_private;
 589         struct hns3_hw *hw = &hns->hw;
 590         int ret;
 591
 592         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 593         if (ret)
 594                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 595                         ret);
 596         return ret;
 597 }
 598
 599 static int
 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         bool allmulti = dev->data->all_multicast ? true : false;
 603         struct hns3_adapter *hns = dev->data->dev_private;
 604         struct hns3_hw *hw = &hns->hw;
 605         int ret;
 606
 607         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 608         if (ret)
 609                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 610                         ret);
 611         return ret;
 612 }
 613
 614 static int
 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 616 {
 617         struct hns3_adapter *hns = dev->data->dev_private;
 618         struct hns3_hw *hw = &hns->hw;
 619         int ret;
 620
 621         if (dev->data->promiscuous)
 622                 return 0;
 623
 624         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 625         if (ret)
 626                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 627                         ret);
 628         return ret;
 629 }
 630
 631 static int
 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 633 {
 634         struct hns3_adapter *hns = dev->data->dev_private;
 635         struct hns3_hw *hw = &hns->hw;
 636         int ret;
 637
 638         if (dev->data->promiscuous)
 639                 return 0;
 640
 641         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 642         if (ret)
 643                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 644                         ret);
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_restore_promisc(struct hns3_adapter *hns)
 650 {
 651         struct hns3_hw *hw = &hns->hw;
 652         bool allmulti = hw->data->all_multicast ? true : false;
 653
 654         if (hw->data->promiscuous)
 655                 return hns3vf_set_promisc_mode(hw, true, true, true);
 656
 657         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 658 }
 659
 660 static int
 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 662                              bool mmap, enum hns3_ring_type queue_type,
 663                              uint16_t queue_id)
 664 {
 665         struct hns3_vf_bind_vector_msg bind_msg;
 666         const char *op_str;
 667         uint16_t code;
 668         int ret;
 669
 670         memset(&bind_msg, 0, sizeof(bind_msg));
 671         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 672                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 673         bind_msg.vector_id = vector_id;
 674
 675         if (queue_type == HNS3_RING_TYPE_RX)
 676                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 677         else
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 679
 680         bind_msg.param[0].ring_type = queue_type;
 681         bind_msg.ring_num = 1;
 682         bind_msg.param[0].tqp_index = queue_id;
 683         op_str = mmap ? "Map" : "Unmap";
 684         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 685                                 sizeof(bind_msg), false, NULL, 0);
 686         if (ret)
 687                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 688                          op_str, queue_id, bind_msg.vector_id, ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 695 {
 696         uint16_t vec;
 697         int ret;
 698         int i;
 699
 700         /*
 701          * In hns3 network engine, vector 0 is always the misc interrupt of this
 702          * function, vector 1~N can be used respectively for the queues of the
 703          * function. Tx and Rx queues with the same number share the interrupt
 704          * vector. In the initialization clearing the all hardware mapping
 705          * relationship configurations between queues and interrupt vectors is
 706          * needed, so some error caused by the residual configurations, such as
 707          * the unexpected Tx interrupt, can be avoid.
 708          */
 709         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 710         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 711                 vec = vec - 1; /* the last interrupt is reserved */
 712         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 713         for (i = 0; i < hw->intr_tqps_num; i++) {
 714                 /*
 715                  * Set gap limiter/rate limiter/quanity limiter algorithm
 716                  * configuration for interrupt coalesce of queue's interrupt.
 717                  */
 718                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 719                                        HNS3_TQP_INTR_GL_DEFAULT);
 720                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 721                                        HNS3_TQP_INTR_GL_DEFAULT);
 722                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 723                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 724
 725                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 726                                                    HNS3_RING_TYPE_TX, i);
 727                 if (ret) {
 728                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 729                                           "vector: %d, ret=%d", i, vec, ret);
 730                         return ret;
 731                 }
 732
 733                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 734                                                    HNS3_RING_TYPE_RX, i);
 735                 if (ret) {
 736                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 737                                           "vector: %d, ret=%d", i, vec, ret);
 738                         return ret;
 739                 }
 740         }
 741
 742         return 0;
 743 }
 744
 745 static int
 746 hns3vf_dev_configure(struct rte_eth_dev *dev)
 747 {
 748         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 749         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 750         struct rte_eth_conf *conf = &dev->data->dev_conf;
 751         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 752         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 753         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 754         struct rte_eth_rss_conf rss_conf;
 755         uint16_t mtu;
 756         bool gro_en;
 757         int ret;
 758
 759         /*
 760          * Hardware does not support individually enable/disable/reset the Tx or
 761          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 762          * and Rx queues at the same time. When the numbers of Tx queues
 763          * allocated by upper applications are not equal to the numbers of Rx
 764          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 765          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 766          * these fake queues are imperceptible, and can not be used by upper
 767          * applications.
 768          */
 769         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 770         if (ret) {
 771                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 772                 return ret;
 773         }
 774
 775         hw->adapter_state = HNS3_NIC_CONFIGURING;
 776         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 777                 hns3_err(hw, "setting link speed/duplex not supported");
 778                 ret = -EINVAL;
 779                 goto cfg_err;
 780         }
 781
 782         /* When RSS is not configured, redirect the packet queue 0 */
 783         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 784                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 785                 rss_conf = conf->rx_adv_conf.rss_conf;
 786                 if (rss_conf.rss_key == NULL) {
 787                         rss_conf.rss_key = rss_cfg->key;
 788                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 789                 }
 790
 791                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 792                 if (ret)
 793                         goto cfg_err;
 794         }
 795
 796         /*
 797          * If jumbo frames are enabled, MTU needs to be refreshed
 798          * according to the maximum RX packet length.
 799          */
 800         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 801                 /*
 802                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 803                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 804                  * can safely assign to "uint16_t" type variable.
 805                  */
 806                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 807                 ret = hns3vf_dev_mtu_set(dev, mtu);
 808                 if (ret)
 809                         goto cfg_err;
 810                 dev->data->mtu = mtu;
 811         }
 812
 813         ret = hns3vf_dev_configure_vlan(dev);
 814         if (ret)
 815                 goto cfg_err;
 816
 817         /* config hardware GRO */
 818         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 819         ret = hns3_config_gro(hw, gro_en);
 820         if (ret)
 821                 goto cfg_err;
 822
 823         hw->adapter_state = HNS3_NIC_CONFIGURED;
 824         return 0;
 825
 826 cfg_err:
 827         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 828         hw->adapter_state = HNS3_NIC_INITIALIZED;
 829
 830         return ret;
 831 }
 832
 833 static int
 834 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 835 {
 836         int ret;
 837
 838         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 839                                 sizeof(mtu), true, NULL, 0);
 840         if (ret)
 841                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 842
 843         return ret;
 844 }
 845
 846 static int
 847 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 848 {
 849         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 850         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 851         int ret;
 852
 853         /*
 854          * The hns3 PF/VF devices on the same port share the hardware MTU
 855          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 856          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 857          * driver, there is no need to stop the port for hns3 VF device, and the
 858          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 859          * PF's MTU.
 860          */
 861         if (rte_atomic16_read(&hw->reset.resetting)) {
 862                 hns3_err(hw, "Failed to set mtu during resetting");
 863                 return -EIO;
 864         }
 865
 866         rte_spinlock_lock(&hw->lock);
 867         ret = hns3vf_config_mtu(hw, mtu);
 868         if (ret) {
 869                 rte_spinlock_unlock(&hw->lock);
 870                 return ret;
 871         }
 872         if (frame_size > RTE_ETHER_MAX_LEN)
 873                 dev->data->dev_conf.rxmode.offloads |=
 874                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 875         else
 876                 dev->data->dev_conf.rxmode.offloads &=
 877                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 878         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 879         rte_spinlock_unlock(&hw->lock);
 880
 881         return 0;
 882 }
 883
 884 static int
 885 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 886 {
 887         struct hns3_adapter *hns = eth_dev->data->dev_private;
 888         struct hns3_hw *hw = &hns->hw;
 889         uint16_t q_num = hw->tqps_num;
 890
 891         /*
 892          * In interrupt mode, 'max_rx_queues' is set based on the number of
 893          * MSI-X interrupt resources of the hardware.
 894          */
 895         if (hw->data->dev_conf.intr_conf.rxq == 1)
 896                 q_num = hw->intr_tqps_num;
 897
 898         info->max_rx_queues = q_num;
 899         info->max_tx_queues = hw->tqps_num;
 900         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 901         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 902         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 903         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 904         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 905
 906         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 907                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 908                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 909                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 910                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 911                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 912                                  DEV_RX_OFFLOAD_SCATTER |
 913                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 914                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 915                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 916                                  DEV_RX_OFFLOAD_RSS_HASH |
 917                                  DEV_RX_OFFLOAD_TCP_LRO);
 918         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 919                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 920                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 921                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 922                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 923                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 924                                  DEV_TX_OFFLOAD_TCP_TSO |
 925                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 926                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 927                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 928                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 929                                  hns3_txvlan_cap_get(hw));
 930
 931         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 932                 .nb_max = HNS3_MAX_RING_DESC,
 933                 .nb_min = HNS3_MIN_RING_DESC,
 934                 .nb_align = HNS3_ALIGN_RING_DESC,
 935         };
 936
 937         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 938                 .nb_max = HNS3_MAX_RING_DESC,
 939                 .nb_min = HNS3_MIN_RING_DESC,
 940                 .nb_align = HNS3_ALIGN_RING_DESC,
 941                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 942                 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT,
 943         };
 944
 945         info->default_rxconf = (struct rte_eth_rxconf) {
 946                 /*
 947                  * If there are no available Rx buffer descriptors, incoming
 948                  * packets are always dropped by hardware based on hns3 network
 949                  * engine.
 950                  */
 951                 .rx_drop_en = 1,
 952         };
 953
 954         info->vmdq_queue_num = 0;
 955
 956         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 957         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 958         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 959         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 960         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 961
 962         return 0;
 963 }
 964
 965 static void
 966 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 967 {
 968         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 969 }
 970
 971 static void
 972 hns3vf_disable_irq0(struct hns3_hw *hw)
 973 {
 974         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 975 }
 976
 977 static void
 978 hns3vf_enable_irq0(struct hns3_hw *hw)
 979 {
 980         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 981 }
 982
 983 static enum hns3vf_evt_cause
 984 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 985 {
 986         struct hns3_hw *hw = &hns->hw;
 987         enum hns3vf_evt_cause ret;
 988         uint32_t cmdq_stat_reg;
 989         uint32_t rst_ing_reg;
 990         uint32_t val;
 991
 992         /* Fetch the events from their corresponding regs */
 993         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 994
 995         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 996                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 997                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 998                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 999                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1000                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1001                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1002                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1003                 if (clearval) {
1004                         hw->reset.stats.global_cnt++;
1005                         hns3_warn(hw, "Global reset detected, clear reset status");
1006                 } else {
1007                         hns3_schedule_delayed_reset(hns);
1008                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1009                 }
1010
1011                 ret = HNS3VF_VECTOR0_EVENT_RST;
1012                 goto out;
1013         }
1014
1015         /* Check for vector0 mailbox(=CMDQ RX) event source */
1016         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1017                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1018                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1019                 goto out;
1020         }
1021
1022         val = 0;
1023         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1024 out:
1025         if (clearval)
1026                 *clearval = val;
1027         return ret;
1028 }
1029
1030 static void
1031 hns3vf_interrupt_handler(void *param)
1032 {
1033         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1034         struct hns3_adapter *hns = dev->data->dev_private;
1035         struct hns3_hw *hw = &hns->hw;
1036         enum hns3vf_evt_cause event_cause;
1037         uint32_t clearval;
1038
1039         if (hw->irq_thread_id == 0)
1040                 hw->irq_thread_id = pthread_self();
1041
1042         /* Disable interrupt */
1043         hns3vf_disable_irq0(hw);
1044
1045         /* Read out interrupt causes */
1046         event_cause = hns3vf_check_event_cause(hns, &clearval);
1047
1048         switch (event_cause) {
1049         case HNS3VF_VECTOR0_EVENT_RST:
1050                 hns3_schedule_reset(hns);
1051                 break;
1052         case HNS3VF_VECTOR0_EVENT_MBX:
1053                 hns3_dev_handle_mbx_msg(hw);
1054                 break;
1055         default:
1056                 break;
1057         }
1058
1059         /* Clear interrupt causes */
1060         hns3vf_clear_event_cause(hw, clearval);
1061
1062         /* Enable interrupt */
1063         hns3vf_enable_irq0(hw);
1064 }
1065
1066 static void
1067 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1068 {
1069         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1070         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1071         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1072 }
1073
1074 static void
1075 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1076 {
1077         struct hns3_dev_specs_0_cmd *req0;
1078
1079         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1080
1081         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1082         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1083         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1084 }
1085
1086 static int
1087 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1088 {
1089         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1090         int ret;
1091         int i;
1092
1093         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1094                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1095                                           true);
1096                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1097         }
1098         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1099
1100         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1101         if (ret)
1102                 return ret;
1103
1104         hns3vf_parse_dev_specifications(hw, desc);
1105
1106         return 0;
1107 }
1108
1109 static int
1110 hns3vf_get_capability(struct hns3_hw *hw)
1111 {
1112         struct rte_pci_device *pci_dev;
1113         struct rte_eth_dev *eth_dev;
1114         uint8_t revision;
1115         int ret;
1116
1117         eth_dev = &rte_eth_devices[hw->data->port_id];
1118         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1119
1120         /* Get PCI revision id */
1121         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1122                                   HNS3_PCI_REVISION_ID);
1123         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1124                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1125                              ret);
1126                 return -EIO;
1127         }
1128         hw->revision = revision;
1129
1130         if (revision < PCI_REVISION_ID_HIP09_A) {
1131                 hns3vf_set_default_dev_specifications(hw);
1132                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1133                 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
1134                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1135                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1136                 return 0;
1137         }
1138
1139         ret = hns3vf_query_dev_specifications(hw);
1140         if (ret) {
1141                 PMD_INIT_LOG(ERR,
1142                              "failed to query dev specifications, ret = %d",
1143                              ret);
1144                 return ret;
1145         }
1146
1147         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1148         hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
1149         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1150         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1151
1152         return 0;
1153 }
1154
1155 static int
1156 hns3vf_check_tqp_info(struct hns3_hw *hw)
1157 {
1158         uint16_t tqps_num;
1159
1160         tqps_num = hw->tqps_num;
1161         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1162                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1163                                   "range: 1~%d",
1164                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1165                 return -EINVAL;
1166         }
1167
1168         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1169
1170         return 0;
1171 }
1172 static int
1173 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1174 {
1175         uint8_t resp_msg;
1176         int ret;
1177
1178         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1179                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1180                                 true, &resp_msg, sizeof(resp_msg));
1181         if (ret) {
1182                 if (ret == -ETIME) {
1183                         /*
1184                          * Getting current port based VLAN state from PF driver
1185                          * will not affect VF driver's basic function. Because
1186                          * the VF driver relies on hns3 PF kernel ether driver,
1187                          * to avoid introducing compatibility issues with older
1188                          * version of PF driver, no failure will be returned
1189                          * when the return value is ETIME. This return value has
1190                          * the following scenarios:
1191                          * 1) Firmware didn't return the results in time
1192                          * 2) the result return by firmware is timeout
1193                          * 3) the older version of kernel side PF driver does
1194                          *    not support this mailbox message.
1195                          * For scenarios 1 and 2, it is most likely that a
1196                          * hardware error has occurred, or a hardware reset has
1197                          * occurred. In this case, these errors will be caught
1198                          * by other functions.
1199                          */
1200                         PMD_INIT_LOG(WARNING,
1201                                 "failed to get PVID state for timeout, maybe "
1202                                 "kernel side PF driver doesn't support this "
1203                                 "mailbox message, or firmware didn't respond.");
1204                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1205                 } else {
1206                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1207                                 " ret = %d", ret);
1208                         return ret;
1209                 }
1210         }
1211         hw->port_base_vlan_cfg.state = resp_msg ?
1212                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1213         return 0;
1214 }
1215
1216 static int
1217 hns3vf_get_queue_info(struct hns3_hw *hw)
1218 {
1219 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1220         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1221         int ret;
1222
1223         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1224                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1225         if (ret) {
1226                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1227                 return ret;
1228         }
1229
1230         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1231         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1232
1233         return hns3vf_check_tqp_info(hw);
1234 }
1235
1236 static int
1237 hns3vf_get_queue_depth(struct hns3_hw *hw)
1238 {
1239 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1240         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1241         int ret;
1242
1243         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1244                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1245         if (ret) {
1246                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1247                              ret);
1248                 return ret;
1249         }
1250
1251         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1252         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1253
1254         return 0;
1255 }
1256
1257 static int
1258 hns3vf_get_tc_info(struct hns3_hw *hw)
1259 {
1260         uint8_t resp_msg;
1261         int ret;
1262
1263         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1264                                 true, &resp_msg, sizeof(resp_msg));
1265         if (ret) {
1266                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1267                          ret);
1268                 return ret;
1269         }
1270
1271         hw->hw_tc_map = resp_msg;
1272
1273         return 0;
1274 }
1275
1276 static int
1277 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1278 {
1279         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1280         int ret;
1281
1282         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1283                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1284         if (ret) {
1285                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1286                 return ret;
1287         }
1288
1289         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1290
1291         return 0;
1292 }
1293
1294 static int
1295 hns3vf_get_configuration(struct hns3_hw *hw)
1296 {
1297         int ret;
1298
1299         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1300         hw->rss_dis_flag = false;
1301
1302         /* Get device capability */
1303         ret = hns3vf_get_capability(hw);
1304         if (ret) {
1305                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1306                 return ret;
1307         }
1308
1309         /* Get queue configuration from PF */
1310         ret = hns3vf_get_queue_info(hw);
1311         if (ret)
1312                 return ret;
1313
1314         /* Get queue depth info from PF */
1315         ret = hns3vf_get_queue_depth(hw);
1316         if (ret)
1317                 return ret;
1318
1319         /* Get user defined VF MAC addr from PF */
1320         ret = hns3vf_get_host_mac_addr(hw);
1321         if (ret)
1322                 return ret;
1323
1324         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1325         if (ret)
1326                 return ret;
1327
1328         /* Get tc configuration from PF */
1329         return hns3vf_get_tc_info(hw);
1330 }
1331
1332 static int
1333 hns3vf_set_tc_info(struct hns3_adapter *hns)
1334 {
1335         struct hns3_hw *hw = &hns->hw;
1336         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1337         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1338         uint8_t i;
1339
1340         hw->num_tc = 0;
1341         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1342                 if (hw->hw_tc_map & BIT(i))
1343                         hw->num_tc++;
1344
1345         if (nb_rx_q < hw->num_tc) {
1346                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1347                          nb_rx_q, hw->num_tc);
1348                 return -EINVAL;
1349         }
1350
1351         if (nb_tx_q < hw->num_tc) {
1352                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1353                          nb_tx_q, hw->num_tc);
1354                 return -EINVAL;
1355         }
1356
1357         hns3_set_rss_size(hw, nb_rx_q);
1358         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1359
1360         return 0;
1361 }
1362
1363 static void
1364 hns3vf_request_link_info(struct hns3_hw *hw)
1365 {
1366         uint8_t resp_msg;
1367         int ret;
1368
1369         if (rte_atomic16_read(&hw->reset.resetting))
1370                 return;
1371         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1372                                 &resp_msg, sizeof(resp_msg));
1373         if (ret)
1374                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1375 }
1376
1377 static int
1378 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1379 {
1380 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1381         struct hns3_hw *hw = &hns->hw;
1382         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1383         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1384         uint8_t is_kill = on ? 0 : 1;
1385
1386         msg_data[0] = is_kill;
1387         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1388         memcpy(&msg_data[3], &proto, sizeof(proto));
1389
1390         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1391                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1392                                  0);
1393 }
1394
1395 static int
1396 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1397 {
1398         struct hns3_adapter *hns = dev->data->dev_private;
1399         struct hns3_hw *hw = &hns->hw;
1400         int ret;
1401
1402         if (rte_atomic16_read(&hw->reset.resetting)) {
1403                 hns3_err(hw,
1404                          "vf set vlan id failed during resetting, vlan_id =%u",
1405                          vlan_id);
1406                 return -EIO;
1407         }
1408         rte_spinlock_lock(&hw->lock);
1409         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1410         rte_spinlock_unlock(&hw->lock);
1411         if (ret)
1412                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1413                          vlan_id, ret);
1414
1415         return ret;
1416 }
1417
1418 static int
1419 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1420 {
1421         uint8_t msg_data;
1422         int ret;
1423
1424         msg_data = enable ? 1 : 0;
1425         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1426                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1427         if (ret)
1428                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1429
1430         return ret;
1431 }
1432
1433 static int
1434 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1435 {
1436         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1437         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1438         unsigned int tmp_mask;
1439         int ret = 0;
1440
1441         if (rte_atomic16_read(&hw->reset.resetting)) {
1442                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1443                              "mask = 0x%x", mask);
1444                 return -EIO;
1445         }
1446
1447         tmp_mask = (unsigned int)mask;
1448         /* Vlan stripping setting */
1449         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1450                 rte_spinlock_lock(&hw->lock);
1451                 /* Enable or disable VLAN stripping */
1452                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1453                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1454                 else
1455                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1456                 rte_spinlock_unlock(&hw->lock);
1457         }
1458
1459         return ret;
1460 }
1461
1462 static int
1463 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1464 {
1465         struct rte_vlan_filter_conf *vfc;
1466         struct hns3_hw *hw = &hns->hw;
1467         uint16_t vlan_id;
1468         uint64_t vbit;
1469         uint64_t ids;
1470         int ret = 0;
1471         uint32_t i;
1472
1473         vfc = &hw->data->vlan_filter_conf;
1474         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1475                 if (vfc->ids[i] == 0)
1476                         continue;
1477                 ids = vfc->ids[i];
1478                 while (ids) {
1479                         /*
1480                          * 64 means the num bits of ids, one bit corresponds to
1481                          * one vlan id
1482                          */
1483                         vlan_id = 64 * i;
1484                         /* count trailing zeroes */
1485                         vbit = ~ids & (ids - 1);
1486                         /* clear least significant bit set */
1487                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1488                         for (; vbit;) {
1489                                 vbit >>= 1;
1490                                 vlan_id++;
1491                         }
1492                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1493                         if (ret) {
1494                                 hns3_err(hw,
1495                                          "VF handle vlan table failed, ret =%d, on = %d",
1496                                          ret, on);
1497                                 return ret;
1498                         }
1499                 }
1500         }
1501
1502         return ret;
1503 }
1504
1505 static int
1506 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1507 {
1508         return hns3vf_handle_all_vlan_table(hns, 0);
1509 }
1510
1511 static int
1512 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1513 {
1514         struct hns3_hw *hw = &hns->hw;
1515         struct rte_eth_conf *dev_conf;
1516         bool en;
1517         int ret;
1518
1519         dev_conf = &hw->data->dev_conf;
1520         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1521                                                                    : false;
1522         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1523         if (ret)
1524                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1525                          ret);
1526         return ret;
1527 }
1528
1529 static int
1530 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1531 {
1532         struct hns3_adapter *hns = dev->data->dev_private;
1533         struct rte_eth_dev_data *data = dev->data;
1534         struct hns3_hw *hw = &hns->hw;
1535         int ret;
1536
1537         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1538             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1539             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1540                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1541                               "or hw_vlan_insert_pvid is not support!");
1542         }
1543
1544         /* Apply vlan offload setting */
1545         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1546         if (ret)
1547                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1548
1549         return ret;
1550 }
1551
1552 static int
1553 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1554 {
1555         uint8_t msg_data;
1556
1557         msg_data = alive ? 1 : 0;
1558         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1559                                  sizeof(msg_data), false, NULL, 0);
1560 }
1561
1562 static void
1563 hns3vf_keep_alive_handler(void *param)
1564 {
1565         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1566         struct hns3_adapter *hns = eth_dev->data->dev_private;
1567         struct hns3_hw *hw = &hns->hw;
1568         uint8_t respmsg;
1569         int ret;
1570
1571         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1572                                 false, &respmsg, sizeof(uint8_t));
1573         if (ret)
1574                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1575                          ret);
1576
1577         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1578                           eth_dev);
1579 }
1580
1581 static void
1582 hns3vf_service_handler(void *param)
1583 {
1584         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1585         struct hns3_adapter *hns = eth_dev->data->dev_private;
1586         struct hns3_hw *hw = &hns->hw;
1587
1588         /*
1589          * The query link status and reset processing are executed in the
1590          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1591          * and the query operation will time out after 30ms. In the case of
1592          * multiple PF/VFs, each query failure timeout causes the IMP reset
1593          * interrupt to fail to respond within 100ms.
1594          * Before querying the link status, check whether there is a reset
1595          * pending, and if so, abandon the query.
1596          */
1597         if (!hns3vf_is_reset_pending(hns))
1598                 hns3vf_request_link_info(hw);
1599         else
1600                 hns3_warn(hw, "Cancel the query when reset is pending");
1601
1602         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1603                           eth_dev);
1604 }
1605
1606 static int
1607 hns3_query_vf_resource(struct hns3_hw *hw)
1608 {
1609         struct hns3_vf_res_cmd *req;
1610         struct hns3_cmd_desc desc;
1611         uint16_t num_msi;
1612         int ret;
1613
1614         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1615         ret = hns3_cmd_send(hw, &desc, 1);
1616         if (ret) {
1617                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1618                 return ret;
1619         }
1620
1621         req = (struct hns3_vf_res_cmd *)desc.data;
1622         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1623                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1624         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1625                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1626                          num_msi, HNS3_MIN_VECTOR_NUM);
1627                 return -EINVAL;
1628         }
1629
1630         hw->num_msi = num_msi;
1631
1632         return 0;
1633 }
1634
1635 static int
1636 hns3vf_init_hardware(struct hns3_adapter *hns)
1637 {
1638         struct hns3_hw *hw = &hns->hw;
1639         uint16_t mtu = hw->data->mtu;
1640         int ret;
1641
1642         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1643         if (ret)
1644                 return ret;
1645
1646         ret = hns3vf_config_mtu(hw, mtu);
1647         if (ret)
1648                 goto err_init_hardware;
1649
1650         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1651         if (ret) {
1652                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1653                 goto err_init_hardware;
1654         }
1655
1656         ret = hns3_config_gro(hw, false);
1657         if (ret) {
1658                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1659                 goto err_init_hardware;
1660         }
1661
1662         /*
1663          * In the initialization clearing the all hardware mapping relationship
1664          * configurations between queues and interrupt vectors is needed, so
1665          * some error caused by the residual configurations, such as the
1666          * unexpected interrupt, can be avoid.
1667          */
1668         ret = hns3vf_init_ring_with_vector(hw);
1669         if (ret) {
1670                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1671                 goto err_init_hardware;
1672         }
1673
1674         ret = hns3vf_set_alive(hw, true);
1675         if (ret) {
1676                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1677                 goto err_init_hardware;
1678         }
1679
1680         hns3vf_request_link_info(hw);
1681         return 0;
1682
1683 err_init_hardware:
1684         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1685         return ret;
1686 }
1687
1688 static int
1689 hns3vf_clear_vport_list(struct hns3_hw *hw)
1690 {
1691         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1692                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1693                                  NULL, 0);
1694 }
1695
1696 static int
1697 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1698 {
1699         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1700         struct hns3_adapter *hns = eth_dev->data->dev_private;
1701         struct hns3_hw *hw = &hns->hw;
1702         int ret;
1703
1704         PMD_INIT_FUNC_TRACE();
1705
1706         /* Get hardware io base address from pcie BAR2 IO space */
1707         hw->io_base = pci_dev->mem_resource[2].addr;
1708
1709         /* Firmware command queue initialize */
1710         ret = hns3_cmd_init_queue(hw);
1711         if (ret) {
1712                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1713                 goto err_cmd_init_queue;
1714         }
1715
1716         /* Firmware command initialize */
1717         ret = hns3_cmd_init(hw);
1718         if (ret) {
1719                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1720                 goto err_cmd_init;
1721         }
1722
1723         /* Get VF resource */
1724         ret = hns3_query_vf_resource(hw);
1725         if (ret)
1726                 goto err_cmd_init;
1727
1728         rte_spinlock_init(&hw->mbx_resp.lock);
1729
1730         hns3vf_clear_event_cause(hw, 0);
1731
1732         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1733                                          hns3vf_interrupt_handler, eth_dev);
1734         if (ret) {
1735                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1736                 goto err_intr_callback_register;
1737         }
1738
1739         /* Enable interrupt */
1740         rte_intr_enable(&pci_dev->intr_handle);
1741         hns3vf_enable_irq0(hw);
1742
1743         /* Get configuration from PF */
1744         ret = hns3vf_get_configuration(hw);
1745         if (ret) {
1746                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1747                 goto err_get_config;
1748         }
1749
1750         ret = hns3vf_clear_vport_list(hw);
1751         if (ret) {
1752                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1753                 goto err_get_config;
1754         }
1755
1756         ret = hns3vf_init_hardware(hns);
1757         if (ret)
1758                 goto err_get_config;
1759
1760         hns3_set_default_rss_args(hw);
1761
1762         return 0;
1763
1764 err_get_config:
1765         hns3vf_disable_irq0(hw);
1766         rte_intr_disable(&pci_dev->intr_handle);
1767         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1768                              eth_dev);
1769 err_intr_callback_register:
1770 err_cmd_init:
1771         hns3_cmd_uninit(hw);
1772         hns3_cmd_destroy_queue(hw);
1773 err_cmd_init_queue:
1774         hw->io_base = NULL;
1775
1776         return ret;
1777 }
1778
1779 static void
1780 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1781 {
1782         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1783         struct hns3_adapter *hns = eth_dev->data->dev_private;
1784         struct hns3_hw *hw = &hns->hw;
1785
1786         PMD_INIT_FUNC_TRACE();
1787
1788         hns3_rss_uninit(hns);
1789         (void)hns3_config_gro(hw, false);
1790         (void)hns3vf_set_alive(hw, false);
1791         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1792         hns3vf_disable_irq0(hw);
1793         rte_intr_disable(&pci_dev->intr_handle);
1794         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1795                              eth_dev);
1796         hns3_cmd_uninit(hw);
1797         hns3_cmd_destroy_queue(hw);
1798         hw->io_base = NULL;
1799 }
1800
1801 static int
1802 hns3vf_do_stop(struct hns3_adapter *hns)
1803 {
1804         struct hns3_hw *hw = &hns->hw;
1805         bool reset_queue;
1806
1807         hw->mac.link_status = ETH_LINK_DOWN;
1808
1809         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1810                 hns3vf_configure_mac_addr(hns, true);
1811                 reset_queue = true;
1812         } else
1813                 reset_queue = false;
1814         return hns3_stop_queues(hns, reset_queue);
1815 }
1816
1817 static void
1818 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1819 {
1820         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1821         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1822         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1823         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1824         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1825         uint16_t q_id;
1826
1827         if (dev->data->dev_conf.intr_conf.rxq == 0)
1828                 return;
1829
1830         /* unmap the ring with vector */
1831         if (rte_intr_allow_others(intr_handle)) {
1832                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1833                 base = RTE_INTR_VEC_RXTX_OFFSET;
1834         }
1835         if (rte_intr_dp_is_en(intr_handle)) {
1836                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1837                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1838                                                            HNS3_RING_TYPE_RX,
1839                                                            q_id);
1840                         if (vec < base + intr_handle->nb_efd - 1)
1841                                 vec++;
1842                 }
1843         }
1844         /* Clean datapath event and queue/vec mapping */
1845         rte_intr_efd_disable(intr_handle);
1846         if (intr_handle->intr_vec) {
1847                 rte_free(intr_handle->intr_vec);
1848                 intr_handle->intr_vec = NULL;
1849         }
1850 }
1851
1852 static void
1853 hns3vf_dev_stop(struct rte_eth_dev *dev)
1854 {
1855         struct hns3_adapter *hns = dev->data->dev_private;
1856         struct hns3_hw *hw = &hns->hw;
1857
1858         PMD_INIT_FUNC_TRACE();
1859
1860         hw->adapter_state = HNS3_NIC_STOPPING;
1861         hns3_set_rxtx_function(dev);
1862         rte_wmb();
1863         /* Disable datapath on secondary process. */
1864         hns3_mp_req_stop_rxtx(dev);
1865         /* Prevent crashes when queues are still in use. */
1866         rte_delay_ms(hw->tqps_num);
1867
1868         rte_spinlock_lock(&hw->lock);
1869         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1870                 hns3vf_do_stop(hns);
1871                 hns3vf_unmap_rx_interrupt(dev);
1872                 hns3_dev_release_mbufs(hns);
1873                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1874         }
1875         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1876         rte_spinlock_unlock(&hw->lock);
1877 }
1878
1879 static void
1880 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1881 {
1882         struct hns3_adapter *hns = eth_dev->data->dev_private;
1883         struct hns3_hw *hw = &hns->hw;
1884
1885         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1886                 return;
1887
1888         if (hw->adapter_state == HNS3_NIC_STARTED)
1889                 hns3vf_dev_stop(eth_dev);
1890
1891         hw->adapter_state = HNS3_NIC_CLOSING;
1892         hns3_reset_abort(hns);
1893         hw->adapter_state = HNS3_NIC_CLOSED;
1894         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1895         hns3vf_configure_all_mc_mac_addr(hns, true);
1896         hns3vf_remove_all_vlan_table(hns);
1897         hns3vf_uninit_vf(eth_dev);
1898         hns3_free_all_queues(eth_dev);
1899         rte_free(hw->reset.wait_data);
1900         rte_free(eth_dev->process_private);
1901         eth_dev->process_private = NULL;
1902         hns3_mp_uninit_primary();
1903         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1904 }
1905
1906 static int
1907 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1908                       size_t fw_size)
1909 {
1910         struct hns3_adapter *hns = eth_dev->data->dev_private;
1911         struct hns3_hw *hw = &hns->hw;
1912         uint32_t version = hw->fw_version;
1913         int ret;
1914
1915         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1916                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1917                                       HNS3_FW_VERSION_BYTE3_S),
1918                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1919                                       HNS3_FW_VERSION_BYTE2_S),
1920                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1921                                       HNS3_FW_VERSION_BYTE1_S),
1922                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1923                                       HNS3_FW_VERSION_BYTE0_S));
1924         ret += 1; /* add the size of '\0' */
1925         if (fw_size < (uint32_t)ret)
1926                 return ret;
1927         else
1928                 return 0;
1929 }
1930
1931 static int
1932 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1933                        __rte_unused int wait_to_complete)
1934 {
1935         struct hns3_adapter *hns = eth_dev->data->dev_private;
1936         struct hns3_hw *hw = &hns->hw;
1937         struct hns3_mac *mac = &hw->mac;
1938         struct rte_eth_link new_link;
1939
1940         memset(&new_link, 0, sizeof(new_link));
1941         switch (mac->link_speed) {
1942         case ETH_SPEED_NUM_10M:
1943         case ETH_SPEED_NUM_100M:
1944         case ETH_SPEED_NUM_1G:
1945         case ETH_SPEED_NUM_10G:
1946         case ETH_SPEED_NUM_25G:
1947         case ETH_SPEED_NUM_40G:
1948         case ETH_SPEED_NUM_50G:
1949         case ETH_SPEED_NUM_100G:
1950         case ETH_SPEED_NUM_200G:
1951                 new_link.link_speed = mac->link_speed;
1952                 break;
1953         default:
1954                 new_link.link_speed = ETH_SPEED_NUM_100M;
1955                 break;
1956         }
1957
1958         new_link.link_duplex = mac->link_duplex;
1959         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1960         new_link.link_autoneg =
1961             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1962
1963         return rte_eth_linkstatus_set(eth_dev, &new_link);
1964 }
1965
1966 static int
1967 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1968 {
1969         struct hns3_hw *hw = &hns->hw;
1970         int ret;
1971
1972         ret = hns3vf_set_tc_info(hns);
1973         if (ret)
1974                 return ret;
1975
1976         ret = hns3_start_queues(hns, reset_queue);
1977         if (ret)
1978                 hns3_err(hw, "Failed to start queues: %d", ret);
1979
1980         return ret;
1981 }
1982
1983 static int
1984 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1985 {
1986         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1987         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1988         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1989         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1990         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1991         uint32_t intr_vector;
1992         uint16_t q_id;
1993         int ret;
1994
1995         if (dev->data->dev_conf.intr_conf.rxq == 0)
1996                 return 0;
1997
1998         /* disable uio/vfio intr/eventfd mapping */
1999         rte_intr_disable(intr_handle);
2000
2001         /* check and configure queue intr-vector mapping */
2002         if (rte_intr_cap_multiple(intr_handle) ||
2003             !RTE_ETH_DEV_SRIOV(dev).active) {
2004                 intr_vector = hw->used_rx_queues;
2005                 /* It creates event fd for each intr vector when MSIX is used */
2006                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2007                         return -EINVAL;
2008         }
2009         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2010                 intr_handle->intr_vec =
2011                         rte_zmalloc("intr_vec",
2012                                     hw->used_rx_queues * sizeof(int), 0);
2013                 if (intr_handle->intr_vec == NULL) {
2014                         hns3_err(hw, "Failed to allocate %d rx_queues"
2015                                      " intr_vec", hw->used_rx_queues);
2016                         ret = -ENOMEM;
2017                         goto vf_alloc_intr_vec_error;
2018                 }
2019         }
2020
2021         if (rte_intr_allow_others(intr_handle)) {
2022                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2023                 base = RTE_INTR_VEC_RXTX_OFFSET;
2024         }
2025         if (rte_intr_dp_is_en(intr_handle)) {
2026                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2027                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2028                                                            HNS3_RING_TYPE_RX,
2029                                                            q_id);
2030                         if (ret)
2031                                 goto vf_bind_vector_error;
2032                         intr_handle->intr_vec[q_id] = vec;
2033                         if (vec < base + intr_handle->nb_efd - 1)
2034                                 vec++;
2035                 }
2036         }
2037         rte_intr_enable(intr_handle);
2038         return 0;
2039
2040 vf_bind_vector_error:
2041         rte_intr_efd_disable(intr_handle);
2042         if (intr_handle->intr_vec) {
2043                 free(intr_handle->intr_vec);
2044                 intr_handle->intr_vec = NULL;
2045         }
2046         return ret;
2047 vf_alloc_intr_vec_error:
2048         rte_intr_efd_disable(intr_handle);
2049         return ret;
2050 }
2051
2052 static int
2053 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2054 {
2055         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2056         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2057         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2058         uint16_t q_id;
2059         int ret;
2060
2061         if (dev->data->dev_conf.intr_conf.rxq == 0)
2062                 return 0;
2063
2064         if (rte_intr_dp_is_en(intr_handle)) {
2065                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2066                         ret = hns3vf_bind_ring_with_vector(hw,
2067                                         intr_handle->intr_vec[q_id], true,
2068                                         HNS3_RING_TYPE_RX, q_id);
2069                         if (ret)
2070                                 return ret;
2071                 }
2072         }
2073
2074         return 0;
2075 }
2076
2077 static void
2078 hns3vf_restore_filter(struct rte_eth_dev *dev)
2079 {
2080         hns3_restore_rss_filter(dev);
2081 }
2082
2083 static int
2084 hns3vf_dev_start(struct rte_eth_dev *dev)
2085 {
2086         struct hns3_adapter *hns = dev->data->dev_private;
2087         struct hns3_hw *hw = &hns->hw;
2088         int ret;
2089
2090         PMD_INIT_FUNC_TRACE();
2091         if (rte_atomic16_read(&hw->reset.resetting))
2092                 return -EBUSY;
2093
2094         rte_spinlock_lock(&hw->lock);
2095         hw->adapter_state = HNS3_NIC_STARTING;
2096         ret = hns3vf_do_start(hns, true);
2097         if (ret) {
2098                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2099                 rte_spinlock_unlock(&hw->lock);
2100                 return ret;
2101         }
2102         ret = hns3vf_map_rx_interrupt(dev);
2103         if (ret) {
2104                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2105                 rte_spinlock_unlock(&hw->lock);
2106                 return ret;
2107         }
2108         hw->adapter_state = HNS3_NIC_STARTED;
2109         rte_spinlock_unlock(&hw->lock);
2110
2111         hns3_set_rxtx_function(dev);
2112         hns3_mp_req_start_rxtx(dev);
2113         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2114
2115         hns3vf_restore_filter(dev);
2116
2117         /* Enable interrupt of all rx queues before enabling queues */
2118         hns3_dev_all_rx_queue_intr_enable(hw, true);
2119         /*
2120          * When finished the initialization, enable queues to receive/transmit
2121          * packets.
2122          */
2123         hns3_enable_all_queues(hw, true);
2124
2125         return ret;
2126 }
2127
2128 static bool
2129 is_vf_reset_done(struct hns3_hw *hw)
2130 {
2131 #define HNS3_FUN_RST_ING_BITS \
2132         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2133          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2134          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2135          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2136
2137         uint32_t val;
2138
2139         if (hw->reset.level == HNS3_VF_RESET) {
2140                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2141                 if (val & HNS3_VF_RST_ING_BIT)
2142                         return false;
2143         } else {
2144                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2145                 if (val & HNS3_FUN_RST_ING_BITS)
2146                         return false;
2147         }
2148         return true;
2149 }
2150
2151 bool
2152 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2153 {
2154         struct hns3_hw *hw = &hns->hw;
2155         enum hns3_reset_level reset;
2156
2157         hns3vf_check_event_cause(hns, NULL);
2158         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2159         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2160                 hns3_warn(hw, "High level reset %d is pending", reset);
2161                 return true;
2162         }
2163         return false;
2164 }
2165
2166 static int
2167 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2168 {
2169         struct hns3_hw *hw = &hns->hw;
2170         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2171         struct timeval tv;
2172
2173         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2174                 /*
2175                  * After vf reset is ready, the PF may not have completed
2176                  * the reset processing. The vf sending mbox to PF may fail
2177                  * during the pf reset, so it is better to add extra delay.
2178                  */
2179                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2180                     hw->reset.level == HNS3_FLR_RESET)
2181                         return 0;
2182                 /* Reset retry process, no need to add extra delay. */
2183                 if (hw->reset.attempts)
2184                         return 0;
2185                 if (wait_data->check_completion == NULL)
2186                         return 0;
2187
2188                 wait_data->check_completion = NULL;
2189                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2190                 wait_data->count = 1;
2191                 wait_data->result = HNS3_WAIT_REQUEST;
2192                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2193                                   wait_data);
2194                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2195                 return -EAGAIN;
2196         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2197                 gettimeofday(&tv, NULL);
2198                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2199                           tv.tv_sec, tv.tv_usec);
2200                 return -ETIME;
2201         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2202                 return -EAGAIN;
2203
2204         wait_data->hns = hns;
2205         wait_data->check_completion = is_vf_reset_done;
2206         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2207                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2208         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2209         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2210         wait_data->result = HNS3_WAIT_REQUEST;
2211         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2212         return -EAGAIN;
2213 }
2214
2215 static int
2216 hns3vf_prepare_reset(struct hns3_adapter *hns)
2217 {
2218         struct hns3_hw *hw = &hns->hw;
2219         int ret = 0;
2220
2221         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2222                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2223                                         0, true, NULL, 0);
2224         }
2225         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2226
2227         return ret;
2228 }
2229
2230 static int
2231 hns3vf_stop_service(struct hns3_adapter *hns)
2232 {
2233         struct hns3_hw *hw = &hns->hw;
2234         struct rte_eth_dev *eth_dev;
2235
2236         eth_dev = &rte_eth_devices[hw->data->port_id];
2237         if (hw->adapter_state == HNS3_NIC_STARTED)
2238                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2239         hw->mac.link_status = ETH_LINK_DOWN;
2240
2241         hns3_set_rxtx_function(eth_dev);
2242         rte_wmb();
2243         /* Disable datapath on secondary process. */
2244         hns3_mp_req_stop_rxtx(eth_dev);
2245         rte_delay_ms(hw->tqps_num);
2246
2247         rte_spinlock_lock(&hw->lock);
2248         if (hw->adapter_state == HNS3_NIC_STARTED ||
2249             hw->adapter_state == HNS3_NIC_STOPPING) {
2250                 hns3vf_do_stop(hns);
2251                 hw->reset.mbuf_deferred_free = true;
2252         } else
2253                 hw->reset.mbuf_deferred_free = false;
2254
2255         /*
2256          * It is cumbersome for hardware to pick-and-choose entries for deletion
2257          * from table space. Hence, for function reset software intervention is
2258          * required to delete the entries.
2259          */
2260         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2261                 hns3vf_configure_all_mc_mac_addr(hns, true);
2262         rte_spinlock_unlock(&hw->lock);
2263
2264         return 0;
2265 }
2266
2267 static int
2268 hns3vf_start_service(struct hns3_adapter *hns)
2269 {
2270         struct hns3_hw *hw = &hns->hw;
2271         struct rte_eth_dev *eth_dev;
2272
2273         eth_dev = &rte_eth_devices[hw->data->port_id];
2274         hns3_set_rxtx_function(eth_dev);
2275         hns3_mp_req_start_rxtx(eth_dev);
2276         if (hw->adapter_state == HNS3_NIC_STARTED) {
2277                 hns3vf_service_handler(eth_dev);
2278
2279                 /* Enable interrupt of all rx queues before enabling queues */
2280                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2281                 /*
2282                  * When finished the initialization, enable queues to receive
2283                  * and transmit packets.
2284                  */
2285                 hns3_enable_all_queues(hw, true);
2286         }
2287
2288         return 0;
2289 }
2290
2291 static int
2292 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2293 {
2294         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2295         struct rte_ether_addr *hw_mac;
2296         int ret;
2297
2298         /*
2299          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2300          * on the host by "ip link set ..." command. If the hns3 PF kernel
2301          * ethdev driver sets the MAC address for VF device after the
2302          * initialization of the related VF device, the PF driver will notify
2303          * VF driver to reset VF device to make the new MAC address effective
2304          * immediately. The hns3 VF PMD driver should check whether the MAC
2305          * address has been changed by the PF kernel ethdev driver, if changed
2306          * VF driver should configure hardware using the new MAC address in the
2307          * recovering hardware configuration stage of the reset process.
2308          */
2309         ret = hns3vf_get_host_mac_addr(hw);
2310         if (ret)
2311                 return ret;
2312
2313         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2314         ret = rte_is_zero_ether_addr(hw_mac);
2315         if (ret) {
2316                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2317         } else {
2318                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2319                 if (!ret) {
2320                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2321                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2322                                               &hw->data->mac_addrs[0]);
2323                         hns3_warn(hw, "Default MAC address has been changed to:"
2324                                   " %s by the host PF kernel ethdev driver",
2325                                   mac_str);
2326                 }
2327         }
2328
2329         return 0;
2330 }
2331
2332 static int
2333 hns3vf_restore_conf(struct hns3_adapter *hns)
2334 {
2335         struct hns3_hw *hw = &hns->hw;
2336         int ret;
2337
2338         ret = hns3vf_check_default_mac_change(hw);
2339         if (ret)
2340                 return ret;
2341
2342         ret = hns3vf_configure_mac_addr(hns, false);
2343         if (ret)
2344                 return ret;
2345
2346         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2347         if (ret)
2348                 goto err_mc_mac;
2349
2350         ret = hns3vf_restore_promisc(hns);
2351         if (ret)
2352                 goto err_vlan_table;
2353
2354         ret = hns3vf_restore_vlan_conf(hns);
2355         if (ret)
2356                 goto err_vlan_table;
2357
2358         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2359         if (ret)
2360                 goto err_vlan_table;
2361
2362         ret = hns3vf_restore_rx_interrupt(hw);
2363         if (ret)
2364                 goto err_vlan_table;
2365
2366         ret = hns3_restore_gro_conf(hw);
2367         if (ret)
2368                 goto err_vlan_table;
2369
2370         if (hw->adapter_state == HNS3_NIC_STARTED) {
2371                 ret = hns3vf_do_start(hns, false);
2372                 if (ret)
2373                         goto err_vlan_table;
2374                 hns3_info(hw, "hns3vf dev restart successful!");
2375         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2376                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2377         return 0;
2378
2379 err_vlan_table:
2380         hns3vf_configure_all_mc_mac_addr(hns, true);
2381 err_mc_mac:
2382         hns3vf_configure_mac_addr(hns, true);
2383         return ret;
2384 }
2385
2386 static enum hns3_reset_level
2387 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2388 {
2389         enum hns3_reset_level reset_level;
2390
2391         /* return the highest priority reset level amongst all */
2392         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2393                 reset_level = HNS3_VF_RESET;
2394         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2395                 reset_level = HNS3_VF_FULL_RESET;
2396         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2397                 reset_level = HNS3_VF_PF_FUNC_RESET;
2398         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2399                 reset_level = HNS3_VF_FUNC_RESET;
2400         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2401                 reset_level = HNS3_FLR_RESET;
2402         else
2403                 reset_level = HNS3_NONE_RESET;
2404
2405         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2406                 return HNS3_NONE_RESET;
2407
2408         return reset_level;
2409 }
2410
2411 static void
2412 hns3vf_reset_service(void *param)
2413 {
2414         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2415         struct hns3_hw *hw = &hns->hw;
2416         enum hns3_reset_level reset_level;
2417         struct timeval tv_delta;
2418         struct timeval tv_start;
2419         struct timeval tv;
2420         uint64_t msec;
2421
2422         /*
2423          * The interrupt is not triggered within the delay time.
2424          * The interrupt may have been lost. It is necessary to handle
2425          * the interrupt to recover from the error.
2426          */
2427         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2428                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2429                 hns3_err(hw, "Handling interrupts in delayed tasks");
2430                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2431                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2432                 if (reset_level == HNS3_NONE_RESET) {
2433                         hns3_err(hw, "No reset level is set, try global reset");
2434                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2435                 }
2436         }
2437         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2438
2439         /*
2440          * Hardware reset has been notified, we now have to poll & check if
2441          * hardware has actually completed the reset sequence.
2442          */
2443         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2444         if (reset_level != HNS3_NONE_RESET) {
2445                 gettimeofday(&tv_start, NULL);
2446                 hns3_reset_process(hns, reset_level);
2447                 gettimeofday(&tv, NULL);
2448                 timersub(&tv, &tv_start, &tv_delta);
2449                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2450                        tv_delta.tv_usec / USEC_PER_MSEC;
2451                 if (msec > HNS3_RESET_PROCESS_MS)
2452                         hns3_err(hw, "%d handle long time delta %" PRIx64
2453                                  " ms time=%ld.%.6ld",
2454                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2455         }
2456 }
2457
2458 static int
2459 hns3vf_reinit_dev(struct hns3_adapter *hns)
2460 {
2461         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2462         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2463         struct hns3_hw *hw = &hns->hw;
2464         int ret;
2465
2466         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2467                 rte_intr_disable(&pci_dev->intr_handle);
2468                 hns3vf_set_bus_master(pci_dev, true);
2469         }
2470
2471         /* Firmware command initialize */
2472         ret = hns3_cmd_init(hw);
2473         if (ret) {
2474                 hns3_err(hw, "Failed to init cmd: %d", ret);
2475                 return ret;
2476         }
2477
2478         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2479                 /*
2480                  * UIO enables msix by writing the pcie configuration space
2481                  * vfio_pci enables msix in rte_intr_enable.
2482                  */
2483                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2484                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2485                         if (hns3vf_enable_msix(pci_dev, true))
2486                                 hns3_err(hw, "Failed to enable msix");
2487                 }
2488
2489                 rte_intr_enable(&pci_dev->intr_handle);
2490         }
2491
2492         ret = hns3_reset_all_queues(hns);
2493         if (ret) {
2494                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2495                 return ret;
2496         }
2497
2498         ret = hns3vf_init_hardware(hns);
2499         if (ret) {
2500                 hns3_err(hw, "Failed to init hardware: %d", ret);
2501                 return ret;
2502         }
2503
2504         return 0;
2505 }
2506
2507 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2508         .dev_start          = hns3vf_dev_start,
2509         .dev_stop           = hns3vf_dev_stop,
2510         .dev_close          = hns3vf_dev_close,
2511         .mtu_set            = hns3vf_dev_mtu_set,
2512         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2513         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2514         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2515         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2516         .stats_get          = hns3_stats_get,
2517         .stats_reset        = hns3_stats_reset,
2518         .xstats_get         = hns3_dev_xstats_get,
2519         .xstats_get_names   = hns3_dev_xstats_get_names,
2520         .xstats_reset       = hns3_dev_xstats_reset,
2521         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2522         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2523         .dev_infos_get      = hns3vf_dev_infos_get,
2524         .fw_version_get     = hns3vf_fw_version_get,
2525         .rx_queue_setup     = hns3_rx_queue_setup,
2526         .tx_queue_setup     = hns3_tx_queue_setup,
2527         .rx_queue_release   = hns3_dev_rx_queue_release,
2528         .tx_queue_release   = hns3_dev_tx_queue_release,
2529         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2530         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2531         .rxq_info_get       = hns3_rxq_info_get,
2532         .txq_info_get       = hns3_txq_info_get,
2533         .dev_configure      = hns3vf_dev_configure,
2534         .mac_addr_add       = hns3vf_add_mac_addr,
2535         .mac_addr_remove    = hns3vf_remove_mac_addr,
2536         .mac_addr_set       = hns3vf_set_default_mac_addr,
2537         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2538         .link_update        = hns3vf_dev_link_update,
2539         .rss_hash_update    = hns3_dev_rss_hash_update,
2540         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2541         .reta_update        = hns3_dev_rss_reta_update,
2542         .reta_query         = hns3_dev_rss_reta_query,
2543         .filter_ctrl        = hns3_dev_filter_ctrl,
2544         .vlan_filter_set    = hns3vf_vlan_filter_set,
2545         .vlan_offload_set   = hns3vf_vlan_offload_set,
2546         .get_reg            = hns3_get_regs,
2547         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2548 };
2549
2550 static const struct hns3_reset_ops hns3vf_reset_ops = {
2551         .reset_service       = hns3vf_reset_service,
2552         .stop_service        = hns3vf_stop_service,
2553         .prepare_reset       = hns3vf_prepare_reset,
2554         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2555         .reinit_dev          = hns3vf_reinit_dev,
2556         .restore_conf        = hns3vf_restore_conf,
2557         .start_service       = hns3vf_start_service,
2558 };
2559
2560 static int
2561 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2562 {
2563         struct hns3_adapter *hns = eth_dev->data->dev_private;
2564         struct hns3_hw *hw = &hns->hw;
2565         int ret;
2566
2567         PMD_INIT_FUNC_TRACE();
2568
2569         eth_dev->process_private = (struct hns3_process_private *)
2570             rte_zmalloc_socket("hns3_filter_list",
2571                                sizeof(struct hns3_process_private),
2572                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2573         if (eth_dev->process_private == NULL) {
2574                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2575                 return -ENOMEM;
2576         }
2577
2578         /* initialize flow filter lists */
2579         hns3_filterlist_init(eth_dev);
2580
2581         hns3_set_rxtx_function(eth_dev);
2582         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2583         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2584                 ret = hns3_mp_init_secondary();
2585                 if (ret) {
2586                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2587                                           "process, ret = %d", ret);
2588                         goto err_mp_init_secondary;
2589                 }
2590
2591                 hw->secondary_cnt++;
2592                 return 0;
2593         }
2594
2595         ret = hns3_mp_init_primary();
2596         if (ret) {
2597                 PMD_INIT_LOG(ERR,
2598                              "Failed to init for primary process, ret = %d",
2599                              ret);
2600                 goto err_mp_init_primary;
2601         }
2602
2603         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2604         hns->is_vf = true;
2605         hw->data = eth_dev->data;
2606
2607         ret = hns3_reset_init(hw);
2608         if (ret)
2609                 goto err_init_reset;
2610         hw->reset.ops = &hns3vf_reset_ops;
2611
2612         ret = hns3vf_init_vf(eth_dev);
2613         if (ret) {
2614                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2615                 goto err_init_vf;
2616         }
2617
2618         /* Allocate memory for storing MAC addresses */
2619         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2620                                                sizeof(struct rte_ether_addr) *
2621                                                HNS3_VF_UC_MACADDR_NUM, 0);
2622         if (eth_dev->data->mac_addrs == NULL) {
2623                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2624                              "to store MAC addresses",
2625                              sizeof(struct rte_ether_addr) *
2626                              HNS3_VF_UC_MACADDR_NUM);
2627                 ret = -ENOMEM;
2628                 goto err_rte_zmalloc;
2629         }
2630
2631         /*
2632          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2633          * on the host by "ip link set ..." command. To avoid some incorrect
2634          * scenes, for example, hns3 VF PMD driver fails to receive and send
2635          * packets after user configure the MAC address by using the
2636          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2637          * address strategy as the hns3 kernel ethdev driver in the
2638          * initialization. If user configure a MAC address by the ip command
2639          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2640          * start with a random MAC address in the initialization.
2641          */
2642         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2643                 rte_eth_random_addr(hw->mac.mac_addr);
2644         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2645                             &eth_dev->data->mac_addrs[0]);
2646
2647         hw->adapter_state = HNS3_NIC_INITIALIZED;
2648         /*
2649          * Pass the information to the rte_eth_dev_close() that it should also
2650          * release the private port resources.
2651          */
2652         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2653
2654         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2655                 hns3_err(hw, "Reschedule reset service after dev_init");
2656                 hns3_schedule_reset(hns);
2657         } else {
2658                 /* IMP will wait ready flag before reset */
2659                 hns3_notify_reset_ready(hw, false);
2660         }
2661         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2662                           eth_dev);
2663         return 0;
2664
2665 err_rte_zmalloc:
2666         hns3vf_uninit_vf(eth_dev);
2667
2668 err_init_vf:
2669         rte_free(hw->reset.wait_data);
2670
2671 err_init_reset:
2672         hns3_mp_uninit_primary();
2673
2674 err_mp_init_primary:
2675 err_mp_init_secondary:
2676         eth_dev->dev_ops = NULL;
2677         eth_dev->rx_pkt_burst = NULL;
2678         eth_dev->tx_pkt_burst = NULL;
2679         eth_dev->tx_pkt_prepare = NULL;
2680         rte_free(eth_dev->process_private);
2681         eth_dev->process_private = NULL;
2682
2683         return ret;
2684 }
2685
2686 static int
2687 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2688 {
2689         struct hns3_adapter *hns = eth_dev->data->dev_private;
2690         struct hns3_hw *hw = &hns->hw;
2691
2692         PMD_INIT_FUNC_TRACE();
2693
2694         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2695                 return -EPERM;
2696
2697         eth_dev->dev_ops = NULL;
2698         eth_dev->rx_pkt_burst = NULL;
2699         eth_dev->tx_pkt_burst = NULL;
2700         eth_dev->tx_pkt_prepare = NULL;
2701
2702         if (hw->adapter_state < HNS3_NIC_CLOSING)
2703                 hns3vf_dev_close(eth_dev);
2704
2705         hw->adapter_state = HNS3_NIC_REMOVED;
2706         return 0;
2707 }
2708
2709 static int
2710 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2711                      struct rte_pci_device *pci_dev)
2712 {
2713         return rte_eth_dev_pci_generic_probe(pci_dev,
2714                                              sizeof(struct hns3_adapter),
2715                                              hns3vf_dev_init);
2716 }
2717
2718 static int
2719 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2720 {
2721         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2722 }
2723
2724 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2725         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2726         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2727         { .vendor_id = 0, /* sentinel */ },
2728 };
2729
2730 static struct rte_pci_driver rte_hns3vf_pmd = {
2731         .id_table = pci_id_hns3vf_map,
2732         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2733         .probe = eth_hns3vf_pci_probe,
2734         .remove = eth_hns3vf_pci_remove,
2735 };
2736
2737 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2738 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2739 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");